ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness

Add a dsb after the isb to ensure that the previous writes to the
CP15 registers take effect before we enable the MMU.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index dec72ee9f7af68d0d03a0b54496f356aa28751f3..a773f4e2869c1f93a0efdfce96d127a97223081b 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume)
        mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
        mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
        isb
+       dsb
        mov     r0, r9                  @ control register
        mov     r2, r7, lsr #14         @ get TTB0 base
        mov     r2, r2, lsl #14