Add a bool in ath9k_platform_data to pass AHB clock speed information.
Driver needs this to configure PLL on some SOCs.
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
/* Enterprise mode cap */
u32 ent_mode;
+
+ bool is_clk_25mhz;
};
struct ath_bus_ops {
sc->sc_ah->gpio_mask = pdata->gpio_mask;
sc->sc_ah->gpio_val = pdata->gpio_val;
sc->sc_ah->led_pin = pdata->led_pin;
+ ah->is_clk_25mhz = pdata->is_clk_25mhz;
}
common = ath9k_hw_common(ah);
int led_pin;
u32 gpio_mask;
u32 gpio_val;
+
+ bool is_clk_25mhz;
};
#endif /* _LINUX_ATH9K_PLATFORM_H */