arm: socfpga: Define NAND reset bit

Define the NAND reset bit and fix the ordering of the macros.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index e50fbd86e6e6eaab795b90cd4ea5e263c320a760..2f070f291cba56d5c8528d9ca677102d3ddc7fd5 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -65,12 +65,13 @@ struct socfpga_reset_manager {
  */
 #define RSTMGR_EMAC0           RSTMGR_DEFINE(1, 0)
 #define RSTMGR_EMAC1           RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NAND            RSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI            RSTMGR_DEFINE(1, 5)
 #define RSTMGR_L4WD0           RSTMGR_DEFINE(1, 6)
 #define RSTMGR_OSC1TIMER0      RSTMGR_DEFINE(1, 8)
 #define RSTMGR_UART0           RSTMGR_DEFINE(1, 16)
 #define RSTMGR_SPIM0           RSTMGR_DEFINE(1, 18)
 #define RSTMGR_SPIM1           RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI            RSTMGR_DEFINE(1, 5)
 #define RSTMGR_SDMMC           RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA             RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR             RSTMGR_DEFINE(1, 29)