drm/i915: only set the HDMI port on the DIP once

Not once for each InfoFrame. Now we have a function that allows us to
do this.

[danvet: Paulo clarified on irc that a later bugfix patch needs this
cleanup.]

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2f2adc4e511c355e7f1fcfbda20f8bd1630dc873..1df1ec764a0185ecb637bf949882ecb5af5364f4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -121,18 +121,9 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
        uint32_t *data = (uint32_t *)frame;
        struct drm_device *dev = encoder->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
        u32 val = I915_READ(VIDEO_DIP_CTL);
        unsigned i, len = DIP_HEADER_SIZE + frame->len;
 
-       val &= ~VIDEO_DIP_PORT_MASK;
-       if (intel_hdmi->sdvox_reg == SDVOB)
-               val |= VIDEO_DIP_PORT_B;
-       else if (intel_hdmi->sdvox_reg == SDVOC)
-               val |= VIDEO_DIP_PORT_C;
-       else
-               return;
-
        val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
        val |= g4x_infoframe_index(frame);
 
@@ -160,26 +151,10 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
        struct drm_device *dev = encoder->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
-       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
        int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
        unsigned i, len = DIP_HEADER_SIZE + frame->len;
        u32 val = I915_READ(reg);
 
-       val &= ~VIDEO_DIP_PORT_MASK;
-       switch (intel_hdmi->sdvox_reg) {
-       case HDMIB:
-               val |= VIDEO_DIP_PORT_B;
-               break;
-       case HDMIC:
-               val |= VIDEO_DIP_PORT_C;
-               break;
-       case HDMID:
-               val |= VIDEO_DIP_PORT_D;
-               break;
-       default:
-               return;
-       }
-
        intel_wait_for_vblank(dev, intel_crtc->pipe);
 
        val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
@@ -369,6 +344,20 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
                return;
        }
 
+       val &= ~VIDEO_DIP_PORT_MASK;
+       switch (intel_hdmi->sdvox_reg) {
+       case SDVOB:
+               val |= VIDEO_DIP_PORT_B;
+               break;
+       case SDVOC:
+               val |= VIDEO_DIP_PORT_C;
+               break;
+       default:
+               return;
+       }
+
+       I915_WRITE(reg, val);
+
        intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
        intel_hdmi_set_spd_infoframe(encoder);
 }
@@ -393,6 +382,23 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
                return;
        }
 
+       val &= ~VIDEO_DIP_PORT_MASK;
+       switch (intel_hdmi->sdvox_reg) {
+       case HDMIB:
+               val |= VIDEO_DIP_PORT_B;
+               break;
+       case HDMIC:
+               val |= VIDEO_DIP_PORT_C;
+               break;
+       case HDMID:
+               val |= VIDEO_DIP_PORT_D;
+               break;
+       default:
+               return;
+       }
+
+       I915_WRITE(reg, val);
+
        intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
        intel_hdmi_set_spd_infoframe(encoder);
 }