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drm/i915: Fix bit name in PP_STATUS register
author
Lucas De Marchi
<lucas.demarchi@intel.com>
Sat, 2 Mar 2019 01:14:04 +0000
(17:14 -0800)
committer
Lucas De Marchi
<lucas.demarchi@intel.com>
Mon, 4 Mar 2019 23:20:05 +0000
(15:20 -0800)
According to the spec PP_SEQUENCE_STATE_ON_S1_1 is the correct name, so
just rename it.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link:
https://patchwork.freedesktop.org/patch/msgid/20190302011405.6405-1-lucas.demarchi@intel.com
drivers/gpu/drm/i915/i915_reg.h
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diff --git
a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index c9b482bc643316fe2abda1dc05bc832d6f0fa13a..c9b868347481ddf93e258132c62176e625712a90 100644
(file)
--- a/
drivers/gpu/drm/i915/i915_reg.h
+++ b/
drivers/gpu/drm/i915/i915_reg.h
@@
-4723,7
+4723,7
@@
enum {
#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
-#define PP_SEQUENCE_STATE_ON_S1_
0
(0x9 << 0)
+#define PP_SEQUENCE_STATE_ON_S1_
1
(0x9 << 0)
#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
#define PP_SEQUENCE_STATE_RESET (0xf << 0)