oprofile/x86: implement lsfr pseudo-random number generator for IBS

This patch implements a linear feedback shift register (LFSR) for
pseudo-random number generation for IBS.

For IBS measurements it would be good to minimize memory traffic in
the interrupt handler since every access pollutes the data
caches. Computing a maximal period LFSR just needs shifts and ORs.

The LFSR method is good enough to randomize the ops at low
overhead. 16 pseudo-random bits are enough for the implementation and
it doesn't matter that the pattern repeats with a fairly short
cycle. It only needs to break up (hard) periodic sampling behavior.

The logic was designed by Paul Drongowski.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Robert Richter <robert.richter@amd.com>

diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 6557683c190eef0016cfc6b8223a4d2c59ec5f42..97c84ebe3f244c43cfaea5f9b12863463cb72f89 100644 (file)
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -218,6 +218,29 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
        }
 }
 
+/*
+ * 16-bit Linear Feedback Shift Register (LFSR)
+ *
+ *                       16   14   13    11
+ * Feedback polynomial = X  + X  + X  +  X  + 1
+ */
+static unsigned int lfsr_random(void)
+{
+       static unsigned int lfsr_value = 0xF00D;
+       unsigned int bit;
+
+       /* Compute next bit to shift in */
+       bit = ((lfsr_value >> 0) ^
+              (lfsr_value >> 2) ^
+              (lfsr_value >> 3) ^
+              (lfsr_value >> 5)) & 0x0001;
+
+       /* Advance to next register value */
+       lfsr_value = (lfsr_value >> 1) | (bit << 15);
+
+       return lfsr_value;
+}
+
 static inline void
 op_amd_handle_ibs(struct pt_regs * const regs,
                  struct op_msrs const * const msrs)