CONFIG_ATH79_MACH_ALL0258N=y
CONFIG_ATH79_MACH_AP113=y
CONFIG_ATH79_MACH_AP121=y
+CONFIG_ATH79_MACH_AP136=y
CONFIG_ATH79_MACH_AP81=y
CONFIG_ATH79_MACH_AP83=y
CONFIG_ATH79_MACH_AP96=y
CONFIG_SOC_AR913X=y
CONFIG_SOC_AR933X=y
CONFIG_SOC_AR934X=y
+CONFIG_SOC_QCA955X=y
CONFIG_SPI=y
CONFIG_SPI_AP83=y
CONFIG_SPI_ATH79=y
--- /dev/null
+From a034da3e4d4960266a94d15c811d5f4529fdff44 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:52:23 +0200
+Subject: [PATCH 27/34] MIPS: ath79: add support for the Qualcomm Atheros AP136 board
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/Kconfig | 12 +++
+ arch/mips/ath79/Makefile | 1 +
+ arch/mips/ath79/mach-ap136.c | 155 ++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ath79/machtypes.h | 1 +
+ 4 files changed, 169 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/ath79/mach-ap136.c
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -14,6 +14,18 @@ config ATH79_MACH_AP121
+ Say 'Y' here if you want your kernel to support the
+ Atheros AP121 reference board.
+
++config ATH79_MACH_AP136
++ bool "Atheros AP136 reference board"
++ select SOC_QCA955X
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_SPI
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++ help
++ Say 'Y' here if you want your kernel to support the
++ Atheros AP136 reference board.
++
+ config ATH79_MACH_AP81
+ bool "Atheros AP81 reference board"
+ select SOC_AR913X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma
+ # Machines
+ #
+ obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
++obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
+ obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
+ obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
+ obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
+--- /dev/null
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -0,0 +1,155 @@
++/*
++ * Qualcomm Atheros AP136 reference board support
++ *
++ * Copyright (c) 2012 Qualcomm Atheros
++ * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ *
++ */
++
++#include <linux/pci.h>
++#include <linux/ath9k_platform.h>
++
++#include "machtypes.h"
++#include "dev-gpio-buttons.h"
++#include "dev-leds-gpio.h"
++#include "dev-spi.h"
++#include "dev-usb.h"
++#include "dev-wmac.h"
++#include "pci.h"
++
++#define AP136_GPIO_LED_STATUS_RED 14
++#define AP136_GPIO_LED_STATUS_GREEN 19
++#define AP136_GPIO_LED_USB 4
++#define AP136_GPIO_LED_WLAN_2G 13
++#define AP136_GPIO_LED_WLAN_5G 12
++#define AP136_GPIO_LED_WPS_RED 15
++#define AP136_GPIO_LED_WPS_GREEN 20
++
++#define AP136_GPIO_BTN_WPS 16
++#define AP136_GPIO_BTN_RFKILL 21
++
++#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
++#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
++
++#define AP136_WMAC_CALDATA_OFFSET 0x1000
++#define AP136_PCIE_CALDATA_OFFSET 0x5000
++
++static struct gpio_led ap136_leds_gpio[] __initdata = {
++ {
++ .name = "ap136:green:status",
++ .gpio = AP136_GPIO_LED_STATUS_GREEN,
++ .active_low = 1,
++ },
++ {
++ .name = "ap136:red:status",
++ .gpio = AP136_GPIO_LED_STATUS_RED,
++ .active_low = 1,
++ },
++ {
++ .name = "ap136:green:wps",
++ .gpio = AP136_GPIO_LED_WPS_GREEN,
++ .active_low = 1,
++ },
++ {
++ .name = "ap136:red:wps",
++ .gpio = AP136_GPIO_LED_WPS_RED,
++ .active_low = 1,
++ },
++ {
++ .name = "ap136:red:wlan-2g",
++ .gpio = AP136_GPIO_LED_WLAN_2G,
++ .active_low = 1,
++ },
++ {
++ .name = "ap136:red:usb",
++ .gpio = AP136_GPIO_LED_USB,
++ .active_low = 1,
++ }
++};
++
++static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
++ {
++ .desc = "WPS button",
++ .type = EV_KEY,
++ .code = KEY_WPS_BUTTON,
++ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = AP136_GPIO_BTN_WPS,
++ .active_low = 1,
++ },
++ {
++ .desc = "RFKILL button",
++ .type = EV_KEY,
++ .code = KEY_RFKILL,
++ .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = AP136_GPIO_BTN_RFKILL,
++ .active_low = 1,
++ },
++};
++
++static struct spi_board_info ap136_spi_info[] = {
++ {
++ .bus_num = 0,
++ .chip_select = 0,
++ .max_speed_hz = 25000000,
++ .modalias = "mx25l6405d",
++ }
++};
++
++static struct ath79_spi_platform_data ap136_spi_data = {
++ .bus_num = 0,
++ .num_chipselect = 1,
++};
++
++#ifdef CONFIG_PCI
++static struct ath9k_platform_data ap136_ath9k_data;
++
++static int ap136_pci_plat_dev_init(struct pci_dev *dev)
++{
++ if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
++ dev->dev.platform_data = &ap136_ath9k_data;
++
++ return 0;
++}
++
++static void __init ap136_pci_init(u8 *eeprom)
++{
++ memcpy(ap136_ath9k_data.eeprom_data, eeprom,
++ sizeof(ap136_ath9k_data.eeprom_data));
++
++ ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
++ ath79_register_pci();
++}
++#else
++static inline void ap136_pci_init(void) {}
++#endif /* CONFIG_PCI */
++
++static void __init ap136_setup(void)
++{
++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
++ ap136_leds_gpio);
++ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
++ ARRAY_SIZE(ap136_gpio_keys),
++ ap136_gpio_keys);
++ ath79_register_spi(&ap136_spi_data, ap136_spi_info,
++ ARRAY_SIZE(ap136_spi_info));
++ ath79_register_usb();
++ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
++ ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
++}
++
++MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
++ ap136_setup);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -17,6 +17,7 @@
+ enum ath79_mach_type {
+ ATH79_MACH_GENERIC = 0,
+ ATH79_MACH_AP121, /* Atheros AP121 reference board */
++ ATH79_MACH_AP136, /* Atheros AP136 reference board */
+ ATH79_MACH_AP81, /* Atheros AP81 reference board */
+ ATH79_MACH_DB120, /* Atheros DB120 reference board */
+ ATH79_MACH_PB44, /* Atheros PB44 reference board */
-From 5e5ffd34e38fbbfa0a78833f35aa3c4d5d77e122 Mon Sep 17 00:00:00 2001
+From cbb3ade4765bc715b5c2eae4a7b6eaf3ff7ad958 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Wed, 11 Jan 2012 20:06:35 +0100
-Subject: [PATCH 41/47] spi/ath79: add delay between SCK changes
+Subject: [PATCH 28/34] spi/ath79: add delay between SCK changes
The driver uses the "as fast as it can" approach
to drive the SCK signal. However this does not
-From 52fa804e11c1722ec56de2e3888a9f8dfb96404b Mon Sep 17 00:00:00 2001
+From bcb0fdebc08f828b54d0a2eb74a9d1378701a8e0 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Wed, 11 Jan 2012 20:33:41 +0100
-Subject: [PATCH 42/47] spi/ath79: add missing HIGH->LOW SCK transition
+Subject: [PATCH 29/34] spi/ath79: add missing HIGH->LOW SCK transition
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
---
-From 3ba7fd81798169e8d40bc7e4800c6a0e691c40b7 Mon Sep 17 00:00:00 2001
+From 06752f9b169493cd1323f8337c147ad2dd31025c Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 9 Jan 2012 15:03:28 +0100
-Subject: [PATCH 43/47] spi/ath79: remove superfluous chip select code
+Subject: [PATCH 30/34] spi/ath79: remove superfluous chip select code
The spi_bitbang driver calls the chipselect function
of the driver from spi_bitbang_setup in order to
-From 07f515fc0f69d18110cb2369e0b5d0fb4bdd7dfa Mon Sep 17 00:00:00 2001
+From 6bd876a46b977643f27d2cc63f49e1bc84b78134 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 9 Jan 2012 15:04:21 +0100
-Subject: [PATCH 44/47] spi/ath79: use gpio_request_one
+Subject: [PATCH 31/34] spi/ath79: use gpio_request_one
Use gpio_request_one() instead of multiple gpiolib calls.
-From 47fdda225880ab0aaa8a75f61991a72fade591ab Mon Sep 17 00:00:00 2001
+From e63ceaa0c4f7be0498cd452981073d3ce8e7d1f5 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 9 Jan 2012 15:00:46 +0100
-Subject: [PATCH 45/47] spi/ath79: avoid multiple initialization of the SPI controller
+Subject: [PATCH 32/34] spi/ath79: avoid multiple initialization of the SPI controller
Currently we are initializing the SPI controller in
the chip select line function, and that function is
-From 8f30eb1354f54684d1d09599b2466f1a0e69d9c3 Mon Sep 17 00:00:00 2001
+From dab305def68a9ea28c1c0ca2fc20bba645944914 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Wed, 11 Jan 2012 22:19:32 +0100
-Subject: [PATCH 46/47] spi/ath79: add shutdown handler
+Subject: [PATCH 33/34] spi/ath79: add shutdown handler
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
---
-From 16535fe56591ff85acd6776f53ff515799b037ba Mon Sep 17 00:00:00 2001
+From 7008284716403237f6bc7d7590b3ed073555bd56 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Wed, 11 Jan 2012 22:25:11 +0100
-Subject: [PATCH 47/47] spi/ath79: make chipselect logic more flexible
+Subject: [PATCH 34/34] spi/ath79: make chipselect logic more flexible
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
---
arch/mips/ath79/mach-ap121.c | 6 ++
+ arch/mips/ath79/mach-ap136.c | 6 ++
arch/mips/ath79/mach-ap81.c | 6 ++
arch/mips/ath79/mach-db120.c | 6 ++
arch/mips/ath79/mach-pb44.c | 6 ++
arch/mips/ath79/mach-ubnt-xm.c | 6 ++
.../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++-
- drivers/spi/spi-ath79.c | 70 +++++++++++++-------
- 7 files changed, 82 insertions(+), 26 deletions(-)
+ drivers/spi/spi-ath79.c | 67 +++++++++++++-------
+ 8 files changed, 88 insertions(+), 23 deletions(-)
--- a/arch/mips/ath79/mach-ap121.c
+++ b/arch/mips/ath79/mach-ap121.c
}
};
+--- a/arch/mips/ath79/mach-ap136.c
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -98,12 +98,18 @@ static struct gpio_keys_button ap136_gpi
+ },
+ };
+
++static struct ath79_spi_controller_data ap136_spi0_data = {
++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++ .cs_line = 0,
++};
++
+ static struct spi_board_info ap136_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "mx25l6405d",
++ .controller_data = &ap136_spi0_data,
+ }
+ };
+
--- a/arch/mips/ath79/mach-ap81.c
+++ b/arch/mips/ath79/mach-ap81.c
@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -94,6 +94,20 @@ config SOC_QCA955X
+@@ -106,6 +106,20 @@ config SOC_QCA955X
select PCI_AR724X if PCI
def_bool n
config PCI_AR724X
def_bool n
-@@ -113,4 +127,10 @@ config ATH79_DEV_WMAC
+@@ -125,4 +139,10 @@ config ATH79_DEV_WMAC
depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
def_bool n
ATH79_MACH_GENERIC = 0,
ATH79_MACH_AP121, /* Atheros AP121 reference board */
+ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
+ ATH79_MACH_AP136, /* Atheros AP136 reference board */
ATH79_MACH_AP81, /* Atheros AP81 reference board */
ATH79_MACH_DB120, /* Atheros DB120 reference board */
- ATH79_MACH_PB44, /* Atheros PB44 reference board */
MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -18,9 +18,10 @@ config ATH79_MACH_AP121
+@@ -30,9 +30,10 @@ config ATH79_MACH_AP136
config ATH79_MACH_AP81
bool "Atheros AP81 reference board"
select SOC_AR913X
MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -31,9 +31,11 @@ config ATH79_MACH_AP81
+@@ -43,9 +43,11 @@ config ATH79_MACH_AP81
config ATH79_MACH_DB120
bool "Atheros DB120 reference board"
select SOC_AR934X
MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -45,6 +45,7 @@ config ATH79_MACH_DB120
+@@ -57,6 +57,7 @@ config ATH79_MACH_DB120
config ATH79_MACH_PB44
bool "Atheros PB44 reference board"
select SOC_AR71XX
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -57,9 +57,10 @@ config ATH79_MACH_PB44
+@@ -69,9 +69,10 @@ config ATH79_MACH_PB44
config ATH79_MACH_UBNT_XM
bool "Ubiquiti Networks XM (rev 1.0) board"
select SOC_AR724X
+ ubnt_unifi_setup);
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -58,9 +58,11 @@ config ATH79_MACH_UBNT_XM
+@@ -70,9 +70,11 @@ config ATH79_MACH_UBNT_XM
bool "Ubiquiti Networks XM (rev 1.0) board"
select SOC_AR724X
select ATH79_DEV_AP9X_PCI if PCI
Ubiquiti Networks XM (rev 1.0) board.
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
-@@ -21,6 +21,11 @@ enum ath79_mach_type {
+@@ -22,6 +22,11 @@ enum ath79_mach_type {
ATH79_MACH_AP81, /* Atheros AP81 reference board */
ATH79_MACH_DB120, /* Atheros DB120 reference board */
ATH79_MACH_PB44, /* Atheros PB44 reference board */
--- /dev/null
+--- a/arch/mips/ath79/mach-ap136.c
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -1,5 +1,5 @@
+ /*
+- * Qualcomm Atheros AP136 reference board support
++ * Atheros AP136 reference board support
+ *
+ * Copyright (c) 2012 Qualcomm Atheros
+ * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
+@@ -18,23 +18,27 @@
+ *
+ */
+
+-#include <linux/pci.h>
+-#include <linux/ath9k_platform.h>
++#include <linux/platform_device.h>
++#include <linux/ar8216_platform.h>
+
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-ap9x-pci.h"
+ #include "dev-gpio-buttons.h"
++#include "dev-eth.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
+-#include "pci.h"
++#include "machtypes.h"
+
+-#define AP136_GPIO_LED_STATUS_RED 14
+-#define AP136_GPIO_LED_STATUS_GREEN 19
+ #define AP136_GPIO_LED_USB 4
+-#define AP136_GPIO_LED_WLAN_2G 13
+ #define AP136_GPIO_LED_WLAN_5G 12
++#define AP136_GPIO_LED_WLAN_2G 13
++#define AP136_GPIO_LED_STATUS_RED 14
+ #define AP136_GPIO_LED_WPS_RED 15
++#define AP136_GPIO_LED_STATUS_GREEN 19
+ #define AP136_GPIO_LED_WPS_GREEN 20
+
+ #define AP136_GPIO_BTN_WPS 16
+@@ -43,8 +47,10 @@
+ #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
+ #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
+
+-#define AP136_WMAC_CALDATA_OFFSET 0x1000
+-#define AP136_PCIE_CALDATA_OFFSET 0x5000
++#define AP136_MAC0_OFFSET 0
++#define AP136_MAC1_OFFSET 6
++#define AP136_WMAC_CALDATA_OFFSET 0x1000
++#define AP136_PCIE_CALDATA_OFFSET 0x5000
+
+ static struct gpio_led ap136_leds_gpio[] __initdata = {
+ {
+@@ -98,63 +104,82 @@ static struct gpio_keys_button ap136_gpi
+ },
+ };
+
+-static struct ath79_spi_controller_data ap136_spi0_data = {
+- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+- .cs_line = 0,
++static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg = {
++ .mode = AR8327_PAD_MAC_RGMII,
++ .txclk_delay_en = true,
++ .rxclk_delay_en = true,
++ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
++ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
+ };
+
+-static struct spi_board_info ap136_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "mx25l6405d",
+- .controller_data = &ap136_spi0_data,
++static struct ar8327_platform_data ap136_ar8327_data = {
++ .pad0_cfg = &ap136_ar8327_pad0_cfg,
++ .cpuport_cfg = {
++ .force_link = 1,
++ .speed = AR8327_PORT_SPEED_1000,
++ .duplex = 1,
++ .txpause = 1,
++ .rxpause = 1,
+ }
+ };
+
+-static struct ath79_spi_platform_data ap136_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
++static struct mdio_board_info ap136_mdio0_info[] = {
++ {
++ .bus_id = "ag71xx-mdio.0",
++ .phy_addr = 0,
++ .platform_data = &ap136_ar8327_data,
++ },
+ };
+
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ap136_ath9k_data;
+-
+-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
++static void __init ap136_gmac_setup(void)
+ {
+- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
+- dev->dev.platform_data = &ap136_ath9k_data;
++ void __iomem *base;
++ u32 t;
+
+- return 0;
+-}
++ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+-static void __init ap136_pci_init(u8 *eeprom)
+-{
+- memcpy(ap136_ath9k_data.eeprom_data, eeprom,
+- sizeof(ap136_ath9k_data.eeprom_data));
++ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
++
++ t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0);
++ t |= QCA955X_ETH_CFG_RGMII_GMAC0;
+
+- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
+- ath79_register_pci();
++ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
++
++ iounmap(base);
+ }
+-#else
+-static inline void ap136_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+
+ static void __init ap136_setup(void)
+ {
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
++ ath79_register_m25p80(NULL);
++
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
+ ap136_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(ap136_gpio_keys),
+ ap136_gpio_keys);
+- ath79_register_spi(&ap136_spi_data, ap136_spi_info,
+- ARRAY_SIZE(ap136_spi_info));
++
+ ath79_register_usb();
+- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
+- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
++ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
++ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
++
++ ap136_gmac_setup();
++
++ ath79_register_mdio(0, 0x0);
++
++ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
++
++ mdiobus_register_board_info(ap136_mdio0_info,
++ ARRAY_SIZE(ap136_mdio0_info));
++
++ /* GMAC0 is connected to an AR8327 switch */
++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++ ath79_eth0_data.phy_mask = BIT(0);
++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++ ath79_eth0_pll_data.pll_1000 = 0x06000000;
++
++ ath79_register_eth(0);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
-@@ -16,17 +16,86 @@
+@@ -16,18 +16,87 @@
enum ath79_mach_type {
ATH79_MACH_GENERIC = 0,
+ ATH79_MACH_AP113, /* Atheros AP113 reference board */
ATH79_MACH_AP121, /* Atheros AP121 reference board */
ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
+ ATH79_MACH_AP136, /* Atheros AP136 reference board */
ATH79_MACH_AP81, /* Atheros AP81 reference board */
+ ATH79_MACH_AP83, /* Atheros AP83 */
+ ATH79_MACH_AP96, /* Atheros AP96 */
config ATH79_MACH_AP121
bool "Atheros AP121 reference board"
select SOC_AR933X
-@@ -28,6 +74,24 @@ config ATH79_MACH_AP81
+@@ -40,6 +86,24 @@ config ATH79_MACH_AP81
Say 'Y' here if you want your kernel to support the
Atheros AP81 reference board.
config ATH79_MACH_DB120
bool "Atheros DB120 reference board"
select SOC_AR934X
-@@ -42,6 +106,13 @@ config ATH79_MACH_DB120
+@@ -54,6 +118,13 @@ config ATH79_MACH_DB120
Say 'Y' here if you want your kernel to support the
Atheros DB120 reference board.
config ATH79_MACH_PB44
bool "Atheros PB44 reference board"
select SOC_AR71XX
-@@ -54,6 +125,382 @@ config ATH79_MACH_PB44
+@@ -66,6 +137,382 @@ config ATH79_MACH_PB44
Say 'Y' here if you want your kernel to support the
Atheros PB44 reference board.
config ATH79_MACH_UBNT_XM
bool "Ubiquiti Networks XM (rev 1.0) board"
select SOC_AR724X
-@@ -67,6 +514,24 @@ config ATH79_MACH_UBNT_XM
+@@ -79,6 +526,24 @@ config ATH79_MACH_UBNT_XM
Say 'Y' here if you want your kernel to support the
Ubiquiti Networks XM (rev 1.0) board.
endmenu
config SOC_AR71XX
-@@ -102,10 +567,6 @@ config SOC_QCA955X
+@@ -114,10 +579,6 @@ config SOC_QCA955X
select PCI_AR724X if PCI
def_bool n
config ATH79_DEV_AP9X_PCI
select ATH79_PCI_ATH9K_FIXUP
def_bool n
-@@ -116,7 +577,14 @@ config ATH79_DEV_DSA
+@@ -128,7 +589,14 @@ config ATH79_DEV_DSA
config ATH79_DEV_ETH
def_bool n
def_bool n
config ATH79_DEV_GPIO_BUTTONS
-@@ -141,4 +609,7 @@ config ATH79_NVRAM
+@@ -153,4 +621,7 @@ config ATH79_NVRAM
config ATH79_PCI_ATH9K_FIXUP
def_bool n
endif
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
-@@ -36,8 +36,57 @@ obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += p
+@@ -36,9 +36,58 @@ obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += p
#
# Machines
#
+obj-$(CONFIG_ATH79_MACH_ALL0258N) += mach-all0258n.o
+obj-$(CONFIG_ATH79_MACH_AP113) += mach-ap113.o
obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
+ obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
+obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o
+obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -451,6 +451,17 @@ config ATH79_MACH_TL_WR941ND
+@@ -463,6 +463,17 @@ config ATH79_MACH_TL_WR941ND
select ATH79_DEV_M25P80
select ATH79_DEV_WMAC
select SOC_AR913X
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
-@@ -64,6 +64,7 @@ enum ath79_mach_type {
+@@ -65,6 +65,7 @@ enum ath79_mach_type {
ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */
ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */
ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */
ATH79_MACH_TL_WR703N, /* TP-LINK TL-WR703N */
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
-@@ -74,6 +74,7 @@ obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += m
+@@ -75,6 +75,7 @@ obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += m
obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o
obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -240,6 +240,18 @@ config ATH79_MACH_DIR_825_B1
+@@ -252,6 +252,18 @@ config ATH79_MACH_DIR_825_B1
select ATH79_DEV_M25P80
select ATH79_DEV_USB
select SOC_AR71XX
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
-@@ -32,6 +32,7 @@ enum ath79_mach_type {
+@@ -33,6 +33,7 @@ enum ath79_mach_type {
ATH79_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */
ATH79_MACH_DIR_615_E4, /* D-Link DIR-615 rev. E4 */
ATH79_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */
ATH79_MACH_JA76PF2, /* jjPlus JA76PF2 */
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
-@@ -49,6 +49,7 @@ obj-$(CONFIG_ATH79_MACH_DB120) += mach-
+@@ -50,6 +50,7 @@ obj-$(CONFIG_ATH79_MACH_DB120) += mach-
obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o
obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o
obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
-@@ -71,6 +71,7 @@ obj-$(CONFIG_ATH79_MACH_TL_MR3020) += ma
+@@ -72,6 +72,7 @@ obj-$(CONFIG_ATH79_MACH_TL_MR3020) += ma
obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o
obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o
obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o
obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
-@@ -416,6 +416,17 @@ config ATH79_MACH_TL_WA901ND_V2
+@@ -428,6 +428,17 @@ config ATH79_MACH_TL_WA901ND_V2
select ATH79_DEV_M25P80
select ATH79_DEV_WMAC
select SOC_AR933X
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
-@@ -65,6 +65,7 @@ enum ath79_mach_type {
+@@ -66,6 +66,7 @@ enum ath79_mach_type {
ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */
ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */
ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */
projects / openwrt / staging / neocturne.git / commitdiff