--- /dev/null
+From: MarkLee <Mark-MC.Lee@mediatek.com>
+Date: Wed, 13 Nov 2019 10:38:42 +0800
+Subject: [PATCH] net: ethernet: mediatek: Integrate GDM/PSE setup operations
+
+Integrate GDM/PSE setup operations into single function "mtk_gdm_config"
+
+Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -2211,6 +2211,28 @@ static int mtk_start_dma(struct mtk_eth
+ return 0;
+ }
+
++static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
++{
++ int i;
++
++ for (i = 0; i < MTK_MAC_COUNT; i++) {
++ u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
++
++ /* default setup the forward port to send frame to PDMA */
++ val &= ~0xffff;
++
++ /* Enable RX checksum */
++ val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
++
++ val |= config;
++
++ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
++ }
++ /* Reset and enable PSE */
++ mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
++ mtk_w32(eth, 0, MTK_RST_GL);
++}
++
+ static int mtk_open(struct net_device *dev)
+ {
+ struct mtk_mac *mac = netdev_priv(dev);
+@@ -2406,8 +2428,6 @@ static int mtk_hw_init(struct mtk_eth *e
+ mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
+ mtk_tx_irq_disable(eth, ~0);
+ mtk_rx_irq_disable(eth, ~0);
+- mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
+- mtk_w32(eth, 0, MTK_RST_GL);
+
+ /* FE int grouping */
+ mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
+@@ -2416,18 +2436,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
+ mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+
+- for (i = 0; i < MTK_MAC_COUNT; i++) {
+- u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
+-
+- /* setup the forward port to send frame to PDMA */
+- val &= ~0xffff;
+-
+- /* Enable RX checksum */
+- val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
+-
+- /* setup the mac dma */
+- mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
+- }
++ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
+
+ return 0;
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -84,6 +84,7 @@
+ #define MTK_GDMA_ICS_EN BIT(22)
+ #define MTK_GDMA_TCS_EN BIT(21)
+ #define MTK_GDMA_UCS_EN BIT(20)
++#define MTK_GDMA_TO_PDMA 0x0
+
+ /* Unicast Filter MAC Address Register - Low */
+ #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
--- /dev/null
+From: MarkLee <Mark-MC.Lee@mediatek.com>
+Date: Wed, 13 Nov 2019 10:38:43 +0800
+Subject: [PATCH] net: ethernet: mediatek: Refine the timing of GDM/PSE setup
+
+Refine the timing of GDM/PSE setup, move it from mtk_hw_init
+to mtk_open. This is recommended by the mt762x HW design to
+do GDM/PSE setup only after PDMA has been started.
+
+We exclude mt7628 in mtk_gdm_config function since it is a old IP
+and there is no GDM/PSE block on it.
+
+Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -2215,6 +2215,9 @@ static void mtk_gdm_config(struct mtk_et
+ {
+ int i;
+
++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
++ return;
++
+ for (i = 0; i < MTK_MAC_COUNT; i++) {
+ u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
+
+@@ -2253,6 +2256,8 @@ static int mtk_open(struct net_device *d
+ if (err)
+ return err;
+
++ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
++
+ napi_enable(ð->tx_napi);
+ napi_enable(ð->rx_napi);
+ mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
+@@ -2436,8 +2441,6 @@ static int mtk_hw_init(struct mtk_eth *e
+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
+ mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+
+- mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
+-
+ return 0;
+
+ err_disable_pm:
--- /dev/null
+From: MarkLee <Mark-MC.Lee@mediatek.com>
+Date: Wed, 13 Nov 2019 10:38:44 +0800
+Subject: [PATCH] net: ethernet: mediatek: Enable GDM GDMA_DROP_ALL mode
+
+Enable GDM GDMA_DROP_ALL mode to drop all packet during the
+stop operation. This is recommended by the mt762x HW design
+to drop all packet from GMAC before stopping PDMA.
+
+Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -2310,6 +2310,8 @@ static int mtk_stop(struct net_device *d
+ if (!refcount_dec_and_test(ð->dma_refcnt))
+ return 0;
+
++ mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
++
+ mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
+ mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
+ napi_disable(ð->tx_napi);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -85,6 +85,7 @@
+ #define MTK_GDMA_TCS_EN BIT(21)
+ #define MTK_GDMA_UCS_EN BIT(20)
+ #define MTK_GDMA_TO_PDMA 0x0
++#define MTK_GDMA_DROP_ALL 0x7777
+
+ /* Unicast Filter MAC Address Register - Low */
+ #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
skb_record_rx_queue(skb, 0);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -293,6 +293,7 @@
+@@ -295,6 +295,7 @@
#define RX_DMA_LSO BIT(30)
#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
MTK_QDMA_GLO_CFG);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -195,7 +195,7 @@
+@@ -197,7 +197,7 @@
#define MTK_RX_BT_32DWORDS (3 << 11)
#define MTK_NDP_CO_PRO BIT(10)
#define MTK_TX_WB_DDONE BIT(6)
if (likely(napi_schedule_prep(ð->tx_napi))) {
__napi_schedule(ð->tx_napi);
mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
-@@ -2282,6 +2299,9 @@ static int mtk_stop(struct net_device *d
+@@ -2311,6 +2328,9 @@ static int mtk_stop(struct net_device *d
napi_disable(ð->tx_napi);
napi_disable(ð->rx_napi);
if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
-@@ -2331,6 +2351,64 @@ err_disable_clks:
+@@ -2360,6 +2380,64 @@ err_disable_clks:
return ret;
}
static int mtk_hw_init(struct mtk_eth *eth)
{
int i, val, ret;
-@@ -2352,9 +2430,6 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2381,9 +2459,6 @@ static int mtk_hw_init(struct mtk_eth *e
goto err_disable_pm;
}
/* disable delay and normal interrupt */
mtk_tx_irq_disable(eth, ~0);
mtk_rx_irq_disable(eth, ~0);
-@@ -2393,11 +2468,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2422,11 +2497,10 @@ static int mtk_hw_init(struct mtk_eth *e
/* Enable RX VLan Offloading */
mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
- mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
mtk_tx_irq_disable(eth, ~0);
mtk_rx_irq_disable(eth, ~0);
- mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
-@@ -2916,6 +2990,13 @@ static int mtk_probe(struct platform_dev
+
+@@ -2930,6 +3004,13 @@ static int mtk_probe(struct platform_dev
spin_lock_init(ð->page_lock);
spin_lock_init(ð->tx_irq_lock);
spin_lock_init(ð->rx_irq_lock);
#define MTK_QDMA_PAGE_SIZE 2048
#define MTK_MAX_RX_LENGTH 1536
-@@ -129,13 +130,18 @@
+@@ -131,13 +132,18 @@
/* PDMA Delay Interrupt Register */
#define MTK_PDMA_DELAY_INT 0xa0c
/* PDMA Interrupt Status Register */
#define MTK_PDMA_INT_STATUS 0xa20
-@@ -217,6 +223,7 @@
+@@ -219,6 +225,7 @@
/* QDMA Interrupt Status Register */
#define MTK_QDMA_INT_STATUS 0x1A18
#define MTK_RX_DONE_DLY BIT(30)
#define MTK_RX_DONE_INT3 BIT(19)
#define MTK_RX_DONE_INT2 BIT(18)
#define MTK_RX_DONE_INT1 BIT(17)
-@@ -226,8 +233,7 @@
+@@ -228,8 +235,7 @@
#define MTK_TX_DONE_INT1 BIT(1)
#define MTK_TX_DONE_INT0 BIT(0)
#define MTK_RX_DONE_INT MTK_RX_DONE_DLY
/* QDMA Interrupt grouping registers */
#define MTK_QDMA_INT_GRP1 0x1a20
-@@ -890,6 +896,18 @@ struct mtk_eth {
+@@ -892,6 +898,18 @@ struct mtk_eth {
const struct mtk_soc_data *soc;
} else {
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -622,6 +622,7 @@ struct mtk_tx_buf {
+@@ -624,6 +624,7 @@ struct mtk_tx_buf {
* @phys: The physical addr of tx_buf
* @next_free: Pointer to the next free descriptor
* @last_free: Pointer to the last free descriptor
* @thresh: The threshold of minimum amount of free descriptors
* @free_count: QDMA uses a linked list. Track how many free descriptors
* are present
-@@ -632,6 +633,7 @@ struct mtk_tx_ring {
+@@ -634,6 +635,7 @@ struct mtk_tx_ring {
dma_addr_t phys;
struct mtk_tx_dma *next_free;
struct mtk_tx_dma *last_free;
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 13 Sep 2020 08:17:02 +0200
+Subject: [PATCH] net: ethernet: mtk_eth_soc: fix parsing packets in GDM
+
+When using DSA, set the special tag in GDM ingress control to allow the MAC
+to parse packets properly earlier. This affects rx DMA source port reporting.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -19,6 +19,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/pinctrl/devinfo.h>
+ #include <linux/phylink.h>
++#include <net/dsa.h>
+
+ #include "mtk_eth_soc.h"
+
+@@ -1240,12 +1241,14 @@ static int mtk_poll_rx(struct napi_struc
+ u8 *data, *new_data;
+ struct mtk_rx_dma *rxd, trxd;
+ int done = 0, bytes = 0;
++ bool uses_dsa = eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]);
+
+ while (done < budget) {
+ struct net_device *netdev;
+ unsigned int pktlen;
+ dma_addr_t dma_addr;
+ int mac;
++ u16 hash;
+
+ ring = mtk_get_rx_ring(eth);
+ if (unlikely(!ring))
+@@ -1259,13 +1262,13 @@ static int mtk_poll_rx(struct napi_struc
+ break;
+
+ /* find out which mac the packet come from. values start at 1 */
+- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+ mac = 0;
+- } else {
+- mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
+- RX_DMA_FPORT_MASK;
+- mac--;
+- }
++ else if (uses_dsa)
++ mac = !(trxd.rxd4 >> 22);
++ else
++ mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
++ RX_DMA_FPORT_MASK) - 1;
+
+ if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
+ !eth->netdev[mac]))
+@@ -2247,6 +2250,9 @@ static void mtk_gdm_config(struct mtk_et
+
+ val |= config;
+
++ if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]))
++ val |= MTK_GDMA_SPECIAL_TAG;
++
+ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
+ }
+ /* Reset and enable PSE */
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -82,6 +82,7 @@
+
+ /* GDM Exgress Control Register */
+ #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
++#define MTK_GDMA_SPECIAL_TAG BIT(24)
+ #define MTK_GDMA_ICS_EN BIT(22)
+ #define MTK_GDMA_TCS_EN BIT(21)
+ #define MTK_GDMA_UCS_EN BIT(20)
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 13 Sep 2020 08:27:24 +0200
+Subject: [PATCH] net: ethernet: mtk_eth_soc: set PPE flow hash as skb hash
+ if present
+
+This improves GRO performance
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1318,6 +1318,10 @@ static int mtk_poll_rx(struct napi_struc
+ skb->protocol = eth_type_trans(skb, netdev);
+ bytes += pktlen;
+
++ hash = trxd.rxd4 & GENMASK(13, 0);
++ if (hash != GENMASK(13, 0))
++ skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
++
+ if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
+ (trxd.rxd2 & RX_DMA_VTAG))
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
#include <linux/phylink.h>
+#include <linux/netfilter.h>
+#include <net/netfilter/nf_flow_table.h>
+ #include <net/dsa.h>
#include "mtk_eth_soc.h"
-
-@@ -1320,8 +1322,16 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1327,8 +1329,16 @@ static int mtk_poll_rx(struct napi_struc
(trxd.rxd2 & RX_DMA_VTAG))
__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
RX_DMA_VID(trxd.rxd3));
skip_rx:
ring->data[idx] = new_data;
-@@ -2255,6 +2265,9 @@ static int mtk_open(struct net_device *d
+@@ -2292,6 +2302,9 @@ static int mtk_open(struct net_device *d
mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
refcount_set(ð->dma_refcnt, 1);
}
else
refcount_inc(ð->dma_refcnt);
-@@ -2316,6 +2329,9 @@ static int mtk_stop(struct net_device *d
+@@ -2355,6 +2368,9 @@ static int mtk_stop(struct net_device *d
mtk_dma_free(eth);
return 0;
}
-@@ -2829,6 +2845,27 @@ static int mtk_set_rxnfc(struct net_devi
+@@ -2853,6 +2869,27 @@ static int mtk_set_rxnfc(struct net_devi
return ret;
}
static const struct ethtool_ops mtk_ethtool_ops = {
.get_link_ksettings = mtk_get_link_ksettings,
.set_link_ksettings = mtk_set_link_ksettings,
-@@ -2860,6 +2897,9 @@ static const struct net_device_ops mtk_n
+@@ -2884,6 +2921,9 @@ static const struct net_device_ops mtk_n
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = mtk_poll_controller,
#endif
};
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
-@@ -3202,6 +3242,7 @@ static const struct mtk_soc_data mt7622_
+@@ -3226,6 +3266,7 @@ static const struct mtk_soc_data mt7622_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7622_CLKS_BITMAP,
.required_pctl = false,
static const struct mtk_soc_data mt7623_data = {
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -787,6 +787,13 @@ enum mkt_eth_capabilities {
+@@ -790,6 +790,13 @@ enum mkt_eth_capabilities {
MTK_MUX_U3_GMAC2_TO_QPHY | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
/* struct mtk_eth_data - This is the structure holding all differences
* among various plaforms
* @ana_rgc3: The offset for register ANA_RGC3 related to
-@@ -804,6 +811,7 @@ struct mtk_soc_data {
+@@ -807,6 +814,7 @@ struct mtk_soc_data {
u32 required_clks;
bool required_pctl;
netdev_features_t hw_features;
};
/* currently no SoC has more than 2 macs */
-@@ -829,6 +837,23 @@ struct mtk_sgmii {
+@@ -832,6 +840,23 @@ struct mtk_sgmii {
u32 ana_rgc3;
};
/* struct mtk_eth - This is the main datasructure for holding the state
* of the driver
* @dev: The device pointer
-@@ -914,6 +939,16 @@ struct mtk_eth {
+@@ -917,6 +942,16 @@ struct mtk_eth {
u32 tx_int_status_reg;
u32 rx_dma_l4_valid;
int ip_align;
};
/* struct mtk_mac - the structure that holds the info about the MACs of the
-@@ -946,6 +981,7 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -949,6 +984,7 @@ void mtk_stats_update_mac(struct mtk_mac
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
u32 ana_rgc3);
-@@ -958,4 +994,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk
+@@ -961,4 +997,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
+++ /dev/null
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2240,6 +2240,31 @@ static int mtk_start_dma(struct mtk_eth
- return 0;
- }
-
-+static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
-+{
-+ int i;
-+
-+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
-+ return;
-+
-+ for (i = 0; i < MTK_MAC_COUNT; i++) {
-+ u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
-+
-+ /* default setup the forward port to send frame to PDMA */
-+ val &= ~0xffff;
-+
-+ /* Enable RX checksum */
-+ val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
-+
-+ val |= config;
-+
-+ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-+ }
-+ /* Reset and enable PSE */
-+ mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
-+ mtk_w32(eth, 0, MTK_RST_GL);
-+}
-+
- static int mtk_open(struct net_device *dev)
- {
- struct mtk_mac *mac = netdev_priv(dev);
-@@ -2260,6 +2285,8 @@ static int mtk_open(struct net_device *d
- if (err)
- return err;
-
-+ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
-+
- napi_enable(ð->tx_napi);
- napi_enable(ð->rx_napi);
- mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
-@@ -2315,6 +2342,8 @@ static int mtk_stop(struct net_device *d
- if (!refcount_dec_and_test(ð->dma_refcnt))
- return 0;
-
-+ mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
-+
- mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
- mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
- napi_disable(ð->tx_napi);
-@@ -2498,8 +2527,6 @@ static int mtk_hw_init(struct mtk_eth *e
- /* disable delay and normal interrupt */
- mtk_tx_irq_disable(eth, ~0);
- mtk_rx_irq_disable(eth, ~0);
-- mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
-- mtk_w32(eth, 0, MTK_RST_GL);
-
- /* FE int grouping */
- mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
-@@ -2508,19 +2535,6 @@ static int mtk_hw_init(struct mtk_eth *e
- mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
- mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
-
-- for (i = 0; i < MTK_MAC_COUNT; i++) {
-- u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
--
-- /* setup the forward port to send frame to PDMA */
-- val &= ~0xffff;
--
-- /* Enable RX checksum */
-- val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
--
-- /* setup the mac dma */
-- mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-- }
--
- return 0;
-
- err_disable_pm:
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -85,6 +85,8 @@
- #define MTK_GDMA_ICS_EN BIT(22)
- #define MTK_GDMA_TCS_EN BIT(21)
- #define MTK_GDMA_UCS_EN BIT(20)
-+#define MTK_GDMA_TO_PDMA 0x0
-+#define MTK_GDMA_DROP_ALL 0x7777
-
- /* Unicast Filter MAC Address Register - Low */
- #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/clk.h>
-@@ -2476,6 +2477,12 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2486,6 +2487,12 @@ static int mtk_hw_init(struct mtk_eth *e
if (ret)
goto err_disable_pm;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
ret = device_reset(eth->dev);
if (ret) {
-@@ -3078,6 +3085,16 @@ static int mtk_probe(struct platform_dev
+@@ -3088,6 +3095,16 @@ static int mtk_probe(struct platform_dev
}
}
GFP_KERNEL);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -425,6 +425,11 @@
+@@ -426,6 +426,11 @@
#define RSTCTRL_FE BIT(6)
#define RSTCTRL_PPE BIT(31)