rcar_gen3: drivers: ddr-a: Unify register definitions

Unify boot_init_dram_regdef_*.h into boot_init_dram_regdef.h and
clean up it's coding style a bit.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Iae3375969c05f80209ebf7b1ebc3633a7f6317ff

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
new file mode 100644 (file)
index 0000000..397bde0
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOOT_INIT_DRAM_REGDEF_H_
+#define BOOT_INIT_DRAM_REGDEF_H_
+
+/* DBSC registers */
+#define DBSC_DBSYSCONF0                0xE6790000U
+#define DBSC_DBSYSCONF1                0xE6790004U
+#define DBSC_DBPHYCONF0                0xE6790010U
+#define DBSC_DBKIND            0xE6790020U
+#define DBSC_DBMEMCONF00       0xE6790030U
+#define DBSC_DBMEMCONF01       0xE6790034U
+#define DBSC_DBMEMCONF02       0xE6790038U
+#define DBSC_DBMEMCONF03       0xE679003CU
+#define DBSC_DBMEMCONF10       0xE6790040U
+#define DBSC_DBMEMCONF11       0xE6790044U
+#define DBSC_DBMEMCONF12       0xE6790048U
+#define DBSC_DBMEMCONF13       0xE679004CU
+#define DBSC_DBMEMCONF20       0xE6790050U
+#define DBSC_DBMEMCONF21       0xE6790054U
+#define DBSC_DBMEMCONF22       0xE6790058U
+#define DBSC_DBMEMCONF23       0xE679005CU
+#define DBSC_DBMEMCONF30       0xE6790060U
+#define DBSC_DBMEMCONF31       0xE6790064U
+#define DBSC_DBMEMCONF32       0xE6790068U
+#define DBSC_DBMEMCONF33       0xE679006CU
+#define DBSC_DBSYSCNT0         0xE6790100U
+#define DBSC_DBSVCR1           0xE6790104U
+#define DBSC_DBSTATE0          0xE6790108U
+#define DBSC_DBSTATE1          0xE679010CU
+#define DBSC_DBINTEN           0xE6790180U
+#define DBSC_DBINTSTAT0                0xE6790184U
+#define DBSC_DBACEN            0xE6790200U
+#define DBSC_DBRFEN            0xE6790204U
+#define DBSC_DBCMD             0xE6790208U
+#define DBSC_DBWAIT            0xE6790210U
+#define DBSC_DBSYSCTRL0                0xE6790280U
+#define DBSC_DBTR0             0xE6790300U
+#define DBSC_DBTR1             0xE6790304U
+#define DBSC_DBTR2             0xE6790308U
+#define DBSC_DBTR3             0xE679030CU
+#define DBSC_DBTR4             0xE6790310U
+#define DBSC_DBTR5             0xE6790314U
+#define DBSC_DBTR6             0xE6790318U
+#define DBSC_DBTR7             0xE679031CU
+#define DBSC_DBTR8             0xE6790320U
+#define DBSC_DBTR9             0xE6790324U
+#define DBSC_DBTR10            0xE6790328U
+#define DBSC_DBTR11            0xE679032CU
+#define DBSC_DBTR12            0xE6790330U
+#define DBSC_DBTR13            0xE6790334U
+#define DBSC_DBTR14            0xE6790338U
+#define DBSC_DBTR15            0xE679033CU
+#define DBSC_DBTR16            0xE6790340U
+#define DBSC_DBTR17            0xE6790344U
+#define DBSC_DBTR18            0xE6790348U
+#define DBSC_DBTR19            0xE679034CU
+#define DBSC_DBTR20            0xE6790350U
+#define DBSC_DBTR21            0xE6790354U
+#define DBSC_DBTR22            0xE6790358U
+#define DBSC_DBTR23            0xE679035CU
+#define DBSC_DBTR24            0xE6790360U
+#define DBSC_DBTR25            0xE6790364U
+#define DBSC_DBBL              0xE6790400U
+#define DBSC_DBRFCNF1          0xE6790414U
+#define DBSC_DBRFCNF2          0xE6790418U
+#define DBSC_DBTSPCNF          0xE6790420U
+#define DBSC_DBCALCNF          0xE6790424U
+#define DBSC_DBRNK2            0xE6790438U
+#define DBSC_DBRNK3            0xE679043CU
+#define DBSC_DBRNK4            0xE6790440U
+#define DBSC_DBRNK5            0xE6790444U
+#define DBSC_DBPDNCNF          0xE6790450U
+#define DBSC_DBODT0            0xE6790460U
+#define DBSC_DBODT1            0xE6790464U
+#define DBSC_DBODT2            0xE6790468U
+#define DBSC_DBODT3            0xE679046CU
+#define DBSC_DBODT4            0xE6790470U
+#define DBSC_DBODT5            0xE6790474U
+#define DBSC_DBODT6            0xE6790478U
+#define DBSC_DBODT7            0xE679047CU
+#define DBSC_DBADJ0            0xE6790500U
+#define DBSC_DBDBICNT          0xE6790518U
+#define DBSC_DBDFIPMSTRCNF     0xE6790520U
+#define DBSC_DBDFIPMSTRSTAT    0xE6790524U
+#define DBSC_DBDFILPCNF                0xE6790528U
+#define DBSC_DBDFICUPDCNF      0xE679052CU
+#define DBSC_DBDFISTAT0                0xE6790600U
+#define DBSC_DBDFICNT0         0xE6790604U
+#define DBSC_DBPDCNT00         0xE6790610U
+#define DBSC_DBPDCNT01         0xE6790614U
+#define DBSC_DBPDCNT02         0xE6790618U
+#define DBSC_DBPDCNT03         0xE679061CU
+#define DBSC_DBPDLK0           0xE6790620U
+#define DBSC_DBPDRGA0          0xE6790624U
+#define DBSC_DBPDRGD0          0xE6790628U
+#define DBSC_DBPDSTAT00                0xE6790630U
+#define DBSC_DBDFISTAT1                0xE6790640U
+#define DBSC_DBDFICNT1         0xE6790644U
+#define DBSC_DBPDCNT10         0xE6790650U
+#define DBSC_DBPDCNT11         0xE6790654U
+#define DBSC_DBPDCNT12         0xE6790658U
+#define DBSC_DBPDCNT13         0xE679065CU
+#define DBSC_DBPDLK1           0xE6790660U
+#define DBSC_DBPDRGA1          0xE6790664U
+#define DBSC_DBPDRGD1          0xE6790668U
+#define DBSC_DBPDSTAT10                0xE6790670U
+#define DBSC_DBDFISTAT2                0xE6790680U
+#define DBSC_DBDFICNT2         0xE6790684U
+#define DBSC_DBPDCNT20         0xE6790690U
+#define DBSC_DBPDCNT21         0xE6790694U
+#define DBSC_DBPDCNT22         0xE6790698U
+#define DBSC_DBPDCNT23         0xE679069CU
+#define DBSC_DBPDLK2           0xE67906A0U
+#define DBSC_DBPDRGA2          0xE67906A4U
+#define DBSC_DBPDRGD2          0xE67906A8U
+#define DBSC_DBPDSTAT20                0xE67906B0U
+#define DBSC_DBDFISTAT3                0xE67906C0U
+#define DBSC_DBDFICNT3         0xE67906C4U
+#define DBSC_DBPDCNT30         0xE67906D0U
+#define DBSC_DBPDCNT31         0xE67906D4U
+#define DBSC_DBPDCNT32         0xE67906D8U
+#define DBSC_DBPDCNT33         0xE67906DCU
+#define DBSC_DBPDLK3           0xE67906E0U
+#define DBSC_DBPDRGA3          0xE67906E4U
+#define DBSC_DBPDRGD3          0xE67906E8U
+#define DBSC_DBPDSTAT30                0xE67906F0U
+#define DBSC_DBBUS0CNF0                0xE6790800U
+#define DBSC_DBBUS0CNF1                0xE6790804U
+#define DBSC_DBCAM0CNF1                0xE6790904U
+#define DBSC_DBCAM0CNF2                0xE6790908U
+#define DBSC_DBCAM0CNF3                0xE679090CU
+#define DBSC_DBCAM0CTRL0       0xE6790940U
+#define DBSC_DBCAM0STAT0       0xE6790980U
+#define DBSC_DBCAM1STAT0       0xE6790990U
+#define DBSC_DBBCAMSWAP                0xE67909F0U
+#define DBSC_DBBCAMDIS         0xE67909FCU
+#define DBSC_DBSCHCNT0         0xE6791000U
+#define DBSC_DBSCHCNT1         0xE6791004U
+#define DBSC_DBSCHSZ0          0xE6791010U
+#define DBSC_DBSCHRW0          0xE6791020U
+#define DBSC_DBSCHRW1          0xE6791024U
+#define DBSC_DBSCHQOS00                0xE6791030U
+#define DBSC_DBSCHQOS01                0xE6791034U
+#define DBSC_DBSCHQOS02                0xE6791038U
+#define DBSC_DBSCHQOS03                0xE679103CU
+#define DBSC_DBSCHQOS10                0xE6791040U
+#define DBSC_DBSCHQOS11                0xE6791044U
+#define DBSC_DBSCHQOS12                0xE6791048U
+#define DBSC_DBSCHQOS13                0xE679104CU
+#define DBSC_DBSCHQOS20                0xE6791050U
+#define DBSC_DBSCHQOS21                0xE6791054U
+#define DBSC_DBSCHQOS22                0xE6791058U
+#define DBSC_DBSCHQOS23                0xE679105CU
+#define DBSC_DBSCHQOS30                0xE6791060U
+#define DBSC_DBSCHQOS31                0xE6791064U
+#define DBSC_DBSCHQOS32                0xE6791068U
+#define DBSC_DBSCHQOS33                0xE679106CU
+#define DBSC_DBSCHQOS40                0xE6791070U
+#define DBSC_DBSCHQOS41                0xE6791074U
+#define DBSC_DBSCHQOS42                0xE6791078U
+#define DBSC_DBSCHQOS43                0xE679107CU
+#define DBSC_DBSCHQOS50                0xE6791080U
+#define DBSC_DBSCHQOS51                0xE6791084U
+#define DBSC_DBSCHQOS52                0xE6791088U
+#define DBSC_DBSCHQOS53                0xE679108CU
+#define DBSC_DBSCHQOS60                0xE6791090U
+#define DBSC_DBSCHQOS61                0xE6791094U
+#define DBSC_DBSCHQOS62                0xE6791098U
+#define DBSC_DBSCHQOS63                0xE679109CU
+#define DBSC_DBSCHQOS70                0xE67910A0U
+#define DBSC_DBSCHQOS71                0xE67910A4U
+#define DBSC_DBSCHQOS72                0xE67910A8U
+#define DBSC_DBSCHQOS73                0xE67910ACU
+#define DBSC_DBSCHQOS80                0xE67910B0U
+#define DBSC_DBSCHQOS81                0xE67910B4U
+#define DBSC_DBSCHQOS82                0xE67910B8U
+#define DBSC_DBSCHQOS83                0xE67910BCU
+#define DBSC_DBSCHQOS90                0xE67910C0U
+#define DBSC_DBSCHQOS91                0xE67910C4U
+#define DBSC_DBSCHQOS92                0xE67910C8U
+#define DBSC_DBSCHQOS93                0xE67910CCU
+#define DBSC_DBSCHQOS100       0xE67910D0U
+#define DBSC_DBSCHQOS101       0xE67910D4U
+#define DBSC_DBSCHQOS102       0xE67910D8U
+#define DBSC_DBSCHQOS103       0xE67910DCU
+#define DBSC_DBSCHQOS110       0xE67910E0U
+#define DBSC_DBSCHQOS111       0xE67910E4U
+#define DBSC_DBSCHQOS112       0xE67910E8U
+#define DBSC_DBSCHQOS113       0xE67910ECU
+#define DBSC_DBSCHQOS120       0xE67910F0U
+#define DBSC_DBSCHQOS121       0xE67910F4U
+#define DBSC_DBSCHQOS122       0xE67910F8U
+#define DBSC_DBSCHQOS123       0xE67910FCU
+#define DBSC_DBSCHQOS130       0xE6791100U
+#define DBSC_DBSCHQOS131       0xE6791104U
+#define DBSC_DBSCHQOS132       0xE6791108U
+#define DBSC_DBSCHQOS133       0xE679110CU
+#define DBSC_DBSCHQOS140       0xE6791110U
+#define DBSC_DBSCHQOS141       0xE6791114U
+#define DBSC_DBSCHQOS142       0xE6791118U
+#define DBSC_DBSCHQOS143       0xE679111CU
+#define DBSC_DBSCHQOS150       0xE6791120U
+#define DBSC_DBSCHQOS151       0xE6791124U
+#define DBSC_DBSCHQOS152       0xE6791128U
+#define DBSC_DBSCHQOS153       0xE679112CU
+#define DBSC_SCFCTST0          0xE6791700U
+#define DBSC_SCFCTST1          0xE6791708U
+#define DBSC_SCFCTST2          0xE679170CU
+#define DBSC_DBMRRDR0          0xE6791800U
+#define DBSC_DBMRRDR1          0xE6791804U
+#define DBSC_DBMRRDR2          0xE6791808U
+#define DBSC_DBMRRDR3          0xE679180CU
+#define DBSC_DBMRRDR4          0xE6791810U
+#define DBSC_DBMRRDR5          0xE6791814U
+#define DBSC_DBMRRDR6          0xE6791818U
+#define DBSC_DBMRRDR7          0xE679181CU
+#define DBSC_DBDTMP0           0xE6791820U
+#define DBSC_DBDTMP1           0xE6791824U
+#define DBSC_DBDTMP2           0xE6791828U
+#define DBSC_DBDTMP3           0xE679182CU
+#define DBSC_DBDTMP4           0xE6791830U
+#define DBSC_DBDTMP5           0xE6791834U
+#define DBSC_DBDTMP6           0xE6791838U
+#define DBSC_DBDTMP7           0xE679183CU
+#define DBSC_DBDQSOSC00                0xE6791840U
+#define DBSC_DBDQSOSC01                0xE6791844U
+#define DBSC_DBDQSOSC10                0xE6791848U
+#define DBSC_DBDQSOSC11                0xE679184CU
+#define DBSC_DBDQSOSC20                0xE6791850U
+#define DBSC_DBDQSOSC21                0xE6791854U
+#define DBSC_DBDQSOSC30                0xE6791858U
+#define DBSC_DBDQSOSC31                0xE679185CU
+#define DBSC_DBDQSOSC40                0xE6791860U
+#define DBSC_DBDQSOSC41                0xE6791864U
+#define DBSC_DBDQSOSC50                0xE6791868U
+#define DBSC_DBDQSOSC51                0xE679186CU
+#define DBSC_DBDQSOSC60                0xE6791870U
+#define DBSC_DBDQSOSC61                0xE6791874U
+#define DBSC_DBDQSOSC70                0xE6791878U
+#define DBSC_DBDQSOSC71                0xE679187CU
+#define DBSC_DBOSCTHH00                0xE6791880U
+#define DBSC_DBOSCTHH01                0xE6791884U
+#define DBSC_DBOSCTHH10                0xE6791888U
+#define DBSC_DBOSCTHH11                0xE679188CU
+#define DBSC_DBOSCTHH20                0xE6791890U
+#define DBSC_DBOSCTHH21                0xE6791894U
+#define DBSC_DBOSCTHH30                0xE6791898U
+#define DBSC_DBOSCTHH31                0xE679189CU
+#define DBSC_DBOSCTHH40                0xE67918A0U
+#define DBSC_DBOSCTHH41                0xE67918A4U
+#define DBSC_DBOSCTHH50                0xE67918A8U
+#define DBSC_DBOSCTHH51                0xE67918ACU
+#define DBSC_DBOSCTHH60                0xE67918B0U
+#define DBSC_DBOSCTHH61                0xE67918B4U
+#define DBSC_DBOSCTHH70                0xE67918B8U
+#define DBSC_DBOSCTHH71                0xE67918BCU
+#define DBSC_DBOSCTHL00                0xE67918C0U
+#define DBSC_DBOSCTHL01                0xE67918C4U
+#define DBSC_DBOSCTHL10                0xE67918C8U
+#define DBSC_DBOSCTHL11                0xE67918CCU
+#define DBSC_DBOSCTHL20                0xE67918D0U
+#define DBSC_DBOSCTHL21                0xE67918D4U
+#define DBSC_DBOSCTHL30                0xE67918D8U
+#define DBSC_DBOSCTHL31                0xE67918DCU
+#define DBSC_DBOSCTHL40                0xE67918E0U
+#define DBSC_DBOSCTHL41                0xE67918E4U
+#define DBSC_DBOSCTHL50                0xE67918E8U
+#define DBSC_DBOSCTHL51                0xE67918ECU
+#define DBSC_DBOSCTHL60                0xE67918F0U
+#define DBSC_DBOSCTHL61                0xE67918F4U
+#define DBSC_DBOSCTHL70                0xE67918F8U
+#define DBSC_DBOSCTHL71                0xE67918FCU
+#define DBSC_DBMEMSWAPCONF0    0xE6792000U
+
+/* CPG registers */
+#define CPG_SRCR4              0xE61500BCU
+#define CPG_PLLECR             0xE61500D0U
+#define CPG_CPGWPR             0xE6150900U
+#define CPG_CPGWPCR            0xE6150904U
+#define CPG_SRSTCLR4           0xE6150950U
+
+/* MODE Monitor registers */
+#define RST_MODEMR             0xE6160060U
+
+#endif /* BOOT_INIT_DRAM_REGDEF_H_*/

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h
deleted file mode 100644 (file)
index 6d48d57..0000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/*
- * Revision history
- *
- * rev.0.01    2017/05/22    New
- */
-
-#ifndef BOOT_INIT_DRAM_REGDEF_D3_H_
-#define BOOT_INIT_DRAM_REGDEF_D3_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* DBSC registers */
-
-#define                                DBSC_D3_DBSYSCONF1         0xE6790004U
-#define                                DBSC_D3_DBPHYCONF0         0xE6790010U
-#define                                DBSC_D3_DBKIND             0xE6790020U
-#define                                DBSC_D3_DBMEMCONF00        0xE6790030U
-#define                                DBSC_D3_DBMEMCONF01        0xE6790034U
-#define                                DBSC_D3_DBMEMCONF02        0xE6790038U
-#define                                DBSC_D3_DBMEMCONF03        0xE679003CU
-#define                                DBSC_D3_DBMEMCONF10        0xE6790040U
-#define                                DBSC_D3_DBMEMCONF11        0xE6790044U
-#define                                DBSC_D3_DBMEMCONF12        0xE6790048U
-#define                                DBSC_D3_DBMEMCONF13        0xE679004CU
-#define                                DBSC_D3_DBMEMCONF20        0xE6790050U
-#define                                DBSC_D3_DBMEMCONF21        0xE6790054U
-#define                                DBSC_D3_DBMEMCONF22        0xE6790058U
-#define                                DBSC_D3_DBMEMCONF23        0xE679005CU
-#define                                DBSC_D3_DBMEMCONF30        0xE6790060U
-#define                                DBSC_D3_DBMEMCONF31        0xE6790064U
-#define                                DBSC_D3_DBMEMCONF32        0xE6790068U
-#define                                DBSC_D3_DBMEMCONF33        0xE679006CU
-#define                                DBSC_D3_DBSYSCNT0          0xE6790100U
-#define                                DBSC_D3_DBSVCR1            0xE6790104U
-#define                                DBSC_D3_DBSTATE0           0xE6790108U
-#define                                DBSC_D3_DBSTATE1           0xE679010CU
-#define                                DBSC_D3_DBINTEN            0xE6790180U
-#define                                DBSC_D3_DBINTSTAT0         0xE6790184U
-#define                                DBSC_D3_DBACEN             0xE6790200U
-#define                                DBSC_D3_DBRFEN             0xE6790204U
-#define                                DBSC_D3_DBCMD              0xE6790208U
-#define                                DBSC_D3_DBWAIT             0xE6790210U
-#define                                DBSC_D3_DBSYSCTRL0         0xE6790280U
-#define                                DBSC_D3_DBTR0              0xE6790300U
-#define                                DBSC_D3_DBTR1              0xE6790304U
-#define                                DBSC_D3_DBTR2              0xE6790308U
-#define                                DBSC_D3_DBTR3              0xE679030CU
-#define                                DBSC_D3_DBTR4              0xE6790310U
-#define                                DBSC_D3_DBTR5              0xE6790314U
-#define                                DBSC_D3_DBTR6              0xE6790318U
-#define                                DBSC_D3_DBTR7              0xE679031CU
-#define                                DBSC_D3_DBTR8              0xE6790320U
-#define                                DBSC_D3_DBTR9              0xE6790324U
-#define                                DBSC_D3_DBTR10             0xE6790328U
-#define                                DBSC_D3_DBTR11             0xE679032CU
-#define                                DBSC_D3_DBTR12             0xE6790330U
-#define                                DBSC_D3_DBTR13             0xE6790334U
-#define                                DBSC_D3_DBTR14             0xE6790338U
-#define                                DBSC_D3_DBTR15             0xE679033CU
-#define                                DBSC_D3_DBTR16             0xE6790340U
-#define                                DBSC_D3_DBTR17             0xE6790344U
-#define                                DBSC_D3_DBTR18             0xE6790348U
-#define                                DBSC_D3_DBTR19             0xE679034CU
-#define                                DBSC_D3_DBTR20             0xE6790350U
-#define                                DBSC_D3_DBTR21             0xE6790354U
-#define                                DBSC_D3_DBTR22             0xE6790358U
-#define                                DBSC_D3_DBTR24             0xE6790360U
-#define                                DBSC_D3_DBTR25             0xE6790364U
-#define                                DBSC_D3_DBBL               0xE6790400U
-#define                                DBSC_D3_DBRFCNF1           0xE6790414U
-#define                                DBSC_D3_DBRFCNF2           0xE6790418U
-#define                                DBSC_D3_DBCALCNF           0xE6790424U
-#define                                DBSC_D3_DBRNK2             0xE6790438U
-#define                                DBSC_D3_DBRNK3             0xE679043CU
-#define                                DBSC_D3_DBRNK4             0xE6790440U
-#define                                DBSC_D3_DBRNK5             0xE6790444U
-#define                                DBSC_D3_DBPDNCNF           0xE6790450U
-#define                                DBSC_D3_DBODT0             0xE6790460U
-#define                                DBSC_D3_DBODT1             0xE6790464U
-#define                                DBSC_D3_DBODT2             0xE6790468U
-#define                                DBSC_D3_DBODT3             0xE679046CU
-#define                                DBSC_D3_DBADJ0             0xE6790500U
-#define                                DBSC_D3_DBDBICNT           0xE6790518U
-#define                                DBSC_D3_DBDFICUPDCNF       0xE679052CU
-#define                                DBSC_D3_DBDFICNT0          0xE6790604U
-#define                                DBSC_D3_DBPDLK0            0xE6790620U
-#define                                DBSC_D3_DBPDRGA0           0xE6790624U
-#define                                DBSC_D3_DBPDRGD0           0xE6790628U
-#define                                DBSC_D3_DBPDSTAT00         0xE6790630U
-#define                                DBSC_D3_DBDFISTAT1         0xE6790640U
-#define                                DBSC_D3_DBDFICNT1          0xE6790644U
-#define                                DBSC_D3_DBPDLK1            0xE6790660U
-#define                                DBSC_D3_DBPDRGA1           0xE6790664U
-#define                                DBSC_D3_DBPDRGD1           0xE6790668U
-#define                                DBSC_D3_DBDFICNT2          0xE6790684U
-#define                                DBSC_D3_DBPDLK2            0xE67906A0U
-#define                                DBSC_D3_DBPDRGA2           0xE67906A4U
-#define                                DBSC_D3_DBPDRGD2           0xE67906A8U
-#define                                DBSC_D3_DBPDSTAT20         0xE67906B0U
-#define                                DBSC_D3_DBDFISTAT3         0xE67906C0U
-#define                                DBSC_D3_DBDFICNT3          0xE67906C4U
-#define                                DBSC_D3_DBPDLK3            0xE67906E0U
-#define                                DBSC_D3_DBPDRGA3           0xE67906E4U
-#define                                DBSC_D3_DBPDRGD3           0xE67906E8U
-#define                                DBSC_D3_DBBUS0CNF1         0xE6790804U
-#define                                DBSC_D3_DBCAM0CNF1         0xE6790904U
-#define                                DBSC_D3_DBCAM0CNF2         0xE6790908U
-#define                                DBSC_D3_DBCAM0STAT0        0xE6790980U
-#define                                DBSC_D3_DBCAM1STAT0        0xE6790990U
-#define                                DBSC_D3_DBBCAMDIS          0xE67909FCU
-#define                                DBSC_D3_DBSCHCNT0          0xE6791000U
-#define                                DBSC_D3_DBSCHSZ0           0xE6791010U
-#define                                DBSC_D3_DBSCHRW0           0xE6791020U
-#define                                DBSC_D3_DBSCHRW1           0xE6791024U
-#define                                DBSC_D3_DBSCHQOS00         0xE6791030U
-#define                                DBSC_D3_DBSCHQOS01         0xE6791034U
-#define                                DBSC_D3_DBSCHQOS02         0xE6791038U
-#define                                DBSC_D3_DBSCHQOS03         0xE679103CU
-#define                                DBSC_D3_DBSCHQOS10         0xE6791040U
-#define                                DBSC_D3_DBSCHQOS11         0xE6791044U
-#define                                DBSC_D3_DBSCHQOS12         0xE6791048U
-#define                                DBSC_D3_DBSCHQOS13         0xE679104CU
-#define                                DBSC_D3_DBSCHQOS20         0xE6791050U
-#define                                DBSC_D3_DBSCHQOS21         0xE6791054U
-#define                                DBSC_D3_DBSCHQOS22         0xE6791058U
-#define                                DBSC_D3_DBSCHQOS23         0xE679105CU
-#define                                DBSC_D3_DBSCHQOS30         0xE6791060U
-#define                                DBSC_D3_DBSCHQOS31         0xE6791064U
-#define                                DBSC_D3_DBSCHQOS32         0xE6791068U
-#define                                DBSC_D3_DBSCHQOS33         0xE679106CU
-#define                                DBSC_D3_DBSCHQOS40         0xE6791070U
-#define                                DBSC_D3_DBSCHQOS41         0xE6791074U
-#define                                DBSC_D3_DBSCHQOS42         0xE6791078U
-#define                                DBSC_D3_DBSCHQOS43         0xE679107CU
-#define                                DBSC_D3_DBSCHQOS50         0xE6791080U
-#define                                DBSC_D3_DBSCHQOS51         0xE6791084U
-#define                                DBSC_D3_DBSCHQOS52         0xE6791088U
-#define                                DBSC_D3_DBSCHQOS53         0xE679108CU
-#define                                DBSC_D3_DBSCHQOS60         0xE6791090U
-#define                                DBSC_D3_DBSCHQOS61         0xE6791094U
-#define                                DBSC_D3_DBSCHQOS62         0xE6791098U
-#define                                DBSC_D3_DBSCHQOS63         0xE679109CU
-#define                                DBSC_D3_DBSCHQOS70         0xE67910A0U
-#define                                DBSC_D3_DBSCHQOS71         0xE67910A4U
-#define                                DBSC_D3_DBSCHQOS72         0xE67910A8U
-#define                                DBSC_D3_DBSCHQOS73         0xE67910ACU
-#define                                DBSC_D3_DBSCHQOS80         0xE67910B0U
-#define                                DBSC_D3_DBSCHQOS81         0xE67910B4U
-#define                                DBSC_D3_DBSCHQOS82         0xE67910B8U
-#define                                DBSC_D3_DBSCHQOS83         0xE67910BCU
-#define                                DBSC_D3_DBSCHQOS90         0xE67910C0U
-#define                                DBSC_D3_DBSCHQOS91         0xE67910C4U
-#define                                DBSC_D3_DBSCHQOS92         0xE67910C8U
-#define                                DBSC_D3_DBSCHQOS93         0xE67910CCU
-#define                                DBSC_D3_DBSCHQOS100        0xE67910D0U
-#define                                DBSC_D3_DBSCHQOS101        0xE67910D4U
-#define                                DBSC_D3_DBSCHQOS102        0xE67910D8U
-#define                                DBSC_D3_DBSCHQOS103        0xE67910DCU
-#define                                DBSC_D3_DBSCHQOS110        0xE67910E0U
-#define                                DBSC_D3_DBSCHQOS111        0xE67910E4U
-#define                                DBSC_D3_DBSCHQOS112        0xE67910E8U
-#define                                DBSC_D3_DBSCHQOS113        0xE67910ECU
-#define                                DBSC_D3_DBSCHQOS120        0xE67910F0U
-#define                                DBSC_D3_DBSCHQOS121        0xE67910F4U
-#define                                DBSC_D3_DBSCHQOS122        0xE67910F8U
-#define                                DBSC_D3_DBSCHQOS123        0xE67910FCU
-#define                                DBSC_D3_DBSCHQOS130        0xE6791100U
-#define                                DBSC_D3_DBSCHQOS131        0xE6791104U
-#define                                DBSC_D3_DBSCHQOS132        0xE6791108U
-#define                                DBSC_D3_DBSCHQOS133        0xE679110CU
-#define                                DBSC_D3_DBSCHQOS140        0xE6791110U
-#define                                DBSC_D3_DBSCHQOS141        0xE6791114U
-#define                                DBSC_D3_DBSCHQOS142        0xE6791118U
-#define                                DBSC_D3_DBSCHQOS143        0xE679111CU
-#define                                DBSC_D3_DBSCHQOS150        0xE6791120U
-#define                                DBSC_D3_DBSCHQOS151        0xE6791124U
-#define                                DBSC_D3_DBSCHQOS152        0xE6791128U
-#define                                DBSC_D3_DBSCHQOS153        0xE679112CU
-#define                                DBSC_D3_SCFCTST0           0xE6791700U
-#define                                DBSC_D3_SCFCTST1           0xE6791708U
-#define                                DBSC_D3_SCFCTST2           0xE679170CU
-#define                                DBSC_D3_DBMRRDR0           0xE6791800U
-#define                                DBSC_D3_DBMRRDR1           0xE6791804U
-#define                                DBSC_D3_DBMRRDR2           0xE6791808U
-#define                                DBSC_D3_DBMRRDR3           0xE679180CU
-#define                                DBSC_D3_DBMRRDR4           0xE6791810U
-#define                                DBSC_D3_DBMRRDR5           0xE6791814U
-#define                                DBSC_D3_DBMRRDR6           0xE6791818U
-#define                                DBSC_D3_DBMRRDR7           0xE679181CU
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* BOOT_INIT_DRAM_REGDEF_D3_H_*/

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h
deleted file mode 100644 (file)
index 6b2d9fe..0000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_REGDEF_E3_H
-#define BOOT_INIT_DRAM_REGDEF_E3_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* DBSC registers */
-
-#define                                DBSC_E3_DBSYSCONF1         0xE6790004U
-#define                                DBSC_E3_DBPHYCONF0         0xE6790010U
-#define                                DBSC_E3_DBKIND             0xE6790020U
-#define                                DBSC_E3_DBMEMCONF00        0xE6790030U
-#define                                DBSC_E3_DBSYSCNT0          0xE6790100U
-#define                                DBSC_E3_DBACEN             0xE6790200U
-#define                                DBSC_E3_DBRFEN             0xE6790204U
-#define                                DBSC_E3_DBCMD              0xE6790208U
-#define                                DBSC_E3_DBWAIT             0xE6790210U
-#define                                DBSC_E3_DBTR0              0xE6790300U
-#define                                DBSC_E3_DBTR1              0xE6790304U
-#define                                DBSC_E3_DBTR2              0xE6790308U
-#define                                DBSC_E3_DBTR3              0xE679030CU
-#define                                DBSC_E3_DBTR4              0xE6790310U
-#define                                DBSC_E3_DBTR5              0xE6790314U
-#define                                DBSC_E3_DBTR6              0xE6790318U
-#define                                DBSC_E3_DBTR7              0xE679031CU
-#define                                DBSC_E3_DBTR8              0xE6790320U
-#define                                DBSC_E3_DBTR9              0xE6790324U
-#define                                DBSC_E3_DBTR10             0xE6790328U
-#define                                DBSC_E3_DBTR11             0xE679032CU
-#define                                DBSC_E3_DBTR12             0xE6790330U
-#define                                DBSC_E3_DBTR13             0xE6790334U
-#define                                DBSC_E3_DBTR14             0xE6790338U
-#define                                DBSC_E3_DBTR15             0xE679033CU
-#define                                DBSC_E3_DBTR16             0xE6790340U
-#define                                DBSC_E3_DBTR17             0xE6790344U
-#define                                DBSC_E3_DBTR18             0xE6790348U
-#define                                DBSC_E3_DBTR19             0xE679034CU
-#define                                DBSC_E3_DBTR20             0xE6790350U
-#define                                DBSC_E3_DBTR21             0xE6790354U
-#define                                DBSC_E3_DBBL               0xE6790400U
-#define                                DBSC_E3_DBRFCNF1           0xE6790414U
-#define                                DBSC_E3_DBRFCNF2           0xE6790418U
-#define                                DBSC_E3_DBCALCNF           0xE6790424U
-#define                                DBSC_E3_DBODT0             0xE6790460U
-#define                                DBSC_E3_DBADJ0             0xE6790500U
-#define                                DBSC_E3_DBDFICUPDCNF       0xE679052CU
-#define                                DBSC_E3_DBDFICNT0          0xE6790604U
-#define                                DBSC_E3_DBPDLK0            0xE6790620U
-#define                                DBSC_E3_DBPDRGA0           0xE6790624U
-#define                                DBSC_E3_DBPDRGD0           0xE6790628U
-#define                                DBSC_E3_DBBUS0CNF1         0xE6790804U
-#define                                DBSC_E3_DBCAM0CNF1         0xE6790904U
-#define                                DBSC_E3_DBCAM0CNF2         0xE6790908U
-#define                                DBSC_E3_DBCAM0STAT0        0xE6790980U
-#define                                DBSC_E3_DBBCAMDIS          0xE67909FCU
-#define                                DBSC_E3_DBSCHCNT0          0xE6791000U
-#define                                DBSC_E3_DBSCHSZ0           0xE6791010U
-#define                                DBSC_E3_DBSCHRW0           0xE6791020U
-#define                                DBSC_E3_DBSCHRW1           0xE6791024U
-#define                                DBSC_E3_DBSCHQOS00         0xE6791030U
-#define                                DBSC_E3_DBSCHQOS01         0xE6791034U
-#define                                DBSC_E3_DBSCHQOS02         0xE6791038U
-#define                                DBSC_E3_DBSCHQOS03         0xE679103CU
-#define                                DBSC_E3_DBSCHQOS40         0xE6791070U
-#define                                DBSC_E3_DBSCHQOS41         0xE6791074U
-#define                                DBSC_E3_DBSCHQOS42         0xE6791078U
-#define                                DBSC_E3_DBSCHQOS43         0xE679107CU
-#define                                DBSC_E3_DBSCHQOS90         0xE67910C0U
-#define                                DBSC_E3_DBSCHQOS91         0xE67910C4U
-#define                                DBSC_E3_DBSCHQOS92         0xE67910C8U
-#define                                DBSC_E3_DBSCHQOS93         0xE67910CCU
-#define                                DBSC_E3_DBSCHQOS130        0xE6791100U
-#define                                DBSC_E3_DBSCHQOS131        0xE6791104U
-#define                                DBSC_E3_DBSCHQOS132        0xE6791108U
-#define                                DBSC_E3_DBSCHQOS133        0xE679110CU
-#define                                DBSC_E3_DBSCHQOS140        0xE6791110U
-#define                                DBSC_E3_DBSCHQOS141        0xE6791114U
-#define                                DBSC_E3_DBSCHQOS142        0xE6791118U
-#define                                DBSC_E3_DBSCHQOS143        0xE679111CU
-#define                                DBSC_E3_DBSCHQOS150        0xE6791120U
-#define                                DBSC_E3_DBSCHQOS151        0xE6791124U
-#define                                DBSC_E3_DBSCHQOS152        0xE6791128U
-#define                                DBSC_E3_DBSCHQOS153        0xE679112CU
-#define                                DBSC_E3_SCFCTST0           0xE6791700U
-#define                                DBSC_E3_SCFCTST1           0xE6791708U
-#define                                DBSC_E3_SCFCTST2           0xE679170CU
-
-/* CPG registers */
-
-#define                                CPG_SRCR4                  0xE61500BCU
-#define                                CPG_PLLECR                 0xE61500D0U
-#define                                CPG_CPGWPR                 0xE6150900U
-#define                                CPG_CPGWPCR                0xE6150904U
-#define                                CPG_SRSTCLR4               0xE6150950U
-
-/* MODE Monitor registers */
-
-#define                                RST_MODEMR                 0xE6160060U
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* BOOT_INIT_DRAM_REGDEF_E3_H */

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h
deleted file mode 100644 (file)
index 2a2e5f8..0000000
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_REGDEF_V3M_H_
-#define BOOT_INIT_DRAM_REGDEF_V3M_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* DBSC registers */
-
-// modified , last 2016.12.08
-
-#define DBSC_V3M_DBSYSCONF0            0xE6790000U
-#define DBSC_V3M_DBSYSCONF1            0xE6790004U
-#define DBSC_V3M_DBPHYCONF0            0xE6790010U
-#define DBSC_V3M_DBKIND                        0xE6790020U
-#define DBSC_V3M_DBMEMCONF00           0xE6790030U
-#define DBSC_V3M_DBMEMCONF01           0xE6790034U
-#define DBSC_V3M_DBMEMCONF02           0xE6790038U
-#define DBSC_V3M_DBMEMCONF03           0xE679003CU
-#define DBSC_V3M_DBMEMCONF10           0xE6790040U
-#define DBSC_V3M_DBMEMCONF11           0xE6790044U
-#define DBSC_V3M_DBMEMCONF12           0xE6790048U
-#define DBSC_V3M_DBMEMCONF13           0xE679004CU
-#define DBSC_V3M_DBMEMCONF20           0xE6790050U
-#define DBSC_V3M_DBMEMCONF21           0xE6790054U
-#define DBSC_V3M_DBMEMCONF22           0xE6790058U
-#define DBSC_V3M_DBMEMCONF23           0xE679005CU
-#define DBSC_V3M_DBMEMCONF30           0xE6790060U
-#define DBSC_V3M_DBMEMCONF31           0xE6790064U
-#define DBSC_V3M_DBMEMCONF32           0xE6790068U
-#define DBSC_V3M_DBMEMCONF33           0xE679006CU
-#define DBSC_V3M_DBSYSCNT0             0xE6790100U
-#define DBSC_V3M_DBSVCR1               0xE6790104U
-#define DBSC_V3M_DBSTATE0              0xE6790108U
-#define DBSC_V3M_DBSTATE1              0xE679010CU
-#define DBSC_V3M_DBINTEN               0xE6790180U
-#define DBSC_V3M_DBINTSTAT0            0xE6790184U
-#define DBSC_V3M_DBACEN                        0xE6790200U
-#define DBSC_V3M_DBRFEN                        0xE6790204U
-#define DBSC_V3M_DBCMD                 0xE6790208U
-#define DBSC_V3M_DBWAIT                        0xE6790210U
-#define DBSC_V3M_DBSYSCTRL0            0xE6790280U
-#define DBSC_V3M_DBTR0                 0xE6790300U
-#define DBSC_V3M_DBTR1                 0xE6790304U
-#define DBSC_V3M_DBTR2                 0xE6790308U
-#define DBSC_V3M_DBTR3                 0xE679030CU
-#define DBSC_V3M_DBTR4                 0xE6790310U
-#define DBSC_V3M_DBTR5                 0xE6790314U
-#define DBSC_V3M_DBTR6                 0xE6790318U
-#define DBSC_V3M_DBTR7                 0xE679031CU
-#define DBSC_V3M_DBTR8                 0xE6790320U
-#define DBSC_V3M_DBTR9                 0xE6790324U
-#define DBSC_V3M_DBTR10                        0xE6790328U
-#define DBSC_V3M_DBTR11                        0xE679032CU
-#define DBSC_V3M_DBTR12                        0xE6790330U
-#define DBSC_V3M_DBTR13                        0xE6790334U
-#define DBSC_V3M_DBTR14                        0xE6790338U
-#define DBSC_V3M_DBTR15                        0xE679033CU
-#define DBSC_V3M_DBTR16                        0xE6790340U
-#define DBSC_V3M_DBTR17                        0xE6790344U
-#define DBSC_V3M_DBTR18                        0xE6790348U
-#define DBSC_V3M_DBTR19                        0xE679034CU
-#define DBSC_V3M_DBTR20                        0xE6790350U
-#define DBSC_V3M_DBTR21                        0xE6790354U
-#define DBSC_V3M_DBTR22                        0xE6790358U
-#define DBSC_V3M_DBTR23                        0xE679035CU
-#define DBSC_V3M_DBTR24                        0xE6790360U
-#define DBSC_V3M_DBTR25                        0xE6790364U
-#define DBSC_V3M_DBBL                  0xE6790400U
-#define DBSC_V3M_DBRFCNF1              0xE6790414U
-#define DBSC_V3M_DBRFCNF2              0xE6790418U
-#define DBSC_V3M_DBTSPCNF              0xE6790420U
-#define DBSC_V3M_DBCALCNF              0xE6790424U
-#define DBSC_V3M_DBRNK2                        0xE6790438U
-#define DBSC_V3M_DBRNK3                        0xE679043CU
-#define DBSC_V3M_DBRNK4                        0xE6790440U
-#define DBSC_V3M_DBRNK5                        0xE6790444U
-#define DBSC_V3M_DBPDNCNF              0xE6790450U
-#define DBSC_V3M_DBODT0                        0xE6790460U
-#define DBSC_V3M_DBODT1                        0xE6790464U
-#define DBSC_V3M_DBODT2                        0xE6790468U
-#define DBSC_V3M_DBODT3                        0xE679046CU
-#define DBSC_V3M_DBODT4                        0xE6790470U
-#define DBSC_V3M_DBODT5                        0xE6790474U
-#define DBSC_V3M_DBODT6                        0xE6790478U
-#define DBSC_V3M_DBODT7                        0xE679047CU
-#define DBSC_V3M_DBADJ0                        0xE6790500U
-#define DBSC_V3M_DBDBICNT              0xE6790518U
-#define DBSC_V3M_DBDFIPMSTRCNF         0xE6790520U
-#define DBSC_V3M_DBDFIPMSTRSTAT                0xE6790524U
-#define DBSC_V3M_DBDFILPCNF            0xE6790528U
-#define DBSC_V3M_DBDFICUPDCNF          0xE679052CU
-#define DBSC_V3M_DBDFISTAT0            0xE6790600U
-#define DBSC_V3M_DBDFICNT0             0xE6790604U
-#define DBSC_V3M_DBPDCNT00             0xE6790610U
-#define DBSC_V3M_DBPDCNT01             0xE6790614U
-#define DBSC_V3M_DBPDCNT02             0xE6790618U
-#define DBSC_V3M_DBPDCNT03             0xE679061CU
-#define DBSC_V3M_DBPDLK0               0xE6790620U
-#define DBSC_V3M_DBPDRGA0              0xE6790624U
-#define DBSC_V3M_DBPDRGD0              0xE6790628U
-#define DBSC_V3M_DBPDSTAT00            0xE6790630U
-#define DBSC_V3M_DBDFISTAT1            0xE6790640U
-#define DBSC_V3M_DBDFICNT1             0xE6790644U
-#define DBSC_V3M_DBPDCNT10             0xE6790650U
-#define DBSC_V3M_DBPDCNT11             0xE6790654U
-#define DBSC_V3M_DBPDCNT12             0xE6790658U
-#define DBSC_V3M_DBPDCNT13             0xE679065CU
-#define DBSC_V3M_DBPDLK1               0xE6790660U
-#define DBSC_V3M_DBPDRGA1              0xE6790664U
-#define DBSC_V3M_DBPDRGD1              0xE6790668U
-#define DBSC_V3M_DBPDSTAT10            0xE6790670U
-#define DBSC_V3M_DBDFISTAT2            0xE6790680U
-#define DBSC_V3M_DBDFICNT2             0xE6790684U
-#define DBSC_V3M_DBPDCNT20             0xE6790690U
-#define DBSC_V3M_DBPDCNT21             0xE6790694U
-#define DBSC_V3M_DBPDCNT22             0xE6790698U
-#define DBSC_V3M_DBPDCNT23             0xE679069CU
-#define DBSC_V3M_DBPDLK2               0xE67906A0U
-#define DBSC_V3M_DBPDRGA2              0xE67906A4U
-#define DBSC_V3M_DBPDRGD2              0xE67906A8U
-#define DBSC_V3M_DBPDSTAT20            0xE67906B0U
-#define DBSC_V3M_DBDFISTAT3            0xE67906C0U
-#define DBSC_V3M_DBDFICNT3             0xE67906C4U
-#define DBSC_V3M_DBPDCNT30             0xE67906D0U
-#define DBSC_V3M_DBPDCNT31             0xE67906D4U
-#define DBSC_V3M_DBPDCNT32             0xE67906D8U
-#define DBSC_V3M_DBPDCNT33             0xE67906DCU
-#define DBSC_V3M_DBPDLK3               0xE67906E0U
-#define DBSC_V3M_DBPDRGA3              0xE67906E4U
-#define DBSC_V3M_DBPDRGD3              0xE67906E8U
-#define DBSC_V3M_DBPDSTAT30            0xE67906F0U
-#define DBSC_V3M_DBBUS0CNF0            0xE6790800U
-#define DBSC_V3M_DBBUS0CNF1            0xE6790804U
-#define DBSC_V3M_DBCAM0CNF1            0xE6790904U
-#define DBSC_V3M_DBCAM0CNF2            0xE6790908U
-#define DBSC_V3M_DBCAM0CNF3            0xE679090CU
-#define DBSC_V3M_DBCAM0CTRL0           0xE6790940U
-#define DBSC_V3M_DBCAM0STAT0           0xE6790980U
-#define DBSC_V3M_DBCAM1STAT0           0xE6790990U
-#define DBSC_V3M_DBBCAMSWAP            0xE67909F0U
-#define DBSC_V3M_DBBCAMDIS             0xE67909FCU
-#define DBSC_V3M_DBSCHCNT0             0xE6791000U
-#define DBSC_V3M_DBSCHCNT1             0xE6791004U
-#define DBSC_V3M_DBSCHSZ0              0xE6791010U
-#define DBSC_V3M_DBSCHRW0              0xE6791020U
-#define DBSC_V3M_DBSCHRW1              0xE6791024U
-#define DBSC_V3M_DBSCHQOS00            0xE6791030U
-#define DBSC_V3M_DBSCHQOS01            0xE6791034U
-#define DBSC_V3M_DBSCHQOS02            0xE6791038U
-#define DBSC_V3M_DBSCHQOS03            0xE679103CU
-#define DBSC_V3M_DBSCHQOS10            0xE6791040U
-#define DBSC_V3M_DBSCHQOS11            0xE6791044U
-#define DBSC_V3M_DBSCHQOS12            0xE6791048U
-#define DBSC_V3M_DBSCHQOS13            0xE679104CU
-#define DBSC_V3M_DBSCHQOS20            0xE6791050U
-#define DBSC_V3M_DBSCHQOS21            0xE6791054U
-#define DBSC_V3M_DBSCHQOS22            0xE6791058U
-#define DBSC_V3M_DBSCHQOS23            0xE679105CU
-#define DBSC_V3M_DBSCHQOS30            0xE6791060U
-#define DBSC_V3M_DBSCHQOS31            0xE6791064U
-#define DBSC_V3M_DBSCHQOS32            0xE6791068U
-#define DBSC_V3M_DBSCHQOS33            0xE679106CU
-#define DBSC_V3M_DBSCHQOS40            0xE6791070U
-#define DBSC_V3M_DBSCHQOS41            0xE6791074U
-#define DBSC_V3M_DBSCHQOS42            0xE6791078U
-#define DBSC_V3M_DBSCHQOS43            0xE679107CU
-#define DBSC_V3M_DBSCHQOS50            0xE6791080U
-#define DBSC_V3M_DBSCHQOS51            0xE6791084U
-#define DBSC_V3M_DBSCHQOS52            0xE6791088U
-#define DBSC_V3M_DBSCHQOS53            0xE679108CU
-#define DBSC_V3M_DBSCHQOS60            0xE6791090U
-#define DBSC_V3M_DBSCHQOS61            0xE6791094U
-#define DBSC_V3M_DBSCHQOS62            0xE6791098U
-#define DBSC_V3M_DBSCHQOS63            0xE679109CU
-#define DBSC_V3M_DBSCHQOS70            0xE67910A0U
-#define DBSC_V3M_DBSCHQOS71            0xE67910A4U
-#define DBSC_V3M_DBSCHQOS72            0xE67910A8U
-#define DBSC_V3M_DBSCHQOS73            0xE67910ACU
-#define DBSC_V3M_DBSCHQOS80            0xE67910B0U
-#define DBSC_V3M_DBSCHQOS81            0xE67910B4U
-#define DBSC_V3M_DBSCHQOS82            0xE67910B8U
-#define DBSC_V3M_DBSCHQOS83            0xE67910BCU
-#define DBSC_V3M_DBSCHQOS90            0xE67910C0U
-#define DBSC_V3M_DBSCHQOS91            0xE67910C4U
-#define DBSC_V3M_DBSCHQOS92            0xE67910C8U
-#define DBSC_V3M_DBSCHQOS93            0xE67910CCU
-#define DBSC_V3M_DBSCHQOS100           0xE67910D0U
-#define DBSC_V3M_DBSCHQOS101           0xE67910D4U
-#define DBSC_V3M_DBSCHQOS102           0xE67910D8U
-#define DBSC_V3M_DBSCHQOS103           0xE67910DCU
-#define DBSC_V3M_DBSCHQOS110           0xE67910E0U
-#define DBSC_V3M_DBSCHQOS111           0xE67910E4U
-#define DBSC_V3M_DBSCHQOS112           0xE67910E8U
-#define DBSC_V3M_DBSCHQOS113           0xE67910ECU
-#define DBSC_V3M_DBSCHQOS120           0xE67910F0U
-#define DBSC_V3M_DBSCHQOS121           0xE67910F4U
-#define DBSC_V3M_DBSCHQOS122           0xE67910F8U
-#define DBSC_V3M_DBSCHQOS123           0xE67910FCU
-#define DBSC_V3M_DBSCHQOS130           0xE6791100U
-#define DBSC_V3M_DBSCHQOS131           0xE6791104U
-#define DBSC_V3M_DBSCHQOS132           0xE6791108U
-#define DBSC_V3M_DBSCHQOS133           0xE679110CU
-#define DBSC_V3M_DBSCHQOS140           0xE6791110U
-#define DBSC_V3M_DBSCHQOS141           0xE6791114U
-#define DBSC_V3M_DBSCHQOS142           0xE6791118U
-#define DBSC_V3M_DBSCHQOS143           0xE679111CU
-#define DBSC_V3M_DBSCHQOS150           0xE6791120U
-#define DBSC_V3M_DBSCHQOS151           0xE6791124U
-#define DBSC_V3M_DBSCHQOS152           0xE6791128U
-#define DBSC_V3M_DBSCHQOS153           0xE679112CU
-#define DBSC_V3M_SCFCTST0              0xE6791700U
-#define DBSC_V3M_SCFCTST1              0xE6791708U
-#define DBSC_V3M_SCFCTST2              0xE679170CU
-#define DBSC_V3M_DBMRRDR0              0xE6791800U
-#define DBSC_V3M_DBMRRDR1              0xE6791804U
-#define DBSC_V3M_DBMRRDR2              0xE6791808U
-#define DBSC_V3M_DBMRRDR3              0xE679180CU
-#define DBSC_V3M_DBMRRDR4              0xE6791810U
-#define DBSC_V3M_DBMRRDR5              0xE6791814U
-#define DBSC_V3M_DBMRRDR6              0xE6791818U
-#define DBSC_V3M_DBMRRDR7              0xE679181CU
-#define DBSC_V3M_DBDTMP0               0xE6791820U
-#define DBSC_V3M_DBDTMP1               0xE6791824U
-#define DBSC_V3M_DBDTMP2               0xE6791828U
-#define DBSC_V3M_DBDTMP3               0xE679182CU
-#define DBSC_V3M_DBDTMP4               0xE6791830U
-#define DBSC_V3M_DBDTMP5               0xE6791834U
-#define DBSC_V3M_DBDTMP6               0xE6791838U
-#define DBSC_V3M_DBDTMP7               0xE679183CU
-#define DBSC_V3M_DBDQSOSC00            0xE6791840U
-#define DBSC_V3M_DBDQSOSC01            0xE6791844U
-#define DBSC_V3M_DBDQSOSC10            0xE6791848U
-#define DBSC_V3M_DBDQSOSC11            0xE679184CU
-#define DBSC_V3M_DBDQSOSC20            0xE6791850U
-#define DBSC_V3M_DBDQSOSC21            0xE6791854U
-#define DBSC_V3M_DBDQSOSC30            0xE6791858U
-#define DBSC_V3M_DBDQSOSC31            0xE679185CU
-#define DBSC_V3M_DBDQSOSC40            0xE6791860U
-#define DBSC_V3M_DBDQSOSC41            0xE6791864U
-#define DBSC_V3M_DBDQSOSC50            0xE6791868U
-#define DBSC_V3M_DBDQSOSC51            0xE679186CU
-#define DBSC_V3M_DBDQSOSC60            0xE6791870U
-#define DBSC_V3M_DBDQSOSC61            0xE6791874U
-#define DBSC_V3M_DBDQSOSC70            0xE6791878U
-#define DBSC_V3M_DBDQSOSC71            0xE679187CU
-#define DBSC_V3M_DBOSCTHH00            0xE6791880U
-#define DBSC_V3M_DBOSCTHH01            0xE6791884U
-#define DBSC_V3M_DBOSCTHH10            0xE6791888U
-#define DBSC_V3M_DBOSCTHH11            0xE679188CU
-#define DBSC_V3M_DBOSCTHH20            0xE6791890U
-#define DBSC_V3M_DBOSCTHH21            0xE6791894U
-#define DBSC_V3M_DBOSCTHH30            0xE6791898U
-#define DBSC_V3M_DBOSCTHH31            0xE679189CU
-#define DBSC_V3M_DBOSCTHH40            0xE67918A0U
-#define DBSC_V3M_DBOSCTHH41            0xE67918A4U
-#define DBSC_V3M_DBOSCTHH50            0xE67918A8U
-#define DBSC_V3M_DBOSCTHH51            0xE67918ACU
-#define DBSC_V3M_DBOSCTHH60            0xE67918B0U
-#define DBSC_V3M_DBOSCTHH61            0xE67918B4U
-#define DBSC_V3M_DBOSCTHH70            0xE67918B8U
-#define DBSC_V3M_DBOSCTHH71            0xE67918BCU
-#define DBSC_V3M_DBOSCTHL00            0xE67918C0U
-#define DBSC_V3M_DBOSCTHL01            0xE67918C4U
-#define DBSC_V3M_DBOSCTHL10            0xE67918C8U
-#define DBSC_V3M_DBOSCTHL11            0xE67918CCU
-#define DBSC_V3M_DBOSCTHL20            0xE67918D0U
-#define DBSC_V3M_DBOSCTHL21            0xE67918D4U
-#define DBSC_V3M_DBOSCTHL30            0xE67918D8U
-#define DBSC_V3M_DBOSCTHL31            0xE67918DCU
-#define DBSC_V3M_DBOSCTHL40            0xE67918E0U
-#define DBSC_V3M_DBOSCTHL41            0xE67918E4U
-#define DBSC_V3M_DBOSCTHL50            0xE67918E8U
-#define DBSC_V3M_DBOSCTHL51            0xE67918ECU
-#define DBSC_V3M_DBOSCTHL60            0xE67918F0U
-#define DBSC_V3M_DBOSCTHL61            0xE67918F4U
-#define DBSC_V3M_DBOSCTHL70            0xE67918F8U
-#define DBSC_V3M_DBOSCTHL71            0xE67918FCU
-#define DBSC_V3M_DBMEMSWAPCONF0                0xE6792000U
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* BOOT_INIT_DRAM_REGDEF_V3M_H_*/

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
index d79d57f6cb9e7e4f2f3369b13578651de245ccbf..516f6be2733641d093bb982ee2b0c2de201aaa8c 100644 (file)
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
@@ -8,7 +8,7 @@
 #include <lib/mmio.h>
 #include <common/debug.h>
 
-#include "boot_init_dram_regdef_d3.h"
+#include "boot_init_dram_regdef.h"
 
 #define RCAR_DDR_VERSION    "rev.0.01"
 
@@ -31,314 +31,314 @@ static void init_ddr_d3_1866(void)
 {
        uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
 
-   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
-   WriteReg_32(DBSC_D3_DBKIND,0x00000007);
-   WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
-   WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
-   WriteReg_32(DBSC_D3_DBTR0,0x0000000D);
-   WriteReg_32(DBSC_D3_DBTR1,0x00000009);
-   WriteReg_32(DBSC_D3_DBTR2,0x00000000);
-   WriteReg_32(DBSC_D3_DBTR3,0x0000000D);
-   WriteReg_32(DBSC_D3_DBTR4,0x000D000D);
-   WriteReg_32(DBSC_D3_DBTR5,0x0000002D);
-   WriteReg_32(DBSC_D3_DBTR6,0x00000020);
-   WriteReg_32(DBSC_D3_DBTR7,0x00060006);
-   WriteReg_32(DBSC_D3_DBTR8,0x00000021);
-   WriteReg_32(DBSC_D3_DBTR9,0x00000007);
-   WriteReg_32(DBSC_D3_DBTR10,0x0000000E);
-   WriteReg_32(DBSC_D3_DBTR11,0x0000000C);
-   WriteReg_32(DBSC_D3_DBTR12,0x00140014);
-   WriteReg_32(DBSC_D3_DBTR13,0x000000F2);
-   WriteReg_32(DBSC_D3_DBTR14,0x00170006);
-   WriteReg_32(DBSC_D3_DBTR15,0x00060005);
-   WriteReg_32(DBSC_D3_DBTR16,0x09210507);
-   WriteReg_32(DBSC_D3_DBTR17,0x040E0000);
-   WriteReg_32(DBSC_D3_DBTR18,0x00000200);
-   WriteReg_32(DBSC_D3_DBTR19,0x012B004B);
-   WriteReg_32(DBSC_D3_DBTR20,0x020000FB);
-   WriteReg_32(DBSC_D3_DBTR21,0x00040004);
-   WriteReg_32(DBSC_D3_DBBL,0x00000000);
-   WriteReg_32(DBSC_D3_DBODT0,0x00000001);
-   WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
-   WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
-   WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
-   WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
-   WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
-   WriteReg_32(DBSC_D3_SCFCTST0,0x0D020D04);
-   WriteReg_32(DBSC_D3_SCFCTST1,0x0306040C);
-
-   WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
-   WriteReg_32(DBSC_D3_DBCMD,0x01000001);
-   WriteReg_32(DBSC_D3_DBCMD,0x08000000);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A04);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058A00);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
-   while ( (BIT(30) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0A206F89);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x35A00D77);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x2A8A2C28);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x30005E00);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0014CB49);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000F14);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x000000A0);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
-   RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
+   WriteReg_32(DBSC_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_DBKIND,0x00000007);
+   WriteReg_32(DBSC_DBMEMCONF00,0x0f030a01);
+   WriteReg_32(DBSC_DBPHYCONF0,0x00000001);
+   WriteReg_32(DBSC_DBTR0,0x0000000D);
+   WriteReg_32(DBSC_DBTR1,0x00000009);
+   WriteReg_32(DBSC_DBTR2,0x00000000);
+   WriteReg_32(DBSC_DBTR3,0x0000000D);
+   WriteReg_32(DBSC_DBTR4,0x000D000D);
+   WriteReg_32(DBSC_DBTR5,0x0000002D);
+   WriteReg_32(DBSC_DBTR6,0x00000020);
+   WriteReg_32(DBSC_DBTR7,0x00060006);
+   WriteReg_32(DBSC_DBTR8,0x00000021);
+   WriteReg_32(DBSC_DBTR9,0x00000007);
+   WriteReg_32(DBSC_DBTR10,0x0000000E);
+   WriteReg_32(DBSC_DBTR11,0x0000000C);
+   WriteReg_32(DBSC_DBTR12,0x00140014);
+   WriteReg_32(DBSC_DBTR13,0x000000F2);
+   WriteReg_32(DBSC_DBTR14,0x00170006);
+   WriteReg_32(DBSC_DBTR15,0x00060005);
+   WriteReg_32(DBSC_DBTR16,0x09210507);
+   WriteReg_32(DBSC_DBTR17,0x040E0000);
+   WriteReg_32(DBSC_DBTR18,0x00000200);
+   WriteReg_32(DBSC_DBTR19,0x012B004B);
+   WriteReg_32(DBSC_DBTR20,0x020000FB);
+   WriteReg_32(DBSC_DBTR21,0x00040004);
+   WriteReg_32(DBSC_DBBL,0x00000000);
+   WriteReg_32(DBSC_DBODT0,0x00000001);
+   WriteReg_32(DBSC_DBADJ0,0x00000001);
+   WriteReg_32(DBSC_DBSYSCONF1,0x00000002);
+   WriteReg_32(DBSC_DBDFICNT0,0x00000010);
+   WriteReg_32(DBSC_DBBCAMDIS,0x00000001);
+   WriteReg_32(DBSC_DBSCHRW1,0x00000046);
+   WriteReg_32(DBSC_SCFCTST0,0x0D020D04);
+   WriteReg_32(DBSC_SCFCTST1,0x0306040C);
+
+   WriteReg_32(DBSC_DBPDLK0,0x0000A55A);
+   WriteReg_32(DBSC_DBCMD,0x01000001);
+   WriteReg_32(DBSC_DBCMD,0x08000000);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x80010000);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000008);
+   WriteReg_32(DBSC_DBPDRGD0,0x000B8000);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0x04058A04);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000091);
+   WriteReg_32(DBSC_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000095);
+   WriteReg_32(DBSC_DBPDRGD0,0x0007BBAD);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000099);
+   WriteReg_32(DBSC_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0x04058A00);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_DBPDRGD0,0x0024641E);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010073);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0x0C058A00);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0x04058A00);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_DBPDRGD0,0x0780C700);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000007);
+   while ( (BIT(30) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000004);
+   WriteReg_32(DBSC_DBPDRGD0,0x0A206F89);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000022);
+   WriteReg_32(DBSC_DBPDRGD0,0x1000040B);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000023);
+   WriteReg_32(DBSC_DBPDRGD0,0x35A00D77);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000024);
+   WriteReg_32(DBSC_DBPDRGD0,0x2A8A2C28);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000025);
+   WriteReg_32(DBSC_DBPDRGD0,0x30005E00);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000026);
+   WriteReg_32(DBSC_DBPDRGD0,0x0014CB49);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000027);
+   WriteReg_32(DBSC_DBPDRGD0,0x00000F14);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000028);
+   WriteReg_32(DBSC_DBPDRGD0,0x00000046);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000029);
+   WriteReg_32(DBSC_DBPDRGD0,0x000000A0);
+   WriteReg_32(DBSC_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_DBPDRGD0,0x81003047);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000020);
+   WriteReg_32(DBSC_DBPDRGD0,0x00181884);
+   WriteReg_32(DBSC_DBPDRGA0,0x0000001A);
+   WriteReg_32(DBSC_DBPDRGD0,0x33C03C10);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A7);
+   WriteReg_32(DBSC_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A8);
+   WriteReg_32(DBSC_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A9);
+   WriteReg_32(DBSC_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C7);
+   WriteReg_32(DBSC_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C8);
+   WriteReg_32(DBSC_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C9);
+   WriteReg_32(DBSC_DBPDRGD0,0x000D0D0D);
+
+   WriteReg_32(DBSC_DBPDRGA0,0x0000000E);
+   RegVal_R2 = ((ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
    RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
    RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
-   WriteReg_32(DBSC_D3_DBCMD,0x08000001);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0x00000011);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R3);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000012);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R3);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000016);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000017);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000018);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000019);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R6);
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010181);
+   WriteReg_32(DBSC_DBCMD,0x08000001);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010601);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
    for (uint32_t i = 0; i<2; i++)
    {
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
-      RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
-      RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
-      RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8;
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
       if ( RegVal_R6 > 0 )
       {
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
-
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | RegVal_R6);
       } else
       {
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
-
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | RegVal_R7);
+
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
       }
    }
 
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
-   RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
-   RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_DBPDRGD0,0xC1AA00C0);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010801);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_DBPDRGD0,0xC1AA00D8);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x0001F001);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x000000AF);
+   RegVal_R2 = ReadReg_32(DBSC_DBPDRGD0);
+   WriteReg_32(DBSC_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+   WriteReg_32(DBSC_DBPDRGA0,0x000000CF);
+   RegVal_R2 = ReadReg_32(DBSC_DBPDRGD0);
+   WriteReg_32(DBSC_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_DBPDRGD0,0x81003087);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010401);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
    for (uint32_t i = 0; i < 2; i++)
    {
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
-      RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
-      RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = ((ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
 
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
-      RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
       RegVal_R12 = (RegVal_R5 >> 0x2);
       if ( RegVal_R12 < RegVal_R6 )
       {
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
 
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
 
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
       }
       else
       {
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
       }
    }
 
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
-   while ( (BIT(30) & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
-
-   WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
-   WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
-   WriteReg_32(DBSC_D3_DBRFCNF1,0x00080E23);
-   WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
-   WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
-   WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
-   WriteReg_32(DBSC_D3_DBACEN,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
-   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00015001);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_DBPDRGD0,0x0380C700);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000007);
+   while ( (BIT(30) & ReadReg_32(DBSC_DBPDRGD0)) != 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_DBPDRGD0,0x0024643E);
+
+   WriteReg_32(DBSC_DBBUS0CNF1,0x00000010);
+   WriteReg_32(DBSC_DBCALCNF,0x0100401B);
+   WriteReg_32(DBSC_DBRFCNF1,0x00080E23);
+   WriteReg_32(DBSC_DBRFCNF2,0x00010000);
+   WriteReg_32(DBSC_DBDFICUPDCNF,0x40100001);
+   WriteReg_32(DBSC_DBRFEN,0x00000001);
+   WriteReg_32(DBSC_DBACEN,0x00000001);
+   WriteReg_32(DBSC_DBPDLK0,0x00000000);
+   WriteReg_32(DBSC_DBSYSCNT0,0x00000000);
 
 #ifdef ddr_qos_init_setting // only for non qos_init
-   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
-   WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
-   WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
-   WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
-   WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
-   WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
-   WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
-   WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
-   WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
-   WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
-   WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
-   WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
-   WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
-   WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
-   WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
-   WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
-   WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
-   WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
-   WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
-   WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
-   WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
-   WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
-   WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
-   WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
-   WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
-   WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
-   WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
-   WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
-   WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
-   WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
-   WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
+   WriteReg_32(DBSC_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_DBCAM0CNF1,0x00043218);
+   WriteReg_32(DBSC_DBCAM0CNF2,0x000000F4);
+   WriteReg_32(DBSC_DBSCHCNT0,0x000f0037);
+   WriteReg_32(DBSC_DBSCHSZ0,0x00000001);
+   WriteReg_32(DBSC_DBSCHRW0,0x22421111);
+   WriteReg_32(DBSC_SCFCTST2,0x012F1123);
+   WriteReg_32(DBSC_DBSCHQOS00,0x00000F00);
+   WriteReg_32(DBSC_DBSCHQOS01,0x00000B00);
+   WriteReg_32(DBSC_DBSCHQOS02,0x00000000);
+   WriteReg_32(DBSC_DBSCHQOS03,0x00000000);
+   WriteReg_32(DBSC_DBSCHQOS40,0x00000300);
+   WriteReg_32(DBSC_DBSCHQOS41,0x000002F0);
+   WriteReg_32(DBSC_DBSCHQOS42,0x00000200);
+   WriteReg_32(DBSC_DBSCHQOS43,0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS90,0x00000300);
+   WriteReg_32(DBSC_DBSCHQOS91,0x000002F0);
+   WriteReg_32(DBSC_DBSCHQOS92,0x00000200);
+   WriteReg_32(DBSC_DBSCHQOS93,0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS130,0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS131,0x000000F0);
+   WriteReg_32(DBSC_DBSCHQOS132,0x000000A0);
+   WriteReg_32(DBSC_DBSCHQOS133,0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS140,0x000000C0);
+   WriteReg_32(DBSC_DBSCHQOS141,0x000000B0);
+   WriteReg_32(DBSC_DBSCHQOS142,0x00000080);
+   WriteReg_32(DBSC_DBSCHQOS143,0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS150,0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS151,0x00000030);
+   WriteReg_32(DBSC_DBSCHQOS152,0x00000020);
+   WriteReg_32(DBSC_DBSCHQOS153,0x00000010);
    WriteReg_32(0xE67F0018,0x00000001);
-   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+   WriteReg_32(DBSC_DBSYSCNT0,0x00000000);
 #endif
 }
 
@@ -346,313 +346,313 @@ static void init_ddr_d3_1600(void)
 {
        uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
 
-   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
-   WriteReg_32(DBSC_D3_DBKIND,0x00000007);
-   WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
-   WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
-   WriteReg_32(DBSC_D3_DBTR0,0x0000000B);
-   WriteReg_32(DBSC_D3_DBTR1,0x00000008);
-   WriteReg_32(DBSC_D3_DBTR2,0x00000000);
-   WriteReg_32(DBSC_D3_DBTR3,0x0000000B);
-   WriteReg_32(DBSC_D3_DBTR4,0x000B000B);
-   WriteReg_32(DBSC_D3_DBTR5,0x00000027);
-   WriteReg_32(DBSC_D3_DBTR6,0x0000001C);
-   WriteReg_32(DBSC_D3_DBTR7,0x00060006);
-   WriteReg_32(DBSC_D3_DBTR8,0x00000020);
-   WriteReg_32(DBSC_D3_DBTR9,0x00000006);
-   WriteReg_32(DBSC_D3_DBTR10,0x0000000C);
-   WriteReg_32(DBSC_D3_DBTR11,0x0000000A);
-   WriteReg_32(DBSC_D3_DBTR12,0x00120012);
-   WriteReg_32(DBSC_D3_DBTR13,0x000000D0);
-   WriteReg_32(DBSC_D3_DBTR14,0x00140005);
-   WriteReg_32(DBSC_D3_DBTR15,0x00050004);
-   WriteReg_32(DBSC_D3_DBTR16,0x071F0305);
-   WriteReg_32(DBSC_D3_DBTR17,0x040C0000);
-   WriteReg_32(DBSC_D3_DBTR18,0x00000200);
-   WriteReg_32(DBSC_D3_DBTR19,0x01000040);
-   WriteReg_32(DBSC_D3_DBTR20,0x020000D8);
-   WriteReg_32(DBSC_D3_DBTR21,0x00040004);
-   WriteReg_32(DBSC_D3_DBBL,0x00000000);
-   WriteReg_32(DBSC_D3_DBODT0,0x00000001);
-   WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
-   WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
-   WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
-   WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
-   WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
-   WriteReg_32(DBSC_D3_SCFCTST0,0x0D020C04);
-   WriteReg_32(DBSC_D3_SCFCTST1,0x0305040C);
-
-   WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
-   WriteReg_32(DBSC_D3_DBCMD,0x01000001);
-   WriteReg_32(DBSC_D3_DBCMD,0x08000000);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058904);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058900);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
-   while ( (BIT(30) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x08C05FF0);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x2D9C0B66);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x2A88C400);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x30005200);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0014A9C9);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000D70);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00000098);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
-   RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
+   WriteReg_32(DBSC_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_DBKIND,0x00000007);
+   WriteReg_32(DBSC_DBMEMCONF00,0x0f030a01);
+   WriteReg_32(DBSC_DBPHYCONF0,0x00000001);
+   WriteReg_32(DBSC_DBTR0,0x0000000B);
+   WriteReg_32(DBSC_DBTR1,0x00000008);
+   WriteReg_32(DBSC_DBTR2,0x00000000);
+   WriteReg_32(DBSC_DBTR3,0x0000000B);
+   WriteReg_32(DBSC_DBTR4,0x000B000B);
+   WriteReg_32(DBSC_DBTR5,0x00000027);
+   WriteReg_32(DBSC_DBTR6,0x0000001C);
+   WriteReg_32(DBSC_DBTR7,0x00060006);
+   WriteReg_32(DBSC_DBTR8,0x00000020);
+   WriteReg_32(DBSC_DBTR9,0x00000006);
+   WriteReg_32(DBSC_DBTR10,0x0000000C);
+   WriteReg_32(DBSC_DBTR11,0x0000000A);
+   WriteReg_32(DBSC_DBTR12,0x00120012);
+   WriteReg_32(DBSC_DBTR13,0x000000D0);
+   WriteReg_32(DBSC_DBTR14,0x00140005);
+   WriteReg_32(DBSC_DBTR15,0x00050004);
+   WriteReg_32(DBSC_DBTR16,0x071F0305);
+   WriteReg_32(DBSC_DBTR17,0x040C0000);
+   WriteReg_32(DBSC_DBTR18,0x00000200);
+   WriteReg_32(DBSC_DBTR19,0x01000040);
+   WriteReg_32(DBSC_DBTR20,0x020000D8);
+   WriteReg_32(DBSC_DBTR21,0x00040004);
+   WriteReg_32(DBSC_DBBL,0x00000000);
+   WriteReg_32(DBSC_DBODT0,0x00000001);
+   WriteReg_32(DBSC_DBADJ0,0x00000001);
+   WriteReg_32(DBSC_DBSYSCONF1,0x00000002);
+   WriteReg_32(DBSC_DBDFICNT0,0x00000010);
+   WriteReg_32(DBSC_DBBCAMDIS,0x00000001);
+   WriteReg_32(DBSC_DBSCHRW1,0x00000046);
+   WriteReg_32(DBSC_SCFCTST0,0x0D020C04);
+   WriteReg_32(DBSC_SCFCTST1,0x0305040C);
+
+   WriteReg_32(DBSC_DBPDLK0,0x0000A55A);
+   WriteReg_32(DBSC_DBCMD,0x01000001);
+   WriteReg_32(DBSC_DBCMD,0x08000000);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x80010000);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000008);
+   WriteReg_32(DBSC_DBPDRGD0,0x000B8000);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0x04058904);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000091);
+   WriteReg_32(DBSC_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000095);
+   WriteReg_32(DBSC_DBPDRGD0,0x0007BBAD);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000099);
+   WriteReg_32(DBSC_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0x04058900);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_DBPDRGD0,0x0024641E);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010073);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0x0C058900);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0x04058900);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_DBPDRGD0,0x0780C700);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000007);
+   while ( (BIT(30) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000004);
+   WriteReg_32(DBSC_DBPDRGD0,0x08C05FF0);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000022);
+   WriteReg_32(DBSC_DBPDRGD0,0x1000040B);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000023);
+   WriteReg_32(DBSC_DBPDRGD0,0x2D9C0B66);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000024);
+   WriteReg_32(DBSC_DBPDRGD0,0x2A88C400);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000025);
+   WriteReg_32(DBSC_DBPDRGD0,0x30005200);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000026);
+   WriteReg_32(DBSC_DBPDRGD0,0x0014A9C9);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000027);
+   WriteReg_32(DBSC_DBPDRGD0,0x00000D70);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000028);
+   WriteReg_32(DBSC_DBPDRGD0,0x00000046);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000029);
+   WriteReg_32(DBSC_DBPDRGD0,0x00000098);
+   WriteReg_32(DBSC_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_DBPDRGD0,0x81003047);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000020);
+   WriteReg_32(DBSC_DBPDRGD0,0x00181884);
+   WriteReg_32(DBSC_DBPDRGA0,0x0000001A);
+   WriteReg_32(DBSC_DBPDRGD0,0x33C03C10);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A7);
+   WriteReg_32(DBSC_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A8);
+   WriteReg_32(DBSC_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A9);
+   WriteReg_32(DBSC_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C7);
+   WriteReg_32(DBSC_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C8);
+   WriteReg_32(DBSC_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C9);
+   WriteReg_32(DBSC_DBPDRGD0,0x000D0D0D);
+
+   WriteReg_32(DBSC_DBPDRGA0,0x0000000E);
+   RegVal_R2 = ((ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
    RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
    RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
-   WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
-   WriteReg_32(DBSC_D3_DBCMD,0x08000001);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0x00000011);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R3);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000012);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R3);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000016);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000017);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000018);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R6);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000019);
+   WriteReg_32(DBSC_DBPDRGD0,RegVal_R6);
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010181);
+   WriteReg_32(DBSC_DBCMD,0x08000001);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010601);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
    for (uint32_t i = 0; i<2; i++)
    {
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
-      RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
-      RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
-      RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8;
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
       if ( RegVal_R6 > 0 )
       {
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
-
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | RegVal_R6);
       } else
       {
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
-
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | RegVal_R7);
+
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
       }
    }
 
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
-   RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
-   RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_DBPDRGD0,0xC1AA00C0);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010801);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_DBPDRGD0,0xC1AA00D8);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x0001F001);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x000000AF);
+   RegVal_R2 = ReadReg_32(DBSC_DBPDRGD0);
+   WriteReg_32(DBSC_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+   WriteReg_32(DBSC_DBPDRGA0,0x000000CF);
+   RegVal_R2 = ReadReg_32(DBSC_DBPDRGD0);
+   WriteReg_32(DBSC_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
+
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_DBPDRGD0,0x81003087);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00010401);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
    for (uint32_t i = 0; i < 2; i++)
    {
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
-      RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
-      RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = ((ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
 
-      WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
-      RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
+      WriteReg_32(DBSC_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
       RegVal_R12 = (RegVal_R5 >> 0x2);
       if ( RegVal_R12 < RegVal_R6 )
       {
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
 
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
 
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
       }
       else
       {
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
-         WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
       }
    }
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
-
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
-   while ( (BIT(30) & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
-   WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
-   WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
-
-   WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
-   WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
-   WriteReg_32(DBSC_D3_DBRFCNF1,0x00080C30);
-   WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
-   WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
-   WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
-   WriteReg_32(DBSC_D3_DBACEN,0x00000001);
-   WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
-   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0x00015001);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_DBPDRGD0,0x0380C700);
+   WriteReg_32(DBSC_DBPDRGA0,0x00000007);
+   while ( (BIT(30) & ReadReg_32(DBSC_DBPDRGD0)) != 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_DBPDRGD0,0x0024643E);
+
+   WriteReg_32(DBSC_DBBUS0CNF1,0x00000010);
+   WriteReg_32(DBSC_DBCALCNF,0x0100401B);
+   WriteReg_32(DBSC_DBRFCNF1,0x00080C30);
+   WriteReg_32(DBSC_DBRFCNF2,0x00010000);
+   WriteReg_32(DBSC_DBDFICUPDCNF,0x40100001);
+   WriteReg_32(DBSC_DBRFEN,0x00000001);
+   WriteReg_32(DBSC_DBACEN,0x00000001);
+   WriteReg_32(DBSC_DBPDLK0,0x00000000);
+   WriteReg_32(DBSC_DBSYSCNT0,0x00000000);
 
 #ifdef ddr_qos_init_setting // only for non qos_init
-   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
-   WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
-   WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
-   WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
-   WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
-   WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
-   WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
-   WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
-   WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
-   WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
-   WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
-   WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
-   WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
-   WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
-   WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
-   WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
-   WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
-   WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
-   WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
-   WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
-   WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
-   WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
-   WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
-   WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
-   WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
-   WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
-   WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
-   WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
-   WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
-   WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
-   WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
+   WriteReg_32(DBSC_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_DBCAM0CNF1,0x00043218);
+   WriteReg_32(DBSC_DBCAM0CNF2,0x000000F4);
+   WriteReg_32(DBSC_DBSCHCNT0,0x000f0037);
+   WriteReg_32(DBSC_DBSCHSZ0,0x00000001);
+   WriteReg_32(DBSC_DBSCHRW0,0x22421111);
+   WriteReg_32(DBSC_SCFCTST2,0x012F1123);
+   WriteReg_32(DBSC_DBSCHQOS00,0x00000F00);
+   WriteReg_32(DBSC_DBSCHQOS01,0x00000B00);
+   WriteReg_32(DBSC_DBSCHQOS02,0x00000000);
+   WriteReg_32(DBSC_DBSCHQOS03,0x00000000);
+   WriteReg_32(DBSC_DBSCHQOS40,0x00000300);
+   WriteReg_32(DBSC_DBSCHQOS41,0x000002F0);
+   WriteReg_32(DBSC_DBSCHQOS42,0x00000200);
+   WriteReg_32(DBSC_DBSCHQOS43,0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS90,0x00000300);
+   WriteReg_32(DBSC_DBSCHQOS91,0x000002F0);
+   WriteReg_32(DBSC_DBSCHQOS92,0x00000200);
+   WriteReg_32(DBSC_DBSCHQOS93,0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS130,0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS131,0x000000F0);
+   WriteReg_32(DBSC_DBSCHQOS132,0x000000A0);
+   WriteReg_32(DBSC_DBSCHQOS133,0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS140,0x000000C0);
+   WriteReg_32(DBSC_DBSCHQOS141,0x000000B0);
+   WriteReg_32(DBSC_DBSCHQOS142,0x00000080);
+   WriteReg_32(DBSC_DBSCHQOS143,0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS150,0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS151,0x00000030);
+   WriteReg_32(DBSC_DBSCHQOS152,0x00000020);
+   WriteReg_32(DBSC_DBSCHQOS153,0x00000010);
    WriteReg_32(0xE67F0018,0x00000001);
-   WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
+   WriteReg_32(DBSC_DBSYSCNT0,0x00000000);
 #endif
 }
 
@@ -660,7 +660,6 @@ static void init_ddr_d3_1600(void)
 #define PRR_PRODUCT_MASK       (0x00007F00U)
 #define PRR_PRODUCT_D3         (0x00005800U)
 
-#define        RST_MODEMR              (0xE6160060)
 #define        MODEMR_MD19             (0x00080000U)
 
 int32_t rcar_dram_init(void)

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
index b5de3d5d8a4bb053b1101f9b214c0d6d9169b71b..59919a491f540f9cdd985714ceac398c093b9905 100644 (file)
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
@@ -8,7 +8,7 @@
 
 #include <common/debug.h>
 
-#include "boot_init_dram_regdef_e3.h"
+#include "boot_init_dram_regdef.h"
 #include "ddr_init_e3.h"
 
 #include "../dram_sub_func.h"
@@ -95,13 +95,13 @@ uint32_t init_ddr(void)
       /* CPG setting ===============================================*/
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
-   WriteReg_32(DBSC_E3_DBKIND, 0x00000007);
+   WriteReg_32(DBSC_DBSYSCNT0, 0x00001234);
+   WriteReg_32(DBSC_DBKIND, 0x00000007);
 
 #if RCAR_DRAM_DDR3L_MEMCONF == 0
-   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /*  1GB */
+   WriteReg_32(DBSC_DBMEMCONF00, 0x0f030a02); /*  1GB */
 #else
-   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /*  2GB(default) */
+   WriteReg_32(DBSC_DBMEMCONF00, 0x10030a02); /*  2GB(default) */
 #endif
 
 #if RCAR_DRAM_DDR3L_MEMDUAL == 1
@@ -110,321 +110,321 @@ uint32_t init_ddr(void)
 #endif
 
 
-   WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001);
+   WriteReg_32(DBSC_DBPHYCONF0, 0x00000001);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR0, 0x0000000B);
-      WriteReg_32(DBSC_E3_DBTR1, 0x00000008);
+      WriteReg_32(DBSC_DBTR0, 0x0000000B);
+      WriteReg_32(DBSC_DBTR1, 0x00000008);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR0, 0x0000000D);
-      WriteReg_32(DBSC_E3_DBTR1, 0x00000009);
+      WriteReg_32(DBSC_DBTR0, 0x0000000D);
+      WriteReg_32(DBSC_DBTR1, 0x00000009);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR2, 0x00000000);
+   WriteReg_32(DBSC_DBTR2, 0x00000000);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR3, 0x0000000B);
-      WriteReg_32(DBSC_E3_DBTR4, 0x000B000B);
-      WriteReg_32(DBSC_E3_DBTR5, 0x00000027);
-      WriteReg_32(DBSC_E3_DBTR6, 0x0000001C);
+      WriteReg_32(DBSC_DBTR3, 0x0000000B);
+      WriteReg_32(DBSC_DBTR4, 0x000B000B);
+      WriteReg_32(DBSC_DBTR5, 0x00000027);
+      WriteReg_32(DBSC_DBTR6, 0x0000001C);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR3, 0x0000000D);
-      WriteReg_32(DBSC_E3_DBTR4, 0x000D000D);
-      WriteReg_32(DBSC_E3_DBTR5, 0x0000002D);
-      WriteReg_32(DBSC_E3_DBTR6, 0x00000020);
+      WriteReg_32(DBSC_DBTR3, 0x0000000D);
+      WriteReg_32(DBSC_DBTR4, 0x000D000D);
+      WriteReg_32(DBSC_DBTR5, 0x0000002D);
+      WriteReg_32(DBSC_DBTR6, 0x00000020);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR7, 0x00060006);
+   WriteReg_32(DBSC_DBTR7, 0x00060006);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR8, 0x00000020);
-      WriteReg_32(DBSC_E3_DBTR9, 0x00000006);
-      WriteReg_32(DBSC_E3_DBTR10, 0x0000000C);
-      WriteReg_32(DBSC_E3_DBTR11, 0x0000000A);
-      WriteReg_32(DBSC_E3_DBTR12, 0x00120012);
-      WriteReg_32(DBSC_E3_DBTR13, 0x000000CE);
-      WriteReg_32(DBSC_E3_DBTR14, 0x00140005);
-      WriteReg_32(DBSC_E3_DBTR15, 0x00050004);
-      WriteReg_32(DBSC_E3_DBTR16, 0x071F0305);
-      WriteReg_32(DBSC_E3_DBTR17, 0x040C0000);
+      WriteReg_32(DBSC_DBTR8, 0x00000020);
+      WriteReg_32(DBSC_DBTR9, 0x00000006);
+      WriteReg_32(DBSC_DBTR10, 0x0000000C);
+      WriteReg_32(DBSC_DBTR11, 0x0000000A);
+      WriteReg_32(DBSC_DBTR12, 0x00120012);
+      WriteReg_32(DBSC_DBTR13, 0x000000CE);
+      WriteReg_32(DBSC_DBTR14, 0x00140005);
+      WriteReg_32(DBSC_DBTR15, 0x00050004);
+      WriteReg_32(DBSC_DBTR16, 0x071F0305);
+      WriteReg_32(DBSC_DBTR17, 0x040C0000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR8, 0x00000021);
-      WriteReg_32(DBSC_E3_DBTR9, 0x00000007);
-      WriteReg_32(DBSC_E3_DBTR10, 0x0000000E);
-      WriteReg_32(DBSC_E3_DBTR11, 0x0000000C);
-      WriteReg_32(DBSC_E3_DBTR12, 0x00140014);
-      WriteReg_32(DBSC_E3_DBTR13, 0x000000F2);
-      WriteReg_32(DBSC_E3_DBTR14, 0x00170006);
-      WriteReg_32(DBSC_E3_DBTR15, 0x00060005);
-      WriteReg_32(DBSC_E3_DBTR16, 0x09210507);
-      WriteReg_32(DBSC_E3_DBTR17, 0x040E0000);
+      WriteReg_32(DBSC_DBTR8, 0x00000021);
+      WriteReg_32(DBSC_DBTR9, 0x00000007);
+      WriteReg_32(DBSC_DBTR10, 0x0000000E);
+      WriteReg_32(DBSC_DBTR11, 0x0000000C);
+      WriteReg_32(DBSC_DBTR12, 0x00140014);
+      WriteReg_32(DBSC_DBTR13, 0x000000F2);
+      WriteReg_32(DBSC_DBTR14, 0x00170006);
+      WriteReg_32(DBSC_DBTR15, 0x00060005);
+      WriteReg_32(DBSC_DBTR16, 0x09210507);
+      WriteReg_32(DBSC_DBTR17, 0x040E0000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR18, 0x00000200);
+   WriteReg_32(DBSC_DBTR18, 0x00000200);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR19, 0x01000040);
-      WriteReg_32(DBSC_E3_DBTR20, 0x020000D6);
+      WriteReg_32(DBSC_DBTR19, 0x01000040);
+      WriteReg_32(DBSC_DBTR20, 0x020000D6);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR19, 0x0129004B);
-      WriteReg_32(DBSC_E3_DBTR20, 0x020000FB);
+      WriteReg_32(DBSC_DBTR19, 0x0129004B);
+      WriteReg_32(DBSC_DBTR20, 0x020000FB);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR21, 0x00040004);
-   WriteReg_32(DBSC_E3_DBBL, 0x00000000);
-   WriteReg_32(DBSC_E3_DBODT0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBADJ0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002);
-   WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010);
-   WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001);
-   WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046);
+   WriteReg_32(DBSC_DBTR21, 0x00040004);
+   WriteReg_32(DBSC_DBBL, 0x00000000);
+   WriteReg_32(DBSC_DBODT0, 0x00000001);
+   WriteReg_32(DBSC_DBADJ0, 0x00000001);
+   WriteReg_32(DBSC_DBSYSCONF1, 0x00000002);
+   WriteReg_32(DBSC_DBDFICNT0, 0x00000010);
+   WriteReg_32(DBSC_DBBCAMDIS, 0x00000001);
+   WriteReg_32(DBSC_DBSCHRW1, 0x00000046);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03);
-      WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C);
+      WriteReg_32(DBSC_SCFCTST0, 0x0D050B03);
+      WriteReg_32(DBSC_SCFCTST1, 0x0306030C);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03);
-      WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C);
+      WriteReg_32(DBSC_SCFCTST0, 0x0C050B03);
+      WriteReg_32(DBSC_SCFCTST1, 0x0305030C);
    } /*  ddr_md */
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step0( INITBYP )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A);
-   WriteReg_32(DBSC_E3_DBCMD, 0x01840001);
-   WriteReg_32(DBSC_E3_DBCMD, 0x08840000);
+   WriteReg_32(DBSC_DBPDLK0, 0x0000A55A);
+   WriteReg_32(DBSC_DBCMD, 0x01840001);
+   WriteReg_32(DBSC_DBCMD, 0x08840000);
    NOTICE("BL2: [COLD_BOOT]\n");       /* rev.0.11 */
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x80010000);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000008);
+   WriteReg_32(DBSC_DBPDRGD0, 0x000B8000);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000090);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058904);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058904);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A04);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058A04);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000091);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0007BB6B);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000095);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0007BBAD);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000099);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0007BB6B);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000090);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000021);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0024641E);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00010073);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step2( DRAMRST/DRAMINT training )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000090);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0C058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0C058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000090);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000003);
    if (byp_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0780C720);
    } else {
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0780C700);
    }
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
-   while ((BIT(30) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000007);
+   while ((BIT(30) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000004);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
+      WriteReg_32(DBSC_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
+      WriteReg_32(DBSC_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000022);
+   WriteReg_32(DBSC_DBPDRGD0, 0x1000040B);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000023);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66);
+      WriteReg_32(DBSC_DBPDRGD0, 0x2D9C0B66);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77);
+      WriteReg_32(DBSC_DBPDRGD0, 0x35A00D77);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000024);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400);
+      WriteReg_32(DBSC_DBPDRGD0, 0x2A88B400);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28);
+      WriteReg_32(DBSC_DBPDRGD0, 0x2A8A2C28);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000025);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200);
+      WriteReg_32(DBSC_DBPDRGD0, 0x30005200);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00);
+      WriteReg_32(DBSC_DBPDRGD0, 0x30005E00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000026);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0014A9C9);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0014CB49);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000027);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000D70);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000F14);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000028);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00000046);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000029);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
       if (REFRESH_RATE > 3900) {
-          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018);  /*            [7]SRT=0 */
+          WriteReg_32(DBSC_DBPDRGD0, 0x00000018);  /*            [7]SRT=0 */
       } else {
-          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098);  /*            [7]SRT=1 */
+          WriteReg_32(DBSC_DBPDRGD0, 0x00000098);  /*            [7]SRT=1 */
       }
    } else {                                        /*  1856Mbps */
       if (REFRESH_RATE > 3900) {
-          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020);  /*            [7]SRT=0 */
+          WriteReg_32(DBSC_DBPDRGD0, 0x00000020);  /*            [7]SRT=0 */
       } else {
-          WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0);  /*            [7]SRT=1 */
+          WriteReg_32(DBSC_DBPDRGD0, 0x000000A0);  /*            [7]SRT=1 */
       } /*  REFRESH_RATE */
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
-
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
-
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010181);
-   WriteReg_32(DBSC_E3_DBCMD, 0x08840001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x0000002C);
+   WriteReg_32(DBSC_DBPDRGD0, 0x81003047);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000020);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00181884);
+   WriteReg_32(DBSC_DBPDRGA0, 0x0000001A);
+   WriteReg_32(DBSC_DBPDRGD0, 0x33C03C10);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
+
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A7);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A8);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A9);
+   WriteReg_32(DBSC_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C7);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C8);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C9);
+   WriteReg_32(DBSC_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E7);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E8);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E9);
+   WriteReg_32(DBSC_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000107);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000108);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000109);
+   WriteReg_32(DBSC_DBPDRGD0, 0x000D0D0D);
+
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00010181);
+   WriteReg_32(DBSC_DBCMD, 0x08840001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step3( WL/QSG training )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010601);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00010601);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    for (i = 0; i < 4; i++) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
-      RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
-      RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
-      RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8;
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B4 + i * 0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B3 + i * 0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
       if (RegVal_R6 > 0) {
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | RegVal_R6);
       } else {
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | RegVal_R7);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
       } /*  RegVal_R6 */
    } /*  for i */
 
@@ -432,188 +432,188 @@ uint32_t init_ddr(void)
    /****************************************************************************
     *  Initial_Step4( WLADJ training )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000005);
+   WriteReg_32(DBSC_DBPDRGD0, 0xC1AA00C0);
 
    /* rev.0.08 */
    if (pdqsr_ctl == 1){} else {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
    }
 
    /* PDR always off */        /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00010801);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    /****************************************************************************
     *  Initial_Step5(Read Data Bit Deskew)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000005);
+   WriteReg_32(DBSC_DBPDRGD0, 0xC1AA00D8);
 
    /* rev.0.08 */
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00011001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
 if (pdqsr_ctl == 1) {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
 }
 
    /* PDR dynamic */   /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
    }
 
    /****************************************************************************
     *  Initial_Step6(Write Data Bit Deskew)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00012001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    /****************************************************************************
     *  Initial_Step7(Read Data Eye Training)
     ***************************************************************************/
 if (pdqsr_ctl == 1) {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
 }
 
    /* PDR always off */        /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00014001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
 if (pdqsr_ctl == 1) {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
 }
 
    /* PDR dynamic */   /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
    }
 
    /****************************************************************************
     *  Initial_Step8(Write Data Eye Training)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00018001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step3_2( DQS Gate Training )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x0000002C);
+   WriteReg_32(DBSC_DBPDRGD0, 0x81003087);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00010401);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    for (i = 0; i < 4; i++) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
-      RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
-      RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
-      RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20);
+      RegVal_R5 = ((ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B4 + i * 0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B3 + i * 0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
       RegVal_R12 = (RegVal_R5 >> 0x2);
       if (RegVal_R12 < RegVal_R6) {
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
       } else {
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
       } /*  RegVal_R12 < RegVal_R6 */
    } /*  for i */
 
@@ -623,40 +623,40 @@ if (pdqsr_ctl == 1) {
     ***************************************************************************/
 /* rev.0.08 */
    if (pdqsr_ctl == 1){} else {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
    }
 
    /* PDR always off */        /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00015001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
 /* rev.0.08 */
    if (lcdl_ctl == 1) {
        for (i = 0; i < 4; i++) {
-          WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-          WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
-         bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
+          WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         dqsgd_0c = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
+          WriteReg_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20);
+         bdlcount_0c = ((ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 8);
          bdlcount_0c_div2  = (bdlcount_0c >> 1);
          bdlcount_0c_div4  = (bdlcount_0c >> 2);
          bdlcount_0c_div8  = (bdlcount_0c >> 3);
@@ -672,159 +672,159 @@ if (pdqsr_ctl == 1) {
 
          if (dqsgd_0c > lcdl_judge1) {
             if (dqsgd_0c <= lcdl_judge2) {
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-                WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+                WriteReg_32(DBSC_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
              } else {
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-               WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-               gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-                WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+               WriteReg_32(DBSC_DBPDRGD0, RegVal);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+               gatesl_0c = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+                WriteReg_32(DBSC_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AF + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0));
                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
-                WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AF + i * 0x20);
+                WriteReg_32(DBSC_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AA + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0));
                 rbd_0c[0] = (RegVal) &0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AA + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xE0E0E0E0);
                 for (j = 0; j < 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                     RegVal = RegVal | (rbd_0c[j] << 8 * j);
                }
-               WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+               WriteReg_32(DBSC_DBPDRGD0, RegVal);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AB + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0));
                 rbd_0c[0] = (RegVal) &0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AB + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xE0E0E0E0);
                 for (j = 0; j < 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                     RegVal = RegVal | (rbd_0c[j] << 8 * j);
                }
-               WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+               WriteReg_32(DBSC_DBPDRGD0, RegVal);
             }
          }
        }
-       WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002);
-       WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37);
+       WriteReg_32(DBSC_DBPDRGA0, 0x00000002);
+       WriteReg_32(DBSC_DBPDRGD0, 0x07D81E37);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000003);
    if (byp_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0380C720);
    } else {
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0380C700);
    }
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
-   while ((BIT(30) & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000007);
+   while ((BIT(30) & ReadReg_32(DBSC_DBPDRGD0)) != 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000021);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0024643E);
 
-   WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010);
-   WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
+   WriteReg_32(DBSC_DBBUS0CNF1, 0x00000010);
+   WriteReg_32(DBSC_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
+      WriteReg_32(DBSC_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
+      WriteReg_32(DBSC_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000);
-   WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001);
-   WriteReg_32(DBSC_E3_DBRFEN, 0x00000001);
-   WriteReg_32(DBSC_E3_DBACEN, 0x00000001);
+   WriteReg_32(DBSC_DBRFCNF2, 0x00010000);
+   WriteReg_32(DBSC_DBDFICUPDCNF, 0x40100001);
+   WriteReg_32(DBSC_DBRFEN, 0x00000001);
+   WriteReg_32(DBSC_DBACEN, 0x00000001);
 
 /* rev.0.08 */
    if (pdqsr_ctl == 1) {
    WriteReg_32(0xE67F0018, 0x00000001);
    RegVal = ReadReg_32(0x40000000);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000);
-   WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000000);
+   WriteReg_32(DBSC_DBPDRGD0, RegVal);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
    }
 
    /* PDR dynamic */   /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
    }
 
    /*  rev.0.03 add Comment */
    /****************************************************************************
     *  Initial_Step9( Initial End )
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000);
-   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
+   WriteReg_32(DBSC_DBPDLK0, 0x00000000);
+   WriteReg_32(DBSC_DBSYSCNT0, 0x00000000);
 
 #ifdef ddr_qos_init_setting /*  only for non qos_init */
-   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
-   WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218);
-   WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4);
-   WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037);
-   WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111);
-   WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123);
-   WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00);
-   WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00);
-   WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000);
-   WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000);
-   WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300);
-   WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200);
-   WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0);
-   WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080);
-   WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030);
-   WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020);
-   WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010);
+   WriteReg_32(DBSC_DBSYSCNT0, 0x00001234);
+   WriteReg_32(DBSC_DBCAM0CNF1, 0x00043218);
+   WriteReg_32(DBSC_DBCAM0CNF2, 0x000000F4);
+   WriteReg_32(DBSC_DBSCHCNT0, 0x000f0037);
+   WriteReg_32(DBSC_DBSCHSZ0, 0x00000001);
+   WriteReg_32(DBSC_DBSCHRW0, 0x22421111);
+   WriteReg_32(DBSC_SCFCTST2, 0x012F1123);
+   WriteReg_32(DBSC_DBSCHQOS00, 0x00000F00);
+   WriteReg_32(DBSC_DBSCHQOS01, 0x00000B00);
+   WriteReg_32(DBSC_DBSCHQOS02, 0x00000000);
+   WriteReg_32(DBSC_DBSCHQOS03, 0x00000000);
+   WriteReg_32(DBSC_DBSCHQOS40, 0x00000300);
+   WriteReg_32(DBSC_DBSCHQOS41, 0x000002F0);
+   WriteReg_32(DBSC_DBSCHQOS42, 0x00000200);
+   WriteReg_32(DBSC_DBSCHQOS43, 0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS90, 0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS91, 0x000000F0);
+   WriteReg_32(DBSC_DBSCHQOS92, 0x000000A0);
+   WriteReg_32(DBSC_DBSCHQOS93, 0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS130, 0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS131, 0x000000F0);
+   WriteReg_32(DBSC_DBSCHQOS132, 0x000000A0);
+   WriteReg_32(DBSC_DBSCHQOS133, 0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS140, 0x000000C0);
+   WriteReg_32(DBSC_DBSCHQOS141, 0x000000B0);
+   WriteReg_32(DBSC_DBSCHQOS142, 0x00000080);
+   WriteReg_32(DBSC_DBSCHQOS143, 0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS150, 0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS151, 0x00000030);
+   WriteReg_32(DBSC_DBSCHQOS152, 0x00000020);
+   WriteReg_32(DBSC_DBSCHQOS153, 0x00000010);
 
 /* rev.0.08 */
    if (pdqsr_ctl == 1){} else {
    WriteReg_32(0xE67F0018, 0x00000001);
    }
 
-   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
+   WriteReg_32(DBSC_DBSYSCNT0, 0x00000000);
 #endif
 
    return 1;   /*  rev.0.04 Restore the return code */
@@ -885,13 +885,13 @@ uint32_t recovery_from_backup_mode(void)
    /* CPG setting ===============================================*/
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
-   WriteReg_32(DBSC_E3_DBKIND, 0x00000007);
+   WriteReg_32(DBSC_DBSYSCNT0, 0x00001234);
+   WriteReg_32(DBSC_DBKIND, 0x00000007);
 
 #if RCAR_DRAM_DDR3L_MEMCONF == 0
-   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02);
+   WriteReg_32(DBSC_DBMEMCONF00, 0x0f030a02);
 #else
-   WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
+   WriteReg_32(DBSC_DBMEMCONF00, 0x10030a02);
 #endif
 
 /* rev.0.08 */
@@ -900,232 +900,232 @@ uint32_t recovery_from_backup_mode(void)
          WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /*  MCS1_N/MODT1 are activated. */
 #endif
 
-   WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001);
+   WriteReg_32(DBSC_DBPHYCONF0, 0x00000001);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR0, 0x0000000B);
-      WriteReg_32(DBSC_E3_DBTR1, 0x00000008);
+      WriteReg_32(DBSC_DBTR0, 0x0000000B);
+      WriteReg_32(DBSC_DBTR1, 0x00000008);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR0, 0x0000000D);
-      WriteReg_32(DBSC_E3_DBTR1, 0x00000009);
+      WriteReg_32(DBSC_DBTR0, 0x0000000D);
+      WriteReg_32(DBSC_DBTR1, 0x00000009);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR2, 0x00000000);
+   WriteReg_32(DBSC_DBTR2, 0x00000000);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR3, 0x0000000B);
-      WriteReg_32(DBSC_E3_DBTR4, 0x000B000B);
-      WriteReg_32(DBSC_E3_DBTR5, 0x00000027);
-      WriteReg_32(DBSC_E3_DBTR6, 0x0000001C);
+      WriteReg_32(DBSC_DBTR3, 0x0000000B);
+      WriteReg_32(DBSC_DBTR4, 0x000B000B);
+      WriteReg_32(DBSC_DBTR5, 0x00000027);
+      WriteReg_32(DBSC_DBTR6, 0x0000001C);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR3, 0x0000000D);
-      WriteReg_32(DBSC_E3_DBTR4, 0x000D000D);
-      WriteReg_32(DBSC_E3_DBTR5, 0x0000002D);
-      WriteReg_32(DBSC_E3_DBTR6, 0x00000020);
+      WriteReg_32(DBSC_DBTR3, 0x0000000D);
+      WriteReg_32(DBSC_DBTR4, 0x000D000D);
+      WriteReg_32(DBSC_DBTR5, 0x0000002D);
+      WriteReg_32(DBSC_DBTR6, 0x00000020);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR7, 0x00060006);
+   WriteReg_32(DBSC_DBTR7, 0x00060006);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR8, 0x00000020);
-      WriteReg_32(DBSC_E3_DBTR9, 0x00000006);
-      WriteReg_32(DBSC_E3_DBTR10, 0x0000000C);
-      WriteReg_32(DBSC_E3_DBTR11, 0x0000000A);
-      WriteReg_32(DBSC_E3_DBTR12, 0x00120012);
-      WriteReg_32(DBSC_E3_DBTR13, 0x000000CE);
-      WriteReg_32(DBSC_E3_DBTR14, 0x00140005);
-      WriteReg_32(DBSC_E3_DBTR15, 0x00050004);
-      WriteReg_32(DBSC_E3_DBTR16, 0x071F0305);
-      WriteReg_32(DBSC_E3_DBTR17, 0x040C0000);
+      WriteReg_32(DBSC_DBTR8, 0x00000020);
+      WriteReg_32(DBSC_DBTR9, 0x00000006);
+      WriteReg_32(DBSC_DBTR10, 0x0000000C);
+      WriteReg_32(DBSC_DBTR11, 0x0000000A);
+      WriteReg_32(DBSC_DBTR12, 0x00120012);
+      WriteReg_32(DBSC_DBTR13, 0x000000CE);
+      WriteReg_32(DBSC_DBTR14, 0x00140005);
+      WriteReg_32(DBSC_DBTR15, 0x00050004);
+      WriteReg_32(DBSC_DBTR16, 0x071F0305);
+      WriteReg_32(DBSC_DBTR17, 0x040C0000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR8, 0x00000021);
-      WriteReg_32(DBSC_E3_DBTR9, 0x00000007);
-      WriteReg_32(DBSC_E3_DBTR10, 0x0000000E);
-      WriteReg_32(DBSC_E3_DBTR11, 0x0000000C);
-      WriteReg_32(DBSC_E3_DBTR12, 0x00140014);
-      WriteReg_32(DBSC_E3_DBTR13, 0x000000F2);
-      WriteReg_32(DBSC_E3_DBTR14, 0x00170006);
-      WriteReg_32(DBSC_E3_DBTR15, 0x00060005);
-      WriteReg_32(DBSC_E3_DBTR16, 0x09210507);
-      WriteReg_32(DBSC_E3_DBTR17, 0x040E0000);
+      WriteReg_32(DBSC_DBTR8, 0x00000021);
+      WriteReg_32(DBSC_DBTR9, 0x00000007);
+      WriteReg_32(DBSC_DBTR10, 0x0000000E);
+      WriteReg_32(DBSC_DBTR11, 0x0000000C);
+      WriteReg_32(DBSC_DBTR12, 0x00140014);
+      WriteReg_32(DBSC_DBTR13, 0x000000F2);
+      WriteReg_32(DBSC_DBTR14, 0x00170006);
+      WriteReg_32(DBSC_DBTR15, 0x00060005);
+      WriteReg_32(DBSC_DBTR16, 0x09210507);
+      WriteReg_32(DBSC_DBTR17, 0x040E0000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR18, 0x00000200);
+   WriteReg_32(DBSC_DBTR18, 0x00000200);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBTR19, 0x01000040);
-      WriteReg_32(DBSC_E3_DBTR20, 0x020000D6);
+      WriteReg_32(DBSC_DBTR19, 0x01000040);
+      WriteReg_32(DBSC_DBTR20, 0x020000D6);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBTR19, 0x0129004B);
-      WriteReg_32(DBSC_E3_DBTR20, 0x020000FB);
+      WriteReg_32(DBSC_DBTR19, 0x0129004B);
+      WriteReg_32(DBSC_DBTR20, 0x020000FB);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBTR21, 0x00040004);
-   WriteReg_32(DBSC_E3_DBBL, 0x00000000);
-   WriteReg_32(DBSC_E3_DBODT0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBADJ0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002);
-   WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010);
-   WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001);
-   WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046);
+   WriteReg_32(DBSC_DBTR21, 0x00040004);
+   WriteReg_32(DBSC_DBBL, 0x00000000);
+   WriteReg_32(DBSC_DBODT0, 0x00000001);
+   WriteReg_32(DBSC_DBADJ0, 0x00000001);
+   WriteReg_32(DBSC_DBSYSCONF1, 0x00000002);
+   WriteReg_32(DBSC_DBDFICNT0, 0x00000010);
+   WriteReg_32(DBSC_DBBCAMDIS, 0x00000001);
+   WriteReg_32(DBSC_DBSCHRW1, 0x00000046);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03);
-      WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C);
+      WriteReg_32(DBSC_SCFCTST0, 0x0D050B03);
+      WriteReg_32(DBSC_SCFCTST1, 0x0306030C);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03);
-      WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C);
+      WriteReg_32(DBSC_SCFCTST0, 0x0C050B03);
+      WriteReg_32(DBSC_SCFCTST1, 0x0305030C);
    } /*  ddr_md */
 
    /****************************************************************************
     *  recovery_Step1(PHY setting 1)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A);
-   WriteReg_32(DBSC_E3_DBCMD, 0x01840001);
-   WriteReg_32(DBSC_E3_DBCMD, 0x0A840000);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); /*  DDR_PLLCR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); /*  DDR_PGCR1 */
+   WriteReg_32(DBSC_DBPDLK0, 0x0000A55A);
+   WriteReg_32(DBSC_DBCMD, 0x01840001);
+   WriteReg_32(DBSC_DBCMD, 0x0A840000);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000008); /*  DDR_PLLCR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x000B8000);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000003); /*  DDR_PGCR1 */
    if (byp_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0780C720);
    } else {
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0780C700);
    }
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); /*  DDR_DXCCR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); /*  DDR_ACIOCR0 */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
-   while ((BIT(30) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000020); /*  DDR_DXCCR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x00181884);
+   WriteReg_32(DBSC_DBPDRGA0, 0x0000001A); /*  DDR_ACIOCR0 */
+   WriteReg_32(DBSC_DBPDRGD0, 0x33C03C10);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000007);
+   while ((BIT(30) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000004);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
+      WriteReg_32(DBSC_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
+      WriteReg_32(DBSC_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000022);
+   WriteReg_32(DBSC_DBPDRGD0, 0x1000040B);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000023);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66);
+      WriteReg_32(DBSC_DBPDRGD0, 0x2D9C0B66);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77);
+      WriteReg_32(DBSC_DBPDRGD0, 0x35A00D77);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000024);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400);
+      WriteReg_32(DBSC_DBPDRGD0, 0x2A88B400);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28);
+      WriteReg_32(DBSC_DBPDRGD0, 0x2A8A2C28);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000025);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200);
+      WriteReg_32(DBSC_DBPDRGD0, 0x30005200);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00);
+      WriteReg_32(DBSC_DBPDRGD0, 0x30005E00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000026);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0014A9C9);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0014CB49);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000027);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000D70);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000F14);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000028);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00000046);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000029);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
       if (REFRESH_RATE > 3900) {
-          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018);  /*            [7]SRT=0 */
+          WriteReg_32(DBSC_DBPDRGD0, 0x00000018);  /*            [7]SRT=0 */
       } else {
-          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098);  /*            [7]SRT=1 */
+          WriteReg_32(DBSC_DBPDRGD0, 0x00000098);  /*            [7]SRT=1 */
       }
    } else {                                        /*  1856Mbps */
       if (REFRESH_RATE > 3900) {
-          WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020);  /*            [7]SRT=0 */
+          WriteReg_32(DBSC_DBPDRGD0, 0x00000020);  /*            [7]SRT=0 */
       } else {
-          WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0);  /*            [7]SRT=1 */
+          WriteReg_32(DBSC_DBPDRGD0, 0x000000A0);  /*            [7]SRT=1 */
       } /*  REFRESH_RATE */
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); /*  DDR_DSGCR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
-
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x40010000);
-
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
-
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /*  DDR_ZQ0DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /*  DDR_ZQ1DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC4285FBF);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /*  DDR_ZQ2DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
+   WriteReg_32(DBSC_DBPDRGA0, 0x0000002C);
+   WriteReg_32(DBSC_DBPDRGD0, 0x81003047);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000091);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0007BB6B);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000095);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0007BBAD);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000099);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0007BB6B);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000021); /*  DDR_DSGCR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x0024641E);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
+
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x40010000);
+
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
+
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000092); /*  DDR_ZQ0DR */
+   WriteReg_32(DBSC_DBPDRGD0, 0xC2C59AB5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000096); /*  DDR_ZQ1DR */
+   WriteReg_32(DBSC_DBPDRGD0, 0xC4285FBF);
+   WriteReg_32(DBSC_DBPDRGA0, 0x0000009A); /*  DDR_ZQ2DR */
+   WriteReg_32(DBSC_DBPDRGD0, 0xC2C59AB5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0C058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0C058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00050001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x00050001);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    /*  ddr backupmode end */
    if (ddrBackup) {
@@ -1139,352 +1139,352 @@ uint32_t recovery_from_backup_mode(void)
       return INITDRAM_ERR_I;
    } /*  err */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /*  DDR_ZQ0DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /*  DDR_ZQ1DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x04285FBF);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /*  DDR_ZQ2DR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000092); /*  DDR_ZQ0DR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x02C59AB5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000096); /*  DDR_ZQ1DR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x04285FBF);
+   WriteReg_32(DBSC_DBPDRGA0, 0x0000009A); /*  DDR_ZQ2DR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x02C59AB5);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x08000000);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x08000000);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000003);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x00000003);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x80010000);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x00010073);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0C058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0C058A00);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000090); /*  DDR_ZQCR */
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058900);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00);
+      WriteReg_32(DBSC_DBPDRGD0, 0x04058A00);
    } /*  ddr_md */
 
 /* rev0.08 */
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000000C);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x18000040);
+   WriteReg_32(DBSC_DBPDRGA0, 0x0000000C);
+   WriteReg_32(DBSC_DBPDRGD0, 0x18000040);
 
    /****************************************************************************
     *  recovery_Step2(PHY setting 2)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
-
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D);
-
-   WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
-   WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
+
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A7);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A8);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A9);
+   WriteReg_32(DBSC_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C7);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C8);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C9);
+   WriteReg_32(DBSC_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E7);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E8);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E9);
+   WriteReg_32(DBSC_DBPDRGD0, 0x000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000107);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000108);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000109);
+   WriteReg_32(DBSC_DBPDRGD0, 0x000D0D0D);
+
+   WriteReg_32(DBSC_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000);
+   WriteReg_32(DBSC_DBBUS0CNF1, 0x00000010);
 
    /*  Select setting value in bps */
    if (ddr_md == 0) {                                 /*  1584Mbps */
-      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
+      WriteReg_32(DBSC_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000);
    } else {                                        /*  1856Mbps */
-      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
+      WriteReg_32(DBSC_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000);
    } /*  ddr_md */
 
-   WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000);
-   WriteReg_32(DBSC_E3_DBRFEN, 0x00000001);
-   WriteReg_32(DBSC_E3_DBCMD, 0x0A840001);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBWAIT)) != 0);
+   WriteReg_32(DBSC_DBRFCNF2, 0x00010000);
+   WriteReg_32(DBSC_DBRFEN, 0x00000001);
+   WriteReg_32(DBSC_DBCMD, 0x0A840001);
+   while ((BIT(0) & ReadReg_32(DBSC_DBWAIT)) != 0);
 
-   WriteReg_32(DBSC_E3_DBCMD, 0x00000000);
+   WriteReg_32(DBSC_DBCMD, 0x00000000);
 
-   WriteReg_32(DBSC_E3_DBCMD, 0x04840010);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBWAIT)) != 0);
+   WriteReg_32(DBSC_DBCMD, 0x04840010);
+   while ((BIT(0) & ReadReg_32(DBSC_DBWAIT)) != 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /*  DDR_PIR */
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010701);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_DBPDRGD0, 0x00010701);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006); /*  DDR_PGSR0 */
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    for (i = 0; i < 4; i++)
    {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
-      RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
-      RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
-      RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8;
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B4 + i * 0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B3 + i * 0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
 
       if (RegVal_R6 > 0) {
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | RegVal_R6);
       } else {
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | RegVal_R7);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
       } /*  RegVal_R6 */
    } /*  for i */
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000005);
+   WriteReg_32(DBSC_DBPDRGD0, 0xC1AA00C0);
 
    /* rev.0.08 */
    if (pdqsr_ctl == 1){} else {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
    }
 
    /* PDR always off */        /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00010801);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000005);
+   WriteReg_32(DBSC_DBPDRGD0, 0xC1AA00D8);
 
    /* rev.0.08 */
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00011001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
 if (pdqsr_ctl == 1) {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
 }
 
    /* PDR dynamic */   /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00012001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
 if (pdqsr_ctl == 1) {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
 }
 
    /* PDR always off */        /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00014001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
 if (pdqsr_ctl == 1) {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
 }
 
    /* PDR dynamic */   /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
-
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00018001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
+
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C000285);
+   WriteReg_32(DBSC_DBPDRGA0, 0x0000002C);
+   WriteReg_32(DBSC_DBPDRGD0, 0x81003087);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00010401);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
    for (i = 0; i < 4; i++) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
-      RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20);
-      RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20);
-      RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20);
+      RegVal_R5 = ((ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x8);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B4 + i * 0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000B3 + i * 0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
       RegVal_R12 = (RegVal_R5 >> 0x2);
 
       if (RegVal_R12 < RegVal_R6) {
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
       } else {
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-        RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-         WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+        RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         WriteReg_32(DBSC_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
       } /*  RegVal_R12 < RegVal_R6 */
    } /*  for i */
 
 /* rev.0.08 */
    if (pdqsr_ctl == 1){} else {
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
    }
 
    /* PDR always off */        /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000008);
    }
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006);
-   while ((BIT(0) & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000001);
+   WriteReg_32(DBSC_DBPDRGD0, 0x00015001);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000006);
+   while ((BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0);
 
 /* rev.0.08 */
    if (lcdl_ctl == 1) {
        for (i = 0; i < 4; i++) {
-          WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-         dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
-          WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20);
-         bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
+          WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+         dqsgd_0c = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
+          WriteReg_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20);
+         bdlcount_0c = ((ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 8);
          bdlcount_0c_div2  = (bdlcount_0c >> 1);
          bdlcount_0c_div4  = (bdlcount_0c >> 2);
          bdlcount_0c_div8  = (bdlcount_0c >> 3);
@@ -1500,147 +1500,147 @@ if (pdqsr_ctl == 1) {
 
          if (dqsgd_0c > lcdl_judge1) {
             if (dqsgd_0c <= lcdl_judge2) {
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-                WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+                WriteReg_32(DBSC_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal));
              } else {
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
-               WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-               gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
-                WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
+               WriteReg_32(DBSC_DBPDRGD0, RegVal);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+               gatesl_0c = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000B2 + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
+                WriteReg_32(DBSC_DBPDRGD0, (RegVal | (gatesl_0c + 1)));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AF + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0));
                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
-                WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AF + i * 0x20);
+                WriteReg_32(DBSC_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)));
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AA + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0));
                 rbd_0c[0] = (RegVal) &0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AA + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xE0E0E0E0);
                 for (j = 0; j < 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                     RegVal = RegVal | (rbd_0c[j] << 8 * j);
                }
-               WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+               WriteReg_32(DBSC_DBPDRGD0, RegVal);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AB + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0));
                 rbd_0c[0] = (RegVal) &0x0000001f;
                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
-               WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
-               RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+               WriteReg_32(DBSC_DBPDRGA0, 0x000000AB + i * 0x20);
+               RegVal = (ReadReg_32(DBSC_DBPDRGD0) & 0xE0E0E0E0);
                 for (j = 0; j < 4; j++) {
                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
                     RegVal = RegVal | (rbd_0c[j] << 8 * j);
                }
-               WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+               WriteReg_32(DBSC_DBPDRGD0, RegVal);
             }
          }
        }
-       WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002);
-       WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37);
+       WriteReg_32(DBSC_DBPDRGA0, 0x00000002);
+       WriteReg_32(DBSC_DBPDRGD0, 0x07D81E37);
    }
 
 
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000003);
    if (byp_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0380C720);
    } else {
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700);
+      WriteReg_32(DBSC_DBPDRGD0, 0x0380C700);
    }
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007);
-   while ((BIT(30) & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000007);
+   while ((BIT(30) & ReadReg_32(DBSC_DBPDRGD0)) != 0);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000021);
+   WriteReg_32(DBSC_DBPDRGD0, 0x0024643E);
 
    /****************************************************************************
     *  recovery_Step3(DBSC Setting 2)
     ***************************************************************************/
-   WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001);
-   WriteReg_32(DBSC_E3_DBACEN, 0x00000001);
+   WriteReg_32(DBSC_DBDFICUPDCNF, 0x40100001);
+   WriteReg_32(DBSC_DBACEN, 0x00000001);
 
 /* rev.0.08 */
    if (pdqsr_ctl == 1) {
    WriteReg_32(0xE67F0018, 0x00000001);
    RegVal = ReadReg_32(0x40000000);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000);
-   WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
-   WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100);
-   WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000000);
+   WriteReg_32(DBSC_DBPDRGD0, RegVal);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000A0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000C0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x000000E0);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0, 0x00000100);
+   WriteReg_32(DBSC_DBPDRGD0, 0x7C0002C5);
    }
 
    /* PDR dynamic */   /* rev.0.10 */
    if (pdr_ctl == 1) {
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
-      WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103);
-      WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000A3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000C3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x000000E3);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
+      WriteReg_32(DBSC_DBPDRGA0, 0x00000103);
+      WriteReg_32(DBSC_DBPDRGD0, 0x00000000);
    }
 
-   WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000);
-   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
+   WriteReg_32(DBSC_DBPDLK0, 0x00000000);
+   WriteReg_32(DBSC_DBSYSCNT0, 0x00000000);
 
 #ifdef ddr_qos_init_setting /*  only for non qos_init */
-   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234);
-   WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218);
-   WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4);
-   WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037);
-   WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001);
-   WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111);
-   WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123);
-   WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00);
-   WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00);
-   WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000);
-   WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000);
-   WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300);
-   WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200);
-   WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100);
-   WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0);
-   WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0);
-   WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0);
-   WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0);
-   WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080);
-   WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040);
-   WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030);
-   WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020);
-   WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010);
+   WriteReg_32(DBSC_DBSYSCNT0, 0x00001234);
+   WriteReg_32(DBSC_DBCAM0CNF1, 0x00043218);
+   WriteReg_32(DBSC_DBCAM0CNF2, 0x000000F4);
+   WriteReg_32(DBSC_DBSCHCNT0, 0x000f0037);
+   WriteReg_32(DBSC_DBSCHSZ0, 0x00000001);
+   WriteReg_32(DBSC_DBSCHRW0, 0x22421111);
+   WriteReg_32(DBSC_SCFCTST2, 0x012F1123);
+   WriteReg_32(DBSC_DBSCHQOS00, 0x00000F00);
+   WriteReg_32(DBSC_DBSCHQOS01, 0x00000B00);
+   WriteReg_32(DBSC_DBSCHQOS02, 0x00000000);
+   WriteReg_32(DBSC_DBSCHQOS03, 0x00000000);
+   WriteReg_32(DBSC_DBSCHQOS40, 0x00000300);
+   WriteReg_32(DBSC_DBSCHQOS41, 0x000002F0);
+   WriteReg_32(DBSC_DBSCHQOS42, 0x00000200);
+   WriteReg_32(DBSC_DBSCHQOS43, 0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS90, 0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS91, 0x000000F0);
+   WriteReg_32(DBSC_DBSCHQOS92, 0x000000A0);
+   WriteReg_32(DBSC_DBSCHQOS93, 0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS130, 0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS131, 0x000000F0);
+   WriteReg_32(DBSC_DBSCHQOS132, 0x000000A0);
+   WriteReg_32(DBSC_DBSCHQOS133, 0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS140, 0x000000C0);
+   WriteReg_32(DBSC_DBSCHQOS141, 0x000000B0);
+   WriteReg_32(DBSC_DBSCHQOS142, 0x00000080);
+   WriteReg_32(DBSC_DBSCHQOS143, 0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS150, 0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS151, 0x00000030);
+   WriteReg_32(DBSC_DBSCHQOS152, 0x00000020);
+   WriteReg_32(DBSC_DBSCHQOS153, 0x00000010);
 
 /* rev.0.08 */
    if (pdqsr_ctl == 1){} else {
    WriteReg_32(0xE67F0018, 0x00000001);
    }
 
-   WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000);
+   WriteReg_32(DBSC_DBSYSCNT0, 0x00000000);
 #endif
 
    return 1;

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
index 94a6bad4e5d26cb5c3674cc3acbe634c45f37fe8..972b590a4e85259b61da69554ba291596c23d9d8 100644 (file)
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
@@ -8,7 +8,7 @@
 #include <lib/utils_def.h>
 #include <stdint.h>
 #include "boot_init_dram.h"
-#include "boot_init_dram_regdef_v3m.h"
+#include "boot_init_dram_regdef.h"
 
 static void WriteReg_32(uintptr_t a, uint32_t v)
 {
@@ -27,309 +27,309 @@ static uint32_t init_ddr_v3m_1600(void)
 
        uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
 
-   WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
-   WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
+   WriteReg_32(DBSC_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_DBKIND,0x00000007);
 #if RCAR_DRAM_DDR3L_MEMCONF == 0
-   WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02); // 1GB: Eagle
+   WriteReg_32(DBSC_DBMEMCONF00,0x0f030a02); // 1GB: Eagle
 #else
-   WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02); // 2GB: V3MSK
+   WriteReg_32(DBSC_DBMEMCONF00,0x10030a02); // 2GB: V3MSK
 #endif
-   WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
-   WriteReg_32(DBSC_V3M_DBTR0,0x0000000B);
-   WriteReg_32(DBSC_V3M_DBTR1,0x00000008);
-   WriteReg_32(DBSC_V3M_DBTR3,0x0000000B);
-   WriteReg_32(DBSC_V3M_DBTR4,0x000B000B);
-   WriteReg_32(DBSC_V3M_DBTR5,0x00000027);
-   WriteReg_32(DBSC_V3M_DBTR6,0x0000001C);
-   WriteReg_32(DBSC_V3M_DBTR7,0x00060006);
-   WriteReg_32(DBSC_V3M_DBTR8,0x00000020);
-   WriteReg_32(DBSC_V3M_DBTR9,0x00000006);
-   WriteReg_32(DBSC_V3M_DBTR10,0x0000000C);
-   WriteReg_32(DBSC_V3M_DBTR11,0x0000000B);
-   WriteReg_32(DBSC_V3M_DBTR12,0x00120012);
-   WriteReg_32(DBSC_V3M_DBTR13,0x01180118);
-   WriteReg_32(DBSC_V3M_DBTR14,0x00140005);
-   WriteReg_32(DBSC_V3M_DBTR15,0x00050004);
-   WriteReg_32(DBSC_V3M_DBTR16,0x071D0305);
-   WriteReg_32(DBSC_V3M_DBTR17,0x040C0010);
-   WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
-   WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
-   WriteReg_32(DBSC_V3M_DBTR20,0x02000120);
-   WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
-   WriteReg_32(DBSC_V3M_DBBL,0x00000000);
-   WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
-   WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
-   WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00082010);
-   WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x00002000);
-   WriteReg_32(DBSC_V3M_DBSCHCNT0,0x080f003f);
-   WriteReg_32(DBSC_V3M_DBSCHCNT1,0x00001010);
-   WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
-   WriteReg_32(DBSC_V3M_DBSCHRW0,0x00000200);
-   WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000040);
-   WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000600);
-   WriteReg_32(DBSC_V3M_DBSCHQOS41,0x00000480);
-   WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000300);
-   WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000180);
-   WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000400);
-   WriteReg_32(DBSC_V3M_DBSCHQOS91,0x00000300);
-   WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
-   WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
-   WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000300);
-   WriteReg_32(DBSC_V3M_DBSCHQOS131,0x00000240);
-   WriteReg_32(DBSC_V3M_DBSCHQOS132,0x00000180);
-   WriteReg_32(DBSC_V3M_DBSCHQOS133,0x000000c0);
-   WriteReg_32(DBSC_V3M_DBSCHQOS140,0x00000200);
-   WriteReg_32(DBSC_V3M_DBSCHQOS141,0x00000180);
-   WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000100);
-   WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000080);
-   WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000100);
-   WriteReg_32(DBSC_V3M_DBSCHQOS151,0x000000c0);
-   WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000080);
-   WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000040);
-   WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
-   WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00040C04);
-   WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000001c4);
-   WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000003);
-   WriteReg_32(DBSC_V3M_DBSCHRW1,0x001a0080);
-   WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
+   WriteReg_32(DBSC_DBPHYCONF0,0x00000001);
+   WriteReg_32(DBSC_DBTR0,0x0000000B);
+   WriteReg_32(DBSC_DBTR1,0x00000008);
+   WriteReg_32(DBSC_DBTR3,0x0000000B);
+   WriteReg_32(DBSC_DBTR4,0x000B000B);
+   WriteReg_32(DBSC_DBTR5,0x00000027);
+   WriteReg_32(DBSC_DBTR6,0x0000001C);
+   WriteReg_32(DBSC_DBTR7,0x00060006);
+   WriteReg_32(DBSC_DBTR8,0x00000020);
+   WriteReg_32(DBSC_DBTR9,0x00000006);
+   WriteReg_32(DBSC_DBTR10,0x0000000C);
+   WriteReg_32(DBSC_DBTR11,0x0000000B);
+   WriteReg_32(DBSC_DBTR12,0x00120012);
+   WriteReg_32(DBSC_DBTR13,0x01180118);
+   WriteReg_32(DBSC_DBTR14,0x00140005);
+   WriteReg_32(DBSC_DBTR15,0x00050004);
+   WriteReg_32(DBSC_DBTR16,0x071D0305);
+   WriteReg_32(DBSC_DBTR17,0x040C0010);
+   WriteReg_32(DBSC_DBTR18,0x00000200);
+   WriteReg_32(DBSC_DBTR19,0x01000040);
+   WriteReg_32(DBSC_DBTR20,0x02000120);
+   WriteReg_32(DBSC_DBTR21,0x00040004);
+   WriteReg_32(DBSC_DBBL,0x00000000);
+   WriteReg_32(DBSC_DBODT0,0x00000001);
+   WriteReg_32(DBSC_DBADJ0,0x00000001);
+   WriteReg_32(DBSC_DBCAM0CNF1,0x00082010);
+   WriteReg_32(DBSC_DBCAM0CNF2,0x00002000);
+   WriteReg_32(DBSC_DBSCHCNT0,0x080f003f);
+   WriteReg_32(DBSC_DBSCHCNT1,0x00001010);
+   WriteReg_32(DBSC_DBSCHSZ0,0x00000001);
+   WriteReg_32(DBSC_DBSCHRW0,0x00000200);
+   WriteReg_32(DBSC_DBSCHRW1,0x00000040);
+   WriteReg_32(DBSC_DBSCHQOS40,0x00000600);
+   WriteReg_32(DBSC_DBSCHQOS41,0x00000480);
+   WriteReg_32(DBSC_DBSCHQOS42,0x00000300);
+   WriteReg_32(DBSC_DBSCHQOS43,0x00000180);
+   WriteReg_32(DBSC_DBSCHQOS90,0x00000400);
+   WriteReg_32(DBSC_DBSCHQOS91,0x00000300);
+   WriteReg_32(DBSC_DBSCHQOS92,0x00000200);
+   WriteReg_32(DBSC_DBSCHQOS93,0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS130,0x00000300);
+   WriteReg_32(DBSC_DBSCHQOS131,0x00000240);
+   WriteReg_32(DBSC_DBSCHQOS132,0x00000180);
+   WriteReg_32(DBSC_DBSCHQOS133,0x000000c0);
+   WriteReg_32(DBSC_DBSCHQOS140,0x00000200);
+   WriteReg_32(DBSC_DBSCHQOS141,0x00000180);
+   WriteReg_32(DBSC_DBSCHQOS142,0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS143,0x00000080);
+   WriteReg_32(DBSC_DBSCHQOS150,0x00000100);
+   WriteReg_32(DBSC_DBSCHQOS151,0x000000c0);
+   WriteReg_32(DBSC_DBSCHQOS152,0x00000080);
+   WriteReg_32(DBSC_DBSCHQOS153,0x00000040);
+   WriteReg_32(DBSC_DBSYSCONF1,0x00000002);
+   WriteReg_32(DBSC_DBCAM0CNF1,0x00040C04);
+   WriteReg_32(DBSC_DBCAM0CNF2,0x000001c4);
+   WriteReg_32(DBSC_DBSCHSZ0,0x00000003);
+   WriteReg_32(DBSC_DBSCHRW1,0x001a0080);
+   WriteReg_32(DBSC_DBDFICNT0,0x00000010);
 
-   WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
-   WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
-   WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDLK0,0X0000A55A);
+   WriteReg_32(DBSC_DBCMD,0x01000001);
+   WriteReg_32(DBSC_DBCMD,0x08000000);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0X80010000);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X00000008);
+   WriteReg_32(DBSC_DBPDRGD0,0X000B8000);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0X04058904);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000091);
+   WriteReg_32(DBSC_DBPDRGD0,0X0007BB6D);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000095);
+   WriteReg_32(DBSC_DBPDRGD0,0X0007BB6B);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000099);
+   WriteReg_32(DBSC_DBPDRGD0,0X0007BB6D);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0X04058900);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000021);
+   WriteReg_32(DBSC_DBPDRGD0,0X0024641E);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0X00010073);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0X0C058900);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000090);
+   WriteReg_32(DBSC_DBPDRGD0,0X04058900);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C700);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
-   while ( (BIT(30)& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X00000003);
+   WriteReg_32(DBSC_DBPDRGD0,0X0780C700);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000007);
+   while ( (BIT(30)& ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X13C03C10);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X00000004);
+   WriteReg_32(DBSC_DBPDRGD0,0X08C0C170);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000022);
+   WriteReg_32(DBSC_DBPDRGD0,0X1000040B);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000023);
+   WriteReg_32(DBSC_DBPDRGD0,0X2D9C0B66);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000024);
+   WriteReg_32(DBSC_DBPDRGD0,0X2A88C400);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000025);
+   WriteReg_32(DBSC_DBPDRGD0,0X30005200);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000026);
+   WriteReg_32(DBSC_DBPDRGD0,0X0014A9C9);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000027);
+   WriteReg_32(DBSC_DBPDRGD0,0X00000D70);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000028);
+   WriteReg_32(DBSC_DBPDRGD0,0X00000004);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000029);
+   WriteReg_32(DBSC_DBPDRGD0,0X00000018);
+   WriteReg_32(DBSC_DBPDRGA0,0X0000002C);
+   WriteReg_32(DBSC_DBPDRGD0,0X81003047);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000020);
+   WriteReg_32(DBSC_DBPDRGD0,0X00181884);
+   WriteReg_32(DBSC_DBPDRGA0,0X0000001A);
+   WriteReg_32(DBSC_DBPDRGD0,0X13C03C10);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
-   WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X000000A7);
+   WriteReg_32(DBSC_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000A8);
+   WriteReg_32(DBSC_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000A9);
+   WriteReg_32(DBSC_DBPDRGD0,0X000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000C7);
+   WriteReg_32(DBSC_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000C8);
+   WriteReg_32(DBSC_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000C9);
+   WriteReg_32(DBSC_DBPDRGD0,0X000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000E7);
+   WriteReg_32(DBSC_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000E8);
+   WriteReg_32(DBSC_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000E9);
+   WriteReg_32(DBSC_DBPDRGD0,0X000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000107);
+   WriteReg_32(DBSC_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000108);
+   WriteReg_32(DBSC_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000109);
+   WriteReg_32(DBSC_DBPDRGD0,0X000D0D0D);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0X00010181);
+   WriteReg_32(DBSC_DBCMD,0x08000001);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0X00010601);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
    for (uint32_t i = 0; i<4; i++)
    {
-      WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
-      RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
-      WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
-      RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
-      WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
-      RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
+      WriteReg_32(DBSC_DBPDRGA0,0X000000B1 + i*0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00 ) >> 8;
+      WriteReg_32(DBSC_DBPDRGA0,0X000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF ) ;
+      WriteReg_32(DBSC_DBPDRGA0,0X000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007 ) ;
       if ( RegVal_R6 > 0 )
       {
-         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
+         WriteReg_32(DBSC_DBPDRGA0,0X000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0XFFFFFFF8 ) ;
 
-         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
-         WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
-         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
-         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
-         WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
+         WriteReg_32(DBSC_DBPDRGA0,0X000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
+         WriteReg_32(DBSC_DBPDRGA0,0X000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0XFFFFFF00 ) ;
+         WriteReg_32(DBSC_DBPDRGA0,0X000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | RegVal_R6);
       } else {
-         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
-         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
-         WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);
+         WriteReg_32(DBSC_DBPDRGA0,0X000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0XFFFFFFF8 ) ;
+         WriteReg_32(DBSC_DBPDRGA0,0X000000B2 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,RegVal_R2 | RegVal_R7);
 
-         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
-         RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
-         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
-         WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
+         WriteReg_32(DBSC_DBPDRGA0,0X000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0XFFFFFF00 ) ;
+         WriteReg_32(DBSC_DBPDRGA0,0X000000B0 + i*0x20);
+         WriteReg_32(DBSC_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
       }
    }
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X00000005);
+   WriteReg_32(DBSC_DBPDRGD0,0XC1AA00A0);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000A0);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000C0);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000E0);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000100);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0X00010801);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X00000005);
+   WriteReg_32(DBSC_DBPDRGD0,0XC1AA00B8);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0X0001F001);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X000000A0);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C000285);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000C0);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C000285);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000E0);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C000285);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000100);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C000285);
+   WriteReg_32(DBSC_DBPDRGA0,0X0000002C);
+   WriteReg_32(DBSC_DBPDRGD0,0X81003087);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0X00010401);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
    for (uint32_t i = 0; i < 4; i++)
    {
-          WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20);
-          RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8;
-          WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20);
-          RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);
+          WriteReg_32(DBSC_DBPDRGA0, 0X000000B1 + i * 0x20);
+          RegVal_R5 = (ReadReg_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 8;
+          WriteReg_32(DBSC_DBPDRGA0, 0X000000B4 + i * 0x20);
+          RegVal_R6 = (ReadReg_32(DBSC_DBPDRGD0) & 0x000000FF);
 
-          WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20);
-          RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
+          WriteReg_32(DBSC_DBPDRGA0, 0X000000B3 + i * 0x20);
+          RegVal_R7 = (ReadReg_32(DBSC_DBPDRGD0) & 0x00000007);
           RegVal_R12 = (RegVal_R5 >> 2);
           if (RegVal_R6 - RegVal_R12 > 0)
           {
-                  WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
-                  RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
+                  WriteReg_32(DBSC_DBPDRGA0, 0X000000B2 + i * 0x20);
+                  RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0XFFFFFFF8);
 
-                  WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
-                  WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2);
-                  WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
-                  RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
+                  WriteReg_32(DBSC_DBPDRGA0, 0X000000B2 + i * 0x20);
+                  WriteReg_32(DBSC_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2);
+                  WriteReg_32(DBSC_DBPDRGA0, 0X000000B0 + i * 0x20);
+                  RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0XFFFFFF00);
 
-                  WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
-                  WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
+                  WriteReg_32(DBSC_DBPDRGA0, 0X000000B0 + i * 0x20);
+                  WriteReg_32(DBSC_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
           }
           else
           {
-                  WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
-                  RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
-                  WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
-                  WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2);
-                  WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
-                  RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
-                  WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
-                  WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2);
+                  WriteReg_32(DBSC_DBPDRGA0, 0X000000B2 + i * 0x20);
+                  RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0XFFFFFFF8);
+                  WriteReg_32(DBSC_DBPDRGA0, 0X000000B2 + i * 0x20);
+                  WriteReg_32(DBSC_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2);
+                  WriteReg_32(DBSC_DBPDRGA0, 0X000000B0 + i * 0x20);
+                  RegVal_R2 = (ReadReg_32(DBSC_DBPDRGD0) & 0XFFFFFF00);
+                  WriteReg_32(DBSC_DBPDRGA0, 0X000000B0 + i * 0x20);
+                  WriteReg_32(DBSC_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2);
           }
    }
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
-   while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X000000A0);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000C0);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0X000000E0);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000100);
+   WriteReg_32(DBSC_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_DBPDRGD0,0X00015001);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000006);
+   while ( (BIT(0) & ReadReg_32(DBSC_DBPDRGD0)) == 0 );
 
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C700);
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
-   while ( (BIT(30)& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );
-   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
-   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000003);
+   WriteReg_32(DBSC_DBPDRGD0,0X0380C700);
+   WriteReg_32(DBSC_DBPDRGA0,0X00000007);
+   while ( (BIT(30)& ReadReg_32(DBSC_DBPDRGD0)) != 0 );
+   WriteReg_32(DBSC_DBPDRGA0,0X00000021);
+   WriteReg_32(DBSC_DBPDRGD0,0X0024643E);
 
-   WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
-   WriteReg_32(DBSC_V3M_DBBUS0CNF0,0x00010001);
-   WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200E);
-   WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860);
-   WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);
-   WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
-   WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
-   WriteReg_32(DBSC_V3M_DBACEN,0x00000001);
-   WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
+   WriteReg_32(DBSC_DBBUS0CNF1,0x00000000);
+   WriteReg_32(DBSC_DBBUS0CNF0,0x00010001);
+   WriteReg_32(DBSC_DBCALCNF,0x0100200E);
+   WriteReg_32(DBSC_DBRFCNF1,0x00081860);
+   WriteReg_32(DBSC_DBRFCNF2,0x00010000);
+   WriteReg_32(DBSC_DBDFICUPDCNF,0x40100001);
+   WriteReg_32(DBSC_DBRFEN,0x00000001);
+   WriteReg_32(DBSC_DBACEN,0x00000001);
+   WriteReg_32(DBSC_DBPDLK0,0X00000000);
    WriteReg_32(0xE67F0024, 0x00000001);
-   WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
+   WriteReg_32(DBSC_DBSYSCNT0,0x00000000);
 
    return 1;
 }