--- /dev/null
+#
+# Copyright (C) 2007 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=ixp4xx-microcode
+PKG_VERSION:=2.4
+PKG_RELEASE:=1
+
+PKG_SOURCE:=IPL_ixp400NpeLibrary-2_4.zip
+PKG_SOURCE_URL:=http://downloadmirror.intel.com/12954/eng/
+PKG_MD5SUM:=9a6dc3846041b899edf9eff8a906fb11
+
+PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/ixp4xx-microcode
+ SECTION:=net
+ CATEGORY:=Network
+ TITLE:=Microcode for the IXP4xx network engines
+ DEPENDS:=@TARGET_ixp4xx
+endef
+
+define Package/ixp4xx-microcode/description
+ This package contains the microcode needed to use the network engines in IXP4xx CPUs
+endef
+
+define Build/Prepare
+ rm -rf $(PKG_BUILD_DIR)
+ mkdir -p $(PKG_BUILD_DIR)
+ unzip -d $(PKG_BUILD_DIR)/ $(DL_DIR)/$(PKG_SOURCE)
+ mv $(PKG_BUILD_DIR)/ixp400_xscale_sw/src/npeDl/IxNpeMicrocode.c $(PKG_BUILD_DIR)/
+ rm -rf $(PKG_BUILD_DIR)/ixp400_xscale_sw
+ $(CP) ./src/* $(PKG_BUILD_DIR)/
+endef
+
+define Build/Compile
+ (cd $(PKG_BUILD_DIR); \
+ $(HOSTCC) -Wall IxNpeMicrocode.c -o IxNpeMicrocode; \
+ ./IxNpeMicrocode -be \
+ )
+endef
+
+define Package/ixp4xx-microcode/install
+ $(INSTALL_DIR) $(1)/lib/firmware
+ $(INSTALL_DIR) $(1)/usr/share/doc
+ $(INSTALL_BIN) $(PKG_BUILD_DIR)/NPE-B $(1)/lib/firmware/
+ $(INSTALL_BIN) $(PKG_BUILD_DIR)/NPE-C $(1)/lib/firmware/
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/LICENSE.IPL $(1)/usr/share/doc/
+endef
+
+$(eval $(call BuildPackage,ixp4xx-microcode))
--- /dev/null
+/*
+ * IxNpeMicrocode.h - Headerfile for compiling the Intel microcode C file
+ *
+ * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
+ *
+ * This file is released under the GPLv2
+ *
+ *
+ * compile with
+ *
+ * gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode
+ *
+ * Executing the resulting binary on your build-host creates the
+ * "NPE-[ABC].xxxxxxxx" files containing the selected microcode
+ *
+ * fetch the IxNpeMicrocode.c from the Intel Access Library.
+ * It will include this header.
+ *
+ * select Images for every NPE from the following
+ * (used C++ comments for easy uncommenting ....)
+ */
+
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_TSLOT_SWITCH
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
+// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0
+// #define IX_NPEDL_NPEIMAGE_NPEA_WEP
+
+
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEB_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
+
+
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
+// #define IX_NPEDL_NPEIMAGE_NPEC_DMA
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_SPAN
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_FIREWALL
+#define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_CCM_ETH
+// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_ETH_LEARN_FILTER_SPAN_FIREWALL
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
+// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
+#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
+
+
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <netinet/in.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <endian.h>
+#include <byteswap.h>
+#include <string.h>
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define to_le32(x) (x)
+#define to_be32(x) bswap_32(x)
+#else
+#define to_be32(x) (x)
+#define to_le32(x) bswap_32(x)
+#endif
+
+struct dl_image {
+ unsigned magic;
+ unsigned id;
+ unsigned size;
+ unsigned data[0];
+};
+
+const unsigned IxNpeMicrocode_array[];
+
+int main(int argc, char *argv[])
+{
+ struct dl_image *image = (struct dl_image *)IxNpeMicrocode_array;
+ int imgsiz, i, fd, cnt;
+ const unsigned *arrayptr = IxNpeMicrocode_array;
+ const char *names[] = { "IXP425", "IXP465", "unknown" };
+ int bigendian = 1;
+
+ if (argc > 1) {
+ if (!strcmp(argv[1], "-le"))
+ bigendian = 0;
+ else if (!strcmp(argv[1], "-be"))
+ bigendian = 1;
+ else {
+ printf("Usage: %s <-le|-be>\n", argv[0]);
+ return EXIT_FAILURE;
+ }
+ }
+
+ for (image = (struct dl_image *)arrayptr, cnt=0;
+ (image->id != 0xfeedf00d) && (image->magic == 0xfeedf00d);
+ image = (struct dl_image *)(arrayptr), cnt++)
+ {
+ unsigned char field[4];
+ imgsiz = image->size + 3;
+ *(unsigned*)field = to_be32(image->id);
+ char filename[40], slnk[10];
+
+ sprintf(filename, "NPE-%c.%08x", (field[0] & 0xf) + 'A',
+ image->id);
+ sprintf(slnk, "NPE-%c", (field[0] & 0xf) + 'A');
+ printf("Writing image: %s.NPE_%c Func: %2x Rev: %02x.%02x "
+ "Size: %5d to: '%s'\n",
+ names[field[0] >> 4], (field[0] & 0xf) + 'A',
+ field[1], field[2], field[3], imgsiz*4, filename);
+ fd = open(filename, O_CREAT | O_RDWR | O_TRUNC, 0644);
+ if (fd >= 0) {
+ for (i=0; i<imgsiz; i++) {
+ *(unsigned*)field = bigendian ?
+ to_be32(arrayptr[i]) :
+ to_le32(arrayptr[i]);
+ write(fd, field, sizeof(field));
+ }
+ close(fd);
+ unlink(slnk);
+ symlink(filename, slnk);
+ } else {
+ perror(filename);
+ }
+ arrayptr += imgsiz;
+ }
+ close(fd);
+ return 0;
+}
--- /dev/null
+INTEL(R) SOFTWARE LICENSE AGREEMENT
+
+Copyright (c) 2007, Intel Corporation.
+All rights reserved.
+
+Redistribution. Redistribution and use in binary form, without modification, are permitted
+provided that the following conditions are met:
+o Redistributions must reproduce the above copyright notice and the following disclaimer in the
+documentation and/or other materials provided with the distribution.
+o Neither the name of Intel Corporation nor the names of its suppliers may be used to endorse
+or promote products derived from this software without specific prior written permission.
+o No reverse engineering, decompilation, or disassembly of this software is permitted.
+
+Limited patent license. Intel Corporation grants a world-wide, royalty-free, non-exclusive
+license under patents it now or hereafter owns or controls to make, have made, use, import,
+offer to sell and sell (.Utilize.) this software, but solely to the extent that any such patent is
+necessary to Utilize the software alone. The patent license shall not apply to any combinations
+which include this software. No hardware per se is licensed hereunder.
+DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
# NOTE: for now it's for only IXP4xx in big endian mode
# list of supported boards, in "boardname machtypeid" format
-for board in "avila 526" "gateway7001 731" "nslu2 597" "nas100d 865" "wg302v2 890" "pronghornmetro 1040" "compex 1273" "wrt300nv2 1077" "loft 849" "dsmg600 964" "fsg3 1091"
+for board in "avila 526" "gateway7001 731" "nslu2 597" "nas100d 865" "wg302v2 890" "pronghornmetro 1040" "compex 1273" "wrt300nv2 1077" "loft 849" "dsmg600 964" "fsg3 1091" "ap1000 1543"
do
set -- $board
hexid=$(printf %x\\n $2)
FEATURES:=squashfs
SUBTARGETS=generic harddisk
-LINUX_VERSION:=2.6.21.7
+LINUX_VERSION:=2.6.23.12
include $(INCLUDE_DIR)/target.mk
+DEFAULT_PACKAGES += ixp4xx-microcode
+
$(eval $(call BuildTarget))
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_IP_NF_TFTP is not set
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
+CONFIG_IXP4XX_ETH=y
+# CONFIG_IXP4XX_HSS is not set
# CONFIG_IXP4XX_INDIRECT_PCI is not set
CONFIG_IXP4XX_MAC=y
CONFIG_IXP4XX_NPE=y
CONFIG_IXP4XX_NPE_FW_LOAD=y
-CONFIG_IXP4XX_NPE_FW_MTD=y
+CONFIG_IXP4XX_FW_LOAD=y
CONFIG_IXP4XX_QMGR=y
CONFIG_IXP4XX_CRYPTO=y
CONFIG_IXP4XX_WATCHDOG=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_LIBCRC32C is not set
# CONFIG_LLC2 is not set
+CONFIG_MACH_AP1000=y
CONFIG_MACH_AVILA=y
CONFIG_MACH_COMPEX=y
CONFIG_MACH_DSMG600=y
CONFIG_MACH_NAS100D=y
CONFIG_MACH_NSLU2=y
CONFIG_MACH_PRONGHORNMETRO=y
+CONFIG_MACH_SIDEWINDER=y
CONFIG_MACH_WG302V2=y
CONFIG_MACH_WRT300NV2=y
# CONFIG_MAC_PARTITION is not set
# CONFIG_RTC_DEBUG is not set
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
+CONFIG_RTC_DRV_DS1672=y
# CONFIG_RTC_DRV_DS1742 is not set
CONFIG_RTC_DRV_ISL1208=y
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_PCF8563=y
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_TEST is not set
# CONFIG_RTC_DRV_V3020 is not set
CONFIG_RTC_DRV_X1205=y
# CONFIG_USB_GTCO is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_UHCI_HCD=m
+# CONFIG_USER_NS is not set
CONFIG_VECTORS_BASE=0xffff0000
# CONFIG_VIA_RHINE is not set
CONFIG_VIA_VELOCITY=m
+++ /dev/null
-config IXP4XX_INCLUDE_UCODE
- bool "Build images with Intel IXP4xx Microcode"
- depends TARGET_ixp4xx
- default y
- help
- You must manually download IPL_ixp400NpeLibrary-2_4.zip from
- http://www.intel.com/design/network/products/npfamily/ixp400_archives.htm
- and put it in the dl/ directory of the build system.
- You will need to agree to the Intel Public License to do so - please do read it!
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
-UCODEFILE:=IPL_ixp400NpeLibrary-2_4.zip
-
-ifneq ($(CONFIG_IXP4XX_INCLUDE_UCODE),)
- define Require/npe-ucode
- [ -f $(DL_DIR)/$(UCODEFILE) ]
- endef
- define Build/Compile/npe
- $(MAKE) -C npe-ucode \
- BUILD_DIR="$(KDIR)" \
- TARGET="$(KDIR)" \
- compile
- endef
- define Image/Build/slug
+define Image/Build/slug
BIN_DIR=$(BIN_DIR) $(TOPDIR)/scripts/slugimage.pl \
- -L $(KDIR)/apex-nslu2-armeb.bin -m $(KDIR)/NPE-B \
+ -L $(KDIR)/apex-nslu2-armeb.bin \
-k $(BIN_DIR)/openwrt-nslu2-zImage \
-r rootfs:$(BIN_DIR)/openwrt-$(BOARD)-$(1).img \
-p -o $(BIN_DIR)/openwrt-nslu2-$(1).bin
BIN_DIR=$(BIN_DIR) $(TOPDIR)/scripts/slugimage.pl \
- -F -L $(KDIR)/apex-nslu2-armeb.bin -m $(KDIR)/NPE-B \
+ -F -L $(KDIR)/apex-nslu2-armeb.bin \
-k $(BIN_DIR)/openwrt-nslu2-zImage \
-r rootfs:$(BIN_DIR)/openwrt-$(BOARD)-$(1).img \
-p -o $(BIN_DIR)/openwrt-nslu2-$(1)-16mb.bin
- endef
-endif
+endef
define Build/Compile
$(MAKE) -C apex \
BUILD_DIR="$(KDIR)" \
TARGET="$(KDIR)" \
compile
- $(call Build/Compile/npe)
endef
define Build/Clean
$(MAKE) -C apex clean
- $(MAKE) -C npe-ucode clean
endef
define Image/Prepare
define Image/BuildKernel
cp $(KDIR)/zImage $(BIN_DIR)/openwrt-$(BOARD)-zImage
-# $(shell BIN_DIR=$(BIN_DIR) $(TOPDIR)/scripts/arm-magic.sh)
BIN_DIR=$(BIN_DIR) $(TOPDIR)/scripts/arm-magic.sh
endef
endef
$(eval $(call BuildImage))
-
-$(eval $(call Require,npe-ucode, \
- You must manually download $(UCODEFILE) from \\\
- http://www.intel.com/design/network/products/npfamily/ixp400_archives.htm \\\
- and put it in $(DL_DIR). \\\
- You will need to agree to the Intel Public License to do so - please do read it! \
-))
+++ /dev/null
-#
-# Copyright (C) 2006 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-# $Id$
-
-include $(TOPDIR)/rules.mk
-
-PKG_NAME:=npe-ucode
-PKG_VERSION:=2.4
-PKG_RELEASE:=2
-
-PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE:=IPL_ixp400NpeLibrary-2_4.zip
-
-include $(INCLUDE_DIR)/package.mk
-
-define Build/Prepare
- rm -rf $(PKG_BUILD_DIR)
- mkdir -p $(PKG_BUILD_DIR)
- unzip -d $(PKG_BUILD_DIR)/ $(DL_DIR)/$(PKG_SOURCE)
- mv $(PKG_BUILD_DIR)/ixp400_xscale_sw/src/npeDl/IxNpeMicrocode.c $(PKG_BUILD_DIR)/
- rm -rf $(PKG_BUILD_DIR)/ixp400_xscale_sw
- $(CP) ./src/* $(PKG_BUILD_DIR)/
-endef
-
-define Build/Compile
- (cd $(PKG_BUILD_DIR); \
- $(HOSTCC) -Wall IxNpeMicrocode.c -o IxNpeMicrocode; \
- ./IxNpeMicrocode -be \
- )
-endef
-
-define Build/InstallDev
- $(INSTALL_BIN) $(PKG_BUILD_DIR)/NPE-B $(TARGET)/
- $(INSTALL_BIN) $(PKG_BUILD_DIR)/NPE-C $(TARGET)/
-endef
-
-$(eval $(call Build/DefaultTargets))
+++ /dev/null
-/*
- * IxNpeMicrocode.h - Headerfile for compiling the Intel microcode C file
- *
- * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt@innominate.com>
- *
- * This file is released under the GPLv2
- *
- *
- * compile with
- *
- * gcc -Wall IxNpeMicrocode.c -o IxNpeMicrocode
- *
- * Executing the resulting binary on your build-host creates the
- * "NPE-[ABC].xxxxxxxx" files containing the selected microcode
- *
- * fetch the IxNpeMicrocode.c from the Intel Access Library.
- * It will include this header.
- *
- * select Images for every NPE from the following
- * (used C++ comments for easy uncommenting ....)
- */
-
-// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
-// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
-// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
-// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_TSLOT_SWITCH
-// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
-// #define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
-// #define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
-// #define IX_NPEDL_NPEIMAGE_NPEA_DMA
-// #define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
-// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
-// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
-// #define IX_NPEDL_NPEIMAGE_NPEA_HSS0
-// #define IX_NPEDL_NPEIMAGE_NPEA_WEP
-
-
-// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
-// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
-// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
-// #define IX_NPEDL_NPEIMAGE_NPEB_DMA
-// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-// #define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
-
-
-// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_MASK_FIREWALL_VLAN_QOS_HDR_CONV_EXTMIB
-// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_VLAN_QOS_HDR_CONV_EXTMIB
-// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_MASK_FIREWALL_VLAN_QOS_EXTMIB
-// #define IX_NPEDL_NPEIMAGE_NPEC_DMA
-// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_SPAN
-// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_ETH_LEARN_FILTER_FIREWALL
-#define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_AES_CCM_ETH
-// #define IX_NPEDL_NPEIMAGE_NPEC_CRYPTO_ETH_LEARN_FILTER_SPAN_FIREWALL
-// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-// #define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
-
-
-#include <stdio.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <netinet/in.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <errno.h>
-#include <endian.h>
-#include <byteswap.h>
-#include <string.h>
-
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-#define to_le32(x) (x)
-#define to_be32(x) bswap_32(x)
-#else
-#define to_be32(x) (x)
-#define to_le32(x) bswap_32(x)
-#endif
-
-struct dl_image {
- unsigned magic;
- unsigned id;
- unsigned size;
- unsigned data[0];
-};
-
-const unsigned IxNpeMicrocode_array[];
-
-int main(int argc, char *argv[])
-{
- struct dl_image *image = (struct dl_image *)IxNpeMicrocode_array;
- int imgsiz, i, fd, cnt;
- const unsigned *arrayptr = IxNpeMicrocode_array;
- const char *names[] = { "IXP425", "IXP465", "unknown" };
- int bigendian = 1;
-
- if (argc > 1) {
- if (!strcmp(argv[1], "-le"))
- bigendian = 0;
- else if (!strcmp(argv[1], "-be"))
- bigendian = 1;
- else {
- printf("Usage: %s <-le|-be>\n", argv[0]);
- return EXIT_FAILURE;
- }
- }
-
- for (image = (struct dl_image *)arrayptr, cnt=0;
- (image->id != 0xfeedf00d) && (image->magic == 0xfeedf00d);
- image = (struct dl_image *)(arrayptr), cnt++)
- {
- unsigned char field[4];
- imgsiz = image->size + 3;
- *(unsigned*)field = to_be32(image->id);
- char filename[40], slnk[10];
-
- sprintf(filename, "NPE-%c.%08x", (field[0] & 0xf) + 'A',
- image->id);
- sprintf(slnk, "NPE-%c", (field[0] & 0xf) + 'A');
- printf("Writing image: %s.NPE_%c Func: %2x Rev: %02x.%02x "
- "Size: %5d to: '%s'\n",
- names[field[0] >> 4], (field[0] & 0xf) + 'A',
- field[1], field[2], field[3], imgsiz*4, filename);
- fd = open(filename, O_CREAT | O_RDWR | O_TRUNC, 0644);
- if (fd >= 0) {
- for (i=0; i<imgsiz; i++) {
- *(unsigned*)field = bigendian ?
- to_be32(arrayptr[i]) :
- to_le32(arrayptr[i]);
- write(fd, field, sizeof(field));
- }
- close(fd);
- unlink(slnk);
- symlink(filename, slnk);
- } else {
- perror(filename);
- }
- arrayptr += imgsiz;
- }
- close(fd);
- return 0;
-}
--- /dev/null
+diff -uprN linux-2.6.23.orig/arch/arm/kernel/relocate_kernel.S linux-2.6.23/arch/arm/kernel/relocate_kernel.S
+--- linux-2.6.23.orig/arch/arm/kernel/relocate_kernel.S 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/arch/arm/kernel/relocate_kernel.S 2007-10-09 22:19:32.000000000 -0500
+@@ -7,6 +7,23 @@
+ .globl relocate_new_kernel
+ relocate_new_kernel:
+
++ /* Move boot params back to where the kernel expects them */
++
++ ldr r0,kexec_boot_params_address
++ teq r0,#0
++ beq 8f
++
++ ldr r1,kexec_boot_params_copy
++ mov r6,#KEXEC_BOOT_PARAMS_SIZE/4
++7:
++ ldr r5,[r1],#4
++ str r5,[r0],#4
++ subs r6,r6,#1
++ bne 7b
++
++8:
++ /* Boot params moved, now go on with the kernel */
++
+ ldr r0,kexec_indirection_page
+ ldr r1,kexec_start_address
+
+@@ -50,7 +67,7 @@ relocate_new_kernel:
+ mov lr,r1
+ mov r0,#0
+ ldr r1,kexec_mach_type
+- mov r2,#0
++ ldr r2,kexec_boot_params_address
+ mov pc,lr
+
+ .globl kexec_start_address
+@@ -65,6 +82,16 @@ kexec_indirection_page:
+ kexec_mach_type:
+ .long 0x0
+
++ /* phy addr where new kernel will expect to find boot params */
++ .globl kexec_boot_params_address
++kexec_boot_params_address:
++ .long 0x0
++
++ /* phy addr where old kernel put a copy of orig boot params */
++ .globl kexec_boot_params_copy
++kexec_boot_params_copy:
++ .long 0x0
++
+ relocate_new_kernel_end:
+
+ .globl relocate_new_kernel_size
+diff -uprN linux-2.6.23.orig/arch/arm/kernel/setup.c linux-2.6.23/arch/arm/kernel/setup.c
+--- linux-2.6.23.orig/arch/arm/kernel/setup.c 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/arch/arm/kernel/setup.c 2007-10-09 20:06:10.000000000 -0500
+@@ -24,6 +24,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/smp.h>
+ #include <linux/fs.h>
++#include <linux/kexec.h>
+
+ #include <asm/cpu.h>
+ #include <asm/elf.h>
+@@ -770,6 +771,23 @@ static int __init customize_machine(void
+ }
+ arch_initcall(customize_machine);
+
++#ifdef CONFIG_KEXEC
++
++/* Physical addr of where the boot params should be for this machine */
++extern unsigned long kexec_boot_params_address;
++
++/* Physical addr of the buffer into which the boot params are copied */
++extern unsigned long kexec_boot_params_copy;
++
++/* Pointer to the boot params buffer, for manipulation and display */
++unsigned long kexec_boot_params;
++EXPORT_SYMBOL(kexec_boot_params);
++
++/* The buffer itself - make sure it is sized correctly */
++static unsigned long kexec_boot_params_buf[(KEXEC_BOOT_PARAMS_SIZE + 3) / 4];
++
++#endif
++
+ void __init setup_arch(char **cmdline_p)
+ {
+ struct tag *tags = (struct tag *)&init_tags;
+@@ -788,6 +806,18 @@ void __init setup_arch(char **cmdline_p)
+ else if (mdesc->boot_params)
+ tags = phys_to_virt(mdesc->boot_params);
+
++#ifdef CONFIG_KEXEC
++ kexec_boot_params_copy = virt_to_phys(kexec_boot_params_buf);
++ kexec_boot_params = (unsigned long)kexec_boot_params_buf;
++ if (__atags_pointer) {
++ kexec_boot_params_address = __atags_pointer;
++ memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE);
++ } else if (mdesc->boot_params) {
++ kexec_boot_params_address = mdesc->boot_params;
++ memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE);
++ }
++#endif
++
+ /*
+ * If we have the old style parameters, convert them to
+ * a tag list.
+diff -uprN linux-2.6.23.orig/include/asm-arm/kexec.h linux-2.6.23/include/asm-arm/kexec.h
+--- linux-2.6.23.orig/include/asm-arm/kexec.h 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/include/asm-arm/kexec.h 2007-10-09 22:19:32.000000000 -0500
+@@ -14,6 +14,8 @@
+
+ #define KEXEC_ARCH KEXEC_ARCH_ARM
+
++#define KEXEC_BOOT_PARAMS_SIZE 1536
++
+ #ifndef __ASSEMBLY__
+
+ struct kimage;
--- /dev/null
+diff -uprN linux-2.6.23.orig/drivers/net/via-velocity.c linux-2.6.23/drivers/net/via-velocity.c
+--- linux-2.6.23.orig/drivers/net/via-velocity.c 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/drivers/net/via-velocity.c 2007-10-11 00:53:45.000000000 -0500
+@@ -96,11 +96,31 @@ MODULE_AUTHOR("VIA Networking Technologi
+ MODULE_LICENSE("GPL");
+ MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
+
++/* Valid values for vdebug (additive, this is a bitmask):
++ * 0x00 => off
++ * 0x01 => always on
++ * 0x02 => additional detail on tx (rx, too, if anyone implements same)
++ * 0x04 => detail the initialization process
++ * 0x08 => spot debug detail; to be used as developers see fit
++ */
++static int vdebug = 0;
++
++/* HAIL - these macros are for the normal 0x01-type tracing... */
++#define HAIL(S) \
++ if (vdebug&1) printk(KERN_NOTICE "%s\n", (S));
++#define HAILS(S,T) \
++ if (vdebug&1) printk(KERN_NOTICE "%s -> status=0x%x\n", (S), (T));
++
+ #define VELOCITY_PARAM(N,D) \
+ static int N[MAX_UNITS]=OPTION_DEFAULT;\
+ module_param_array(N, int, NULL, 0); \
+ MODULE_PARM_DESC(N, D);
+
++#define VELO_DEBUG_MIN 0
++#define VELO_DEBUG_MAX 255
++#define VELO_DEBUG_DEF 0
++VELOCITY_PARAM(velo_debug, "Debug level");
++
+ #define RX_DESC_MIN 64
+ #define RX_DESC_MAX 255
+ #define RX_DESC_DEF 64
+@@ -385,12 +405,12 @@ static void __devinit velocity_set_int_o
+ if (val == -1)
+ *opt = def;
+ else if (val < min || val > max) {
+- VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
+- devname, name, min, max);
++ VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "via-velocity: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
++ name, min, max);
+ *opt = def;
+ } else {
+- VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
+- devname, name, val);
++ VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "via-velocity: set value of parameter %s to %d\n",
++ name, val);
+ *opt = val;
+ }
+ }
+@@ -415,12 +435,12 @@ static void __devinit velocity_set_bool_
+ if (val == -1)
+ *opt |= (def ? flag : 0);
+ else if (val < 0 || val > 1) {
+- printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
+- devname, name);
++ printk(KERN_NOTICE "via-velocity: the value of parameter %s is invalid, the valid range is (0-1)\n",
++ name);
+ *opt |= (def ? flag : 0);
+ } else {
+- printk(KERN_INFO "%s: set parameter %s to %s\n",
+- devname, name, val ? "TRUE" : "FALSE");
++ printk(KERN_INFO "via-velocity: set parameter %s to %s\n",
++ name, val ? "TRUE" : "FALSE");
+ *opt |= (val ? flag : 0);
+ }
+ }
+@@ -438,6 +458,7 @@ static void __devinit velocity_set_bool_
+ static void __devinit velocity_get_options(struct velocity_opt *opts, int index, char *devname)
+ {
+
++ velocity_set_int_opt(&opts->velo_debug, velo_debug[index], VELO_DEBUG_MIN, VELO_DEBUG_MAX, VELO_DEBUG_DEF, "velo_debug", devname);
+ velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
+ velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
+ velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
+@@ -452,6 +473,7 @@ static void __devinit velocity_get_optio
+ velocity_set_int_opt((int *) &opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
+ velocity_set_int_opt((int *) &opts->int_works, int_works[index], INT_WORKS_MIN, INT_WORKS_MAX, INT_WORKS_DEF, "Interrupt service works", devname);
+ opts->numrx = (opts->numrx & ~3);
++ vdebug = opts->velo_debug;
+ }
+
+ /**
+@@ -466,6 +488,8 @@ static void velocity_init_cam_filter(str
+ {
+ struct mac_regs __iomem * regs = vptr->mac_regs;
+
++ HAIL("velocity_init_cam_filter");
++
+ /* Turn on MCFG_PQEN, turn off MCFG_RTGOPT */
+ WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, ®s->MCFG);
+ WORD_REG_BITS_ON(MCFG_VIDFR, ®s->MCFG);
+@@ -484,14 +508,12 @@ static void velocity_init_cam_filter(str
+ WORD_REG_BITS_ON(MCFG_RTGOPT, ®s->MCFG);
+
+ mac_set_cam(regs, 0, (u8 *) & (vptr->options.vid), VELOCITY_VLAN_ID_CAM);
+- vptr->vCAMmask[0] |= 1;
+- mac_set_cam_mask(regs, vptr->vCAMmask, VELOCITY_VLAN_ID_CAM);
+ } else {
+ u16 temp = 0;
+ mac_set_cam(regs, 0, (u8 *) &temp, VELOCITY_VLAN_ID_CAM);
+- temp = 1;
+- mac_set_cam_mask(regs, (u8 *) &temp, VELOCITY_VLAN_ID_CAM);
+ }
++ vptr->vCAMmask[0] |= 1;
++ mac_set_cam_mask(regs, vptr->vCAMmask, VELOCITY_VLAN_ID_CAM);
+ }
+
+ /**
+@@ -508,13 +530,15 @@ static void velocity_rx_reset(struct vel
+ struct mac_regs __iomem * regs = vptr->mac_regs;
+ int i;
+
++ HAIL("velocity_rx_reset");
+ vptr->rd_dirty = vptr->rd_filled = vptr->rd_curr = 0;
+
+ /*
+ * Init state, all RD entries belong to the NIC
+ */
+ for (i = 0; i < vptr->options.numrx; ++i)
+- vptr->rd_ring[i].rdesc0.owner = OWNED_BY_NIC;
++ /* vptr->rd_ring[i].rdesc0.owner = OWNED_BY_NIC; BE */
++ vptr->rd_ring[i].rdesc0 |= cpu_to_le32(BE_OWNED_BY_NIC); /* BE */
+
+ writew(vptr->options.numrx, ®s->RBRDU);
+ writel(vptr->rd_pool_dma, ®s->RDBaseLo);
+@@ -537,12 +561,15 @@ static void velocity_init_registers(stru
+ struct mac_regs __iomem * regs = vptr->mac_regs;
+ int i, mii_status;
+
++ if (vdebug&5) printk(KERN_NOTICE "velocity_init_registers: entering\n");
++
+ mac_wol_reset(regs);
+
+ switch (type) {
+ case VELOCITY_INIT_RESET:
+ case VELOCITY_INIT_WOL:
+
++ if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: RESET or WOL\n");
+ netif_stop_queue(vptr->dev);
+
+ /*
+@@ -570,12 +597,13 @@ static void velocity_init_registers(stru
+
+ case VELOCITY_INIT_COLD:
+ default:
++ if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: COLD or default\n");
+ /*
+ * Do reset
+ */
+ velocity_soft_reset(vptr);
++ if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: soft reset complete.\n");
+ mdelay(5);
+-
+ mac_eeprom_reload(regs);
+ for (i = 0; i < 6; i++) {
+ writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
+@@ -593,11 +621,16 @@ static void velocity_init_registers(stru
+ */
+ BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), ®s->CFGB);
+
++ if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: Initializing CAM filter\n");
+ /*
+ * Init CAM filter
+ */
++ if (vdebug&8) printk(KERN_NOTICE "velocity: spot debug: about to init CAM filters\n");
++ mdelay(5); /* MJW - ARM processors, kernel 2.6.19 - this fixes oopses and hangs */
+ velocity_init_cam_filter(vptr);
++ if (vdebug&8) printk(KERN_NOTICE "velocity: spot debug: init CAM filters complete\n");
+
++ if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: Setting packet filter\n");
+ /*
+ * Set packet filter: Receive directed and broadcast address
+ */
+@@ -607,10 +640,12 @@ static void velocity_init_registers(stru
+ * Enable MII auto-polling
+ */
+ enable_mii_autopoll(regs);
++ if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: enable_mii_autopoll complete.\n");
+
+ vptr->int_mask = INT_MASK_DEF;
+
+- writel(cpu_to_le32(vptr->rd_pool_dma), ®s->RDBaseLo);
++ /* writel(cpu_to_le32(vptr->rd_pool_dma), ®s->RDBaseLo); BE */
++ writel((vptr->rd_pool_dma), ®s->RDBaseLo); /* BE */
+ writew(vptr->options.numrx - 1, ®s->RDCSize);
+ mac_rx_queue_run(regs);
+ mac_rx_queue_wake(regs);
+@@ -618,10 +653,13 @@ static void velocity_init_registers(stru
+ writew(vptr->options.numtx - 1, ®s->TDCSize);
+
+ for (i = 0; i < vptr->num_txq; i++) {
+- writel(cpu_to_le32(vptr->td_pool_dma[i]), &(regs->TDBaseLo[i]));
++ /* writel(cpu_to_le32(vptr->td_pool_dma[i]), &(regs->TDBaseLo[i])); BE */
++ writel((vptr->td_pool_dma[i]), &(regs->TDBaseLo[i])); /* BE */
+ mac_tx_queue_run(regs, i);
+ }
+
++ if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: DMA settings complete.\n");
++
+ init_flow_control_register(vptr);
+
+ writel(CR0_STOP, ®s->CR0Clr);
+@@ -640,8 +678,10 @@ static void velocity_init_registers(stru
+
+ enable_flow_control_ability(vptr);
+ mac_hw_mibs_init(regs);
++ if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: Set interrupt mask\n");
+ mac_write_int_mask(vptr->int_mask, regs);
+ mac_clear_isr(regs);
++ if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: complete.\n");
+
+ }
+ }
+@@ -659,6 +699,7 @@ static int velocity_soft_reset(struct ve
+ struct mac_regs __iomem * regs = vptr->mac_regs;
+ int i = 0;
+
++ HAIL("velocity_soft_reset");
+ writel(CR0_SFRST, ®s->CR0Set);
+
+ for (i = 0; i < W_MAX_TIMEOUT; i++) {
+@@ -722,6 +763,7 @@ static int __devinit velocity_found1(str
+ VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
+ printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
+ printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
++ printk(KERN_INFO "BE support, misc. fixes MJW 01Jan2007 - may be unstable\n");
+ first = 0;
+ }
+
+@@ -934,6 +976,7 @@ static int velocity_init_rings(struct ve
+ dma_addr_t pool_dma;
+ u8 *pool;
+
++ HAIL("velocity_init_rings");
+ /*
+ * Allocate all RD/TD rings a single pool
+ */
+@@ -996,6 +1039,7 @@ static int velocity_init_rings(struct ve
+ static void velocity_free_rings(struct velocity_info *vptr)
+ {
+ int size;
++ HAIL("velocity_free_rings");
+
+ size = vptr->options.numrx * sizeof(struct rx_desc) +
+ vptr->options.numtx * sizeof(struct tx_desc) * vptr->num_txq;
+@@ -1012,6 +1056,7 @@ static inline void velocity_give_many_rx
+ struct mac_regs __iomem *regs = vptr->mac_regs;
+ int avail, dirty, unusable;
+
++ HAIL("velocity_give_many_rx_descs");
+ /*
+ * RD number must be equal to 4X per hardware spec
+ * (programming guide rev 1.20, p.13)
+@@ -1025,7 +1070,8 @@ static inline void velocity_give_many_rx
+ dirty = vptr->rd_dirty - unusable;
+ for (avail = vptr->rd_filled & 0xfffc; avail; avail--) {
+ dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
+- vptr->rd_ring[dirty].rdesc0.owner = OWNED_BY_NIC;
++ /* vptr->rd_ring[dirty].rdesc0.owner = OWNED_BY_NIC; BE */
++ vptr->rd_ring[dirty].rdesc0 |= cpu_to_le32(BE_OWNED_BY_NIC); /* BE */
+ }
+
+ writew(vptr->rd_filled & 0xfffc, ®s->RBRDU);
+@@ -1035,12 +1081,14 @@ static inline void velocity_give_many_rx
+ static int velocity_rx_refill(struct velocity_info *vptr)
+ {
+ int dirty = vptr->rd_dirty, done = 0, ret = 0;
++ HAIL("velocity_rx_refill");
+
+ do {
+ struct rx_desc *rd = vptr->rd_ring + dirty;
+
+ /* Fine for an all zero Rx desc at init time as well */
+- if (rd->rdesc0.owner == OWNED_BY_NIC)
++ /* if (rd->rdesc0.owner == OWNED_BY_NIC) BE */
++ if (rd->rdesc0 & cpu_to_le32(BE_OWNED_BY_NIC)) /* BE */
+ break;
+
+ if (!vptr->rd_info[dirty].skb) {
+@@ -1075,6 +1123,7 @@ static int velocity_init_rd_ring(struct
+ unsigned int rsize = sizeof(struct velocity_rd_info) *
+ vptr->options.numrx;
+
++ HAIL("velocity_init_rd_ring");
+ vptr->rd_info = kmalloc(rsize, GFP_KERNEL);
+ if(vptr->rd_info == NULL)
+ goto out;
+@@ -1104,6 +1153,7 @@ static void velocity_free_rd_ring(struct
+ {
+ int i;
+
++ HAIL("velocity_free_rd_ring");
+ if (vptr->rd_info == NULL)
+ return;
+
+@@ -1145,6 +1195,7 @@ static int velocity_init_td_ring(struct
+ unsigned int tsize = sizeof(struct velocity_td_info) *
+ vptr->options.numtx;
+
++ HAIL("velocity_init_td_ring");
+ /* Init the TD ring entries */
+ for (j = 0; j < vptr->num_txq; j++) {
+ curr = vptr->td_pool_dma[j];
+@@ -1181,6 +1232,7 @@ static void velocity_free_td_ring_entry(
+ struct velocity_td_info * td_info = &(vptr->td_infos[q][n]);
+ int i;
+
++ HAIL("velocity_free_td_ring_entry");
+ if (td_info == NULL)
+ return;
+
+@@ -1210,6 +1262,7 @@ static void velocity_free_td_ring(struct
+ {
+ int i, j;
+
++ HAIL("velocity_free_td_ring");
+ for (j = 0; j < vptr->num_txq; j++) {
+ if (vptr->td_infos[j] == NULL)
+ continue;
+@@ -1237,34 +1290,42 @@ static int velocity_rx_srv(struct veloci
+ struct net_device_stats *stats = &vptr->stats;
+ int rd_curr = vptr->rd_curr;
+ int works = 0;
++ u16 wRSR; /* BE */
+
++ HAILS("velocity_rx_srv", status);
+ do {
+ struct rx_desc *rd = vptr->rd_ring + rd_curr;
+
+ if (!vptr->rd_info[rd_curr].skb)
+ break;
+
+- if (rd->rdesc0.owner == OWNED_BY_NIC)
++ /* if (rd->rdesc0.owner == OWNED_BY_NIC) BE */
++ if (rd->rdesc0 & cpu_to_le32(BE_OWNED_BY_NIC)) /* BE */
+ break;
+
+ rmb();
+
++ wRSR = (u16)(cpu_to_le32(rd->rdesc0)); /* BE */
+ /*
+ * Don't drop CE or RL error frame although RXOK is off
+ */
+- if ((rd->rdesc0.RSR & RSR_RXOK) || (!(rd->rdesc0.RSR & RSR_RXOK) && (rd->rdesc0.RSR & (RSR_CE | RSR_RL)))) {
++ /* if ((rd->rdesc0.RSR & RSR_RXOK) || (!(rd->rdesc0.RSR & RSR_RXOK) && (rd->rdesc0.RSR & (RSR_CE | RSR_RL)))) { BE */
++ if ((wRSR & RSR_RXOK) || (!(wRSR & RSR_RXOK) && (wRSR & (RSR_CE | RSR_RL)))) { /* BE */
+ if (velocity_receive_frame(vptr, rd_curr) < 0)
+ stats->rx_dropped++;
+ } else {
+- if (rd->rdesc0.RSR & RSR_CRC)
++ /* if (rd->rdesc0.RSR & RSR_CRC) BE */
++ if (wRSR & RSR_CRC) /* BE */
+ stats->rx_crc_errors++;
+- if (rd->rdesc0.RSR & RSR_FAE)
++ /* if (rd->rdesc0.RSR & RSR_FAE) BE */
++ if (wRSR & RSR_FAE) /* BE */
+ stats->rx_frame_errors++;
+
+ stats->rx_dropped++;
+ }
+
+- rd->inten = 1;
++ /* rd->inten = 1; BE */
++ rd->ltwo |= cpu_to_le32(BE_INT_ENABLE); /* BE */
+
+ vptr->dev->last_rx = jiffies;
+
+@@ -1295,13 +1356,21 @@ static int velocity_rx_srv(struct veloci
+
+ static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
+ {
++ u8 bCSM;
++ HAIL("velocity_rx_csum");
+ skb->ip_summed = CHECKSUM_NONE;
+
+- if (rd->rdesc1.CSM & CSM_IPKT) {
+- if (rd->rdesc1.CSM & CSM_IPOK) {
+- if ((rd->rdesc1.CSM & CSM_TCPKT) ||
+- (rd->rdesc1.CSM & CSM_UDPKT)) {
+- if (!(rd->rdesc1.CSM & CSM_TUPOK)) {
++// if (rd->rdesc1.CSM & CSM_IPKT) {
++// if (rd->rdesc1.CSM & CSM_IPOK) {
++// if ((rd->rdesc1.CSM & CSM_TCPKT) ||
++// (rd->rdesc1.CSM & CSM_UDPKT)) {
++// if (!(rd->rdesc1.CSM & CSM_TUPOK)) {
++ bCSM = (u8)(cpu_to_le32(rd->rdesc1) >> 16); /* BE */
++ if (bCSM & CSM_IPKT) {
++ if (bCSM & CSM_IPOK) {
++ if ((bCSM & CSM_TCPKT) ||
++ (bCSM & CSM_UDPKT)) {
++ if (!(bCSM & CSM_TUPOK)) { /* BE */
+ return;
+ }
+ }
+@@ -1327,9 +1396,11 @@ static inline int velocity_rx_copy(struc
+ {
+ int ret = -1;
+
++ HAIL("velocity_rx_copy");
+ if (pkt_size < rx_copybreak) {
+ struct sk_buff *new_skb;
+
++ HAIL("velocity_rx_copy (working...)");
+ new_skb = dev_alloc_skb(pkt_size + 2);
+ if (new_skb) {
+ new_skb->dev = vptr->dev;
+@@ -1360,10 +1431,12 @@ static inline int velocity_rx_copy(struc
+ static inline void velocity_iph_realign(struct velocity_info *vptr,
+ struct sk_buff *skb, int pkt_size)
+ {
++ HAIL("velocity_iph_realign");
+ /* FIXME - memmove ? */
+ if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
+ int i;
+
++ HAIL("velocity_iph_realign (working...)");
+ for (i = pkt_size; i >= 0; i--)
+ *(skb->data + i + 2) = *(skb->data + i);
+ skb_reserve(skb, 2);
+@@ -1382,19 +1455,27 @@ static inline void velocity_iph_realign(
+ static int velocity_receive_frame(struct velocity_info *vptr, int idx)
+ {
+ void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
++ u16 pkt_len; /* BE */
++ u16 wRSR; /* BE */
++ struct sk_buff *skb;
+ struct net_device_stats *stats = &vptr->stats;
+ struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
+ struct rx_desc *rd = &(vptr->rd_ring[idx]);
+- int pkt_len = rd->rdesc0.len;
+- struct sk_buff *skb;
++ /* int pkt_len = rd->rdesc0.len BE */;
++
++ pkt_len = ((cpu_to_le32(rd->rdesc0) >> 16) & 0x00003FFFUL); /* BE */
++ wRSR = (u16)(cpu_to_le32(rd->rdesc0)); /* BE */
+
+- if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
++ HAIL("velocity_receive_frame");
++ /* if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) { BE */
++ if (wRSR & (RSR_STP | RSR_EDP)) { /* BE */
+ VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
+ stats->rx_length_errors++;
+ return -EINVAL;
+ }
+
+- if (rd->rdesc0.RSR & RSR_MAR)
++ /* if (rd->rdesc0.RSR & RSR_MAR) BE */
++ if (wRSR & RSR_MAR) /* BE */
+ vptr->stats.multicast++;
+
+ skb = rd_info->skb;
+@@ -1407,7 +1488,8 @@ static int velocity_receive_frame(struct
+ */
+
+ if (vptr->flags & VELOCITY_FLAGS_VAL_PKT_LEN) {
+- if (rd->rdesc0.RSR & RSR_RL) {
++ /* if (rd->rdesc0.RSR & RSR_RL) { BE */
++ if (wRSR & RSR_RL) { /* BE */
+ stats->rx_length_errors++;
+ return -EINVAL;
+ }
+@@ -1451,6 +1533,7 @@ static int velocity_alloc_rx_buf(struct
+ struct rx_desc *rd = &(vptr->rd_ring[idx]);
+ struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
+
++ HAIL("velocity_alloc_rx_buf");
+ rd_info->skb = dev_alloc_skb(vptr->rx_buf_sz + 64);
+ if (rd_info->skb == NULL)
+ return -ENOMEM;
+@@ -1468,10 +1551,14 @@ static int velocity_alloc_rx_buf(struct
+ */
+
+ *((u32 *) & (rd->rdesc0)) = 0;
+- rd->len = cpu_to_le32(vptr->rx_buf_sz);
+- rd->inten = 1;
++ /* rd->len = cpu_to_le32(vptr->rx_buf_sz); BE */
++ /* rd->inten = 1; BE */
+ rd->pa_low = cpu_to_le32(rd_info->skb_dma);
+- rd->pa_high = 0;
++ /* rd->pa_high = 0; BE */
++ rd->ltwo &= cpu_to_le32(0xC000FFFFUL); /* BE */
++ rd->ltwo |= cpu_to_le32((vptr->rx_buf_sz << 16)); /* BE */
++ rd->ltwo |= cpu_to_le32(BE_INT_ENABLE); /* BE */
++ rd->ltwo &= cpu_to_le32(0xFFFF0000UL); /* BE */
+ return 0;
+ }
+
+@@ -1492,9 +1579,11 @@ static int velocity_tx_srv(struct veloci
+ int full = 0;
+ int idx;
+ int works = 0;
++ u16 wTSR; /* BE */
+ struct velocity_td_info *tdinfo;
+ struct net_device_stats *stats = &vptr->stats;
+
++ HAILS("velocity_tx_srv", status);
+ for (qnum = 0; qnum < vptr->num_txq; qnum++) {
+ for (idx = vptr->td_tail[qnum]; vptr->td_used[qnum] > 0;
+ idx = (idx + 1) % vptr->options.numtx) {
+@@ -1505,22 +1594,29 @@ static int velocity_tx_srv(struct veloci
+ td = &(vptr->td_rings[qnum][idx]);
+ tdinfo = &(vptr->td_infos[qnum][idx]);
+
+- if (td->tdesc0.owner == OWNED_BY_NIC)
++ /* if (td->tdesc0.owner == OWNED_BY_NIC) BE */
++ if (td->tdesc0 & cpu_to_le32(BE_OWNED_BY_NIC)) /* BE */
+ break;
+
+ if ((works++ > 15))
+ break;
+
+- if (td->tdesc0.TSR & TSR0_TERR) {
++ wTSR = (u16)cpu_to_le32(td->tdesc0);
++ /* if (td->tdesc0.TSR & TSR0_TERR) { BE */
++ if (wTSR & TSR0_TERR) { /* BE */
+ stats->tx_errors++;
+ stats->tx_dropped++;
+- if (td->tdesc0.TSR & TSR0_CDH)
++ /* if (td->tdesc0.TSR & TSR0_CDH) BE */
++ if (wTSR & TSR0_CDH) /* BE */
+ stats->tx_heartbeat_errors++;
+- if (td->tdesc0.TSR & TSR0_CRS)
++ /* if (td->tdesc0.TSR & TSR0_CRS) BE */
++ if (wTSR & TSR0_CRS) /* BE */
+ stats->tx_carrier_errors++;
+- if (td->tdesc0.TSR & TSR0_ABT)
++ /* if (td->tdesc0.TSR & TSR0_ABT) BE */
++ if (wTSR & TSR0_ABT) /* BE */
+ stats->tx_aborted_errors++;
+- if (td->tdesc0.TSR & TSR0_OWC)
++ /* if (td->tdesc0.TSR & TSR0_OWC) BE */
++ if (wTSR & TSR0_OWC) /* BE */
+ stats->tx_window_errors++;
+ } else {
+ stats->tx_packets++;
+@@ -1609,6 +1705,7 @@ static void velocity_print_link_status(s
+
+ static void velocity_error(struct velocity_info *vptr, int status)
+ {
++ HAILS("velocity_error", status);
+
+ if (status & ISR_TXSTLI) {
+ struct mac_regs __iomem * regs = vptr->mac_regs;
+@@ -1698,6 +1795,7 @@ static void velocity_free_tx_buf(struct
+ struct sk_buff *skb = tdinfo->skb;
+ int i;
+
++ HAIL("velocity_free_tx_buf");
+ /*
+ * Don't unmap the pre-allocated tx_bufs
+ */
+@@ -1901,6 +1999,7 @@ static int velocity_xmit(struct sk_buff
+ struct velocity_td_info *tdinfo;
+ unsigned long flags;
+ int index;
++ u32 lbufsz; /* BE */
+
+ int pktlen = skb->len;
+
+@@ -1917,9 +2016,18 @@ static int velocity_xmit(struct sk_buff
+ td_ptr = &(vptr->td_rings[qnum][index]);
+ tdinfo = &(vptr->td_infos[qnum][index]);
+
+- td_ptr->tdesc1.TCPLS = TCPLS_NORMAL;
+- td_ptr->tdesc1.TCR = TCR0_TIC;
+- td_ptr->td_buf[0].queue = 0;
++ td_ptr->tdesc0 = 0x00000000UL; /* BE */
++ td_ptr->tdesc1 = 0x00000000UL; /* BE */
++
++ /* td_ptr->tdesc1.TCPLS = TCPLS_NORMAL; BE */
++ td_ptr->tdesc1 &= cpu_to_le32(0xfcffffffUL); /* BE */
++ td_ptr->tdesc1 |= cpu_to_le32(((u32)TCPLS_NORMAL) << 24); /* BE */
++
++ /* td_ptr->tdesc1.TCR = TCR0_TIC; BE */
++ td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_TIC); /* BE */
++
++ /* td_ptr->td_buf[0].queue = 0; BE */
++ td_ptr->td_buf[0].ltwo &= cpu_to_le32(~BE_QUEUE_ENABLE); /* BE */
+
+ /*
+ * Pad short frames.
+@@ -1931,20 +2039,36 @@ static int velocity_xmit(struct sk_buff
+ memset(tdinfo->buf + skb->len, 0, ETH_ZLEN - skb->len);
+ tdinfo->skb = skb;
+ tdinfo->skb_dma[0] = tdinfo->buf_dma;
+- td_ptr->tdesc0.pktsize = pktlen;
++ /* td_ptr->tdesc0.pktsize = pktlen; */
++ td_ptr->tdesc0 &= cpu_to_le32(0xc000ffffUL); /* BE */
++ lbufsz = pktlen; /* Assign, and make sure it's unsigned 32 bits - BE */
++ lbufsz = lbufsz << 16; /* BE - shift over */
++ td_ptr->tdesc0 |= cpu_to_le32(lbufsz); /* BE */
++
+ td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
+- td_ptr->td_buf[0].pa_high = 0;
+- td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
++ /* td_ptr->td_buf[0].pa_high = 0; */
++ /* td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize; */
++ td_ptr->td_buf[0].ltwo = cpu_to_le32(lbufsz); /* BE */
+ tdinfo->nskb_dma = 1;
+- td_ptr->tdesc1.CMDZ = 2;
++ /* td_ptr->tdesc1.CMDZ = 2; */
++ td_ptr->tdesc1 &= cpu_to_le32(0x0fffffffUL); /* BE */
++ td_ptr->tdesc1 |= cpu_to_le32(((u32)0x2) << 28); /* BE */
+ } else
+ #ifdef VELOCITY_ZERO_COPY_SUPPORT
++ /*
++ * BE - NOTE on the VELOCITY_ZERO_COPY_SUPPORT:
++ * This block of code has NOT been patched up for BE support, as
++ * it is certainly broken -- if it compiles at all. Since the BE
++ * fixes depend on the broken code, attempts to convert to BE support
++ * would almost certainly confuse more than help.
++ */
+ if (skb_shinfo(skb)->nr_frags > 0) {
+ int nfrags = skb_shinfo(skb)->nr_frags;
+ tdinfo->skb = skb;
+ if (nfrags > 6) {
+ skb_copy_from_linear_data(skb, tdinfo->buf, skb->len);
+ tdinfo->skb_dma[0] = tdinfo->buf_dma;
++ /* BE: Er, exactly what value are we assigning in this next line? */
+ td_ptr->tdesc0.pktsize =
+ td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
+ td_ptr->td_buf[0].pa_high = 0;
+@@ -1961,6 +2085,7 @@ static int velocity_xmit(struct sk_buff
+ /* FIXME: support 48bit DMA later */
+ td_ptr->td_buf[i].pa_low = cpu_to_le32(tdinfo->skb_dma);
+ td_ptr->td_buf[i].pa_high = 0;
++ /* BE: This next line can't be right: */
+ td_ptr->td_buf[i].bufsize = skb->len->skb->data_len;
+
+ for (i = 0; i < nfrags; i++) {
+@@ -1978,7 +2103,7 @@ static int velocity_xmit(struct sk_buff
+ }
+
+ } else
+-#endif
++#endif /* (broken) VELOCITY_ZERO_COPY_SUPPORT */
+ {
+ /*
+ * Map the linear network buffer into PCI space and
+@@ -1986,19 +2111,30 @@ static int velocity_xmit(struct sk_buff
+ */
+ tdinfo->skb = skb;
+ tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
+- td_ptr->tdesc0.pktsize = pktlen;
++ /* td_ptr->tdesc0.pktsize = pktlen; BE */
++ td_ptr->tdesc0 &= cpu_to_le32(0xc000ffffUL); /* BE */
++ lbufsz = pktlen; /* Assign, and make sure it's unsigned 32 bits - BE */
++ lbufsz = lbufsz << 16; /* BE */
++ td_ptr->tdesc0 |= cpu_to_le32(lbufsz); /* BE */
+ td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
+- td_ptr->td_buf[0].pa_high = 0;
+- td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
++ /* td_ptr->td_buf[0].pa_high = 0; BE */
++ /* td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize; BE */
++ td_ptr->td_buf[0].ltwo = cpu_to_le32(lbufsz); /* BE */
++
+ tdinfo->nskb_dma = 1;
+- td_ptr->tdesc1.CMDZ = 2;
++ /* td_ptr->tdesc1.CMDZ = 2; BE */
++ td_ptr->tdesc1 &= cpu_to_le32(0x0fffffffUL); /* BE */
++ td_ptr->tdesc1 |= cpu_to_le32(((u32)0x2) << 28);/* BE */
+ }
+
+ if (vptr->flags & VELOCITY_FLAGS_TAGGING) {
+- td_ptr->tdesc1.pqinf.VID = (vptr->options.vid & 0xfff);
+- td_ptr->tdesc1.pqinf.priority = 0;
+- td_ptr->tdesc1.pqinf.CFI = 0;
+- td_ptr->tdesc1.TCR |= TCR0_VETAG;
++ /* td_ptr->tdesc1.pqinf.priority = 0; BE */
++ /* td_ptr->tdesc1.pqinf.CFI = 0; BE */
++ td_ptr->tdesc1 &= cpu_to_le32(0xFFFF0000UL); /* BE */
++ /* td_ptr->tdesc1.pqinf.VID = (vptr->options.vid & 0xfff); BE */
++ td_ptr->tdesc1 |= cpu_to_le32((vptr->options.vid & 0xfff)); /* BE */
++ /* td_ptr->tdesc1.TCR |= TCR0_VETAG; BE */
++ td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_VETAG); /* BE */
+ }
+
+ /*
+@@ -2008,26 +2144,34 @@ static int velocity_xmit(struct sk_buff
+ && (skb->ip_summed == CHECKSUM_PARTIAL)) {
+ const struct iphdr *ip = ip_hdr(skb);
+ if (ip->protocol == IPPROTO_TCP)
+- td_ptr->tdesc1.TCR |= TCR0_TCPCK;
++ /* td_ptr->tdesc1.TCR |= TCR0_TCPCK; BE */
++ td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_TCPCK); /* BE */
+ else if (ip->protocol == IPPROTO_UDP)
+- td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
+- td_ptr->tdesc1.TCR |= TCR0_IPCK;
+- }
++ /* td_ptr->tdesc1.TCR |= (TCR0_UDPCK); BE */
++ td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_UDPCK); /* BE */
++ /* td_ptr->tdesc1.TCR |= TCR0_IPCK; BE */
++ td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_IPCK); /* BE */
++ }
+ {
+
+ int prev = index - 1;
+
+ if (prev < 0)
+ prev = vptr->options.numtx - 1;
+- td_ptr->tdesc0.owner = OWNED_BY_NIC;
++ /* td_ptr->tdesc0.owner = OWNED_BY_NIC; BE */
++ td_ptr->tdesc0 |= cpu_to_le32(BE_OWNED_BY_NIC); /* BE */
+ vptr->td_used[qnum]++;
+ vptr->td_curr[qnum] = (index + 1) % vptr->options.numtx;
+
+ if (AVAIL_TD(vptr, qnum) < 1)
+ netif_stop_queue(dev);
+
+- td_ptr = &(vptr->td_rings[qnum][prev]);
+- td_ptr->td_buf[0].queue = 1;
++ td_ptr = &(vptr->td_rings[qnum][prev]);
++ /* td_ptr->td_buf[0].queue = 1; BE */
++ td_ptr->td_buf[0].ltwo |= cpu_to_le32(BE_QUEUE_ENABLE); /* BE */
++ if (vdebug&2) printk(KERN_NOTICE "velocity_xmit: (%s) len=%d idx=%d tdesc0=0x%x tdesc1=0x%x ltwo=0x%x\n",
++ (pktlen<ETH_ZLEN) ? "short" : "normal", pktlen, index,
++ td_ptr->tdesc0, td_ptr->tdesc1, td_ptr->td_buf[0].ltwo);
+ mac_tx_queue_wake(vptr->mac_regs, qnum);
+ }
+ dev->trans_start = jiffies;
+@@ -2053,7 +2197,7 @@ static int velocity_intr(int irq, void *
+ u32 isr_status;
+ int max_count = 0;
+
+-
++ HAIL("velocity_intr");
+ spin_lock(&vptr->lock);
+ isr_status = mac_read_isr(vptr->mac_regs);
+
+@@ -2072,7 +2216,10 @@ static int velocity_intr(int irq, void *
+
+ while (isr_status != 0) {
+ mac_write_isr(vptr->mac_regs, isr_status);
+- if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
++ HAILS("velocity_intr",isr_status);
++ /* MJW - velocity_error is ALWAYS called; need to mask off some other flags */
++ /* if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI))) */
++ if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI | ISR_PTX0I | ISR_ISR0)))
+ velocity_error(vptr, isr_status);
+ if (isr_status & (ISR_PRXI | ISR_PPRXI))
+ max_count += velocity_rx_srv(vptr, isr_status);
+@@ -2110,6 +2257,7 @@ static void velocity_set_multi(struct ne
+ int i;
+ struct dev_mc_list *mclist;
+
++ HAIL("velocity_set_multi");
+ if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
+ writel(0xffffffff, ®s->MARCAM[0]);
+ writel(0xffffffff, ®s->MARCAM[4]);
+@@ -2153,6 +2301,7 @@ static struct net_device_stats *velocity
+ {
+ struct velocity_info *vptr = netdev_priv(dev);
+
++ HAIL("net_device_stats");
+ /* If the hardware is down, don't touch MII */
+ if(!netif_running(dev))
+ return &vptr->stats;
+@@ -2197,6 +2346,7 @@ static int velocity_ioctl(struct net_dev
+ struct velocity_info *vptr = netdev_priv(dev);
+ int ret;
+
++ HAIL("velocity_ioctl");
+ /* If we are asked for information and the device is power
+ saving then we need to bring the device back up to talk to it */
+
+@@ -2415,6 +2565,7 @@ static int velocity_mii_read(struct mac_
+ {
+ u16 ww;
+
++ HAIL("velocity_mii_read");
+ /*
+ * Disable MIICR_MAUTO, so that mii addr can be set normally
+ */
+@@ -2451,6 +2602,7 @@ static int velocity_mii_write(struct mac
+ {
+ u16 ww;
+
++ HAIL("velocity_mii_write");
+ /*
+ * Disable MIICR_MAUTO, so that mii addr can be set normally
+ */
+diff -uprN linux-2.6.23.orig/drivers/net/via-velocity.h linux-2.6.23/drivers/net/via-velocity.h
+--- linux-2.6.23.orig/drivers/net/via-velocity.h 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/drivers/net/via-velocity.h 2007-10-11 00:53:45.000000000 -0500
+@@ -196,64 +196,70 @@
+ * Receive descriptor
+ */
+
+-struct rdesc0 {
+- u16 RSR; /* Receive status */
+- u16 len:14; /* Received packet length */
+- u16 reserved:1;
+- u16 owner:1; /* Who owns this buffer ? */
+-};
+-
+-struct rdesc1 {
+- u16 PQTAG;
+- u8 CSM;
+- u8 IPKT;
+-};
++//struct rdesc0 {
++// u16 RSR; /* Receive status */
++// u16 len:14; /* Received packet length */
++// u16 reserved:1;
++// u16 owner:1; /* Who owns this buffer ? */
++//};
++
++//struct rdesc1 {
++// u16 PQTAG;
++// u8 CSM;
++// u8 IPKT;
++//};
+
+ struct rx_desc {
+- struct rdesc0 rdesc0;
+- struct rdesc1 rdesc1;
++// struct rdesc0 rdesc0;
++// struct rdesc1 rdesc1;
++ u32 rdesc0;
++ u32 rdesc1;
+ u32 pa_low; /* Low 32 bit PCI address */
+- u16 pa_high; /* Next 16 bit PCI address (48 total) */
+- u16 len:15; /* Frame size */
+- u16 inten:1; /* Enable interrupt */
++// u16 pa_high; /* Next 16 bit PCI address (48 total) */
++// u16 len:15; /* Frame size */
++// u16 inten:1; /* Enable interrupt */
++ u32 ltwo;
+ } __attribute__ ((__packed__));
+
+ /*
+ * Transmit descriptor
+ */
+
+-struct tdesc0 {
+- u16 TSR; /* Transmit status register */
+- u16 pktsize:14; /* Size of frame */
+- u16 reserved:1;
+- u16 owner:1; /* Who owns the buffer */
+-};
+-
+-struct pqinf { /* Priority queue info */
+- u16 VID:12;
+- u16 CFI:1;
+- u16 priority:3;
+-} __attribute__ ((__packed__));
+-
+-struct tdesc1 {
+- struct pqinf pqinf;
+- u8 TCR;
+- u8 TCPLS:2;
+- u8 reserved:2;
+- u8 CMDZ:4;
+-} __attribute__ ((__packed__));
++//struct tdesc0 {
++// u16 TSR; /* Transmit status register */
++// u16 pktsize:14; /* Size of frame */
++// u16 reserved:1;
++// u16 owner:1; /* Who owns the buffer */
++//};
++
++//struct pqinf { /* Priority queue info */
++// u16 VID:12;
++// u16 CFI:1;
++// u16 priority:3;
++//} __attribute__ ((__packed__));
++
++//struct tdesc1 {
++// struct pqinf pqinf;
++// u8 TCR;
++// u8 TCPLS:2;
++// u8 reserved:2;
++// u8 CMDZ:4;
++//} __attribute__ ((__packed__));
+
+ struct td_buf {
+ u32 pa_low;
+- u16 pa_high;
+- u16 bufsize:14;
+- u16 reserved:1;
+- u16 queue:1;
++// u16 pa_high;
++// u16 bufsize:14;
++// u16 reserved:1;
++// u16 queue:1;
++ u32 ltwo;
+ } __attribute__ ((__packed__));
+
+ struct tx_desc {
+- struct tdesc0 tdesc0;
+- struct tdesc1 tdesc1;
++// struct tdesc0 tdesc0;
++// struct tdesc1 tdesc1;
++ u32 tdesc0;
++ u32 tdesc1;
+ struct td_buf td_buf[7];
+ };
+
+@@ -279,6 +285,16 @@ enum velocity_owner {
+ OWNED_BY_NIC = 1
+ };
+
++/* Constants added for the BE fixes */
++#define BE_OWNED_BY_NIC 0x80000000UL
++#define BE_INT_ENABLE 0x80000000UL
++#define BE_QUEUE_ENABLE 0x80000000UL
++#define BE_TCR_TIC 0x00800000UL
++#define BE_TCR_VETAG 0x00200000UL
++#define BE_TCR_TCPCK 0x00040000UL
++#define BE_TCR_UDPCK 0x00080000UL
++#define BE_TCR_IPCK 0x00100000UL
++
+
+ /*
+ * MAC registers and macros.
+@@ -1698,6 +1714,7 @@ enum velocity_flow_cntl_type {
+ };
+
+ struct velocity_opt {
++ int velo_debug; /* debug flag */
+ int numrx; /* Number of RX descriptors */
+ int numtx; /* Number of TX descriptors */
+ enum speed_opt spd_dpx; /* Media link mode */
--- /dev/null
+diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/fsg-pci.c linux-2.6.23/arch/arm/mach-ixp4xx/fsg-pci.c
+--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/fsg-pci.c 1969-12-31 18:00:00.000000000 -0600
++++ linux-2.6.23/arch/arm/mach-ixp4xx/fsg-pci.c 2007-10-11 00:55:34.000000000 -0500
+@@ -0,0 +1,71 @@
++/*
++ * arch/arch/mach-ixp4xx/fsg-pci.c
++ *
++ * FSG board-level PCI initialization
++ *
++ * Author: Rod Whitby <rod@whitby.id.au>
++ * Maintainer: http://www.nslu2-linux.org/
++ *
++ * based on ixdp425-pci.c:
++ * Copyright (C) 2002 Intel Corporation.
++ * Copyright (C) 2003-2004 MontaVista Software, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach/pci.h>
++#include <asm/mach-types.h>
++
++void __init fsg_pci_preinit(void)
++{
++ set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW);
++ set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW);
++ set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ static int pci_irq_table[FSG_PCI_IRQ_LINES] = {
++ IRQ_FSG_PCI_INTC,
++ IRQ_FSG_PCI_INTB,
++ IRQ_FSG_PCI_INTA,
++ };
++
++ int irq = -1;
++ slot = slot - 11;
++
++ if (slot >= 1 && slot <= FSG_PCI_MAX_DEV &&
++ pin >= 1 && pin <= FSG_PCI_IRQ_LINES) {
++ irq = pci_irq_table[(slot - 1)];
++ }
++ printk("%s: Mapped slot %d pin %d to IRQ %d\n", __FUNCTION__,slot, pin, irq);
++
++ return irq;
++}
++
++struct hw_pci fsg_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = fsg_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = fsg_map_irq,
++};
++
++int __init fsg_pci_init(void)
++{
++ if (machine_is_fsg())
++ pci_common_init(&fsg_pci);
++ return 0;
++}
++
++subsys_initcall(fsg_pci_init);
+diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/fsg-setup.c linux-2.6.23/arch/arm/mach-ixp4xx/fsg-setup.c
+--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/fsg-setup.c 1969-12-31 18:00:00.000000000 -0600
++++ linux-2.6.23/arch/arm/mach-ixp4xx/fsg-setup.c 2007-10-11 00:55:34.000000000 -0500
+@@ -0,0 +1,186 @@
++/*
++ * arch/arm/mach-ixp4xx/fsg-setup.c
++ *
++ * FSG board-setup
++ *
++ * based ixdp425-setup.c:
++ * Copyright (C) 2003-2004 MontaVista Software, Inc.
++ *
++ * Author: Rod Whitby <rod@whitby.id.au>
++ * Maintainers: http://www.nslu2-linux.org/
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/serial.h>
++#include <linux/serial_8250.h>
++#include <linux/leds.h>
++#include <linux/i2c-gpio.h>
++
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data fsg_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource fsg_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device fsg_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev.platform_data = &fsg_flash_data,
++ .num_resources = 1,
++ .resource = &fsg_flash_resource,
++};
++
++static struct i2c_gpio_platform_data fsg_i2c_gpio_data = {
++ .sda_pin = FSG_SDA_PIN,
++ .scl_pin = FSG_SCL_PIN,
++};
++
++static struct platform_device fsg_i2c_gpio = {
++ .name = "i2c-gpio",
++ .id = 0,
++ .dev = {
++ .platform_data = &fsg_i2c_gpio_data,
++ },
++};
++
++#ifdef CONFIG_LEDS_CLASS
++static struct resource fsg_led_resources[] = {
++ {
++ .name = "ring",
++ .start = FSG_LED_RING_GPIO,
++ .end = FSG_LED_RING_GPIO,
++ .flags = IXP4XX_GPIO_HIGH,
++ },
++ {
++ .name = "sync",
++ .start = FSG_LED_SYNC_GPIO,
++ .end = FSG_LED_SYNC_GPIO,
++ .flags = IXP4XX_GPIO_HIGH,
++ },
++ {
++ .name = "usb",
++ .start = FSG_LED_USB_GPIO,
++ .end = FSG_LED_USB_GPIO,
++ .flags = IXP4XX_GPIO_HIGH,
++ },
++ {
++ .name = "sata",
++ .start = FSG_LED_SATA_GPIO,
++ .end = FSG_LED_SATA_GPIO,
++ .flags = IXP4XX_GPIO_HIGH,
++ },
++ {
++ .name = "wan",
++ .start = FSG_LED_WAN_GPIO,
++ .end = FSG_LED_WAN_GPIO,
++ .flags = IXP4XX_GPIO_HIGH,
++ },
++ {
++ .name = "wlan",
++ .start = FSG_LED_WLAN_GPIO,
++ .end = FSG_LED_WLAN_GPIO,
++ .flags = IXP4XX_GPIO_HIGH,
++ },
++};
++
++static struct platform_device fsg_leds = {
++ .name = "IXP4XX-GPIO-LED",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(fsg_led_resources),
++ .resource = fsg_led_resources,
++};
++#endif
++
++static struct resource fsg_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct plat_serial8250_port fsg_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { }
++};
++
++static struct platform_device fsg_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev.platform_data = fsg_uart_data,
++ .num_resources = ARRAY_SIZE(fsg_uart_resources),
++ .resource = fsg_uart_resources,
++};
++
++static struct platform_device *fsg_devices[] __initdata = {
++ &fsg_i2c_gpio,
++ &fsg_flash,
++#ifdef CONFIG_LEDS_IXP4XX
++ &fsg_leds,
++#endif
++};
++
++static void __init fsg_init(void)
++{
++ ixp4xx_sys_init();
++
++ fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ fsg_flash_resource.end =
++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ /* Configure CS2 for operation, 8bit and writable */
++ *IXP4XX_EXP_CS2 = 0xbfff0002;
++
++ /* This is only useful on a modified machine, but it is valuable
++ * to have it first in order to see debug messages, and so that
++ * it does *not* get removed if platform_add_devices fails!
++ */
++ (void)platform_device_register(&fsg_uart);
++
++ platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
++}
++
++MACHINE_START(FSG, "Freecom FSG-3")
++ /* Maintainer: www.nslu2-linux.org */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = fsg_init,
++MACHINE_END
++
+diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/Kconfig 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-11 00:55:34.000000000 -0500
+@@ -125,6 +125,15 @@ config ARCH_IXDP4XX
+ depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
+ default y
+
++config MACH_FSG
++ bool
++ prompt "Freecom FSG-3"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support Freecom's
++ FSG-3 device. For more information on this platform
++ see http://www.nslu2-linux.org/wiki/FSG3/HomePage
++
+ #
+ # Certain registers and IRQs are only enabled if supporting IXP465 CPUs
+ #
+diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/Makefile linux-2.6.23/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/Makefile 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-11 00:55:34.000000000 -0500
+@@ -15,6 +15,7 @@ obj-pci-$(CONFIG_MACH_NAS100D) += nas10
+ obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
+ obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
+ obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
++obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
+
+ obj-y += common.o
+
+@@ -28,5 +29,6 @@ obj-$(CONFIG_MACH_NAS100D) += nas100d-se
+ obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o dsmg600-power.o
+ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
+ obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
++obj-$(CONFIG_MACH_FSG) += fsg-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+diff -uprN linux-2.6.23.orig/include/asm-arm/arch-ixp4xx/fsg.h linux-2.6.23/include/asm-arm/arch-ixp4xx/fsg.h
+--- linux-2.6.23.orig/include/asm-arm/arch-ixp4xx/fsg.h 1969-12-31 18:00:00.000000000 -0600
++++ linux-2.6.23/include/asm-arm/arch-ixp4xx/fsg.h 2007-10-11 00:55:34.000000000 -0500
+@@ -0,0 +1,74 @@
++/*
++ * include/asm-arm/arch-ixp4xx/fsg.h
++ *
++ * Freecom FSG-3 platform specific definitions
++ *
++ * Author: Rod Whitby <rod@whitby.id.au>
++ * Author: Tomasz Chmielewski <mangoo@wpkg.org>
++ * Maintainers: http://www.nslu2-linux.org
++ *
++ * Based on coyote.h by
++ * Copyright 2004 (c) MontaVista, Software, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef __ASM_ARCH_HARDWARE_H__
++#error "Do not include this directly, instead #include <asm/hardware.h>"
++#endif
++
++#define FSG_SDA_PIN 12
++#define FSG_SCL_PIN 13
++
++/*
++ * FSG PCI IRQs
++ */
++#define FSG_PCI_MAX_DEV 3
++#define FSG_PCI_IRQ_LINES 3
++
++
++/* PCI controller GPIO to IRQ pin mappings */
++#define FSG_PCI_INTA_PIN 6
++#define FSG_PCI_INTB_PIN 7
++#define FSG_PCI_INTC_PIN 5
++
++/* Buttons */
++
++#define FSG_SB_GPIO 4
++#define FSG_RB_GPIO 9
++#define FSG_UB_GPIO 10
++
++#define FSG_SB_IRQ IRQ_IXP4XX_GPIO4
++#define FSG_RB_IRQ IRQ_IXP4XX_GPIO9
++#define FSG_UB_IRQ IRQ_IXP4XX_GPIO10
++
++#define FSG_SB_BM (1L << FSG_SB_GPIO)
++#define FSG_RB_BM (1L << FSG_RB_GPIO)
++#define FSG_UB_BM (1L << FSG_UB_GPIO)
++
++/* LEDs */
++
++#define FSG_LED_RING_GPIO 0
++#define FSG_LED_SYNC_GPIO 1
++#define FSG_LED_USB_GPIO 2
++#define FSG_LED_SATA_GPIO 3
++#define FSG_LED_WAN_GPIO 4
++#define FSG_LED_WLAN_GPIO 5
++
++/* %%% REMOVE %%%
++#define FSG_PCI_SLOT0_PIN 6
++#define FSG_PCI_SLOT1_PIN 7
++
++#define FSG_PCI_SLOT0_DEVID 14
++#define FSG_PCI_SLOT1_DEVID 15
++
++#define FSG_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
++#define FSG_IDE_BASE_VIRT 0xFFFE1000
++#define FSG_IDE_REGION_SIZE 0x1000
++
++#define FSG_IDE_DATA_PORT 0xFFFE10E0
++#define FSG_IDE_CTRL_PORT 0xFFFE10FC
++#define FSG_IDE_ERROR_PORT 0xFFFE10E2
++*/
+diff -uprN linux-2.6.23.orig/include/asm-arm/arch-ixp4xx/hardware.h linux-2.6.23/include/asm-arm/arch-ixp4xx/hardware.h
+--- linux-2.6.23.orig/include/asm-arm/arch-ixp4xx/hardware.h 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/include/asm-arm/arch-ixp4xx/hardware.h 2007-10-11 00:55:34.000000000 -0500
+@@ -45,5 +45,6 @@
+ #include "nslu2.h"
+ #include "nas100d.h"
+ #include "dsmg600.h"
++#include "fsg.h"
+
+ #endif /* _ASM_ARCH_HARDWARE_H */
+diff -uprN linux-2.6.23.orig/include/asm-arm/arch-ixp4xx/irqs.h linux-2.6.23/include/asm-arm/arch-ixp4xx/irqs.h
+--- linux-2.6.23.orig/include/asm-arm/arch-ixp4xx/irqs.h 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/include/asm-arm/arch-ixp4xx/irqs.h 2007-10-11 00:55:34.000000000 -0500
+@@ -128,4 +128,17 @@
+ #define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
+ #define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
+
++/*
++ * Freecom FSG-3 Board IRQs
++ */
++#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6
++#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7
++#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5
++
++/* %%% REMOVE %%%
++#define IRQ_FSG_PCI_SLOT0 IRQ_IXP4XX_GPIO6
++#define IRQ_FSG_PCI_SLOT1 IRQ_IXP4XX_GPIO7
++#define IRQ_FSG_IDE IRQ_IXP4XX_GPIO5
++*/
++
+ #endif
--- /dev/null
+diff -uprN linux-2.6.23.orig/drivers/i2c/chips/eeprom.c linux-2.6.23/drivers/i2c/chips/eeprom.c
+--- linux-2.6.23.orig/drivers/i2c/chips/eeprom.c 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/drivers/i2c/chips/eeprom.c 2007-10-11 00:57:25.000000000 -0500
+@@ -33,6 +33,8 @@
+ #include <linux/jiffies.h>
+ #include <linux/i2c.h>
+ #include <linux/mutex.h>
++#include <linux/notifier.h>
++#include <linux/eeprom.h>
+
+ /* Addresses to scan */
+ static unsigned short normal_i2c[] = { 0x50, 0x51, 0x52, 0x53, 0x54,
+@@ -41,26 +43,7 @@ static unsigned short normal_i2c[] = { 0
+ /* Insmod parameters */
+ I2C_CLIENT_INSMOD_1(eeprom);
+
+-
+-/* Size of EEPROM in bytes */
+-#define EEPROM_SIZE 256
+-
+-/* possible types of eeprom devices */
+-enum eeprom_nature {
+- UNKNOWN,
+- VAIO,
+-};
+-
+-/* Each client has this additional data */
+-struct eeprom_data {
+- struct i2c_client client;
+- struct mutex update_lock;
+- u8 valid; /* bitfield, bit!=0 if slice is valid */
+- unsigned long last_updated[8]; /* In jiffies, 8 slices */
+- u8 data[EEPROM_SIZE]; /* Register values */
+- enum eeprom_nature nature;
+-};
+-
++ATOMIC_NOTIFIER_HEAD(eeprom_chain);
+
+ static int eeprom_attach_adapter(struct i2c_adapter *adapter);
+ static int eeprom_detect(struct i2c_adapter *adapter, int address, int kind);
+@@ -191,6 +174,7 @@ static int eeprom_detect(struct i2c_adap
+ data->valid = 0;
+ mutex_init(&data->update_lock);
+ data->nature = UNKNOWN;
++ data->attr = &eeprom_attr;
+
+ /* Tell the I2C layer a new client has arrived */
+ if ((err = i2c_attach_client(new_client)))
+@@ -214,6 +198,9 @@ static int eeprom_detect(struct i2c_adap
+ if (err)
+ goto exit_detach;
+
++ /* call the notifier chain */
++ atomic_notifier_call_chain(&eeprom_chain, EEPROM_REGISTER, data);
++
+ return 0;
+
+ exit_detach:
+@@ -239,6 +226,41 @@ static int eeprom_detach_client(struct i
+ return 0;
+ }
+
++/**
++ * register_eeprom_notifier - register a 'user' of EEPROM devices.
++ * @nb: pointer to notifier info structure
++ *
++ * Registers a callback function to be called upon detection
++ * of an EEPROM device. Detection invokes the 'add' callback
++ * with the kobj of the mutex and a bin_attribute which allows
++ * read from the EEPROM. The intention is that the notifier
++ * will be able to read system configuration from the notifier.
++ *
++ * Only EEPROMs detected *after* the addition of the notifier
++ * are notified. I.e. EEPROMs already known to the system
++ * will not be notified - add the notifier from board level
++ * code!
++ */
++int register_eeprom_notifier(struct notifier_block *nb)
++{
++ return atomic_notifier_chain_register(&eeprom_chain, nb);
++}
++
++/**
++ * unregister_eeprom_notifier - unregister a 'user' of EEPROM devices.
++ * @old: pointer to notifier info structure
++ *
++ * Removes a callback function from the list of 'users' to be
++ * notified upon detection of EEPROM devices.
++ */
++int unregister_eeprom_notifier(struct notifier_block *nb)
++{
++ return atomic_notifier_chain_unregister(&eeprom_chain, nb);
++}
++
++EXPORT_SYMBOL_GPL(register_eeprom_notifier);
++EXPORT_SYMBOL_GPL(unregister_eeprom_notifier);
++
+ static int __init eeprom_init(void)
+ {
+ return i2c_add_driver(&eeprom_driver);
+diff -uprN linux-2.6.23.orig/include/linux/eeprom.h linux-2.6.23/include/linux/eeprom.h
+--- linux-2.6.23.orig/include/linux/eeprom.h 1969-12-31 18:00:00.000000000 -0600
++++ linux-2.6.23/include/linux/eeprom.h 2007-10-11 00:57:25.000000000 -0500
+@@ -0,0 +1,71 @@
++#ifndef _LINUX_EEPROM_H
++#define _LINUX_EEPROM_H
++/*
++ * EEPROM notifier header
++ *
++ * Copyright (C) 2006 John Bowler
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __KERNEL__
++#error This is a kernel header
++#endif
++
++#include <linux/list.h>
++#include <linux/kobject.h>
++#include <linux/sysfs.h>
++
++/* Size of EEPROM in bytes */
++#define EEPROM_SIZE 256
++
++/* possible types of eeprom devices */
++enum eeprom_nature {
++ UNKNOWN,
++ VAIO,
++};
++
++/* Each client has this additional data */
++struct eeprom_data {
++ struct i2c_client client;
++ struct mutex update_lock;
++ u8 valid; /* bitfield, bit!=0 if slice is valid */
++ unsigned long last_updated[8]; /* In jiffies, 8 slices */
++ u8 data[EEPROM_SIZE]; /* Register values */
++ enum eeprom_nature nature;
++ struct bin_attribute *attr;
++};
++
++/*
++ * This is very basic.
++ *
++ * If an EEPROM is detected on the I2C bus (this only works for
++ * I2C EEPROMs) the notifier chain is called with
++ * both the I2C information and the kobject for the sysfs
++ * device which has been registers. It is then possible to
++ * read from the device via the bin_attribute::read method
++ * to extract configuration information.
++ *
++ * Register the notifier in the board level code, there is no
++ * need to unregister it but you can if you want (it will save
++ * a little bit or kernel memory to do so).
++ */
++
++extern int register_eeprom_notifier(struct notifier_block *nb);
++extern int unregister_eeprom_notifier(struct notifier_block *nb);
++
++#endif /* _LINUX_EEPROM_H */
+diff -uprN linux-2.6.23.orig/include/linux/notifier.h linux-2.6.23/include/linux/notifier.h
+--- linux-2.6.23.orig/include/linux/notifier.h 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/include/linux/notifier.h 2007-10-11 00:57:25.000000000 -0500
+@@ -231,5 +231,8 @@ static inline int notifier_to_errno(int
+ #define PM_SUSPEND_PREPARE 0x0003 /* Going to suspend the system */
+ #define PM_POST_SUSPEND 0x0004 /* Suspend finished */
+
++/* eeprom notifier chain */
++#define EEPROM_REGISTER 0x0001
++
+ #endif /* __KERNEL__ */
+ #endif /* _LINUX_NOTIFIER_H */
--- /dev/null
+diff -uprN linux-2.6.23.orig/drivers/ata/pata_artop.c linux-2.6.23/drivers/ata/pata_artop.c
+--- linux-2.6.23.orig/drivers/ata/pata_artop.c 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/drivers/ata/pata_artop.c 2007-10-11 00:59:14.000000000 -0500
+@@ -27,6 +27,7 @@
+ #include <scsi/scsi_host.h>
+ #include <linux/libata.h>
+ #include <linux/ata.h>
++#include <asm/mach-types.h>
+
+ #define DRV_NAME "pata_artop"
+ #define DRV_VERSION "0.4.4"
+@@ -489,6 +490,11 @@ static int artop_init_one (struct pci_de
+ pci_read_config_byte(pdev, 0x4a, ®);
+ pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
+
++ /* NAS100D workaround - probing second port kills uhci_hcd */
++#ifdef CONFIG_MACH_NAS100D
++ if (machine_is_nas100d())
++ ppi[1] = &ata_dummy_port_info;
++#endif
+ }
+
+ BUG_ON(ppi[0] == NULL);
--- /dev/null
+---
+ arch/arm/mach-ixp4xx/dsmg600-power.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+Index: linux-2.6.22-rc5-armeb/arch/arm/mach-ixp4xx/dsmg600-power.c
+===================================================================
+--- linux-2.6.22-rc5-armeb.orig/arch/arm/mach-ixp4xx/dsmg600-power.c
++++ linux-2.6.22-rc5-armeb/arch/arm/mach-ixp4xx/dsmg600-power.c
+@@ -50,6 +50,13 @@
+ if (*IXP4XX_GPIO_GPINR & DSMG600_PB_BM) {
+
+ /* IO Pin is 1 (button pushed) */
++ if (power_button_countdown > 0) {
++ power_button_countdown--;
++ }
++
++ } else {
++
++ /* Done on button release, to allow for auto-power-on mods. */
+ if (power_button_countdown == 0) {
+ /* Signal init to do the ctrlaltdel action, this will bypass
+ * init if it hasn't started and do a kernel_restart.
+@@ -58,11 +65,9 @@
+
+ /* Change the state of the power LED to "blink" */
+ gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW);
++ } else {
++ power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
+ }
+- power_button_countdown--;
+-
+- } else {
+- power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
+ }
+
+ mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500));
--- /dev/null
+---
+ arch/arm/mach-ixp4xx/nas100d-power.c | 68 ++++++++++++++++++++++++++++++++--
+ include/asm-arm/arch-ixp4xx/nas100d.h | 18 +++++----
+ 2 files changed, 75 insertions(+), 11 deletions(-)
+
+Index: linux-2.6.22-rc5-armeb/arch/arm/mach-ixp4xx/nas100d-power.c
+===================================================================
+--- linux-2.6.22-rc5-armeb.orig/arch/arm/mach-ixp4xx/nas100d-power.c
++++ linux-2.6.22-rc5-armeb/arch/arm/mach-ixp4xx/nas100d-power.c
+@@ -21,15 +21,60 @@
+ #include <linux/irq.h>
+ #include <linux/module.h>
+ #include <linux/reboot.h>
++#include <linux/jiffies.h>
++#include <linux/timer.h>
+
+ #include <asm/mach-types.h>
+
+-static irqreturn_t nas100d_reset_handler(int irq, void *dev_id)
++extern void ctrl_alt_del(void);
++
++/* This is used to make sure the power-button pusher is serious. The button
++ * must be held until the value of this counter reaches zero.
++ */
++static volatile int power_button_countdown;
++
++/* Must hold the button down for at least this many counts to be processed */
++#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */
++
++static void nas100d_power_handler(unsigned long data);
++static DEFINE_TIMER(nas100d_power_timer, nas100d_power_handler, 0, 0);
++
++static void nas100d_power_handler(unsigned long data)
+ {
+- /* Signal init to do the ctrlaltdel action, this will bypass init if
+- * it hasn't started and do a kernel_restart.
++ /* This routine is called twice per second to check the
++ * state of the power button.
+ */
+- ctrl_alt_del();
++
++ if (*IXP4XX_GPIO_GPINR & NAS100D_PB_BM) {
++
++ /* IO Pin is 1 (button pushed) */
++ if (power_button_countdown > 0) {
++ power_button_countdown--;
++ }
++
++ } else {
++
++ /* Done on button release, to allow for auto-power-on mods. */
++ if (power_button_countdown == 0) {
++ /* Signal init to do the ctrlaltdel action, this will bypass
++ * init if it hasn't started and do a kernel_restart.
++ */
++ ctrl_alt_del();
++
++ /* Change the state of the power LED to "blink" */
++ gpio_line_set(NAS100D_LED_PWR_GPIO, IXP4XX_GPIO_LOW);
++ } else {
++ power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
++ }
++ }
++
++ mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500));
++}
++
++static irqreturn_t nas100d_reset_handler(int irq, void *dev_id)
++{
++ /* This is the paper-clip reset, it shuts the machine down directly. */
++ machine_power_off();
+
+ return IRQ_HANDLED;
+ }
+@@ -50,6 +95,19 @@
+ return -EIO;
+ }
+
++ /* The power button on the Iomega NAS100d is on GPIO 14, but
++ * it cannot handle interrupts on that GPIO line. So we'll
++ * have to poll it with a kernel timer.
++ */
++
++ /* Make sure that the power button GPIO is set up as an input */
++ gpio_line_config(NAS100D_PB_GPIO, IXP4XX_GPIO_IN);
++
++ /* Set the initial value for the power button IRQ handler */
++ power_button_countdown = PBUTTON_HOLDDOWN_COUNT;
++
++ mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500));
++
+ return 0;
+ }
+
+@@ -58,6 +116,8 @@
+ if (!(machine_is_nas100d()))
+ return;
+
++ del_timer_sync(&nas100d_power_timer);
++
+ free_irq(NAS100D_RB_IRQ, NULL);
+ }
+
+Index: linux-2.6.22-rc5-armeb/include/asm-arm/arch-ixp4xx/nas100d.h
+===================================================================
+--- linux-2.6.22-rc5-armeb.orig/include/asm-arm/arch-ixp4xx/nas100d.h
++++ linux-2.6.22-rc5-armeb/include/asm-arm/arch-ixp4xx/nas100d.h
+@@ -39,14 +39,18 @@
+ /* Buttons */
+
+ #define NAS100D_PB_GPIO 14
++#define NAS100D_PB_BM (1L << NAS100D_PB_GPIO)
++
+ #define NAS100D_RB_GPIO 4
+-#define NAS100D_PO_GPIO 12 /* power off */
+
+-#define NAS100D_PB_IRQ IRQ_IXP4XX_GPIO14
+ #define NAS100D_RB_IRQ IRQ_IXP4XX_GPIO4
+
+-/*
+-#define NAS100D_PB_BM (1L << NAS100D_PB_GPIO)
+-#define NAS100D_PO_BM (1L << NAS100D_PO_GPIO)
+-#define NAS100D_RB_BM (1L << NAS100D_RB_GPIO)
+-*/
++#define NAS100D_PO_GPIO 12 /* power off */
++
++/* LEDs */
++
++#define NAS100D_LED_PWR_GPIO 15
++#define NAS100D_LED_PWR_BM (1L << NAS100D_LED_PWR_GPIO)
++
++#define NAS100D_LED_WLAN_GPIO 0
++#define NAS100D_LED_WLAN_BM (1L << NAS100D_LED_WLAN_GPIO)
--- /dev/null
+diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
+index 9bf8ccb..77277d2 100644
+--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -18,6 +18,7 @@
+ #include <linux/serial.h>
+ #include <linux/serial_8250.h>
+ #include <linux/leds.h>
++#include <linux/i2c-gpio.h>
+
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -41,7 +42,7 @@ static struct platform_device nslu2_flash = {
+ .resource = &nslu2_flash_resource,
+ };
+
+-static struct ixp4xx_i2c_pins nslu2_i2c_gpio_pins = {
++static struct i2c_gpio_platform_data nslu2_i2c_gpio_data = {
+ .sda_pin = NSLU2_SDA_PIN,
+ .scl_pin = NSLU2_SCL_PIN,
+ };
+@@ -82,11 +83,12 @@ static struct platform_device nslu2_leds = {
+ };
+ #endif
+
+-static struct platform_device nslu2_i2c_controller = {
+- .name = "IXP4XX-I2C",
++static struct platform_device nslu2_i2c_gpio = {
++ .name = "i2c-gpio",
+ .id = 0,
+- .dev.platform_data = &nslu2_i2c_gpio_pins,
+- .num_resources = 0,
++ .dev = {
++ .platform_data = &nslu2_i2c_gpio_data,
++ },
+ };
+
+ static struct platform_device nslu2_beeper = {
+@@ -139,7 +141,7 @@ static struct platform_device nslu2_uart = {
+ };
+
+ static struct platform_device *nslu2_devices[] __initdata = {
+- &nslu2_i2c_controller,
++ &nslu2_i2c_gpio,
+ &nslu2_flash,
+ &nslu2_beeper,
+ #ifdef CONFIG_LEDS_IXP4XX
--- /dev/null
+diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
+index 78a1741..54d884f 100644
+--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -16,6 +16,7 @@
+ #include <linux/serial.h>
+ #include <linux/serial_8250.h>
+ #include <linux/leds.h>
++#include <linux/i2c-gpio.h>
+
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -68,16 +69,17 @@ static struct platform_device nas100d_leds = {
+ };
+ #endif
+
+-static struct ixp4xx_i2c_pins nas100d_i2c_gpio_pins = {
++static struct i2c_gpio_platform_data nas100d_i2c_gpio_data = {
+ .sda_pin = NAS100D_SDA_PIN,
+ .scl_pin = NAS100D_SCL_PIN,
+ };
+
+-static struct platform_device nas100d_i2c_controller = {
+- .name = "IXP4XX-I2C",
++static struct platform_device nas100d_i2c_gpio = {
++ .name = "i2c-gpio",
+ .id = 0,
+- .dev.platform_data = &nas100d_i2c_gpio_pins,
+- .num_resources = 0,
++ .dev = {
++ .platform_data = &nas100d_i2c_gpio_data,
++ },
+ };
+
+ static struct resource nas100d_uart_resources[] = {
+@@ -124,7 +126,7 @@ static struct platform_device nas100d_uart = {
+ };
+
+ static struct platform_device *nas100d_devices[] __initdata = {
+- &nas100d_i2c_controller,
++ &nas100d_i2c_gpio,
+ &nas100d_flash,
+ #ifdef CONFIG_LEDS_IXP4XX
+ &nas100d_leds,
--- /dev/null
+Index: linux-2.6.22-rc3-git2-armeb/arch/arm/mach-ixp4xx/avila-setup.c
+===================================================================
+--- linux-2.6.22-rc3-git2-armeb.orig/arch/arm/mach-ixp4xx/avila-setup.c 2007-05-31 04:05:33.000000000 -0700
++++ linux-2.6.22-rc3-git2-armeb/arch/arm/mach-ixp4xx/avila-setup.c 2007-05-31 04:12:50.000000000 -0700
+@@ -18,6 +18,7 @@
+ #include <linux/tty.h>
+ #include <linux/serial_8250.h>
+ #include <linux/slab.h>
++#include <linux/i2c-gpio.h>
+
+ #include <asm/types.h>
+ #include <asm/setup.h>
+@@ -47,18 +48,17 @@
+ .resource = &avila_flash_resource,
+ };
+
+-static struct ixp4xx_i2c_pins avila_i2c_gpio_pins = {
++static struct i2c_gpio_platform_data avila_i2c_gpio_data = {
+ .sda_pin = AVILA_SDA_PIN,
+ .scl_pin = AVILA_SCL_PIN,
+ };
+
+-static struct platform_device avila_i2c_controller = {
+- .name = "IXP4XX-I2C",
++static struct platform_device avila_i2c_gpio = {
++ .name = "i2c-gpio",
+ .id = 0,
+- .dev = {
+- .platform_data = &avila_i2c_gpio_pins,
++ .dev = {
++ .platform_data = &avila_i2c_gpio_data,
+ },
+- .num_resources = 0
+ };
+
+ static struct resource avila_uart_resources[] = {
+@@ -133,7 +133,7 @@
+ };
+
+ static struct platform_device *avila_devices[] __initdata = {
+- &avila_i2c_controller,
++ &avila_i2c_gpio,
+ &avila_flash,
+ &avila_uart
+ };
--- /dev/null
+Index: linux-2.6.22-rc3-git2-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c
+===================================================================
+--- linux-2.6.22-rc3-git2-armeb.orig/arch/arm/mach-ixp4xx/dsmg600-setup.c 2007-05-31 04:05:30.000000000 -0700
++++ linux-2.6.22-rc3-git2-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c 2007-05-31 04:13:02.000000000 -0700
+@@ -14,6 +14,7 @@
+ #include <linux/kernel.h>
+ #include <linux/serial.h>
+ #include <linux/serial_8250.h>
++#include <linux/i2c-gpio.h>
+
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -37,15 +38,17 @@
+ .resource = &dsmg600_flash_resource,
+ };
+
+-static struct ixp4xx_i2c_pins dsmg600_i2c_gpio_pins = {
++static struct i2c_gpio_platform_data dsmg600_i2c_gpio_data = {
+ .sda_pin = DSMG600_SDA_PIN,
+ .scl_pin = DSMG600_SCL_PIN,
+ };
+
+-static struct platform_device dsmg600_i2c_controller = {
+- .name = "IXP4XX-I2C",
++static struct platform_device dsmg600_i2c_gpio = {
++ .name = "i2c-gpio",
+ .id = 0,
+- .dev.platform_data = &dsmg600_i2c_gpio_pins,
++ .dev = {
++ .platform_data = &dsmg600_i2c_gpio_data,
++ },
+ };
+
+ #ifdef CONFIG_LEDS_CLASS
+@@ -116,7 +119,7 @@
+ };
+
+ static struct platform_device *dsmg600_devices[] __initdata = {
+- &dsmg600_i2c_controller,
++ &dsmg600_i2c_gpio,
+ &dsmg600_flash,
+ };
+
--- /dev/null
+diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/ixdp425-setup.c linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-setup.c
+--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/ixdp425-setup.c 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-setup.c 2007-10-11 01:01:02.000000000 -0500
+@@ -15,6 +15,7 @@
+ #include <linux/tty.h>
+ #include <linux/serial_8250.h>
+ #include <linux/slab.h>
++#include <linux/i2c-gpio.h>
+ #include <linux/io.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/nand.h>
+@@ -120,18 +121,17 @@ static struct platform_device ixdp425_fl
+ };
+ #endif /* CONFIG_MTD_NAND_PLATFORM */
+
+-static struct ixp4xx_i2c_pins ixdp425_i2c_gpio_pins = {
++static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = {
+ .sda_pin = IXDP425_SDA_PIN,
+ .scl_pin = IXDP425_SCL_PIN,
+ };
+
+-static struct platform_device ixdp425_i2c_controller = {
+- .name = "IXP4XX-I2C",
++static struct platform_device ixdp425_i2c_gpio = {
++ .name = "i2c-gpio",
+ .id = 0,
+- .dev = {
+- .platform_data = &ixdp425_i2c_gpio_pins,
++ .dev = {
++ .platform_data = &ixdp425_i2c_gpio_data,
+ },
+- .num_resources = 0
+ };
+
+ static struct resource ixdp425_uart_resources[] = {
+@@ -178,7 +178,7 @@ static struct platform_device ixdp425_ua
+ };
+
+ static struct platform_device *ixdp425_devices[] __initdata = {
+- &ixdp425_i2c_controller,
++ &ixdp425_i2c_gpio,
+ &ixdp425_flash,
+ #if defined(CONFIG_MTD_NAND_PLATFORM) || \
+ defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
--- /dev/null
+diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
+index 77277d2..e0d0dde 100644
+--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -140,6 +140,23 @@ static struct platform_device nslu2_uart = {
+ .resource = nslu2_uart_resources,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info nslu2_plat_eth[] = {
++ {
++ .phy = 1,
++ .rxq = 3,
++ .txreadyq = 20,
++ }
++};
++
++static struct platform_device nslu2_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = nslu2_plat_eth,
++ }
++};
++
+ static struct platform_device *nslu2_devices[] __initdata = {
+ &nslu2_i2c_gpio,
+ &nslu2_flash,
+@@ -147,6 +164,7 @@ static struct platform_device *nslu2_devices[] __initdata = {
+ #ifdef CONFIG_LEDS_IXP4XX
+ &nslu2_leds,
+ #endif
++ &nslu2_eth[0],
+ };
+
+ static void nslu2_power_off(void)
--- /dev/null
+diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
+index 54d884f..d4d8540 100644
+--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -125,12 +125,30 @@ static struct platform_device nas100d_uart = {
+ .resource = nas100d_uart_resources,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info nas100d_plat_eth[] = {
++ {
++ .phy = 0,
++ .rxq = 3,
++ .txreadyq = 20,
++ }
++};
++
++static struct platform_device nas100d_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = nas100d_plat_eth,
++ }
++};
++
+ static struct platform_device *nas100d_devices[] __initdata = {
+ &nas100d_i2c_gpio,
+ &nas100d_flash,
+ #ifdef CONFIG_LEDS_IXP4XX
+ &nas100d_leds,
+ #endif
++ &nas100d_eth[0],
+ };
+
+ static void nas100d_power_off(void)
--- /dev/null
+diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
+index e38f45f..10ed5d6 100644
+--- a/arch/arm/mach-ixp4xx/avila-setup.c
++++ b/arch/arm/mach-ixp4xx/avila-setup.c
+@@ -132,10 +132,37 @@ static struct platform_device avila_pata = {
+ .resource = avila_pata_resources,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info avila_plat_eth[] = {
++ {
++ .phy = 0,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device avila_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = avila_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = avila_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *avila_devices[] __initdata = {
+ &avila_i2c_gpio,
+ &avila_flash,
+- &avila_uart
++ &avila_uart,
++ &avila_eth[0],
++ &avila_eth[1],
+ };
+
+ static void __init avila_init(void)
--- /dev/null
+diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
+index 11336e6..ec3d517 100644
+--- a/arch/arm/mach-ixp4xx/fsg-setup.c
++++ b/arch/arm/mach-ixp4xx/fsg-setup.c
+@@ -142,12 +142,39 @@ static struct platform_device fsg_uart = {
+ .resource = fsg_uart_resources,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info fsg_plat_eth[] = {
++ {
++ .phy = 5,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 4,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device fsg_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = fsg_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = fsg_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *fsg_devices[] __initdata = {
+ &fsg_i2c_gpio,
+ &fsg_flash,
+ #ifdef CONFIG_LEDS_IXP4XX
+ &fsg_leds,
+ #endif
++ &fsg_eth[0],
++ &fsg_eth[1],
+ };
+
+ static void __init fsg_init(void)
--- /dev/null
+diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
+index e0d0dde..6e24916 100644
+--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
++++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
+@@ -19,6 +19,7 @@
+ #include <linux/serial_8250.h>
+ #include <linux/leds.h>
+ #include <linux/i2c-gpio.h>
++#include <linux/mtd/mtd.h>
+
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -167,6 +168,30 @@ static struct platform_device *nslu2_devices[] __initdata = {
+ &nslu2_eth[0],
+ };
+
++static void nslu2_flash_add(struct mtd_info *mtd)
++{
++ if (strcmp(mtd->name, "RedBoot") == 0) {
++ size_t retlen;
++ u_char mac[6];
++
++ if (mtd->read(mtd, 0x3FFB0, 6, &retlen, mac) == 0 && retlen == 6) {
++ printk(KERN_INFO "nslu2 mac: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++ memcpy(nslu2_plat_eth[0].hwaddr, mac, 6);
++ } else {
++ printk(KERN_ERR "nslu2 mac: read failed\n");
++ }
++ }
++}
++
++static void nslu2_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier nslu2_flash_notifier = {
++ .add = nslu2_flash_add,
++ .remove = nslu2_flash_remove,
++};
++
+ static void nslu2_power_off(void)
+ {
+ /* This causes the box to drop the power and go dead. */
+@@ -209,6 +234,8 @@ static void __init nslu2_init(void)
+ (void)platform_device_register(&nslu2_uart);
+
+ platform_add_devices(nslu2_devices, ARRAY_SIZE(nslu2_devices));
++
++ register_mtd_user(&nslu2_flash_notifier);
+ }
+
+ MACHINE_START(NSLU2, "Linksys NSLU2")
--- /dev/null
+diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
+index d4d8540..b8c99fa 100644
+--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
++++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
+@@ -17,6 +17,7 @@
+ #include <linux/serial_8250.h>
+ #include <linux/leds.h>
+ #include <linux/i2c-gpio.h>
++#include <linux/mtd/mtd.h>
+
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -151,6 +152,30 @@ static struct platform_device *nas100d_devices[] __initdata = {
+ &nas100d_eth[0],
+ };
+
++static void nas100d_flash_add(struct mtd_info *mtd)
++{
++ if (strcmp(mtd->name, "RedBoot config") == 0) {
++ size_t retlen;
++ u_char mac[6];
++
++ if (mtd->read(mtd, 0x0FD8, 6, &retlen, mac) == 0 && retlen == 6) {
++ printk(KERN_INFO "nas100d mac: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++ memcpy(nas100d_plat_eth[0].hwaddr, mac, 6);
++ } else {
++ printk(KERN_ERR "nas100d mac: read failed\n");
++ }
++ }
++}
++
++static void nas100d_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier nas100d_flash_notifier = {
++ .add = nas100d_flash_add,
++ .remove = nas100d_flash_remove,
++};
++
+ static void nas100d_power_off(void)
+ {
+ /* This causes the box to drop the power and go dead. */
+@@ -183,6 +208,8 @@ static void __init nas100d_init(void)
+ (void)platform_device_register(&nas100d_uart);
+
+ platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices));
++
++ register_mtd_user(&nas100d_flash_notifier);
+ }
+
+ MACHINE_START(NAS100D, "Iomega NAS 100d")
--- /dev/null
+diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
+index ec3d517..7cc7201 100644
+--- a/arch/arm/mach-ixp4xx/fsg-setup.c
++++ b/arch/arm/mach-ixp4xx/fsg-setup.c
+@@ -16,6 +16,7 @@
+ #include <linux/serial_8250.h>
+ #include <linux/leds.h>
+ #include <linux/i2c-gpio.h>
++#include <linux/mtd/mtd.h>
+
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -177,6 +178,34 @@ static struct platform_device *fsg_devices[] __initdata = {
+ &fsg_eth[1],
+ };
+
++static void fsg_flash_add(struct mtd_info *mtd)
++{
++ if (strcmp(mtd->name, "RedBoot config") == 0) {
++ size_t retlen;
++ u_char mac[6];
++
++ if (mtd->read(mtd, 0x0422, 6, &retlen, mac) == 0 && retlen == 6) {
++ printk(KERN_INFO "eth0 mac: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++ memcpy(fsg_plat_eth[0].hwaddr, mac, 6);
++ mac[5]++;
++ printk(KERN_INFO "eth1 mac: %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++ memcpy(fsg_plat_eth[1].hwaddr, mac, 6);
++ } else {
++ printk(KERN_ERR "fsg mac: read failed\n");
++ }
++ }
++}
++
++static void fsg_flash_remove(struct mtd_info *mtd) {
++}
++
++static struct mtd_notifier fsg_flash_notifier = {
++ .add = fsg_flash_add,
++ .remove = fsg_flash_remove,
++};
++
+ static void __init fsg_init(void)
+ {
+ ixp4xx_sys_init();
+@@ -198,6 +227,8 @@ static void __init fsg_init(void)
+ (void)platform_device_register(&fsg_uart);
+
+ platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
++
++ register_mtd_user(&fsg_flash_notifier);
+ }
+
+ MACHINE_START(FSG, "Freecom FSG-3")
--- /dev/null
+Index: linux-2.6.19/drivers/char/random.c
+===================================================================
+--- linux-2.6.19.orig/drivers/char/random.c
++++ linux-2.6.19/drivers/char/random.c
+@@ -248,9 +248,9 @@
+ /*
+ * Configuration information
+ */
+-#define INPUT_POOL_WORDS 128
+-#define OUTPUT_POOL_WORDS 32
+-#define SEC_XFER_SIZE 512
++#define INPUT_POOL_WORDS 256
++#define OUTPUT_POOL_WORDS 64
++#define SEC_XFER_SIZE 1024
+
+ /*
+ * The minimum number of bits of entropy before we wake up a read on
--- /dev/null
+diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/nslu2-setup.c linux-2.6.23/arch/arm/mach-ixp4xx/nslu2-setup.c
+--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/nslu2-setup.c 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/arch/arm/mach-ixp4xx/nslu2-setup.c 2007-10-11 01:04:46.000000000 -0500
+@@ -19,6 +19,7 @@
+ #include <linux/serial_8250.h>
+ #include <linux/leds.h>
+
++#include <asm/setup.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
+@@ -171,6 +172,35 @@ static struct sys_timer nslu2_timer = {
+ .init = nslu2_timer_init,
+ };
+
++static char nslu2_rtc_probe[] __initdata = "rtc-isl1208.ignore=0,0x6f rtc-x1205.probe=0,0x6f ";
++
++static void __init nslu2_fixup(struct machine_desc *desc,
++ struct tag *tags, char **cmdline, struct meminfo *mi)
++{
++ struct tag *t = tags;
++ char *p = *cmdline;
++
++ /* Find the end of the tags table, taking note of any cmdline tag. */
++ for (; t->hdr.size; t = tag_next(t)) {
++ if (t->hdr.tag == ATAG_CMDLINE) {
++ p = t->u.cmdline.cmdline;
++ }
++ }
++
++ /* Overwrite the end of the table with a new cmdline tag. */
++ t->hdr.tag = ATAG_CMDLINE;
++ t->hdr.size = (sizeof (struct tag_header) +
++ strlen(nslu2_rtc_probe) + strlen(p) + 1 + 4) >> 2;
++ strlcpy(t->u.cmdline.cmdline, nslu2_rtc_probe, COMMAND_LINE_SIZE);
++ strlcpy(t->u.cmdline.cmdline + strlen(nslu2_rtc_probe), p,
++ COMMAND_LINE_SIZE - strlen(nslu2_rtc_probe));
++
++ /* Terminate the table. */
++ t = tag_next(t);
++ t->hdr.tag = ATAG_NONE;
++ t->hdr.size = 0;
++}
++
+ static void __init nslu2_init(void)
+ {
+ ixp4xx_sys_init();
+@@ -196,6 +226,7 @@ MACHINE_START(NSLU2, "Linksys NSLU2")
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+ .boot_params = 0x00000100,
++ .fixup = nslu2_fixup,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &nslu2_timer,
--- /dev/null
+diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/nas100d-setup.c linux-2.6.23/arch/arm/mach-ixp4xx/nas100d-setup.c
+--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/nas100d-setup.c 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/arch/arm/mach-ixp4xx/nas100d-setup.c 2007-10-11 01:06:33.000000000 -0500
+@@ -17,6 +17,7 @@
+ #include <linux/serial_8250.h>
+ #include <linux/leds.h>
+
++#include <asm/setup.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
+@@ -142,6 +143,35 @@ static void nas100d_power_off(void)
+ gpio_line_set(NAS100D_PO_GPIO, IXP4XX_GPIO_HIGH);
+ }
+
++static char nas100d_rtc_probe[] __initdata = "rtc-pcf8563.probe=0,0x51 ";
++
++static void __init nas100d_fixup(struct machine_desc *desc,
++ struct tag *tags, char **cmdline, struct meminfo *mi)
++{
++ struct tag *t = tags;
++ char *p = *cmdline;
++
++ /* Find the end of the tags table, taking note of any cmdline tag. */
++ for (; t->hdr.size; t = tag_next(t)) {
++ if (t->hdr.tag == ATAG_CMDLINE) {
++ p = t->u.cmdline.cmdline;
++ }
++ }
++
++ /* Overwrite the end of the table with a new cmdline tag. */
++ t->hdr.tag = ATAG_CMDLINE;
++ t->hdr.size = (sizeof (struct tag_header) +
++ strlen(nas100d_rtc_probe) + strlen(p) + 1 + 4) >> 2;
++ strlcpy(t->u.cmdline.cmdline, nas100d_rtc_probe, COMMAND_LINE_SIZE);
++ strlcpy(t->u.cmdline.cmdline + strlen(nas100d_rtc_probe), p,
++ COMMAND_LINE_SIZE - strlen(nas100d_rtc_probe));
++
++ /* Terminate the table. */
++ t = tag_next(t);
++ t->hdr.tag = ATAG_NONE;
++ t->hdr.size = 0;
++}
++
+ static void __init nas100d_init(void)
+ {
+ ixp4xx_sys_init();
+@@ -170,6 +200,7 @@ MACHINE_START(NAS100D, "Iomega NAS 100d"
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+ .boot_params = 0x00000100,
++ .fixup = nas100d_fixup,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
--- /dev/null
+diff -uprN linux-2.6.23.orig/arch/arm/mach-ixp4xx/avila-setup.c linux-2.6.23/arch/arm/mach-ixp4xx/avila-setup.c
+--- linux-2.6.23.orig/arch/arm/mach-ixp4xx/avila-setup.c 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/arch/arm/mach-ixp4xx/avila-setup.c 2007-10-11 01:08:21.000000000 -0500
+@@ -138,6 +138,35 @@ static struct platform_device *avila_dev
+ &avila_uart
+ };
+
++static char avila_rtc_probe[] __initdata = "rtc-ds1672.probe=0,0x68 ";
++
++static void __init avila_fixup(struct machine_desc *desc,
++ struct tag *tags, char **cmdline, struct meminfo *mi)
++{
++ struct tag *t = tags;
++ char *p = *cmdline;
++
++ /* Find the end of the tags table, taking note of any cmdline tag. */
++ for (; t->hdr.size; t = tag_next(t)) {
++ if (t->hdr.tag == ATAG_CMDLINE) {
++ p = t->u.cmdline.cmdline;
++ }
++ }
++
++ /* Overwrite the end of the table with a new cmdline tag. */
++ t->hdr.tag = ATAG_CMDLINE;
++ t->hdr.size = (sizeof (struct tag_header) +
++ strlen(avila_rtc_probe) + strlen(p) + 1 + 4) >> 2;
++ strlcpy(t->u.cmdline.cmdline, avila_rtc_probe, COMMAND_LINE_SIZE);
++ strlcpy(t->u.cmdline.cmdline + strlen(avila_rtc_probe), p,
++ COMMAND_LINE_SIZE - strlen(avila_rtc_probe));
++
++ /* Terminate the table. */
++ t = tag_next(t);
++ t->hdr.tag = ATAG_NONE;
++ t->hdr.size = 0;
++}
++
+ static void __init avila_init(void)
+ {
+ ixp4xx_sys_init();
+@@ -165,6 +194,7 @@ MACHINE_START(AVILA, "Gateworks Avila Ne
+ /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .fixup = avila_fixup,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
+@@ -182,6 +212,7 @@ MACHINE_START(LOFT, "Giant Shoulder Inc
+ /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .fixup = avila_fixup,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &ixp4xx_timer,
--- /dev/null
+Index: linux-2.6.22-rc4-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c
+===================================================================
+--- linux-2.6.22-rc4-armeb.orig/arch/arm/mach-ixp4xx/dsmg600-setup.c
++++ linux-2.6.22-rc4-armeb/arch/arm/mach-ixp4xx/dsmg600-setup.c
+@@ -16,6 +16,7 @@
+ #include <linux/serial_8250.h>
+ #include <linux/i2c-gpio.h>
+
++#include <asm/setup.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/flash.h>
+@@ -145,6 +146,35 @@ static struct sys_timer dsmg600_timer =
+ .init = dsmg600_timer_init,
+ };
+
++static char dsmg600_rtc_probe[] __initdata = "rtc-pcf8563.probe=0,0x51 ";
++
++static void __init dsmg600_fixup(struct machine_desc *desc,
++ struct tag *tags, char **cmdline, struct meminfo *mi)
++{
++ struct tag *t = tags;
++ char *p = *cmdline;
++
++ /* Find the end of the tags table, taking note of any cmdline tag. */
++ for (; t->hdr.size; t = tag_next(t)) {
++ if (t->hdr.tag == ATAG_CMDLINE) {
++ p = t->u.cmdline.cmdline;
++ }
++ }
++
++ /* Overwrite the end of the table with a new cmdline tag. */
++ t->hdr.tag = ATAG_CMDLINE;
++ t->hdr.size = (sizeof (struct tag_header) +
++ strlen(dsmg600_rtc_probe) + strlen(p) + 1 + 4) >> 2;
++ strlcpy(t->u.cmdline.cmdline, dsmg600_rtc_probe, COMMAND_LINE_SIZE);
++ strlcpy(t->u.cmdline.cmdline + strlen(dsmg600_rtc_probe), p,
++ COMMAND_LINE_SIZE - strlen(dsmg600_rtc_probe));
++
++ /* Terminate the table. */
++ t = tag_next(t);
++ t->hdr.tag = ATAG_NONE;
++ t->hdr.size = 0;
++}
++
+ static void __init dsmg600_init(void)
+ {
+ ixp4xx_sys_init();
+@@ -177,6 +207,7 @@ MACHINE_START(DSMG600, "D-Link DSM-G600
+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+ .boot_params = 0x00000100,
++ .fixup = dsmg600_fixup,
+ .map_io = ixp4xx_map_io,
+ .init_irq = ixp4xx_init_irq,
+ .timer = &dsmg600_timer,
--- /dev/null
+diff -uprN linux-2.6.23.orig/kernel/ksysfs.c linux-2.6.23/kernel/ksysfs.c
+--- linux-2.6.23.orig/kernel/ksysfs.c 2007-10-09 15:31:38.000000000 -0500
++++ linux-2.6.23/kernel/ksysfs.c 2007-10-11 01:10:26.000000000 -0500
+@@ -49,6 +49,165 @@ KERNEL_ATTR_RW(uevent_helper);
+ #endif
+
+ #ifdef CONFIG_KEXEC
++
++#include <asm/setup.h>
++
++extern unsigned long kexec_boot_params;
++
++char kexec_cmdline[COMMAND_LINE_SIZE] = "";
++
++static void
++replace_cmdline_tag(void)
++{
++ char *t;
++ struct tag *real;
++ struct tag *copy;
++ struct tag *rend;
++ int i;
++
++/* TODO: check the return params */
++ t = kmalloc(KEXEC_BOOT_PARAMS_SIZE + COMMAND_LINE_SIZE, GFP_KERNEL);
++ memset((void *)t, 0, KEXEC_BOOT_PARAMS_SIZE + COMMAND_LINE_SIZE);
++
++/* TODO: validate that the boot params are ATAGS, in fact */
++
++ copy = (struct tag *)t;
++ real = (struct tag *)kexec_boot_params;
++ rend = (struct tag *)(kexec_boot_params + KEXEC_BOOT_PARAMS_SIZE);
++ while ((real->hdr.size) && (real < rend)) {
++ if (real->hdr.tag != ATAG_CMDLINE) {
++ memcpy((void *)copy, (void *)real, real->hdr.size * 4);
++ copy = tag_next(copy);
++ }
++ real = tag_next(real);
++ }
++
++/* TODO: validate that we have enough space in the buffer */
++
++ i = strlen(kexec_cmdline);
++ if (i) {
++ copy->hdr.tag = ATAG_CMDLINE;
++ copy->hdr.size = (sizeof(struct tag_header) + i + 1 + 4) >> 2;
++ strcpy(copy->u.cmdline.cmdline, kexec_cmdline);
++ copy = tag_next(copy);
++ }
++
++ copy->hdr.tag = ATAG_NONE; /* Empty tag ends list */
++ copy->hdr.size = 0; /* zero length */
++
++/* TODO: validate that the temporary buffer isn't too full */
++
++ memcpy((void *)kexec_boot_params, (void *)t, KEXEC_BOOT_PARAMS_SIZE);
++
++ kfree(t); /* Don't forget to free the big buffer we used */
++}
++
++static ssize_t kexec_cmdline_show(struct kset *kset, char *page)
++{
++ return sprintf(page, "%s\n", kexec_cmdline);
++}
++
++static ssize_t kexec_cmdline_store(struct kset *kset, const char *page,
++ size_t count)
++{
++ if ((count + 1) > COMMAND_LINE_SIZE)
++ count = COMMAND_LINE_SIZE;
++ memcpy(kexec_cmdline, page, count);
++ kexec_cmdline[count] = '\0';
++ if (count && (kexec_cmdline[count - 1] == '\n'))
++ kexec_cmdline[count - 1] = '\0';
++ replace_cmdline_tag();
++ return count;
++}
++KERNEL_ATTR_RW(kexec_cmdline);
++
++static ssize_t kexec_boot_params_show(struct kset *kset, char *page)
++{
++ unsigned long *p;
++ char buf[PAGE_SIZE];
++ int keep_doing;
++
++ p = (unsigned long *)kexec_boot_params;
++
++ /* if this doesn't look like atags, just print first few words */
++ if (p[1] != ATAG_CORE)
++ return sprintf(page, "0x%lx 0x%lx 0x%lx 0x%lx\n",
++ p[0], p[1], p[2], p[3]);
++
++ /* carefully walk the atag list, and print out the structure */
++ keep_doing = 1;
++ do {
++ switch (p[1]) {
++ case ATAG_CORE:
++ /* watch out, core tag is permitted to be empty */
++ if (p[0] == 5)
++ sprintf(buf,
++ "CORE flg=%ld pgsz=%ld rdev=0x%lx\n",
++ p[2], p[3], p[4]);
++ else
++ sprintf(buf,"CORE\n");
++ break;
++ case ATAG_MEM:
++ sprintf(buf,"MEM %ldM@0x%lx\n", p[2] / (1024 * 1024),
++ p[3]);
++ break;
++ case ATAG_VIDEOTEXT:
++ sprintf(buf,"VIDEOTEXT sz=%ld\n", p[0]);
++ break;
++ case ATAG_RAMDISK:
++ sprintf(buf,"RAMDISK prmpt=%ld %ldK@0x%lx\n",
++ p[2], p[3], p[4]);
++ break;
++ case ATAG_INITRD2:
++ sprintf(buf,"INITRD2 %ldK@0x%lx\n", p[3] / 1024, p[2]);
++ break;
++ case ATAG_SERIAL:
++ sprintf(buf,"SERIAL high=0x%08lx low=0x%08lx\n",
++ p[3], p[2]);
++ break;
++ case ATAG_REVISION:
++ sprintf(buf,"REVISION rev=%ld\n", p[2]);
++ break;
++ case ATAG_VIDEOLFB:
++ sprintf(buf,"VIDEOLFB sz=%ld\n", p[0]);
++ break;
++ case ATAG_CMDLINE:
++ sprintf(buf,"CMD \"%s\"\n", (char *)&p[2]);
++ break;
++ case ATAG_NONE:
++ sprintf(buf,"NONE\n");
++ keep_doing = 0;
++ break;
++ default:
++ sprintf(buf,"-unknown- sz=%ld\n", p[0]);
++ break;
++ }
++
++ /* carefully add to page */
++ if ((strlen(buf) + strlen(page)) < PAGE_SIZE) {
++ strcat(page, buf);
++ } else {
++ keep_doing = 0;
++ }
++
++ /* stop when we encounter a header length of 0 */
++ if (p[0] == 0)
++ keep_doing = 0;
++
++ /* go to the next tag */
++ p += p[0];
++
++ /* stop if we walked off the end of the buffer */
++ if (p > (unsigned long *)(kexec_boot_params +
++ KEXEC_BOOT_PARAMS_SIZE))
++ keep_doing = 0;
++
++ } while (keep_doing);
++
++ return (strlen(page));
++}
++KERNEL_ATTR_RO(kexec_boot_params);
++
+ static ssize_t kexec_loaded_show(struct kset *kset, char *page)
+ {
+ return sprintf(page, "%d\n", !!kexec_image);
+@@ -95,6 +254,8 @@ static struct attribute * kernel_attrs[]
+ #ifdef CONFIG_KEXEC
+ &kexec_loaded_attr.attr,
+ &kexec_crash_loaded_attr.attr,
++ &kexec_cmdline_attr.attr,
++ &kexec_boot_params_attr.attr,
+ #endif
+ NULL
+ };
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/gateway7001-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/gateway7001-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/gateway7001-setup.c 2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/gateway7001-setup.c 2007-10-22 15:09:33.000000000 +0200
+@@ -76,9 +76,36 @@
+ .resource = &gateway7001_uart_resource,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info gateway7001_plat_eth[] = {
++ {
++ .phy = 1,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 2,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device gateway7001_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = gateway7001_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = gateway7001_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *gateway7001_devices[] __initdata = {
+ &gateway7001_flash,
+- &gateway7001_uart
++ &gateway7001_uart,
++ &gateway7001_eth[0],
++ &gateway7001_eth[1],
+ };
+
+ static void __init gateway7001_init(void)
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/wg302v2-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wg302v2-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/wg302v2-setup.c 2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wg302v2-setup.c 2007-10-22 15:02:20.000000000 +0200
+@@ -77,9 +77,27 @@
+ .resource = &wg302v2_uart_resource,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info wg302_plat_eth[] = {
++ {
++ .phy = 8,
++ .rxq = 3,
++ .txreadyq = 20,
++ }
++};
++
++static struct platform_device wg302_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = wg302_plat_eth,
++ }
++};
++
+ static struct platform_device *wg302v2_devices[] __initdata = {
+ &wg302v2_flash,
+ &wg302v2_uart,
++ &wg302_eth[0],
+ };
+
+ static void __init wg302v2_init(void)
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-22 14:47:50.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig 2007-10-22 15:16:43.000000000 +0200
+@@ -57,6 +57,14 @@
+ WG302 v2 or WAG302 v2 Access Points. For more information
+ on this platform, see http://openwrt.org
+
++config MACH_PRONGHORNMETRO
++ bool "Pronghorn Metro"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support the ADI
++ Engineering Pronghorn Metro Platform. For more
++ information on this platform, see <file:Documentation/arm/IXP4xx>.
++
+ config ARCH_IXDP425
+ bool "IXDP425"
+ help
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Makefile linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-22 14:47:50.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile 2007-10-22 15:26:15.000000000 +0200
+@@ -16,6 +16,7 @@
+ obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
+ obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
+ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
++obj-pci-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-pci.o
+
+ obj-y += common.o
+
+@@ -30,6 +31,7 @@
+ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
+ obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
+ obj-$(CONFIG_MACH_FSG) += fsg-setup.o
++obj-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/pronghornmetro-pci.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/pronghornmetro-pci.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/pronghornmetro-pci.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/pronghornmetro-pci.c 2007-10-22 15:16:43.000000000 +0200
+@@ -0,0 +1,74 @@
++/*
++ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c
++ *
++ * PCI setup routines for ADI Engineering Pronghorn Metro
++ *
++ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init pronghornmetro_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO4, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO1, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init pronghornmetro_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 13)
++ return IRQ_IXP4XX_GPIO4;
++ else if (slot == 14)
++ return IRQ_IXP4XX_GPIO6;
++ else if (slot == 15)
++ return IRQ_IXP4XX_GPIO11;
++ else if (slot == 16)
++ return IRQ_IXP4XX_GPIO1;
++ else return -1;
++}
++
++struct hw_pci pronghornmetro_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = pronghornmetro_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = pronghornmetro_map_irq,
++};
++
++int __init pronghornmetro_pci_init(void)
++{
++ if (machine_is_pronghorn_metro())
++ pci_common_init(&pronghornmetro_pci);
++ return 0;
++}
++
++subsys_initcall(pronghornmetro_pci_init);
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/pronghornmetro-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/pronghornmetro-setup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c 2007-10-22 15:36:35.000000000 +0200
+@@ -0,0 +1,147 @@
++/*
++ * arch/arm/mach-ixp4xx/pronghornmetro-setup.c
++ *
++ * Board setup for the ADI Engineering Pronghorn Metro
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data pronghornmetro_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource pronghornmetro_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device pronghornmetro_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &pronghornmetro_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &pronghornmetro_flash_resource,
++};
++
++static struct resource pronghornmetro_uart_resource = {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port pronghornmetro_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device pronghornmetro_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = pronghornmetro_uart_data,
++ },
++ .num_resources = 1,
++ .resource = &pronghornmetro_uart_resource,
++};
++
++static struct resource pronghornmetro_pata_resources[] = {
++ {
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "intrq",
++ .start = IRQ_IXP4XX_GPIO0,
++ .end = IRQ_IXP4XX_GPIO0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct ixp4xx_pata_data pronghornmetro_pata_data = {
++ .cs0_bits = 0xbfff0043,
++ .cs1_bits = 0xbfff0043,
++};
++
++static struct platform_device pronghornmetro_pata = {
++ .name = "pata_ixp4xx_cf",
++ .id = 0,
++ .dev.platform_data = &pronghornmetro_pata_data,
++ .num_resources = ARRAY_SIZE(pronghornmetro_pata_resources),
++ .resource = pronghornmetro_pata_resources,
++};
++
++static struct platform_device *pronghornmetro_devices[] __initdata = {
++ &pronghornmetro_flash,
++ &pronghornmetro_uart,
++};
++
++static void __init pronghornmetro_init(void)
++{
++ ixp4xx_sys_init();
++
++ pronghornmetro_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ pronghornmetro_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_16M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(pronghornmetro_devices, ARRAY_SIZE(pronghornmetro_devices));
++
++ pronghornmetro_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1);
++ pronghornmetro_pata_resources[0].end = IXP4XX_EXP_BUS_END(1);
++
++ pronghornmetro_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
++ pronghornmetro_pata_resources[1].end = IXP4XX_EXP_BUS_END(2);
++
++ pronghornmetro_pata_data.cs0_cfg = IXP4XX_EXP_CS1;
++ pronghornmetro_pata_data.cs1_cfg = IXP4XX_EXP_CS2;
++
++ platform_device_register(&pronghornmetro_pata);
++}
++
++#ifdef CONFIG_MACH_PRONGHORNMETRO
++MACHINE_START(PRONGHORNMETRO, "ADI Engineering Pronghorn Metro")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = pronghornmetro_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.23/Documentation/arm/IXP4xx linux-2.6.23-owrt/Documentation/arm/IXP4xx
+--- linux-2.6.23/Documentation/arm/IXP4xx 2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23-owrt/Documentation/arm/IXP4xx 2007-10-22 15:16:43.000000000 +0200
+@@ -111,6 +111,9 @@
+ the platform has two mini-PCI slots used for 802.11[bga] cards.
+ Finally, there is an IDE port hanging off the expansion bus.
+
++ADI Engineering Pronghorn Metro Platform
++http://www.adiengineering.com/php-bin/ecomm4/productDisplay.php?category_id=30&product_id=85
++
+ Gateworks Avila Network Platform
+ http://www.gateworks.com/avila_sbc.htm
+
+diff -Nur linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h linux-2.6.23-owrt/include/asm-arm/arch-ixp4xx/uncompress.h
+--- linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-22 14:47:50.000000000 +0200
++++ linux-2.6.23-owrt/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-22 15:18:47.000000000 +0200
+@@ -41,7 +41,8 @@
+ * Some boards are using UART2 as console
+ */
+ if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
+- machine_is_gateway7001() || machine_is_wg302v2())
++ machine_is_gateway7001() || machine_is_wg302v2() ||
++ machine_is_pronghorn_metro())
+ uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+ else
+ uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/pronghornmetro-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/pronghornmetro-setup.c 2007-10-22 15:41:27.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/pronghornmetro-setup.c 2007-10-22 15:43:30.000000000 +0200
+@@ -104,9 +104,36 @@
+ .resource = pronghornmetro_pata_resources,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info pronghornmetro_plat_eth[] = {
++ {
++ .phy = 0,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device pronghornmetro_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = pronghornmetro_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = pronghornmetro_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *pronghornmetro_devices[] __initdata = {
+ &pronghornmetro_flash,
+ &pronghornmetro_uart,
++ &pronghornmetro_eth[0],
++ &pronghornmetro_eth[1],
+ };
+
+ static void __init pronghornmetro_init(void)
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 18:03:34.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 18:22:41.000000000 +0200
+@@ -65,6 +65,14 @@
+ Engineering Pronghorn Metro Platform. For more
+ information on this platform, see <file:Documentation/arm/IXP4xx>.
+
++config MACH_COMPEX
++ bool "Compex WP18 / NP18A"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support Compex'
++ WP18 or NP18A boards. For more information on this
++ platform, see http://openwrt.org
++
+ config ARCH_IXDP425
+ bool "IXDP425"
+ help
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Makefile linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-23 18:03:34.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile 2007-10-23 18:22:41.000000000 +0200
+@@ -17,6 +17,7 @@
+ obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
+ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
+ obj-pci-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-pci.o
++obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
+
+ obj-y += common.o
+
+@@ -32,6 +33,7 @@
+ obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
+ obj-$(CONFIG_MACH_FSG) += fsg-setup.o
+ obj-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-setup.o
++obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/compex-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/compex-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/compex-setup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/compex-setup.c 2007-10-23 18:22:41.000000000 +0200
+@@ -0,0 +1,120 @@
++/*
++ * arch/arm/mach-ixp4xx/compex-setup.c
++ *
++ * Ccompex WP18 / NP18A board-setup
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on ixdp425-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/mach-types.h>
++#include <asm/irq.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data compex_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource compex_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device compex_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &compex_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &compex_flash_resource,
++};
++
++static struct resource compex_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ }
++};
++
++static struct plat_serial8250_port compex_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device compex_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev.platform_data = compex_uart_data,
++ .num_resources = 2,
++ .resource = compex_uart_resources,
++};
++
++static struct platform_device *compex_devices[] __initdata = {
++ &compex_flash,
++ &compex_uart
++};
++
++static void __init compex_init(void)
++{
++ ixp4xx_sys_init();
++
++ compex_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ compex_flash_resource.end =
++ IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++ platform_add_devices(compex_devices, ARRAY_SIZE(compex_devices));
++}
++
++#ifdef CONFIG_MACH_COMPEX
++MACHINE_START(COMPEX, "Compex WP18 / NP18A")
++ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = compex_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-pci.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-pci.c 2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c 2007-10-23 18:22:41.000000000 +0200
+@@ -66,7 +66,7 @@
+ int __init ixdp425_pci_init(void)
+ {
+ if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
+- machine_is_ixdp465() || machine_is_kixrp435())
++ machine_is_ixdp465() || machine_is_kixrp435() || machine_is_compex())
+ pci_common_init(&ixdp425_pci);
+ return 0;
+ }
+diff -Nur linux-2.6.23/arch/arm/tools/mach-types linux-2.6.23-owrt/arch/arm/tools/mach-types
+--- linux-2.6.23/arch/arm/tools/mach-types 2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/tools/mach-types 2007-10-23 18:22:41.000000000 +0200
+@@ -1278,7 +1278,7 @@
+ smdk6400 MACH_SMDK6400 SMDK6400 1270
+ nokia_n800 MACH_NOKIA_N800 NOKIA_N800 1271
+ greenphone MACH_GREENPHONE GREENPHONE 1272
+-compex42x MACH_COMPEXWP18 COMPEXWP18 1273
++compex MACH_COMPEX COMPEX 1273
+ xmate MACH_XMATE XMATE 1274
+ energizer MACH_ENERGIZER ENERGIZER 1275
+ ime1 MACH_IME1 IME1 1276
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/compex-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/compex-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/compex-setup.c 2007-10-23 18:39:29.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/compex-setup.c 2007-10-23 18:45:34.000000000 +0200
+@@ -90,9 +90,36 @@
+ .resource = compex_uart_resources,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info compex_plat_eth[] = {
++ {
++ .phy = -1,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 3,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device compex_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = compex_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = compex_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *compex_devices[] __initdata = {
+ &compex_flash,
+- &compex_uart
++ &compex_uart,
++ &compex_eth[0],
++ &compex_eth[1],
+ };
+
+ static void __init compex_init(void)
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 18:39:29.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 19:11:31.000000000 +0200
+@@ -73,6 +73,14 @@
+ WP18 or NP18A boards. For more information on this
+ platform, see http://openwrt.org
+
++config MACH_WRT300NV2
++ bool "Linksys WRT300N v2"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support Linksys'
++ WRT300N v2 router. For more information on this
++ platform, see http://openwrt.org
++
+ config ARCH_IXDP425
+ bool "IXDP425"
+ help
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Makefile linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-23 18:39:29.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile 2007-10-23 19:11:31.000000000 +0200
+@@ -18,6 +18,7 @@
+ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
+ obj-pci-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-pci.o
+ obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
++obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
+
+ obj-y += common.o
+
+@@ -34,6 +35,7 @@
+ obj-$(CONFIG_MACH_FSG) += fsg-setup.o
+ obj-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-setup.o
+ obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
++obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-pci.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-pci.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-pci.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-pci.c 2007-10-23 19:11:31.000000000 +0200
+@@ -0,0 +1,65 @@
++/*
++ * arch/arch/mach-ixp4xx/wrt300nv2-pci.c
++ *
++ * PCI setup routines for Linksys WRT300N v2
++ *
++ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init wrt300nv2_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init wrt300nv2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 1)
++ return IRQ_IXP4XX_GPIO8;
++ else return -1;
++}
++
++struct hw_pci wrt300nv2_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = wrt300nv2_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = wrt300nv2_map_irq,
++};
++
++int __init wrt300nv2_pci_init(void)
++{
++ if (machine_is_wrt300nv2())
++ pci_common_init(&wrt300nv2_pci);
++ return 0;
++}
++
++subsys_initcall(wrt300nv2_pci_init);
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-setup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c 2007-10-23 19:11:31.000000000 +0200
+@@ -0,0 +1,108 @@
++/*
++ * arch/arm/mach-ixp4xx/wrt300nv2-setup.c
++ *
++ * Board setup for the Linksys WRT300N v2
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data wrt300nv2_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource wrt300nv2_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device wrt300nv2_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &wrt300nv2_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &wrt300nv2_flash_resource,
++};
++
++static struct resource wrt300nv2_uart_resource = {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct plat_serial8250_port wrt300nv2_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device wrt300nv2_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = wrt300nv2_uart_data,
++ },
++ .num_resources = 1,
++ .resource = &wrt300nv2_uart_resource,
++};
++
++static struct platform_device *wrt300nv2_devices[] __initdata = {
++ &wrt300nv2_flash,
++ &wrt300nv2_uart
++};
++
++static void __init wrt300nv2_init(void)
++{
++ ixp4xx_sys_init();
++
++ wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ wrt300nv2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices));
++}
++
++#ifdef CONFIG_MACH_WRT300NV2
++MACHINE_START(WRT300NV2, "Linksys WRT300N v2")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = wrt300nv2_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h linux-2.6.23-owrt/include/asm-arm/arch-ixp4xx/uncompress.h
+--- linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-23 18:03:35.000000000 +0200
++++ linux-2.6.23-owrt/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-23 19:12:30.000000000 +0200
+@@ -42,7 +42,7 @@
+ */
+ if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
+ machine_is_gateway7001() || machine_is_wg302v2() ||
+- machine_is_pronghorn_metro())
++ machine_is_pronghorn_metro() || machine_is_wrt300nv2())
+ uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+ else
+ uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/wrt300nv2-setup.c 2007-10-23 19:20:08.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/wrt300nv2-setup.c 2007-10-23 19:22:19.000000000 +0200
+@@ -76,9 +76,36 @@
+ .resource = &wrt300nv2_uart_resource,
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info wrt300nv2_plat_eth[] = {
++ {
++ .phy = -1,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device wrt300nv2_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = wrt300nv2_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = wrt300nv2_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *wrt300nv2_devices[] __initdata = {
+ &wrt300nv2_flash,
+- &wrt300nv2_uart
++ &wrt300nv2_uart,
++ &wrt300nv2_eth[0],
++ &wrt300nv2_eth[1],
+ };
+
+ static void __init wrt300nv2_init(void)
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 19:20:08.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Kconfig 2007-10-23 19:26:46.000000000 +0200
+@@ -65,6 +65,14 @@
+ Engineering Pronghorn Metro Platform. For more
+ information on this platform, see <file:Documentation/arm/IXP4xx>.
+
++config MACH_SIDEWINDER
++ bool "Sidewinder"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support the ADI
++ Engineering Sidewinder Platform. For more
++ information on this platform, see <file:Documentation/arm/IXP4xx>.
++
+ config MACH_COMPEX
+ bool "Compex WP18 / NP18A"
+ select PCI
+@@ -163,7 +171,7 @@
+ #
+ config CPU_IXP46X
+ bool
+- depends on MACH_IXDP465
++ depends on MACH_IXDP465 || MACH_SIDEWINDER
+ default y
+
+ config CPU_IXP43X
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/Makefile linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-23 19:20:08.000000000 +0200
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/Makefile 2007-10-23 19:23:52.000000000 +0200
+@@ -19,6 +19,7 @@
+ obj-pci-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-pci.o
+ obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
+ obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
++obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
+
+ obj-y += common.o
+
+@@ -36,6 +37,7 @@
+ obj-$(CONFIG_MACH_PRONGHORNMETRO) += pronghornmetro-setup.o
+ obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
+ obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
++obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/sidewinder-pci.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/sidewinder-pci.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/sidewinder-pci.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/sidewinder-pci.c 2007-10-23 19:23:52.000000000 +0200
+@@ -0,0 +1,71 @@
++/*
++ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c
++ *
++ * PCI setup routines for ADI Engineering Sidewinder
++ *
++ * Copyright (C) 2007 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * based on coyote-pci.c:
++ * Copyright (C) 2002 Jungo Software Technologies.
++ * Copyright (C) 2003 MontaVista Softwrae, Inc.
++ *
++ * Maintainer: Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++
++#include <asm/mach-types.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++
++#include <asm/mach/pci.h>
++
++extern void ixp4xx_pci_preinit(void);
++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
++
++void __init sidewinder_pci_preinit(void)
++{
++ set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
++ set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init sidewinder_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ if (slot == 1)
++ return IRQ_IXP4XX_GPIO11;
++ else if (slot == 2)
++ return IRQ_IXP4XX_GPIO10;
++ else if (slot == 3)
++ return IRQ_IXP4XX_GPIO9;
++ else return -1;
++}
++
++struct hw_pci sidewinder_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = sidewinder_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = sidewinder_map_irq,
++};
++
++int __init sidewinder_pci_init(void)
++{
++ if (machine_is_sidewinder())
++ pci_common_init(&sidewinder_pci);
++ return 0;
++}
++
++subsys_initcall(sidewinder_pci_init);
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/sidewinder-setup.c linux-2.6.23-owrt/arch/arm/mach-ixp4xx/sidewinder-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/sidewinder-setup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.23-owrt/arch/arm/mach-ixp4xx/sidewinder-setup.c 2007-10-23 19:23:52.000000000 +0200
+@@ -0,0 +1,115 @@
++/*
++ * arch/arm/mach-ixp4xx/sidewinder-setup.c
++ *
++ * Board setup for the ADI Engineering Sidewinder
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on coyote-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/serial.h>
++#include <linux/serial_8250.h>
++
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data sidewinder_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource sidewinder_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device sidewinder_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &sidewinder_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &sidewinder_flash_resource,
++};
++
++static struct resource sidewinder_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++static struct plat_serial8250_port sidewinder_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device sidewinder_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = sidewinder_uart_data,
++ },
++ .num_resources = 2,
++ .resource = &sidewinder_uart_resources,
++};
++
++static struct platform_device *sidewinder_devices[] __initdata = {
++ &sidewinder_flash,
++ &sidewinder_uart,
++};
++
++static void __init sidewinder_init(void)
++{
++ ixp4xx_sys_init();
++
++ sidewinder_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ sidewinder_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_64M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
++
++ platform_add_devices(sidewinder_devices, ARRAY_SIZE(sidewinder_devices));
++}
++
++#ifdef CONFIG_MACH_SIDEWINDER
++MACHINE_START(SIDEWINDER, "ADI Engineering Sidewinder")
++ /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = sidewinder_init,
++MACHINE_END
++#endif
--- /dev/null
+diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c
+--- linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c 2007-11-14 13:58:58.000000000 +0100
+@@ -0,0 +1,151 @@
++/*
++ * arch/arm/mach-ixp4xx/ap1000-setup.c
++ *
++ * Lanready AP-1000
++ *
++ * Copyright (C) 2007 Imre Kaloz <Kaloz@openwrt.org>
++ *
++ * based on ixdp425-setup.c:
++ * Copyright (C) 2003-2005 MontaVista Software, Inc.
++ *
++ * Author: Imre Kaloz <Kaloz@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/mach-types.h>
++#include <asm/irq.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++
++static struct flash_platform_data ap1000_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource ap1000_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device ap1000_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &ap1000_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &ap1000_flash_resource,
++};
++
++static struct resource ap1000_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM
++ }
++};
++
++static struct plat_serial8250_port ap1000_uart_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device ap1000_uart = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev.platform_data = ap1000_uart_data,
++ .num_resources = 2,
++ .resource = ap1000_uart_resources
++};
++
++static struct platform_device *ap1000_devices[] __initdata = {
++ &ap1000_flash,
++ &ap1000_uart
++};
++
++static char ap1000_mem_fixup[] __initdata = "mem=64M ";
++
++static void __init ap1000_fixup(struct machine_desc *desc,
++ struct tag *tags, char **cmdline, struct meminfo *mi)
++
++{
++ struct tag *t = tags;
++ char *p = *cmdline;
++
++ /* Find the end of the tags table, taking note of any cmdline tag. */
++ for (; t->hdr.size; t = tag_next(t)) {
++ if (t->hdr.tag == ATAG_CMDLINE) {
++ p = t->u.cmdline.cmdline;
++ }
++ }
++
++ /* Overwrite the end of the table with a new cmdline tag. */
++ t->hdr.tag = ATAG_CMDLINE;
++ t->hdr.size = (sizeof (struct tag_header) +
++ strlen(ap1000_mem_fixup) + strlen(p) + 1 + 4) >> 2;
++ strlcpy(t->u.cmdline.cmdline, ap1000_mem_fixup, COMMAND_LINE_SIZE);
++ strlcpy(t->u.cmdline.cmdline + strlen(ap1000_mem_fixup), p,
++ COMMAND_LINE_SIZE - strlen(ap1000_mem_fixup));
++
++ /* Terminate the table. */
++ t = tag_next(t);
++ t->hdr.tag = ATAG_NONE;
++ t->hdr.size = 0;
++}
++
++static void __init ap1000_init(void)
++{
++ ixp4xx_sys_init();
++
++ ap1000_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ ap1000_flash_resource.end =
++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
++
++ platform_add_devices(ap1000_devices, ARRAY_SIZE(ap1000_devices));
++}
++
++#ifdef CONFIG_MACH_AP1000
++MACHINE_START(AP1000, "Lanready AP-1000")
++ /* Maintainer: Imre Kaloz <Kaloz@openwrt.org> */
++ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
++ .fixup = ap1000_fixup,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = ap1000_init,
++MACHINE_END
++#endif
+diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/ixdp425-pci.c linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c
+--- linux-2.6.23.1/arch/arm/mach-ixp4xx/ixdp425-pci.c 2007-11-14 13:15:50.000000000 +0100
++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ixdp425-pci.c 2007-11-14 13:27:16.000000000 +0100
+@@ -66,7 +66,8 @@
+ int __init ixdp425_pci_init(void)
+ {
+ if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
+- machine_is_ixdp465() || machine_is_kixrp435() || machine_is_compex())
++ machine_is_ixdp465() || machine_is_kixrp435() ||
++ machine_is_compex() || machine_is_ap1000())
+ pci_common_init(&ixdp425_pci);
+ return 0;
+ }
+diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/Kconfig linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.23.1/arch/arm/mach-ixp4xx/Kconfig 2007-11-14 13:15:50.000000000 +0100
++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/Kconfig 2007-11-14 13:25:07.000000000 +0100
+@@ -89,6 +89,14 @@
+ WRT300N v2 router. For more information on this
+ platform, see http://openwrt.org
+
++config MACH_AP1000
++ bool "Lanready AP-1000"
++ select PCI
++ help
++ Say 'Y' here if you want your kernel to support Lanready's
++ AP1000 board. For more information on this
++ platform, see http://openwrt.org
++
+ config ARCH_IXDP425
+ bool "IXDP425"
+ help
+diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/Makefile linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.23.1/arch/arm/mach-ixp4xx/Makefile 2007-11-14 13:15:50.000000000 +0100
++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/Makefile 2007-11-14 13:31:29.000000000 +0100
+@@ -20,6 +20,7 @@
+ obj-pci-$(CONFIG_MACH_COMPEX) += ixdp425-pci.o
+ obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
+ obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o
++obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
+
+ obj-y += common.o
+
+@@ -38,5 +39,6 @@
+ obj-$(CONFIG_MACH_COMPEX) += compex-setup.o
+ obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
+ obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o
++obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+diff -Nur linux-2.6.23.1/arch/arm/tools/mach-types linux-2.6.23.1-owrt/arch/arm/tools/mach-types
+--- linux-2.6.23.1/arch/arm/tools/mach-types 2007-11-14 13:15:50.000000000 +0100
++++ linux-2.6.23.1-owrt/arch/arm/tools/mach-types 2007-11-14 13:26:06.000000000 +0100
+@@ -1367,3 +1367,4 @@
+ csb726 MACH_CSB726 CSB726 1359
+ tik27 MACH_TIK27 TIK27 1360
+ mx_uc7420 MACH_MX_UC7420 MX_UC7420 1361
++ap1000 MACH_AP1000 AP1000 1543
--- /dev/null
+diff -Nur linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c
+--- linux-2.6.23.1/arch/arm/mach-ixp4xx/ap1000-setup.c 2007-11-14 14:11:10.000000000 +0100
++++ linux-2.6.23.1-owrt/arch/arm/mach-ixp4xx/ap1000-setup.c 2007-11-14 14:09:30.000000000 +0100
+@@ -90,9 +90,36 @@
+ .resource = ap1000_uart_resources
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info ap1000_plat_eth[] = {
++ {
++ .phy = 4,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 5,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device ap1000_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = ap1000_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = ap1000_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *ap1000_devices[] __initdata = {
+ &ap1000_flash,
+- &ap1000_uart
++ &ap1000_uart,
++ &ap1000_eth[0],
++ &ap1000_eth[1],
+ };
+
+ static char ap1000_mem_fixup[] __initdata = "mem=64M ";
--- /dev/null
+diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/kernel/setup.c ixp4xx-nep.git/arch/arm/kernel/setup.c
+--- linux-2.6.23/arch/arm/kernel/setup.c 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/arch/arm/kernel/setup.c 2007-10-22 19:19:41.000000000 +0200
+@@ -61,6 +61,7 @@
+ extern void _stext, _text, _etext, __data_start, _edata, _end;
+
+ unsigned int processor_id;
++EXPORT_SYMBOL(processor_id);
+ unsigned int __machine_arch_type;
+ EXPORT_SYMBOL(__machine_arch_type);
+
+diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig ixp4xx-nep.git/arch/arm/mach-ixp4xx/Kconfig
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Kconfig 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/Kconfig 2007-10-22 19:19:41.000000000 +0200
+@@ -189,6 +189,20 @@
+ need to use the indirect method instead. If you don't know
+ what you need, leave this option unselected.
+
++config IXP4XX_QMGR
++ tristate "IXP4xx Queue Manager support"
++ help
++ This driver supports IXP4xx built-in hardware queue manager
++ and is automatically selected by Ethernet and HSS drivers.
++
++config IXP4XX_NPE
++ tristate "IXP4xx Network Processor Engine support"
++ select HOTPLUG
++ select FW_LOADER
++ help
++ This driver supports IXP4xx built-in network coprocessors
++ and is automatically selected by Ethernet and HSS drivers.
++
+ endmenu
+
+ endif
+diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/Makefile ixp4xx-nep.git/arch/arm/mach-ixp4xx/Makefile
+--- linux-2.6.23/arch/arm/mach-ixp4xx/Makefile 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/Makefile 2007-10-22 19:19:41.000000000 +0200
+@@ -30,3 +30,5 @@
+ obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
++obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
++obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
+diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-setup.c ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixdp425-setup.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/ixdp425-setup.c 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixdp425-setup.c 2007-10-22 19:19:41.000000000 +0200
+@@ -177,6 +177,31 @@
+ .resource = ixdp425_uart_resources
+ };
+
++/* Built-in 10/100 Ethernet MAC interfaces */
++static struct eth_plat_info ixdp425_plat_eth[] = {
++ {
++ .phy = 0,
++ .rxq = 3,
++ .txreadyq = 20,
++ }, {
++ .phy = 1,
++ .rxq = 4,
++ .txreadyq = 21,
++ }
++};
++
++static struct platform_device ixdp425_eth[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = ixdp425_plat_eth,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = ixdp425_plat_eth + 1,
++ }
++};
++
+ static struct platform_device *ixdp425_devices[] __initdata = {
+ &ixdp425_i2c_controller,
+ &ixdp425_flash,
+@@ -184,7 +209,9 @@
+ defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+ &ixdp425_flash_nand,
+ #endif
+- &ixdp425_uart
++ &ixdp425_uart,
++ &ixdp425_eth[0],
++ &ixdp425_eth[1],
+ };
+
+ static void __init ixdp425_init(void)
+diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_npe.c ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_npe.c 1970-01-01 01:00:00.000000000 +0100
++++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixp4xx_npe.c 2007-10-22 19:19:41.000000000 +0200
+@@ -0,0 +1,737 @@
++/*
++ * Intel IXP4xx Network Processor Engine driver for Linux
++ *
++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License
++ * as published by the Free Software Foundation.
++ *
++ * The code is based on publicly available information:
++ * - Intel IXP4xx Developer's Manual and other e-papers
++ * - Intel IXP400 Access Library Software (BSD license)
++ * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
++ * Thanks, Christian.
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/firmware.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <asm/delay.h>
++#include <asm/io.h>
++#include <asm/arch/npe.h>
++
++#define DEBUG_MSG 0
++#define DEBUG_FW 0
++
++#define NPE_COUNT 3
++#define MAX_RETRIES 1000 /* microseconds */
++#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
++#define NPE_46X_DATA_SIZE 0x1000
++#define NPE_A_42X_INSTR_SIZE 0x1000
++#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
++#define NPE_46X_INSTR_SIZE 0x1000
++#define REGS_SIZE 0x1000
++
++#define NPE_PHYS_REG 32
++
++#define FW_MAGIC 0xFEEDF00D
++#define FW_BLOCK_TYPE_INSTR 0x0
++#define FW_BLOCK_TYPE_DATA 0x1
++#define FW_BLOCK_TYPE_EOF 0xF
++
++/* NPE exec status (read) and command (write) */
++#define CMD_NPE_STEP 0x01
++#define CMD_NPE_START 0x02
++#define CMD_NPE_STOP 0x03
++#define CMD_NPE_CLR_PIPE 0x04
++#define CMD_CLR_PROFILE_CNT 0x0C
++#define CMD_RD_INS_MEM 0x10 /* instruction memory */
++#define CMD_WR_INS_MEM 0x11
++#define CMD_RD_DATA_MEM 0x12 /* data memory */
++#define CMD_WR_DATA_MEM 0x13
++#define CMD_RD_ECS_REG 0x14 /* exec access register */
++#define CMD_WR_ECS_REG 0x15
++
++#define STAT_RUN 0x80000000
++#define STAT_STOP 0x40000000
++#define STAT_CLEAR 0x20000000
++#define STAT_ECS_K 0x00800000 /* pipeline clean */
++
++#define NPE_STEVT 0x1B
++#define NPE_STARTPC 0x1C
++#define NPE_REGMAP 0x1E
++#define NPE_CINDEX 0x1F
++
++#define INSTR_WR_REG_SHORT 0x0000C000
++#define INSTR_WR_REG_BYTE 0x00004000
++#define INSTR_RD_FIFO 0x0F888220
++#define INSTR_RESET_MBOX 0x0FAC8210
++
++#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
++#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
++#define ECS_BG_CTXT_REG_2 0x02
++#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
++#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
++#define ECS_PRI_1_CTXT_REG_2 0x06
++#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
++#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
++#define ECS_PRI_2_CTXT_REG_2 0x0A
++#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
++#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
++#define ECS_DBG_CTXT_REG_2 0x0E
++#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
++
++#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
++#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
++#define ECS_REG_0_LDUR_BITS 8
++#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
++#define ECS_REG_1_CCTXT_BITS 16
++#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
++#define ECS_REG_1_SELCTXT_BITS 0
++#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
++#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
++#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
++
++/* NPE watchpoint_fifo register bit */
++#define WFIFO_VALID 0x80000000
++
++/* NPE messaging_status register bit definitions */
++#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
++#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
++#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
++#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
++#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
++#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
++#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
++#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
++
++/* NPE messaging_control register bit definitions */
++#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
++#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
++#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
++#define MSGCTL_IN_FIFO_WRITE 0x02000000
++
++/* NPE mailbox_status value for reset */
++#define RESET_MBOX_STAT 0x0000F0F0
++
++const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
++
++#define print_npe(pri, npe, fmt, ...) \
++ printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
++
++#if DEBUG_MSG
++#define debug_msg(npe, fmt, ...) \
++ print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
++#else
++#define debug_msg(npe, fmt, ...)
++#endif
++
++static struct {
++ u32 reg, val;
++}ecs_reset[] = {
++ { ECS_BG_CTXT_REG_0, 0xA0000000 },
++ { ECS_BG_CTXT_REG_1, 0x01000000 },
++ { ECS_BG_CTXT_REG_2, 0x00008000 },
++ { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
++ { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
++ { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
++ { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
++ { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
++ { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
++ { ECS_DBG_CTXT_REG_0, 0x20000000 },
++ { ECS_DBG_CTXT_REG_1, 0x00000000 },
++ { ECS_DBG_CTXT_REG_2, 0x001E0000 },
++ { ECS_INSTRUCT_REG, 0x1003C00F },
++};
++
++static struct npe npe_tab[NPE_COUNT] = {
++ {
++ .id = 0,
++ .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
++ .regs_phys = IXP4XX_NPEA_BASE_PHYS,
++ }, {
++ .id = 1,
++ .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
++ .regs_phys = IXP4XX_NPEB_BASE_PHYS,
++ }, {
++ .id = 2,
++ .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
++ .regs_phys = IXP4XX_NPEC_BASE_PHYS,
++ }
++};
++
++int npe_running(struct npe *npe)
++{
++ return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
++}
++
++static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
++{
++ __raw_writel(data, &npe->regs->exec_data);
++ __raw_writel(addr, &npe->regs->exec_addr);
++ __raw_writel(cmd, &npe->regs->exec_status_cmd);
++}
++
++static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
++{
++ __raw_writel(addr, &npe->regs->exec_addr);
++ __raw_writel(cmd, &npe->regs->exec_status_cmd);
++ /* Iintroduce extra read cycles after issuing read command to NPE
++ so that we read the register after the NPE has updated it.
++ This is to overcome race condition between XScale and NPE */
++ __raw_readl(&npe->regs->exec_data);
++ __raw_readl(&npe->regs->exec_data);
++ return __raw_readl(&npe->regs->exec_data);
++}
++
++static void npe_clear_active(struct npe *npe, u32 reg)
++{
++ u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
++ npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
++}
++
++static void npe_start(struct npe *npe)
++{
++ /* ensure only Background Context Stack Level is active */
++ npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
++ npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
++ npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
++
++ __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
++ __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
++}
++
++static void npe_stop(struct npe *npe)
++{
++ __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
++ __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
++}
++
++static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
++ u32 ldur)
++{
++ u32 wc;
++ int i;
++
++ /* set the Active bit, and the LDUR, in the debug level */
++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
++ ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
++
++ /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
++ the instruction, and set SELCTXT at ECS DEBUG Level to specify
++ which context store to access.
++ Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
++ */
++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
++ (ctx << ECS_REG_1_CCTXT_BITS) |
++ (ctx << ECS_REG_1_SELCTXT_BITS));
++
++ /* clear the pipeline */
++ __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
++
++ /* load NPE instruction into the instruction register */
++ npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
++
++ /* we need this value later to wait for completion of NPE execution
++ step */
++ wc = __raw_readl(&npe->regs->watch_count);
++
++ /* issue a Step One command via the Execution Control register */
++ __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
++
++ /* Watch Count register increments when NPE completes an instruction */
++ for (i = 0; i < MAX_RETRIES; i++) {
++ if (wc != __raw_readl(&npe->regs->watch_count))
++ return 0;
++ udelay(1);
++ }
++
++ print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
++ return -ETIMEDOUT;
++}
++
++static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
++ u8 val, u32 ctx)
++{
++ /* here we build the NPE assembler instruction: mov8 d0, #0 */
++ u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
++ addr << 9 | /* base Operand */
++ (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
++ (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
++ return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
++}
++
++static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
++ u16 val, u32 ctx)
++{
++ /* here we build the NPE assembler instruction: mov16 d0, #0 */
++ u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
++ addr << 9 | /* base Operand */
++ (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
++ (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
++ return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
++}
++
++static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
++ u32 val, u32 ctx)
++{
++ /* write in 16 bit steps first the high and then the low value */
++ if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
++ return -ETIMEDOUT;
++ return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
++}
++
++static int npe_reset(struct npe *npe)
++{
++ u32 val, ctl, exec_count, ctx_reg2;
++ int i;
++
++ ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
++ 0x3F3FFFFF;
++
++ /* disable parity interrupt */
++ __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
++
++ /* pre exec - debug instruction */
++ /* turn off the halt bit by clearing Execution Count register. */
++ exec_count = __raw_readl(&npe->regs->exec_count);
++ __raw_writel(0, &npe->regs->exec_count);
++ /* ensure that IF and IE are on (temporarily), so that we don't end up
++ stepping forever */
++ ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
++ ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
++
++ /* clear the FIFOs */
++ while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
++ ;
++ while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
++ /* read from the outFIFO until empty */
++ print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
++ __raw_readl(&npe->regs->in_out_fifo));
++
++ while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
++ /* step execution of the NPE intruction to read inFIFO using
++ the Debug Executing Context stack */
++ if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
++ return -ETIMEDOUT;
++
++ /* reset the mailbox reg from the XScale side */
++ __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
++ /* from NPE side */
++ if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
++ return -ETIMEDOUT;
++
++ /* Reset the physical registers in the NPE register file */
++ for (val = 0; val < NPE_PHYS_REG; val++) {
++ if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
++ return -ETIMEDOUT;
++ /* address is either 0 or 4 */
++ if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
++ return -ETIMEDOUT;
++ }
++
++ /* Reset the context store = each context's Context Store registers */
++
++ /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
++ for Background ECS, to set where NPE starts executing code */
++ val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
++ val &= ~ECS_REG_0_NEXTPC_MASK;
++ val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
++ npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
++
++ for (i = 0; i < 16; i++) {
++ if (i) { /* Context 0 has no STEVT nor STARTPC */
++ /* STEVT = off, 0x80 */
++ if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
++ return -ETIMEDOUT;
++ if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
++ return -ETIMEDOUT;
++ }
++ /* REGMAP = d0->p0, d8->p2, d16->p4 */
++ if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
++ return -ETIMEDOUT;
++ if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
++ return -ETIMEDOUT;
++ }
++
++ /* post exec */
++ /* clear active bit in debug level */
++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
++ /* clear the pipeline */
++ __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
++ /* restore previous values */
++ __raw_writel(exec_count, &npe->regs->exec_count);
++ npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
++
++ /* write reset values to Execution Context Stack registers */
++ for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
++ npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
++ ecs_reset[val].val);
++
++ /* clear the profile counter */
++ __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
++
++ __raw_writel(0, &npe->regs->exec_count);
++ __raw_writel(0, &npe->regs->action_points[0]);
++ __raw_writel(0, &npe->regs->action_points[1]);
++ __raw_writel(0, &npe->regs->action_points[2]);
++ __raw_writel(0, &npe->regs->action_points[3]);
++ __raw_writel(0, &npe->regs->watch_count);
++
++ val = ixp4xx_read_fuses();
++ /* reset the NPE */
++ ixp4xx_write_fuses(val & ~(IXP4XX_FUSE_RESET_NPEA << npe->id));
++ for (i = 0; i < MAX_RETRIES; i++) {
++ if (!(ixp4xx_read_fuses() &
++ (IXP4XX_FUSE_RESET_NPEA << npe->id)))
++ break; /* reset completed */
++ udelay(1);
++ }
++ if (i == MAX_RETRIES)
++ return -ETIMEDOUT;
++
++ /* deassert reset */
++ ixp4xx_write_fuses(val | (IXP4XX_FUSE_RESET_NPEA << npe->id));
++ for (i = 0; i < MAX_RETRIES; i++) {
++ if (ixp4xx_read_fuses() & (IXP4XX_FUSE_RESET_NPEA << npe->id))
++ break; /* NPE is back alive */
++ udelay(1);
++ }
++ if (i == MAX_RETRIES)
++ return -ETIMEDOUT;
++
++ npe_stop(npe);
++
++ /* restore NPE configuration bus Control Register - parity settings */
++ __raw_writel(ctl, &npe->regs->messaging_control);
++ return 0;
++}
++
++
++int npe_send_message(struct npe *npe, const void *msg, const char *what)
++{
++ const u32 *send = msg;
++ int cycles = 0;
++
++ debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
++ what, send[0], send[1]);
++
++ if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
++ debug_msg(npe, "NPE input FIFO not empty\n");
++ return -EIO;
++ }
++
++ __raw_writel(send[0], &npe->regs->in_out_fifo);
++
++ if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
++ debug_msg(npe, "NPE input FIFO full\n");
++ return -EIO;
++ }
++
++ __raw_writel(send[1], &npe->regs->in_out_fifo);
++
++ while ((cycles < MAX_RETRIES) &&
++ (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
++ udelay(1);
++ cycles++;
++ }
++
++ if (cycles == MAX_RETRIES) {
++ debug_msg(npe, "Timeout sending message\n");
++ return -ETIMEDOUT;
++ }
++
++ debug_msg(npe, "Sending a message took %i cycles\n", cycles);
++ return 0;
++}
++
++int npe_recv_message(struct npe *npe, void *msg, const char *what)
++{
++ u32 *recv = msg;
++ int cycles = 0, cnt = 0;
++
++ debug_msg(npe, "Trying to receive message %s\n", what);
++
++ while (cycles < MAX_RETRIES) {
++ if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
++ recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
++ if (cnt == 2)
++ break;
++ } else {
++ udelay(1);
++ cycles++;
++ }
++ }
++
++ switch(cnt) {
++ case 1:
++ debug_msg(npe, "Received [%08X]\n", recv[0]);
++ break;
++ case 2:
++ debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
++ break;
++ }
++
++ if (cycles == MAX_RETRIES) {
++ debug_msg(npe, "Timeout waiting for message\n");
++ return -ETIMEDOUT;
++ }
++
++ debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
++ return 0;
++}
++
++int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
++{
++ int result;
++ u32 *send = msg, recv[2];
++
++ if ((result = npe_send_message(npe, msg, what)) != 0)
++ return result;
++ if ((result = npe_recv_message(npe, recv, what)) != 0)
++ return result;
++
++ if ((recv[0] != send[0]) || (recv[1] != send[1])) {
++ debug_msg(npe, "Message %s: unexpected message received\n",
++ what);
++ return -EIO;
++ }
++ return 0;
++}
++
++
++int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
++{
++ const struct firmware *fw_entry;
++
++ struct dl_block {
++ u32 type;
++ u32 offset;
++ } *blk;
++
++ struct dl_image {
++ u32 magic;
++ u32 id;
++ u32 size;
++ union {
++ u32 data[0];
++ struct dl_block blocks[0];
++ };
++ } *image;
++
++ struct dl_codeblock {
++ u32 npe_addr;
++ u32 size;
++ u32 data[0];
++ } *cb;
++
++ int i, j, err, data_size, instr_size, blocks, table_end;
++ u32 cmd;
++
++ if ((err = request_firmware(&fw_entry, name, dev)) != 0)
++ return err;
++
++ err = -EINVAL;
++ if (fw_entry->size < sizeof(struct dl_image)) {
++ print_npe(KERN_ERR, npe, "incomplete firmware file\n");
++ goto err;
++ }
++ image = (struct dl_image*)fw_entry->data;
++
++#if DEBUG_FW
++ print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
++ image->magic, image->id, image->size, image->size * 4);
++#endif
++
++ if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
++ image->id = swab32(image->id);
++ image->size = swab32(image->size);
++ } else if (image->magic != FW_MAGIC) {
++ print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
++ image->magic);
++ goto err;
++ }
++ if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
++ print_npe(KERN_ERR, npe,
++ "inconsistent size of firmware file\n");
++ goto err;
++ }
++ if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
++ print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
++ goto err;
++ }
++ if (image->magic == swab32(FW_MAGIC))
++ for (i = 0; i < image->size; i++)
++ image->data[i] = swab32(image->data[i]);
++
++ if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
++ print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
++ "IXP42x\n");
++ goto err;
++ }
++
++ if (npe_running(npe)) {
++ print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
++ "already running\n");
++ err = -EBUSY;
++ goto err;
++ }
++#if 0
++ npe_stop(npe);
++ npe_reset(npe);
++#endif
++
++ print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
++ "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
++ (image->id >> 8) & 0xFF, image->id & 0xFF);
++
++ if (!cpu_is_ixp46x()) {
++ if (!npe->id)
++ instr_size = NPE_A_42X_INSTR_SIZE;
++ else
++ instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
++ data_size = NPE_42X_DATA_SIZE;
++ } else {
++ instr_size = NPE_46X_INSTR_SIZE;
++ data_size = NPE_46X_DATA_SIZE;
++ }
++
++ for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
++ blocks++)
++ if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
++ break;
++ if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
++ print_npe(KERN_INFO, npe, "firmware EOF block marker not "
++ "found\n");
++ goto err;
++ }
++
++#if DEBUG_FW
++ print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
++#endif
++
++ table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
++ for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
++ if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
++ || blk->offset < table_end) {
++ print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
++ "firmware block #%i\n", blk->offset, i);
++ goto err;
++ }
++
++ cb = (struct dl_codeblock*)&image->data[blk->offset];
++ if (blk->type == FW_BLOCK_TYPE_INSTR) {
++ if (cb->npe_addr + cb->size > instr_size)
++ goto too_big;
++ cmd = CMD_WR_INS_MEM;
++ } else if (blk->type == FW_BLOCK_TYPE_DATA) {
++ if (cb->npe_addr + cb->size > data_size)
++ goto too_big;
++ cmd = CMD_WR_DATA_MEM;
++ } else {
++ print_npe(KERN_INFO, npe, "invalid firmware block #%i "
++ "type 0x%X\n", i, blk->type);
++ goto err;
++ }
++ if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
++ print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
++ "fit in firmware image: type %c, start 0x%X,"
++ " length 0x%X\n", i,
++ blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
++ cb->npe_addr, cb->size);
++ goto err;
++ }
++
++ for (j = 0; j < cb->size; j++)
++ npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
++ }
++
++ npe_start(npe);
++ if (!npe_running(npe))
++ print_npe(KERN_ERR, npe, "unable to start\n");
++ release_firmware(fw_entry);
++ return 0;
++
++too_big:
++ print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
++ "memory: type %c, start 0x%X, length 0x%X\n", i,
++ blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
++ cb->npe_addr, cb->size);
++err:
++ release_firmware(fw_entry);
++ return err;
++}
++
++
++struct npe *npe_request(int id)
++{
++ if (id < NPE_COUNT)
++ if (npe_tab[id].valid)
++ if (try_module_get(THIS_MODULE))
++ return &npe_tab[id];
++ return NULL;
++}
++
++void npe_release(struct npe *npe)
++{
++ module_put(THIS_MODULE);
++}
++
++
++static int __init npe_init_module(void)
++{
++
++ int i, found = 0;
++
++ for (i = 0; i < NPE_COUNT; i++) {
++ struct npe *npe = &npe_tab[i];
++ if (!(ixp4xx_read_fuses() & (IXP4XX_FUSE_RESET_NPEA << i)))
++ continue; /* NPE already disabled or not present */
++ if (!(npe->mem_res = request_mem_region(npe->regs_phys,
++ REGS_SIZE,
++ npe_name(npe)))) {
++ print_npe(KERN_ERR, npe,
++ "failed to request memory region\n");
++ continue;
++ }
++
++ if (npe_reset(npe))
++ continue;
++ npe->valid = 1;
++ found++;
++ }
++
++ if (!found)
++ return -ENOSYS;
++ return 0;
++}
++
++static void __exit npe_cleanup_module(void)
++{
++ int i;
++
++ for (i = 0; i < NPE_COUNT; i++)
++ if (npe_tab[i].mem_res) {
++ npe_reset(&npe_tab[i]);
++ release_resource(npe_tab[i].mem_res);
++ }
++}
++
++module_init(npe_init_module);
++module_exit(npe_cleanup_module);
++
++MODULE_AUTHOR("Krzysztof Halasa");
++MODULE_LICENSE("GPL v2");
++
++EXPORT_SYMBOL(npe_names);
++EXPORT_SYMBOL(npe_running);
++EXPORT_SYMBOL(npe_request);
++EXPORT_SYMBOL(npe_release);
++EXPORT_SYMBOL(npe_load_firmware);
++EXPORT_SYMBOL(npe_send_message);
++EXPORT_SYMBOL(npe_recv_message);
++EXPORT_SYMBOL(npe_send_recv_message);
+diff -Nur -x .git -x .gitignore linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c 1970-01-01 01:00:00.000000000 +0100
++++ ixp4xx-nep.git/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c 2007-10-22 19:19:41.000000000 +0200
+@@ -0,0 +1,274 @@
++/*
++ * Intel IXP4xx Queue Manager driver for Linux
++ *
++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License
++ * as published by the Free Software Foundation.
++ */
++
++#include <linux/ioport.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <asm/arch/qmgr.h>
++
++#define DEBUG 0
++
++struct qmgr_regs __iomem *qmgr_regs;
++static struct resource *mem_res;
++static spinlock_t qmgr_lock;
++static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
++static void (*irq_handlers[HALF_QUEUES])(void *pdev);
++static void *irq_pdevs[HALF_QUEUES];
++
++void qmgr_set_irq(unsigned int queue, int src,
++ void (*handler)(void *pdev), void *pdev)
++{
++ u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
++ int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
++ unsigned long flags;
++
++ src &= 7;
++ spin_lock_irqsave(&qmgr_lock, flags);
++ __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
++ irq_handlers[queue] = handler;
++ irq_pdevs[queue] = pdev;
++ spin_unlock_irqrestore(&qmgr_lock, flags);
++}
++
++
++static irqreturn_t qmgr_irq1(int irq, void *pdev)
++{
++ int i;
++ u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
++ __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
++
++ for (i = 0; i < HALF_QUEUES; i++)
++ if (val & (1 << i))
++ irq_handlers[i](irq_pdevs[i]);
++
++ return val ? IRQ_HANDLED : 0;
++}
++
++
++void qmgr_enable_irq(unsigned int queue)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&qmgr_lock, flags);
++ __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
++ &qmgr_regs->irqen[0]);
++ spin_unlock_irqrestore(&qmgr_lock, flags);
++}
++
++void qmgr_disable_irq(unsigned int queue)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&qmgr_lock, flags);
++ __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
++ &qmgr_regs->irqen[0]);
++ spin_unlock_irqrestore(&qmgr_lock, flags);
++}
++
++static inline void shift_mask(u32 *mask)
++{
++ mask[3] = mask[3] << 1 | mask[2] >> 31;
++ mask[2] = mask[2] << 1 | mask[1] >> 31;
++ mask[1] = mask[1] << 1 | mask[0] >> 31;
++ mask[0] <<= 1;
++}
++
++int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
++ unsigned int nearly_empty_watermark,
++ unsigned int nearly_full_watermark)
++{
++ u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
++ int err;
++
++ if (queue >= HALF_QUEUES)
++ return -ERANGE;
++
++ if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
++ return -EINVAL;
++
++ switch (len) {
++ case 16:
++ cfg = 0 << 24;
++ mask[0] = 0x1;
++ break;
++ case 32:
++ cfg = 1 << 24;
++ mask[0] = 0x3;
++ break;
++ case 64:
++ cfg = 2 << 24;
++ mask[0] = 0xF;
++ break;
++ case 128:
++ cfg = 3 << 24;
++ mask[0] = 0xFF;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ cfg |= nearly_empty_watermark << 26;
++ cfg |= nearly_full_watermark << 29;
++ len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
++ mask[1] = mask[2] = mask[3] = 0;
++
++ if (!try_module_get(THIS_MODULE))
++ return -ENODEV;
++
++ spin_lock_irq(&qmgr_lock);
++ if (__raw_readl(&qmgr_regs->sram[queue])) {
++ err = -EBUSY;
++ goto err;
++ }
++
++ while (1) {
++ if (!(used_sram_bitmap[0] & mask[0]) &&
++ !(used_sram_bitmap[1] & mask[1]) &&
++ !(used_sram_bitmap[2] & mask[2]) &&
++ !(used_sram_bitmap[3] & mask[3]))
++ break; /* found free space */
++
++ addr++;
++ shift_mask(mask);
++ if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
++ printk(KERN_ERR "qmgr: no free SRAM space for"
++ " queue %i\n", queue);
++ err = -ENOMEM;
++ goto err;
++ }
++ }
++
++ used_sram_bitmap[0] |= mask[0];
++ used_sram_bitmap[1] |= mask[1];
++ used_sram_bitmap[2] |= mask[2];
++ used_sram_bitmap[3] |= mask[3];
++ __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
++ spin_unlock_irq(&qmgr_lock);
++
++#if DEBUG
++ printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n",
++ queue, addr);
++#endif
++ return 0;
++
++err:
++ spin_unlock_irq(&qmgr_lock);
++ module_put(THIS_MODULE);
++ return err;
++}
++
++void qmgr_release_queue(unsigned int queue)
++{
++ u32 cfg, addr, mask[4];
++
++ BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
++
++ spin_lock_irq(&qmgr_lock);
++ cfg = __raw_readl(&qmgr_regs->sram[queue]);
++ addr = (cfg >> 14) & 0xFF;
++
++ BUG_ON(!addr); /* not requested */
++
++ switch ((cfg >> 24) & 3) {
++ case 0: mask[0] = 0x1; break;
++ case 1: mask[0] = 0x3; break;
++ case 2: mask[0] = 0xF; break;
++ case 3: mask[0] = 0xFF; break;
++ }
++
++ while (addr--)
++ shift_mask(mask);
++
++ __raw_writel(0, &qmgr_regs->sram[queue]);
++
++ used_sram_bitmap[0] &= ~mask[0];
++ used_sram_bitmap[1] &= ~mask[1];
++ used_sram_bitmap[2] &= ~mask[2];
++ used_sram_bitmap[3] &= ~mask[3];
++ irq_handlers[queue] = NULL; /* catch IRQ bugs */
++ spin_unlock_irq(&qmgr_lock);
++
++ module_put(THIS_MODULE);
++#if DEBUG
++ printk(KERN_DEBUG "qmgr: released queue %i\n", queue);
++#endif
++}
++
++static int qmgr_init(void)
++{
++ int i, err;
++ mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
++ IXP4XX_QMGR_REGION_SIZE,
++ "IXP4xx Queue Manager");
++ if (mem_res == NULL)
++ return -EBUSY;
++
++ qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
++ if (qmgr_regs == NULL) {
++ err = -ENOMEM;
++ goto error_map;
++ }
++
++ /* reset qmgr registers */
++ for (i = 0; i < 4; i++) {
++ __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
++ __raw_writel(0, &qmgr_regs->irqsrc[i]);
++ }
++ for (i = 0; i < 2; i++) {
++ __raw_writel(0, &qmgr_regs->stat2[i]);
++ __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
++ __raw_writel(0, &qmgr_regs->irqen[i]);
++ }
++
++ for (i = 0; i < QUEUES; i++)
++ __raw_writel(0, &qmgr_regs->sram[i]);
++
++ err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
++ "IXP4xx Queue Manager", NULL);
++ if (err) {
++ printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
++ IRQ_IXP4XX_QM1);
++ goto error_irq;
++ }
++
++ used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
++ spin_lock_init(&qmgr_lock);
++
++ printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
++ return 0;
++
++error_irq:
++ iounmap(qmgr_regs);
++error_map:
++ release_resource(mem_res);
++ return err;
++}
++
++static void qmgr_remove(void)
++{
++ free_irq(IRQ_IXP4XX_QM1, NULL);
++ synchronize_irq(IRQ_IXP4XX_QM1);
++ iounmap(qmgr_regs);
++ release_resource(mem_res);
++}
++
++module_init(qmgr_init);
++module_exit(qmgr_remove);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Krzysztof Halasa");
++
++EXPORT_SYMBOL(qmgr_regs);
++EXPORT_SYMBOL(qmgr_set_irq);
++EXPORT_SYMBOL(qmgr_enable_irq);
++EXPORT_SYMBOL(qmgr_disable_irq);
++EXPORT_SYMBOL(qmgr_request_queue);
++EXPORT_SYMBOL(qmgr_release_queue);
+diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/arm/Kconfig ixp4xx-nep.git/drivers/net/arm/Kconfig
+--- linux-2.6.23/drivers/net/arm/Kconfig 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/drivers/net/arm/Kconfig 2007-10-22 19:20:02.000000000 +0200
+@@ -47,3 +47,13 @@
+ help
+ This is a driver for the ethernet hardware included in EP93xx CPUs.
+ Say Y if you are building a kernel for EP93xx based devices.
++
++config IXP4XX_ETH
++ tristate "IXP4xx Ethernet support"
++ depends on NET_ETHERNET && ARM && ARCH_IXP4XX
++ select IXP4XX_NPE
++ select IXP4XX_QMGR
++ select MII
++ help
++ Say Y here if you want to use built-in Ethernet ports
++ on IXP4xx processor.
+diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/arm/Makefile ixp4xx-nep.git/drivers/net/arm/Makefile
+--- linux-2.6.23/drivers/net/arm/Makefile 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/drivers/net/arm/Makefile 2007-10-22 19:20:02.000000000 +0200
+@@ -9,3 +9,4 @@
+ obj-$(CONFIG_ARM_ETHER1) += ether1.o
+ obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
+ obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
++obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o
+diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/arm/ixp4xx_eth.c ixp4xx-nep.git/drivers/net/arm/ixp4xx_eth.c
+--- linux-2.6.23/drivers/net/arm/ixp4xx_eth.c 1970-01-01 01:00:00.000000000 +0100
++++ ixp4xx-nep.git/drivers/net/arm/ixp4xx_eth.c 2007-10-22 19:20:02.000000000 +0200
+@@ -0,0 +1,1258 @@
++/*
++ * Intel IXP4xx Ethernet driver for Linux
++ *
++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License
++ * as published by the Free Software Foundation.
++ *
++ * Ethernet port config (0x00 is not present on IXP42X):
++ *
++ * logical port 0x00 0x10 0x20
++ * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
++ * physical PortId 2 0 1
++ * TX queue 23 24 25
++ * RX-free queue 26 27 28
++ * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
++ *
++ *
++ * Queue entries:
++ * bits 0 -> 1 - NPE ID (RX and TX-done)
++ * bits 0 -> 2 - priority (TX, per 802.1D)
++ * bits 3 -> 4 - port ID (user-set?)
++ * bits 5 -> 31 - physical descriptor address
++ */
++
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/kernel.h>
++#include <linux/mii.h>
++#include <linux/platform_device.h>
++#include <asm/io.h>
++#include <asm/arch/npe.h>
++#include <asm/arch/qmgr.h>
++
++#define DEBUG_QUEUES 0
++#define DEBUG_DESC 0
++#define DEBUG_RX 0
++#define DEBUG_TX 0
++#define DEBUG_PKT_BYTES 0
++#define DEBUG_MDIO 0
++#define DEBUG_CLOSE 0
++
++#define DRV_NAME "ixp4xx_eth"
++
++#define MAX_NPES 3
++
++#define RX_DESCS 64 /* also length of all RX queues */
++#define TX_DESCS 16 /* also length of all TX queues */
++#define TXDONE_QUEUE_LEN 64 /* dwords */
++
++#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
++#define REGS_SIZE 0x1000
++#define MAX_MRU 1536 /* 0x600 */
++
++#define MDIO_INTERVAL (3 * HZ)
++#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
++#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
++#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
++
++#define NPE_ID(port_id) ((port_id) >> 4)
++#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
++#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
++#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
++#define TXDONE_QUEUE 31
++
++/* TX Control Registers */
++#define TX_CNTRL0_TX_EN 0x01
++#define TX_CNTRL0_HALFDUPLEX 0x02
++#define TX_CNTRL0_RETRY 0x04
++#define TX_CNTRL0_PAD_EN 0x08
++#define TX_CNTRL0_APPEND_FCS 0x10
++#define TX_CNTRL0_2DEFER 0x20
++#define TX_CNTRL0_RMII 0x40 /* reduced MII */
++#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
++
++/* RX Control Registers */
++#define RX_CNTRL0_RX_EN 0x01
++#define RX_CNTRL0_PADSTRIP_EN 0x02
++#define RX_CNTRL0_SEND_FCS 0x04
++#define RX_CNTRL0_PAUSE_EN 0x08
++#define RX_CNTRL0_LOOP_EN 0x10
++#define RX_CNTRL0_ADDR_FLTR_EN 0x20
++#define RX_CNTRL0_RX_RUNT_EN 0x40
++#define RX_CNTRL0_BCAST_DIS 0x80
++#define RX_CNTRL1_DEFER_EN 0x01
++
++/* Core Control Register */
++#define CORE_RESET 0x01
++#define CORE_RX_FIFO_FLUSH 0x02
++#define CORE_TX_FIFO_FLUSH 0x04
++#define CORE_SEND_JAM 0x08
++#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
++
++#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
++ TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
++ TX_CNTRL0_2DEFER)
++#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
++#define DEFAULT_CORE_CNTRL CORE_MDC_EN
++
++
++/* NPE message codes */
++#define NPE_GETSTATUS 0x00
++#define NPE_EDB_SETPORTADDRESS 0x01
++#define NPE_EDB_GETMACADDRESSDATABASE 0x02
++#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
++#define NPE_GETSTATS 0x04
++#define NPE_RESETSTATS 0x05
++#define NPE_SETMAXFRAMELENGTHS 0x06
++#define NPE_VLAN_SETRXTAGMODE 0x07
++#define NPE_VLAN_SETDEFAULTRXVID 0x08
++#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
++#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
++#define NPE_VLAN_SETRXQOSENTRY 0x0B
++#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
++#define NPE_STP_SETBLOCKINGSTATE 0x0D
++#define NPE_FW_SETFIREWALLMODE 0x0E
++#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
++#define NPE_PC_SETAPMACTABLE 0x11
++#define NPE_SETLOOPBACK_MODE 0x12
++#define NPE_PC_SETBSSIDTABLE 0x13
++#define NPE_ADDRESS_FILTER_CONFIG 0x14
++#define NPE_APPENDFCSCONFIG 0x15
++#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
++#define NPE_MAC_RECOVERY_START 0x17
++
++
++#ifdef __ARMEB__
++typedef struct sk_buff buffer_t;
++#define free_buffer dev_kfree_skb
++#define free_buffer_irq dev_kfree_skb_irq
++#else
++typedef void buffer_t;
++#define free_buffer kfree
++#define free_buffer_irq kfree
++#endif
++
++struct eth_regs {
++ u32 tx_control[2], __res1[2]; /* 000 */
++ u32 rx_control[2], __res2[2]; /* 010 */
++ u32 random_seed, __res3[3]; /* 020 */
++ u32 partial_empty_threshold, __res4; /* 030 */
++ u32 partial_full_threshold, __res5; /* 038 */
++ u32 tx_start_bytes, __res6[3]; /* 040 */
++ u32 tx_deferral, rx_deferral,__res7[2]; /* 050 */
++ u32 tx_2part_deferral[2], __res8[2]; /* 060 */
++ u32 slot_time, __res9[3]; /* 070 */
++ u32 mdio_command[4]; /* 080 */
++ u32 mdio_status[4]; /* 090 */
++ u32 mcast_mask[6], __res10[2]; /* 0A0 */
++ u32 mcast_addr[6], __res11[2]; /* 0C0 */
++ u32 int_clock_threshold, __res12[3]; /* 0E0 */
++ u32 hw_addr[6], __res13[61]; /* 0F0 */
++ u32 core_control; /* 1FC */
++};
++
++struct port {
++ struct resource *mem_res;
++ struct eth_regs __iomem *regs;
++ struct npe *npe;
++ struct net_device *netdev;
++ struct net_device_stats stat;
++ struct mii_if_info mii;
++ struct delayed_work mdio_thread;
++ struct eth_plat_info *plat;
++ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
++ struct desc *desc_tab; /* coherent */
++ u32 desc_tab_phys;
++ int id; /* logical port ID */
++ u16 mii_bmcr;
++};
++
++/* NPE message structure */
++struct msg {
++#ifdef __ARMEB__
++ u8 cmd, eth_id, byte2, byte3;
++ u8 byte4, byte5, byte6, byte7;
++#else
++ u8 byte3, byte2, eth_id, cmd;
++ u8 byte7, byte6, byte5, byte4;
++#endif
++};
++
++/* Ethernet packet descriptor */
++struct desc {
++ u32 next; /* pointer to next buffer, unused */
++
++#ifdef __ARMEB__
++ u16 buf_len; /* buffer length */
++ u16 pkt_len; /* packet length */
++ u32 data; /* pointer to data buffer in RAM */
++ u8 dest_id;
++ u8 src_id;
++ u16 flags;
++ u8 qos;
++ u8 padlen;
++ u16 vlan_tci;
++#else
++ u16 pkt_len; /* packet length */
++ u16 buf_len; /* buffer length */
++ u32 data; /* pointer to data buffer in RAM */
++ u16 flags;
++ u8 src_id;
++ u8 dest_id;
++ u16 vlan_tci;
++ u8 padlen;
++ u8 qos;
++#endif
++
++#ifdef __ARMEB__
++ u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
++ u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
++ u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
++#else
++ u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
++ u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
++ u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
++#endif
++};
++
++
++#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
++ (n) * sizeof(struct desc))
++#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
++
++#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
++ ((n) + RX_DESCS) * sizeof(struct desc))
++#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
++
++#ifndef __ARMEB__
++static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
++{
++ int i;
++ for (i = 0; i < cnt; i++)
++ dest[i] = swab32(src[i]);
++}
++#endif
++
++static spinlock_t mdio_lock;
++static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
++static int ports_open;
++static struct port *npe_port_tab[MAX_NPES];
++static struct dma_pool *dma_pool;
++
++
++static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
++ int write, u16 cmd)
++{
++ int cycles = 0;
++
++ if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
++ printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
++ return 0;
++ }
++
++ if (write) {
++ __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
++ __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
++ }
++ __raw_writel(((phy_id << 5) | location) & 0xFF,
++ &mdio_regs->mdio_command[2]);
++ __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
++ &mdio_regs->mdio_command[3]);
++
++ while ((cycles < MAX_MDIO_RETRIES) &&
++ (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
++ udelay(1);
++ cycles++;
++ }
++
++ if (cycles == MAX_MDIO_RETRIES) {
++ printk(KERN_ERR "%s: MII write failed\n", dev->name);
++ return 0;
++ }
++
++#if DEBUG_MDIO
++ printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
++ cycles);
++#endif
++
++ if (write)
++ return 0;
++
++ if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
++ printk(KERN_ERR "%s: MII read failed\n", dev->name);
++ return 0;
++ }
++
++ return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
++ (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
++}
++
++static int mdio_read(struct net_device *dev, int phy_id, int location)
++{
++ unsigned long flags;
++ u16 val;
++
++ spin_lock_irqsave(&mdio_lock, flags);
++ val = mdio_cmd(dev, phy_id, location, 0, 0);
++ spin_unlock_irqrestore(&mdio_lock, flags);
++ return val;
++}
++
++static void mdio_write(struct net_device *dev, int phy_id, int location,
++ int val)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&mdio_lock, flags);
++ mdio_cmd(dev, phy_id, location, 1, val);
++ spin_unlock_irqrestore(&mdio_lock, flags);
++}
++
++static void phy_reset(struct net_device *dev, int phy_id)
++{
++ struct port *port = netdev_priv(dev);
++ int cycles = 0;
++
++ mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
++
++ while (cycles < MAX_MII_RESET_RETRIES) {
++ if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
++#if DEBUG_MDIO
++ printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
++ dev->name, cycles);
++#endif
++ return;
++ }
++ udelay(1);
++ cycles++;
++ }
++
++ printk(KERN_ERR "%s: MII reset failed\n", dev->name);
++}
++
++static void eth_set_duplex(struct port *port)
++{
++ if (port->mii.full_duplex)
++ __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
++ &port->regs->tx_control[0]);
++ else
++ __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
++ &port->regs->tx_control[0]);
++}
++
++
++static void phy_check_media(struct port *port, int init)
++{
++ if (mii_check_media(&port->mii, 1, init))
++ eth_set_duplex(port);
++ if (port->mii.force_media) { /* mii_check_media() doesn't work */
++ struct net_device *dev = port->netdev;
++ int cur_link = mii_link_ok(&port->mii);
++ int prev_link = netif_carrier_ok(dev);
++
++ if (!prev_link && cur_link) {
++ printk(KERN_INFO "%s: link up\n", dev->name);
++ netif_carrier_on(dev);
++ } else if (prev_link && !cur_link) {
++ printk(KERN_INFO "%s: link down\n", dev->name);
++ netif_carrier_off(dev);
++ }
++ }
++}
++
++
++static void mdio_thread(struct work_struct *work)
++{
++ struct port *port = container_of(work, struct port, mdio_thread.work);
++
++ phy_check_media(port, 0);
++ schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
++}
++
++
++static inline void debug_pkt(struct net_device *dev, const char *func,
++ u8 *data, int len)
++{
++#if DEBUG_PKT_BYTES
++ int i;
++
++ printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
++ for (i = 0; i < len; i++) {
++ if (i >= DEBUG_PKT_BYTES)
++ break;
++ printk("%s%02X",
++ ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
++ data[i]);
++ }
++ printk("\n");
++#endif
++}
++
++
++static inline void debug_desc(u32 phys, struct desc *desc)
++{
++#if DEBUG_DESC
++ printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
++ " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
++ phys, desc->next, desc->buf_len, desc->pkt_len,
++ desc->data, desc->dest_id, desc->src_id, desc->flags,
++ desc->qos, desc->padlen, desc->vlan_tci,
++ desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
++ desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
++ desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
++ desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
++#endif
++}
++
++static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
++{
++#if DEBUG_QUEUES
++ static struct {
++ int queue;
++ char *name;
++ } names[] = {
++ { TX_QUEUE(0x10), "TX#0 " },
++ { TX_QUEUE(0x20), "TX#1 " },
++ { TX_QUEUE(0x00), "TX#2 " },
++ { RXFREE_QUEUE(0x10), "RX-free#0 " },
++ { RXFREE_QUEUE(0x20), "RX-free#1 " },
++ { RXFREE_QUEUE(0x00), "RX-free#2 " },
++ { TXDONE_QUEUE, "TX-done " },
++ };
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(names); i++)
++ if (names[i].queue == queue)
++ break;
++
++ printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
++ i < ARRAY_SIZE(names) ? names[i].name : "",
++ is_get ? "->" : "<-", phys);
++#endif
++}
++
++static inline u32 queue_get_entry(unsigned int queue)
++{
++ u32 phys = qmgr_get_entry(queue);
++ debug_queue(queue, 1, phys);
++ return phys;
++}
++
++static inline int queue_get_desc(unsigned int queue, struct port *port,
++ int is_tx)
++{
++ u32 phys, tab_phys, n_desc;
++ struct desc *tab;
++
++ if (!(phys = queue_get_entry(queue)))
++ return -1;
++
++ phys &= ~0x1F; /* mask out non-address bits */
++ tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
++ tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
++ n_desc = (phys - tab_phys) / sizeof(struct desc);
++ BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
++ debug_desc(phys, &tab[n_desc]);
++ BUG_ON(tab[n_desc].next);
++ return n_desc;
++}
++
++static inline void queue_put_desc(unsigned int queue, u32 phys,
++ struct desc *desc)
++{
++ debug_queue(queue, 0, phys);
++ debug_desc(phys, desc);
++ BUG_ON(phys & 0x1F);
++ qmgr_put_entry(queue, phys);
++ BUG_ON(qmgr_stat_overflow(queue));
++}
++
++
++static inline void dma_unmap_tx(struct port *port, struct desc *desc)
++{
++#ifdef __ARMEB__
++ dma_unmap_single(&port->netdev->dev, desc->data,
++ desc->buf_len, DMA_TO_DEVICE);
++#else
++ dma_unmap_single(&port->netdev->dev, desc->data & ~3,
++ ALIGN((desc->data & 3) + desc->buf_len, 4),
++ DMA_TO_DEVICE);
++#endif
++}
++
++
++static void eth_rx_irq(void *pdev)
++{
++ struct net_device *dev = pdev;
++ struct port *port = netdev_priv(dev);
++
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
++#endif
++ qmgr_disable_irq(port->plat->rxq);
++ netif_rx_schedule(dev);
++}
++
++static int eth_poll(struct net_device *dev, int *budget)
++{
++ struct port *port = netdev_priv(dev);
++ unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
++ int quota = dev->quota, received = 0;
++
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
++#endif
++
++ while (quota) {
++ struct sk_buff *skb;
++ struct desc *desc;
++ int n;
++#ifdef __ARMEB__
++ struct sk_buff *temp;
++ u32 phys;
++#endif
++
++ if ((n = queue_get_desc(rxq, port, 0)) < 0) {
++ dev->quota -= received; /* No packet received */
++ *budget -= received;
++ received = 0;
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
++ dev->name);
++#endif
++ netif_rx_complete(dev);
++ qmgr_enable_irq(rxq);
++ if (!qmgr_stat_empty(rxq) &&
++ netif_rx_reschedule(dev, 0)) {
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: eth_poll"
++ " netif_rx_reschedule successed\n",
++ dev->name);
++#endif
++ qmgr_disable_irq(rxq);
++ continue;
++ }
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: eth_poll all done\n",
++ dev->name);
++#endif
++ return 0; /* all work done */
++ }
++
++ desc = rx_desc_ptr(port, n);
++
++#ifdef __ARMEB__
++ if ((skb = netdev_alloc_skb(dev, MAX_MRU)) != NULL) {
++ phys = dma_map_single(&dev->dev, skb->data,
++ MAX_MRU, DMA_FROM_DEVICE);
++ if (dma_mapping_error(phys)) {
++ dev_kfree_skb(skb);
++ skb = NULL;
++ }
++ }
++#else
++ skb = netdev_alloc_skb(dev, desc->pkt_len);
++#endif
++
++ if (!skb) {
++ port->stat.rx_dropped++;
++ /* put the desc back on RX-ready queue */
++ desc->buf_len = MAX_MRU;
++ desc->pkt_len = 0;
++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
++ continue;
++ }
++
++ /* process received frame */
++#ifdef __ARMEB__
++ temp = skb;
++ skb = port->rx_buff_tab[n];
++ dma_unmap_single(&dev->dev, desc->data,
++ MAX_MRU, DMA_FROM_DEVICE);
++#else
++ dma_sync_single(&dev->dev, desc->data,
++ MAX_MRU, DMA_FROM_DEVICE);
++ memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
++ ALIGN(desc->pkt_len, 4) / 4);
++#endif
++ skb_put(skb, desc->pkt_len);
++
++ debug_pkt(dev, "eth_poll", skb->data, skb->len);
++
++ skb->protocol = eth_type_trans(skb, dev);
++ dev->last_rx = jiffies;
++ port->stat.rx_packets++;
++ port->stat.rx_bytes += skb->len;
++ netif_receive_skb(skb);
++
++ /* put the new buffer on RX-free queue */
++#ifdef __ARMEB__
++ port->rx_buff_tab[n] = temp;
++ desc->data = phys;
++#endif
++ desc->buf_len = MAX_MRU;
++ desc->pkt_len = 0;
++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
++ quota--;
++ received++;
++ }
++ dev->quota -= received;
++ *budget -= received;
++#if DEBUG_RX
++ printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
++#endif
++ return 1; /* not all work done */
++}
++
++
++static void eth_txdone_irq(void *unused)
++{
++ u32 phys;
++
++#if DEBUG_TX
++ printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
++#endif
++ while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
++ u32 npe_id, n_desc;
++ struct port *port;
++ struct desc *desc;
++ int start;
++
++ npe_id = phys & 3;
++ BUG_ON(npe_id >= MAX_NPES);
++ port = npe_port_tab[npe_id];
++ BUG_ON(!port);
++ phys &= ~0x1F; /* mask out non-address bits */
++ n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
++ BUG_ON(n_desc >= TX_DESCS);
++ desc = tx_desc_ptr(port, n_desc);
++ debug_desc(phys, desc);
++
++ if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
++ port->stat.tx_packets++;
++ port->stat.tx_bytes += desc->pkt_len;
++
++ dma_unmap_tx(port, desc);
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
++ port->netdev->name, port->tx_buff_tab[n_desc]);
++#endif
++ free_buffer_irq(port->tx_buff_tab[n_desc]);
++ port->tx_buff_tab[n_desc] = NULL;
++ }
++
++ start = qmgr_stat_empty(port->plat->txreadyq);
++ queue_put_desc(port->plat->txreadyq, phys, desc);
++ if (start) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
++ port->netdev->name);
++#endif
++ netif_wake_queue(port->netdev);
++ }
++ }
++}
++
++static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ struct port *port = netdev_priv(dev);
++ unsigned int txreadyq = port->plat->txreadyq;
++ int len, offset, bytes, n;
++ void *mem;
++ u32 phys;
++ struct desc *desc;
++
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
++#endif
++
++ if (unlikely(skb->len > MAX_MRU)) {
++ dev_kfree_skb(skb);
++ port->stat.tx_errors++;
++ return NETDEV_TX_OK;
++ }
++
++ debug_pkt(dev, "eth_xmit", skb->data, skb->len);
++
++ len = skb->len;
++#ifdef __ARMEB__
++ offset = 0; /* no need to keep alignment */
++ bytes = len;
++ mem = skb->data;
++#else
++ offset = (int)skb->data & 3; /* keep 32-bit alignment */
++ bytes = ALIGN(offset + len, 4);
++ if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
++ dev_kfree_skb(skb);
++ port->stat.tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++ memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
++ dev_kfree_skb(skb);
++#endif
++
++ phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
++ if (dma_mapping_error(phys)) {
++#ifdef __ARMEB__
++ dev_kfree_skb(skb);
++#else
++ kfree(mem);
++#endif
++ port->stat.tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++
++ n = queue_get_desc(txreadyq, port, 1);
++ BUG_ON(n < 0);
++ desc = tx_desc_ptr(port, n);
++
++#ifdef __ARMEB__
++ port->tx_buff_tab[n] = skb;
++#else
++ port->tx_buff_tab[n] = mem;
++#endif
++ desc->data = phys + offset;
++ desc->buf_len = desc->pkt_len = len;
++
++ /* NPE firmware pads short frames with zeros internally */
++ wmb();
++ queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
++ dev->trans_start = jiffies;
++
++ if (qmgr_stat_empty(txreadyq)) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
++#endif
++ netif_stop_queue(dev);
++ /* we could miss TX ready interrupt */
++ if (!qmgr_stat_empty(txreadyq)) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: eth_xmit ready again\n",
++ dev->name);
++#endif
++ netif_wake_queue(dev);
++ }
++ }
++
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
++#endif
++ return NETDEV_TX_OK;
++}
++
++
++static struct net_device_stats *eth_stats(struct net_device *dev)
++{
++ struct port *port = netdev_priv(dev);
++ return &port->stat;
++}
++
++static void eth_set_mcast_list(struct net_device *dev)
++{
++ struct port *port = netdev_priv(dev);
++ struct dev_mc_list *mclist = dev->mc_list;
++ u8 diffs[ETH_ALEN], *addr;
++ int cnt = dev->mc_count, i;
++
++ if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
++ __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
++ &port->regs->rx_control[0]);
++ return;
++ }
++
++ memset(diffs, 0, ETH_ALEN);
++ addr = mclist->dmi_addr; /* first MAC address */
++
++ while (--cnt && (mclist = mclist->next))
++ for (i = 0; i < ETH_ALEN; i++)
++ diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
++
++ for (i = 0; i < ETH_ALEN; i++) {
++ __raw_writel(addr[i], &port->regs->mcast_addr[i]);
++ __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
++ }
++
++ __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
++ &port->regs->rx_control[0]);
++}
++
++
++static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
++{
++ struct port *port = netdev_priv(dev);
++ unsigned int duplex_chg;
++ int err;
++
++ if (!netif_running(dev))
++ return -EINVAL;
++ err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
++ if (duplex_chg)
++ eth_set_duplex(port);
++ return err;
++}
++
++
++static int request_queues(struct port *port)
++{
++ int err;
++
++ err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
++ if (err)
++ return err;
++
++ err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
++ if (err)
++ goto rel_rxfree;
++
++ err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
++ if (err)
++ goto rel_rx;
++
++ err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_tx;
++
++ /* TX-done queue handles skbs sent out by the NPEs */
++ if (!ports_open) {
++ err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
++ if (err)
++ goto rel_txready;
++ }
++ return 0;
++
++rel_txready:
++ qmgr_release_queue(port->plat->txreadyq);
++rel_tx:
++ qmgr_release_queue(TX_QUEUE(port->id));
++rel_rx:
++ qmgr_release_queue(port->plat->rxq);
++rel_rxfree:
++ qmgr_release_queue(RXFREE_QUEUE(port->id));
++ printk(KERN_DEBUG "%s: unable to request hardware queues\n",
++ port->netdev->name);
++ return err;
++}
++
++static void release_queues(struct port *port)
++{
++ qmgr_release_queue(RXFREE_QUEUE(port->id));
++ qmgr_release_queue(port->plat->rxq);
++ qmgr_release_queue(TX_QUEUE(port->id));
++ qmgr_release_queue(port->plat->txreadyq);
++
++ if (!ports_open)
++ qmgr_release_queue(TXDONE_QUEUE);
++}
++
++static int init_queues(struct port *port)
++{
++ int i;
++
++ if (!ports_open)
++ if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
++ POOL_ALLOC_SIZE, 32, 0)))
++ return -ENOMEM;
++
++ if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
++ &port->desc_tab_phys)))
++ return -ENOMEM;
++ memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
++ memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
++ memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
++
++ /* Setup RX buffers */
++ for (i = 0; i < RX_DESCS; i++) {
++ struct desc *desc = rx_desc_ptr(port, i);
++ buffer_t *buff;
++ void *data;
++#ifdef __ARMEB__
++ if (!(buff = netdev_alloc_skb(port->netdev, MAX_MRU)))
++ return -ENOMEM;
++ data = buff->data;
++#else
++ if (!(buff = kmalloc(MAX_MRU, GFP_KERNEL)))
++ return -ENOMEM;
++ data = buff;
++#endif
++ desc->buf_len = MAX_MRU;
++ desc->data = dma_map_single(&port->netdev->dev, data,
++ MAX_MRU, DMA_FROM_DEVICE);
++ if (dma_mapping_error(desc->data)) {
++ free_buffer(buff);
++ return -EIO;
++ }
++ port->rx_buff_tab[i] = buff;
++ }
++
++ return 0;
++}
++
++static void destroy_queues(struct port *port)
++{
++ int i;
++
++ if (port->desc_tab) {
++ for (i = 0; i < RX_DESCS; i++) {
++ struct desc *desc = rx_desc_ptr(port, i);
++ buffer_t *buff = port->rx_buff_tab[i];
++ if (buff) {
++ dma_unmap_single(&port->netdev->dev,
++ desc->data, MAX_MRU,
++ DMA_FROM_DEVICE);
++ free_buffer(buff);
++ }
++ }
++ for (i = 0; i < TX_DESCS; i++) {
++ struct desc *desc = tx_desc_ptr(port, i);
++ buffer_t *buff = port->tx_buff_tab[i];
++ if (buff) {
++ dma_unmap_tx(port, desc);
++ free_buffer(buff);
++ }
++ }
++ dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
++ port->desc_tab = NULL;
++ }
++
++ if (!ports_open && dma_pool) {
++ dma_pool_destroy(dma_pool);
++ dma_pool = NULL;
++ }
++}
++
++static int eth_open(struct net_device *dev)
++{
++ struct port *port = netdev_priv(dev);
++ struct npe *npe = port->npe;
++ struct msg msg;
++ int i, err;
++
++ if (!npe_running(npe)) {
++ err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
++ if (err)
++ return err;
++
++ if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
++ printk(KERN_ERR "%s: %s not responding\n", dev->name,
++ npe_name(npe));
++ return -EIO;
++ }
++ }
++
++ mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = NPE_VLAN_SETRXQOSENTRY;
++ msg.eth_id = port->id;
++ msg.byte5 = port->plat->rxq | 0x80;
++ msg.byte7 = port->plat->rxq << 4;
++ for (i = 0; i < 8; i++) {
++ msg.byte3 = i;
++ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
++ return -EIO;
++ }
++
++ msg.cmd = NPE_EDB_SETPORTADDRESS;
++ msg.eth_id = PHYSICAL_ID(port->id);
++ msg.byte2 = dev->dev_addr[0];
++ msg.byte3 = dev->dev_addr[1];
++ msg.byte4 = dev->dev_addr[2];
++ msg.byte5 = dev->dev_addr[3];
++ msg.byte6 = dev->dev_addr[4];
++ msg.byte7 = dev->dev_addr[5];
++ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
++ return -EIO;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = NPE_FW_SETFIREWALLMODE;
++ msg.eth_id = port->id;
++ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
++ return -EIO;
++
++ if ((err = request_queues(port)) != 0)
++ return err;
++
++ if ((err = init_queues(port)) != 0) {
++ destroy_queues(port);
++ release_queues(port);
++ return err;
++ }
++
++ for (i = 0; i < ETH_ALEN; i++)
++ __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
++ __raw_writel(0x08, &port->regs->random_seed);
++ __raw_writel(0x12, &port->regs->partial_empty_threshold);
++ __raw_writel(0x30, &port->regs->partial_full_threshold);
++ __raw_writel(0x08, &port->regs->tx_start_bytes);
++ __raw_writel(0x15, &port->regs->tx_deferral);
++ __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
++ __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
++ __raw_writel(0x80, &port->regs->slot_time);
++ __raw_writel(0x01, &port->regs->int_clock_threshold);
++
++ /* Populate queues with buffers, no failure after this point */
++ for (i = 0; i < TX_DESCS; i++)
++ queue_put_desc(port->plat->txreadyq,
++ tx_desc_phys(port, i), tx_desc_ptr(port, i));
++
++ for (i = 0; i < RX_DESCS; i++)
++ queue_put_desc(RXFREE_QUEUE(port->id),
++ rx_desc_phys(port, i), rx_desc_ptr(port, i));
++
++ __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
++ __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
++ __raw_writel(0, &port->regs->rx_control[1]);
++ __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
++
++ phy_check_media(port, 1);
++ eth_set_mcast_list(dev);
++ netif_start_queue(dev);
++ schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
++
++ qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
++ eth_rx_irq, dev);
++ if (!ports_open) {
++ qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
++ eth_txdone_irq, NULL);
++ qmgr_enable_irq(TXDONE_QUEUE);
++ }
++ ports_open++;
++ netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
++ return 0;
++}
++
++static int eth_close(struct net_device *dev)
++{
++ struct port *port = netdev_priv(dev);
++ struct msg msg;
++ int buffs = RX_DESCS; /* allocated RX buffers */
++ int i;
++
++ ports_open--;
++ qmgr_disable_irq(port->plat->rxq);
++ netif_stop_queue(dev);
++
++ while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
++ buffs--;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = NPE_SETLOOPBACK_MODE;
++ msg.eth_id = port->id;
++ msg.byte3 = 1;
++ if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
++ printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
++
++ i = 0;
++ do { /* drain RX buffers */
++ while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
++ buffs--;
++ if (!buffs)
++ break;
++ if (qmgr_stat_empty(TX_QUEUE(port->id))) {
++ /* we have to inject some packet */
++ struct desc *desc;
++ u32 phys;
++ int n = queue_get_desc(port->plat->txreadyq, port, 1);
++ BUG_ON(n < 0);
++ desc = tx_desc_ptr(port, n);
++ phys = tx_desc_phys(port, n);
++ desc->buf_len = desc->pkt_len = 1;
++ wmb();
++ queue_put_desc(TX_QUEUE(port->id), phys, desc);
++ }
++ udelay(1);
++ } while (++i < MAX_CLOSE_WAIT);
++
++ if (buffs)
++ printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
++ " left in NPE\n", dev->name, buffs);
++#if DEBUG_CLOSE
++ if (!buffs)
++ printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
++#endif
++
++ buffs = TX_DESCS;
++ while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
++ buffs--; /* cancel TX */
++
++ i = 0;
++ do {
++ while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
++ buffs--;
++ if (!buffs)
++ break;
++ } while (++i < MAX_CLOSE_WAIT);
++
++ if (buffs)
++ printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
++ "left in NPE\n", dev->name, buffs);
++#if DEBUG_CLOSE
++ if (!buffs)
++ printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
++#endif
++
++ msg.byte3 = 0;
++ if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
++ printk(KERN_CRIT "%s: unable to disable loopback\n",
++ dev->name);
++
++ port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
++ ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
++ mdio_write(dev, port->plat->phy, MII_BMCR,
++ port->mii_bmcr | BMCR_PDOWN);
++
++ if (!ports_open)
++ qmgr_disable_irq(TXDONE_QUEUE);
++ cancel_rearming_delayed_work(&port->mdio_thread);
++ destroy_queues(port);
++ release_queues(port);
++ return 0;
++}
++
++static int __devinit eth_init_one(struct platform_device *pdev)
++{
++ struct port *port;
++ struct net_device *dev;
++ struct eth_plat_info *plat = pdev->dev.platform_data;
++ u32 regs_phys;
++ int err;
++
++ if (!(dev = alloc_etherdev(sizeof(struct port))))
++ return -ENOMEM;
++
++ SET_MODULE_OWNER(dev);
++ SET_NETDEV_DEV(dev, &pdev->dev);
++ port = netdev_priv(dev);
++ port->netdev = dev;
++ port->id = pdev->id;
++
++ switch (port->id) {
++ case IXP4XX_ETH_NPEA:
++ port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
++ regs_phys = IXP4XX_EthA_BASE_PHYS;
++ break;
++ case IXP4XX_ETH_NPEB:
++ port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
++ regs_phys = IXP4XX_EthB_BASE_PHYS;
++ break;
++ case IXP4XX_ETH_NPEC:
++ port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
++ regs_phys = IXP4XX_EthC_BASE_PHYS;
++ break;
++ default:
++ err = -ENOSYS;
++ goto err_free;
++ }
++
++ dev->open = eth_open;
++ dev->hard_start_xmit = eth_xmit;
++ dev->poll = eth_poll;
++ dev->stop = eth_close;
++ dev->get_stats = eth_stats;
++ dev->do_ioctl = eth_ioctl;
++ dev->set_multicast_list = eth_set_mcast_list;
++ dev->weight = 16;
++ dev->tx_queue_len = 100;
++
++ if (!(port->npe = npe_request(NPE_ID(port->id)))) {
++ err = -EIO;
++ goto err_free;
++ }
++
++ if (register_netdev(dev)) {
++ err = -EIO;
++ goto err_npe_rel;
++ }
++
++ port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
++ if (!port->mem_res) {
++ err = -EBUSY;
++ goto err_unreg;
++ }
++
++ port->plat = plat;
++ npe_port_tab[NPE_ID(port->id)] = port;
++ memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
++
++ platform_set_drvdata(pdev, dev);
++
++ __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
++ &port->regs->core_control);
++ udelay(50);
++ __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
++ udelay(50);
++
++ port->mii.dev = dev;
++ port->mii.mdio_read = mdio_read;
++ port->mii.mdio_write = mdio_write;
++ port->mii.phy_id = plat->phy;
++ port->mii.phy_id_mask = 0x1F;
++ port->mii.reg_num_mask = 0x1F;
++
++ printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
++ npe_name(port->npe));
++
++ phy_reset(dev, plat->phy);
++ port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
++ ~(BMCR_RESET | BMCR_PDOWN);
++ mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
++
++ INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
++ return 0;
++
++err_unreg:
++ unregister_netdev(dev);
++err_npe_rel:
++ npe_release(port->npe);
++err_free:
++ free_netdev(dev);
++ return err;
++}
++
++static int __devexit eth_remove_one(struct platform_device *pdev)
++{
++ struct net_device *dev = platform_get_drvdata(pdev);
++ struct port *port = netdev_priv(dev);
++
++ unregister_netdev(dev);
++ npe_port_tab[NPE_ID(port->id)] = NULL;
++ platform_set_drvdata(pdev, NULL);
++ npe_release(port->npe);
++ release_resource(port->mem_res);
++ free_netdev(dev);
++ return 0;
++}
++
++static struct platform_driver drv = {
++ .driver.name = DRV_NAME,
++ .probe = eth_init_one,
++ .remove = eth_remove_one,
++};
++
++static int __init eth_init_module(void)
++{
++ if (!(ixp4xx_read_fuses() & IXP4XX_FUSE_NPEB_ETH0))
++ return -ENOSYS;
++
++ /* All MII PHY accesses use NPE-B Ethernet registers */
++ spin_lock_init(&mdio_lock);
++ mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
++ __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
++
++ return platform_driver_register(&drv);
++}
++
++static void __exit eth_cleanup_module(void)
++{
++ platform_driver_unregister(&drv);
++}
++
++MODULE_AUTHOR("Krzysztof Halasa");
++MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
++MODULE_LICENSE("GPL v2");
++module_init(eth_init_module);
++module_exit(eth_cleanup_module);
+diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/wan/Kconfig ixp4xx-nep.git/drivers/net/wan/Kconfig
+--- linux-2.6.23/drivers/net/wan/Kconfig 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/drivers/net/wan/Kconfig 2007-10-22 19:20:05.000000000 +0200
+@@ -334,6 +334,15 @@
+
+ Say Y if your card supports this feature.
+
++config IXP4XX_HSS
++ tristate "IXP4xx HSS (synchronous serial port) support"
++ depends on HDLC && ARM && ARCH_IXP4XX
++ select IXP4XX_NPE
++ select IXP4XX_QMGR
++ help
++ Say Y here if you want to use built-in HSS ports
++ on IXP4xx processor.
++
+ config DLCI
+ tristate "Frame Relay DLCI support"
+ ---help---
+diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/wan/Makefile ixp4xx-nep.git/drivers/net/wan/Makefile
+--- linux-2.6.23/drivers/net/wan/Makefile 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/drivers/net/wan/Makefile 2007-10-22 19:20:05.000000000 +0200
+@@ -42,6 +42,7 @@
+ obj-$(CONFIG_WANXL) += wanxl.o
+ obj-$(CONFIG_PCI200SYN) += pci200syn.o
+ obj-$(CONFIG_PC300TOO) += pc300too.o
++obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
+
+ clean-files := wanxlfw.inc
+ $(obj)/wanxl.o: $(obj)/wanxlfw.inc
+diff -Nur -x .git -x .gitignore linux-2.6.23/drivers/net/wan/ixp4xx_hss.c ixp4xx-nep.git/drivers/net/wan/ixp4xx_hss.c
+--- linux-2.6.23/drivers/net/wan/ixp4xx_hss.c 1970-01-01 01:00:00.000000000 +0100
++++ ixp4xx-nep.git/drivers/net/wan/ixp4xx_hss.c 2007-10-22 19:20:05.000000000 +0200
+@@ -0,0 +1,1248 @@
++/*
++ * Intel IXP4xx HSS (synchronous serial port) driver for Linux
++ *
++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License
++ * as published by the Free Software Foundation.
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/kernel.h>
++#include <linux/hdlc.h>
++#include <linux/platform_device.h>
++#include <asm/io.h>
++#include <asm/arch/npe.h>
++#include <asm/arch/qmgr.h>
++
++#define DEBUG_QUEUES 0
++#define DEBUG_DESC 0
++#define DEBUG_RX 0
++#define DEBUG_TX 0
++#define DEBUG_PKT_BYTES 0
++#define DEBUG_CLOSE 0
++
++#define DRV_NAME "ixp4xx_hss"
++
++#define PKT_EXTRA_FLAGS 0 /* orig 1 */
++#define FRAME_SYNC_OFFSET 0 /* unused, channelized only */
++#define FRAME_SYNC_SIZE 1024
++#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
++#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
++
++#define RX_DESCS 16 /* also length of all RX queues */
++#define TX_DESCS 16 /* also length of all TX queues */
++
++#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
++#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
++#define MAX_CLOSE_WAIT 1000 /* microseconds */
++
++/* Queue IDs */
++#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
++#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
++#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
++#define HSS0_PKT_TX1_QUEUE 15
++#define HSS0_PKT_TX2_QUEUE 16
++#define HSS0_PKT_TX3_QUEUE 17
++#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
++#define HSS0_PKT_RXFREE1_QUEUE 19
++#define HSS0_PKT_RXFREE2_QUEUE 20
++#define HSS0_PKT_RXFREE3_QUEUE 21
++#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
++
++#define HSS1_CHL_RXTRIG_QUEUE 10
++#define HSS1_PKT_RX_QUEUE 0
++#define HSS1_PKT_TX0_QUEUE 5
++#define HSS1_PKT_TX1_QUEUE 6
++#define HSS1_PKT_TX2_QUEUE 7
++#define HSS1_PKT_TX3_QUEUE 8
++#define HSS1_PKT_RXFREE0_QUEUE 1
++#define HSS1_PKT_RXFREE1_QUEUE 2
++#define HSS1_PKT_RXFREE2_QUEUE 3
++#define HSS1_PKT_RXFREE3_QUEUE 4
++#define HSS1_PKT_TXDONE_QUEUE 9
++
++#define NPE_PKT_MODE_HDLC 0
++#define NPE_PKT_MODE_RAW 1
++#define NPE_PKT_MODE_56KMODE 2
++#define NPE_PKT_MODE_56KENDIAN_MSB 4
++
++/* PKT_PIPE_HDLC_CFG_WRITE flags */
++#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
++#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
++#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
++
++
++/* hss_config, PCRs */
++/* Frame sync sampling, default = active low */
++#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
++#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
++#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
++
++/* Frame sync pin: input (default) or output generated off a given clk edge */
++#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
++#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
++
++/* Frame and data clock sampling on edge, default = falling */
++#define PCR_FCLK_EDGE_RISING 0x08000000
++#define PCR_DCLK_EDGE_RISING 0x04000000
++
++/* Clock direction, default = input */
++#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
++
++/* Generate/Receive frame pulses, default = enabled */
++#define PCR_FRM_PULSE_DISABLED 0x01000000
++
++ /* Data rate is full (default) or half the configured clk speed */
++#define PCR_HALF_CLK_RATE 0x00200000
++
++/* Invert data between NPE and HSS FIFOs? (default = no) */
++#define PCR_DATA_POLARITY_INVERT 0x00100000
++
++/* TX/RX endianness, default = LSB */
++#define PCR_MSB_ENDIAN 0x00080000
++
++/* Normal (default) / open drain mode (TX only) */
++#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
++
++/* No framing bit transmitted and expected on RX? (default = framing bit) */
++#define PCR_SOF_NO_FBIT 0x00020000
++
++/* Drive data pins? */
++#define PCR_TX_DATA_ENABLE 0x00010000
++
++/* Voice 56k type: drive the data pins low (default), high, high Z */
++#define PCR_TX_V56K_HIGH 0x00002000
++#define PCR_TX_V56K_HIGH_IMP 0x00004000
++
++/* Unassigned type: drive the data pins low (default), high, high Z */
++#define PCR_TX_UNASS_HIGH 0x00000800
++#define PCR_TX_UNASS_HIGH_IMP 0x00001000
++
++/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
++#define PCR_TX_FB_HIGH_IMP 0x00000400
++
++/* 56k data endiannes - which bit unused: high (default) or low */
++#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
++
++/* 56k data transmission type: 32/8 bit data (default) or 56K data */
++#define PCR_TX_56KS_56K_DATA 0x00000100
++
++/* hss_config, cCR */
++/* Number of packetized clients, default = 1 */
++#define CCR_NPE_HFIFO_2_HDLC 0x04000000
++#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
++
++/* default = no loopback */
++#define CCR_LOOPBACK 0x02000000
++
++/* HSS number, default = 0 (first) */
++#define CCR_SECOND_HSS 0x01000000
++
++
++/* hss_config, clkCR: main:10, num:10, denom:12 */
++#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
++
++#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
++#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
++#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
++#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
++#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
++#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
++
++#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
++#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
++#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
++#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
++#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
++#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
++
++
++/* hss_config, LUTs: default = unassigned */
++#define TDMMAP_HDLC 1 /* HDLC - packetised */
++#define TDMMAP_VOICE56K 2 /* Voice56K - channelised */
++#define TDMMAP_VOICE64K 3 /* Voice64K - channelised */
++
++
++/* NPE command codes */
++/* writes the ConfigWord value to the location specified by offset */
++#define PORT_CONFIG_WRITE 0x40
++
++/* triggers the NPE to load the contents of the configuration table */
++#define PORT_CONFIG_LOAD 0x41
++
++/* triggers the NPE to return an HssErrorReadResponse message */
++#define PORT_ERROR_READ 0x42
++
++/* reset NPE internal status and enable the HssChannelized operation */
++#define CHAN_FLOW_ENABLE 0x43
++#define CHAN_FLOW_DISABLE 0x44
++#define CHAN_IDLE_PATTERN_WRITE 0x45
++#define CHAN_NUM_CHANS_WRITE 0x46
++#define CHAN_RX_BUF_ADDR_WRITE 0x47
++#define CHAN_RX_BUF_CFG_WRITE 0x48
++#define CHAN_TX_BLK_CFG_WRITE 0x49
++#define CHAN_TX_BUF_ADDR_WRITE 0x4A
++#define CHAN_TX_BUF_SIZE_WRITE 0x4B
++#define CHAN_TSLOTSWITCH_ENABLE 0x4C
++#define CHAN_TSLOTSWITCH_DISABLE 0x4D
++
++/* downloads the gainWord value for a timeslot switching channel associated
++ with bypassNum */
++#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
++
++/* triggers the NPE to reset internal status and enable the HssPacketized
++ operation for the flow specified by pPipe */
++#define PKT_PIPE_FLOW_ENABLE 0x50
++#define PKT_PIPE_FLOW_DISABLE 0x51
++#define PKT_NUM_PIPES_WRITE 0x52
++#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
++#define PKT_PIPE_HDLC_CFG_WRITE 0x54
++#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
++#define PKT_PIPE_RX_SIZE_WRITE 0x56
++#define PKT_PIPE_MODE_WRITE 0x57
++
++
++#define HSS_TIMESLOTS 128
++#define HSS_LUT_BITS 2
++
++/* HDLC packet status values - desc->status */
++#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
++#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
++#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
++#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
++ this packet (if buf_len < pkt_len) */
++#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
++#define ERR_HDLC_ABORT 6 /* abort sequence received */
++#define ERR_DISCONNECTING 7 /* disconnect is in progress */
++
++
++#ifdef __ARMEB__
++typedef struct sk_buff buffer_t;
++#define free_buffer dev_kfree_skb
++#define free_buffer_irq dev_kfree_skb_irq
++#else
++typedef void buffer_t;
++#define free_buffer kfree
++#define free_buffer_irq kfree
++#endif
++
++struct port {
++ struct npe *npe;
++ struct net_device *netdev;
++ struct hss_plat_info *plat;
++ buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
++ struct desc *desc_tab; /* coherent */
++ u32 desc_tab_phys;
++ sync_serial_settings settings;
++ int id;
++ u8 hdlc_cfg;
++};
++
++/* NPE message structure */
++struct msg {
++#ifdef __ARMEB__
++ u8 cmd, unused, hss_port, index;
++ union {
++ struct { u8 data8a, data8b, data8c, data8d; };
++ struct { u16 data16a, data16b; };
++ struct { u32 data32; };
++ };
++#else
++ u8 index, hss_port, unused, cmd;
++ union {
++ struct { u8 data8d, data8c, data8b, data8a; };
++ struct { u16 data16b, data16a; };
++ struct { u32 data32; };
++ };
++#endif
++};
++
++/* HDLC packet descriptor */
++struct desc {
++ u32 next; /* pointer to next buffer, unused */
++
++#ifdef __ARMEB__
++ u16 buf_len; /* buffer length */
++ u16 pkt_len; /* packet length */
++ u32 data; /* pointer to data buffer in RAM */
++ u8 status;
++ u8 error_count;
++ u16 __reserved;
++#else
++ u16 pkt_len; /* packet length */
++ u16 buf_len; /* buffer length */
++ u32 data; /* pointer to data buffer in RAM */
++ u16 __reserved;
++ u8 error_count;
++ u8 status;
++#endif
++ u32 __reserved1[4];
++};
++
++
++#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
++ (n) * sizeof(struct desc))
++#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
++
++#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
++ ((n) + RX_DESCS) * sizeof(struct desc))
++#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
++
++#ifndef __ARMEB__
++static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
++{
++ int i;
++ for (i = 0; i < cnt; i++)
++ dest[i] = swab32(src[i]);
++}
++#endif
++
++static int ports_open;
++static struct dma_pool *dma_pool;
++
++static struct {
++ int tx, txdone, rx, rxfree;
++}queue_ids[2] = {{ HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE,
++ HSS0_PKT_RX_QUEUE, HSS0_PKT_RXFREE0_QUEUE },
++ { HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE,
++ HSS1_PKT_RX_QUEUE, HSS1_PKT_RXFREE0_QUEUE },
++};
++
++
++static inline struct port* dev_to_port(struct net_device *dev)
++{
++ return dev_to_hdlc(dev)->priv;
++}
++
++
++static inline void debug_pkt(struct net_device *dev, const char *func,
++ u8 *data, int len)
++{
++#if DEBUG_PKT_BYTES
++ int i;
++
++ printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
++ for (i = 0; i < len; i++) {
++ if (i >= DEBUG_PKT_BYTES)
++ break;
++ printk("%s%02X", !(i % 4) ? " " : "", data[i]);
++ }
++ printk("\n");
++#endif
++}
++
++
++static inline void debug_desc(u32 phys, struct desc *desc)
++{
++#if DEBUG_DESC
++ printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
++ phys, desc->next, desc->buf_len, desc->pkt_len,
++ desc->data, desc->status, desc->error_count);
++#endif
++}
++
++static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
++{
++#if DEBUG_QUEUES
++ static struct {
++ int queue;
++ char *name;
++ } names[] = {
++ { HSS0_PKT_TX0_QUEUE, "TX#0 " },
++ { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
++ { HSS0_PKT_RX_QUEUE, "RX#0 " },
++ { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
++ { HSS1_PKT_TX0_QUEUE, "TX#1 " },
++ { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
++ { HSS1_PKT_RX_QUEUE, "RX#1 " },
++ { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
++ };
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(names); i++)
++ if (names[i].queue == queue)
++ break;
++
++ printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
++ i < ARRAY_SIZE(names) ? names[i].name : "",
++ is_get ? "->" : "<-", phys);
++#endif
++}
++
++static inline u32 queue_get_entry(unsigned int queue)
++{
++ u32 phys = qmgr_get_entry(queue);
++ debug_queue(queue, 1, phys);
++ return phys;
++}
++
++static inline int queue_get_desc(unsigned int queue, struct port *port,
++ int is_tx)
++{
++ u32 phys, tab_phys, n_desc;
++ struct desc *tab;
++
++ if (!(phys = queue_get_entry(queue)))
++ return -1;
++
++ BUG_ON(phys & 0x1F);
++ tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
++ tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
++ n_desc = (phys - tab_phys) / sizeof(struct desc);
++ BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
++ debug_desc(phys, &tab[n_desc]);
++ BUG_ON(tab[n_desc].next);
++ return n_desc;
++}
++
++static inline void queue_put_desc(unsigned int queue, u32 phys,
++ struct desc *desc)
++{
++ debug_queue(queue, 0, phys);
++ debug_desc(phys, desc);
++ BUG_ON(phys & 0x1F);
++ qmgr_put_entry(queue, phys);
++ BUG_ON(qmgr_stat_overflow(queue));
++}
++
++
++static inline void dma_unmap_tx(struct port *port, struct desc *desc)
++{
++#ifdef __ARMEB__
++ dma_unmap_single(&port->netdev->dev, desc->data,
++ desc->buf_len, DMA_TO_DEVICE);
++#else
++ dma_unmap_single(&port->netdev->dev, desc->data & ~3,
++ ALIGN((desc->data & 3) + desc->buf_len, 4),
++ DMA_TO_DEVICE);
++#endif
++}
++
++
++static void hss_set_carrier(void *pdev, int carrier)
++{
++ struct net_device *dev = pdev;
++ if (carrier)
++ netif_carrier_on(dev);
++ else
++ netif_carrier_off(dev);
++}
++
++static void hss_rx_irq(void *pdev)
++{
++ struct net_device *dev = pdev;
++ struct port *port = dev_to_port(dev);
++
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_rx_irq\n", dev->name);
++#endif
++ qmgr_disable_irq(queue_ids[port->id].rx);
++ netif_rx_schedule(dev);
++}
++
++static int hss_poll(struct net_device *dev, int *budget)
++{
++ struct port *port = dev_to_port(dev);
++ unsigned int rxq = queue_ids[port->id].rx;
++ unsigned int rxfreeq = queue_ids[port->id].rxfree;
++ struct net_device_stats *stats = hdlc_stats(dev);
++ int quota = dev->quota, received = 0;
++
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_poll\n", dev->name);
++#endif
++
++ while (quota) {
++ struct sk_buff *skb;
++ struct desc *desc;
++ int n;
++#ifdef __ARMEB__
++ struct sk_buff *temp;
++ u32 phys;
++#endif
++
++ if ((n = queue_get_desc(rxq, port, 0)) < 0) {
++ dev->quota -= received; /* No packet received */
++ *budget -= received;
++ received = 0;
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_poll netif_rx_complete\n",
++ dev->name);
++#endif
++ netif_rx_complete(dev);
++ qmgr_enable_irq(rxq);
++ if (!qmgr_stat_empty(rxq) &&
++ netif_rx_reschedule(dev, 0)) {
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_poll"
++ " netif_rx_reschedule successed\n",
++ dev->name);
++#endif
++ qmgr_disable_irq(rxq);
++ continue;
++ }
++#if DEBUG_RX
++ printk(KERN_DEBUG "%s: hss_poll all done\n",
++ dev->name);
++#endif
++ return 0; /* all work done */
++ }
++
++ desc = rx_desc_ptr(port, n);
++
++ if (desc->error_count) /* FIXME - remove printk */
++ printk(KERN_DEBUG "%s: hss_poll status 0x%02X errors"
++ " %u\n", dev->name, desc->status,
++ desc->error_count);
++
++ skb = NULL;
++ switch (desc->status) {
++ case 0:
++#ifdef __ARMEB__
++ if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
++ phys = dma_map_single(&dev->dev, skb->data,
++ RX_SIZE,
++ DMA_FROM_DEVICE);
++ if (dma_mapping_error(phys)) {
++ dev_kfree_skb(skb);
++ skb = NULL;
++ }
++ }
++#else
++ skb = netdev_alloc_skb(dev, desc->pkt_len);
++#endif
++ if (!skb)
++ stats->rx_dropped++;
++ break;
++ case ERR_HDLC_ALIGN:
++ case ERR_HDLC_ABORT:
++ stats->rx_frame_errors++;
++ stats->rx_errors++;
++ break;
++ case ERR_HDLC_FCS:
++ stats->rx_crc_errors++;
++ stats->rx_errors++;
++ break;
++ case ERR_HDLC_TOO_LONG:
++ stats->rx_length_errors++;
++ stats->rx_errors++;
++ break;
++ default: /* FIXME - remove printk */
++ printk(KERN_ERR "%s: hss_poll(): status 0x%02X errors"
++ " %u\n", dev->name, desc->status,
++ desc->error_count);
++ stats->rx_errors++;
++ }
++
++ if (!skb) {
++ /* put the desc back on RX-ready queue */
++ desc->buf_len = RX_SIZE;
++ desc->pkt_len = desc->status = 0;
++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
++ continue;
++ }
++
++ /* process received frame */
++#ifdef __ARMEB__
++ temp = skb;
++ skb = port->rx_buff_tab[n];
++ dma_unmap_single(&dev->dev, desc->data,
++ RX_SIZE, DMA_FROM_DEVICE);
++#else
++ dma_sync_single(&dev->dev, desc->data,
++ RX_SIZE, DMA_FROM_DEVICE);
++ memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
++ ALIGN(desc->pkt_len, 4) / 4);
++#endif
++ skb_put(skb, desc->pkt_len);
++
++ debug_pkt(dev, "hss_poll", skb->data, skb->len);
++
++ skb->protocol = hdlc_type_trans(skb, dev);
++ dev->last_rx = jiffies;
++ stats->rx_packets++;
++ stats->rx_bytes += skb->len;
++ netif_receive_skb(skb);
++
++ /* put the new buffer on RX-free queue */
++#ifdef __ARMEB__
++ port->rx_buff_tab[n] = temp;
++ desc->data = phys;
++#endif
++ desc->buf_len = RX_SIZE;
++ desc->pkt_len = 0;
++ queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
++ quota--;
++ received++;
++ }
++ dev->quota -= received;
++ *budget -= received;
++#if DEBUG_RX
++ printk(KERN_DEBUG "hss_poll(): end, not all work done\n");
++#endif
++ return 1; /* not all work done */
++}
++
++
++static void hss_txdone_irq(void *pdev)
++{
++ struct net_device *dev = pdev;
++ struct port *port = dev_to_port(dev);
++ struct net_device_stats *stats = hdlc_stats(dev);
++ int n_desc;
++
++#if DEBUG_TX
++ printk(KERN_DEBUG DRV_NAME ": hss_txdone_irq\n");
++#endif
++ while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
++ port, 1)) >= 0) {
++ struct desc *desc;
++ int start;
++
++ desc = tx_desc_ptr(port, n_desc);
++
++ stats->tx_packets++;
++ stats->tx_bytes += desc->pkt_len;
++
++ dma_unmap_tx(port, desc);
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_txdone_irq free %p\n",
++ port->netdev->name, port->tx_buff_tab[n_desc]);
++#endif
++ free_buffer_irq(port->tx_buff_tab[n_desc]);
++ port->tx_buff_tab[n_desc] = NULL;
++
++ start = qmgr_stat_empty(port->plat->txreadyq);
++ queue_put_desc(port->plat->txreadyq,
++ tx_desc_phys(port, n_desc), desc);
++ if (start) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_txdone_irq xmit ready\n",
++ port->netdev->name);
++#endif
++ netif_wake_queue(port->netdev);
++ }
++ }
++}
++
++static int hss_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ struct port *port = dev_to_port(dev);
++ struct net_device_stats *stats = hdlc_stats(dev);
++ unsigned int txreadyq = port->plat->txreadyq;
++ int len, offset, bytes, n;
++ void *mem;
++ u32 phys;
++ struct desc *desc;
++
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_xmit\n", dev->name);
++#endif
++
++ if (unlikely(skb->len > HDLC_MAX_MRU)) {
++ dev_kfree_skb(skb);
++ stats->tx_errors++;
++ return NETDEV_TX_OK;
++ }
++
++ debug_pkt(dev, "hss_xmit", skb->data, skb->len);
++
++ len = skb->len;
++#ifdef __ARMEB__
++ offset = 0; /* no need to keep alignment */
++ bytes = len;
++ mem = skb->data;
++#else
++ offset = (int)skb->data & 3; /* keep 32-bit alignment */
++ bytes = ALIGN(offset + len, 4);
++ if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
++ dev_kfree_skb(skb);
++ stats->tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++ memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
++ dev_kfree_skb(skb);
++#endif
++
++ phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
++ if (dma_mapping_error(phys)) {
++#ifdef __ARMEB__
++ dev_kfree_skb(skb);
++#else
++ kfree(mem);
++#endif
++ stats->tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++
++ n = queue_get_desc(txreadyq, port, 1);
++ BUG_ON(n < 0);
++ desc = tx_desc_ptr(port, n);
++
++#ifdef __ARMEB__
++ port->tx_buff_tab[n] = skb;
++#else
++ port->tx_buff_tab[n] = mem;
++#endif
++ desc->data = phys + offset;
++ desc->buf_len = desc->pkt_len = len;
++
++ wmb();
++ queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
++ dev->trans_start = jiffies;
++
++ if (qmgr_stat_empty(txreadyq)) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_xmit queue full\n", dev->name);
++#endif
++ netif_stop_queue(dev);
++ /* we could miss TX ready interrupt */
++ if (!qmgr_stat_empty(txreadyq)) {
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_xmit ready again\n",
++ dev->name);
++#endif
++ netif_wake_queue(dev);
++ }
++ }
++
++#if DEBUG_TX
++ printk(KERN_DEBUG "%s: hss_xmit end\n", dev->name);
++#endif
++ return NETDEV_TX_OK;
++}
++
++
++static int request_queues(struct port *port)
++{
++ int err;
++
++ err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
++ if (err)
++ return err;
++
++ err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
++ if (err)
++ goto rel_rxfree;
++
++ err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_rx;
++
++ err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_tx;
++
++ err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
++ if (err)
++ goto rel_txready;
++ return 0;
++
++rel_txready:
++ qmgr_release_queue(port->plat->txreadyq);
++rel_tx:
++ qmgr_release_queue(queue_ids[port->id].tx);
++rel_rx:
++ qmgr_release_queue(queue_ids[port->id].rx);
++rel_rxfree:
++ qmgr_release_queue(queue_ids[port->id].rxfree);
++ printk(KERN_DEBUG "%s: unable to request hardware queues\n",
++ port->netdev->name);
++ return err;
++}
++
++static void release_queues(struct port *port)
++{
++ qmgr_release_queue(queue_ids[port->id].rxfree);
++ qmgr_release_queue(queue_ids[port->id].rx);
++ qmgr_release_queue(queue_ids[port->id].txdone);
++ qmgr_release_queue(queue_ids[port->id].tx);
++ qmgr_release_queue(port->plat->txreadyq);
++}
++
++static int init_queues(struct port *port)
++{
++ int i;
++
++ if (!ports_open)
++ if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
++ POOL_ALLOC_SIZE, 32, 0)))
++ return -ENOMEM;
++
++ if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
++ &port->desc_tab_phys)))
++ return -ENOMEM;
++ memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
++ memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
++ memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
++
++ /* Setup RX buffers */
++ for (i = 0; i < RX_DESCS; i++) {
++ struct desc *desc = rx_desc_ptr(port, i);
++ buffer_t *buff;
++ void *data;
++#ifdef __ARMEB__
++ if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
++ return -ENOMEM;
++ data = buff->data;
++#else
++ if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
++ return -ENOMEM;
++ data = buff;
++#endif
++ desc->buf_len = RX_SIZE;
++ desc->data = dma_map_single(&port->netdev->dev, data,
++ RX_SIZE, DMA_FROM_DEVICE);
++ if (dma_mapping_error(desc->data)) {
++ free_buffer(buff);
++ return -EIO;
++ }
++ port->rx_buff_tab[i] = buff;
++ }
++
++ return 0;
++}
++
++static void destroy_queues(struct port *port)
++{
++ int i;
++
++ if (port->desc_tab) {
++ for (i = 0; i < RX_DESCS; i++) {
++ struct desc *desc = rx_desc_ptr(port, i);
++ buffer_t *buff = port->rx_buff_tab[i];
++ if (buff) {
++ dma_unmap_single(&port->netdev->dev,
++ desc->data, RX_SIZE,
++ DMA_FROM_DEVICE);
++ free_buffer(buff);
++ }
++ }
++ for (i = 0; i < TX_DESCS; i++) {
++ struct desc *desc = tx_desc_ptr(port, i);
++ buffer_t *buff = port->tx_buff_tab[i];
++ if (buff) {
++ dma_unmap_tx(port, desc);
++ free_buffer(buff);
++ }
++ }
++ dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
++ port->desc_tab = NULL;
++ }
++
++ if (!ports_open && dma_pool) {
++ dma_pool_destroy(dma_pool);
++ dma_pool = NULL;
++ }
++}
++
++static int hss_open(struct net_device *dev)
++{
++ struct port *port = dev_to_port(dev);
++ struct npe *npe = port->npe;
++ struct msg msg;
++ int i, err;
++
++ if (!npe_running(npe)) {
++ err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
++ if (err)
++ return err;
++ }
++
++ if ((err = hdlc_open(dev)) != 0)
++ return err;
++
++ if (port->plat->open)
++ if ((err = port->plat->open(port->id, port->netdev,
++ hss_set_carrier)) != 0)
++ goto err_hdlc_close;
++
++ /* HSS main configuration */
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_WRITE;
++ msg.hss_port = port->id;
++ msg.index = 0; /* offset in HSS config */
++
++ msg.data32 = PCR_FRM_PULSE_DISABLED |
++ PCR_SOF_NO_FBIT |
++ PCR_MSB_ENDIAN |
++ PCR_TX_DATA_ENABLE;
++
++ if (port->settings.clock_type == CLOCK_INT)
++ msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
++
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_PCR") != 0))
++ goto err_plat_close; /* 0: TX PCR */
++
++ msg.index = 4;
++ msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_PCR") != 0))
++ goto err_plat_close; /* 4: RX PCR */
++
++ msg.index = 8;
++ msg.data32 = (port->settings.loopback ? CCR_LOOPBACK : 0) |
++ (port->id ? CCR_SECOND_HSS : 0);
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_CORE_CR") != 0))
++ goto err_plat_close; /* 8: Core CR */
++
++ msg.index = 12;
++ msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_CLK_CR") != 0))
++ goto err_plat_close; /* 12: CLK CR */
++
++ msg.data32 = (FRAME_SYNC_OFFSET << 16) | (FRAME_SYNC_SIZE - 1);
++ msg.index = 16;
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_FCR") != 0))
++ goto err_plat_close; /* 16: TX FCR */
++
++ msg.index = 20;
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_FCR") != 0))
++ goto err_plat_close; /* 20: RX FCR */
++
++ msg.data32 = 0; /* Fill LUT with HDLC timeslots */
++ for (i = 0; i < 32 / HSS_LUT_BITS; i++)
++ msg.data32 |= TDMMAP_HDLC << (HSS_LUT_BITS * i);
++
++ for (i = 0; i < 2 /* TX and RX */ * HSS_TIMESLOTS * HSS_LUT_BITS / 8;
++ i += 4) {
++ msg.index = 24 + i; /* 24 - 55: TX LUT, 56 - 87: RX LUT */
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_LUT") != 0))
++ goto err_plat_close;
++ }
++
++ /* HDLC mode configuration */
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_NUM_PIPES_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = PKT_NUM_PIPES;
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_PIPES") != 0))
++ goto err_plat_close;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = PKT_PIPE_FIFO_SIZEW;
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_FIFO") != 0))
++ goto err_plat_close;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
++ msg.hss_port = port->id;
++ msg.data32 = 0x7F7F7F7F;
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_IDLE") != 0))
++ goto err_plat_close;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PORT_CONFIG_LOAD;
++ msg.hss_port = port->id;
++ if ((err = npe_send_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
++ goto err_plat_close;
++ if ((err = npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
++ goto err_plat_close;
++
++ /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
++ if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
++ printk(KERN_DEBUG "%s: unexpected message received in"
++ " response to HSS_LOAD_CONFIG\n", npe_name(npe));
++ err = EIO;
++ goto err_plat_close;
++ }
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = port->hdlc_cfg; /* rx_cfg */
++ msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_HDLC_CFG") != 0))
++ goto err_plat_close;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_MODE_WRITE;
++ msg.hss_port = port->id;
++ msg.data8a = NPE_PKT_MODE_HDLC;
++ /* msg.data8b = inv_mask */
++ /* msg.data8c = or_mask */
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_MODE") != 0))
++ goto err_plat_close;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
++ msg.hss_port = port->id;
++ msg.data16a = HDLC_MAX_MRU;
++ if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_RX_SIZE") != 0))
++ goto err_plat_close;
++
++ if ((err = request_queues(port)) != 0)
++ goto err_plat_close;
++
++ if ((err = init_queues(port)) != 0)
++ goto err_destroy_queues;
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_FLOW_ENABLE;
++ msg.hss_port = port->id;
++ if ((err = npe_send_message(npe, &msg, "HSS_ENABLE_PKT_PIPE") != 0))
++ goto err_destroy_queues;
++
++ /* Populate queues with buffers, no failure after this point */
++ for (i = 0; i < TX_DESCS; i++)
++ queue_put_desc(port->plat->txreadyq,
++ tx_desc_phys(port, i), tx_desc_ptr(port, i));
++
++ for (i = 0; i < RX_DESCS; i++)
++ queue_put_desc(queue_ids[port->id].rxfree,
++ rx_desc_phys(port, i), rx_desc_ptr(port, i));
++
++ netif_start_queue(dev);
++
++ qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
++ hss_rx_irq, dev);
++
++ qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
++ hss_txdone_irq, dev);
++ qmgr_enable_irq(queue_ids[port->id].txdone);
++
++ ports_open++;
++ netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
++ return 0;
++
++err_destroy_queues:
++ destroy_queues(port);
++ release_queues(port);
++err_plat_close:
++ if (port->plat->close)
++ port->plat->close(port->id, port->netdev);
++err_hdlc_close:
++ hdlc_close(dev);
++ return err;
++}
++
++static int hss_close(struct net_device *dev)
++{
++ struct port *port = dev_to_port(dev);
++ struct npe *npe = port->npe;
++ struct msg msg;
++ int buffs = RX_DESCS; /* allocated RX buffers */
++ int i;
++
++ ports_open--;
++ qmgr_disable_irq(queue_ids[port->id].rx);
++ netif_stop_queue(dev);
++
++ memset(&msg, 0, sizeof(msg));
++ msg.cmd = PKT_PIPE_FLOW_DISABLE;
++ msg.hss_port = port->id;
++ if (npe_send_message(npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
++ printk(KERN_CRIT "HSS-%i: unable to stop HDLC flow\n",
++ port->id);
++ /* The upper level would ignore the error anyway */
++ }
++
++ while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
++ buffs--;
++ while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
++ buffs--;
++
++ if (buffs)
++ printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
++ " left in NPE\n", dev->name, buffs);
++
++ buffs = TX_DESCS;
++ while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
++ buffs--; /* cancel TX */
++
++ i = 0;
++ do {
++ while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
++ buffs--;
++ if (!buffs)
++ break;
++ } while (++i < MAX_CLOSE_WAIT);
++
++ if (buffs)
++ printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
++ "left in NPE\n", dev->name, buffs);
++#if DEBUG_CLOSE
++ if (!buffs)
++ printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
++#endif
++ qmgr_disable_irq(queue_ids[port->id].txdone);
++ destroy_queues(port);
++ release_queues(port);
++
++ if (port->plat->close)
++ port->plat->close(port->id, port->netdev);
++ hdlc_close(dev);
++ return 0;
++}
++
++
++static int hss_attach(struct net_device *dev, unsigned short encoding,
++ unsigned short parity)
++{
++ struct port *port = dev_to_port(dev);
++
++ if (encoding != ENCODING_NRZ)
++ return -EINVAL;
++
++ switch(parity) {
++ case PARITY_CRC16_PR1_CCITT:
++ port->hdlc_cfg = 0;
++ return 0;
++
++ case PARITY_CRC32_PR1_CCITT:
++ port->hdlc_cfg = PKT_HDLC_CRC_32;
++ return 0;
++
++ default:
++ return -EINVAL;
++ }
++}
++
++
++static int hss_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
++{
++ const size_t size = sizeof(sync_serial_settings);
++ sync_serial_settings new_line;
++ int clk;
++ sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
++ struct port *port = dev_to_port(dev);
++
++ if (cmd != SIOCWANDEV)
++ return hdlc_ioctl(dev, ifr, cmd);
++
++ switch(ifr->ifr_settings.type) {
++ case IF_GET_IFACE:
++ ifr->ifr_settings.type = IF_IFACE_V35;
++ if (ifr->ifr_settings.size < size) {
++ ifr->ifr_settings.size = size; /* data size wanted */
++ return -ENOBUFS;
++ }
++ if (copy_to_user(line, &port->settings, size))
++ return -EFAULT;
++ return 0;
++
++ case IF_IFACE_SYNC_SERIAL:
++ case IF_IFACE_V35:
++ if(!capable(CAP_NET_ADMIN))
++ return -EPERM;
++ if (dev->flags & IFF_UP)
++ return -EBUSY; /* Cannot change parameters when open */
++
++ if (copy_from_user(&new_line, line, size))
++ return -EFAULT;
++
++ clk = new_line.clock_type;
++ if (port->plat->set_clock)
++ clk = port->plat->set_clock(port->id, clk);
++
++ if (clk != CLOCK_EXT && clk != CLOCK_INT)
++ return -EINVAL; /* No such clock setting */
++
++ if (new_line.loopback != 0 && new_line.loopback != 1)
++ return -EINVAL;
++
++ memcpy(&port->settings, &new_line, size); /* Update settings */
++ return 0;
++
++ default:
++ return hdlc_ioctl(dev, ifr, cmd);
++ }
++}
++
++
++static int __devinit hss_init_one(struct platform_device *pdev)
++{
++ struct port *port;
++ struct net_device *dev;
++ hdlc_device *hdlc;
++ int err;
++
++ if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
++ return -ENOMEM;
++ platform_set_drvdata(pdev, port);
++ port->id = pdev->id;
++
++ if ((port->npe = npe_request(0)) == NULL) {
++ err = -ENOSYS;
++ goto err_free;
++ }
++
++ port->plat = pdev->dev.platform_data;
++ if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
++ err = -ENOMEM;
++ goto err_plat;
++ }
++
++ SET_MODULE_OWNER(net);
++ SET_NETDEV_DEV(dev, &pdev->dev);
++ hdlc = dev_to_hdlc(dev);
++ hdlc->attach = hss_attach;
++ hdlc->xmit = hss_xmit;
++ dev->open = hss_open;
++ dev->poll = hss_poll;
++ dev->stop = hss_close;
++ dev->do_ioctl = hss_ioctl;
++ dev->weight = 16;
++ dev->tx_queue_len = 100;
++ port->settings.clock_type = CLOCK_EXT;
++ port->settings.clock_rate = 2048000;
++
++ if (register_hdlc_device(dev)) {
++ printk(KERN_ERR "HSS-%i: unable to register HDLC device\n",
++ port->id);
++ err = -ENOBUFS;
++ goto err_free_netdev;
++ }
++ printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
++ return 0;
++
++err_free_netdev:
++ free_netdev(dev);
++err_plat:
++ npe_release(port->npe);
++ platform_set_drvdata(pdev, NULL);
++err_free:
++ kfree(port);
++ return err;
++}
++
++static int __devexit hss_remove_one(struct platform_device *pdev)
++{
++ struct port *port = platform_get_drvdata(pdev);
++
++ unregister_hdlc_device(port->netdev);
++ free_netdev(port->netdev);
++ npe_release(port->npe);
++ platform_set_drvdata(pdev, NULL);
++ kfree(port);
++ return 0;
++}
++
++static struct platform_driver drv = {
++ .driver.name = DRV_NAME,
++ .probe = hss_init_one,
++ .remove = hss_remove_one,
++};
++
++static int __init hss_init_module(void)
++{
++ if ((ixp4xx_read_fuses() & (IXP4XX_FUSE_HDLC | IXP4XX_FUSE_HSS)) !=
++ (IXP4XX_FUSE_HDLC | IXP4XX_FUSE_HSS))
++ return -ENOSYS;
++ return platform_driver_register(&drv);
++}
++
++static void __exit hss_cleanup_module(void)
++{
++ platform_driver_unregister(&drv);
++}
++
++MODULE_AUTHOR("Krzysztof Halasa");
++MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
++MODULE_LICENSE("GPL v2");
++module_init(hss_init_module);
++module_exit(hss_cleanup_module);
+diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/cpu.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/cpu.h
+--- linux-2.6.23/include/asm-arm/arch-ixp4xx/cpu.h 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/cpu.h 2007-10-22 19:20:22.000000000 +0200
+@@ -28,4 +28,19 @@
+ #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+ IXP465_PROCESSOR_ID_VALUE)
+
++static inline u32 ixp4xx_read_fuses(void)
++{
++ unsigned int fuses = ~*IXP4XX_EXP_CFG2;
++ fuses &= ~IXP4XX_FUSE_RESERVED;
++ if (!cpu_is_ixp46x())
++ fuses &= ~IXP4XX_FUSE_IXP46X_ONLY;
++
++ return fuses;
++}
++
++static inline void ixp4xx_write_fuses(u32 value)
++{
++ *IXP4XX_EXP_CFG2 = ~value;
++}
++
+ #endif /* _ASM_ARCH_CPU_H */
+diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/hardware.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/hardware.h
+--- linux-2.6.23/include/asm-arm/arch-ixp4xx/hardware.h 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/hardware.h 2007-10-22 19:20:22.000000000 +0200
+@@ -27,13 +27,13 @@
+
+ #define pcibios_assign_all_busses() 1
+
++/* Register locations and bits */
++#include "ixp4xx-regs.h"
++
+ #ifndef __ASSEMBLER__
+ #include <asm/arch/cpu.h>
+ #endif
+
+-/* Register locations and bits */
+-#include "ixp4xx-regs.h"
+-
+ /* Platform helper functions and definitions */
+ #include "platform.h"
+
+diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+--- linux-2.6.23/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h 2007-10-22 19:20:22.000000000 +0200
+@@ -607,4 +607,36 @@
+
+ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
+
++/* Fuse Bits of IXP_EXP_CFG2 */
++#define IXP4XX_FUSE_RCOMP (1 << 0)
++#define IXP4XX_FUSE_USB_DEVICE (1 << 1)
++#define IXP4XX_FUSE_HASH (1 << 2)
++#define IXP4XX_FUSE_AES (1 << 3)
++#define IXP4XX_FUSE_DES (1 << 4)
++#define IXP4XX_FUSE_HDLC (1 << 5)
++#define IXP4XX_FUSE_AAL (1 << 6)
++#define IXP4XX_FUSE_HSS (1 << 7)
++#define IXP4XX_FUSE_UTOPIA (1 << 8)
++#define IXP4XX_FUSE_NPEB_ETH0 (1 << 9)
++#define IXP4XX_FUSE_NPEC_ETH (1 << 10)
++#define IXP4XX_FUSE_RESET_NPEA (1 << 11)
++#define IXP4XX_FUSE_RESET_NPEB (1 << 12)
++#define IXP4XX_FUSE_RESET_NPEC (1 << 13)
++#define IXP4XX_FUSE_PCI (1 << 14)
++#define IXP4XX_FUSE_ECC_TIMESYNC (1 << 15)
++#define IXP4XX_FUSE_UTOPIA_PHY_LIMIT (3 << 16)
++#define IXP4XX_FUSE_USB_HOST (1 << 18)
++#define IXP4XX_FUSE_NPEA_ETH (1 << 19)
++#define IXP4XX_FUSE_NPEB_ETH_1_TO_3 (1 << 20)
++#define IXP4XX_FUSE_RSA (1 << 21)
++#define IXP4XX_FUSE_XSCALE_MAX_FREQ (3 << 22)
++#define IXP4XX_FUSE_RESERVED (0xFF << 24)
++
++#define IXP4XX_FUSE_IXP46X_ONLY (IXP4XX_FUSE_ECC_TIMESYNC | \
++ IXP4XX_FUSE_USB_HOST | \
++ IXP4XX_FUSE_NPEA_ETH | \
++ IXP4XX_FUSE_NPEB_ETH_1_TO_3 | \
++ IXP4XX_FUSE_RSA | \
++ IXP4XX_FUSE_XSCALE_MAX_FREQ)
++
+ #endif
+diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/npe.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/npe.h
+--- linux-2.6.23/include/asm-arm/arch-ixp4xx/npe.h 1970-01-01 01:00:00.000000000 +0100
++++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/npe.h 2007-10-22 19:20:22.000000000 +0200
+@@ -0,0 +1,41 @@
++#ifndef __IXP4XX_NPE_H
++#define __IXP4XX_NPE_H
++
++#include <linux/etherdevice.h>
++#include <linux/kernel.h>
++#include <asm/io.h>
++
++extern const char *npe_names[];
++
++struct npe_regs {
++ u32 exec_addr, exec_data, exec_status_cmd, exec_count;
++ u32 action_points[4];
++ u32 watchpoint_fifo, watch_count;
++ u32 profile_count;
++ u32 messaging_status, messaging_control;
++ u32 mailbox_status, /*messaging_*/ in_out_fifo;
++};
++
++struct npe {
++ struct resource *mem_res;
++ struct npe_regs __iomem *regs;
++ u32 regs_phys;
++ int id;
++ int valid;
++};
++
++
++static inline const char *npe_name(struct npe *npe)
++{
++ return npe_names[npe->id];
++}
++
++int npe_running(struct npe *npe);
++int npe_send_message(struct npe *npe, const void *msg, const char *what);
++int npe_recv_message(struct npe *npe, void *msg, const char *what);
++int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
++int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
++struct npe *npe_request(int id);
++void npe_release(struct npe *npe);
++
++#endif /* __IXP4XX_NPE_H */
+diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/platform.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/platform.h
+--- linux-2.6.23/include/asm-arm/arch-ixp4xx/platform.h 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/platform.h 2007-10-22 19:20:22.000000000 +0200
+@@ -77,8 +77,7 @@
+
+ /*
+ * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
+- * used to
+- * Used as platform_data to provide GPIO pin information to the ixp42x
++ * used as platform_data to provide GPIO pin information to the ixp42x
+ * I2C driver.
+ */
+ struct ixp4xx_i2c_pins {
+@@ -86,6 +85,27 @@
+ unsigned long scl_pin;
+ };
+
++#define IXP4XX_ETH_NPEA 0x00
++#define IXP4XX_ETH_NPEB 0x10
++#define IXP4XX_ETH_NPEC 0x20
++
++/* Information about built-in Ethernet MAC interfaces */
++struct eth_plat_info {
++ u8 phy; /* MII PHY ID, 0 - 31 */
++ u8 rxq; /* configurable, currently 0 - 31 only */
++ u8 txreadyq;
++ u8 hwaddr[6];
++};
++
++/* Information about built-in HSS (synchronous serial) interfaces */
++struct hss_plat_info {
++ int (*set_clock)(int port, unsigned int clock_type);
++ int (*open)(int port, void *pdev,
++ void (*set_carrier_cb)(void *pdev, int carrier));
++ void (*close)(int port, void *pdev);
++ u8 txreadyq;
++};
++
+ /*
+ * This structure provide a means for the board setup code
+ * to give information to th pata_ixp4xx driver. It is
+diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/qmgr.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/qmgr.h
+--- linux-2.6.23/include/asm-arm/arch-ixp4xx/qmgr.h 1970-01-01 01:00:00.000000000 +0100
++++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/qmgr.h 2007-10-22 19:20:22.000000000 +0200
+@@ -0,0 +1,124 @@
++/*
++ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License
++ * as published by the Free Software Foundation.
++ */
++
++#ifndef IXP4XX_QMGR_H
++#define IXP4XX_QMGR_H
++
++#include <linux/kernel.h>
++#include <asm/io.h>
++
++#define HALF_QUEUES 32
++#define QUEUES 64 /* only 32 lower queues currently supported */
++#define MAX_QUEUE_LENGTH 4 /* in dwords */
++
++#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
++#define QUEUE_STAT1_NEARLY_EMPTY 2
++#define QUEUE_STAT1_NEARLY_FULL 4
++#define QUEUE_STAT1_FULL 8
++#define QUEUE_STAT2_UNDERFLOW 1
++#define QUEUE_STAT2_OVERFLOW 2
++
++#define QUEUE_WATERMARK_0_ENTRIES 0
++#define QUEUE_WATERMARK_1_ENTRY 1
++#define QUEUE_WATERMARK_2_ENTRIES 2
++#define QUEUE_WATERMARK_4_ENTRIES 3
++#define QUEUE_WATERMARK_8_ENTRIES 4
++#define QUEUE_WATERMARK_16_ENTRIES 5
++#define QUEUE_WATERMARK_32_ENTRIES 6
++#define QUEUE_WATERMARK_64_ENTRIES 7
++
++/* queue interrupt request conditions */
++#define QUEUE_IRQ_SRC_EMPTY 0
++#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
++#define QUEUE_IRQ_SRC_NEARLY_FULL 2
++#define QUEUE_IRQ_SRC_FULL 3
++#define QUEUE_IRQ_SRC_NOT_EMPTY 4
++#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
++#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
++#define QUEUE_IRQ_SRC_NOT_FULL 7
++
++struct qmgr_regs {
++ u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
++ u32 stat1[4]; /* 0x400 - 0x40F */
++ u32 stat2[2]; /* 0x410 - 0x417 */
++ u32 statne_h; /* 0x418 - queue nearly empty */
++ u32 statf_h; /* 0x41C - queue full */
++ u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
++ u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
++ u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
++ u32 reserved[1776];
++ u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
++};
++
++extern struct qmgr_regs __iomem *qmgr_regs;
++
++void qmgr_set_irq(unsigned int queue, int src,
++ void (*handler)(void *pdev), void *pdev);
++void qmgr_enable_irq(unsigned int queue);
++void qmgr_disable_irq(unsigned int queue);
++
++/* request_ and release_queue() must be called from non-IRQ context */
++int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
++ unsigned int nearly_empty_watermark,
++ unsigned int nearly_full_watermark);
++void qmgr_release_queue(unsigned int queue);
++
++
++static inline void qmgr_put_entry(unsigned int queue, u32 val)
++{
++ __raw_writel(val, &qmgr_regs->acc[queue][0]);
++}
++
++static inline u32 qmgr_get_entry(unsigned int queue)
++{
++ return __raw_readl(&qmgr_regs->acc[queue][0]);
++}
++
++static inline int qmgr_get_stat1(unsigned int queue)
++{
++ return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
++ >> ((queue & 7) << 2)) & 0xF;
++}
++
++static inline int qmgr_get_stat2(unsigned int queue)
++{
++ return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
++ >> ((queue & 0xF) << 1)) & 0x3;
++}
++
++static inline int qmgr_stat_empty(unsigned int queue)
++{
++ return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
++}
++
++static inline int qmgr_stat_nearly_empty(unsigned int queue)
++{
++ return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
++}
++
++static inline int qmgr_stat_nearly_full(unsigned int queue)
++{
++ return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
++}
++
++static inline int qmgr_stat_full(unsigned int queue)
++{
++ return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
++}
++
++static inline int qmgr_stat_underflow(unsigned int queue)
++{
++ return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
++}
++
++static inline int qmgr_stat_overflow(unsigned int queue)
++{
++ return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
++}
++
++#endif
+diff -Nur -x .git -x .gitignore linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/uncompress.h
+--- linux-2.6.23/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-09 22:31:38.000000000 +0200
++++ ixp4xx-nep.git/include/asm-arm/arch-ixp4xx/uncompress.h 2007-10-22 19:20:22.000000000 +0200
+@@ -13,7 +13,8 @@
+ #ifndef _ARCH_UNCOMPRESS_H_
+ #define _ARCH_UNCOMPRESS_H_
+
+-#include <asm/hardware.h>
++#define __ASM_ARCH_HARDWARE_H__
++#include "ixp4xx-regs.h"
+ #include <asm/mach-types.h>
+ #include <linux/serial_reg.h>
+
--- /dev/null
+diff -Nur linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_npe.c linux-2.6.23-openwrt/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+--- linux-2.6.23/arch/arm/mach-ixp4xx/ixp4xx_npe.c 2007-10-22 22:18:15.000000000 +0200
++++ linux-2.6.23-openwrt/arch/arm/mach-ixp4xx/ixp4xx_npe.c 2007-10-22 22:32:48.000000000 +0200
+@@ -585,6 +585,8 @@
+ npe_reset(npe);
+ #endif
+
++ print_npe(KERN_INFO, npe, "firmware's license can be found in /usr/share/doc/LICENSE.IPL\n");
++
+ print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
+ "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
+ (image->id >> 8) & 0xFF, image->id & 0xFF);
projects / openwrt / staging / jow.git / commitdiff