source "drivers/staging/rtl8188eu/Kconfig"
-source "drivers/staging/rtlwifi/Kconfig"
-
source "drivers/staging/rts5208/Kconfig"
source "drivers/staging/octeon/Kconfig"
obj-$(CONFIG_RTL8723BS) += rtl8723bs/
obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_R8188EU) += rtl8188eu/
-obj-$(CONFIG_R8822BE) += rtlwifi/
obj-$(CONFIG_RTS5208) += rts5208/
obj-$(CONFIG_NETLOGIC_XLR_NET) += netlogic/
obj-$(CONFIG_OCTEON_ETHERNET) += octeon/
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-config R8822BE
- tristate "Realtek RTL8822BE Wireless Network Adapter"
- depends on PCI && MAC80211 && m
- select FW_LOADER
- help
- This is the staging driver for Realtek RTL8822BE 802.11ac PCIe
- wireless network adapters.
-
-config RTLWIFI_DEBUG_ST
- bool
- depends on R8822BE
- default y
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_R8822BE) += r8822be.o
-
-r8822be-objs := \
- base.o \
- cam.o \
- core.o \
- debug.o \
- efuse.o \
- ps.o \
- rc.o \
- regd.o \
- stats.o \
- pci.o \
- rtl8822be/fw.o \
- rtl8822be/hw.o \
- rtl8822be/led.o \
- rtl8822be/phy.o \
- rtl8822be/sw.o \
- rtl8822be/trx.o \
- btcoexist/halbtc8822b2ant.o \
- btcoexist/halbtc8822b1ant.o \
- btcoexist/halbtc8822bwifionly.o \
- btcoexist/halbtcoutsrc.o \
- btcoexist/rtl_btc.o \
- halmac/halmac_api.o \
- halmac/halmac_88xx/halmac_api_88xx_usb.o \
- halmac/halmac_88xx/halmac_api_88xx_sdio.o \
- halmac/halmac_88xx/halmac_api_88xx.o \
- halmac/halmac_88xx/halmac_api_88xx_pcie.o \
- halmac/halmac_88xx/halmac_func_88xx.o \
- halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.o \
- halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.o \
- halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.o \
- halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.o \
- halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.o \
- halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.o \
- halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.o \
- halmac/rtl_halmac.o \
- phydm/phydm_debug.o \
- phydm/phydm_antdiv.o\
- phydm/phydm_interface.o\
- phydm/phydm_hwconfig.o\
- phydm/phydm.o\
- phydm/halphyrf_ce.o\
- phydm/phydm_edcaturbocheck.o\
- phydm/phydm_dig.o\
- phydm/phydm_rainfo.o\
- phydm/phydm_dynamicbbpowersaving.o\
- phydm/phydm_powertracking_ce.o\
- phydm/phydm_dynamictxpower.o\
- phydm/phydm_adaptivity.o\
- phydm/phydm_cfotracking.o\
- phydm/phydm_noisemonitor.o\
- phydm/phydm_acs.o\
- phydm/phydm_psd.o\
- phydm/phydm_adc_sampling.o\
- phydm/phydm_kfree.o\
- phydm/phydm_ccx.o \
- phydm/rtl8822b/halhwimg8822b_bb.o\
- phydm/rtl8822b/halhwimg8822b_mac.o\
- phydm/rtl8822b/halhwimg8822b_rf.o\
- phydm/rtl8822b/halphyrf_8822b.o\
- phydm/rtl8822b/phydm_hal_api8822b.o\
- phydm/rtl8822b/phydm_iqk_8822b.o\
- phydm/rtl8822b/phydm_regconfig8822b.o\
- phydm/rtl8822b/phydm_rtl8822b.o \
- phydm/rtl_phydm.o
-
-
-obj-$(CONFIG_R8822BE) += rtl8822be/
+++ /dev/null
-TODO:
-- find and remove code blocks guarded by never set CONFIG_FOO defines
-- convert any remaining unusual variable types
-- find codes that can use %pM and %Nph formatting
-- checkpatch.pl fixes - most of the remaining ones are lines too long. Many
- of them will require refactoring
-- merge Realtek's bugfixes and new features into the driver
-- address any reviewers comments
-
-Please send any patches to Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
-and Larry Finger <Larry.Finger@lwfinger.net>.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "wifi.h"
-#include "rc.h"
-#include "base.h"
-#include "efuse.h"
-#include "cam.h"
-#include "ps.h"
-#include "regd.h"
-#include "pci.h"
-#include <linux/ip.h>
-#include <linux/module.h>
-#include <linux/udp.h>
-
-/*
- *NOTICE!!!: This file will be very big, we should
- *keep it clear under following roles:
- *
- *This file include following parts, so, if you add new
- *functions into this file, please check which part it
- *should includes. or check if you should add new part
- *for this file:
- *
- *1) mac80211 init functions
- *2) tx information functions
- *3) functions called by core.c
- *4) wq & timer callback functions
- *5) frame process functions
- *6) IOT functions
- *7) sysfs functions
- *8) vif functions
- *9) ...
- */
-
-/*********************************************************
- *
- * mac80211 init functions
- *
- *********************************************************/
-static struct ieee80211_channel rtl_channeltable_2g[] = {
- {.center_freq = 2412, .hw_value = 1,},
- {.center_freq = 2417, .hw_value = 2,},
- {.center_freq = 2422, .hw_value = 3,},
- {.center_freq = 2427, .hw_value = 4,},
- {.center_freq = 2432, .hw_value = 5,},
- {.center_freq = 2437, .hw_value = 6,},
- {.center_freq = 2442, .hw_value = 7,},
- {.center_freq = 2447, .hw_value = 8,},
- {.center_freq = 2452, .hw_value = 9,},
- {.center_freq = 2457, .hw_value = 10,},
- {.center_freq = 2462, .hw_value = 11,},
- {.center_freq = 2467, .hw_value = 12,},
- {.center_freq = 2472, .hw_value = 13,},
- {.center_freq = 2484, .hw_value = 14,},
-};
-
-static struct ieee80211_channel rtl_channeltable_5g[] = {
- {.center_freq = 5180, .hw_value = 36,},
- {.center_freq = 5200, .hw_value = 40,},
- {.center_freq = 5220, .hw_value = 44,},
- {.center_freq = 5240, .hw_value = 48,},
- {.center_freq = 5260, .hw_value = 52,},
- {.center_freq = 5280, .hw_value = 56,},
- {.center_freq = 5300, .hw_value = 60,},
- {.center_freq = 5320, .hw_value = 64,},
- {.center_freq = 5500, .hw_value = 100,},
- {.center_freq = 5520, .hw_value = 104,},
- {.center_freq = 5540, .hw_value = 108,},
- {.center_freq = 5560, .hw_value = 112,},
- {.center_freq = 5580, .hw_value = 116,},
- {.center_freq = 5600, .hw_value = 120,},
- {.center_freq = 5620, .hw_value = 124,},
- {.center_freq = 5640, .hw_value = 128,},
- {.center_freq = 5660, .hw_value = 132,},
- {.center_freq = 5680, .hw_value = 136,},
- {.center_freq = 5700, .hw_value = 140,},
- {.center_freq = 5745, .hw_value = 149,},
- {.center_freq = 5765, .hw_value = 153,},
- {.center_freq = 5785, .hw_value = 157,},
- {.center_freq = 5805, .hw_value = 161,},
- {.center_freq = 5825, .hw_value = 165,},
-};
-
-static struct ieee80211_rate rtl_ratetable_2g[] = {
- {.bitrate = 10, .hw_value = 0x00,},
- {.bitrate = 20, .hw_value = 0x01,},
- {.bitrate = 55, .hw_value = 0x02,},
- {.bitrate = 110, .hw_value = 0x03,},
- {.bitrate = 60, .hw_value = 0x04,},
- {.bitrate = 90, .hw_value = 0x05,},
- {.bitrate = 120, .hw_value = 0x06,},
- {.bitrate = 180, .hw_value = 0x07,},
- {.bitrate = 240, .hw_value = 0x08,},
- {.bitrate = 360, .hw_value = 0x09,},
- {.bitrate = 480, .hw_value = 0x0a,},
- {.bitrate = 540, .hw_value = 0x0b,},
-};
-
-static struct ieee80211_rate rtl_ratetable_5g[] = {
- {.bitrate = 60, .hw_value = 0x04,},
- {.bitrate = 90, .hw_value = 0x05,},
- {.bitrate = 120, .hw_value = 0x06,},
- {.bitrate = 180, .hw_value = 0x07,},
- {.bitrate = 240, .hw_value = 0x08,},
- {.bitrate = 360, .hw_value = 0x09,},
- {.bitrate = 480, .hw_value = 0x0a,},
- {.bitrate = 540, .hw_value = 0x0b,},
-};
-
-static const struct ieee80211_supported_band rtl_band_2ghz = {
- .band = NL80211_BAND_2GHZ,
-
- .channels = rtl_channeltable_2g,
- .n_channels = ARRAY_SIZE(rtl_channeltable_2g),
-
- .bitrates = rtl_ratetable_2g,
- .n_bitrates = ARRAY_SIZE(rtl_ratetable_2g),
-
- .ht_cap = {0},
-};
-
-static struct ieee80211_supported_band rtl_band_5ghz = {
- .band = NL80211_BAND_5GHZ,
-
- .channels = rtl_channeltable_5g,
- .n_channels = ARRAY_SIZE(rtl_channeltable_5g),
-
- .bitrates = rtl_ratetable_5g,
- .n_bitrates = ARRAY_SIZE(rtl_ratetable_5g),
-
- .ht_cap = {0},
-};
-
-static const u8 tid_to_ac[] = {
- 2, /* IEEE80211_AC_BE */
- 3, /* IEEE80211_AC_BK */
- 3, /* IEEE80211_AC_BK */
- 2, /* IEEE80211_AC_BE */
- 1, /* IEEE80211_AC_VI */
- 1, /* IEEE80211_AC_VI */
- 0, /* IEEE80211_AC_VO */
- 0, /* IEEE80211_AC_VO */
-};
-
-u8 rtl_tid_to_ac(u8 tid)
-{
- return tid_to_ac[tid];
-}
-
-static void _rtl_init_hw_ht_capab(struct ieee80211_hw *hw,
- struct ieee80211_sta_ht_cap *ht_cap)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
-
- ht_cap->ht_supported = true;
- ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
- IEEE80211_HT_CAP_SGI_40 |
- IEEE80211_HT_CAP_SGI_20 |
- IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU;
-
- if (rtlpriv->rtlhal.disable_amsdu_8k)
- ht_cap->cap &= ~IEEE80211_HT_CAP_MAX_AMSDU;
-
- /*
- *Maximum length of AMPDU that the STA can receive.
- *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets)
- */
- ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
-
- /*Minimum MPDU start spacing , */
- ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
-
- ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
-
- /*hw->wiphy->bands[NL80211_BAND_2GHZ]
- *base on ant_num
- *rx_mask: RX mask
- *if rx_ant = 1 rx_mask[0]= 0xff;==>MCS0-MCS7
- *if rx_ant = 2 rx_mask[1]= 0xff;==>MCS8-MCS15
- *if rx_ant >= 3 rx_mask[2]= 0xff;
- *if BW_40 rx_mask[4]= 0x01;
- *highest supported RX rate
- */
- if (rtlpriv->dm.supp_phymode_switch) {
- pr_info("Support phy mode switch\n");
-
- ht_cap->mcs.rx_mask[0] = 0xFF;
- ht_cap->mcs.rx_mask[1] = 0xFF;
- ht_cap->mcs.rx_mask[4] = 0x01;
-
- ht_cap->mcs.rx_highest = cpu_to_le16(MAX_BIT_RATE_40MHZ_MCS15);
- } else {
- if (get_rf_type(rtlphy) == RF_1T2R ||
- get_rf_type(rtlphy) == RF_2T2R) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "1T2R or 2T2R\n");
- ht_cap->mcs.rx_mask[0] = 0xFF;
- ht_cap->mcs.rx_mask[1] = 0xFF;
- ht_cap->mcs.rx_mask[4] = 0x01;
-
- ht_cap->mcs.rx_highest =
- cpu_to_le16(MAX_BIT_RATE_40MHZ_MCS15);
- } else if (get_rf_type(rtlphy) == RF_1T1R) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "1T1R\n");
-
- ht_cap->mcs.rx_mask[0] = 0xFF;
- ht_cap->mcs.rx_mask[1] = 0x00;
- ht_cap->mcs.rx_mask[4] = 0x01;
-
- ht_cap->mcs.rx_highest =
- cpu_to_le16(MAX_BIT_RATE_40MHZ_MCS7);
- }
- }
-}
-
-static void _rtl_init_hw_vht_capab(struct ieee80211_hw *hw,
- struct ieee80211_sta_vht_cap *vht_cap)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
-
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE ||
- rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
- u16 mcs_map;
-
- vht_cap->vht_supported = true;
- vht_cap->cap =
- IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
- IEEE80211_VHT_CAP_SHORT_GI_80 |
- IEEE80211_VHT_CAP_TXSTBC |
- IEEE80211_VHT_CAP_RXSTBC_1 |
- IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
- IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
- IEEE80211_VHT_CAP_HTC_VHT |
- IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
- IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN |
- IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN |
- 0;
-
- mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
- IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
-
- vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
- vht_cap->vht_mcs.rx_highest =
- cpu_to_le16(MAX_BIT_RATE_SHORT_GI_2NSS_80MHZ_MCS9);
- vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
- vht_cap->vht_mcs.tx_highest =
- cpu_to_le16(MAX_BIT_RATE_SHORT_GI_2NSS_80MHZ_MCS9);
- } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
- u16 mcs_map;
-
- vht_cap->vht_supported = true;
- vht_cap->cap =
- IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
- IEEE80211_VHT_CAP_SHORT_GI_80 |
- IEEE80211_VHT_CAP_TXSTBC |
- IEEE80211_VHT_CAP_RXSTBC_1 |
- IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
- IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
- IEEE80211_VHT_CAP_HTC_VHT |
- IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
- IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN |
- IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN |
- 0;
-
- mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 2 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
- IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
-
- vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
- vht_cap->vht_mcs.rx_highest =
- cpu_to_le16(MAX_BIT_RATE_SHORT_GI_1NSS_80MHZ_MCS9);
- vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
- vht_cap->vht_mcs.tx_highest =
- cpu_to_le16(MAX_BIT_RATE_SHORT_GI_1NSS_80MHZ_MCS9);
- }
-}
-
-static void _rtl_init_mac80211(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- struct ieee80211_supported_band *sband;
-
- if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
- rtlhal->bandset == BAND_ON_BOTH) {
- /* 1: 2.4 G bands */
- /* <1> use mac->bands as mem for hw->wiphy->bands */
- sband = &rtlmac->bands[NL80211_BAND_2GHZ];
-
- /* <2> set hw->wiphy->bands[NL80211_BAND_2GHZ]
- * to default value(1T1R)
- */
- memcpy(&rtlmac->bands[NL80211_BAND_2GHZ], &rtl_band_2ghz,
- sizeof(struct ieee80211_supported_band));
-
- /* <3> init ht cap base on ant_num */
- _rtl_init_hw_ht_capab(hw, &sband->ht_cap);
-
- /* <4> set mac->sband to wiphy->sband */
- hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
-
- /* 2: 5 G bands */
- /* <1> use mac->bands as mem for hw->wiphy->bands */
- sband = &rtlmac->bands[NL80211_BAND_5GHZ];
-
- /* <2> set hw->wiphy->bands[NL80211_BAND_5GHZ]
- * to default value(1T1R)
- */
- memcpy(&rtlmac->bands[NL80211_BAND_5GHZ], &rtl_band_5ghz,
- sizeof(struct ieee80211_supported_band));
-
- /* <3> init ht cap base on ant_num */
- _rtl_init_hw_ht_capab(hw, &sband->ht_cap);
-
- _rtl_init_hw_vht_capab(hw, &sband->vht_cap);
- /* <4> set mac->sband to wiphy->sband */
- hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
- } else {
- if (rtlhal->current_bandtype == BAND_ON_2_4G) {
- /* <1> use mac->bands as mem for hw->wiphy->bands */
- sband = &rtlmac->bands[NL80211_BAND_2GHZ];
-
- /* <2> set hw->wiphy->bands[NL80211_BAND_2GHZ]
- * to default value(1T1R)
- */
- memcpy(&rtlmac->bands[NL80211_BAND_2GHZ],
- &rtl_band_2ghz,
- sizeof(struct ieee80211_supported_band));
-
- /* <3> init ht cap base on ant_num */
- _rtl_init_hw_ht_capab(hw, &sband->ht_cap);
-
- /* <4> set mac->sband to wiphy->sband */
- hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
- } else if (rtlhal->current_bandtype == BAND_ON_5G) {
- /* <1> use mac->bands as mem for hw->wiphy->bands */
- sband = &rtlmac->bands[NL80211_BAND_5GHZ];
-
- /* <2> set hw->wiphy->bands[NL80211_BAND_5GHZ]
- * to default value(1T1R)
- */
- memcpy(&rtlmac->bands[NL80211_BAND_5GHZ],
- &rtl_band_5ghz,
- sizeof(struct ieee80211_supported_band));
-
- /* <3> init ht cap base on ant_num */
- _rtl_init_hw_ht_capab(hw, &sband->ht_cap);
-
- _rtl_init_hw_vht_capab(hw, &sband->vht_cap);
- /* <4> set mac->sband to wiphy->sband */
- hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
- } else {
- pr_err("Err BAND %d\n",
- rtlhal->current_bandtype);
- }
- }
- /* <5> set hw caps */
- ieee80211_hw_set(hw, SIGNAL_DBM);
- ieee80211_hw_set(hw, RX_INCLUDES_FCS);
- ieee80211_hw_set(hw, AMPDU_AGGREGATION);
- ieee80211_hw_set(hw, CONNECTION_MONITOR);
- ieee80211_hw_set(hw, MFP_CAPABLE);
- ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
- ieee80211_hw_set(hw, SUPPORTS_TX_FRAG);
- ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
- ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
-
- /* swlps or hwlps has been set in diff chip in init_sw_vars */
- if (rtlpriv->psc.swctrl_lps) {
- ieee80211_hw_set(hw, SUPPORTS_PS);
- ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
- }
- if (rtlpriv->psc.fwctrl_lps) {
- ieee80211_hw_set(hw, SUPPORTS_PS);
- ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
- }
- hw->wiphy->interface_modes =
- BIT(NL80211_IFTYPE_AP) |
- BIT(NL80211_IFTYPE_STATION) |
- BIT(NL80211_IFTYPE_ADHOC) |
- BIT(NL80211_IFTYPE_MESH_POINT) |
- BIT(NL80211_IFTYPE_P2P_CLIENT) |
- BIT(NL80211_IFTYPE_P2P_GO);
- hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
-
- hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
-
- hw->wiphy->rts_threshold = 2347;
-
- hw->queues = AC_MAX;
- hw->extra_tx_headroom = RTL_TX_HEADER_SIZE;
-
- /* TODO: Correct this value for our hw */
- hw->max_listen_interval = MAX_LISTEN_INTERVAL;
- hw->max_rate_tries = MAX_RATE_TRIES;
- /* hw->max_rates = 1; */
- hw->sta_data_size = sizeof(struct rtl_sta_info);
-
-/* wowlan is not supported by kernel if CONFIG_PM is not defined */
-#ifdef CONFIG_PM
- if (rtlpriv->psc.wo_wlan_mode) {
- if (rtlpriv->psc.wo_wlan_mode & WAKE_ON_MAGIC_PACKET)
- rtlpriv->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT;
- if (rtlpriv->psc.wo_wlan_mode & WAKE_ON_PATTERN_MATCH) {
- rtlpriv->wowlan.n_patterns =
- MAX_SUPPORT_WOL_PATTERN_NUM;
- rtlpriv->wowlan.pattern_min_len = MIN_WOL_PATTERN_SIZE;
- rtlpriv->wowlan.pattern_max_len = MAX_WOL_PATTERN_SIZE;
- }
- hw->wiphy->wowlan = &rtlpriv->wowlan;
- }
-#endif
-
- /* <6> mac address */
- if (is_valid_ether_addr(rtlefuse->dev_addr)) {
- SET_IEEE80211_PERM_ADDR(hw, rtlefuse->dev_addr);
- } else {
- u8 rtlmac1[] = { 0x00, 0xe0, 0x4c, 0x81, 0x92, 0x00 };
-
- get_random_bytes((rtlmac1 + (ETH_ALEN - 1)), 1);
- SET_IEEE80211_PERM_ADDR(hw, rtlmac1);
- }
-}
-
-static void _rtl_init_deferred_work(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- /* <1> timer */
- timer_setup(&rtlpriv->works.watchdog_timer,
- rtl_watch_dog_timer_callback, 0);
- timer_setup(&rtlpriv->works.dualmac_easyconcurrent_retrytimer,
- rtl_easy_concurrent_retrytimer_callback, 0);
- /* <2> work queue */
- rtlpriv->works.hw = hw;
- rtlpriv->works.rtl_wq = alloc_workqueue("%s", 0, 0, rtlpriv->cfg->name);
- INIT_DELAYED_WORK(&rtlpriv->works.watchdog_wq,
- (void *)rtl_watchdog_wq_callback);
- INIT_DELAYED_WORK(&rtlpriv->works.ips_nic_off_wq,
- (void *)rtl_ips_nic_off_wq_callback);
- INIT_DELAYED_WORK(&rtlpriv->works.ps_work,
- (void *)rtl_swlps_wq_callback);
- INIT_DELAYED_WORK(&rtlpriv->works.ps_rfon_wq,
- (void *)rtl_swlps_rfon_wq_callback);
- INIT_DELAYED_WORK(&rtlpriv->works.fwevt_wq,
- (void *)rtl_fwevt_wq_callback);
- INIT_DELAYED_WORK(&rtlpriv->works.c2hcmd_wq,
- (void *)rtl_c2hcmd_wq_callback);
-}
-
-void rtl_deinit_deferred_work(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- del_timer_sync(&rtlpriv->works.watchdog_timer);
-
- cancel_delayed_work(&rtlpriv->works.watchdog_wq);
- cancel_delayed_work(&rtlpriv->works.ips_nic_off_wq);
- cancel_delayed_work(&rtlpriv->works.ps_work);
- cancel_delayed_work(&rtlpriv->works.ps_rfon_wq);
- cancel_delayed_work(&rtlpriv->works.fwevt_wq);
- cancel_delayed_work(&rtlpriv->works.c2hcmd_wq);
-}
-
-void rtl_init_rfkill(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- bool radio_state;
- bool blocked;
- u8 valid = 0;
-
- /*set init state to on */
- rtlpriv->rfkill.rfkill_state = true;
- wiphy_rfkill_set_hw_state(hw->wiphy, 0);
-
- radio_state = rtlpriv->cfg->ops->radio_onoff_checking(hw, &valid);
-
- if (valid) {
- pr_info("rtlwifi: wireless switch is %s\n",
- rtlpriv->rfkill.rfkill_state ? "on" : "off");
-
- rtlpriv->rfkill.rfkill_state = radio_state;
-
- blocked = (rtlpriv->rfkill.rfkill_state == 1) ? 0 : 1;
- wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
- }
-
- wiphy_rfkill_start_polling(hw->wiphy);
-}
-
-void rtl_deinit_rfkill(struct ieee80211_hw *hw)
-{
- wiphy_rfkill_stop_polling(hw->wiphy);
-}
-
-int rtl_init_core(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
-
- /* <1> init mac80211 */
- _rtl_init_mac80211(hw);
- rtlmac->hw = hw;
-
- /* <2> rate control register */
- hw->rate_control_algorithm = "rtl_rc";
-
- /*
- * <3> init CRDA must come after init
- * mac80211 hw in _rtl_init_mac80211.
- */
- if (rtl_regd_init(hw, rtl_reg_notifier)) {
- pr_err("REGD init failed\n");
- return 1;
- }
-
- /* <4> locks */
- mutex_init(&rtlpriv->locks.conf_mutex);
- mutex_init(&rtlpriv->locks.ips_mutex);
- mutex_init(&rtlpriv->locks.lps_mutex);
- spin_lock_init(&rtlpriv->locks.irq_th_lock);
- spin_lock_init(&rtlpriv->locks.h2c_lock);
- spin_lock_init(&rtlpriv->locks.rf_ps_lock);
- spin_lock_init(&rtlpriv->locks.rf_lock);
- spin_lock_init(&rtlpriv->locks.waitq_lock);
- spin_lock_init(&rtlpriv->locks.entry_list_lock);
- spin_lock_init(&rtlpriv->locks.c2hcmd_lock);
- spin_lock_init(&rtlpriv->locks.scan_list_lock);
- spin_lock_init(&rtlpriv->locks.cck_and_rw_pagea_lock);
- spin_lock_init(&rtlpriv->locks.fw_ps_lock);
- spin_lock_init(&rtlpriv->locks.iqk_lock);
- /* <5> init list */
- INIT_LIST_HEAD(&rtlpriv->entry_list);
- INIT_LIST_HEAD(&rtlpriv->c2hcmd_list);
- INIT_LIST_HEAD(&rtlpriv->scan_list.list);
-
- rtlmac->link_state = MAC80211_NOLINK;
-
- /* <6> init deferred work */
- _rtl_init_deferred_work(hw);
-
- return 0;
-}
-
-static void rtl_free_entries_from_scan_list(struct ieee80211_hw *hw);
-
-void rtl_deinit_core(struct ieee80211_hw *hw)
-{
- rtl_c2hcmd_launcher(hw, 0);
- rtl_free_entries_from_scan_list(hw);
-}
-
-void rtl_init_rx_config(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-
- rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)&mac->rx_conf);
-}
-
-/*********************************************************
- *
- * tx information functions
- *
- *********************************************************/
-static void _rtl_qurey_shortpreamble_mode(struct ieee80211_hw *hw,
- struct rtl_tcb_desc *tcb_desc,
- struct ieee80211_tx_info *info)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 rate_flag = info->control.rates[0].flags;
-
- tcb_desc->use_shortpreamble = false;
-
- /* 1M can only use Long Preamble. 11B spec */
- if (tcb_desc->hw_rate == rtlpriv->cfg->maps[RTL_RC_CCK_RATE1M])
- return;
- else if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
- tcb_desc->use_shortpreamble = true;
-}
-
-static void _rtl_query_shortgi(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- struct rtl_tcb_desc *tcb_desc,
- struct ieee80211_tx_info *info)
-{
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- u8 rate_flag = info->control.rates[0].flags;
- u8 sgi_40 = 0, sgi_20 = 0, bw_40 = 0;
- u8 sgi_80 = 0, bw_80 = 0;
-
- tcb_desc->use_shortgi = false;
-
- if (!sta)
- return;
-
- sgi_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40;
- sgi_20 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20;
- sgi_80 = sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80;
-
- if (!sta->ht_cap.ht_supported && !sta->vht_cap.vht_supported)
- return;
-
- if (!sgi_40 && !sgi_20)
- return;
-
- if (mac->opmode == NL80211_IFTYPE_STATION) {
- bw_40 = mac->bw_40;
- bw_80 = mac->bw_80;
- } else if (mac->opmode == NL80211_IFTYPE_AP ||
- mac->opmode == NL80211_IFTYPE_ADHOC ||
- mac->opmode == NL80211_IFTYPE_MESH_POINT) {
- bw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
- bw_80 = sta->vht_cap.vht_supported;
- }
-
- if (bw_80) {
- if (sgi_80)
- tcb_desc->use_shortgi = true;
- else
- tcb_desc->use_shortgi = false;
- } else {
- if (bw_40 && sgi_40)
- tcb_desc->use_shortgi = true;
- else if (!bw_40 && sgi_20)
- tcb_desc->use_shortgi = true;
- }
-
- if (!(rate_flag & IEEE80211_TX_RC_SHORT_GI))
- tcb_desc->use_shortgi = false;
-}
-
-static void _rtl_query_protection_mode(struct ieee80211_hw *hw,
- struct rtl_tcb_desc *tcb_desc,
- struct ieee80211_tx_info *info)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 rate_flag = info->control.rates[0].flags;
-
- /* Common Settings */
- tcb_desc->rts_stbc = false;
- tcb_desc->cts_enable = false;
- tcb_desc->rts_sc = 0;
- tcb_desc->rts_bw = false;
- tcb_desc->rts_use_shortpreamble = false;
- tcb_desc->rts_use_shortgi = false;
-
- if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT) {
- /* Use CTS-to-SELF in protection mode. */
- tcb_desc->rts_enable = true;
- tcb_desc->cts_enable = true;
- tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M];
- } else if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
- /* Use RTS-CTS in protection mode. */
- tcb_desc->rts_enable = true;
- tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M];
- }
-}
-
-u8 rtl_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index,
- enum wireless_mode wirelessmode)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 ret = 0;
-
- switch (rate_index) {
- case RATR_INX_WIRELESS_NGB:
- if (rtlphy->rf_type == RF_1T1R)
- ret = RATEID_IDX_BGN_40M_1SS;
- else
- ret = RATEID_IDX_BGN_40M_2SS;
- break;
- case RATR_INX_WIRELESS_N:
- case RATR_INX_WIRELESS_NG:
- if (rtlphy->rf_type == RF_1T1R)
- ret = RATEID_IDX_GN_N1SS;
- else
- ret = RATEID_IDX_GN_N2SS;
- break;
- case RATR_INX_WIRELESS_NB:
- if (rtlphy->rf_type == RF_1T1R)
- ret = RATEID_IDX_BGN_20M_1SS_BN;
- else
- ret = RATEID_IDX_BGN_20M_2SS_BN;
- break;
- case RATR_INX_WIRELESS_GB:
- ret = RATEID_IDX_BG;
- break;
- case RATR_INX_WIRELESS_G:
- ret = RATEID_IDX_G;
- break;
- case RATR_INX_WIRELESS_B:
- ret = RATEID_IDX_B;
- break;
- case RATR_INX_WIRELESS_MC:
- if (wirelessmode == WIRELESS_MODE_B ||
- wirelessmode == WIRELESS_MODE_G ||
- wirelessmode == WIRELESS_MODE_N_24G ||
- wirelessmode == WIRELESS_MODE_AC_24G)
- ret = RATEID_IDX_BG;
- else
- ret = RATEID_IDX_G;
- break;
- case RATR_INX_WIRELESS_AC_5N:
- if (rtlphy->rf_type == RF_1T1R)
- ret = RATEID_IDX_VHT_1SS;
- else
- ret = RATEID_IDX_VHT_2SS;
- break;
- case RATR_INX_WIRELESS_AC_24N:
- if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
- if (rtlphy->rf_type == RF_1T1R)
- ret = RATEID_IDX_VHT_1SS;
- else
- ret = RATEID_IDX_VHT_2SS;
- } else {
- if (rtlphy->rf_type == RF_1T1R)
- ret = RATEID_IDX_MIX1;
- else
- ret = RATEID_IDX_MIX2;
- }
- break;
- default:
- ret = RATEID_IDX_BGN_40M_2SS;
- break;
- }
- return ret;
-}
-
-static inline u8 _rtl_rate_id(struct ieee80211_hw *hw,
- struct rtl_sta_info *sta_entry,
- int rate_index)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- if (rtlpriv->cfg->spec_ver & RTL_SPEC_NEW_RATEID) {
- int wireless_mode = sta_entry ?
- sta_entry->wireless_mode : WIRELESS_MODE_G;
-
- return rtl_mrate_idx_to_arfr_id(hw, rate_index, wireless_mode);
- } else {
- return rate_index;
- }
-}
-
-static void _rtl_txrate_selectmode(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- struct rtl_tcb_desc *tcb_desc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_sta_info *sta_entry = NULL;
- u8 ratr_index = _rtl_rate_id(hw, sta_entry, RATR_INX_WIRELESS_MC);
-
- if (sta) {
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- ratr_index = sta_entry->ratr_index;
- }
- if (!tcb_desc->disable_ratefallback || !tcb_desc->use_driver_rate) {
- if (mac->opmode == NL80211_IFTYPE_STATION) {
- tcb_desc->ratr_index = 0;
- } else if (mac->opmode == NL80211_IFTYPE_ADHOC ||
- mac->opmode == NL80211_IFTYPE_MESH_POINT) {
- if (tcb_desc->multicast || tcb_desc->broadcast) {
- tcb_desc->hw_rate =
- rtlpriv->cfg->maps[RTL_RC_CCK_RATE2M];
- tcb_desc->use_driver_rate = 1;
- tcb_desc->ratr_index =
- _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_MC);
- } else {
- tcb_desc->ratr_index = ratr_index;
- }
- } else if (mac->opmode == NL80211_IFTYPE_AP) {
- tcb_desc->ratr_index = ratr_index;
- }
- }
-
- if (rtlpriv->dm.useramask) {
- tcb_desc->ratr_index = ratr_index;
- /* TODO we will differentiate adhoc and station future */
- if (mac->opmode == NL80211_IFTYPE_STATION ||
- mac->opmode == NL80211_IFTYPE_MESH_POINT) {
- tcb_desc->mac_id = 0;
-
- if (sta &&
- (rtlpriv->cfg->spec_ver & RTL_SPEC_NEW_RATEID))
- ; /* use sta_entry->ratr_index */
- else if (mac->mode == WIRELESS_MODE_AC_5G)
- tcb_desc->ratr_index =
- _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_AC_5N);
- else if (mac->mode == WIRELESS_MODE_AC_24G)
- tcb_desc->ratr_index =
- _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_AC_24N);
- else if (mac->mode == WIRELESS_MODE_N_24G)
- tcb_desc->ratr_index =
- _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_NGB);
- else if (mac->mode == WIRELESS_MODE_N_5G)
- tcb_desc->ratr_index =
- _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_NG);
- else if (mac->mode & WIRELESS_MODE_G)
- tcb_desc->ratr_index =
- _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_GB);
- else if (mac->mode & WIRELESS_MODE_B)
- tcb_desc->ratr_index =
- _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_B);
- else if (mac->mode & WIRELESS_MODE_A)
- tcb_desc->ratr_index =
- _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_G);
-
- } else if (mac->opmode == NL80211_IFTYPE_AP ||
- mac->opmode == NL80211_IFTYPE_ADHOC) {
- if (sta) {
- if (sta->aid > 0)
- tcb_desc->mac_id = sta->aid + 1;
- else
- tcb_desc->mac_id = 1;
- } else {
- tcb_desc->mac_id = 0;
- }
- }
- }
-}
-
-static void _rtl_query_bandwidth_mode(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- struct rtl_tcb_desc *tcb_desc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-
- tcb_desc->packet_bw = false;
- if (!sta)
- return;
- if (mac->opmode == NL80211_IFTYPE_AP ||
- mac->opmode == NL80211_IFTYPE_ADHOC ||
- mac->opmode == NL80211_IFTYPE_MESH_POINT) {
- if (!(sta->ht_cap.ht_supported) ||
- !(sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40))
- return;
- } else if (mac->opmode == NL80211_IFTYPE_STATION) {
- if (!mac->bw_40 || !(sta->ht_cap.ht_supported))
- return;
- }
- if (tcb_desc->multicast || tcb_desc->broadcast)
- return;
-
- /*use legency rate, shall use 20MHz */
- if (tcb_desc->hw_rate <= rtlpriv->cfg->maps[RTL_RC_OFDM_RATE54M])
- return;
-
- tcb_desc->packet_bw = HT_CHANNEL_WIDTH_20_40;
-
- if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE ||
- rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8821AE ||
- (rtlpriv->cfg->spec_ver & RTL_SPEC_SUPPORT_VHT)) {
- if (mac->opmode == NL80211_IFTYPE_AP ||
- mac->opmode == NL80211_IFTYPE_ADHOC ||
- mac->opmode == NL80211_IFTYPE_MESH_POINT) {
- if (!(sta->vht_cap.vht_supported))
- return;
- } else if (mac->opmode == NL80211_IFTYPE_STATION) {
- if (!mac->bw_80 ||
- !(sta->vht_cap.vht_supported))
- return;
- }
- if (tcb_desc->hw_rate <=
- rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS15])
- return;
- tcb_desc->packet_bw = HT_CHANNEL_WIDTH_80;
- }
-}
-
-static u8 _rtl_get_vht_highest_n_rate(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 hw_rate;
- u16 tx_mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.tx_mcs_map);
-
- if ((get_rf_type(rtlphy) == RF_2T2R) &&
- (tx_mcs_map & 0x000c) != 0x000c) {
- if ((tx_mcs_map & 0x000c) >> 2 ==
- IEEE80211_VHT_MCS_SUPPORT_0_7)
- hw_rate =
- rtlpriv->cfg->maps[RTL_RC_VHT_RATE_2SS_MCS7];
- else if ((tx_mcs_map & 0x000c) >> 2 ==
- IEEE80211_VHT_MCS_SUPPORT_0_8)
- hw_rate =
- rtlpriv->cfg->maps[RTL_RC_VHT_RATE_2SS_MCS8];
- else
- hw_rate =
- rtlpriv->cfg->maps[RTL_RC_VHT_RATE_2SS_MCS9];
- } else {
- if ((tx_mcs_map & 0x0003) ==
- IEEE80211_VHT_MCS_SUPPORT_0_7)
- hw_rate =
- rtlpriv->cfg->maps[RTL_RC_VHT_RATE_1SS_MCS7];
- else if ((tx_mcs_map & 0x0003) ==
- IEEE80211_VHT_MCS_SUPPORT_0_8)
- hw_rate =
- rtlpriv->cfg->maps[RTL_RC_VHT_RATE_1SS_MCS8];
- else
- hw_rate =
- rtlpriv->cfg->maps[RTL_RC_VHT_RATE_1SS_MCS9];
- }
-
- return hw_rate;
-}
-
-static u8 _rtl_get_highest_n_rate(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 hw_rate;
-
- if (get_rf_type(rtlphy) == RF_2T2R &&
- sta->ht_cap.mcs.rx_mask[1] != 0)
- hw_rate = rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS15];
- else
- hw_rate = rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS7];
-
- return hw_rate;
-}
-
-/* mac80211's rate_idx is like this:
- *
- * 2.4G band:rx_status->band == NL80211_BAND_2GHZ
- *
- * B/G rate:
- * (rx_status->flag & RX_FLAG_HT) = 0,
- * DESC_RATE1M-->DESC_RATE54M ==> idx is 0-->11,
- *
- * N rate:
- * (rx_status->flag & RX_FLAG_HT) = 1,
- * DESC_RATEMCS0-->DESC_RATEMCS15 ==> idx is 0-->15
- *
- * 5G band:rx_status->band == NL80211_BAND_5GHZ
- * A rate:
- * (rx_status->flag & RX_FLAG_HT) = 0,
- * DESC_RATE6M-->DESC_RATE54M ==> idx is 0-->7,
- *
- * N rate:
- * (rx_status->flag & RX_FLAG_HT) = 1,
- * DESC_RATEMCS0-->DESC_RATEMCS15 ==> idx is 0-->15
- *
- * VHT rates:
- * DESC_RATEVHT1SS_MCS0-->DESC_RATEVHT1SS_MCS9 ==> idx is 0-->9
- * DESC_RATEVHT2SS_MCS0-->DESC_RATEVHT2SS_MCS9 ==> idx is 0-->9
- */
-int rtlwifi_rate_mapping(struct ieee80211_hw *hw, bool isht, bool isvht,
- u8 desc_rate)
-{
- int rate_idx;
-
- if (isvht) {
- switch (desc_rate) {
- case DESC_RATEVHT1SS_MCS0:
- rate_idx = 0;
- break;
- case DESC_RATEVHT1SS_MCS1:
- rate_idx = 1;
- break;
- case DESC_RATEVHT1SS_MCS2:
- rate_idx = 2;
- break;
- case DESC_RATEVHT1SS_MCS3:
- rate_idx = 3;
- break;
- case DESC_RATEVHT1SS_MCS4:
- rate_idx = 4;
- break;
- case DESC_RATEVHT1SS_MCS5:
- rate_idx = 5;
- break;
- case DESC_RATEVHT1SS_MCS6:
- rate_idx = 6;
- break;
- case DESC_RATEVHT1SS_MCS7:
- rate_idx = 7;
- break;
- case DESC_RATEVHT1SS_MCS8:
- rate_idx = 8;
- break;
- case DESC_RATEVHT1SS_MCS9:
- rate_idx = 9;
- break;
- case DESC_RATEVHT2SS_MCS0:
- rate_idx = 0;
- break;
- case DESC_RATEVHT2SS_MCS1:
- rate_idx = 1;
- break;
- case DESC_RATEVHT2SS_MCS2:
- rate_idx = 2;
- break;
- case DESC_RATEVHT2SS_MCS3:
- rate_idx = 3;
- break;
- case DESC_RATEVHT2SS_MCS4:
- rate_idx = 4;
- break;
- case DESC_RATEVHT2SS_MCS5:
- rate_idx = 5;
- break;
- case DESC_RATEVHT2SS_MCS6:
- rate_idx = 6;
- break;
- case DESC_RATEVHT2SS_MCS7:
- rate_idx = 7;
- break;
- case DESC_RATEVHT2SS_MCS8:
- rate_idx = 8;
- break;
- case DESC_RATEVHT2SS_MCS9:
- rate_idx = 9;
- break;
- default:
- rate_idx = 0;
- break;
- }
- return rate_idx;
- }
- if (!isht) {
- if (hw->conf.chandef.chan->band == NL80211_BAND_2GHZ) {
- switch (desc_rate) {
- case DESC_RATE1M:
- rate_idx = 0;
- break;
- case DESC_RATE2M:
- rate_idx = 1;
- break;
- case DESC_RATE5_5M:
- rate_idx = 2;
- break;
- case DESC_RATE11M:
- rate_idx = 3;
- break;
- case DESC_RATE6M:
- rate_idx = 4;
- break;
- case DESC_RATE9M:
- rate_idx = 5;
- break;
- case DESC_RATE12M:
- rate_idx = 6;
- break;
- case DESC_RATE18M:
- rate_idx = 7;
- break;
- case DESC_RATE24M:
- rate_idx = 8;
- break;
- case DESC_RATE36M:
- rate_idx = 9;
- break;
- case DESC_RATE48M:
- rate_idx = 10;
- break;
- case DESC_RATE54M:
- rate_idx = 11;
- break;
- default:
- rate_idx = 0;
- break;
- }
- } else {
- switch (desc_rate) {
- case DESC_RATE6M:
- rate_idx = 0;
- break;
- case DESC_RATE9M:
- rate_idx = 1;
- break;
- case DESC_RATE12M:
- rate_idx = 2;
- break;
- case DESC_RATE18M:
- rate_idx = 3;
- break;
- case DESC_RATE24M:
- rate_idx = 4;
- break;
- case DESC_RATE36M:
- rate_idx = 5;
- break;
- case DESC_RATE48M:
- rate_idx = 6;
- break;
- case DESC_RATE54M:
- rate_idx = 7;
- break;
- default:
- rate_idx = 0;
- break;
- }
- }
- } else {
- switch (desc_rate) {
- case DESC_RATEMCS0:
- rate_idx = 0;
- break;
- case DESC_RATEMCS1:
- rate_idx = 1;
- break;
- case DESC_RATEMCS2:
- rate_idx = 2;
- break;
- case DESC_RATEMCS3:
- rate_idx = 3;
- break;
- case DESC_RATEMCS4:
- rate_idx = 4;
- break;
- case DESC_RATEMCS5:
- rate_idx = 5;
- break;
- case DESC_RATEMCS6:
- rate_idx = 6;
- break;
- case DESC_RATEMCS7:
- rate_idx = 7;
- break;
- case DESC_RATEMCS8:
- rate_idx = 8;
- break;
- case DESC_RATEMCS9:
- rate_idx = 9;
- break;
- case DESC_RATEMCS10:
- rate_idx = 10;
- break;
- case DESC_RATEMCS11:
- rate_idx = 11;
- break;
- case DESC_RATEMCS12:
- rate_idx = 12;
- break;
- case DESC_RATEMCS13:
- rate_idx = 13;
- break;
- case DESC_RATEMCS14:
- rate_idx = 14;
- break;
- case DESC_RATEMCS15:
- rate_idx = 15;
- break;
- default:
- rate_idx = 0;
- break;
- }
- }
- return rate_idx;
-}
-
-static u8 _rtl_get_tx_hw_rate(struct ieee80211_hw *hw,
- struct ieee80211_tx_info *info)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_tx_rate *r = &info->status.rates[0];
- struct ieee80211_rate *txrate;
- u8 hw_value = 0x0;
-
- if (r->flags & IEEE80211_TX_RC_MCS) {
- /* HT MCS0-15 */
- hw_value = rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS15] - 15 +
- r->idx;
- } else if (r->flags & IEEE80211_TX_RC_VHT_MCS) {
- /* VHT MCS0-9, NSS */
- if (ieee80211_rate_get_vht_nss(r) == 2)
- hw_value = rtlpriv->cfg->maps[RTL_RC_VHT_RATE_2SS_MCS9];
- else
- hw_value = rtlpriv->cfg->maps[RTL_RC_VHT_RATE_1SS_MCS9];
-
- hw_value = hw_value - 9 + ieee80211_rate_get_vht_mcs(r);
- } else {
- /* legacy */
- txrate = ieee80211_get_tx_rate(hw, info);
-
- if (txrate)
- hw_value = txrate->hw_value;
- }
-
- /* check 5G band */
- if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G &&
- hw_value < rtlpriv->cfg->maps[RTL_RC_OFDM_RATE6M])
- hw_value = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE6M];
-
- return hw_value;
-}
-
-void rtl_get_tcb_desc(struct ieee80211_hw *hw,
- struct ieee80211_tx_info *info,
- struct ieee80211_sta *sta,
- struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
- struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
- struct rtl_sta_info *sta_entry =
- (sta ? (struct rtl_sta_info *)sta->drv_priv : NULL);
-
- __le16 fc = rtl_get_fc(skb);
-
- tcb_desc->hw_rate = _rtl_get_tx_hw_rate(hw, info);
-
- if (rtl_is_tx_report_skb(hw, skb))
- tcb_desc->use_spe_rpt = 1;
-
- if (!ieee80211_is_data(fc)) {
- tcb_desc->use_driver_rate = true;
- tcb_desc->ratr_index = _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_MC);
- tcb_desc->disable_ratefallback = 1;
- tcb_desc->mac_id = 0;
- tcb_desc->packet_bw = false;
-
- return;
- }
-
- /*
- * We set data rate INX 0
- * in rtl_rc.c if skb is special data or
- * mgt which need low data rate.
- */
-
- /*
- * So tcb_desc->hw_rate is just used for
- * special data and mgt frames
- */
- if (info->control.rates[0].idx == 0 || ieee80211_is_nullfunc(fc)) {
- tcb_desc->use_driver_rate = true;
- tcb_desc->ratr_index = _rtl_rate_id(hw, sta_entry,
- RATR_INX_WIRELESS_MC);
-
- tcb_desc->disable_ratefallback = 1;
- } else if (sta && sta->vht_cap.vht_supported) {
- /*
- * Because hw will never use hw_rate
- * when tcb_desc->use_driver_rate = false
- * so we never set highest N rate here,
- * and N rate will all be controlled by FW
- * when tcb_desc->use_driver_rate = false
- */
- tcb_desc->hw_rate = _rtl_get_vht_highest_n_rate(hw, sta);
- } else if (sta && sta->ht_cap.ht_supported) {
- tcb_desc->hw_rate = _rtl_get_highest_n_rate(hw, sta);
- } else {
- enum rtl_var_map var = RTL_RC_OFDM_RATE54M;
-
- if (rtlmac->mode == WIRELESS_MODE_B)
- var = RTL_RC_CCK_RATE11M;
-
- tcb_desc->hw_rate = rtlpriv->cfg->maps[var];
- }
-
- if (is_multicast_ether_addr(hdr->addr1))
- tcb_desc->multicast = 1;
- else if (is_broadcast_ether_addr(hdr->addr1))
- tcb_desc->broadcast = 1;
-
- _rtl_txrate_selectmode(hw, sta, tcb_desc);
- _rtl_query_bandwidth_mode(hw, sta, tcb_desc);
- _rtl_qurey_shortpreamble_mode(hw, tcb_desc, info);
- _rtl_query_shortgi(hw, sta, tcb_desc, info);
- _rtl_query_protection_mode(hw, tcb_desc, info);
-}
-
-bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- __le16 fc = rtl_get_fc(skb);
-
- if (rtlpriv->dm.supp_phymode_switch &&
- mac->link_state < MAC80211_LINKED &&
- (ieee80211_is_auth(fc) || ieee80211_is_probe_req(fc))) {
- if (rtlpriv->cfg->ops->chk_switch_dmdp)
- rtlpriv->cfg->ops->chk_switch_dmdp(hw);
- }
- if (ieee80211_is_auth(fc)) {
- RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n");
-
- mac->link_state = MAC80211_LINKING;
- /* Dul mac */
- rtlpriv->phy.need_iqk = true;
- }
- return true;
-}
-
-struct sk_buff *rtl_make_del_ba(struct ieee80211_hw *hw, u8 *sa,
- u8 *bssid, u16 tid);
-
-static void process_agg_start(struct ieee80211_hw *hw,
- struct ieee80211_hdr *hdr, u16 tid)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_rx_status rx_status = { 0 };
- struct sk_buff *skb_delba = NULL;
-
- skb_delba = rtl_make_del_ba(hw, hdr->addr2, hdr->addr3, tid);
- if (skb_delba) {
- rx_status.freq = hw->conf.chandef.chan->center_freq;
- rx_status.band = hw->conf.chandef.chan->band;
- rx_status.flag |= RX_FLAG_DECRYPTED;
- rx_status.flag |= RX_FLAG_MACTIME_START;
- rx_status.rate_idx = 0;
- rx_status.signal = 50 + 10;
- memcpy(IEEE80211_SKB_RXCB(skb_delba),
- &rx_status, sizeof(rx_status));
- RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG,
- "fake del\n",
- skb_delba->data,
- skb_delba->len);
- ieee80211_rx_irqsafe(hw, skb_delba);
- }
-}
-
-bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
-{
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- __le16 fc = rtl_get_fc(skb);
- u8 *act = (u8 *)(((u8 *)skb->data + MAC80211_3ADDR_LEN));
- u8 category;
-
- if (!ieee80211_is_action(fc))
- return true;
-
- category = *act;
- act++;
- switch (category) {
- case ACT_CAT_BA:
- switch (*act) {
- case ACT_ADDBAREQ:
- if (mac->act_scanning)
- return false;
-
- RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
- "%s ACT_ADDBAREQ From :%pM\n",
- is_tx ? "Tx" : "Rx", hdr->addr2);
- RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "req\n",
- skb->data, skb->len);
- if (!is_tx) {
- struct ieee80211_sta *sta = NULL;
- struct rtl_sta_info *sta_entry = NULL;
- struct rtl_tid_data *tid_data;
- struct ieee80211_mgmt *mgmt = (void *)skb->data;
- u16 capab = 0, tid = 0;
-
- rcu_read_lock();
- sta = rtl_find_sta(hw, hdr->addr3);
- if (!sta) {
- RT_TRACE(rtlpriv, COMP_SEND | COMP_RECV,
- DBG_DMESG, "sta is NULL\n");
- rcu_read_unlock();
- return true;
- }
-
- sta_entry =
- (struct rtl_sta_info *)sta->drv_priv;
- if (!sta_entry) {
- rcu_read_unlock();
- return true;
- }
- capab =
- le16_to_cpu(mgmt->u.action.u.addba_req.capab);
- tid = (capab &
- IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
- if (tid >= MAX_TID_COUNT) {
- rcu_read_unlock();
- return true;
- }
- tid_data = &sta_entry->tids[tid];
- if (tid_data->agg.rx_agg_state ==
- RTL_RX_AGG_START)
- process_agg_start(hw, hdr, tid);
- rcu_read_unlock();
- }
- break;
- case ACT_ADDBARSP:
- RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
- "%s ACT_ADDBARSP From :%pM\n",
- is_tx ? "Tx" : "Rx", hdr->addr2);
- break;
- case ACT_DELBA:
- RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
- "ACT_ADDBADEL From :%pM\n", hdr->addr2);
- break;
- }
- break;
- default:
- break;
- }
-
- return true;
-}
-
-static void setup_special_tx(struct rtl_priv *rtlpriv, struct rtl_ps_ctl *ppsc,
- int type)
-{
- struct ieee80211_hw *hw = rtlpriv->hw;
-
- rtlpriv->ra.is_special_data = true;
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_special_packet_notify(rtlpriv,
- type);
- rtl_lps_leave(hw);
- ppsc->last_delaylps_stamp_jiffies = jiffies;
-}
-
-static const u8 *rtl_skb_ether_type_ptr(struct ieee80211_hw *hw,
- struct sk_buff *skb, bool is_enc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 mac_hdr_len = ieee80211_get_hdrlen_from_skb(skb);
- u8 encrypt_header_len = 0;
- u8 offset;
-
- switch (rtlpriv->sec.pairwise_enc_algorithm) {
- case WEP40_ENCRYPTION:
- case WEP104_ENCRYPTION:
- encrypt_header_len = 4;/*WEP_IV_LEN*/
- break;
- case TKIP_ENCRYPTION:
- encrypt_header_len = 8;/*TKIP_IV_LEN*/
- break;
- case AESCCMP_ENCRYPTION:
- encrypt_header_len = 8;/*CCMP_HDR_LEN;*/
- break;
- default:
- break;
- }
-
- offset = mac_hdr_len + SNAP_SIZE;
- if (is_enc)
- offset += encrypt_header_len;
-
- return skb->data + offset;
-}
-
-/*should call before software enc*/
-u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx,
- bool is_enc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- __le16 fc = rtl_get_fc(skb);
- u16 ether_type;
- const u8 *ether_type_ptr;
- const struct iphdr *ip;
-
- if (!ieee80211_is_data(fc))
- goto end;
-
- ether_type_ptr = rtl_skb_ether_type_ptr(hw, skb, is_enc);
- ether_type = be16_to_cpup((__be16 *)ether_type_ptr);
-
- if (ether_type == ETH_P_IP) {
- ip = (struct iphdr *)((u8 *)ether_type_ptr +
- PROTOC_TYPE_SIZE);
- if (ip->protocol == IPPROTO_UDP) {
- struct udphdr *udp = (struct udphdr *)((u8 *)ip +
- (ip->ihl << 2));
- if (((((u8 *)udp)[1] == 68) &&
- (((u8 *)udp)[3] == 67)) ||
- ((((u8 *)udp)[1] == 67) &&
- (((u8 *)udp)[3] == 68))) {
- /* 68 : UDP BOOTP client
- * 67 : UDP BOOTP server
- */
- RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV),
- DBG_DMESG, "dhcp %s !!\n",
- (is_tx) ? "Tx" : "Rx");
-
- if (is_tx)
- setup_special_tx(rtlpriv, ppsc,
- PACKET_DHCP);
-
- return true;
- }
- }
- } else if (ether_type == ETH_P_ARP) {
- if (is_tx)
- setup_special_tx(rtlpriv, ppsc, PACKET_ARP);
-
- return true;
- } else if (ether_type == ETH_P_PAE) {
- /* EAPOL is seen as in-4way */
- rtlpriv->btcoexist.btc_info.in_4way = true;
- rtlpriv->btcoexist.btc_info.in_4way_ts = jiffies;
- rtlpriv->btcoexist.btc_info.in_4way_ts = jiffies;
-
- RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
- "802.1X %s EAPOL pkt!!\n", (is_tx) ? "Tx" : "Rx");
-
- if (is_tx) {
- rtlpriv->ra.is_special_data = true;
- rtl_lps_leave(hw);
- ppsc->last_delaylps_stamp_jiffies = jiffies;
-
- setup_special_tx(rtlpriv, ppsc, PACKET_EAPOL);
- }
-
- return true;
- } else if (ether_type == ETH_P_IPV6) {
- /* TODO: Handle any IPv6 cases that need special handling.
- * For now, always return false
- */
- goto end;
- }
-
-end:
- rtlpriv->ra.is_special_data = false;
- return false;
-}
-
-bool rtl_is_tx_report_skb(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
- u16 ether_type;
- const u8 *ether_type_ptr;
-
- ether_type_ptr = rtl_skb_ether_type_ptr(hw, skb, true);
- ether_type = be16_to_cpup((__be16 *)ether_type_ptr);
-
- /* EAPOL */
- if (ether_type == ETH_P_PAE)
- return true;
-
- return false;
-}
-
-static u16 rtl_get_tx_report_sn(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_tx_report *tx_report = &rtlpriv->tx_report;
- u16 sn;
-
- /*
- * SW_DEFINE[11:8] are reserved (driver fills zeros)
- * SW_DEFINE[7:2] are used by driver
- * SW_DEFINE[1:0] are reserved for firmware (driver fills zeros)
- */
- sn = (atomic_inc_return(&tx_report->sn) & 0x003F) << 2;
-
- tx_report->last_sent_sn = sn;
- tx_report->last_sent_time = jiffies;
-
- RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_DMESG,
- "Send TX-Report sn=0x%X\n", sn);
-
- return sn;
-}
-
-void rtl_get_tx_report(struct rtl_tcb_desc *ptcb_desc, u8 *pdesc,
- struct ieee80211_hw *hw)
-{
- if (ptcb_desc->use_spe_rpt) {
- u16 sn = rtl_get_tx_report_sn(hw);
-
- SET_TX_DESC_SPE_RPT(pdesc, 1);
- SET_TX_DESC_SW_DEFINE(pdesc, sn);
- }
-}
-
-void rtl_tx_report_handler(struct ieee80211_hw *hw, u8 *tmp_buf, u8 c2h_cmd_len)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_tx_report *tx_report = &rtlpriv->tx_report;
- u16 sn;
- u8 st, retry;
-
- if (rtlpriv->cfg->spec_ver & RTL_SPEC_NEW_FW_C2H) {
- sn = tmp_buf[6];
- st = tmp_buf[7] & 0xC0;
- retry = tmp_buf[8] & 0x3F;
- } else {
- sn = ((tmp_buf[7] & 0x0F) << 8) | tmp_buf[6];
- st = tmp_buf[0] & 0xC0;
- retry = tmp_buf[2] & 0x3F;
- }
-
- tx_report->last_recv_sn = sn;
-
- RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_DMESG,
- "Recv TX-Report st=0x%02X sn=0x%X retry=0x%X\n",
- st, sn, retry);
-}
-
-bool rtl_check_tx_report_acked(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_tx_report *tx_report = &rtlpriv->tx_report;
-
- if (tx_report->last_sent_sn == tx_report->last_recv_sn)
- return true;
-
- if (time_before(tx_report->last_sent_time + 3 * HZ, jiffies)) {
- RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_WARNING,
- "Check TX-Report timeout!! s_sn=0x%X r_sn=0x%X\n",
- tx_report->last_sent_sn, tx_report->last_recv_sn);
- return true; /* 3 sec. (timeout) seen as acked */
- }
-
- return false;
-}
-
-void rtl_wait_tx_report_acked(struct ieee80211_hw *hw, u32 wait_ms)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- int i;
-
- for (i = 0; i < wait_ms; i++) {
- if (rtl_check_tx_report_acked(hw))
- break;
- usleep_range(1000, 2000);
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "Wait 1ms (%d/%d) to disable key.\n", i, wait_ms);
- }
-}
-
-u32 rtl_get_hal_edca_param(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- enum wireless_mode wirelessmode,
- struct ieee80211_tx_queue_params *param)
-{
- u32 reg = 0;
- u8 sifstime = 10;
- u8 slottime = 20;
-
- /* AIFS = AIFSN * slot time + SIFS */
- switch (wirelessmode) {
- case WIRELESS_MODE_A:
- case WIRELESS_MODE_N_24G:
- case WIRELESS_MODE_N_5G:
- case WIRELESS_MODE_AC_5G:
- case WIRELESS_MODE_AC_24G:
- sifstime = 16;
- slottime = 9;
- break;
- case WIRELESS_MODE_G:
- slottime = (vif->bss_conf.use_short_slot ? 9 : 20);
- break;
- default:
- break;
- }
-
- reg |= (param->txop & 0x7FF) << 16;
- reg |= (fls(param->cw_max) & 0xF) << 12;
- reg |= (fls(param->cw_min) & 0xF) << 8;
- reg |= (param->aifs & 0x0F) * slottime + sifstime;
-
- return reg;
-}
-
-/*********************************************************
- *
- * functions called by core.c
- *
- *********************************************************/
-int rtl_tx_agg_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
- struct ieee80211_sta *sta, u16 tid, u16 *ssn)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_tid_data *tid_data;
- struct rtl_sta_info *sta_entry = NULL;
-
- if (!sta)
- return -EINVAL;
-
- if (unlikely(tid >= MAX_TID_COUNT))
- return -EINVAL;
-
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- if (!sta_entry)
- return -ENXIO;
- tid_data = &sta_entry->tids[tid];
-
- RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG,
- "on ra = %pM tid = %d seq:%d\n", sta->addr, tid,
- tid_data->seq_number);
-
- *ssn = tid_data->seq_number;
- tid_data->agg.agg_state = RTL_AGG_START;
-
- ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
- return 0;
-}
-
-int rtl_tx_agg_stop(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
- struct ieee80211_sta *sta, u16 tid)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_sta_info *sta_entry = NULL;
-
- if (!sta)
- return -EINVAL;
-
- RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG,
- "on ra = %pM tid = %d\n", sta->addr, tid);
-
- if (unlikely(tid >= MAX_TID_COUNT))
- return -EINVAL;
-
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- sta_entry->tids[tid].agg.agg_state = RTL_AGG_STOP;
-
- ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
- return 0;
-}
-
-int rtl_rx_agg_start(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u16 tid)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_tid_data *tid_data;
- struct rtl_sta_info *sta_entry = NULL;
- u8 reject_agg;
-
- if (!sta)
- return -EINVAL;
-
- if (unlikely(tid >= MAX_TID_COUNT))
- return -EINVAL;
-
- if (rtlpriv->cfg->ops->get_btc_status()) {
- rtlpriv->btcoexist.btc_ops->btc_get_ampdu_cfg(rtlpriv,
- &reject_agg,
- NULL, NULL);
- if (reject_agg)
- return -EINVAL;
- }
-
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- if (!sta_entry)
- return -ENXIO;
- tid_data = &sta_entry->tids[tid];
-
- RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
- "on ra = %pM tid = %d seq:%d\n", sta->addr, tid,
- tid_data->seq_number);
-
- tid_data->agg.rx_agg_state = RTL_RX_AGG_START;
- return 0;
-}
-
-int rtl_rx_agg_stop(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u16 tid)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_sta_info *sta_entry = NULL;
-
- if (!sta)
- return -EINVAL;
-
- RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG,
- "on ra = %pM tid = %d\n", sta->addr, tid);
-
- if (unlikely(tid >= MAX_TID_COUNT))
- return -EINVAL;
-
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- sta_entry->tids[tid].agg.rx_agg_state = RTL_RX_AGG_STOP;
-
- return 0;
-}
-
-int rtl_tx_agg_oper(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u16 tid)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_sta_info *sta_entry = NULL;
-
- if (!sta)
- return -EINVAL;
-
- RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG,
- "on ra = %pM tid = %d\n", sta->addr, tid);
-
- if (unlikely(tid >= MAX_TID_COUNT))
- return -EINVAL;
-
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- sta_entry->tids[tid].agg.agg_state = RTL_AGG_OPERATIONAL;
-
- return 0;
-}
-
-void rtl_rx_ampdu_apply(struct rtl_priv *rtlpriv)
-{
- struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
- u8 reject_agg = 0, ctrl_agg_size = 0, agg_size = 0;
-
- if (rtlpriv->cfg->ops->get_btc_status())
- btc_ops->btc_get_ampdu_cfg(rtlpriv, &reject_agg,
- &ctrl_agg_size, &agg_size);
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
- "Set RX AMPDU: coex - reject=%d, ctrl_agg_size=%d, size=%d",
- reject_agg, ctrl_agg_size, agg_size);
-
- rtlpriv->hw->max_rx_aggregation_subframes =
- (ctrl_agg_size ? agg_size : IEEE80211_MAX_AMPDU_BUF_HT);
-}
-
-/*********************************************************
- *
- * wq & timer callback functions
- *
- *********************************************************/
-/* this function is used for roaming */
-void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
-
- if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
- return;
-
- if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
- return;
-
- /* check if this really is a beacon */
- if (!ieee80211_is_beacon(hdr->frame_control) &&
- !ieee80211_is_probe_resp(hdr->frame_control))
- return;
-
- /* min. beacon length + FCS_LEN */
- if (skb->len <= 40 + FCS_LEN)
- return;
-
- /* and only beacons from the associated BSSID, please */
- if (!ether_addr_equal(hdr->addr3, rtlpriv->mac80211.bssid))
- return;
-
- rtlpriv->link_info.bcn_rx_inperiod++;
-}
-
-static void rtl_free_entries_from_scan_list(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_bssid_entry *entry, *next;
-
- list_for_each_entry_safe(entry, next, &rtlpriv->scan_list.list, list) {
- list_del(&entry->list);
- kfree(entry);
- rtlpriv->scan_list.num--;
- }
-}
-
-void rtl_scan_list_expire(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_bssid_entry *entry, *next;
- unsigned long flags;
-
- spin_lock_irqsave(&rtlpriv->locks.scan_list_lock, flags);
-
- list_for_each_entry_safe(entry, next, &rtlpriv->scan_list.list, list) {
- /* 180 seconds */
- if (jiffies_to_msecs(jiffies - entry->age) < 180000)
- continue;
-
- list_del(&entry->list);
- rtlpriv->scan_list.num--;
-
- RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
- "BSSID=%pM is expire in scan list (total=%d)\n",
- entry->bssid, rtlpriv->scan_list.num);
- kfree(entry);
- }
-
- spin_unlock_irqrestore(&rtlpriv->locks.scan_list_lock, flags);
-
- rtlpriv->btcoexist.btc_info.ap_num = rtlpriv->scan_list.num;
-}
-
-void rtl_collect_scan_list(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- unsigned long flags;
-
- struct rtl_bssid_entry *entry;
- bool entry_found = false;
-
- /* check if it is scanning */
- if (!mac->act_scanning)
- return;
-
- /* check if this really is a beacon */
- if (!ieee80211_is_beacon(hdr->frame_control) &&
- !ieee80211_is_probe_resp(hdr->frame_control))
- return;
-
- spin_lock_irqsave(&rtlpriv->locks.scan_list_lock, flags);
-
- list_for_each_entry(entry, &rtlpriv->scan_list.list, list) {
- if (memcmp(entry->bssid, hdr->addr3, ETH_ALEN) == 0) {
- list_del_init(&entry->list);
- entry_found = true;
- RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
- "Update BSSID=%pM to scan list (total=%d)\n",
- hdr->addr3, rtlpriv->scan_list.num);
- break;
- }
- }
-
- if (!entry_found) {
- entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
-
- if (!entry)
- goto label_err;
-
- memcpy(entry->bssid, hdr->addr3, ETH_ALEN);
- rtlpriv->scan_list.num++;
-
- RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
- "Add BSSID=%pM to scan list (total=%d)\n",
- hdr->addr3, rtlpriv->scan_list.num);
- }
-
- entry->age = jiffies;
-
- list_add_tail(&entry->list, &rtlpriv->scan_list.list);
-
-label_err:
- spin_unlock_irqrestore(&rtlpriv->locks.scan_list_lock, flags);
-}
-
-void rtl_watchdog_wq_callback(void *data)
-{
- struct rtl_works *rtlworks = container_of_dwork_rtl(data,
- struct rtl_works,
- watchdog_wq);
- struct ieee80211_hw *hw = rtlworks->hw;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- bool busytraffic = false;
- bool tx_busy_traffic = false;
- bool rx_busy_traffic = false;
- bool higher_busytraffic = false;
- bool higher_busyrxtraffic = false;
- u8 idx, tid;
- u32 rx_cnt_inp4eriod = 0;
- u32 tx_cnt_inp4eriod = 0;
- u32 aver_rx_cnt_inperiod = 0;
- u32 aver_tx_cnt_inperiod = 0;
- u32 aver_tidtx_inperiod[MAX_TID_COUNT] = {0};
- u32 tidtx_inp4eriod[MAX_TID_COUNT] = {0};
-
- if (is_hal_stop(rtlhal))
- return;
-
- /* <1> Determine if action frame is allowed */
- if (mac->link_state > MAC80211_NOLINK) {
- if (mac->cnt_after_linked < 20)
- mac->cnt_after_linked++;
- } else {
- mac->cnt_after_linked = 0;
- }
-
- /* <2> to check if traffic busy, if
- * busytraffic we don't change channel
- */
- if (mac->link_state >= MAC80211_LINKED) {
- /* (1) get aver_rx_cnt_inperiod & aver_tx_cnt_inperiod */
- for (idx = 0; idx <= 2; idx++) {
- rtlpriv->link_info.num_rx_in4period[idx] =
- rtlpriv->link_info.num_rx_in4period[idx + 1];
- rtlpriv->link_info.num_tx_in4period[idx] =
- rtlpriv->link_info.num_tx_in4period[idx + 1];
- }
- rtlpriv->link_info.num_rx_in4period[3] =
- rtlpriv->link_info.num_rx_inperiod;
- rtlpriv->link_info.num_tx_in4period[3] =
- rtlpriv->link_info.num_tx_inperiod;
- for (idx = 0; idx <= 3; idx++) {
- rx_cnt_inp4eriod +=
- rtlpriv->link_info.num_rx_in4period[idx];
- tx_cnt_inp4eriod +=
- rtlpriv->link_info.num_tx_in4period[idx];
- }
- aver_rx_cnt_inperiod = rx_cnt_inp4eriod / 4;
- aver_tx_cnt_inperiod = tx_cnt_inp4eriod / 4;
-
- /* (2) check traffic busy */
- if (aver_rx_cnt_inperiod > 100 || aver_tx_cnt_inperiod > 100) {
- busytraffic = true;
- if (aver_rx_cnt_inperiod > aver_tx_cnt_inperiod)
- rx_busy_traffic = true;
- else
- tx_busy_traffic = false;
- }
-
- /* Higher Tx/Rx data. */
- if (aver_rx_cnt_inperiod > 4000 ||
- aver_tx_cnt_inperiod > 4000) {
- higher_busytraffic = true;
-
- /* Extremely high Rx data. */
- if (aver_rx_cnt_inperiod > 5000)
- higher_busyrxtraffic = true;
- }
-
- /* check every tid's tx traffic */
- for (tid = 0; tid <= 7; tid++) {
- for (idx = 0; idx <= 2; idx++)
- rtlpriv->link_info.tidtx_in4period[tid][idx] =
- rtlpriv->link_info.tidtx_in4period[tid]
- [idx + 1];
- rtlpriv->link_info.tidtx_in4period[tid][3] =
- rtlpriv->link_info.tidtx_inperiod[tid];
-
- for (idx = 0; idx <= 3; idx++)
- tidtx_inp4eriod[tid] +=
- rtlpriv->link_info.tidtx_in4period[tid][idx];
- aver_tidtx_inperiod[tid] = tidtx_inp4eriod[tid] / 4;
- if (aver_tidtx_inperiod[tid] > 5000)
- rtlpriv->link_info.higher_busytxtraffic[tid] =
- true;
- else
- rtlpriv->link_info.higher_busytxtraffic[tid] =
- false;
- }
-
- /* PS is controlled by coex. */
- if (rtlpriv->cfg->ops->get_btc_status() &&
- rtlpriv->btcoexist.btc_ops->btc_is_bt_ctrl_lps(rtlpriv))
- goto label_lps_done;
-
- if (rtlpriv->link_info.num_rx_inperiod +
- rtlpriv->link_info.num_tx_inperiod > 8 ||
- rtlpriv->link_info.num_rx_inperiod > 2)
- rtl_lps_leave(hw);
- else
- rtl_lps_enter(hw);
-
-label_lps_done:
- ;
- }
-
- rtlpriv->link_info.num_rx_inperiod = 0;
- rtlpriv->link_info.num_tx_inperiod = 0;
- for (tid = 0; tid <= 7; tid++)
- rtlpriv->link_info.tidtx_inperiod[tid] = 0;
-
- rtlpriv->link_info.busytraffic = busytraffic;
- rtlpriv->link_info.higher_busytraffic = higher_busytraffic;
- rtlpriv->link_info.rx_busy_traffic = rx_busy_traffic;
- rtlpriv->link_info.tx_busy_traffic = tx_busy_traffic;
- rtlpriv->link_info.higher_busyrxtraffic = higher_busyrxtraffic;
-
- rtlpriv->stats.txbytesunicast_inperiod =
- rtlpriv->stats.txbytesunicast -
- rtlpriv->stats.txbytesunicast_last;
- rtlpriv->stats.rxbytesunicast_inperiod =
- rtlpriv->stats.rxbytesunicast -
- rtlpriv->stats.rxbytesunicast_last;
- rtlpriv->stats.txbytesunicast_last = rtlpriv->stats.txbytesunicast;
- rtlpriv->stats.rxbytesunicast_last = rtlpriv->stats.rxbytesunicast;
-
- rtlpriv->stats.txbytesunicast_inperiod_tp =
- (u32)(rtlpriv->stats.txbytesunicast_inperiod * 8 / 2 /
- 1024 / 1024);
- rtlpriv->stats.rxbytesunicast_inperiod_tp =
- (u32)(rtlpriv->stats.rxbytesunicast_inperiod * 8 / 2 /
- 1024 / 1024);
-
- /* <3> DM */
- if (!rtlpriv->cfg->mod_params->disable_watchdog)
- rtlpriv->cfg->ops->dm_watchdog(hw);
-
- /* <4> roaming */
- if (mac->link_state == MAC80211_LINKED &&
- mac->opmode == NL80211_IFTYPE_STATION) {
- if ((rtlpriv->link_info.bcn_rx_inperiod +
- rtlpriv->link_info.num_rx_inperiod) == 0) {
- rtlpriv->link_info.roam_times++;
- RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
- "AP off for %d s\n",
- (rtlpriv->link_info.roam_times * 2));
-
- /* if we can't recv beacon for 10s,
- * we should reconnect this AP
- */
- if (rtlpriv->link_info.roam_times >= 5) {
- pr_err("AP off, try to reconnect now\n");
- rtlpriv->link_info.roam_times = 0;
- ieee80211_connection_loss(rtlpriv->mac80211.vif);
- }
- } else {
- rtlpriv->link_info.roam_times = 0;
- }
- }
-
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_periodical(rtlpriv);
-
- if (rtlpriv->btcoexist.btc_info.in_4way) {
- if (time_after(jiffies, rtlpriv->btcoexist.btc_info.in_4way_ts +
- msecs_to_jiffies(IN_4WAY_TIMEOUT_TIME)))
- rtlpriv->btcoexist.btc_info.in_4way = false;
- }
-
- rtlpriv->link_info.bcn_rx_inperiod = 0;
-
- /* <6> scan list */
- rtl_scan_list_expire(hw);
-}
-
-void rtl_watch_dog_timer_callback(struct timer_list *t)
-{
- struct rtl_priv *rtlpriv = from_timer(rtlpriv, t, works.watchdog_timer);
-
- queue_delayed_work(rtlpriv->works.rtl_wq,
- &rtlpriv->works.watchdog_wq, 0);
-
- mod_timer(&rtlpriv->works.watchdog_timer,
- jiffies + MSECS(RTL_WATCH_DOG_TIME));
-}
-
-void rtl_fwevt_wq_callback(void *data)
-{
- struct rtl_works *rtlworks =
- container_of_dwork_rtl(data, struct rtl_works, fwevt_wq);
- struct ieee80211_hw *hw = rtlworks->hw;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtlpriv->cfg->ops->c2h_command_handle(hw);
-}
-
-void rtl_c2hcmd_enqueue(struct ieee80211_hw *hw, u8 tag, u8 len, u8 *val)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- unsigned long flags;
- struct rtl_c2hcmd *c2hcmd;
-
- c2hcmd = kmalloc(sizeof(*c2hcmd),
- in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
-
- if (!c2hcmd)
- goto label_err;
-
- c2hcmd->val = kmalloc(len,
- in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
-
- if (!c2hcmd->val)
- goto label_err2;
-
- /* fill data */
- c2hcmd->tag = tag;
- c2hcmd->len = len;
- memcpy(c2hcmd->val, val, len);
-
- /* enqueue */
- spin_lock_irqsave(&rtlpriv->locks.c2hcmd_lock, flags);
-
- list_add_tail(&c2hcmd->list, &rtlpriv->c2hcmd_list);
-
- spin_unlock_irqrestore(&rtlpriv->locks.c2hcmd_lock, flags);
-
- /* wake up wq */
- queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.c2hcmd_wq, 0);
-
- return;
-
-label_err2:
- kfree(c2hcmd);
-
-label_err:
- RT_TRACE(rtlpriv, COMP_CMD, DBG_WARNING,
- "C2H cmd enqueue fail.\n");
-}
-
-void rtl_c2hcmd_launcher(struct ieee80211_hw *hw, int exec)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- unsigned long flags;
- struct rtl_c2hcmd *c2hcmd;
- int i;
-
- for (i = 0; i < 200; i++) {
- /* dequeue a task */
- spin_lock_irqsave(&rtlpriv->locks.c2hcmd_lock, flags);
-
- c2hcmd = list_first_entry_or_null(&rtlpriv->c2hcmd_list,
- struct rtl_c2hcmd, list);
-
- if (c2hcmd)
- list_del(&c2hcmd->list);
-
- spin_unlock_irqrestore(&rtlpriv->locks.c2hcmd_lock, flags);
-
- /* do it */
- if (!c2hcmd)
- break;
-
- if (rtlpriv->cfg->ops->c2h_content_parsing && exec)
- rtlpriv->cfg->ops->c2h_content_parsing(hw,
- c2hcmd->tag, c2hcmd->len, c2hcmd->val);
-
- /* free */
- kfree(c2hcmd->val);
-
- kfree(c2hcmd);
- }
-}
-
-void rtl_c2hcmd_wq_callback(void *data)
-{
- struct rtl_works *rtlworks = container_of_dwork_rtl(data,
- struct rtl_works,
- c2hcmd_wq);
- struct ieee80211_hw *hw = rtlworks->hw;
-
- rtl_c2hcmd_launcher(hw, 1);
-}
-
-void rtl_easy_concurrent_retrytimer_callback(struct timer_list *t)
-{
- struct rtl_priv *rtlpriv =
- from_timer(rtlpriv, t, works.dualmac_easyconcurrent_retrytimer);
- struct ieee80211_hw *hw = rtlpriv->hw;
- struct rtl_priv *buddy_priv = rtlpriv->buddy_priv;
-
- if (!buddy_priv)
- return;
-
- rtlpriv->cfg->ops->dualmac_easy_concurrent(hw);
-}
-
-/*********************************************************
- *
- * frame process functions
- *
- *********************************************************/
-u8 *rtl_find_ie(u8 *data, unsigned int len, u8 ie)
-{
- struct ieee80211_mgmt *mgmt = (void *)data;
- u8 *pos, *end;
-
- pos = (u8 *)mgmt->u.beacon.variable;
- end = data + len;
- while (pos < end) {
- if (pos + 2 + pos[1] > end)
- return NULL;
-
- if (pos[0] == ie)
- return pos;
-
- pos += 2 + pos[1];
- }
- return NULL;
-}
-
-/* when we use 2 rx ants we send IEEE80211_SMPS_OFF */
-/* when we use 1 rx ant we send IEEE80211_SMPS_STATIC */
-static struct sk_buff *rtl_make_smps_action(struct ieee80211_hw *hw,
- enum ieee80211_smps_mode smps,
- u8 *da, u8 *bssid)
-{
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- struct sk_buff *skb;
- struct ieee80211_mgmt *action_frame;
-
- /* 27 = header + category + action + smps mode */
- skb = dev_alloc_skb(27 + hw->extra_tx_headroom);
- if (!skb)
- return NULL;
-
- skb_reserve(skb, hw->extra_tx_headroom);
- action_frame = skb_put_zero(skb, 27);
- memcpy(action_frame->da, da, ETH_ALEN);
- memcpy(action_frame->sa, rtlefuse->dev_addr, ETH_ALEN);
- memcpy(action_frame->bssid, bssid, ETH_ALEN);
- action_frame->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
- IEEE80211_STYPE_ACTION);
- action_frame->u.action.category = WLAN_CATEGORY_HT;
- action_frame->u.action.u.ht_smps.action = WLAN_HT_ACTION_SMPS;
- switch (smps) {
- case IEEE80211_SMPS_AUTOMATIC:/* 0 */
- case IEEE80211_SMPS_NUM_MODES:/* 4 */
- WARN_ON(1);
- /* fall through */
- case IEEE80211_SMPS_OFF:/* 1 */ /*MIMO_PS_NOLIMIT*/
- action_frame->u.action.u.ht_smps.smps_control =
- WLAN_HT_SMPS_CONTROL_DISABLED;/* 0 */
- break;
- case IEEE80211_SMPS_STATIC:/* 2 */ /*MIMO_PS_STATIC*/
- action_frame->u.action.u.ht_smps.smps_control =
- WLAN_HT_SMPS_CONTROL_STATIC;/* 1 */
- break;
- case IEEE80211_SMPS_DYNAMIC:/* 3 */ /*MIMO_PS_DYNAMIC*/
- action_frame->u.action.u.ht_smps.smps_control =
- WLAN_HT_SMPS_CONTROL_DYNAMIC;/* 3 */
- break;
- }
-
- return skb;
-}
-
-int rtl_send_smps_action(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- enum ieee80211_smps_mode smps)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct sk_buff *skb = NULL;
- struct rtl_tcb_desc tcb_desc;
- u8 bssid[ETH_ALEN] = {0};
-
- memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
-
- if (rtlpriv->mac80211.act_scanning)
- goto err_free;
-
- if (!sta)
- goto err_free;
-
- if (unlikely(is_hal_stop(rtlhal) || ppsc->rfpwr_state != ERFON))
- goto err_free;
-
- if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
- goto err_free;
-
- if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP)
- memcpy(bssid, rtlpriv->efuse.dev_addr, ETH_ALEN);
- else
- memcpy(bssid, rtlpriv->mac80211.bssid, ETH_ALEN);
-
- skb = rtl_make_smps_action(hw, smps, sta->addr, bssid);
- /* this is a type = mgmt * stype = action frame */
- if (skb) {
- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
- struct rtl_sta_info *sta_entry =
- (struct rtl_sta_info *)sta->drv_priv;
- sta_entry->mimo_ps = smps;
- /* rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0, true); */
-
- info->control.rates[0].idx = 0;
- info->band = hw->conf.chandef.chan->band;
- rtlpriv->intf_ops->adapter_tx(hw, sta, skb, &tcb_desc);
- }
- return 1;
-
-err_free:
- return 0;
-}
-
-void rtl_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- enum io_type iotype;
-
- if (!is_hal_stop(rtlhal)) {
- switch (operation) {
- case SCAN_OPT_BACKUP:
- iotype = IO_CMD_PAUSE_DM_BY_SCAN;
- rtlpriv->cfg->ops->set_hw_reg(hw,
- HW_VAR_IO_CMD,
- (u8 *)&iotype);
- break;
- case SCAN_OPT_RESTORE:
- iotype = IO_CMD_RESUME_DM_BY_SCAN;
- rtlpriv->cfg->ops->set_hw_reg(hw,
- HW_VAR_IO_CMD,
- (u8 *)&iotype);
- break;
- default:
- pr_err("Unknown Scan Backup operation.\n");
- break;
- }
- }
-}
-
-/* because mac80211 have issues when can receive del ba
- * so here we just make a fake del_ba if we receive a ba_req
- * but rx_agg was opened to let mac80211 release some ba
- * related resources, so please this del_ba for tx
- */
-struct sk_buff *rtl_make_del_ba(struct ieee80211_hw *hw,
- u8 *sa, u8 *bssid, u16 tid)
-{
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- struct sk_buff *skb;
- struct ieee80211_mgmt *action_frame;
- u16 params;
-
- /* 27 = header + category + action + smps mode */
- skb = dev_alloc_skb(34 + hw->extra_tx_headroom);
- if (!skb)
- return NULL;
-
- skb_reserve(skb, hw->extra_tx_headroom);
- action_frame = skb_put_zero(skb, 34);
- memcpy(action_frame->sa, sa, ETH_ALEN);
- memcpy(action_frame->da, rtlefuse->dev_addr, ETH_ALEN);
- memcpy(action_frame->bssid, bssid, ETH_ALEN);
- action_frame->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
- IEEE80211_STYPE_ACTION);
- action_frame->u.action.category = WLAN_CATEGORY_BACK;
- action_frame->u.action.u.delba.action_code = WLAN_ACTION_DELBA;
- params = BIT(11); /* bit 11 initiator */
- params |= (u16)(tid << 12); /* bit 15:12 TID number */
-
- action_frame->u.action.u.delba.params = cpu_to_le16(params);
- action_frame->u.action.u.delba.reason_code =
- cpu_to_le16(WLAN_REASON_QSTA_TIMEOUT);
-
- return skb;
-}
-
-bool rtl_check_beacon_key(struct ieee80211_hw *hw, void *data, unsigned int len)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct ieee80211_hdr *hdr = data;
- struct ieee80211_ht_cap *ht_cap_ie;
- struct ieee80211_ht_operation *ht_oper_ie = NULL;
- struct rtl_beacon_keys bcn_key = {};
- struct rtl_beacon_keys *cur_bcn_key;
- u8 *ht_cap;
- u8 *ht_oper;
- u8 *ds_param;
-
- if (mac->opmode != NL80211_IFTYPE_STATION)
- return false;
-
- /* check if this really is a beacon*/
- if (!ieee80211_is_beacon(hdr->frame_control))
- return false;
-
- /* min. beacon length + FCS_LEN */
- if (len <= 40 + FCS_LEN)
- return false;
-
- cur_bcn_key = &mac->cur_beacon_keys;
-
- if (rtlpriv->mac80211.link_state == MAC80211_NOLINK) {
- if (cur_bcn_key->valid) {
- cur_bcn_key->valid = false;
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
- "Reset cur_beacon_keys.valid to false!\n");
- }
- return false;
- }
-
- /* and only beacons from the associated BSSID, please */
- if (!ether_addr_equal(hdr->addr3, rtlpriv->mac80211.bssid))
- return false;
-
- /***** Parsing DS Param IE ******/
- ds_param = rtl_find_ie(data, len - FCS_LEN, WLAN_EID_DS_PARAMS);
-
- if (ds_param && !(ds_param[1] < sizeof(*ds_param)))
- bcn_key.bcn_channel = ds_param[2];
- else
- ds_param = NULL;
-
- /***** Parsing HT Cap. IE ******/
- ht_cap = rtl_find_ie(data, len - FCS_LEN, WLAN_EID_HT_CAPABILITY);
-
- if (ht_cap && !(ht_cap[1] < sizeof(*ht_cap))) {
- ht_cap_ie = (struct ieee80211_ht_cap *)&ht_cap[2];
- bcn_key.ht_cap_info = ht_cap_ie->cap_info;
- } else {
- ht_cap = NULL;
- }
-
- /***** Parsing HT Info. IE ******/
- ht_oper = rtl_find_ie(data, len - FCS_LEN, WLAN_EID_HT_OPERATION);
-
- if (ht_oper && !(ht_oper[1] < sizeof(*ht_oper)))
- ht_oper_ie = (struct ieee80211_ht_operation *)&ht_oper[2];
- else
- ht_oper = NULL;
-
- /* update bcn_key */
-
- if (!ds_param && ht_oper && ht_oper_ie)
- bcn_key.bcn_channel = ht_oper_ie->primary_chan;
-
- if (ht_oper && ht_oper_ie)
- bcn_key.ht_info_infos_0_sco = ht_oper_ie->ht_param & 0x03;
-
- bcn_key.valid = true;
-
- /* update cur_beacon_keys or compare beacon key */
- if (rtlpriv->mac80211.link_state != MAC80211_LINKED &&
- rtlpriv->mac80211.link_state != MAC80211_LINKED_SCANNING)
- return true;
-
- if (!cur_bcn_key->valid) {
- /* update cur_beacon_keys */
- memcpy(cur_bcn_key, &bcn_key, sizeof(bcn_key));
- cur_bcn_key->valid = true;
-
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
- "Beacon key update!ch=%d, ht_cap_info=0x%x, sco=0x%x\n",
- cur_bcn_key->bcn_channel,
- cur_bcn_key->ht_cap_info,
- cur_bcn_key->ht_info_infos_0_sco);
- return true;
- }
-
- /* compare beacon key */
- if (!memcmp(cur_bcn_key, &bcn_key, sizeof(bcn_key))) {
- /* same beacon key */
- mac->new_beacon_cnt = 0;
- goto chk_exit;
- }
-
- if (cur_bcn_key->bcn_channel == bcn_key.bcn_channel &&
- cur_bcn_key->ht_cap_info == bcn_key.ht_cap_info) {
- /* Beacon HT info IE, secondary channel offset check */
- /* 40M -> 20M */
- if (cur_bcn_key->ht_info_infos_0_sco >
- bcn_key.ht_info_infos_0_sco) {
- /* Not a new beacon */
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
- "Beacon BW change! sco:0x%x -> 0x%x\n",
- cur_bcn_key->ht_info_infos_0_sco,
- bcn_key.ht_info_infos_0_sco);
-
- cur_bcn_key->ht_info_infos_0_sco =
- bcn_key.ht_info_infos_0_sco;
- } else {
- /* 20M -> 40M */
- if (rtlphy->max_ht_chan_bw >= HT_CHANNEL_WIDTH_20_40) {
- /* Not a new beacon */
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
- "Beacon BW change! sco:0x%x -> 0x%x\n",
- cur_bcn_key->ht_info_infos_0_sco,
- bcn_key.ht_info_infos_0_sco);
-
- cur_bcn_key->ht_info_infos_0_sco =
- bcn_key.ht_info_infos_0_sco;
- } else {
- mac->new_beacon_cnt++;
- }
- }
- } else {
- mac->new_beacon_cnt++;
- }
-
- if (mac->new_beacon_cnt == 1) {
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
- "Get new beacon.\n");
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
- "Cur : ch=%d, ht_cap=0x%x, sco=0x%x\n",
- cur_bcn_key->bcn_channel,
- cur_bcn_key->ht_cap_info,
- cur_bcn_key->ht_info_infos_0_sco);
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
- "New RX : ch=%d, ht_cap=0x%x, sco=0x%x\n",
- bcn_key.bcn_channel,
- bcn_key.ht_cap_info,
- bcn_key.ht_info_infos_0_sco);
-
- } else if (mac->new_beacon_cnt > 1) {
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
- "new beacon cnt: %d\n",
- mac->new_beacon_cnt);
- }
-
- if (mac->new_beacon_cnt > 3) {
- ieee80211_connection_loss(rtlpriv->mac80211.vif);
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
- "new beacon cnt >3, disconnect !\n");
- }
-
-chk_exit:
-
- return true;
-}
-
-/*********************************************************
- *
- * IOT functions
- *
- *********************************************************/
-static bool rtl_chk_vendor_ouisub(struct ieee80211_hw *hw,
- struct octet_string vendor_ie)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- bool matched = false;
- static u8 athcap_1[] = { 0x00, 0x03, 0x7F };
- static u8 athcap_2[] = { 0x00, 0x13, 0x74 };
- static u8 broadcap_1[] = { 0x00, 0x10, 0x18 };
- static u8 broadcap_2[] = { 0x00, 0x0a, 0xf7 };
- static u8 broadcap_3[] = { 0x00, 0x05, 0xb5 };
- static u8 racap[] = { 0x00, 0x0c, 0x43 };
- static u8 ciscocap[] = { 0x00, 0x40, 0x96 };
- static u8 marvcap[] = { 0x00, 0x50, 0x43 };
-
- if (memcmp(vendor_ie.octet, athcap_1, 3) == 0 ||
- memcmp(vendor_ie.octet, athcap_2, 3) == 0) {
- rtlpriv->mac80211.vendor = PEER_ATH;
- matched = true;
- } else if (memcmp(vendor_ie.octet, broadcap_1, 3) == 0 ||
- memcmp(vendor_ie.octet, broadcap_2, 3) == 0 ||
- memcmp(vendor_ie.octet, broadcap_3, 3) == 0) {
- rtlpriv->mac80211.vendor = PEER_BROAD;
- matched = true;
- } else if (memcmp(vendor_ie.octet, racap, 3) == 0) {
- rtlpriv->mac80211.vendor = PEER_RAL;
- matched = true;
- } else if (memcmp(vendor_ie.octet, ciscocap, 3) == 0) {
- rtlpriv->mac80211.vendor = PEER_CISCO;
- matched = true;
- } else if (memcmp(vendor_ie.octet, marvcap, 3) == 0) {
- rtlpriv->mac80211.vendor = PEER_MARV;
- matched = true;
- }
-
- return matched;
-}
-
-static bool rtl_find_221_ie(struct ieee80211_hw *hw, u8 *data,
- unsigned int len)
-{
- struct ieee80211_mgmt *mgmt = (void *)data;
- struct octet_string vendor_ie;
- u8 *pos, *end;
-
- pos = (u8 *)mgmt->u.beacon.variable;
- end = data + len;
- while (pos < end) {
- if (pos[0] == 221) {
- vendor_ie.length = pos[1];
- vendor_ie.octet = &pos[2];
- if (rtl_chk_vendor_ouisub(hw, vendor_ie))
- return true;
- }
-
- if (pos + 2 + pos[1] > end)
- return false;
-
- pos += 2 + pos[1];
- }
- return false;
-}
-
-void rtl_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct ieee80211_hdr *hdr = (void *)data;
- u32 vendor = PEER_UNKNOWN;
-
- static u8 ap3_1[3] = { 0x00, 0x14, 0xbf };
- static u8 ap3_2[3] = { 0x00, 0x1a, 0x70 };
- static u8 ap3_3[3] = { 0x00, 0x1d, 0x7e };
- static u8 ap4_1[3] = { 0x00, 0x90, 0xcc };
- static u8 ap4_2[3] = { 0x00, 0x0e, 0x2e };
- static u8 ap4_3[3] = { 0x00, 0x18, 0x02 };
- static u8 ap4_4[3] = { 0x00, 0x17, 0x3f };
- static u8 ap4_5[3] = { 0x00, 0x1c, 0xdf };
- static u8 ap5_1[3] = { 0x00, 0x1c, 0xf0 };
- static u8 ap5_2[3] = { 0x00, 0x21, 0x91 };
- static u8 ap5_3[3] = { 0x00, 0x24, 0x01 };
- static u8 ap5_4[3] = { 0x00, 0x15, 0xe9 };
- static u8 ap5_5[3] = { 0x00, 0x17, 0x9A };
- static u8 ap5_6[3] = { 0x00, 0x18, 0xE7 };
- static u8 ap6_1[3] = { 0x00, 0x17, 0x94 };
- static u8 ap7_1[3] = { 0x00, 0x14, 0xa4 };
-
- if (mac->opmode != NL80211_IFTYPE_STATION)
- return;
-
- if (mac->link_state == MAC80211_NOLINK) {
- mac->vendor = PEER_UNKNOWN;
- return;
- }
-
- if (mac->cnt_after_linked > 2)
- return;
-
- /* check if this really is a beacon */
- if (!ieee80211_is_beacon(hdr->frame_control))
- return;
-
- /* min. beacon length + FCS_LEN */
- if (len <= 40 + FCS_LEN)
- return;
-
- /* and only beacons from the associated BSSID, please */
- if (!ether_addr_equal_64bits(hdr->addr3, rtlpriv->mac80211.bssid))
- return;
-
- if (rtl_find_221_ie(hw, data, len))
- vendor = mac->vendor;
-
- if ((memcmp(mac->bssid, ap5_1, 3) == 0) ||
- (memcmp(mac->bssid, ap5_2, 3) == 0) ||
- (memcmp(mac->bssid, ap5_3, 3) == 0) ||
- (memcmp(mac->bssid, ap5_4, 3) == 0) ||
- (memcmp(mac->bssid, ap5_5, 3) == 0) ||
- (memcmp(mac->bssid, ap5_6, 3) == 0) ||
- vendor == PEER_ATH) {
- vendor = PEER_ATH;
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ath find\n");
- } else if ((memcmp(mac->bssid, ap4_4, 3) == 0) ||
- (memcmp(mac->bssid, ap4_5, 3) == 0) ||
- (memcmp(mac->bssid, ap4_1, 3) == 0) ||
- (memcmp(mac->bssid, ap4_2, 3) == 0) ||
- (memcmp(mac->bssid, ap4_3, 3) == 0) ||
- vendor == PEER_RAL) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ral find\n");
- vendor = PEER_RAL;
- } else if (memcmp(mac->bssid, ap6_1, 3) == 0 ||
- vendor == PEER_CISCO) {
- vendor = PEER_CISCO;
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>cisco find\n");
- } else if ((memcmp(mac->bssid, ap3_1, 3) == 0) ||
- (memcmp(mac->bssid, ap3_2, 3) == 0) ||
- (memcmp(mac->bssid, ap3_3, 3) == 0) ||
- vendor == PEER_BROAD) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>broad find\n");
- vendor = PEER_BROAD;
- } else if (memcmp(mac->bssid, ap7_1, 3) == 0 ||
- vendor == PEER_MARV) {
- vendor = PEER_MARV;
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>marv find\n");
- }
-
- mac->vendor = vendor;
-}
-
-MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
-MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
-MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
-
-struct rtl_global_var rtl_global_var = {};
-
-int rtl_core_module_init(void)
-{
- if (rtl_rate_control_register())
- pr_err("rtl: Unable to register rtl_rc, use default RC !!\n");
-
- /* add debugfs */
- rtl_debugfs_add_topdir();
-
- /* init some global vars */
- INIT_LIST_HEAD(&rtl_global_var.glb_priv_list);
- spin_lock_init(&rtl_global_var.glb_list_lock);
-
- return 0;
-}
-
-void rtl_core_module_exit(void)
-{
- /*RC*/
- rtl_rate_control_unregister();
-
- /* remove debugfs */
- rtl_debugfs_remove_topdir();
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_BASE_H__
-#define __RTL_BASE_H__
-
-enum ap_peer {
- PEER_UNKNOWN = 0,
- PEER_RTL = 1,
- PEER_RTL_92SE = 2,
- PEER_BROAD = 3,
- PEER_RAL = 4,
- PEER_ATH = 5,
- PEER_CISCO = 6,
- PEER_MARV = 7,
- PEER_AIRGO = 9,
- PEER_MAX = 10,
-};
-
-#define RTL_DUMMY_OFFSET 0
-#define RTL_DUMMY_UNIT 8
-#define RTL_TX_DUMMY_SIZE (RTL_DUMMY_OFFSET * RTL_DUMMY_UNIT)
-#define RTL_TX_DESC_SIZE 32
-#define RTL_TX_HEADER_SIZE (RTL_TX_DESC_SIZE + RTL_TX_DUMMY_SIZE)
-
-#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */
-#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */
-
-#define MAX_BIT_RATE_SHORT_GI_2NSS_80MHZ_MCS9 867 /* Mbps */
-#define MAX_BIT_RATE_SHORT_GI_2NSS_80MHZ_MCS7 650 /* Mbps */
-#define MAX_BIT_RATE_LONG_GI_2NSS_80MHZ_MCS9 780 /* Mbps */
-#define MAX_BIT_RATE_LONG_GI_2NSS_80MHZ_MCS7 585 /* Mbps */
-
-#define MAX_BIT_RATE_SHORT_GI_1NSS_80MHZ_MCS9 434 /* Mbps */
-#define MAX_BIT_RATE_SHORT_GI_1NSS_80MHZ_MCS7 325 /* Mbps */
-#define MAX_BIT_RATE_LONG_GI_1NSS_80MHZ_MCS9 390 /* Mbps */
-#define MAX_BIT_RATE_LONG_GI_1NSS_80MHZ_MCS7 293 /* Mbps */
-
-#define FRAME_OFFSET_FRAME_CONTROL 0
-#define FRAME_OFFSET_DURATION 2
-#define FRAME_OFFSET_ADDRESS1 4
-#define FRAME_OFFSET_ADDRESS2 10
-#define FRAME_OFFSET_ADDRESS3 16
-#define FRAME_OFFSET_SEQUENCE 22
-#define FRAME_OFFSET_ADDRESS4 24
-#define MAX_LISTEN_INTERVAL 10
-#define MAX_RATE_TRIES 4
-
-#define SET_80211_HDR_FRAME_CONTROL(_hdr, _val) \
- WRITEEF2BYTE(_hdr, _val)
-#define SET_80211_HDR_TYPE_AND_SUBTYPE(_hdr, _val) \
- WRITEEF1BYTE(_hdr, _val)
-#define SET_80211_HDR_PWR_MGNT(_hdr, _val) \
- SET_BITS_TO_LE_2BYTE(_hdr, 12, 1, _val)
-#define SET_80211_HDR_TO_DS(_hdr, _val) \
- SET_BITS_TO_LE_2BYTE(_hdr, 8, 1, _val)
-
-#define SET_80211_PS_POLL_AID(_hdr, _val) \
- (*(u16 *)((u8 *)(_hdr) + 2) = _val)
-#define SET_80211_PS_POLL_BSSID(_hdr, _val) \
- ether_addr_copy(((u8 *)(_hdr)) + 4, (u8 *)(_val))
-#define SET_80211_PS_POLL_TA(_hdr, _val) \
- ether_addr_copy(((u8 *)(_hdr)) + 10, (u8 *)(_val))
-
-#define SET_80211_HDR_DURATION(_hdr, _val) \
- (*(u16 *)((u8 *)(_hdr) + FRAME_OFFSET_DURATION) = le16_to_cpu(_val))
-#define SET_80211_HDR_ADDRESS1(_hdr, _val) \
- CP_MACADDR((u8 *)(_hdr) + FRAME_OFFSET_ADDRESS1, (u8 *)(_val))
-#define SET_80211_HDR_ADDRESS2(_hdr, _val) \
- CP_MACADDR((u8 *)(_hdr) + FRAME_OFFSET_ADDRESS2, (u8 *)(_val))
-#define SET_80211_HDR_ADDRESS3(_hdr, _val) \
- CP_MACADDR((u8 *)(_hdr) + FRAME_OFFSET_ADDRESS3, (u8 *)(_val))
-#define SET_80211_HDR_FRAGMENT_SEQUENCE(_hdr, _val) \
- WRITEEF2BYTE((u8 *)(_hdr) + FRAME_OFFSET_SEQUENCE, _val)
-
-#define SET_BEACON_PROBE_RSP_TIME_STAMP_LOW(__phdr, __val) \
- WRITEEF4BYTE(((u8 *)(__phdr)) + 24, __val)
-#define SET_BEACON_PROBE_RSP_TIME_STAMP_HIGH(__phdr, __val) \
- WRITEEF4BYTE(((u8 *)(__phdr)) + 28, __val)
-#define SET_BEACON_PROBE_RSP_BEACON_INTERVAL(__phdr, __val) \
- WRITEEF2BYTE(((u8 *)(__phdr)) + 32, __val)
-#define GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) \
- READEF2BYTE(((u8 *)(__phdr)) + 34)
-#define SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
- WRITEEF2BYTE(((u8 *)(__phdr)) + 34, __val)
-#define MASK_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
- SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, \
- (GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) & (~(__val))))
-
-#define SET_TX_DESC_SPE_RPT(__pdesc, __val) \
- SET_BITS_TO_LE_4BYTE((__pdesc) + 8, 19, 1, __val)
-#define SET_TX_DESC_SW_DEFINE(__pdesc, __val) \
- SET_BITS_TO_LE_4BYTE((__pdesc) + 24, 0, 12, __val)
-
-int rtl_init_core(struct ieee80211_hw *hw);
-void rtl_deinit_core(struct ieee80211_hw *hw);
-void rtl_init_rx_config(struct ieee80211_hw *hw);
-void rtl_init_rfkill(struct ieee80211_hw *hw);
-void rtl_deinit_rfkill(struct ieee80211_hw *hw);
-
-void rtl_watch_dog_timer_callback(struct timer_list *t);
-void rtl_deinit_deferred_work(struct ieee80211_hw *hw);
-
-bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
-int rtlwifi_rate_mapping(struct ieee80211_hw *hw, bool isht,
- bool isvht, u8 desc_rate);
-bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb);
-u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx,
- bool is_enc);
-
-bool rtl_is_tx_report_skb(struct ieee80211_hw *hw, struct sk_buff *skb);
-void rtl_get_tx_report(struct rtl_tcb_desc *ptcb_desc, u8 *pdesc,
- struct ieee80211_hw *hw);
-void rtl_tx_report_handler(struct ieee80211_hw *hw, u8 *tmp_buf,
- u8 c2h_cmd_len);
-bool rtl_check_tx_report_acked(struct ieee80211_hw *hw);
-void rtl_wait_tx_report_acked(struct ieee80211_hw *hw, u32 wait_ms);
-u32 rtl_get_hal_edca_param(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- enum wireless_mode wirelessmode,
- struct ieee80211_tx_queue_params *param);
-
-void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb);
-void rtl_collect_scan_list(struct ieee80211_hw *hw, struct sk_buff *skb);
-void rtl_scan_list_expire(struct ieee80211_hw *hw);
-int rtl_tx_agg_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
- struct ieee80211_sta *sta, u16 tid, u16 *ssn);
-int rtl_tx_agg_stop(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
- struct ieee80211_sta *sta, u16 tid);
-int rtl_tx_agg_oper(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u16 tid);
-int rtl_rx_agg_start(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u16 tid);
-int rtl_rx_agg_stop(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u16 tid);
-void rtl_rx_ampdu_apply(struct rtl_priv *rtlpriv);
-void rtl_watchdog_wq_callback(void *data);
-void rtl_fwevt_wq_callback(void *data);
-void rtl_c2hcmd_wq_callback(void *data);
-void rtl_c2hcmd_launcher(struct ieee80211_hw *hw, int exec);
-void rtl_c2hcmd_enqueue(struct ieee80211_hw *hw, u8 tag, u8 len, u8 *val);
-
-u8 rtl_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
- u8 rate_index,
- enum wireless_mode wirelessmode);
-void rtl_get_tcb_desc(struct ieee80211_hw *hw,
- struct ieee80211_tx_info *info,
- struct ieee80211_sta *sta,
- struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc);
-
-int rtl_send_smps_action(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- enum ieee80211_smps_mode smps);
-u8 *rtl_find_ie(u8 *data, unsigned int len, u8 ie);
-void rtl_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len);
-u8 rtl_tid_to_ac(u8 tid);
-void rtl_easy_concurrent_retrytimer_callback(struct timer_list *t);
-extern struct rtl_global_var rtl_global_var;
-void rtl_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation);
-bool rtl_check_beacon_key(struct ieee80211_hw *hw, void *data,
- unsigned int len);
-int rtl_core_module_init(void);
-void rtl_core_module_exit(void);
-#endif
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-btcoexist-objs := \
- halbtc8822b1ant.o \
- halbtc8822b2ant.o \
- halbtc8822bwifionly.o \
- halbtcoutsrc.o \
- rtl_btc.o
-
-obj-$(CONFIG_RTLBTCOEXIST) += btcoexist.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- ******************************************************************************/
-
-#ifndef __HALBT_PRECOMP_H__
-#define __HALBT_PRECOMP_H__
-/*************************************************************
- * include files
- *************************************************************/
-#include "../wifi.h"
-#include "../efuse.h"
-#include "../base.h"
-#include "../regd.h"
-#include "../cam.h"
-#include "../ps.h"
-#include "../pci.h"
-
-#include "halbtcoutsrc.h"
-
-/* Interface type */
-#define RT_PCI_INTERFACE 1
-#define RT_USB_INTERFACE 2
-#define RT_SDIO_INTERFACE 3
-#define DEV_BUS_TYPE RT_PCI_INTERFACE
-
-#include "halbtc8822b1ant.h"
-#include "halbtc8822b2ant.h"
-#include "halbtc8822bwifionly.h"
-
-#define GETDEFAULTADAPTER(padapter) padapter
-
-#define BIT0 0x00000001
-#define BIT1 0x00000002
-#define BIT2 0x00000004
-#define BIT3 0x00000008
-#define BIT4 0x00000010
-#define BIT5 0x00000020
-#define BIT6 0x00000040
-#define BIT7 0x00000080
-#define BIT8 0x00000100
-#define BIT9 0x00000200
-#define BIT10 0x00000400
-#define BIT11 0x00000800
-#define BIT12 0x00001000
-#define BIT13 0x00002000
-#define BIT14 0x00004000
-#define BIT15 0x00008000
-#define BIT16 0x00010000
-#define BIT17 0x00020000
-#define BIT18 0x00040000
-#define BIT19 0x00080000
-#define BIT20 0x00100000
-#define BIT21 0x00200000
-#define BIT22 0x00400000
-#define BIT23 0x00800000
-#define BIT24 0x01000000
-#define BIT25 0x02000000
-#define BIT26 0x04000000
-#define BIT27 0x08000000
-#define BIT28 0x10000000
-#define BIT29 0x20000000
-#define BIT30 0x40000000
-#define BIT31 0x80000000
-
-#endif /* __HALBT_PRECOMP_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8822B Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * *************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-/*only for rf4ce*/
-#include "halbt_precomp.h"
-
-/* ************************************************************
- * Global variables, these are static variables
- * *************************************************************/
-static struct coex_dm_8822b_1ant glcoex_dm_8822b_1ant;
-static struct coex_dm_8822b_1ant *coex_dm = &glcoex_dm_8822b_1ant;
-static struct coex_sta_8822b_1ant glcoex_sta_8822b_1ant;
-static struct coex_sta_8822b_1ant *coex_sta = &glcoex_sta_8822b_1ant;
-static struct psdscan_sta_8822b_1ant gl_psd_scan_8822b_1ant;
-static struct psdscan_sta_8822b_1ant *psd_scan = &gl_psd_scan_8822b_1ant;
-static struct rfe_type_8822b_1ant gl_rfe_type_8822b_1ant;
-static struct rfe_type_8822b_1ant *rfe_type = &gl_rfe_type_8822b_1ant;
-
-static const char *const glbt_info_src_8822b_1ant[] = {
- "BT Info[wifi fw]", "BT Info[bt rsp]", "BT Info[bt auto report]",
-};
-
-static u32 glcoex_ver_date_8822b_1ant = 20170327;
-static u32 glcoex_ver_8822b_1ant = 0x44;
-static u32 glcoex_ver_btdesired_8822b_1ant = 0x42;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8822b1ant_
- * *************************************************************/
-
-static u8 halbtc8822b1ant_wifi_rssi_state(struct btc_coexist *btcoexist,
- u8 index, u8 level_num,
- u8 rssi_thresh, u8 rssi_thresh1)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >=
- (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], wifi RSSI thresh error!!\n");
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >=
- (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-static void halbtc8822b1ant_update_ra_mask(struct btc_coexist *btcoexist,
- bool force_exec, u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-static void
-halbtc8822b1ant_auto_rate_fallback_retry(struct btc_coexist *btcoexist,
- bool force_exec, u8 type)
-{
- bool wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- 0x0);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- 0x0);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-static void halbtc8822b1ant_retry_limit(struct btc_coexist *btcoexist,
- bool force_exec, u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type != coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-static void halbtc8822b1ant_ampdu_max_time(struct btc_coexist *btcoexist,
- bool force_exec, u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(
- btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-static void halbtc8822b1ant_limited_tx(struct btc_coexist *btcoexist,
- bool force_exec, u8 ra_mask_type,
- u8 arfr_type, u8 retry_limit_type,
- u8 ampdu_time_type)
-{
- switch (ra_mask_type) {
- case 0: /* normal mode */
- halbtc8822b1ant_update_ra_mask(btcoexist, force_exec, 0x0);
- break;
- case 1: /* disable cck 1/2 */
- halbtc8822b1ant_update_ra_mask(btcoexist, force_exec,
- 0x00000003);
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- halbtc8822b1ant_update_ra_mask(btcoexist, force_exec,
- 0x0001f1f7);
- break;
- default:
- break;
- }
-
- halbtc8822b1ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8822b1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8822b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-/*
- * rx agg size setting :
- * 1: true / don't care / don't care
- * max: false / false / don't care
- * 7: false / true / 7
- */
-
-static void halbtc8822b1ant_limited_rx(struct btc_coexist *btcoexist,
- bool force_exec, bool rej_ap_agg_pkt,
- bool bt_ctrl_agg_buf_size,
- u8 agg_buf_size)
-{
- bool reject_rx_agg = rej_ap_agg_pkt;
- bool bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size*/
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-}
-
-static void halbtc8822b1ant_query_bt_info(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 h2c_parameter[1] = {0};
-
- if (coex_sta->bt_disabled) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], No query BT info because BT is disabled!\n");
- return;
- }
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], WL query BT info!!\n");
-}
-
-static void halbtc8822b1ant_monitor_bt_ctr(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
- static u8 num_of_bt_counter_chk, cnt_slave, cnt_autoslot_hang;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
- reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-
- if ((coex_sta->low_priority_tx > 1150) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- if ((coex_sta->low_priority_rx >= 1150) &&
- (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) &&
- (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) &&
- (coex_sta->bt_link_exist)) {
- if (cnt_slave >= 3) {
- bt_link_info->slave_role = true;
- cnt_slave = 3;
- } else {
- cnt_slave++;
- }
- } else {
- if (cnt_slave == 0) {
- bt_link_info->slave_role = false;
- cnt_slave = 0;
- } else {
- cnt_slave--;
- }
- }
-
- if (coex_sta->is_tdma_btautoslot) {
- if ((coex_sta->low_priority_tx >= 1300) &&
- (coex_sta->low_priority_rx <= 150)) {
- if (cnt_autoslot_hang >= 2) {
- coex_sta->is_tdma_btautoslot_hang = true;
- cnt_autoslot_hang = 2;
- } else {
- cnt_autoslot_hang++;
- }
- } else {
- if (cnt_autoslot_hang == 0) {
- coex_sta->is_tdma_btautoslot_hang = false;
- cnt_autoslot_hang = 0;
- } else {
- cnt_autoslot_hang--;
- }
- }
- }
-
- if (bt_link_info->hid_only) {
- if (coex_sta->low_priority_rx > 50)
- coex_sta->is_hid_low_pri_tx_overhead = true;
- else
- coex_sta->is_hid_low_pri_tx_overhead = false;
- }
-
- if ((coex_sta->high_priority_tx == 0) &&
- (coex_sta->high_priority_rx == 0) &&
- (coex_sta->low_priority_tx == 0) &&
- (coex_sta->low_priority_rx == 0)) {
- num_of_bt_counter_chk++;
-
- if (num_of_bt_counter_chk >= 3) {
- halbtc8822b1ant_query_bt_info(btcoexist);
- num_of_bt_counter_chk = 0;
- }
- }
-}
-
-static void halbtc8822b1ant_monitor_wifi_ctr(struct btc_coexist *btcoexist)
-{
- s32 wifi_rssi = 0;
- bool wifi_busy = false, wifi_under_b_mode = false, wifi_scan = false;
- static u8 cck_lock_counter, wl_noisy_count0, wl_noisy_count1 = 3,
- wl_noisy_count2;
- u32 total_cnt, cck_cnt;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
-
- coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_OK_CCK");
- coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_OK_LEGACY");
- coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_OK_HT");
- coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_OK_VHT");
-
- coex_sta->crc_err_cck = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_ERROR_CCK");
- coex_sta->crc_err_11g = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_ERROR_LEGACY");
- coex_sta->crc_err_11n = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_ERROR_HT");
- coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_ERROR_VHT");
-
- cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
-
- if (cck_cnt > 250) {
- if (wl_noisy_count2 < 3)
- wl_noisy_count2++;
-
- if (wl_noisy_count2 == 3) {
- wl_noisy_count0 = 0;
- wl_noisy_count1 = 0;
- }
-
- } else if (cck_cnt < 50) {
- if (wl_noisy_count0 < 3)
- wl_noisy_count0++;
-
- if (wl_noisy_count0 == 3) {
- wl_noisy_count1 = 0;
- wl_noisy_count2 = 0;
- }
-
- } else {
- if (wl_noisy_count1 < 3)
- wl_noisy_count1++;
-
- if (wl_noisy_count1 == 3) {
- wl_noisy_count0 = 0;
- wl_noisy_count2 = 0;
- }
- }
-
- if (wl_noisy_count2 == 3)
- coex_sta->wl_noisy_level = 2;
- else if (wl_noisy_count1 == 3)
- coex_sta->wl_noisy_level = 1;
- else
- coex_sta->wl_noisy_level = 0;
-
- if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
- total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
- coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht;
-
- if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status ==
- BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
- (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY)) {
- if (coex_sta->crc_ok_cck >
- (total_cnt - coex_sta->crc_ok_cck)) {
- if (cck_lock_counter < 3)
- cck_lock_counter++;
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- if (!coex_sta->pre_ccklock) {
- if (cck_lock_counter >= 3)
- coex_sta->cck_lock = true;
- else
- coex_sta->cck_lock = false;
- } else {
- if (cck_lock_counter == 0)
- coex_sta->cck_lock = false;
- else
- coex_sta->cck_lock = true;
- }
-
- if (coex_sta->cck_lock)
- coex_sta->cck_ever_lock = true;
-
- coex_sta->pre_ccklock = coex_sta->cck_lock;
-}
-
-static bool
-halbtc8822b1ant_is_wifi_status_changed(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static bool pre_wifi_busy, pre_under_4way, pre_bt_hs_on,
- pre_rf4ce_enabled, pre_bt_off, pre_bt_slave,
- pre_hid_low_pri_tx_overhead, pre_wifi_under_lps,
- pre_bt_setup_link;
- static u8 pre_hid_busy_num, pre_wl_noisy_level;
- bool wifi_busy = false, under_4way = false, bt_hs_on = false,
- rf4ce_enabled = false;
- bool wifi_connected = false;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (coex_sta->bt_disabled != pre_bt_off) {
- pre_bt_off = coex_sta->bt_disabled;
-
- if (coex_sta->bt_disabled)
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is disabled !!\n");
- else
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is enabled !!\n");
-
- coex_sta->bt_coex_supported_feature = 0;
- coex_sta->bt_coex_supported_version = 0;
- return true;
- }
- btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED,
- &rf4ce_enabled);
-
- if (rf4ce_enabled != pre_rf4ce_enabled) {
- pre_rf4ce_enabled = rf4ce_enabled;
-
- if (rf4ce_enabled)
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], rf4ce is enabled !!\n");
- else
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], rf4ce is disabled !!\n");
-
- return true;
- }
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
- pre_wl_noisy_level = coex_sta->wl_noisy_level;
- return true;
- }
- if (coex_sta->under_lps != pre_wifi_under_lps) {
- pre_wifi_under_lps = coex_sta->under_lps;
- if (coex_sta->under_lps)
- return true;
- }
- }
-
- if (!coex_sta->bt_disabled) {
- if (coex_sta->hid_busy_num != pre_hid_busy_num) {
- pre_hid_busy_num = coex_sta->hid_busy_num;
- return true;
- }
-
- if (bt_link_info->slave_role != pre_bt_slave) {
- pre_bt_slave = bt_link_info->slave_role;
- return true;
- }
-
- if (pre_hid_low_pri_tx_overhead !=
- coex_sta->is_hid_low_pri_tx_overhead) {
- pre_hid_low_pri_tx_overhead =
- coex_sta->is_hid_low_pri_tx_overhead;
- return true;
- }
-
- if (pre_bt_setup_link != coex_sta->is_setup_link) {
- pre_bt_setup_link = coex_sta->is_setup_link;
- return true;
- }
- }
-
- return false;
-}
-
-static void halbtc8822b1ant_update_bt_link_info(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool bt_hs_on = false;
- bool bt_busy = false;
-
- coex_sta->num_of_profile = 0;
-
- /* set link exist status */
- if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_FTP) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- } else {
- coex_sta->pan_exist = false;
- }
-
- if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_A2DP) {
- coex_sta->a2dp_exist = true;
- coex_sta->num_of_profile++;
- } else {
- coex_sta->a2dp_exist = false;
- }
-
- if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_HID) {
- coex_sta->hid_exist = true;
- coex_sta->num_of_profile++;
- } else {
- coex_sta->hid_exist = false;
- }
-
- if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) {
- coex_sta->sco_exist = true;
- coex_sta->num_of_profile++;
- } else {
- coex_sta->sco_exist = false;
- }
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
- bt_link_info->acl_busy = coex_sta->acl_busy;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist && !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist && bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist && !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist && !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist && bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-
- if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_INQ_PAGE) {
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_INQ_PAGE;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
- } else if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- } else if (coex_sta->bt_info == BT_INFO_8822B_1ANT_B_CONNECTION) {
- /* connection exists but no busy */
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- } else if (((coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) ||
- (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) &&
- (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY)) {
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
- } else if ((coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) ||
- (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_SCO_BUSY;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- } else if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY) {
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_BUSY;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- } else {
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_MAX;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- }
-
- if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY) ||
- (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY))
- bt_busy = true;
- else
- bt_busy = false;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-}
-
-static void halbtc8822b1ant_update_wifi_ch_info(struct btc_coexist *btcoexist,
- u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((type == BTC_MEDIA_CONNECT) && (wifi_central_chnl <= 14)) {
- /* enable BT AFH skip WL channel for 8822b
- * because BT Rx LO interference
- */
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = wifi_central_chnl;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (wifi_bw == BTC_WIFI_BW_HT40)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-}
-
-static u8 halbtc8822b1ant_action_algorithm(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool bt_hs_on = false;
- u8 algorithm = BT_8822B_1ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], No BT link exists!!!\n");
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT Profile = SCO only\n");
- algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT Profile = HID only\n");
- algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT Profile = A2DP only\n");
- algorithm = BT_8822B_1ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = PAN(HS) only\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANHS;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = PAN(EDR) only\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT Profile = SCO + HID\n");
- algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
- algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = SCO + PAN(HS)\n");
- algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = SCO + PAN(EDR)\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT Profile = HID + A2DP\n");
- algorithm = BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = HID + PAN(HS)\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = HID + PAN(EDR)\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = A2DP + PAN(HS)\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
- algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
- algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
-
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-static void halbtc8822b1ant_low_penalty_ra(struct btc_coexist *btcoexist,
- bool force_exec, bool low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
-
- if (low_penalty_ra)
- btcoexist->btc_phydm_modify_ra_pcr_threshold(btcoexist, 0, 25);
- else
- btcoexist->btc_phydm_modify_ra_pcr_threshold(btcoexist, 0, 0);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-static void halbtc8822b1ant_write_score_board(struct btc_coexist *btcoexist,
- u16 bitpos, bool state)
-{
- static u16 originalval = 0x8002;
-
- if (state)
- originalval = originalval | bitpos;
- else
- originalval = originalval & (~bitpos);
-
- btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
-}
-
-static void halbtc8822b1ant_read_score_board(struct btc_coexist *btcoexist,
- u16 *score_board_val)
-{
- *score_board_val =
- (btcoexist->btc_read_2byte(btcoexist, 0xaa)) & 0x7fff;
-}
-
-static void halbtc8822b1ant_post_state_to_bt(struct btc_coexist *btcoexist,
- u16 type, bool state)
-{
- halbtc8822b1ant_write_score_board(btcoexist, (u16)type, state);
-}
-
-static void
-halbtc8822b1ant_monitor_bt_enable_disable(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u32 bt_disable_cnt;
- bool bt_active = true, bt_disabled = false, wifi_under_5g = false;
- u16 u16tmp;
-
- /* This function check if bt is disabled */
-
- /* Read BT on/off status from scoreboard[1],
- * enable this only if BT patch support this feature
- */
- halbtc8822b1ant_read_score_board(btcoexist, &u16tmp);
-
- bt_active = u16tmp & BIT(1);
-
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- } else {
- bt_disable_cnt++;
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- bt_disable_cnt = 2;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if ((wifi_under_5g) || (bt_disabled))
- halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
- else
- halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true);
-
- if (coex_sta->bt_disabled != bt_disabled) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- coex_sta->bt_disabled = bt_disabled;
- }
-}
-
-static void halbtc8822b1ant_enable_gnt_to_gpio(struct btc_coexist *btcoexist,
- bool isenable)
-{
- static u8 bit_val[5] = {0, 0, 0, 0, 0};
- static bool state;
-
- if (!btcoexist->dbg_mode_1ant)
- return;
-
- if (state == isenable)
- return;
-
- state = isenable;
-
- if (isenable) {
- /* enable GNT_WL, GNT_BT to GPIO for debug */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
-
- /* store original value */
- bit_val[0] =
- (btcoexist->btc_read_1byte(btcoexist, 0x66) & BIT(4)) >>
- 4; /*0x66[4] */
- bit_val[1] = (btcoexist->btc_read_1byte(btcoexist, 0x67) &
- BIT(0)); /*0x66[8] */
- bit_val[2] =
- (btcoexist->btc_read_1byte(btcoexist, 0x42) & BIT(3)) >>
- 3; /*0x40[19] */
- bit_val[3] =
- (btcoexist->btc_read_1byte(btcoexist, 0x65) & BIT(7)) >>
- 7; /*0x64[15] */
- bit_val[4] =
- (btcoexist->btc_read_1byte(btcoexist, 0x72) & BIT(2)) >>
- 2; /*0x70[18] */
-
- /* switch GPIO Mux */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
- 0x0); /*0x66[4] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
- 0x0); /*0x66[8] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
- 0x0); /*0x40[19] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
- 0x0); /*0x64[15] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
- 0x0); /*0x70[18] = 0 */
-
- } else {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
-
- /* Restore original value */
- /* switch GPIO Mux */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
- bit_val[0]); /*0x66[4] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
- bit_val[1]); /*0x66[8] = 0 */
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x42, BIT(3), bit_val[2]); /*0x40[19] = 0 */
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x65, BIT(7), bit_val[3]); /*0x64[15] = 0 */
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x72, BIT(2), bit_val[4]); /*0x70[18] = 0 */
- }
-}
-
-static u32
-halbtc8822b1ant_ltecoex_indirect_read_reg(struct btc_coexist *btcoexist,
- u16 reg_addr)
-{
- u32 delay_count = 0;
-
- /* wait for ready bit before access 0x1700 */
- while (1) {
- if ((btcoexist->btc_read_1byte(btcoexist, 0x1703) & BIT(5)) ==
- 0) {
- mdelay(50);
- delay_count++;
- if (delay_count >= 10) {
- delay_count = 0;
- break;
- }
- } else {
- break;
- }
- }
-
- btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr);
-
- return btcoexist->btc_read_4byte(btcoexist, 0x1708); /* get read data */
-}
-
-static void
-halbtc8822b1ant_ltecoex_indirect_write_reg(struct btc_coexist *btcoexist,
- u16 reg_addr, u32 bit_mask,
- u32 reg_value)
-{
- u32 val, i = 0, bitpos = 0, delay_count = 0;
-
- if (bit_mask == 0x0)
- return;
-
- if (bit_mask == 0xffffffff) {
- /* wait for ready bit before access 0x1700/0x1704 */
- while (1) {
- if ((btcoexist->btc_read_1byte(btcoexist, 0x1703) &
- BIT(5)) == 0) {
- mdelay(50);
- delay_count++;
- if (delay_count >= 10) {
- delay_count = 0;
- break;
- }
- } else {
- break;
- }
- }
-
- btcoexist->btc_write_4byte(btcoexist, 0x1704,
- reg_value); /* put write data */
-
- btcoexist->btc_write_4byte(btcoexist, 0x1700,
- 0xc00F0000 | reg_addr);
- } else {
- for (i = 0; i <= 31; i++) {
- if (((bit_mask >> i) & 0x1) == 0x1) {
- bitpos = i;
- break;
- }
- }
-
- /* read back register value before write */
- val = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- reg_addr);
- val = (val & (~bit_mask)) | (reg_value << bitpos);
-
- /* wait for ready bit before access 0x1700/0x1704 */
- while (1) {
- if ((btcoexist->btc_read_1byte(btcoexist, 0x1703) &
- BIT(5)) == 0) {
- mdelay(50);
- delay_count++;
- if (delay_count >= 10) {
- delay_count = 0;
- break;
- }
- } else {
- break;
- }
- }
-
- btcoexist->btc_write_4byte(btcoexist, 0x1704,
- val); /* put write data */
-
- btcoexist->btc_write_4byte(btcoexist, 0x1700,
- 0xc00F0000 | reg_addr);
- }
-}
-
-static void halbtc8822b1ant_ltecoex_enable(struct btc_coexist *btcoexist,
- bool enable)
-{
- u8 val;
-
- val = (enable) ? 1 : 0;
- /* 0x38[7] */
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, val);
-}
-
-static void
-halbtc8822b1ant_ltecoex_pathcontrol_owner(struct btc_coexist *btcoexist,
- bool wifi_control)
-{
- u8 val;
-
- val = (wifi_control) ? 1 : 0;
- /* 0x70[26] */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, val);
-}
-
-static void halbtc8822b1ant_ltecoex_set_gnt_bt(struct btc_coexist *btcoexist,
- u8 control_block,
- bool sw_control, u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1)
- *0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0)
- *0x38=0x55xx(hw pta :gnt_wl /gnt_bt )
- */
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8822B_1ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0xc000;
- halbtc8822b1ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[15:14] */
- bit_mask = 0x0c00;
- halbtc8822b1ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
- case BT_8822B_1ANT_GNT_BLOCK_RFC:
- bit_mask = 0xc000;
- halbtc8822b1ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[15:14] */
- break;
- case BT_8822B_1ANT_GNT_BLOCK_BB:
- bit_mask = 0x0c00;
- halbtc8822b1ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
- }
-}
-
-static void halbtc8822b1ant_ltecoex_set_gnt_wl(struct btc_coexist *btcoexist,
- u8 control_block,
- bool sw_control, u8 state)
-{
- u32 val = 0, bit_mask;
- /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1)
- *0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0)
- *0x38=0x55xx(hw pta :gnt_wl /gnt_bt )
- */
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8822B_1ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0x3000;
- halbtc8822b1ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[13:12] */
- bit_mask = 0x0300;
- halbtc8822b1ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
- case BT_8822B_1ANT_GNT_BLOCK_RFC:
- bit_mask = 0x3000;
- halbtc8822b1ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[13:12] */
- break;
- case BT_8822B_1ANT_GNT_BLOCK_BB:
- bit_mask = 0x0300;
- halbtc8822b1ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
- }
-}
-
-static void
-halbtc8822b1ant_ltecoex_set_coex_table(struct btc_coexist *btcoexist,
- u8 table_type, u16 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8822B_1ANT_CTT_WL_VS_LTE:
- reg_addr = 0xa0;
- break;
- case BT_8822B_1ANT_CTT_BT_VS_LTE:
- reg_addr = 0xa4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8822b1ant_ltecoex_indirect_write_reg(
- btcoexist, reg_addr, 0xffff,
- table_content); /* 0xa0[15:0] or 0xa4[15:0] */
-}
-
-static void halbtc8822b1ant_set_wltoggle_coex_table(
- struct btc_coexist *btcoexist, bool force_exec, u8 interval,
- u8 val0x6c4_b0, u8 val0x6c4_b1, u8 val0x6c4_b2, u8 val0x6c4_b3)
-{
- static u8 pre_h2c_parameter[6] = {0};
- u8 cur_h2c_parameter[6] = {0};
- u8 i, match_cnt = 0;
-
- cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/
-
- cur_h2c_parameter[1] = interval;
- cur_h2c_parameter[2] = val0x6c4_b0;
- cur_h2c_parameter[3] = val0x6c4_b1;
- cur_h2c_parameter[4] = val0x6c4_b2;
- cur_h2c_parameter[5] = val0x6c4_b3;
-
- if (!force_exec) {
- for (i = 1; i <= 5; i++) {
- if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
- break;
-
- match_cnt++;
- }
-
- if (match_cnt == 5)
- return;
- }
-
- for (i = 1; i <= 5; i++)
- pre_h2c_parameter[i] = cur_h2c_parameter[i];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
-}
-
-static void halbtc8822b1ant_set_coex_table(struct btc_coexist *btcoexist,
- u32 val0x6c0, u32 val0x6c4,
- u32 val0x6c8, u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-static void halbtc8822b1ant_coex_table(struct btc_coexist *btcoexist,
- bool force_exec, u32 val0x6c0,
- u32 val0x6c4, u32 val0x6c8, u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8822b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-static void halbtc8822b1ant_coex_table_with_type(struct btc_coexist *btcoexist,
- bool force_exec, u8 type)
-{
- u32 break_table;
- u8 select_table;
-
- coex_sta->coex_table_type = type;
-
- if (coex_sta->concurrent_rx_mode_on) {
- break_table = 0xf0ffffff; /* set WL hi-pri can break BT */
- select_table = 0x3; /* set Tx response = Hi-Pri
- * (ex: Transmitting ACK,BA,CTS)
- */
- } else {
- break_table = 0xffffff;
- select_table = 0x3;
- }
-
- switch (type) {
- case 0:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0x55555555, break_table,
- select_table);
- break;
- case 1:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0x5a5a5a5a, break_table,
- select_table);
- break;
- case 2:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0xaa5a5a5a,
- 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 3:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 4:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0xaa555555,
- 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 5:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
- 0x5a5a5a5a, break_table,
- select_table);
- break;
- case 6:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 7:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0xaaaaaaaa,
- 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 8:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0xffffffff,
- 0xffffffff, break_table,
- select_table);
- break;
- case 9:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x5a5a5555,
- 0xaaaa5a5a, break_table,
- select_table);
- break;
- case 10:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0xaaaa5aaa,
- 0xaaaa5aaa, break_table,
- select_table);
- break;
- case 11:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0xaaaaa5aa,
- 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 12:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0xaaaaa5aa,
- 0xaaaaa5aa, break_table,
- select_table);
- break;
- case 13:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0xaaaa5a5a, break_table,
- select_table);
- break;
- case 14:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x5a5a555a,
- 0xaaaa5a5a, break_table,
- select_table);
- break;
- case 15:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0xaaaa55aa, break_table,
- select_table);
- break;
- case 16:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x5a5a555a,
- 0x5a5a555a, break_table,
- select_table);
- break;
- case 17:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0xaaaa55aa,
- 0xaaaa55aa, break_table,
- select_table);
- break;
- case 18:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0x5aaa5a5a, break_table,
- select_table);
- break;
- case 19:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0xa5555555,
- 0xaaaa5aaa, break_table,
- select_table);
- break;
- case 20:
- halbtc8822b1ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0xaaaa5aaa, break_table,
- select_table);
- break;
- default:
- break;
- }
-}
-
-static void
-halbtc8822b1ant_set_fw_ignore_wlan_act(struct btc_coexist *btcoexist,
- bool enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable)
- h2c_parameter[0] |= BIT(0); /* function enable */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-static void halbtc8822b1ant_ignore_wlan_act(struct btc_coexist *btcoexist,
- bool force_exec, bool enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act) {
- coex_dm->pre_ignore_wlan_act =
- coex_dm->cur_ignore_wlan_act;
- return;
- }
- }
-
- halbtc8822b1ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-static void halbtc8822b1ant_set_lps_rpwm(struct btc_coexist *btcoexist,
- u8 lps_val, u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-static void halbtc8822b1ant_lps_rpwm(struct btc_coexist *btcoexist,
- bool force_exec, u8 lps_val, u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8822b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-static void halbtc8822b1ant_ps_tdma_check_for_power_save_state(
- struct btc_coexist *btcoexist, bool new_ps_state)
-{
- u8 lps_mode = 0x0;
- u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0};
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
- h2c_parameter);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
- h2c_parameter);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-static bool halbtc8822b1ant_power_save_state(struct btc_coexist *btcoexist,
- u8 ps_type, u8 lps_val,
- u8 rpwm_val)
-{
- bool low_pwr_disable = false, result = true;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- coex_sta->force_lps_ctrl = false;
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
- break;
- case BTC_PS_LPS_ON:
-
- coex_sta->force_lps_ctrl = true;
- halbtc8822b1ant_ps_tdma_check_for_power_save_state(btcoexist,
- true);
- halbtc8822b1ant_lps_rpwm(btcoexist, NORMAL_EXEC, lps_val,
- rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
-
- break;
- case BTC_PS_LPS_OFF:
-
- coex_sta->force_lps_ctrl = true;
- halbtc8822b1ant_ps_tdma_check_for_power_save_state(btcoexist,
- false);
- result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
-
- break;
- default:
- break;
- }
-
- return result;
-}
-
-static void halbtc8822b1ant_set_fw_pstdma(struct btc_coexist *btcoexist,
- u8 byte1, u8 byte2, u8 byte3,
- u8 byte4, u8 byte5)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- bool ap_enable = false, result = false;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- if (byte5 & BIT(2))
- coex_sta->is_tdma_btautoslot = true;
- else
- coex_sta->is_tdma_btautoslot = false;
-
- /* release bt-auto slot for auto-slot hang is detected!! */
- if (coex_sta->is_tdma_btautoslot)
- if ((coex_sta->is_tdma_btautoslot_hang) ||
- (bt_link_info->slave_role))
- byte5 = byte5 & 0xfb;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == FW for 1Ant AP mode\n", __func__);
-
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
-
- halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == Force LPS (byte1 = 0x%x)\n",
- __func__, byte1);
- if (!halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_LPS_OFF,
- 0x50, 0x4))
- result = true;
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == native power save (byte1 = 0x%x)\n",
- __func__, byte1);
- halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- }
-
- coex_sta->is_set_ps_state_fail = result;
-
- if (!coex_sta->is_set_ps_state_fail) {
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-
- } else {
- coex_sta->cnt_set_ps_state_fail++;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == Force Leave LPS Fail (cnt = %d)\n",
- __func__, coex_sta->cnt_set_ps_state_fail);
- }
-}
-
-static void halbtc8822b1ant_ps_tdma(struct btc_coexist *btcoexist,
- bool force_exec, bool turn_on, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool wifi_busy = false;
- static u8 ps_tdma_byte4_modify, pre_ps_tdma_byte4_modify;
- static bool pre_wifi_busy;
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (wifi_busy != pre_wifi_busy) {
- force_exec = true;
- pre_wifi_busy = wifi_busy;
- }
-
- /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
- if (bt_link_info->slave_role)
- ps_tdma_byte4_modify = 0x1;
- else
- ps_tdma_byte4_modify = 0x0;
-
- if (pre_ps_tdma_byte4_modify != ps_tdma_byte4_modify) {
- force_exec = true;
- pre_ps_tdma_byte4_modify = ps_tdma_byte4_modify;
- }
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n",
- (coex_dm->cur_ps_tdma_on ? "on" : "off"),
- coex_dm->cur_ps_tdma);
- return;
- }
- }
-
- if (coex_dm->cur_ps_tdma_on) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** TDMA(on, %d) **********\n",
- coex_dm->cur_ps_tdma);
-
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x550, 0x8, 0x1); /* enable TBTT nterrupt */
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** TDMA(off, %d) **********\n",
- coex_dm->cur_ps_tdma);
- }
-
- if (turn_on) {
- /* enable TBTT nterrupt */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1);
-
- switch (type) {
- default:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x35,
- 0x03, 0x11, 0x11);
- break;
- case 1:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x3a,
- 0x03, 0x11, 0x10);
- break;
- case 3:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x30,
- 0x03, 0x10, 0x50);
- break;
- case 4:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x21,
- 0x03, 0x10, 0x50);
- break;
- case 5:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x15,
- 0x3, 0x11, 0x11);
- break;
- case 6:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x20,
- 0x3, 0x11, 0x10);
- break;
- case 7:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x51, 0x10, 0x03, 0x10,
- 0x54 | ps_tdma_byte4_modify);
- break;
- case 8:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x51, 0x10, 0x03, 0x10,
- 0x14 | ps_tdma_byte4_modify);
- break;
- case 11:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x61, 0x25, 0x03, 0x11,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 12:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x51, 0x30, 0x03, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
- case 13:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x51, 0x10, 0x07, 0x10,
- 0x54 | ps_tdma_byte4_modify);
- break;
- case 14:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x51, 0x15, 0x03, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
- case 15:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x51, 0x20, 0x03, 0x10,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 17:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x61, 0x10, 0x03, 0x11,
- 0x14 | ps_tdma_byte4_modify);
- break;
- case 18:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x51, 0x10, 0x03, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
-
- case 20:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x30,
- 0x03, 0x11, 0x10);
- break;
- case 22:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x25,
- 0x03, 0x11, 0x10);
- break;
- case 27:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x10,
- 0x03, 0x11, 0x15);
- break;
- case 32:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x35,
- 0x3, 0x11, 0x11);
- break;
- case 33:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x35,
- 0x03, 0x11, 0x10);
- break;
- case 41:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x45,
- 0x3, 0x11, 0x11);
- break;
- case 42:
- halbtc8822b1ant_set_fw_pstdma(
- btcoexist, 0x51, 0x1e, 0x3, 0x10,
- 0x14 | ps_tdma_byte4_modify);
- break;
- case 43:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x45,
- 0x3, 0x10, 0x14);
- break;
- case 44:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x25,
- 0x3, 0x10, 0x10);
- break;
- case 45:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x29,
- 0x3, 0x10, 0x10);
- break;
- case 46:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x1a,
- 0x3, 0x10, 0x10);
- break;
- case 47:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x32,
- 0x3, 0x10, 0x10);
- break;
- case 48:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x29,
- 0x3, 0x10, 0x10);
- break;
- case 49:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x55, 0x10,
- 0x3, 0x10, 0x54);
- break;
- case 50:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x51, 0x4a,
- 0x3, 0x10, 0x10);
- break;
- case 51:
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x61, 0x35,
- 0x3, 0x10, 0x11);
- break;
- }
- } else {
- switch (type) {
- case 0:
- default: /* Software control, Antenna at BT side */
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0,
- 0x0, 0x0);
- break;
- case 8: /* PTA Control */
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x8, 0x0, 0x0,
- 0x0, 0x0);
- break;
- case 9: /* Software control, Antenna at WiFi side */
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0,
- 0x0, 0x0);
- break;
- case 10: /* under 5G , 0x778=1*/
- halbtc8822b1ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0,
- 0x0, 0x0);
-
- break;
- }
- }
-
- if (!coex_sta->is_set_ps_state_fail) {
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
- }
-}
-
-static void halbtc8822b1ant_sw_mechanism(struct btc_coexist *btcoexist,
- bool low_penalty_ra)
-{
- halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-/* rf4 type by efuse, and for ant at main aux inverse use,
- * because is 2x2, and control types are the same, does not need
- */
-
-static void halbtc8822b1ant_set_rfe_type(struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
-
- /* the following setup should be got from Efuse in the future */
- rfe_type->rfe_module_type = board_info->rfe_type;
-
- rfe_type->ext_ant_switch_ctrl_polarity = 0;
-
- switch (rfe_type->rfe_module_type) {
- case 0:
- default:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 1:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 2:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 3:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 4:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 5:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 6:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 7:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- }
-}
-
-/*anttenna control by bb mac bt antdiv pta to write 0x4c 0xcb4,0xcbd*/
-
-static void halbtc8822b1ant_set_ext_ant_switch(struct btc_coexist *btcoexist,
- bool force_exec, u8 ctrl_type,
- u8 pos_type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool switch_polatiry_inverse = false;
- u8 regval_0xcbd = 0, regval_0x64;
- u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
-
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
-
- if (!rfe_type->ext_ant_switch_exist)
- return;
-
- coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type;
-
- if (!force_exec) {
- if (coex_dm->pre_ext_ant_switch_status ==
- coex_dm->cur_ext_ant_switch_status)
- return;
- }
-
- coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status;
-
- /* swap control polarity if use different switch control polarity*/
- /* Normal switch polarity for SPDT,
- * 0xcbd[1:0] = 2b'01 => Ant to BTG,
- * 0xcbd[1:0] = 2b'10 => Ant to WLG
- */
- switch_polatiry_inverse = rfe_type->ext_ant_switch_ctrl_polarity == 1;
-
- switch (pos_type) {
- default:
- case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT:
- case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE:
-
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG:
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA:
- break;
- }
-
- if (rfe_type->ext_ant_switch_type ==
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT) {
- switch (ctrl_type) {
- default:
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW:
- /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
- 0x80, 0x0);
- /* 0x4c[24] = 1 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
- 0x01, 0x1);
- /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4,
- 0xff, 0x77);
-
- /* 0xcbd[1:0] = 2b'01 for no switch_polatiry_inverse,
- * ANTSWB =1, ANTSW =0
- */
- regval_0xcbd = (!switch_polatiry_inverse ? 0x1 : 0x2);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
- 0x3, regval_0xcbd);
-
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA:
- /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
- 0x80, 0x0);
- /* 0x4c[24] = 1 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
- 0x01, 0x1);
- /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4,
- 0xff, 0x66);
-
- /* 0xcbd[1:0] = 2b'10 for no switch_polatiry_inverse,
- * ANTSWB =1, ANTSW =0 @ GNT_BT=1
- */
- regval_0xcbd = (!switch_polatiry_inverse ? 0x2 : 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
- 0x3, regval_0xcbd);
-
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV:
- /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
- 0x80, 0x0);
- /* 0x4c[24] = 1 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
- 0x01, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4,
- 0xff, 0x88);
-
- /* no regval_0xcbd setup required, because
- * antenna switch control value by antenna diversity
- */
-
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC:
- /* 0x4c[23] = 1 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
- 0x80, 0x1);
-
- /* 0x64[0] = 1b'0 for no switch_polatiry_inverse,
- * DPDT_SEL_N =1, DPDT_SEL_P =0
- */
- regval_0x64 = (!switch_polatiry_inverse ? 0x0 : 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1,
- regval_0x64);
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT:
- /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
- 0x80, 0x0);
- /* 0x4c[24] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
- 0x01, 0x0);
-
- /* no setup required, because antenna switch control
- * value by BT vendor 0xac[1:0]
- */
- break;
- }
- }
-
- u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcbc);
- u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (After Ext Ant switch setup) 0xcbc = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x**********\n",
- u32tmp1, u32tmp2, u32tmp3);
-}
-
-/* set gnt_wl gnt_bt control by sw high low, or
- * hwpta while in power on, ini, wlan off, wlan only, wl2g non-currrent,
- * wl2g current, wl5g
- */
-
-static void halbtc8822b1ant_set_ant_path(struct btc_coexist *btcoexist,
- u8 ant_pos_type, bool force_exec,
- u8 phase)
-
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 u8tmp = 0;
- u32 u32tmp1 = 0;
- u32 u32tmp2 = 0, u32tmp3 = 0;
-
- u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
-
- /* To avoid indirect access fail */
- if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
- force_exec = true;
- coex_sta->gnt_error_cnt++;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex],(Before Ant Setup) 0x38= 0x%x\n", u32tmp1);
- }
-
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
-
- coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase;
-
- if (!force_exec) {
- if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type)
- return;
- }
-
- coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
-
- if (btcoexist->dbg_mode_1ant) {
- u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x38);
- u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x54);
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
-
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u32tmp3, u8tmp, u32tmp1, u32tmp2);
- }
-
- switch (phase) {
- case BT_8822B_1ANT_PHASE_COEX_INIT:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_COEX_INIT) **********\n");
-
- /* Disable LTE Coex Function in WiFi side
- * (this should be on if LTE coex is required)
- */
- halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* GNT_WL_LTE always = 1
- * (this should be config if LTE coex is required)
- */
- halbtc8822b1ant_ltecoex_set_coex_table(
- btcoexist, BT_8822B_1ANT_CTT_WL_VS_LTE, 0xffff);
-
- /* GNT_BT_LTE always = 1
- * (this should be config if LTE coex is required)
- */
- halbtc8822b1ant_ltecoex_set_coex_table(
- btcoexist, BT_8822B_1ANT_CTT_BT_VS_LTE, 0xffff);
-
- /* set GNT_BT to SW high */
- halbtc8822b1ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* set GNT_WL to SW low */
- halbtc8822b1ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
-
- /* set Path control owner to WL at initial step */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = false;
-
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
-
- if (ant_pos_type == BTC_ANT_PATH_AUTO)
- ant_pos_type = BTC_ANT_PATH_BT;
-
- break;
- case BT_8822B_1ANT_PHASE_WLANONLY_INIT:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLANONLY_INIT) **********\n");
-
- /* Disable LTE Coex Function in WiFi side
- * (this should be on if LTE coex is required)
- */
- halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* GNT_WL_LTE always = 1
- * (this should be config if LTE coex is required)
- */
- halbtc8822b1ant_ltecoex_set_coex_table(
- btcoexist, BT_8822B_1ANT_CTT_WL_VS_LTE, 0xffff);
-
- /* GNT_BT_LTE always = 1
- * (this should be config if LTE coex is required)
- */
- halbtc8822b1ant_ltecoex_set_coex_table(
- btcoexist, BT_8822B_1ANT_CTT_BT_VS_LTE, 0xffff);
-
- /* set GNT_BT to SW Low */
- halbtc8822b1ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
-
- /* Set GNT_WL to SW high */
- halbtc8822b1ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* set Path control owner to WL at initial step */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = false;
-
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
-
- if (ant_pos_type == BTC_ANT_PATH_AUTO)
- ant_pos_type = BTC_ANT_PATH_WIFI;
-
- break;
- case BT_8822B_1ANT_PHASE_WLAN_OFF:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLAN_OFF) **********\n");
-
- /* Disable LTE Coex Function in WiFi side */
- halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* set Path control owner to BT */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_1ANT_PCO_BTSIDE);
-
- /* Set Ext Ant Switch to BT control at wifi off step */
- halbtc8822b1ant_set_ext_ant_switch(
- btcoexist, FORCE_EXEC,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE);
-
- coex_sta->run_time_state = false;
-
- break;
- case BT_8822B_1ANT_PHASE_2G_RUNTIME:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_2G_RUNTIME) **********\n");
-
- /* set GNT_BT to PTA */
- halbtc8822b1ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_PTA,
- BT_8822B_1ANT_SIG_STA_SET_BY_HW);
-
- /* Set GNT_WL to PTA */
- halbtc8822b1ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_PTA,
- BT_8822B_1ANT_SIG_STA_SET_BY_HW);
-
- /* set Path control owner to WL at runtime step */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = true;
-
- if (ant_pos_type == BTC_ANT_PATH_AUTO)
- ant_pos_type = BTC_ANT_PATH_PTA;
-
- break;
- case BT_8822B_1ANT_PHASE_5G_RUNTIME:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_5G_RUNTIME) **********\n");
-
- /* set GNT_BT to SW Hi */
- halbtc8822b1ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* Set GNT_WL to SW Hi */
- halbtc8822b1ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* set Path control owner to WL at runtime step */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = true;
-
- if (ant_pos_type == BTC_ANT_PATH_AUTO)
- ant_pos_type = BTC_ANT_PATH_WIFI5G;
-
- break;
- case BT_8822B_1ANT_PHASE_BTMPMODE:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_BTMPMODE) **********\n");
-
- /* Disable LTE Coex Function in WiFi side */
- halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* set GNT_BT to SW Hi */
- halbtc8822b1ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* Set GNT_WL to SW Lo */
- halbtc8822b1ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
-
- /* set Path control owner to WL */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = false;
-
- /* Set Ext Ant Switch to BT side at BT MP mode */
- if (ant_pos_type == BTC_ANT_PATH_AUTO)
- ant_pos_type = BTC_ANT_PATH_BT;
-
- break;
- }
-
- if (phase != BT_8822B_1ANT_PHASE_WLAN_OFF) {
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- halbtc8822b1ant_set_ext_ant_switch(
- btcoexist, force_exec,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG);
- break;
- case BTC_ANT_PATH_WIFI5G:
- halbtc8822b1ant_set_ext_ant_switch(
- btcoexist, force_exec,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA);
- break;
- case BTC_ANT_PATH_BT:
- halbtc8822b1ant_set_ext_ant_switch(
- btcoexist, force_exec,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT);
- break;
- default:
- case BTC_ANT_PATH_PTA:
- halbtc8822b1ant_set_ext_ant_switch(
- btcoexist, force_exec,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE);
- break;
- }
- }
-
- if (btcoexist->dbg_mode_1ant) {
- u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x38);
- u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x54);
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
-
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (After Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u32tmp3, u8tmp, u32tmp1, u32tmp2);
- }
-}
-
-static bool halbtc8822b1ant_is_common_action(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool common = false, wifi_connected = false, wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected &&
- coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (coex_dm->bt_status ==
- BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected && (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected && (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected && (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE !=
- coex_dm->bt_status)) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else {
- if (wifi_busy) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- }
-
- common = false;
- }
-
- return common;
-}
-
-static void halbtc8822b1ant_action_wifi_under5g(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], under 5g start\n");
- /* for test : s3 bt disappear , fail rate 1/600*/
- /*set sw gnt wl bt high*/
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_1ANT_PHASE_5G_RUNTIME);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1);
-}
-
-static void halbtc8822b1ant_action_wifi_only(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_under_5g = false, rf4ce_enabled = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (wlan only -- under 5g ) **********\n");
- return;
- }
-
- if (rf4ce_enabled) {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 50);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- return;
- }
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
- halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (wlan only -- under 2g ) **********\n");
-}
-
-static void
-halbtc8822b1ant_action_wifi_native_lps(struct btc_coexist *btcoexist)
-{
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-}
-
-/* *********************************************
- *
- * Non-Software Coex Mechanism start
- *
- * **********************************************/
-
-static void halbtc8822b1ant_action_bt_whck_test(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex],action_bt_whck_test\n");
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-static void
-halbtc8822b1ant_action_wifi_multi_port(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex],action_wifi_multi_port\n");
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-static void halbtc8822b1ant_action_hs(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "[BTCoex], action_hs\n");
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-}
-
-static void halbtc8822b1ant_action_bt_relink(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], run bt multi link function\n");
-
- if (coex_sta->is_bt_multi_link)
- return;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], run bt_re-link function\n");
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-/*"""bt inquiry"""" + wifi any + bt any*/
-
-static void halbtc8822b1ant_action_bt_inquiry(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool wifi_connected = false, ap_enable = false, wifi_busy = false,
- bt_busy = false, rf4ce_enabled = false;
-
- bool wifi_scan = false, link = false, roam = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (bt inquiry) **********\n");
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** scan = %d, link =%d, roam = %d**********\n",
- wifi_scan, link, roam);
-
- if ((link) || (roam) || (coex_sta->wifi_is_high_pri_task)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (bt inquiry wifi connect or scan ) **********\n");
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((wifi_scan) && (coex_sta->bt_create_connection)) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((!wifi_connected) && (!wifi_scan)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (bt inquiry wifi non connect) **********\n");
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
- } else if (wifi_scan) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (wifi_busy) {
- /* for BT inquiry/page fail after S4 resume */
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- /*aaaa->55aa for bt connect while wl busy*/
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 15);
- if (rf4ce_enabled) {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e,
- 0x8, 0x1);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 50);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
- }
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (bt inquiry wifi connect) **********\n");
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- }
-}
-
-static void
-halbtc8822b1ant_action_bt_sco_hid_only_busy(struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool wifi_connected = false, wifi_busy = false;
- u32 wifi_bw = 1;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (bt_link_info->sco_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else {
- if (coex_sta->is_hid_low_pri_tx_overhead) {
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 6);
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 18);
- } else if (wifi_bw == 0) { /* if 11bg mode */
-
- if (coex_sta->is_bt_multi_link) {
- halbtc8822b1ant_coex_table_with_type(
- btcoexist, NORMAL_EXEC, 11);
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 11);
- } else {
- halbtc8822b1ant_coex_table_with_type(
- btcoexist, NORMAL_EXEC, 6);
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 11);
- }
- } else {
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 6);
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 11);
- }
- }
-}
-
-static void
-halbtc8822b1ant_action_wifi_connected_bt_acl_busy(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool wifi_busy = false, wifi_turbo = false;
- u32 wifi_bw = 1;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n",
- coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
-
- if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
- wifi_turbo = true;
-
- if ((coex_sta->bt_relink_downcount != 0) &&
- (!bt_link_info->pan_exist) && (wifi_busy)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Re-Link + A2DP + WL busy\n");
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 12);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
- } else if (bt_link_info->a2dp_only) { /* A2DP */
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 7);
-
- if (wifi_turbo)
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 19);
- else
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
- (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist)) {
- /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
-
- if (wifi_busy)
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 13);
- else
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
-
- if (bt_link_info->hid_exist)
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- else if (wifi_turbo)
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 19);
- else
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) { /* HID+A2DP */
-
- if (wifi_bw == 0) { /* if 11bg mode */
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- halbtc8822b1ant_set_wltoggle_coex_table(
- btcoexist, NORMAL_EXEC, 1, 0xaa, 0x5a, 0xaa,
- 0xaa);
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 49);
- } else {
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, true, 8);
- halbtc8822b1ant_set_wltoggle_coex_table(
- btcoexist, NORMAL_EXEC, 1, 0xaa, 0x5a, 0xaa,
- 0xaa);
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 49);
- }
- /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
-
- } else if ((bt_link_info->pan_only) ||
- (bt_link_info->hid_exist && bt_link_info->pan_exist)) {
- if (!wifi_busy)
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 4);
- else
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 3);
-
- if (bt_link_info->hid_exist)
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- else if (wifi_turbo)
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 19);
- else
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- /* BT no-profile busy (0x9) */
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- }
-}
-
-/*wifi not connected + bt action*/
-
-static void
-halbtc8822b1ant_action_wifi_not_connected(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool rf4ce_enabled = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (wifi not connect) **********\n");
-
- /* tdma and coex table */
- if (rf4ce_enabled) {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 50);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- return;
- }
- halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-/*""""wl not connected scan"""" + bt action*/
-static void
-halbtc8822b1ant_action_wifi_not_connected_scan(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- bool bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (wifi non connect scan) **********\n");
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Is Inquirying\n");
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else {
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
- }
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) {
- if (bt_link_info->a2dp_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- }
- } else if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- }
-}
-
-/*""""wl not connected asso"""" + bt action*/
-
-static void halbtc8822b1ant_action_wifi_not_connected_asso_auth(
- struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- bool bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (wifi non connect asso_auth) **********\n");
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Is Inquirying\n");
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else {
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
- }
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
- }
-}
-
-/*""""wl connected scan"""" + bt action*/
-
-static void
-halbtc8822b1ant_action_wifi_connected_scan(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- bool bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (wifi connect scan) **********\n");
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Is Inquirying\n");
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else {
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
- }
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) {
- if (bt_link_info->a2dp_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- }
- } else if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
- }
-}
-
-/*""""wl connected specific packet"""" + bt action*/
-
-static void halbtc8822b1ant_action_wifi_connected_specific_packet(
- struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- bool bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
- bool wifi_busy = false;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (wifi connect specific packet) **********\n");
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Is Inquirying\n");
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else {
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
- }
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* no specific packet process for both WiFi and BT very busy */
- if ((wifi_busy) &&
- ((bt_link_info->pan_exist) || (coex_sta->num_of_profile >= 2)))
- return;
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else if (bt_link_info->a2dp_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- /*for a2dp glitch,change from 1 to 15*/
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 15);
- } else if (bt_link_info->pan_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- }
-}
-
-/* wifi connected input point:
- * to set different ps and tdma case (+bt different case)
- */
-
-static void halbtc8822b1ant_action_wifi_connected(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_busy = false, rf4ce_enabled = false;
- bool scan = false, link = false, roam = false;
- bool under_4way = false, ap_enable = false, wifi_under_5g = false;
- u8 wifi_rssi_state;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], CoexForWifiConnect()===>\n");
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if (wifi_under_5g) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 5g<===\n");
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
-
- return;
- }
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 2g<===\n");
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (under_4way) {
- halbtc8822b1ant_action_wifi_connected_specific_packet(
- btcoexist);
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- if (scan || link || roam) {
- if (scan)
- halbtc8822b1ant_action_wifi_connected_scan(btcoexist);
- else
- halbtc8822b1ant_action_wifi_connected_specific_packet(
- btcoexist);
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* tdma and coex table */
- if (!wifi_busy) {
- if (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) {
- halbtc8822b1ant_action_wifi_connected_bt_acl_busy(
- btcoexist);
- } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
-
- halbtc8822b1ant_set_ant_path(
- btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- if ((coex_sta->high_priority_tx) +
- (coex_sta->high_priority_rx) <=
- 60)
- /*sy modify case16 -> case17*/
- halbtc8822b1ant_coex_table_with_type(
- btcoexist, NORMAL_EXEC, 1);
- else
- halbtc8822b1ant_coex_table_with_type(
- btcoexist, NORMAL_EXEC, 1);
- }
- } else {
- if (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) {
- halbtc8822b1ant_action_wifi_connected_bt_acl_busy(
- btcoexist);
- } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist);
- } else {
- if (rf4ce_enabled) {
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x45e, 0x8, 0x1);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 50);
-
- halbtc8822b1ant_coex_table_with_type(
- btcoexist, NORMAL_EXEC, 1);
- return;
- }
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
-
- halbtc8822b1ant_set_ant_path(
- btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- wifi_rssi_state = halbtc8822b1ant_wifi_rssi_state(
- btcoexist, 1, 2, 25, 0);
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** before **********\n");
- if (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- if (rf4ce_enabled) {
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x45e, 0x8, 0x1);
-
- halbtc8822b1ant_ps_tdma(btcoexist,
- NORMAL_EXEC,
- true, 50);
-
- halbtc8822b1ant_coex_table_with_type(
- btcoexist, NORMAL_EXEC, 1);
- return;
- }
-
- halbtc8822b1ant_coex_table_with_type(
- btcoexist, NORMAL_EXEC, 1);
- } else {
- halbtc8822b1ant_coex_table_with_type(
- btcoexist, NORMAL_EXEC, 1);
- }
- }
- }
-}
-
-static void
-halbtc8822b1ant_run_sw_coexist_mechanism(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 algorithm = 0;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (run sw coexmech) **********\n");
- algorithm = halbtc8822b1ant_action_algorithm(btcoexist);
- coex_dm->cur_algorithm = algorithm;
-
- if (halbtc8822b1ant_is_common_action(btcoexist)) {
- } else {
- switch (coex_dm->cur_algorithm) {
- case BT_8822B_1ANT_COEX_ALGO_SCO:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = SCO.\n");
- break;
- case BT_8822B_1ANT_COEX_ALGO_HID:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = HID.\n");
- break;
- case BT_8822B_1ANT_COEX_ALGO_A2DP:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = A2DP.\n");
- break;
- case BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
- break;
- case BT_8822B_1ANT_COEX_ALGO_PANEDR:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = PAN(EDR).\n");
- break;
- case BT_8822B_1ANT_COEX_ALGO_PANHS:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = HS mode.\n");
- break;
- case BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = PAN+A2DP.\n");
- break;
- case BT_8822B_1ANT_COEX_ALGO_PANEDR_HID:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
- break;
- case BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
- break;
- case BT_8822B_1ANT_COEX_ALGO_HID_A2DP:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = HID+A2DP.\n");
- break;
- default:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action algorithm = coexist All Off!!\n");
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-static void halbtc8822b1ant_run_coexist_mechanism(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool wifi_connected = false, bt_hs_on = false;
- bool increase_scan_dev_num = false;
- bool bt_ctrl_agg_buf_size = false;
- bool miracast_plus_bt = false;
- u8 agg_buf_size = 5;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0, wifi_bw;
- u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
- bool wifi_under_5g = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RunCoexistMechanism()===>\n");
-
- if (btcoexist->manual_control) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- return;
- }
-
- if (coex_sta->under_ips) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], wifi is under IPS !!!\n");
- return;
- }
-
- if ((coex_sta->under_lps) &&
- (coex_dm->bt_status != BT_8822B_1ANT_BT_STATUS_ACL_BUSY)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n");
- halbtc8822b1ant_action_wifi_native_lps(btcoexist);
- return;
- }
-
- if (!coex_sta->run_time_state) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], return for run_time_state = false !!!\n");
- return;
- }
-
- if (coex_sta->freeze_coexrun_by_btinfo) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n");
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], WiFi is under 5G!!!\n");
- return;
- }
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], WiFi is under 2G!!!\n");
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- if (coex_sta->bt_whck_test) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- halbtc8822b1ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- if (coex_sta->bt_disabled) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is disabled !!!\n");
- halbtc8822b1ant_action_wifi_only(btcoexist);
- return;
- }
-
- if (coex_sta->is_setup_link) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is re-link !!!\n");
- halbtc8822b1ant_action_bt_relink(btcoexist);
- return;
- }
-
- if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY) ||
- (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY))
- increase_scan_dev_num = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
- &increase_scan_dev_num);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
-
- if (bt_link_info->bt_link_exist) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
- 0, 1);
- miracast_plus_bt = true;
- } else {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
- 0, 0);
- miracast_plus_bt = false;
- }
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if ((bt_link_info->a2dp_exist) &&
- (coex_sta->c2h_bt_inquiry_page)) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Is Inquirying\n");
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else {
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
- }
-
- return;
- }
-
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
-
- if (iot_peer != BTC_IOT_PEER_CISCO) {
- if (bt_link_info->sco_exist)
- halbtc8822b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, true,
- false, 0x5);
- else
- halbtc8822b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false,
- false, 0x5);
- } else {
- if (bt_link_info->sco_exist) {
- halbtc8822b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, true,
- false, 0x5);
- } else {
- if (wifi_bw == BTC_WIFI_BW_HT40)
- halbtc8822b1ant_limited_rx(
- btcoexist, NORMAL_EXEC, false,
- true, 0x10);
- else
- halbtc8822b1ant_limited_rx(
- btcoexist, NORMAL_EXEC, false,
- true, 0x8);
- }
- }
-
- halbtc8822b1ant_sw_mechanism(btcoexist, true);
- halbtc8822b1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- } else {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x5);
-
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
- halbtc8822b1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Is Inquirying\n");
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
- if (!wifi_connected) {
- bool scan = false, link = false, roam = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], wifi is non connected-idle !!!\n");
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan)
- halbtc8822b1ant_action_wifi_not_connected_scan(
- btcoexist);
- else if (link || roam)
- halbtc8822b1ant_action_wifi_not_connected_asso_auth(
- btcoexist);
- else
- halbtc8822b1ant_action_wifi_not_connected(btcoexist);
- } else { /* wifi LPS/Busy */
- halbtc8822b1ant_action_wifi_connected(btcoexist);
- }
-}
-
-static void halbtc8822b1ant_init_coex_dm(struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
-
- halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
-
- /* sw all off */
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
-
- coex_sta->pop_event_cnt = 0;
-}
-
-static void halbtc8822b1ant_init_hw_config(struct btc_coexist *btcoexist,
- bool back_up, bool wifi_only)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 u8tmp = 0, i = 0;
- u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
-
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u32tmp3, u32tmp1, u32tmp2);
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], 1Ant Init HW Config!!\n");
-
- coex_sta->bt_coex_supported_feature = 0;
- coex_sta->bt_coex_supported_version = 0;
- coex_sta->bt_ble_scan_type = 0;
- coex_sta->bt_ble_scan_para[0] = 0;
- coex_sta->bt_ble_scan_para[1] = 0;
- coex_sta->bt_ble_scan_para[2] = 0;
- coex_sta->bt_reg_vendor_ac = 0xffff;
- coex_sta->bt_reg_vendor_ae = 0xffff;
- coex_sta->isolation_btween_wb = BT_8822B_1ANT_DEFAULT_ISOLATION;
- coex_sta->gnt_error_cnt = 0;
- coex_sta->bt_relink_downcount = 0;
- coex_sta->is_set_ps_state_fail = false;
- coex_sta->cnt_set_ps_state_fail = 0;
-
- for (i = 0; i <= 9; i++)
- coex_sta->bt_afh_map[i] = 0;
-
- /* Setup RF front end type */
- halbtc8822b1ant_set_rfe_type(btcoexist);
-
- /* 0xf0[15:12] --> Chip Cut information */
- coex_sta->cut_version =
- (btcoexist->btc_read_1byte(btcoexist, 0xf1) & 0xf0) >> 4;
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
-
- /* BT report packet sample rate */
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-
- /* Enable BT counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
-
- /* Enable PTA (3-wire function form BT side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
-
- /* Enable PTA (tx/rx signal form WiFi side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
- /*GNT_BT=1 while select both */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1);
-
- /* enable GNT_WL */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
-
- if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ONOFF, true);
-
- /* Antenna config */
- if (coex_sta->is_rf_state_off) {
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLAN_OFF);
-
- btcoexist->stop_coex_dm = true;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** %s (RF Off)**********\n",
- __func__);
- } else if (wifi_only) {
- coex_sta->concurrent_rx_mode_on = false;
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLANONLY_INIT);
- } else {
- coex_sta->concurrent_rx_mode_on = true;
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_COEX_INIT);
- }
-
- /* PTA parameter */
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, true);
-}
-
-void ex_btc8822b1ant_power_on_setting(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x0;
- u16 u16tmp = 0x0;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "xxxxxxxxxxxxxxxx Execute 8822b 1-Ant PowerOn Setting!! xxxxxxxxxxxxxxxx\n");
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "Ant Det Finish = %s, Ant Det Number = %d\n",
- board_info->btdm_ant_det_finish ? "Yes" : "No",
- board_info->btdm_ant_num_by_ant_det);
-
- btcoexist->dbg_mode_1ant = false;
- btcoexist->stop_coex_dm = true;
-
- /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
- btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
-
- /* set Path control owner to WiFi */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8822B_1ANT_PCO_WLSIDE);
-
- /* set GNT_BT to high */
- halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to low */
- halbtc8822b1ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW, BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
-
- /* set WLAN_ACT = 0 */
- /* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); */
-
- /* SD1 Chunchu red x issue */
- btcoexist->btc_write_1byte(btcoexist, 0xff1a, 0x0);
-
- halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, true);
-
- /* */
- /* S0 or S1 setting and Local register setting
- * (By the setting fw can get ant number, S0/S1, ... info)
- */
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==>
- * BIT1=0 and BIT2=0
- */
-
- u8tmp = 0;
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
-
- if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
-}
-
-void ex_btc8822b1ant_pre_load_firmware(struct btc_coexist *btcoexist) {}
-
-void ex_btc8822b1ant_init_hw_config(struct btc_coexist *btcoexist,
- bool wifi_only)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (ini hw config) **********\n");
-
- halbtc8822b1ant_init_hw_config(btcoexist, true, wifi_only);
- btcoexist->stop_coex_dm = false;
- btcoexist->auto_report_1ant = true;
-}
-
-void ex_btc8822b1ant_init_coex_dm(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Coex Mechanism Init!!\n");
-
- btcoexist->stop_coex_dm = false;
-
- halbtc8822b1ant_init_coex_dm(btcoexist);
-
- halbtc8822b1ant_query_bt_info(btcoexist);
-}
-
-void ex_btc8822b1ant_display_coex_info(struct btc_coexist *btcoexist,
- struct seq_file *m)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- u8 u8tmp[4], i, ps_tdma_case = 0;
- u16 u16tmp[4];
- u32 u32tmp[4];
- u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck;
- u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
- static u8 pop_report_in_10s;
- u32 phyver = 0;
- bool lte_coex_on = false;
- static u8 cnt;
-
- seq_puts(m, "\r\n ============[BT Coexist info]============");
-
- if (btcoexist->manual_control) {
- seq_puts(m,
- "\r\n ============[Under Manual Control]============");
- seq_puts(m, "\r\n ==========================================");
- }
- if (btcoexist->stop_coex_dm) {
- seq_puts(m, "\r\n ============[Coex is STOPPED]============");
- seq_puts(m, "\r\n ==========================================");
- }
-
- if (!coex_sta->bt_disabled) {
- if (coex_sta->bt_coex_supported_feature == 0)
- btcoexist->btc_get(
- btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
- &coex_sta->bt_coex_supported_feature);
-
- if ((coex_sta->bt_coex_supported_version == 0) ||
- (coex_sta->bt_coex_supported_version == 0xffff))
- btcoexist->btc_get(
- btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
- &coex_sta->bt_coex_supported_version);
-
- if (coex_sta->bt_reg_vendor_ac == 0xffff)
- coex_sta->bt_reg_vendor_ac = (u16)(
- btcoexist->btc_get_bt_reg(btcoexist, 3, 0xac) &
- 0xffff);
-
- if (coex_sta->bt_reg_vendor_ae == 0xffff)
- coex_sta->bt_reg_vendor_ae = (u16)(
- btcoexist->btc_get_bt_reg(btcoexist, 3, 0xae) &
- 0xffff);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
- &bt_patch_ver);
- btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
-
- if (coex_sta->num_of_profile > 0) {
- cnt++;
-
- if (cnt >= 3) {
- btcoexist->btc_get_bt_afh_map_from_bt(
- btcoexist, 0, &coex_sta->bt_afh_map[0]);
- cnt = 0;
- }
- }
- }
-
- if (psd_scan->ant_det_try_count == 0) {
- seq_printf(
- m, "\r\n %-35s = %d/ %d/ %s / %d",
- "Ant PG Num/ Mech/ Pos/ RFE", board_info->pg_ant_num,
- board_info->btdm_ant_num,
- (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT ?
- "Main" :
- "Aux"),
- rfe_type->rfe_module_type);
- } else {
- seq_printf(
- m, "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)",
- "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE",
- board_info->pg_ant_num,
- board_info->btdm_ant_num_by_ant_det,
- (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT ?
- "Main" :
- "Aux"),
- rfe_type->rfe_module_type, psd_scan->ant_det_try_count,
- psd_scan->ant_det_fail_count, psd_scan->ant_det_result);
-
- if (board_info->btdm_ant_det_finish) {
- if (psd_scan->ant_det_result != 12)
- seq_printf(m, "\r\n %-35s = %s",
- "Ant Det PSD Value",
- psd_scan->ant_det_peak_val);
- else
- seq_printf(m, "\r\n %-35s = %d",
- "Ant Det PSD Value",
- psd_scan->ant_det_psd_scan_peak_val /
- 100);
- }
- }
-
- bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
-
- bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
-
- seq_printf(
- m, "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
- "CoexVer WL/ BT_Desired/ BT_Report",
- glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant,
- glcoex_ver_btdesired_8822b_1ant, bt_coex_ver,
- (bt_coex_ver == 0xff ?
- "Unknown" :
- (coex_sta->bt_disabled ? "BT-disable" :
- (bt_coex_ver >= glcoex_ver_btdesired_8822b_1ant ?
- "Match" :
- "Mis-Match"))));
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", "W_FW/ B_FW/ Phy/ Kt",
- fw_ver, bt_patch_ver, phyver, coex_sta->cut_version + 65);
-
- seq_printf(m, "\r\n %-35s = %02x %02x %02x ", "AFH Map to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
-
- /* wifi status */
- seq_printf(m, "\r\n %-35s", "============[Wifi Status]============");
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS, m);
-
- seq_printf(m, "\r\n %-35s", "============[BT Status]============");
-
- pop_report_in_10s++;
- seq_printf(
- m, "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt/ popCnt]",
- ((coex_sta->bt_disabled) ?
- ("disabled") :
- ((coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") :
- ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ?
- "non-connected idle" :
- ((coex_dm->bt_status ==
- BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE) ?
- "connected-idle" :
- "busy")))),
- coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
- coex_sta->pop_event_cnt);
-
- if (pop_report_in_10s >= 5) {
- coex_sta->pop_event_cnt = 0;
- pop_report_in_10s = 0;
- }
-
- if (coex_sta->num_of_profile != 0)
- seq_printf(
- m, "\r\n %-35s = %s%s%s%s%s", "Profiles",
- ((bt_link_info->a2dp_exist) ?
- ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," :
- "A2DP,") :
- ""),
- ((bt_link_info->sco_exist) ? "HFP," : ""),
- ((bt_link_info->hid_exist) ?
- ((coex_sta->hid_busy_num >= 2) ?
- "HID(4/18)," :
- "HID(2/18),") :
- ""),
- ((bt_link_info->pan_exist) ? "PAN," : ""),
- ((coex_sta->voice_over_HOGP) ? "Voice" : ""));
- else
- seq_printf(m, "\r\n %-35s = None", "Profiles");
-
- if (bt_link_info->a2dp_exist) {
- seq_printf(m, "\r\n %-35s = %s/ %d/ %s",
- "A2DP Rate/Bitpool/Auto_Slot",
- ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
- coex_sta->a2dp_bit_pool,
- ((coex_sta->is_autoslot) ? "On" : "Off"));
- }
-
- if (bt_link_info->hid_exist) {
- seq_printf(m, "\r\n %-35s = %d/ %d", "HID PairNum/Forbid_Slot",
- coex_sta->hid_pair_cnt, coex_sta->forbidden_slot);
- }
-
- seq_printf(m, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
- "Role/RoleSwCnt/IgnWlact/Feature",
- ((bt_link_info->slave_role) ? "Slave" : "Master"),
- coex_sta->cnt_role_switch,
- ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
- coex_sta->bt_coex_supported_feature);
-
- if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) {
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "BLEScan Type/TV/Init/Ble",
- coex_sta->bt_ble_scan_type,
- (coex_sta->bt_ble_scan_type & 0x1 ?
- coex_sta->bt_ble_scan_para[0] :
- 0x0),
- (coex_sta->bt_ble_scan_type & 0x2 ?
- coex_sta->bt_ble_scan_para[1] :
- 0x0),
- (coex_sta->bt_ble_scan_type & 0x4 ?
- coex_sta->bt_ble_scan_para[2] :
- 0x0));
- }
-
- seq_printf(m, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
- "ReInit/ReLink/IgnWlact/Page/NameReq", coex_sta->cnt_reinit,
- coex_sta->cnt_setup_link, coex_sta->cnt_ign_wlan_act,
- coex_sta->cnt_page, coex_sta->cnt_remote_name_req);
-
- halbtc8822b1ant_read_score_board(btcoexist, &u16tmp[0]);
-
- if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
- (coex_sta->bt_reg_vendor_ac == 0xffff))
- seq_printf(m, "\r\n %-35s = x/ x/ %04x",
- "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]);
- else
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ %04x",
- "0xae[4]/0xac[1:0]/Scoreboard",
- (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
- coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
-
- if (coex_sta->num_of_profile > 0) {
- seq_printf(
- m,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
- "AFH MAP", coex_sta->bt_afh_map[0],
- coex_sta->bt_afh_map[1], coex_sta->bt_afh_map[2],
- coex_sta->bt_afh_map[3], coex_sta->bt_afh_map[4],
- coex_sta->bt_afh_map[5], coex_sta->bt_afh_map[6],
- coex_sta->bt_afh_map[7], coex_sta->bt_afh_map[8],
- coex_sta->bt_afh_map[9]);
- }
-
- for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- seq_printf(
- m,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8822b_1ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- }
- }
-
- if (btcoexist->manual_control)
- seq_printf(
- m, "\r\n %-35s",
- "============[mechanisms] (before Manual)============");
- else
- seq_printf(m, "\r\n %-35s",
- "============[Mechanisms]============");
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- seq_printf(m, "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)",
- "TDMA", coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"));
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- seq_printf(m, "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
- "Table/0x6c0/0x6c4/0x6c8", coex_sta->coex_table_type,
- u32tmp[0], u32tmp[1], u32tmp[2]);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x", "0x778/0x6cc", u8tmp[0],
- u32tmp[0]);
-
- seq_printf(m, "\r\n %-35s = %s/ %s/ %s/ %d",
- "AntDiv/BtCtrlLPS/LPRA/PsFail",
- ((board_info->ant_div_cfg) ? "On" : "Off"),
- ((coex_sta->force_lps_ctrl) ? "On" : "Off"),
- ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"),
- coex_sta->cnt_set_ps_state_fail);
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false;
-
- if (lte_coex_on) {
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa0);
- u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa4);
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x",
- "LTE Coex Table W_L/B_L", u32tmp[0] & 0xffff,
- u32tmp[1] & 0xffff);
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa8);
- u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xac);
- u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb0);
- u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb4);
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "LTE Break Table W_L/B_L/L_W/L_B",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
- u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
- }
-
- /* Hw setting */
- seq_printf(m, "\r\n %-35s", "============[Hw setting]============");
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- seq_printf(m, "\r\n %-35s = %s/ %s", "LTE Coex/Path Owner",
- ((lte_coex_on) ? "On" : "Off"),
- ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
-
- if (lte_coex_on) {
- seq_printf(m, "\r\n %-35s = %d/ %d/ %d/ %d",
- "LTE 3Wire/OPMode/UART/UARTMode",
- (int)((u32tmp[0] & BIT(6)) >> 6),
- (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
- (int)((u32tmp[0] & BIT(3)) >> 3),
- (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
-
- seq_printf(m, "\r\n %-35s = %d/ %d", "LTE_Busy/UART_Busy",
- (int)((u32tmp[1] & BIT(1)) >> 1),
- (int)(u32tmp[1] & BIT(0)));
- }
- seq_printf(m, "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d",
- "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
- ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
- ((u32tmp[0] & BIT(8)) ? "SW" : "HW"),
- ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
- ((u32tmp[0] & BIT(10)) ? "SW" : "HW"),
- ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
- coex_sta->gnt_error_cnt);
-
- seq_printf(m, "\r\n %-35s = %d/ %d", "GNT_WL/GNT_BT",
- (int)((u32tmp[1] & BIT(2)) >> 2),
- (int)((u32tmp[1] & BIT(3)) >> 3));
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba);
-
- seq_printf(m, "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s",
- "0xcb0/0xcb4/0xcb8[23:16]", u32tmp[0], u32tmp[1], u8tmp[0],
- ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)"));
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "4c[24:23]/64[0]/4c6[4]/40[5]",
- (int)((u32tmp[0] & (BIT(24) | BIT(23))) >> 23),
- u8tmp[2] & 0x1, (int)((u8tmp[0] & BIT(4)) >> 4),
- (int)((u8tmp[1] & BIT(5)) >> 5));
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
- u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50);
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x",
- "0x550/0x522/4-RxAGC/0xc50", u32tmp[0], u8tmp[0],
- (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]);
-
- fa_ofdm = btcoexist->btc_phydm_query_phy_counter(btcoexist,
- "PHYDM_INFO_FA_OFDM");
- fa_cck = btcoexist->btc_phydm_query_phy_counter(btcoexist,
- "PHYDM_INFO_FA_CCK");
- cca_ofdm = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CCA_OFDM");
- cca_cck = btcoexist->btc_phydm_query_phy_counter(btcoexist,
- "PHYDM_INFO_CCA_CCK");
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", cca_cck, fa_cck, cca_ofdm,
- fa_ofdm);
-
- seq_printf(m, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_OK CCK/11g/11n/11ac",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
-
- seq_printf(m, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_Err CCK/11g/11n/11ac",
- coex_sta->crc_err_cck, coex_sta->crc_err_11g,
- coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
-
- seq_printf(m, "\r\n %-35s = %s/ %s/ %s/ %d",
- "WlHiPri/ Locking/ Locked/ Noisy",
- (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
- (coex_sta->cck_lock ? "Yes" : "No"),
- (coex_sta->cck_ever_lock ? "Yes" : "No"),
- coex_sta->wl_noisy_level);
-
- seq_printf(m, "\r\n %-35s = %d/ %d", "0x770(Hi-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
-
- seq_printf(m, "\r\n %-35s = %d/ %d %s", "0x774(Lo-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx,
- (bt_link_info->slave_role ?
- "(Slave!!)" :
- (coex_sta->is_tdma_btautoslot_hang ?
- "(auto-slot hang!!)" :
- "")));
-
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS, m);
-}
-
-void ex_btc8822b1ant_ips_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (type == BTC_IPS_ENTER) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], IPS ENTER notify\n");
- coex_sta->under_ips = true;
-
- /* Write WL "Active" in Score-board for LPS off */
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
-
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ONOFF, false);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLAN_OFF);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if (type == BTC_IPS_LEAVE) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], IPS LEAVE notify\n");
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
-
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ONOFF, true);
-
- /*leave IPS : run ini hw config (exclude wifi only)*/
- halbtc8822b1ant_init_hw_config(btcoexist, false, false);
- /*sw all off*/
- halbtc8822b1ant_init_coex_dm(btcoexist);
- /*leave IPS : Query bt info*/
- halbtc8822b1ant_query_bt_info(btcoexist);
-
- coex_sta->under_ips = false;
- }
-}
-
-void ex_btc8822b1ant_lps_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static bool pre_force_lps_on;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (type == BTC_LPS_ENABLE) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], LPS ENABLE notify\n");
- coex_sta->under_lps = true;
-
- if (coex_sta->force_lps_ctrl) { /* LPS No-32K */
- /* Write WL "Active" in Score-board for PS-TDMA */
- pre_force_lps_on = true;
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE,
- true);
- } else {
- /* LPS-32K, need check if this h2c 0x71 can work??
- * (2015/08/28)
- */
- /* Write WL "Non-Active" in Score-board for Native-PS */
- pre_force_lps_on = false;
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE,
- false);
- }
- } else if (type == BTC_LPS_DISABLE) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], LPS DISABLE notify\n");
- coex_sta->under_lps = false;
-
- /* Write WL "Active" in Score-board for LPS off */
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
-
- if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl))
- halbtc8822b1ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_btc8822b1ant_scan_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_connected = false;
- bool wifi_under_5g = false;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- coex_sta->freeze_coexrun_by_btinfo = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- if (wifi_connected)
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** WL connected before SCAN\n");
- else
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** WL is not connected before SCAN\n");
-
- halbtc8822b1ant_query_bt_info(btcoexist);
-
- /*2.4 g 1*/
- if (type == BTC_SCAN_START) {
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
- &wifi_under_5g);
- /*5 g 1*/
-
- if (wifi_under_5g) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (scan_notify_5g_scan_start) **********\n");
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
- return;
- }
-
- /* 2.4G.2.3*/
- coex_sta->wifi_is_high_pri_task = true;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (scan_notify_2g_scan_start) **********\n");
-
- if (!wifi_connected) { /* non-connected scan */
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** wifi is not connected scan **********\n");
- halbtc8822b1ant_action_wifi_not_connected_scan(
- btcoexist);
- } else { /* wifi is connected */
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** wifi is connected scan **********\n");
- halbtc8822b1ant_action_wifi_connected_scan(btcoexist);
- }
-
- return;
- }
-
- if (type == BTC_SCAN_START_2G) {
- coex_sta->wifi_is_high_pri_task = true;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (scan_notify_2g_sacn_start_for_switch_band_used) **********\n");
-
- if (!wifi_connected) { /* non-connected scan */
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** wifi is not connected **********\n");
-
- halbtc8822b1ant_action_wifi_not_connected_scan(
- btcoexist);
- } else { /* wifi is connected */
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** wifi is connected **********\n");
- halbtc8822b1ant_action_wifi_connected_scan(btcoexist);
- }
- } else {
- coex_sta->wifi_is_high_pri_task = false;
-
- /* 2.4G 5 WL scan finish, then get and update sacn ap numbers */
- /*5 g 4*/
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (scan_finish_notify) **********\n");
-
- if (!wifi_connected) { /* non-connected scan */
- halbtc8822b1ant_action_wifi_not_connected(btcoexist);
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** scan_finish_notify wifi is connected **********\n");
- halbtc8822b1ant_action_wifi_connected(btcoexist);
- }
- }
-}
-
-void ex_btc8822b1ant_scan_notify_without_bt(struct btc_coexist *btcoexist,
- u8 type)
-{
- bool wifi_under_5g = false;
-
- if (type == BTC_SCAN_START) {
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
- &wifi_under_5g);
-
- if (wifi_under_5g) {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
- 0x3, 1);
- return;
- }
-
- /* under 2.4G */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2);
- return;
- }
- if (type == BTC_SCAN_START_2G)
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2);
-}
-
-void ex_btc8822b1ant_switchband_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (switchband_notify) **********\n");
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- coex_sta->switch_band_notify_to = type;
- /*2.4g 4.*/ /*5 g 2*/
- if (type == BTC_SWITCH_TO_5G) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_5G) **********\n");
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
- return;
- } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G (no for scan)) **********\n");
-
- halbtc8822b1ant_run_coexist_mechanism(btcoexist);
- /*5 g 3*/
-
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G) **********\n");
-
- ex_btc8822b1ant_scan_notify(btcoexist, BTC_SCAN_START_2G);
- }
- coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
-}
-
-void ex_btc8822b1ant_switchband_notify_without_bt(struct btc_coexist *btcoexist,
- u8 type)
-{
- bool wifi_under_5g = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if (type == BTC_SWITCH_TO_5G) {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1);
- return;
- } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
- if (wifi_under_5g)
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
- 0x3, 1);
-
- else
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
- 0x3, 2);
- } else {
- ex_btc8822b1ant_scan_notify_without_bt(btcoexist,
- BTC_SCAN_START_2G);
- }
-}
-
-void ex_btc8822b1ant_connect_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_connected = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (connect notify) **********\n");
-
- halbtc8822b1ant_post_state_to_bt(btcoexist,
- BT_8822B_1ANT_SCOREBOARD_SCAN, true);
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if ((type == BTC_ASSOCIATE_5G_START) ||
- (type == BTC_ASSOCIATE_5G_FINISH)) {
- if (type == BTC_ASSOCIATE_5G_START) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (5G associate start notify) **********\n");
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
-
- } else if (type == BTC_ASSOCIATE_5G_FINISH) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (5G associate finish notify) **********\n");
- }
-
- return;
- }
-
- if (type == BTC_ASSOCIATE_START) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], 2G CONNECT START notify\n");
-
- coex_sta->wifi_is_high_pri_task = true;
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- coex_dm->arp_cnt = 0;
-
- halbtc8822b1ant_action_wifi_not_connected_asso_auth(btcoexist);
-
- coex_sta->freeze_coexrun_by_btinfo = true;
-
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], 2G CONNECT Finish notify\n");
- coex_sta->wifi_is_high_pri_task = false;
- coex_sta->freeze_coexrun_by_btinfo = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- if (!wifi_connected) /* non-connected scan */
- halbtc8822b1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8822b1ant_action_wifi_connected(btcoexist);
- }
-}
-
-void ex_btc8822b1ant_media_status_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_under_b_mode = false;
- bool wifi_under_5g = false;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if (type == BTC_MEDIA_CONNECT) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], 2g media connect notify");
-
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
-
- if (wifi_under_5g) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], 5g media notify\n");
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
- return;
- }
- /* Force antenna setup for no scan result issue */
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- /* Set CCK Tx/Rx high Pri except 11b mode */
- if (wifi_under_b_mode) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (media status notify under b mode) **********\n");
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x00); /* CCK Rx */
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** (media status notify not under b mode) **********\n");
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x10); /* CCK Rx */
- }
-
- coex_dm->backup_arfr_cnt1 =
- btcoexist->btc_read_4byte(btcoexist, 0x430);
- coex_dm->backup_arfr_cnt2 =
- btcoexist->btc_read_4byte(btcoexist, 0x434);
- coex_dm->backup_retry_limit =
- btcoexist->btc_read_2byte(btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time =
- btcoexist->btc_read_1byte(btcoexist, 0x456);
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], 2g media disconnect notify\n");
- coex_dm->arp_cnt = 0;
-
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
-
- coex_sta->cck_ever_lock = false;
- }
-
- halbtc8822b1ant_update_wifi_ch_info(btcoexist, type);
-}
-
-void ex_btc8822b1ant_specific_packet_notify(struct btc_coexist *btcoexist,
- u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool under_4way = false, wifi_under_5g = false;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], 5g special packet notify\n");
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (under_4way) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], specific Packet ---- under_4way!!\n");
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- } else if (type == BTC_PACKET_ARP) {
- coex_dm->arp_cnt++;
-
- if (coex_sta->wifi_is_high_pri_task) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], specific Packet ARP notify -cnt = %d\n",
- coex_dm->arp_cnt);
- }
-
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
- type);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- }
-
- if (coex_sta->wifi_is_high_pri_task)
- halbtc8822b1ant_action_wifi_connected_specific_packet(
- btcoexist);
-}
-
-void ex_btc8822b1ant_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
- u8 length)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 i, rsp_source = 0;
- bool wifi_connected = false;
- bool wifi_scan = false, wifi_link = false, wifi_roam = false,
- wifi_busy = false;
- static bool is_scoreboard_scan;
-
- if (psd_scan->is_ant_det_running) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], bt_info_notify return for AntDet is running\n");
- return;
- }
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8822B_1ANT_MAX)
- rsp_source = BT_INFO_SRC_8822B_1ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, length);
-
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
-
- if (i == length - 1) {
- /* last one */
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "0x%02x]\n", tmp_buf[i]);
- } else {
- /* normal */
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "0x%02x, ",
- tmp_buf[i]);
- }
- }
-
- coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
- coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
- coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
-
- if (rsp_source != BT_INFO_SRC_8822B_1ANT_WIFI_FW) {
- /* if 0xff, it means BT is under WHCK test */
- coex_sta->bt_whck_test =
- ((coex_sta->bt_info == 0xff) ? true : false);
-
- coex_sta->bt_create_connection =
- ((coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true :
- false);
-
- /* unit: %, value-100 to translate to unit: dBm */
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- coex_sta->c2h_bt_remote_name_req =
- ((coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true :
- false);
-
- coex_sta->is_A2DP_3M =
- ((coex_sta->bt_info_c2h[rsp_source][2] & 0x10) ? true :
- false);
-
- coex_sta->acl_busy =
- ((coex_sta->bt_info_c2h[rsp_source][1] & 0x9) ? true :
- false);
-
- coex_sta->voice_over_HOGP =
- ((coex_sta->bt_info_ext & 0x10) ? true : false);
-
- coex_sta->c2h_bt_inquiry_page =
- ((coex_sta->bt_info & BT_INFO_8822B_1ANT_B_INQ_PAGE) ?
- true :
- false);
-
- coex_sta->a2dp_bit_pool =
- (((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) ==
- 0x49) ?
- (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) :
- 0);
-
- coex_sta->is_bt_a2dp_sink =
- (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? true :
- false;
-
- coex_sta->bt_retry_cnt =
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
-
- coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
-
- coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
-
- coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- if (coex_sta->c2h_bt_remote_name_req)
- coex_sta->cnt_remote_name_req++;
-
- if (coex_sta->bt_info_ext & BIT(1))
- coex_sta->cnt_reinit++;
-
- if (coex_sta->bt_info_ext & BIT(2)) {
- coex_sta->cnt_setup_link++;
- coex_sta->is_setup_link = true;
- coex_sta->bt_relink_downcount = 2;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Re-Link start in BT info!!\n");
- } else {
- coex_sta->is_setup_link = false;
- coex_sta->bt_relink_downcount = 0;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Re-Link stop in BT info!!\n");
- }
-
- if (coex_sta->bt_info_ext & BIT(3))
- coex_sta->cnt_ign_wlan_act++;
-
- if (coex_sta->bt_info_ext & BIT(6))
- coex_sta->cnt_role_switch++;
-
- if (coex_sta->bt_info_ext & BIT(7))
- coex_sta->is_bt_multi_link = true;
- else
- coex_sta->is_bt_multi_link = false;
-
- if (coex_sta->bt_create_connection) {
- coex_sta->cnt_page++;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY,
- &wifi_busy);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN,
- &wifi_scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK,
- &wifi_link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM,
- &wifi_roam);
-
- if ((wifi_link) || (wifi_roam) || (wifi_scan) ||
- (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) {
- is_scoreboard_scan = true;
- halbtc8822b1ant_post_state_to_bt(
- btcoexist,
- BT_8822B_1ANT_SCOREBOARD_SCAN, true);
-
- } else {
- halbtc8822b1ant_post_state_to_bt(
- btcoexist,
- BT_8822B_1ANT_SCOREBOARD_SCAN, false);
- }
- } else {
- if (is_scoreboard_scan) {
- halbtc8822b1ant_post_state_to_bt(
- btcoexist,
- BT_8822B_1ANT_SCOREBOARD_SCAN, false);
- is_scoreboard_scan = false;
- }
- }
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
-
- if ((!btcoexist->manual_control) &&
- (!btcoexist->stop_coex_dm)) {
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- /* Re-Init */
- if ((coex_sta->bt_info_ext & BIT(1))) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- if (wifi_connected)
- halbtc8822b1ant_update_wifi_ch_info(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- halbtc8822b1ant_update_wifi_ch_info(
- btcoexist,
- BTC_MEDIA_DISCONNECT);
- }
-
- /* If Ignore_WLanAct && not SetUp_Link */
- if ((coex_sta->bt_info_ext & BIT(3)) &&
- (!(coex_sta->bt_info_ext & BIT(2)))) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- halbtc8822b1ant_ignore_wlan_act(
- btcoexist, FORCE_EXEC, false);
- }
- }
- }
-
- if ((coex_sta->bt_info_ext & BIT(5))) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
- coex_sta->bt_ble_scan_type =
- btcoexist->btc_get_ble_scan_type_from_bt(btcoexist);
-
- if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
- coex_sta->bt_ble_scan_para[0] =
- btcoexist->btc_get_ble_scan_para_from_bt(
- btcoexist, 0x1);
- if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
- coex_sta->bt_ble_scan_para[1] =
- btcoexist->btc_get_ble_scan_para_from_bt(
- btcoexist, 0x2);
- if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
- coex_sta->bt_ble_scan_para[2] =
- btcoexist->btc_get_ble_scan_para_from_bt(
- btcoexist, 0x4);
- }
-
- halbtc8822b1ant_update_bt_link_info(btcoexist);
-
- halbtc8822b1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_btc8822b1ant_rf_status_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RF Status notify\n");
-
- if (type == BTC_RF_ON) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RF is turned ON!!\n");
- btcoexist->stop_coex_dm = false;
-
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, true);
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ONOFF, true);
-
- } else if (type == BTC_RF_OFF) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RF is turned OFF!!\n");
-
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ONOFF, false);
- halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLAN_OFF);
- /* for test : s3 bt disppear , fail rate 1/600*/
-
- halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- btcoexist->stop_coex_dm = true;
- }
-}
-
-void ex_btc8822b1ant_halt_notify(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "[BTCoex], Halt notify\n");
-
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE, false);
- halbtc8822b1ant_post_state_to_bt(btcoexist,
- BT_8822B_1ANT_SCOREBOARD_ONOFF, false);
-
- halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLAN_OFF);
- /* for test : s3 bt disppear , fail rate 1/600*/
-
- halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- ex_btc8822b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
- btcoexist->stop_coex_dm = true;
-}
-
-void ex_btc8822b1ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_under_5g = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "[BTCoex], Pnp notify\n");
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if ((pnp_state == BTC_WIFI_PNP_SLEEP) ||
- (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT)) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Pnp notify to SLEEP\n");
-
- halbtc8822b1ant_post_state_to_bt(
- btcoexist, BT_8822B_1ANT_SCOREBOARD_ACTIVE |
- BT_8822B_1ANT_SCOREBOARD_ONOFF |
- BT_8822B_1ANT_SCOREBOARD_SCAN |
- BT_8822B_1ANT_SCOREBOARD_UNDERTEST,
- false);
-
- if (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) {
- if (wifi_under_5g)
- halbtc8822b1ant_set_ant_path(
- btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_5G_RUNTIME);
- else
- halbtc8822b1ant_set_ant_path(
- btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
- } else {
- halbtc8822b1ant_set_ant_path(
- btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLAN_OFF);
- }
-
- btcoexist->stop_coex_dm = true;
- } else if (pnp_state == BTC_WIFI_PNP_WAKE_UP) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Pnp notify to WAKE UP\n");
- btcoexist->stop_coex_dm = false;
- }
-}
-
-void ex_btc8822b1ant_coex_dm_reset(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], *****************Coex DM Reset*****************\n");
-
- halbtc8822b1ant_init_hw_config(btcoexist, false, false);
- halbtc8822b1ant_init_coex_dm(btcoexist);
-}
-
-void ex_btc8822b1ant_periodical(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool bt_relink_finish = false;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ==========================Periodical===========================\n");
-
- if (!btcoexist->auto_report_1ant)
- halbtc8822b1ant_query_bt_info(btcoexist);
-
- halbtc8822b1ant_monitor_bt_ctr(btcoexist);
- halbtc8822b1ant_monitor_wifi_ctr(btcoexist);
-
- halbtc8822b1ant_monitor_bt_enable_disable(btcoexist);
-
- if (coex_sta->bt_relink_downcount != 0) {
- coex_sta->bt_relink_downcount--;
-
- if (coex_sta->bt_relink_downcount == 0) {
- coex_sta->is_setup_link = false;
- bt_relink_finish = true;
- }
- }
-
- /* for 4-way, DHCP, EAPOL packet */
- if (coex_sta->specific_pkt_period_cnt > 0) {
- coex_sta->specific_pkt_period_cnt--;
-
- if ((coex_sta->specific_pkt_period_cnt == 0) &&
- (coex_sta->wifi_is_high_pri_task))
- coex_sta->wifi_is_high_pri_task = false;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
- (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"));
- }
-
- if (halbtc8822b1ant_is_wifi_status_changed(btcoexist) ||
- (bt_relink_finish) || (coex_sta->is_set_ps_state_fail))
- halbtc8822b1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_btc8822b1ant_antenna_detection(struct btc_coexist *btcoexist,
- u32 cent_freq, u32 offset, u32 span,
- u32 seconds)
-{
-}
-
-void ex_btc8822b1ant_antenna_isolation(struct btc_coexist *btcoexist,
- u32 cent_freq, u32 offset, u32 span,
- u32 seconds)
-{
-}
-
-void ex_btc8822b1ant_psd_scan(struct btc_coexist *btcoexist, u32 cent_freq,
- u32 offset, u32 span, u32 seconds)
-{
-}
-
-void ex_btc8822b1ant_display_ant_detection(struct btc_coexist *btcoexist) {}
-
-void ex_btc8822b1ant_dbg_control(struct btc_coexist *btcoexist, u8 op_code,
- u8 op_len, u8 *pdata)
-{
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* *******************************************
- * The following is for 8822B 1ANT BT Co-exist definition
- * ********************************************/
-#define BT_INFO_8822B_1ANT_B_FTP BIT(7)
-#define BT_INFO_8822B_1ANT_B_A2DP BIT(6)
-#define BT_INFO_8822B_1ANT_B_HID BIT(5)
-#define BT_INFO_8822B_1ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8822B_1ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8822B_1ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8822B_1ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8822B_1ANT_B_CONNECTION BIT(0)
-
-#define BT_INFO_8822B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
- (((_BT_INFO_EXT_ & BIT(0))) ? true : false)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT 2
-
-#define BT_8822B_1ANT_WIFI_NOISY_THRESH 150 /* max: 255 */
-#define BT_8822B_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */
-
-/* for Antenna detection */
-#define BT_8822B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50
-#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
-#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55
-#define BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT 35
-#define BT_8822B_1ANT_ANTDET_RETRY_INTERVAL \
- 10 /* retry timer if ant det is fail, unit: second */
-#define BT_8822B_1ANT_ANTDET_ENABLE 0
-#define BT_8822B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0
-
-#define BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
-
-enum bt_8822b_1ant_signal_state {
- BT_8822B_1ANT_SIG_STA_SET_TO_LOW = 0x0,
- BT_8822B_1ANT_SIG_STA_SET_BY_HW = 0x0,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH = 0x1,
- BT_8822B_1ANT_SIG_STA_MAX
-};
-
-enum bt_8822b_1ant_path_ctrl_owner {
- BT_8822B_1ANT_PCO_BTSIDE = 0x0,
- BT_8822B_1ANT_PCO_WLSIDE = 0x1,
- BT_8822B_1ANT_PCO_MAX
-};
-
-enum bt_8822b_1ant_gnt_ctrl_type {
- BT_8822B_1ANT_GNT_CTRL_BY_PTA = 0x0,
- BT_8822B_1ANT_GNT_CTRL_BY_SW = 0x1,
- BT_8822B_1ANT_GNT_CTRL_MAX
-};
-
-enum bt_8822b_1ant_gnt_ctrl_block {
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB = 0x0,
- BT_8822B_1ANT_GNT_BLOCK_RFC = 0x1,
- BT_8822B_1ANT_GNT_BLOCK_BB = 0x2,
- BT_8822B_1ANT_GNT_BLOCK_MAX
-};
-
-enum bt_8822b_1ant_lte_coex_table_type {
- BT_8822B_1ANT_CTT_WL_VS_LTE = 0x0,
- BT_8822B_1ANT_CTT_BT_VS_LTE = 0x1,
- BT_8822B_1ANT_CTT_MAX
-};
-
-enum bt_8822b_1ant_lte_break_table_type {
- BT_8822B_1ANT_LBTT_WL_BREAK_LTE = 0x0,
- BT_8822B_1ANT_LBTT_BT_BREAK_LTE = 0x1,
- BT_8822B_1ANT_LBTT_LTE_BREAK_WL = 0x2,
- BT_8822B_1ANT_LBTT_LTE_BREAK_BT = 0x3,
- BT_8822B_1ANT_LBTT_MAX
-};
-
-enum bt_info_src_8822b_1ant {
- BT_INFO_SRC_8822B_1ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8822B_1ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8822B_1ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8822B_1ANT_MAX
-};
-
-enum bt_8822b_1ant_bt_status {
- BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8822B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8822B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8822B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8822B_1ANT_BT_STATUS_MAX
-};
-
-enum bt_8822b_1ant_wifi_status {
- BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
- BT_8822B_1ANT_WIFI_STATUS_MAX
-};
-
-enum bt_8822b_1ant_coex_algo {
- BT_8822B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8822B_1ANT_COEX_ALGO_SCO = 0x1,
- BT_8822B_1ANT_COEX_ALGO_HID = 0x2,
- BT_8822B_1ANT_COEX_ALGO_A2DP = 0x3,
- BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8822B_1ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8822B_1ANT_COEX_ALGO_PANHS = 0x6,
- BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8822B_1ANT_COEX_ALGO_MAX = 0xb,
-};
-
-enum bt_8822b_1ant_ext_ant_switch_type {
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT = 0x0,
- BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SP3T = 0x1,
- BT_8822B_1ANT_EXT_ANT_SWITCH_MAX
-};
-
-enum bt_8822b_1ant_ext_ant_switch_ctrl_type {
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_MAX
-};
-
-enum bt_8822b_1ant_ext_ant_switch_pos_type {
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT = 0x0,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_MAX
-};
-
-enum bt_8822b_1ant_phase {
- BT_8822B_1ANT_PHASE_COEX_INIT = 0x0,
- BT_8822B_1ANT_PHASE_WLANONLY_INIT = 0x1,
- BT_8822B_1ANT_PHASE_WLAN_OFF = 0x2,
- BT_8822B_1ANT_PHASE_2G_RUNTIME = 0x3,
- BT_8822B_1ANT_PHASE_5G_RUNTIME = 0x4,
- BT_8822B_1ANT_PHASE_BTMPMODE = 0x5,
- BT_8822B_1ANT_PHASE_MAX
-};
-
-/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
-enum bt_8822b_1ant_scoreboard {
- BT_8822B_1ANT_SCOREBOARD_ACTIVE = BIT(0),
- BT_8822B_1ANT_SCOREBOARD_ONOFF = BIT(1),
- BT_8822B_1ANT_SCOREBOARD_SCAN = BIT(2),
- BT_8822B_1ANT_SCOREBOARD_UNDERTEST = BIT(3),
- BT_8822B_1ANT_SCOREBOARD_WLBUSY = BIT(6)
-};
-
-struct coex_dm_8822b_1ant {
- /* hw setting */
- u32 pre_ant_pos_type;
- u32 cur_ant_pos_type;
- /* fw mechanism */
- bool cur_ignore_wlan_act;
- bool pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- bool auto_tdma_adjust;
- bool pre_ps_tdma_on;
- bool cur_ps_tdma_on;
- bool pre_bt_auto_report;
- bool cur_bt_auto_report;
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- /* sw mechanism */
- bool pre_low_penalty_ra;
- bool cur_low_penalty_ra;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- bool limited_dig;
-
- u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
- u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
- u16 backup_retry_limit;
- u8 backup_ampdu_max_time;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
- u8 pre_arfr_type;
- u8 cur_arfr_type;
- u8 pre_retry_limit_type;
- u8 cur_retry_limit_type;
- u8 pre_ampdu_time_type;
- u8 cur_ampdu_time_type;
- u32 arp_cnt;
-
- u32 pre_ext_ant_switch_status;
- u32 cur_ext_ant_switch_status;
-
- u8 error_condition;
-};
-
-struct coex_sta_8822b_1ant {
- bool bt_disabled;
- bool bt_link_exist;
- bool sco_exist;
- bool a2dp_exist;
- bool hid_exist;
- bool pan_exist;
- u8 num_of_profile;
-
- bool under_lps;
- bool under_ips;
- u32 specific_pkt_period_cnt;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- bool is_hi_pri_rx_overhead;
- s8 bt_rssi;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- u8 bt_info_c2h[BT_INFO_SRC_8822B_1ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_1ANT_MAX];
- bool bt_whck_test;
- bool c2h_bt_inquiry_page;
- bool c2h_bt_remote_name_req;
- bool c2h_bt_page; /* Add for win8.1 page out issue */
- bool wifi_is_high_pri_task; /* Add for win8.1 page out issue */
-
- u8 bt_info_ext;
- u8 bt_info_ext2;
- u32 pop_event_cnt;
- u8 scan_ap_num;
- u8 bt_retry_cnt;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_vht;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_vht;
-
- bool cck_lock;
- bool pre_ccklock;
- bool cck_ever_lock;
- u8 coex_table_type;
-
- bool force_lps_ctrl;
-
- bool concurrent_rx_mode_on;
-
- u16 score_board;
- u8 isolation_btween_wb; /* 0~ 50 */
-
- u8 a2dp_bit_pool;
- u8 cut_version;
- bool acl_busy;
- bool bt_create_connection;
-
- u32 bt_coex_supported_feature;
- u32 bt_coex_supported_version;
-
- u8 bt_ble_scan_type;
- u32 bt_ble_scan_para[3];
-
- bool run_time_state;
- bool freeze_coexrun_by_btinfo;
-
- bool is_A2DP_3M;
- bool voice_over_HOGP;
- u8 bt_info;
- bool is_autoslot;
- u8 forbidden_slot;
- u8 hid_busy_num;
- u8 hid_pair_cnt;
-
- u32 cnt_remote_name_req;
- u32 cnt_setup_link;
- u32 cnt_reinit;
- u32 cnt_ign_wlan_act;
- u32 cnt_page;
- u32 cnt_role_switch;
-
- u16 bt_reg_vendor_ac;
- u16 bt_reg_vendor_ae;
-
- bool is_setup_link;
- u8 wl_noisy_level;
- u32 gnt_error_cnt;
- u8 bt_afh_map[10];
- u8 bt_relink_downcount;
- bool is_tdma_btautoslot;
- bool is_tdma_btautoslot_hang;
-
- u8 switch_band_notify_to;
- bool is_rf_state_off;
-
- bool is_hid_low_pri_tx_overhead;
- bool is_bt_multi_link;
- bool is_bt_a2dp_sink;
- bool rf4ce_enabled;
-
- bool is_set_ps_state_fail;
- u8 cnt_set_ps_state_fail;
-};
-
-struct rfe_type_8822b_1ant {
- u8 rfe_module_type;
- bool ext_ant_switch_exist;
- u8 ext_ant_switch_type;
- /* iF 0: ANTSW(rfe_sel9)=0, ANTSWB(rfe_sel8)=1 => Ant to BT/5G */
- u8 ext_ant_switch_ctrl_polarity;
-};
-
-#define BT_8822B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
-#define BT_8822B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
-#define BT_8822B_1ANT_ANTDET_BUF_LEN 16
-
-struct psdscan_sta_8822b_1ant {
- u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
- u32 ant_det_bt_tx_time;
- u32 ant_det_pre_psdscan_peak_val;
- bool ant_det_is_ant_det_available;
- u32 ant_det_psd_scan_peak_val;
- bool ant_det_is_btreply_available;
- u32 ant_det_psd_scan_peak_freq;
-
- u8 ant_det_result;
- u8 ant_det_peak_val[BT_8822B_1ANT_ANTDET_BUF_LEN];
- u8 ant_det_peak_freq[BT_8822B_1ANT_ANTDET_BUF_LEN];
- u32 ant_det_try_count;
- u32 ant_det_fail_count;
- u32 ant_det_inteval_count;
- u32 ant_det_thres_offset;
-
- u32 real_cent_freq;
- s32 real_offset;
- u32 real_span;
-
- u32 psd_band_width; /* unit: Hz */
- u32 psd_point; /* 128/256/512/1024 */
- u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_start_point;
- u32 psd_stop_point;
- u32 psd_max_value_point;
- u32 psd_max_value;
- u32 psd_start_base;
- u32 psd_avg_num; /* 1/8/16/32 */
- u32 psd_gen_count;
- bool is_psd_running;
- bool is_psd_show_max_only;
- bool is_ant_det_running;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ********************************************/
-void ex_btc8822b1ant_power_on_setting(struct btc_coexist *btcoexist);
-void ex_btc8822b1ant_pre_load_firmware(struct btc_coexist *btcoexist);
-void ex_btc8822b1ant_init_hw_config(struct btc_coexist *btcoexist,
- bool wifi_only);
-void ex_btc8822b1ant_init_coex_dm(struct btc_coexist *btcoexist);
-void ex_btc8822b1ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b1ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b1ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b1ant_scan_notify_without_bt(struct btc_coexist *btcoexist,
- u8 type);
-void ex_btc8822b1ant_switchband_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b1ant_switchband_notify_without_bt(struct btc_coexist *btcoexist,
- u8 type);
-void ex_btc8822b1ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b1ant_media_status_notify(struct btc_coexist *btcoexist,
- u8 type);
-void ex_btc8822b1ant_specific_packet_notify(struct btc_coexist *btcoexist,
- u8 type);
-void ex_btc8822b1ant_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
- u8 length);
-void ex_btc8822b1ant_rf_status_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b1ant_halt_notify(struct btc_coexist *btcoexist);
-void ex_btc8822b1ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state);
-void ex_halbtc8822b1ant_score_board_status_notify(struct btc_coexist *btcoexist,
- u8 *tmp_buf, u8 length);
-void ex_btc8822b1ant_coex_dm_reset(struct btc_coexist *btcoexist);
-void ex_btc8822b1ant_periodical(struct btc_coexist *btcoexist);
-void ex_btc8822b1ant_display_coex_info(struct btc_coexist *btcoexist,
- struct seq_file *m);
-void ex_btc8822b1ant_antenna_detection(struct btc_coexist *btcoexist,
- u32 cent_freq, u32 offset, u32 span,
- u32 seconds);
-void ex_btc8822b1ant_antenna_isolation(struct btc_coexist *btcoexist,
- u32 cent_freq, u32 offset, u32 span,
- u32 seconds);
-
-void ex_btc8822b1ant_psd_scan(struct btc_coexist *btcoexist, u32 cent_freq,
- u32 offset, u32 span, u32 seconds);
-void ex_btc8822b1ant_display_ant_detection(struct btc_coexist *btcoexist);
-
-void ex_btc8822b1ant_dbg_control(struct btc_coexist *btcoexist, u8 op_code,
- u8 op_len, u8 *pdata);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8822B Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * *************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-#include "halbt_precomp.h"
-
-/* ************************************************************
- * Global variables, these are static variables
- * *************************************************************/
-static struct coex_dm_8822b_2ant glcoex_dm_8822b_2ant;
-static struct coex_dm_8822b_2ant *coex_dm = &glcoex_dm_8822b_2ant;
-static struct coex_sta_8822b_2ant glcoex_sta_8822b_2ant;
-static struct coex_sta_8822b_2ant *coex_sta = &glcoex_sta_8822b_2ant;
-static struct psdscan_sta_8822b_2ant gl_psd_scan_8822b_2ant;
-static struct psdscan_sta_8822b_2ant *psd_scan = &gl_psd_scan_8822b_2ant;
-static struct rfe_type_8822b_2ant gl_rfe_type_8822b_2ant;
-static struct rfe_type_8822b_2ant *rfe_type = &gl_rfe_type_8822b_2ant;
-
-static const char *const glbt_info_src_8822b_2ant[] = {
- "BT Info[wifi fw]", "BT Info[bt rsp]", "BT Info[bt auto report]",
-};
-
-static u32 glcoex_ver_date_8822b_2ant = 20170327;
-static u32 glcoex_ver_8822b_2ant = 0x44;
-static u32 glcoex_ver_btdesired_8822b_2ant = 0x42;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8822b2ant_
- * *************************************************************/
-static u8 halbtc8822b2ant_bt_rssi_state(struct btc_coexist *btcoexist,
- u8 *ppre_bt_rssi_state, u8 level_num,
- u8 rssi_thresh, u8 rssi_thresh1)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- s32 bt_rssi = 0;
- u8 bt_rssi_state = *ppre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >=
- (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT Rssi thresh error!!\n");
- return *ppre_bt_rssi_state;
- }
-
- if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >=
- (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (*ppre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- *ppre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-static u8 halbtc8822b2ant_wifi_rssi_state(struct btc_coexist *btcoexist,
- u8 *pprewifi_rssi_state, u8 level_num,
- u8 rssi_thresh, u8 rssi_thresh1)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = *pprewifi_rssi_state;
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >=
- (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], wifi RSSI thresh error!!\n");
- return *pprewifi_rssi_state;
- }
-
- if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >=
- (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (*pprewifi_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- *pprewifi_rssi_state = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-static void halbtc8822b2ant_coex_switch_threshold(struct btc_coexist *btcoexist,
- u8 isolation_measuared)
-{
- s8 interference_wl_tx = 0, interference_bt_tx = 0;
-
- interference_wl_tx =
- BT_8822B_2ANT_WIFI_MAX_TX_POWER - isolation_measuared;
- interference_bt_tx =
- BT_8822B_2ANT_BT_MAX_TX_POWER - isolation_measuared;
-
- coex_sta->wifi_coex_thres = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
- coex_sta->wifi_coex_thres2 = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2;
-
- coex_sta->bt_coex_thres = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1;
- coex_sta->bt_coex_thres2 = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2;
-}
-
-static void halbtc8822b2ant_query_bt_info(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 h2c_parameter[1] = {0};
-
- if (coex_sta->bt_disabled) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], No query BT info because BT is disabled!\n");
- return;
- }
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-static void halbtc8822b2ant_monitor_bt_ctr(struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
- static u8 num_of_bt_counter_chk, cnt_slave, cnt_autoslot_hang;
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-
- if ((coex_sta->low_priority_tx > 1050) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- if ((coex_sta->low_priority_rx >= 950) &&
- (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) &&
- (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) &&
- (coex_sta->bt_link_exist)) {
- if (cnt_slave >= 2) {
- bt_link_info->slave_role = true;
- cnt_slave = 2;
- } else {
- cnt_slave++;
- }
- } else {
- if (cnt_slave == 0) {
- bt_link_info->slave_role = false;
- cnt_slave = 0;
- } else {
- cnt_slave--;
- }
- }
-
- if (coex_sta->is_tdma_btautoslot) {
- if ((coex_sta->low_priority_tx >= 1300) &&
- (coex_sta->low_priority_rx <= 150)) {
- if (cnt_autoslot_hang >= 2) {
- coex_sta->is_tdma_btautoslot_hang = true;
- cnt_autoslot_hang = 2;
- } else {
- cnt_autoslot_hang++;
- }
- } else {
- if (cnt_autoslot_hang == 0) {
- coex_sta->is_tdma_btautoslot_hang = false;
- cnt_autoslot_hang = 0;
- } else {
- cnt_autoslot_hang--;
- }
- }
- }
-
- if (coex_sta->sco_exist) {
- if ((coex_sta->high_priority_tx >= 400) &&
- (coex_sta->high_priority_rx >= 400))
- coex_sta->is_esco_mode = false;
- else
- coex_sta->is_esco_mode = true;
- }
-
- if (bt_link_info->hid_only) {
- if (coex_sta->low_priority_rx > 50)
- coex_sta->is_hid_low_pri_tx_overhead = true;
- else
- coex_sta->is_hid_low_pri_tx_overhead = false;
- }
-
- if ((coex_sta->high_priority_tx == 0) &&
- (coex_sta->high_priority_rx == 0) &&
- (coex_sta->low_priority_tx == 0) &&
- (coex_sta->low_priority_rx == 0)) {
- num_of_bt_counter_chk++;
- if (num_of_bt_counter_chk >= 3) {
- halbtc8822b2ant_query_bt_info(btcoexist);
- num_of_bt_counter_chk = 0;
- }
- }
-}
-
-static void halbtc8822b2ant_monitor_wifi_ctr(struct btc_coexist *btcoexist)
-{
- s32 wifi_rssi = 0;
- bool wifi_busy = false, wifi_under_b_mode = false, wifi_scan = false;
- bool bt_idle = false;
- static u8 cck_lock_counter, wl_noisy_count0, wl_noisy_count1 = 3,
- wl_noisy_count2;
- u32 total_cnt, cck_cnt;
- u32 cnt_crcok = 0, cnt_crcerr = 0;
- static u8 cnt;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
-
- coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_OK_CCK");
- coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_OK_LEGACY");
- coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_OK_HT");
- coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_OK_VHT");
-
- coex_sta->crc_err_cck = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_ERROR_CCK");
- coex_sta->crc_err_11g = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_ERROR_LEGACY");
- coex_sta->crc_err_11n = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_ERROR_HT");
- coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CRC32_ERROR_VHT");
-
- cnt_crcok = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
- coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht;
-
- cnt_crcerr = coex_sta->crc_err_cck + coex_sta->crc_err_11g +
- coex_sta->crc_err_11n + coex_sta->crc_err_11n_vht;
-
- if ((wifi_busy) && (cnt_crcerr != 0)) {
- coex_sta->now_crc_ratio = cnt_crcok / cnt_crcerr;
-
- if (cnt == 0)
- coex_sta->acc_crc_ratio = coex_sta->now_crc_ratio;
- else
- coex_sta->acc_crc_ratio =
- (coex_sta->acc_crc_ratio * 7 +
- coex_sta->now_crc_ratio * 3) /
- 10;
-
- if (cnt >= 10)
- cnt = 0;
- else
- cnt++;
- }
-
- cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
-
- if ((coex_dm->bt_status ==
- BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE) ||
- (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE) ||
- (coex_sta->bt_disabled))
- bt_idle = true;
-
- if (cck_cnt > 250) {
- if (wl_noisy_count2 < 3)
- wl_noisy_count2++;
-
- if (wl_noisy_count2 == 3) {
- wl_noisy_count0 = 0;
- wl_noisy_count1 = 0;
- }
-
- } else if (cck_cnt < 50) {
- if (wl_noisy_count0 < 3)
- wl_noisy_count0++;
-
- if (wl_noisy_count0 == 3) {
- wl_noisy_count1 = 0;
- wl_noisy_count2 = 0;
- }
-
- } else {
- if (wl_noisy_count1 < 3)
- wl_noisy_count1++;
-
- if (wl_noisy_count1 == 3) {
- wl_noisy_count0 = 0;
- wl_noisy_count2 = 0;
- }
- }
-
- if (wl_noisy_count2 == 3)
- coex_sta->wl_noisy_level = 2;
- else if (wl_noisy_count1 == 3)
- coex_sta->wl_noisy_level = 1;
- else
- coex_sta->wl_noisy_level = 0;
-
- if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
- total_cnt = cnt_crcok;
-
- if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status ==
- BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
- (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY)) {
- if (coex_sta->crc_ok_cck >
- (total_cnt - coex_sta->crc_ok_cck)) {
- if (cck_lock_counter < 3)
- cck_lock_counter++;
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- if (!coex_sta->pre_ccklock) {
- if (cck_lock_counter >= 3)
- coex_sta->cck_lock = true;
- else
- coex_sta->cck_lock = false;
- } else {
- if (cck_lock_counter == 0)
- coex_sta->cck_lock = false;
- else
- coex_sta->cck_lock = true;
- }
-
- if (coex_sta->cck_lock)
- coex_sta->cck_ever_lock = true;
-
- coex_sta->pre_ccklock = coex_sta->cck_lock;
-}
-
-static bool
-halbtc8822b2ant_is_wifibt_status_changed(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static bool pre_wifi_busy, pre_under_4way, pre_bt_hs_on, pre_bt_off,
- pre_bt_slave, pre_hid_low_pri_tx_overhead, pre_wifi_under_lps,
- pre_bt_setup_link;
- static u8 pre_hid_busy_num, pre_wl_noisy_level;
- bool wifi_busy = false, under_4way = false, bt_hs_on = false;
- bool wifi_connected = false;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (coex_sta->bt_disabled != pre_bt_off) {
- pre_bt_off = coex_sta->bt_disabled;
-
- if (coex_sta->bt_disabled)
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is disabled !!\n");
- else
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is enabled !!\n");
-
- coex_sta->bt_coex_supported_feature = 0;
- coex_sta->bt_coex_supported_version = 0;
- coex_sta->bt_ble_scan_type = 0;
- coex_sta->bt_ble_scan_para[0] = 0;
- coex_sta->bt_ble_scan_para[1] = 0;
- coex_sta->bt_ble_scan_para[2] = 0;
- coex_sta->bt_reg_vendor_ac = 0xffff;
- coex_sta->bt_reg_vendor_ae = 0xffff;
- return true;
- }
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
- pre_wl_noisy_level = coex_sta->wl_noisy_level;
- return true;
- }
- if (coex_sta->under_lps != pre_wifi_under_lps) {
- pre_wifi_under_lps = coex_sta->under_lps;
- if (coex_sta->under_lps)
- return true;
- }
- }
-
- if (!coex_sta->bt_disabled) {
- if (coex_sta->hid_busy_num != pre_hid_busy_num) {
- pre_hid_busy_num = coex_sta->hid_busy_num;
- return true;
- }
-
- if (bt_link_info->slave_role != pre_bt_slave) {
- pre_bt_slave = bt_link_info->slave_role;
- return true;
- }
-
- if (pre_hid_low_pri_tx_overhead !=
- coex_sta->is_hid_low_pri_tx_overhead) {
- pre_hid_low_pri_tx_overhead =
- coex_sta->is_hid_low_pri_tx_overhead;
- return true;
- }
-
- if (pre_bt_setup_link != coex_sta->is_setup_link) {
- pre_bt_setup_link = coex_sta->is_setup_link;
- return true;
- }
- }
-
- return false;
-}
-
-static void halbtc8822b2ant_update_bt_link_info(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool bt_hs_on = false;
- bool bt_busy = false;
-
- coex_sta->num_of_profile = 0;
-
- /* set link exist status */
- if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_FTP) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- } else {
- coex_sta->pan_exist = false;
- }
-
- if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_A2DP) {
- coex_sta->a2dp_exist = true;
- coex_sta->num_of_profile++;
- } else {
- coex_sta->a2dp_exist = false;
- }
-
- if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_HID) {
- coex_sta->hid_exist = true;
- coex_sta->num_of_profile++;
- } else {
- coex_sta->hid_exist = false;
- }
-
- if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) {
- coex_sta->sco_exist = true;
- coex_sta->num_of_profile++;
- } else {
- coex_sta->sco_exist = false;
- }
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
- bt_link_info->acl_busy = coex_sta->acl_busy;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist && !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist && bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist && !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist && !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist && bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-
- if (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_INQ_PAGE) {
- coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_INQ_PAGE;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
- } else if (!(coex_sta->bt_info & BT_INFO_8822B_2ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- } else if (coex_sta->bt_info == BT_INFO_8822B_2ANT_B_CONNECTION) {
- /* connection exists but no busy */
- coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- } else if (((coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_ESCO) ||
- (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_BUSY)) &&
- (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_ACL_BUSY)) {
- coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
- } else if ((coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_ESCO) ||
- (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_SCO_BUSY;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- } else if (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_ACL_BUSY) {
- coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_ACL_BUSY;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- } else {
- coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_MAX;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- }
-
- if ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_SCO_BUSY) ||
- (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY))
- bt_busy = true;
- else
- bt_busy = false;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-}
-
-static void halbtc8822b2ant_update_wifi_ch_info(struct btc_coexist *btcoexist,
- u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
- u32 RTL97F_8822B = 0;
-
- if (RTL97F_8822B)
- return;
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((type == BTC_MEDIA_CONNECT) && (wifi_central_chnl <= 14)) {
- /* enable BT AFH skip WL channel for 8822b
- * because BT Rx LO interference
- */
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (wifi_bw == BTC_WIFI_BW_HT40)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-}
-
-static void
-halbtc8822b2ant_set_fw_dac_swing_level(struct btc_coexist *btcoexist,
- u8 dac_swing_lvl)
-{
- u8 h2c_parameter[1] = {0};
- u32 RTL97F_8822B = 0;
-
- if (RTL97F_8822B)
- return;
-
- /* There are several type of dacswing */
- /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
- h2c_parameter[0] = dac_swing_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
-}
-
-static void halbtc8822b2ant_fw_dac_swing_lvl(struct btc_coexist *btcoexist,
- bool force_exec,
- u8 fw_dac_swing_lvl)
-{
- u32 RTL97F_8822B = 0;
-
- if (RTL97F_8822B)
- return;
-
- coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_fw_dac_swing_lvl ==
- coex_dm->cur_fw_dac_swing_lvl)
- return;
- }
-
- halbtc8822b2ant_set_fw_dac_swing_level(btcoexist,
- coex_dm->cur_fw_dac_swing_lvl);
-
- coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
-}
-
-static void halbtc8822b2ant_set_fw_dec_bt_pwr(struct btc_coexist *btcoexist,
- u8 dec_bt_pwr_lvl)
-{
- u32 RTL97F_8822B = 0;
- u8 h2c_parameter[1] = {0};
-
- if (RTL97F_8822B)
- return;
-
- h2c_parameter[0] = dec_bt_pwr_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
-}
-
-static void halbtc8822b2ant_dec_bt_pwr(struct btc_coexist *btcoexist,
- bool force_exec, u8 dec_bt_pwr_lvl)
-{
- coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
- return;
- }
- halbtc8822b2ant_set_fw_dec_bt_pwr(btcoexist,
- coex_dm->cur_bt_dec_pwr_lvl);
-
- coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
-}
-
-static void halbtc8822b2ant_low_penalty_ra(struct btc_coexist *btcoexist,
- bool force_exec, bool low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
-
- if (low_penalty_ra)
- btcoexist->btc_phydm_modify_ra_pcr_threshold(btcoexist, 0, 50);
- else
- btcoexist->btc_phydm_modify_ra_pcr_threshold(btcoexist, 0, 0);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-static void halbtc8822b2ant_write_score_board(struct btc_coexist *btcoexist,
- u16 bitpos, bool state)
-{
- static u16 originalval = 0x8002;
-
- if (state)
- originalval = originalval | bitpos;
- else
- originalval = originalval & (~bitpos);
-
- btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
-}
-
-static void halbtc8822b2ant_read_score_board(struct btc_coexist *btcoexist,
- u16 *score_board_val)
-{
- *score_board_val =
- (btcoexist->btc_read_2byte(btcoexist, 0xaa)) & 0x7fff;
-}
-
-static void halbtc8822b2ant_post_state_to_bt(struct btc_coexist *btcoexist,
- u16 type, bool state)
-{
- halbtc8822b2ant_write_score_board(btcoexist, (u16)type, state);
-}
-
-static void
-halbtc8822b2ant_monitor_bt_enable_disable(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u32 bt_disable_cnt;
- bool bt_active = true, bt_disabled = false, wifi_under_5g = false;
- u16 u16tmp;
-
- /* This function check if bt is disabled */
-
- /* Read BT on/off status from scoreboard[1],
- * enable this only if BT patch support this feature
- */
- halbtc8822b2ant_read_score_board(btcoexist, &u16tmp);
-
- bt_active = u16tmp & BIT(1);
-
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- } else {
- bt_disable_cnt++;
- if (bt_disable_cnt >= 10) {
- bt_disabled = true;
- bt_disable_cnt = 10;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if ((wifi_under_5g) || (bt_disabled))
- halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
- else
- halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true);
-
- if (coex_sta->bt_disabled != bt_disabled) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- coex_sta->bt_disabled = bt_disabled;
- }
-}
-
-static void halbtc8822b2ant_enable_gnt_to_gpio(struct btc_coexist *btcoexist,
- bool isenable)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u8 bit_val[5] = {0, 0, 0, 0, 0};
-
- if (!btcoexist->dbg_mode_2ant)
- return;
-
- if (isenable) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], enable_gnt_to_gpio!!\n");
-
- /* enable GNT_WL, GNT_BT to GPIO for debug */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
-
- /* store original value */
- bit_val[0] =
- (btcoexist->btc_read_1byte(btcoexist, 0x66) & BIT(4)) >>
- 4; /*0x66[4] */
- bit_val[1] = (btcoexist->btc_read_1byte(btcoexist, 0x67) &
- BIT(0)); /*0x66[8] */
- bit_val[2] =
- (btcoexist->btc_read_1byte(btcoexist, 0x42) & BIT(3)) >>
- 3; /*0x40[19] */
- bit_val[3] =
- (btcoexist->btc_read_1byte(btcoexist, 0x65) & BIT(7)) >>
- 7; /*0x64[15] */
- bit_val[4] =
- (btcoexist->btc_read_1byte(btcoexist, 0x72) & BIT(2)) >>
- 2; /*0x70[18] */
-
- /* switch GPIO Mux */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
- 0x0); /*0x66[4] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
- 0x0); /*0x66[8] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
- 0x0); /*0x40[19] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
- 0x0); /*0x64[15] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
- 0x0); /*0x70[18] = 0 */
-
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], disable_gnt_to_gpio!!\n");
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
-
- /* Restore original value */
- /* switch GPIO Mux */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
- bit_val[0]); /*0x66[4] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
- bit_val[1]); /*0x66[8] = 0 */
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x42, BIT(3), bit_val[2]); /*0x40[19] = 0 */
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x65, BIT(7), bit_val[3]); /*0x64[15] = 0 */
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x72, BIT(2), bit_val[4]); /*0x70[18] = 0 */
- }
-}
-
-static u32
-halbtc8822b2ant_ltecoex_indirect_read_reg(struct btc_coexist *btcoexist,
- u16 reg_addr)
-{
- u32 delay_count = 0;
-
- while (1) {
- if ((btcoexist->btc_read_1byte(btcoexist, 0x1703) & BIT(5)) ==
- 0) {
- mdelay(50);
- delay_count++;
- if (delay_count >= 10) {
- delay_count = 0;
- break;
- }
- } else {
- break;
- }
- }
-
- /* wait for ready bit before access 0x1700 */
- btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr);
-
- return btcoexist->btc_read_4byte(btcoexist, 0x1708); /* get read data */
-}
-
-static void
-halbtc8822b2ant_ltecoex_indirect_write_reg(struct btc_coexist *btcoexist,
- u16 reg_addr, u32 bit_mask,
- u32 reg_value)
-{
- u32 val, i = 0, bitpos = 0, delay_count = 0;
-
- if (bit_mask == 0x0)
- return;
- if (bit_mask == 0xffffffff) {
- /* wait for ready bit before access 0x1700/0x1704 */
- while (1) {
- if ((btcoexist->btc_read_1byte(btcoexist, 0x1703) &
- BIT(5)) == 0) {
- mdelay(50);
- delay_count++;
- if (delay_count >= 10) {
- delay_count = 0;
- break;
- }
- } else {
- break;
- }
- }
-
- btcoexist->btc_write_4byte(btcoexist, 0x1704,
- reg_value); /* put write data */
-
- btcoexist->btc_write_4byte(btcoexist, 0x1700,
- 0xc00F0000 | reg_addr);
- } else {
- for (i = 0; i <= 31; i++) {
- if (((bit_mask >> i) & 0x1) == 0x1) {
- bitpos = i;
- break;
- }
- }
-
- /* read back register value before write */
- val = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- reg_addr);
- val = (val & (~bit_mask)) | (reg_value << bitpos);
-
- /* wait for ready bit before access 0x1700/0x1704 */
- while (1) {
- if ((btcoexist->btc_read_1byte(btcoexist, 0x1703) &
- BIT(5)) == 0) {
- mdelay(50);
- delay_count++;
- if (delay_count >= 10) {
- delay_count = 0;
- break;
- }
- } else {
- break;
- }
- }
-
- btcoexist->btc_write_4byte(btcoexist, 0x1704,
- val); /* put write data */
-
- btcoexist->btc_write_4byte(btcoexist, 0x1700,
- 0xc00F0000 | reg_addr);
- }
-}
-
-static void halbtc8822b2ant_ltecoex_enable(struct btc_coexist *btcoexist,
- bool enable)
-{
- u8 val;
-
- val = (enable) ? 1 : 0;
- halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
- val); /* 0x38[7] */
-}
-
-static void
-halbtc8822b2ant_ltecoex_pathcontrol_owner(struct btc_coexist *btcoexist,
- bool wifi_control)
-{
- u8 val;
-
- val = (wifi_control) ? 1 : 0;
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
- val); /* 0x70[26] */
-}
-
-static void halbtc8822b2ant_ltecoex_set_gnt_bt(struct btc_coexist *btcoexist,
- u8 control_block,
- bool sw_control, u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8822B_2ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0xc000;
- halbtc8822b2ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[15:14] */
- bit_mask = 0x0c00;
- halbtc8822b2ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
- case BT_8822B_2ANT_GNT_BLOCK_RFC:
- bit_mask = 0xc000;
- halbtc8822b2ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[15:14] */
- break;
- case BT_8822B_2ANT_GNT_BLOCK_BB:
- bit_mask = 0x0c00;
- halbtc8822b2ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
- }
-}
-
-static void halbtc8822b2ant_ltecoex_set_gnt_wl(struct btc_coexist *btcoexist,
- u8 control_block,
- bool sw_control, u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8822B_2ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0x3000;
- halbtc8822b2ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[13:12] */
- bit_mask = 0x0300;
- halbtc8822b2ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
- case BT_8822B_2ANT_GNT_BLOCK_RFC:
- bit_mask = 0x3000;
- halbtc8822b2ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[13:12] */
- break;
- case BT_8822B_2ANT_GNT_BLOCK_BB:
- bit_mask = 0x0300;
- halbtc8822b2ant_ltecoex_indirect_write_reg(
- btcoexist, 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
- }
-}
-
-static void
-halbtc8822b2ant_ltecoex_set_coex_table(struct btc_coexist *btcoexist,
- u8 table_type, u16 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8822B_2ANT_CTT_WL_VS_LTE:
- reg_addr = 0xa0;
- break;
- case BT_8822B_2ANT_CTT_BT_VS_LTE:
- reg_addr = 0xa4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8822b2ant_ltecoex_indirect_write_reg(
- btcoexist, reg_addr, 0xffff,
- table_content); /* 0xa0[15:0] or 0xa4[15:0] */
-}
-
-static void halbtc8822b2ant_set_wltoggle_coex_table(
- struct btc_coexist *btcoexist, bool force_exec, u8 interval,
- u8 val0x6c4_b0, u8 val0x6c4_b1, u8 val0x6c4_b2, u8 val0x6c4_b3)
-{
- static u8 pre_h2c_parameter[6] = {0};
- u8 cur_h2c_parameter[6] = {0};
- u8 i, match_cnt = 0;
-
- cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/
-
- cur_h2c_parameter[1] = interval;
- cur_h2c_parameter[2] = val0x6c4_b0;
- cur_h2c_parameter[3] = val0x6c4_b1;
- cur_h2c_parameter[4] = val0x6c4_b2;
- cur_h2c_parameter[5] = val0x6c4_b3;
-
- if (!force_exec) {
- for (i = 1; i <= 5; i++) {
- if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
- break;
-
- match_cnt++;
- }
-
- if (match_cnt == 5)
- return;
- }
-
- for (i = 1; i <= 5; i++)
- pre_h2c_parameter[i] = cur_h2c_parameter[i];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
-}
-
-static void halbtc8822b2ant_set_coex_table(struct btc_coexist *btcoexist,
- u32 val0x6c0, u32 val0x6c4,
- u32 val0x6c8, u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-static void halbtc8822b2ant_coex_table(struct btc_coexist *btcoexist,
- bool force_exec, u32 val0x6c0,
- u32 val0x6c4, u32 val0x6c8, u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8822b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-static void halbtc8822b2ant_coex_table_with_type(struct btc_coexist *btcoexist,
- bool force_exec, u8 type)
-{
- u32 break_table;
- u8 select_table;
-
- coex_sta->coex_table_type = type;
-
- if (coex_sta->concurrent_rx_mode_on) {
- break_table = 0xf0ffffff; /* set WL hi-pri can break BT */
- /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
- select_table = 0xb;
- } else {
- break_table = 0xffffff;
- select_table = 0x3;
- }
-
- switch (type) {
- case 0:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0xffffffff,
- 0xffffffff, break_table,
- select_table);
- break;
- case 1:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0x5a5a5a5a, break_table,
- select_table);
- break;
- case 2:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
- 0x5a5a5a5a, break_table,
- select_table);
- break;
- case 3:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0x5a5a5a5a, break_table,
- select_table);
- break;
- case 4:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0x5a5a5a5a, break_table,
- select_table);
- break;
- case 5:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0x55555555, break_table,
- select_table);
- break;
- case 6:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0xa5555555,
- 0xfafafafa, break_table,
- select_table);
- break;
- case 7:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0xa5555555,
- 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 8:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0xa5555555,
- 0xfafafafa, break_table,
- select_table);
- break;
- case 9:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
- 0xaaaa5aaa, break_table,
- select_table);
- break;
- case 10:
- halbtc8822b2ant_coex_table(btcoexist, force_exec, 0x55555555,
- 0x5a5a555a, break_table,
- select_table);
- break;
- default:
- break;
- }
-}
-
-static void
-halbtc8822b2ant_set_fw_ignore_wlan_act(struct btc_coexist *btcoexist,
- bool enable)
-{
- u8 h2c_parameter[1] = {0};
- u32 RTL97F_8822B = 0;
-
- if (RTL97F_8822B)
- return;
-
- if (enable)
- h2c_parameter[0] |= BIT(0); /* function enable */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-static void halbtc8822b2ant_ignore_wlan_act(struct btc_coexist *btcoexist,
- bool force_exec, bool enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8822b2ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-static void halbtc8822b2ant_set_lps_rpwm(struct btc_coexist *btcoexist,
- u8 lps_val, u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-static void halbtc8822b2ant_lps_rpwm(struct btc_coexist *btcoexist,
- bool force_exec, u8 lps_val, u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8822b2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-static void halbtc8822b2ant_ps_tdma_check_for_power_save_state(
- struct btc_coexist *btcoexist, bool new_ps_state)
-{
- u8 lps_mode = 0x0;
- u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0};
- u32 RTL97F_8822B = 0;
-
- if (RTL97F_8822B)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
- h2c_parameter);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
- h2c_parameter);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-static bool halbtc8822b2ant_power_save_state(struct btc_coexist *btcoexist,
- u8 ps_type, u8 lps_val,
- u8 rpwm_val)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool low_pwr_disable = false, result = true;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- coex_sta->force_lps_ctrl = false;
- /* recover to original 32k low power setting */
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == BTC_PS_WIFI_NATIVE\n", __func__);
-
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
- break;
- case BTC_PS_LPS_ON:
- coex_sta->force_lps_ctrl = true;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == BTC_PS_LPS_ON\n", __func__);
-
- halbtc8822b2ant_ps_tdma_check_for_power_save_state(btcoexist,
- true);
- halbtc8822b2ant_lps_rpwm(btcoexist, NORMAL_EXEC, lps_val,
- rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
- break;
- case BTC_PS_LPS_OFF:
- coex_sta->force_lps_ctrl = true;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == BTC_PS_LPS_OFF\n", __func__);
-
- halbtc8822b2ant_ps_tdma_check_for_power_save_state(btcoexist,
- false);
- result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- break;
- default:
- break;
- }
-
- return result;
-}
-
-static void halbtc8822b2ant_set_fw_pstdma(struct btc_coexist *btcoexist,
- u8 byte1, u8 byte2, u8 byte3,
- u8 byte4, u8 byte5)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- bool ap_enable = false, result = false;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- if (byte5 & BIT(2))
- coex_sta->is_tdma_btautoslot = true;
- else
- coex_sta->is_tdma_btautoslot = false;
-
- /* release bt-auto slot for auto-slot hang is detected!! */
- if (coex_sta->is_tdma_btautoslot)
- if ((coex_sta->is_tdma_btautoslot_hang) ||
- (bt_link_info->slave_role))
- byte5 = byte5 & 0xfb;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == FW for AP mode\n", __func__);
-
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
-
- halbtc8822b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == Force LPS (byte1 = 0x%x)\n",
- __func__, byte1);
-
- if (!halbtc8822b2ant_power_save_state(btcoexist, BTC_PS_LPS_OFF,
- 0x50, 0x4))
- result = true;
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == Native LPS (byte1 = 0x%x)\n",
- __func__, byte1);
-
- halbtc8822b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- }
-
- coex_sta->is_set_ps_state_fail = result;
-
- if (!coex_sta->is_set_ps_state_fail) {
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
- } else {
- coex_sta->cnt_set_ps_state_fail++;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], %s == Force Leave LPS Fail (cnt = %d)\n",
- __func__, coex_sta->cnt_set_ps_state_fail);
- }
-}
-
-static void halbtc8822b2ant_ps_tdma(struct btc_coexist *btcoexist,
- bool force_exec, bool turn_on, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u8 ps_tdma_byte4_modify, pre_ps_tdma_byte4_modify;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
- if (bt_link_info->slave_role)
- ps_tdma_byte4_modify = 0x1;
- else
- ps_tdma_byte4_modify = 0x0;
-
- if (pre_ps_tdma_byte4_modify != ps_tdma_byte4_modify) {
- force_exec = true;
- pre_ps_tdma_byte4_modify = ps_tdma_byte4_modify;
- }
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n",
- (coex_dm->cur_ps_tdma_on ? "on" : "off"),
- coex_dm->cur_ps_tdma);
- return;
- }
- }
-
- if (coex_dm->cur_ps_tdma_on) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** TDMA(on, %d) **********\n",
- coex_dm->cur_ps_tdma);
-
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x550, 0x8, 0x1); /* enable TBTT nterrupt */
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** TDMA(off, %d) **********\n",
- coex_dm->cur_ps_tdma);
- }
-
- if (turn_on) {
- switch (type) {
- case 1:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x10, 0x03, 0x91,
- 0x54 | ps_tdma_byte4_modify);
- break;
- case 2:
- default:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x35, 0x03, 0x11,
- 0x11 | ps_tdma_byte4_modify);
- break;
- case 3:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x3a, 0x3, 0x91,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 4:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x21, 0x3, 0x91,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 5:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x25, 0x3, 0x91,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 6:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x10, 0x3, 0x91,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 7:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x20, 0x3, 0x91,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 8:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, 0x15,
- 0x03, 0x11, 0x11);
- break;
- case 10:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, 0x30,
- 0x03, 0x11, 0x10);
- break;
- case 11:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x35, 0x03, 0x11,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 12:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, 0x35,
- 0x03, 0x11, 0x11);
- break;
- case 13:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x1c, 0x03, 0x11,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 14:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, 0x20,
- 0x03, 0x11, 0x11);
- break;
- case 15:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, 0x10,
- 0x03, 0x11, 0x14);
- break;
- case 16:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, 0x10,
- 0x03, 0x11, 0x15);
- break;
- case 21:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, 0x30,
- 0x03, 0x11, 0x10);
- break;
- case 22:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, 0x25,
- 0x03, 0x11, 0x10);
- break;
- case 23:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61, 0x10,
- 0x03, 0x11, 0x10);
- break;
- case 51:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x10, 0x03, 0x91,
- 0x10 | ps_tdma_byte4_modify);
- break;
- case 101:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x25, 0x03, 0x11,
- 0x11 | ps_tdma_byte4_modify);
- break;
- case 102:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x35, 0x03, 0x11,
- 0x11 | ps_tdma_byte4_modify);
- break;
- case 103:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x51, 0x3a, 0x3, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
- case 104:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x51, 0x21, 0x3, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
- case 105:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x51, 0x30, 0x3, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
- case 106:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x51, 0x10, 0x3, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
- case 107:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x51, 0x10, 0x7, 0x10,
- 0x54 | ps_tdma_byte4_modify);
- break;
- case 108:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x51, 0x30, 0x3, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
- case 109:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x51, 0x10, 0x03, 0x10,
- 0x54 | ps_tdma_byte4_modify);
- break;
- case 110:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x55, 0x30, 0x03, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
- case 111:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x61, 0x25, 0x03, 0x11,
- 0x11 | ps_tdma_byte4_modify);
- break;
- case 151:
- halbtc8822b2ant_set_fw_pstdma(
- btcoexist, 0x51, 0x10, 0x03, 0x10,
- 0x50 | ps_tdma_byte4_modify);
- break;
- }
- } else {
- /* disable PS tdma */
- switch (type) {
- case 0:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0,
- 0x40, 0x0);
- break;
- case 1:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0,
- 0x48, 0x0);
- break;
- default:
- halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0, 0x0, 0x0,
- 0x40, 0x0);
- break;
- }
- }
-
- if (!coex_sta->is_set_ps_state_fail) {
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
- }
-}
-
-/*anttenna control by bb mac bt antdiv pta to write 0x4c 0xcb4,0xcbd*/
-static void halbtc8822b2ant_set_ext_ant_switch(struct btc_coexist *btcoexist,
- bool force_exec, u8 ctrl_type,
- u8 pos_type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool switch_polatiry_inverse = false;
- u8 regval_0xcbc = 0, regval_0x64;
- u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
-
- if (!rfe_type->ext_ant_switch_exist)
- return;
-
- coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type;
-
- if (!force_exec) {
- if (coex_dm->pre_ext_ant_switch_status ==
- coex_dm->cur_ext_ant_switch_status)
- return;
- }
- coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status;
-
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
-
- switch (ctrl_type) {
- default:
- case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80,
- 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01,
- 0x1); /* 0x4c[24] = 1 */
- /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff,
- 0x77);
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 01);
-
- break;
- case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80,
- 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01,
- 0x1); /* 0x4c[24] = 1 */
- /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff,
- 0x66);
-
- /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse,
- * DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1
- */
- regval_0xcbc = (!switch_polatiry_inverse ? 0x2 : 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbc, 0x03,
- regval_0xcbc);
-
- break;
- case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80,
- 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01,
- 0x1); /* 0x4c[24] = 1 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff,
- 0x88);
- break;
- case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80,
- 0x1); /* 0x4c[23] = 1 */
-
- /* 0x64[0] = 1b'0 for no switch_polatiry_inverse,
- * DPDT_SEL_N =1, DPDT_SEL_P =0
- */
- regval_0x64 = (!switch_polatiry_inverse ? 0x0 : 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1,
- regval_0x64);
- break;
- case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80,
- 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01,
- 0x0); /* 0x4c[24] = 0 */
-
- /* no setup required, because antenna switch control value by
- * BT vendor 0x1c[1:0]
- */
- break;
- }
-
- /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue*/
- if (ctrl_type == BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT) {
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x67, 0x20, 0x0); /* PAPE 0x64[29] = 0 */
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x67, 0x10, 0x0); /* LNA_ON 0x64[28] = 0 */
- } else {
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x67, 0x20, 0x1); /* PAPE 0x64[29] = 1 */
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x67, 0x10, 0x1); /* LNA_ON 0x64[28] = 1 */
- }
-
- if (btcoexist->dbg_mode_2ant) {
- u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n",
- u32tmp1, u32tmp2, u32tmp3);
- }
-}
-
-/* rf4 type by efuse, and for ant at main aux inverse use,
- * because is 2x2, and control types are the same, does not need
- */
-static void halbtc8822b2ant_set_rfe_type(struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- rfe_type->ext_band_switch_exist = false;
- rfe_type->ext_band_switch_type =
- BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT; /* SPDT; */
- rfe_type->ext_band_switch_ctrl_polarity = 0;
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
-
- if (rfe_type->ext_band_switch_exist) {
- /* band switch use RFE_ctrl1 (pin name: PAPE_A) and
- * RFE_ctrl3 (pin name: LNAON_A)
- */
-
- /* set RFE_ctrl1 as software control */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb0, 0xf0, 0x7);
-
- /* set RFE_ctrl3 as software control */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb1, 0xf0, 0x7);
- }
-
- /* the following setup should be got from Efuse in the future */
- rfe_type->rfe_module_type = board_info->rfe_type;
-
- rfe_type->ext_ant_switch_ctrl_polarity = 0;
-
- switch (rfe_type->rfe_module_type) {
- case 0:
- default:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 1:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 2:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 3:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 4:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 5:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 6:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 7:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type =
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- }
-}
-
-/* set gnt_wl gnt_bt control by sw high low, or hwpta while in
- * power on, ini, wlan off, wlan only, wl2g non-currrent, wl2g current, wl5g
- */
-static void halbtc8822b2ant_set_ant_path(struct btc_coexist *btcoexist,
- u8 ant_pos_type, bool force_exec,
- u8 phase)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 u8tmp = 0;
- u32 u32tmp1 = 0;
- u32 u32tmp2 = 0, u32tmp3 = 0;
-
- u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
-
- /* To avoid indirect access fail */
- if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
- force_exec = true;
- coex_sta->gnt_error_cnt++;
- }
-
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80,
- 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01,
- 0x1); /* 0x4c[24] = 1 */
-
- coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase;
-
- if (!force_exec) {
- if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type)
- return;
- }
-
- coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
-
- if (btcoexist->dbg_mode_2ant) {
- u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0x38);
- u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0x54);
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
- u32tmp3, u8tmp, u32tmp1, u32tmp2);
- }
-
- switch (phase) {
- case BT_8822B_2ANT_PHASE_COEX_POWERON:
-
- /* set Path control owner to WL at initial step */
- halbtc8822b2ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_2ANT_PCO_BTSIDE);
-
- /* set GNT_BT to SW high */
- halbtc8822b2ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to SW high */
- halbtc8822b2ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
-
- coex_sta->run_time_state = false;
-
- break;
- case BT_8822B_2ANT_PHASE_COEX_INIT:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80,
- 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01,
- 0x1); /* 0x4c[24] = 1 */
- /* Disable LTE Coex Function in WiFi side
- * (this should be on if LTE coex is required)
- */
- halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
-
- /* GNT_WL_LTE always = 1
- * (this should be config if LTE coex is required)
- */
- halbtc8822b2ant_ltecoex_set_coex_table(
- btcoexist, BT_8822B_2ANT_CTT_WL_VS_LTE, 0xffff);
-
- /* GNT_BT_LTE always = 1
- * (this should be config if LTE coex is required)
- */
- halbtc8822b2ant_ltecoex_set_coex_table(
- btcoexist, BT_8822B_2ANT_CTT_BT_VS_LTE, 0xffff);
-
- /* set Path control owner to WL at initial step */
- halbtc8822b2ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_2ANT_PCO_WLSIDE);
-
- /* set GNT_BT to SW high */
- halbtc8822b2ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to SW high */
- halbtc8822b2ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
-
- coex_sta->run_time_state = false;
-
- break;
- case BT_8822B_2ANT_PHASE_WLANONLY_INIT:
- /* Disable LTE Coex Function in WiFi side
- * (this should be on if LTE coex is required)
- */
- halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
-
- /* GNT_WL_LTE always = 1
- * (this should be config if LTE coex is required)
- */
- halbtc8822b2ant_ltecoex_set_coex_table(
- btcoexist, BT_8822B_2ANT_CTT_WL_VS_LTE, 0xffff);
-
- /* GNT_BT_LTE always = 1
- * (this should be config if LTE coex is required)
- */
- halbtc8822b2ant_ltecoex_set_coex_table(
- btcoexist, BT_8822B_2ANT_CTT_BT_VS_LTE, 0xffff);
-
- /* set Path control owner to WL at initial step */
- halbtc8822b2ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_2ANT_PCO_WLSIDE);
-
- /* set GNT_BT to SW Low */
- halbtc8822b2ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_LOW);
- /* Set GNT_WL to SW high */
- halbtc8822b2ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
-
- coex_sta->run_time_state = false;
-
- break;
- case BT_8822B_2ANT_PHASE_WLAN_OFF:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80,
- 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01,
- 0x0); /* 0x4c[24] = 0 */
- /* Disable LTE Coex Function in WiFi side */
- halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
-
- /* set Path control owner to BT */
- halbtc8822b2ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_2ANT_PCO_BTSIDE);
-
- /* Set Ext Ant Switch to BT control at wifi off step */
- halbtc8822b2ant_set_ext_ant_switch(
- btcoexist, FORCE_EXEC,
- BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT,
- BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE);
- coex_sta->run_time_state = false;
- break;
- case BT_8822B_2ANT_PHASE_2G_RUNTIME:
- case BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT:
-
- /* set Path control owner to WL at runtime step */
- halbtc8822b2ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_2ANT_PCO_WLSIDE);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff,
- 0x66);
- if (phase == BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT) {
- /* set GNT_BT to PTA */
- halbtc8822b2ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA,
- BT_8822B_2ANT_SIG_STA_SET_BY_HW);
-
- /* Set GNT_WL to SW High */
- halbtc8822b2ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
- } else {
- /* set GNT_BT to PTA */
- halbtc8822b2ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA,
- BT_8822B_2ANT_SIG_STA_SET_BY_HW);
-
- /* Set GNT_WL to PTA */
- halbtc8822b2ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA,
- BT_8822B_2ANT_SIG_STA_SET_BY_HW);
- }
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ************* under2g 0xcbd setting =2 *************\n");
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 02);
- break;
-
- case BT_8822B_2ANT_PHASE_5G_RUNTIME:
-
- /* set Path control owner to WL at runtime step */
- halbtc8822b2ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_2ANT_PCO_WLSIDE);
-
- /* set GNT_BT to SW Hi */
- halbtc8822b2ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to SW Hi */
- halbtc8822b2ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
- coex_sta->run_time_state = true;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ************* under5g 0xcbd setting =1 *************\n");
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 01);
-
- break;
- case BT_8822B_2ANT_PHASE_BTMPMODE:
- /* Disable LTE Coex Function in WiFi side */
- halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
-
- /* set Path control owner to WL */
- halbtc8822b2ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8822B_2ANT_PCO_WLSIDE);
-
- /* set GNT_BT to SW Hi */
- halbtc8822b2ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
-
- /* Set GNT_WL to SW Lo */
- halbtc8822b2ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_LOW);
-
- coex_sta->run_time_state = false;
- break;
- }
-
- if (btcoexist->dbg_mode_2ant) {
- u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0x38);
- u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0x54);
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], (After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
- phase, u32tmp3, u8tmp, u32tmp1, u32tmp2);
- }
-}
-
-static u8 halbtc8822b2ant_action_algorithm(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool bt_hs_on = false;
- u8 algorithm = BT_8822B_2ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], No BT link exists!!!\n");
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 0) {
- if (bt_link_info->acl_busy) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], No-Profile busy\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY;
- }
- } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], A2DP Sink\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_A2DPSINK;
- } else if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], SCO only\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], HID only\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], A2DP only\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], PAN(HS) only\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_PANHS;
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], PAN(EDR) only\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], SCO + HID\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->a2dp_exist) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], SCO + A2DP ==> A2DP\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], SCO + PAN(HS)\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_SCO;
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], SCO + PAN(EDR)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_PANEDR;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], HID + A2DP\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_HID_A2DP;
- }
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], HID + PAN(HS)\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_HID;
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], HID + PAN(EDR)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], A2DP + PAN(HS)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], A2DP + PAN(EDR)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n");
- algorithm = BT_8822B_2ANT_COEX_ALGO_HID_A2DP;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], SCO + HID + PAN(HS)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_PANEDR_HID;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], SCO + HID + PAN(EDR)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], SCO + A2DP + PAN(HS)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], HID + A2DP + PAN(HS)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], HID + A2DP + PAN(EDR)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- algorithm =
- BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-static void halbtc8822b2ant_action_coex_all_off(struct btc_coexist *btcoexist)
-{
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-
- /* fw all off */
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-}
-
-static void halbtc8822b2ant_action_wifi_under5g(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- /* fw all off */
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ************* under5g *************\n");
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_2ANT_PHASE_5G_RUNTIME);
-}
-
-static void
-halbtc8822b2ant_action_wifi_native_lps(struct btc_coexist *btcoexist)
-{
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-}
-
-static void halbtc8822b2ant_action_bt_inquiry(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_connected = false;
- bool wifi_scan = false, wifi_link = false, wifi_roam = false;
- bool wifi_busy = false;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
-
- if ((coex_sta->bt_create_connection) &&
- ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) ||
- (coex_sta->wifi_is_high_pri_task))) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n");
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-
- if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist))
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 15);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 11);
- } else if ((!wifi_connected) && (!wifi_scan)) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n");
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (bt_link_info->pan_exist) {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-
- } else if (bt_link_info->a2dp_exist) {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8);
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 10);
- } else {
- if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) ||
- (coex_sta->wifi_is_high_pri_task))
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 21);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 23);
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
- }
-
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8);
-}
-
-static void
-halbtc8822b2ant_action_wifi_link_process(struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd4);
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-
- if (bt_link_info->pan_exist) {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-
- } else if (bt_link_info->a2dp_exist) {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 16);
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
- } else {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
- }
-}
-
-static void
-halbtc8822b2ant_action_wifi_nonconnected(struct btc_coexist *btcoexist)
-{
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* fw all off */
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-}
-
-static void halbtc8822b2ant_action_bt_relink(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], run bt multi link function\n");
-
- if (coex_sta->is_bt_multi_link)
- return;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], run bt re-link function\n");
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-}
-
-static void halbtc8822b2ant_action_bt_idle(struct btc_coexist *btcoexist)
-{
- bool wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_busy) {
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
- } else { /* if wl busy */
-
- if (BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- } else {
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 8);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 12);
- }
- }
-
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8);
-}
-
-/* SCO only or SCO+PAN(HS) */
-static void halbtc8822b2ant_action_sco(struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false;
- u32 wifi_bw = 1;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- if (coex_sta->is_esco_mode)
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- else /* 2-Ant free run if SCO mode */
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8);
- }
-}
-
-static void halbtc8822b2ant_action_hid(struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false;
- u32 wifi_bw = 1;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- if (coex_sta->is_hid_low_pri_tx_overhead) {
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 108);
- } else if (wifi_bw == 0) { /* if 11bg mode */
-
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 8);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 111);
- } else {
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 8);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 111);
- }
- }
-}
-
-static void halbtc8822b2ant_action_a2dpsink(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false, wifi_turbo = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
- coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
-
- if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
- wifi_turbo = true;
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy)
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 1);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 16);
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- if ((coex_sta->bt_relink_downcount != 0) && (wifi_busy)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Re-Link + A2DP + WL busy\n");
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 5);
-
- } else {
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 8);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 105);
- }
- }
-}
-
-/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
-static void halbtc8822b2ant_action_a2dp(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false, wifi_turbo = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
- coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
-
- if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
- wifi_turbo = true;
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy)
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 1);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 16);
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- if ((coex_sta->bt_relink_downcount != 0) && (wifi_busy)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Re-Link + A2DP + WL busy\n");
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 5);
-
- } else {
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 10);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 109);
- }
- }
-}
-
-static void halbtc8822b2ant_action_pan_edr(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false, wifi_turbo = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
- coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
-
- if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
- wifi_turbo = true;
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy)
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 3);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 4);
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-
- if (wifi_busy)
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 103);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 104);
- }
-}
-
-static void halbtc8822b2ant_action_hid_a2dp(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false;
- u32 wifi_bw = 1;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy)
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 1);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 16);
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- if ((coex_sta->bt_relink_downcount != 0) && (wifi_busy)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Re-Link + A2DP + WL busy\n");
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 5);
- } else {
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 8);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 109);
- }
- }
-}
-
-static void halbtc8822b2ant_action_a2dp_pan_hs(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false, wifi_turbo = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
- coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
-
- if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
- wifi_turbo = true;
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
- /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);*/
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy) {
- if ((coex_sta->a2dp_bit_pool > 40) &&
- (coex_sta->a2dp_bit_pool < 255))
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 7);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 5);
- } else {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 6);
- }
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- /*halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);*/
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- if (wifi_turbo)
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 6);
- else
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 7);
-
- if (wifi_busy) {
- if ((coex_sta->a2dp_bit_pool > 40) &&
- (coex_sta->a2dp_bit_pool < 255))
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 107);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 105);
- } else {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 106);
- }
- }
-}
-
-/* PAN(EDR)+A2DP */
-static void halbtc8822b2ant_action_pan_edr_a2dp(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false, wifi_turbo = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
- coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
-
- if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
- wifi_turbo = true;
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy) {
- if (((coex_sta->a2dp_bit_pool > 40) &&
- (coex_sta->a2dp_bit_pool < 255)) ||
- (!coex_sta->is_A2DP_3M))
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 7);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 5);
- } else {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 6);
- }
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
- if (wifi_busy)
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 107);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 106);
- }
-}
-
-static void halbtc8822b2ant_action_pan_edr_hid(struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false;
- u32 wifi_bw = 1;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy)
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 3);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 4);
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
- halbtc8822b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-
- if (wifi_busy)
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 103);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 104);
- }
-}
-
-/* HID+A2DP+PAN(EDR) */
-static void
-halbtc8822b2ant_action_hid_a2dp_pan_edr(struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false;
- u32 wifi_bw = 1;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy) {
- if (((coex_sta->a2dp_bit_pool > 40) &&
- (coex_sta->a2dp_bit_pool < 255)) ||
- (!coex_sta->is_A2DP_3M))
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 7);
- else
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 5);
- } else {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 6);
- }
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- if (coex_sta->hid_busy_num >= 2) {
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 8);
-
- if (wifi_bw == 0) {
- halbtc8822b2ant_set_wltoggle_coex_table(
- btcoexist, NORMAL_EXEC, 0x1, 0xaa, 0x5a,
- 0xaa, 0xaa);
- } else {
- halbtc8822b2ant_set_wltoggle_coex_table(
- btcoexist, NORMAL_EXEC, 0x2, 0xaa, 0x5a,
- 0xaa, 0xaa);
- }
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 110);
- } else {
- halbtc8822b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
-
- if (wifi_busy) {
- if ((coex_sta->a2dp_bit_pool > 40) &&
- (coex_sta->a2dp_bit_pool < 255))
- halbtc8822b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC,
- true, 107);
- else
- halbtc8822b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC,
- true, 105);
- } else {
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 106);
- }
- }
- }
-}
-
-static void halbtc8822b2ant_action_bt_whck_test(struct btc_coexist *btcoexist)
-{
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-}
-
-static void halbtc8822b2ant_action_bt_hs(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- bool wifi_busy = false, wifi_turbo = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
- coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
-
- if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
- wifi_turbo = true;
-
- wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state, 2, coex_sta->wifi_coex_thres,
- 0);
-
- wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(
- btcoexist, &prewifi_rssi_state2, 2, coex_sta->wifi_coex_thres2,
- 0);
-
- bt_rssi_state = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state, 2, coex_sta->bt_coex_thres, 0);
-
- bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(
- btcoexist, &pre_bt_rssi_state2, 2, coex_sta->bt_coex_thres2, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- } else {
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
-}
-
-static void
-halbtc8822b2ant_action_wifi_multi_port(struct btc_coexist *btcoexist)
-{
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-
- /* hw all off */
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-}
-
-static void halbtc8822b2ant_action_wifi_connected(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- switch (coex_dm->cur_algorithm) {
- case BT_8822B_2ANT_COEX_ALGO_SCO:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
- halbtc8822b2ant_action_sco(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_HID:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = HID.\n");
- halbtc8822b2ant_action_hid(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_A2DP:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
- halbtc8822b2ant_action_a2dp(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_A2DPSINK:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = A2DP Sink.\n");
- halbtc8822b2ant_action_a2dpsink(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
- halbtc8822b2ant_action_a2dp_pan_hs(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_PANEDR:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
- halbtc8822b2ant_action_pan_edr(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
- halbtc8822b2ant_action_pan_edr_a2dp(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_PANEDR_HID:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
- halbtc8822b2ant_action_pan_edr_hid(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
- halbtc8822b2ant_action_hid_a2dp_pan_edr(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_HID_A2DP:
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
- halbtc8822b2ant_action_hid_a2dp(btcoexist);
- break;
- case BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n");
- halbtc8822b2ant_action_bt_idle(btcoexist);
- break;
- default:
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
- halbtc8822b2ant_action_coex_all_off(btcoexist);
- break;
- }
-
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
-}
-
-static void halbtc8822b2ant_run_coexist_mechanism(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 algorithm = 0;
- u32 num_of_wifi_link = 0;
- u32 wifi_link_status = 0;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bool miracast_plus_bt = false;
- bool scan = false, link = false, roam = false, under_4way = false,
- wifi_connected = false, wifi_under_5g = false, bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RunCoexistMechanism()===>\n");
-
- if (btcoexist->manual_control) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- return;
- }
-
- if (coex_sta->under_ips) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], wifi is under IPS !!!\n");
- return;
- }
-
- if ((coex_sta->under_lps) &&
- (coex_dm->bt_status != BT_8822B_2ANT_BT_STATUS_ACL_BUSY)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n");
- halbtc8822b2ant_action_wifi_native_lps(btcoexist);
- return;
- }
-
- if (!coex_sta->run_time_state) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], return for run_time_state = false !!!\n");
- return;
- }
-
- if (coex_sta->freeze_coexrun_by_btinfo) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n");
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if ((wifi_under_5g) &&
- (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) &&
- (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], WiFi is under 5G!!!\n");
-
- halbtc8822b2ant_action_wifi_under5g(btcoexist);
- return;
- }
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], WiFi is under 2G!!!\n");
-
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
- BT_8822B_2ANT_PHASE_2G_RUNTIME);
-
- if (coex_sta->bt_whck_test) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- halbtc8822b2ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- if (coex_sta->bt_disabled) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is disabled!!!\n");
- halbtc8822b2ant_action_coex_all_off(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is under inquiry/page scan !!\n");
- halbtc8822b2ant_action_bt_inquiry(btcoexist);
- return;
- }
-
- if (coex_sta->is_setup_link) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT is re-link !!!\n");
- halbtc8822b2ant_action_bt_relink(btcoexist);
- return;
- }
-
- /* for P2P */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
-
- if (bt_link_info->bt_link_exist)
- miracast_plus_bt = true;
- else
- miracast_plus_bt = false;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
-
- if (scan || link || roam || under_4way) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
- scan, link, roam, under_4way);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], wifi is under linkscan process + Multi-Port !!\n");
-
- halbtc8822b2ant_action_wifi_link_process(btcoexist);
- } else {
- halbtc8822b2ant_action_wifi_multi_port(btcoexist);
- }
-
- return;
- }
-
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (bt_hs_on) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "############# [BTCoex], BT Is hs\n");
- halbtc8822b2ant_action_bt_hs(btcoexist);
- return;
- }
-
- if ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ||
- (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE)) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, bt idle!!.\n");
-
- halbtc8822b2ant_action_bt_idle(btcoexist);
- return;
- }
-
- algorithm = halbtc8822b2ant_action_algorithm(btcoexist);
- coex_dm->cur_algorithm = algorithm;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Algorithm = %d\n", coex_dm->cur_algorithm);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- if (scan || link || roam || under_4way) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], WiFi is under Link Process !!\n");
- halbtc8822b2ant_action_wifi_link_process(btcoexist);
- } else if (wifi_connected) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, wifi connected!!.\n");
- halbtc8822b2ant_action_wifi_connected(btcoexist);
-
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Action 2-Ant, wifi not-connected!!.\n");
- halbtc8822b2ant_action_wifi_nonconnected(btcoexist);
- }
-}
-
-static void halbtc8822b2ant_init_coex_dm(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Coex Mechanism Init!!\n");
-
- halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, false);
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-
- /* fw all off */
- halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8822b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8);
-
- coex_sta->pop_event_cnt = 0;
- coex_sta->cnt_remote_name_req = 0;
- coex_sta->cnt_reinit = 0;
- coex_sta->cnt_setup_link = 0;
- coex_sta->cnt_ign_wlan_act = 0;
- coex_sta->cnt_page = 0;
- coex_sta->cnt_role_switch = 0;
- coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
-
- halbtc8822b2ant_query_bt_info(btcoexist);
-}
-
-static void halbtc8822b2ant_init_hw_config(struct btc_coexist *btcoexist,
- bool wifi_only)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
- u32 RTL97F_8822B = 0;
- u8 i = 0;
-
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- if (RTL97F_8822B) {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x04, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x0);
-
- /* set GNT_BT to SW high */
- halbtc8822b2ant_ltecoex_set_gnt_bt(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to SW high */
- halbtc8822b2ant_ltecoex_set_gnt_wl(
- btcoexist, BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
- return;
- }
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
- u32tmp3, u32tmp1, u32tmp2);
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], 2Ant Init HW Config!!\n");
-
- coex_sta->bt_coex_supported_feature = 0;
- coex_sta->bt_coex_supported_version = 0;
- coex_sta->bt_ble_scan_type = 0;
- coex_sta->bt_ble_scan_para[0] = 0;
- coex_sta->bt_ble_scan_para[1] = 0;
- coex_sta->bt_ble_scan_para[2] = 0;
- coex_sta->bt_reg_vendor_ac = 0xffff;
- coex_sta->bt_reg_vendor_ae = 0xffff;
- coex_sta->isolation_btween_wb = BT_8822B_2ANT_DEFAULT_ISOLATION;
- coex_sta->gnt_error_cnt = 0;
- coex_sta->bt_relink_downcount = 0;
- coex_sta->is_set_ps_state_fail = false;
- coex_sta->cnt_set_ps_state_fail = 0;
-
- for (i = 0; i <= 9; i++)
- coex_sta->bt_afh_map[i] = 0;
-
- /* 0xf0[15:12] --> Chip Cut information */
- coex_sta->cut_version =
- (btcoexist->btc_read_1byte(btcoexist, 0xf1) & 0xf0) >> 4;
-
- coex_sta->dis_ver_info_cnt = 0;
-
- halbtc8822b2ant_coex_switch_threshold(btcoexist,
- coex_sta->isolation_btween_wb);
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
-
- /* BT report packet sample rate */
- btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
-
- /* Init 0x778 = 0x1 for 2-Ant */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
-
- /* Enable PTA (3-wire function form BT side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
-
- /* Enable PTA (tx/rx signal form WiFi side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
-
- halbtc8822b2ant_enable_gnt_to_gpio(btcoexist, true);
-
- /*GNT_BT=1 while select both */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1);
-
- /* check if WL firmware download ok */
- halbtc8822b2ant_post_state_to_bt(btcoexist,
- BT_8822B_2ANT_SCOREBOARD_ONOFF, true);
-
- /* Enable counter statistics */
- btcoexist->btc_write_1byte(
- btcoexist, 0x76e,
- 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */
-
- halbtc8822b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 5);
-
- halbtc8822b2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
-
- psd_scan->ant_det_is_ant_det_available = true;
-
- if (coex_sta->is_rf_state_off) {
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_WLAN_OFF);
-
- btcoexist->stop_coex_dm = true;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** %s (RF Off)**********\n",
- __func__);
- } else if (wifi_only) {
- coex_sta->concurrent_rx_mode_on = false;
- /* Path config */
- /* Set Antenna Path */
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_WLANONLY_INIT);
-
- btcoexist->stop_coex_dm = true;
- } else {
- /* Set BT polluted packet on for Tx rate adaptive not including
- * Tx retry break by PTA, 0x45c[19] =1
- */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
-
- coex_sta->concurrent_rx_mode_on = true;
-
- /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for
- * con-current Rx, mask Tx only
- */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0);
-
- /* Set Antenna Path */
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_COEX_INIT);
-
- btcoexist->stop_coex_dm = false;
- }
-}
-
-/* ************************************************************
- * work around function start with wa_halbtc8822b2ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8822b2ant_
- * *************************************************************/
-void ex_btc8822b2ant_power_on_setting(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x0;
- u16 u16tmp = 0x0;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "xxxxxxxxxxxxxxxx Execute 8822b 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "Ant Det Finish = %s, Ant Det Number = %d\n",
- (board_info->btdm_ant_det_finish ? "Yes" : "No"),
- board_info->btdm_ant_num_by_ant_det);
-
- btcoexist->dbg_mode_2ant = false;
- btcoexist->stop_coex_dm = true;
- psd_scan->ant_det_is_ant_det_available = false;
-
- /* enable BB, REG_SYS_FUNC_EN such that we can write BB Reg correctly */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
- btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
-
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==>
- * BIT1=0 and BIT2=0
- */
-
- /* Check efuse 0xc3[6] for Single Antenna Path */
-
- /* Setup RF front end type */
- halbtc8822b2ant_set_rfe_type(btcoexist);
-
- /* Set Antenna Path to BT side */
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_2ANT_PHASE_COEX_POWERON);
-
- /* Save"single antenna position" info in Local register setting for
- * FW reading, because FW may not ready at power on
- */
- if (btcoexist->chip_interface == BTC_INTF_PCI)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
-
- /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
- halbtc8822b2ant_enable_gnt_to_gpio(btcoexist, true);
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n",
- halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n",
- btcoexist->btc_read_4byte(btcoexist, 0x70),
- btcoexist->btc_read_4byte(btcoexist, 0xcb4));
-}
-
-void ex_btc8822b2ant_pre_load_firmware(struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
-
- /* */
- /* S0 or S1 setting and Local register setting
- * (By the setting fw can get ant number, S0/S1, ... info)
- */
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==>
- * BIT1=0 and BIT2=0
- */
- if (btcoexist->chip_interface == BTC_INTF_USB) {
- /* fixed at S0 for USB interface */
- u8tmp |= 0x1; /* antenna inverse */
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- } else {
- /* for PCIE and SDIO interface, we check efuse 0xc3[6] */
- if (board_info->single_ant_path == 0) {
- } else if (board_info->single_ant_path == 1) {
- /* set to S0 */
- u8tmp |= 0x1; /* antenna inverse */
- }
-
- if (btcoexist->chip_interface == BTC_INTF_PCI)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0,
- u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
- u8tmp);
- }
-}
-
-void ex_btc8822b2ant_init_hw_config(struct btc_coexist *btcoexist,
- bool wifi_only)
-{
- halbtc8822b2ant_init_hw_config(btcoexist, wifi_only);
- btcoexist->auto_report_2ant = true;
-}
-
-void ex_btc8822b2ant_init_coex_dm(struct btc_coexist *btcoexist)
-{
- halbtc8822b2ant_init_coex_dm(btcoexist);
-}
-
-void ex_btc8822b2ant_display_coex_info(struct btc_coexist *btcoexist,
- struct seq_file *m)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- u8 u8tmp[4], i, ps_tdma_case = 0;
- u32 u32tmp[4];
- u16 u16tmp[4];
- u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck, ratio_ofdm;
- u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
- static u8 pop_report_in_10s;
- u32 phyver = 0;
- bool lte_coex_on = false;
- static u8 cnt;
-
- seq_puts(m, "\r\n ============[BT Coexist info]============");
-
- if (btcoexist->manual_control) {
- seq_puts(m,
- "\r\n ============[Under Manual Control]============");
- seq_puts(m, "\r\n ==========================================");
- }
-
- if (!coex_sta->bt_disabled) {
- if (coex_sta->bt_coex_supported_feature == 0)
- btcoexist->btc_get(
- btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
- &coex_sta->bt_coex_supported_feature);
-
- if ((coex_sta->bt_coex_supported_version == 0) ||
- (coex_sta->bt_coex_supported_version == 0xffff))
- btcoexist->btc_get(
- btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
- &coex_sta->bt_coex_supported_version);
-
- if (coex_sta->bt_reg_vendor_ac == 0xffff)
- coex_sta->bt_reg_vendor_ac = (u16)(
- btcoexist->btc_get_bt_reg(btcoexist, 3, 0xac) &
- 0xffff);
-
- if (coex_sta->bt_reg_vendor_ae == 0xffff)
- coex_sta->bt_reg_vendor_ae = (u16)(
- btcoexist->btc_get_bt_reg(btcoexist, 3, 0xae) &
- 0xffff);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
- &bt_patch_ver);
- btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
-
- if (coex_sta->num_of_profile > 0) {
- cnt++;
-
- if (cnt >= 3) {
- btcoexist->btc_get_bt_afh_map_from_bt(
- btcoexist, 0, &coex_sta->bt_afh_map[0]);
- cnt = 0;
- }
- }
- }
-
- if (psd_scan->ant_det_try_count == 0) {
- seq_printf(
- m, "\r\n %-35s = %d/ %d/ %s / %d",
- "Ant PG Num/ Mech/ Pos/ RFE", board_info->pg_ant_num,
- board_info->btdm_ant_num,
- (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT ?
- "Main" :
- "Aux"),
- rfe_type->rfe_module_type);
- } else {
- seq_printf(
- m, "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)",
- "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE",
- board_info->pg_ant_num,
- board_info->btdm_ant_num_by_ant_det,
- (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT ?
- "Main" :
- "Aux"),
- rfe_type->rfe_module_type, psd_scan->ant_det_try_count,
- psd_scan->ant_det_fail_count, psd_scan->ant_det_result);
-
- if (board_info->btdm_ant_det_finish) {
- if (psd_scan->ant_det_result != 12)
- seq_printf(m, "\r\n %-35s = %s",
- "Ant Det PSD Value",
- psd_scan->ant_det_peak_val);
- else
- seq_printf(m, "\r\n %-35s = %d",
- "Ant Det PSD Value",
- psd_scan->ant_det_psd_scan_peak_val /
- 100);
- }
- }
-
- bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
-
- bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff);
-
- seq_printf(
- m, "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
- "CoexVer WL/ BT_Desired/ BT_Report",
- glcoex_ver_date_8822b_2ant, glcoex_ver_8822b_2ant,
- glcoex_ver_btdesired_8822b_2ant, bt_coex_ver,
- (bt_coex_ver == 0xff ?
- "Unknown" :
- (coex_sta->bt_disabled ? "BT-disable" :
- (bt_coex_ver >= glcoex_ver_btdesired_8822b_2ant ?
- "Match" :
- "Mis-Match"))));
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", "W_FW/ B_FW/ Phy/ Kt",
- fw_ver, bt_patch_ver, phyver, coex_sta->cut_version + 65);
-
- seq_printf(m, "\r\n %-35s = %02x %02x %02x ", "AFH Map to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
-
- seq_printf(m, "\r\n %-35s = %d / %d / %d ",
- "Isolation/WL_Thres/BT_Thres", coex_sta->isolation_btween_wb,
- coex_sta->wifi_coex_thres, coex_sta->bt_coex_thres);
-
- /* wifi status */
- seq_printf(m, "\r\n %-35s", "============[Wifi Status]============");
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS, m);
-
- seq_printf(m, "\r\n %-35s", "============[BT Status]============");
-
- pop_report_in_10s++;
- seq_printf(
- m, "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt/ popCnt]",
- ((coex_sta->bt_disabled) ?
- ("disabled") :
- ((coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") :
- ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ?
- "non-connected idle" :
- ((coex_dm->bt_status ==
- BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE) ?
- "connected-idle" :
- "busy")))),
- coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
- coex_sta->pop_event_cnt);
-
- if (pop_report_in_10s >= 5) {
- coex_sta->pop_event_cnt = 0;
- pop_report_in_10s = 0;
- }
-
- if (coex_sta->num_of_profile != 0)
- seq_printf(
- m, "\r\n %-35s = %s%s%s%s%s", "Profiles",
- ((bt_link_info->a2dp_exist) ?
- ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," :
- "A2DP,") :
- ""),
- ((bt_link_info->sco_exist) ? "HFP," : ""),
- ((bt_link_info->hid_exist) ?
- ((coex_sta->hid_busy_num >= 2) ?
- "HID(4/18)," :
- "HID(2/18),") :
- ""),
- ((bt_link_info->pan_exist) ? "PAN," : ""),
- ((coex_sta->voice_over_HOGP) ? "Voice" : ""));
- else
- seq_printf(m, "\r\n %-35s = None", "Profiles");
-
- if (bt_link_info->a2dp_exist) {
- seq_printf(m, "\r\n %-35s = %s/ %d/ %s",
- "A2DP Rate/Bitpool/Auto_Slot",
- ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
- coex_sta->a2dp_bit_pool,
- ((coex_sta->is_autoslot) ? "On" : "Off"));
- }
-
- if (bt_link_info->hid_exist) {
- seq_printf(m, "\r\n %-35s = %d/ %d", "HID PairNum/Forbid_Slot",
- coex_sta->hid_pair_cnt, coex_sta->forbidden_slot);
- }
-
- seq_printf(m, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
- "Role/RoleSwCnt/IgnWlact/Feature",
- ((bt_link_info->slave_role) ? "Slave" : "Master"),
- coex_sta->cnt_role_switch,
- ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
- coex_sta->bt_coex_supported_feature);
-
- if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) {
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "BLEScan Type/TV/Init/Ble",
- coex_sta->bt_ble_scan_type,
- (coex_sta->bt_ble_scan_type & 0x1 ?
- coex_sta->bt_ble_scan_para[0] :
- 0x0),
- (coex_sta->bt_ble_scan_type & 0x2 ?
- coex_sta->bt_ble_scan_para[1] :
- 0x0),
- (coex_sta->bt_ble_scan_type & 0x4 ?
- coex_sta->bt_ble_scan_para[2] :
- 0x0));
- }
-
- seq_printf(m, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
- "ReInit/ReLink/IgnWlact/Page/NameReq", coex_sta->cnt_reinit,
- coex_sta->cnt_setup_link, coex_sta->cnt_ign_wlan_act,
- coex_sta->cnt_page, coex_sta->cnt_remote_name_req);
-
- halbtc8822b2ant_read_score_board(btcoexist, &u16tmp[0]);
-
- if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
- (coex_sta->bt_reg_vendor_ac == 0xffff))
- seq_printf(m, "\r\n %-35s = x/ x/ %04x",
- "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]);
- else
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ %04x",
- "0xae[4]/0xac[1:0]/Scoreboard",
- (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
- coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
-
- if (coex_sta->num_of_profile > 0) {
- seq_printf(
- m,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
- "AFH MAP", coex_sta->bt_afh_map[0],
- coex_sta->bt_afh_map[1], coex_sta->bt_afh_map[2],
- coex_sta->bt_afh_map[3], coex_sta->bt_afh_map[4],
- coex_sta->bt_afh_map[5], coex_sta->bt_afh_map[6],
- coex_sta->bt_afh_map[7], coex_sta->bt_afh_map[8],
- coex_sta->bt_afh_map[9]);
- }
-
- for (i = 0; i < BT_INFO_SRC_8822B_2ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- seq_printf(
- m,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8822b_2ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- }
- }
-
- /* Sw mechanism */
- if (btcoexist->manual_control)
- seq_printf(
- m, "\r\n %-35s",
- "============[mechanism] (before Manual)============");
- else
- seq_printf(m, "\r\n %-35s",
- "============[Mechanism]============");
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
-
- seq_printf(m, "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)",
- "TDMA", coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"),
- (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant"));
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- seq_printf(m, "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
- "Table/0x6c0/0x6c4/0x6c8", coex_sta->coex_table_type,
- u32tmp[0], u32tmp[1], u32tmp[2]);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x", "0x778/0x6cc", u8tmp[0],
- u32tmp[0]);
-
- seq_printf(m, "\r\n %-35s = %s/ %s/ %s/ %d",
- "AntDiv/BtCtrlLPS/LPRA/PsFail",
- ((board_info->ant_div_cfg) ? "On" : "Off"),
- ((coex_sta->force_lps_ctrl) ? "On" : "Off"),
- ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"),
- coex_sta->cnt_set_ps_state_fail);
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x", "WL_DACSwing/ BT_Dec_Pwr",
- coex_dm->cur_fw_dac_swing_lvl, coex_dm->cur_bt_dec_pwr_lvl);
-
- u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? true : false;
-
- if (lte_coex_on) {
- u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa0);
- u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa4);
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x",
- "LTE Coex Table W_L/B_L", u32tmp[0] & 0xffff,
- u32tmp[1] & 0xffff);
-
- u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa8);
- u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xac);
- u32tmp[2] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb0);
- u32tmp[3] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb4);
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "LTE Break Table W_L/B_L/L_W/L_B",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
- u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
- }
-
- /* Hw setting */
- seq_printf(m, "\r\n %-35s", "============[Hw setting]============");
-
- u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- seq_printf(m, "\r\n %-35s = %s/ %s", "LTE Coex/Path Owner",
- ((lte_coex_on) ? "On" : "Off"),
- ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
-
- if (lte_coex_on) {
- seq_printf(m, "\r\n %-35s = %d/ %d/ %d/ %d",
- "LTE 3Wire/OPMode/UART/UARTMode",
- (int)((u32tmp[0] & BIT(6)) >> 6),
- (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
- (int)((u32tmp[0] & BIT(3)) >> 3),
- (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
-
- seq_printf(m, "\r\n %-35s = %d/ %d", "LTE_Busy/UART_Busy",
- (int)((u32tmp[1] & BIT(1)) >> 1),
- (int)(u32tmp[1] & BIT(0)));
- }
- seq_printf(m, "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d",
- "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
- ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
- ((u32tmp[0] & BIT(8)) ? "SW" : "HW"),
- ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
- ((u32tmp[0] & BIT(10)) ? "SW" : "HW"),
- ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
- coex_sta->gnt_error_cnt);
-
- seq_printf(m, "\r\n %-35s = %d/ %d", "GNT_WL/GNT_BT",
- (int)((u32tmp[1] & BIT(2)) >> 2),
- (int)((u32tmp[1] & BIT(3)) >> 3));
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcbc);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba);
-
- seq_printf(m, "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s",
- "0xcbc/0xcb4/0xcb8[23:16]", u32tmp[0], u32tmp[1], u8tmp[0],
- ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)"));
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "4c[24:23]/64[0]/4c6[4]/40[5]",
- (int)(u32tmp[0] & (BIT(24) | BIT(23))) >> 23, u8tmp[2] & 0x1,
- (int)((u8tmp[0] & BIT(4)) >> 4),
- (int)((u8tmp[1] & BIT(5)) >> 5));
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
- u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50);
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x",
- "0x550/0x522/4-RxAGC/0xc50", u32tmp[0], u8tmp[0],
- (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]);
-
- fa_ofdm = btcoexist->btc_phydm_query_phy_counter(btcoexist,
- "PHYDM_INFO_FA_OFDM");
- fa_cck = btcoexist->btc_phydm_query_phy_counter(btcoexist,
- "PHYDM_INFO_FA_CCK");
- cca_ofdm = btcoexist->btc_phydm_query_phy_counter(
- btcoexist, "PHYDM_INFO_CCA_OFDM");
- cca_cck = btcoexist->btc_phydm_query_phy_counter(btcoexist,
- "PHYDM_INFO_CCA_CCK");
-
- ratio_ofdm = (fa_ofdm == 0) ? 1000 : (cca_ofdm / fa_ofdm);
-
- seq_printf(m, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x (%d)",
- "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", cca_cck, fa_cck, cca_ofdm,
- fa_ofdm, ratio_ofdm);
-
- seq_printf(m, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_OK CCK/11g/11n/11ac",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht);
-
- seq_printf(m, "\r\n %-35s = %d/ %d/ %d/ %d (%d, %d)",
- "CRC_Err CCK/11g/11n/11ac", coex_sta->crc_err_cck,
- coex_sta->crc_err_11g, coex_sta->crc_err_11n,
- coex_sta->crc_err_11n_vht, coex_sta->now_crc_ratio,
- coex_sta->acc_crc_ratio);
-
- seq_printf(m, "\r\n %-35s = %s/ %s/ %s/ %d",
- "WlHiPri/ Locking/ Locked/ Noisy",
- (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
- (coex_sta->cck_lock ? "Yes" : "No"),
- (coex_sta->cck_ever_lock ? "Yes" : "No"),
- coex_sta->wl_noisy_level);
-
- seq_printf(m, "\r\n %-35s = %d/ %d", "0x770(Hi-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
-
- seq_printf(m, "\r\n %-35s = %d/ %d %s", "0x774(Lo-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx,
- (bt_link_info->slave_role ?
- "(Slave!!)" :
- (coex_sta->is_tdma_btautoslot_hang ?
- "(auto-slot hang!!)" :
- "")));
-
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS, m);
-}
-
-void ex_btc8822b2ant_ips_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (type == BTC_IPS_ENTER) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], IPS ENTER notify\n");
- coex_sta->under_ips = true;
- coex_sta->under_lps = false;
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ONOFF, false);
-
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_WLAN_OFF);
-
- halbtc8822b2ant_action_coex_all_off(btcoexist);
- } else if (type == BTC_IPS_LEAVE) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], IPS LEAVE notify\n");
- coex_sta->under_ips = false;
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ONOFF, true);
- halbtc8822b2ant_init_hw_config(btcoexist, false);
- halbtc8822b2ant_init_coex_dm(btcoexist);
- halbtc8822b2ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_btc8822b2ant_lps_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- static bool pre_force_lps_on;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (type == BTC_LPS_ENABLE) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], LPS ENABLE notify\n");
- coex_sta->under_lps = true;
- coex_sta->under_ips = false;
-
- if (coex_sta->force_lps_ctrl) { /* LPS No-32K */
- /* Write WL "Active" in Score-board for PS-TDMA */
- pre_force_lps_on = true;
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE,
- true);
-
- } else {
- /* LPS-32K, need check if this h2c 0x71 can work??
- * (2015/08/28)
- */
- /* Write WL "Non-Active" in Score-board for Native-PS */
- pre_force_lps_on = false;
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE,
- false);
- }
-
- } else if (type == BTC_LPS_DISABLE) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], LPS DISABLE notify\n");
- coex_sta->under_lps = false;
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
-
- if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl))
- halbtc8822b2ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_btc8822b2ant_scan_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_connected = false;
- bool wifi_under_5g = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], SCAN notify()\n");
-
- halbtc8822b2ant_post_state_to_bt(btcoexist,
- BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- /* this can't be removed for RF off_on event, or BT would dis-connect */
- halbtc8822b2ant_query_bt_info(btcoexist);
-
- if (type == BTC_SCAN_START) {
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
- &wifi_under_5g);
-
- if (wifi_under_5g) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** SCAN START notify (5g)\n");
-
- halbtc8822b2ant_action_wifi_under5g(btcoexist);
- return;
- }
-
- coex_sta->wifi_is_high_pri_task = true;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** SCAN START notify (2g)\n");
-
- halbtc8822b2ant_run_coexist_mechanism(btcoexist);
-
- return;
- }
-
- if (type == BTC_SCAN_START_2G) {
- if (!wifi_connected)
- coex_sta->wifi_is_high_pri_task = true;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], SCAN START notify (2G)\n");
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_SCAN, true);
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
-
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b2ant_run_coexist_mechanism(btcoexist);
-
- } else if (type == BTC_SCAN_FINISH) {
- coex_sta->wifi_is_high_pri_task = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n",
- coex_sta->scan_ap_num);
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_SCAN, false);
-
- halbtc8822b2ant_run_coexist_mechanism(btcoexist);
- }
-}
-
-void ex_btc8822b2ant_switchband_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
- coex_sta->switch_band_notify_to = type;
-
- if (type == BTC_SWITCH_TO_5G) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], switchband_notify --- switch to 5G\n");
-
- halbtc8822b2ant_action_wifi_under5g(btcoexist);
-
- } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n");
-
- halbtc8822b2ant_run_coexist_mechanism(btcoexist);
-
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], switchband_notify --- switch to 2G\n");
-
- ex_btc8822b2ant_scan_notify(btcoexist, BTC_SCAN_START_2G);
- }
- coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
-}
-
-void ex_btc8822b2ant_connect_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- halbtc8822b2ant_post_state_to_bt(btcoexist,
- BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if ((type == BTC_ASSOCIATE_5G_START) ||
- (type == BTC_ASSOCIATE_5G_FINISH)) {
- if (type == BTC_ASSOCIATE_5G_START)
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], connect_notify --- 5G start\n");
- else
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], connect_notify --- 5G finish\n");
-
- halbtc8822b2ant_action_wifi_under5g(btcoexist);
- return;
- }
-
- if (type == BTC_ASSOCIATE_START) {
- coex_sta->wifi_is_high_pri_task = true;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], CONNECT START notify (2G)\n");
-
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b2ant_action_wifi_link_process(btcoexist);
-
- /* To keep TDMA case during connect process,
- * to avoid changed by Btinfo and runcoexmechanism
- */
- coex_sta->freeze_coexrun_by_btinfo = true;
-
- coex_dm->arp_cnt = 0;
-
- } else if (type == BTC_ASSOCIATE_FINISH) {
- coex_sta->wifi_is_high_pri_task = false;
- coex_sta->freeze_coexrun_by_btinfo = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], CONNECT FINISH notify (2G)\n");
-
- halbtc8822b2ant_run_coexist_mechanism(btcoexist);
- }
-}
-
-void ex_btc8822b2ant_media_status_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_under_b_mode = false, wifi_under_5g = false;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if (type == BTC_MEDIA_CONNECT) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], MEDIA connect notify\n");
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
-
- if (wifi_under_5g) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], WiFi is under 5G!!!\n");
-
- halbtc8822b2ant_action_wifi_under5g(btcoexist);
- return;
- }
-
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_2G_RUNTIME);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- /* Set CCK Tx/Rx high Pri except 11b mode */
- if (wifi_under_b_mode) {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x00); /* CCK Rx */
- } else {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x10); /* CCK Rx */
- }
-
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], MEDIA disconnect notify\n");
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
- }
-
- halbtc8822b2ant_update_wifi_ch_info(btcoexist, type);
-}
-
-void ex_btc8822b2ant_specific_packet_notify(struct btc_coexist *btcoexist,
- u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool under_4way = false, wifi_under_5g = false;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if (wifi_under_5g) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], WiFi is under 5G!!!\n");
-
- halbtc8822b2ant_action_wifi_under5g(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (under_4way) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], specific Packet ---- under_4way!!\n");
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
-
- } else if (type == BTC_PACKET_ARP) {
- coex_dm->arp_cnt++;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], specific Packet ARP notify -cnt = %d\n",
- coex_dm->arp_cnt);
-
- } else {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
- type);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- }
-
- if (coex_sta->wifi_is_high_pri_task)
- halbtc8822b2ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_btc8822b2ant_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
- u8 length)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 i, rsp_source = 0;
- bool wifi_connected = false;
- bool wifi_scan = false, wifi_link = false, wifi_roam = false,
- wifi_busy = false;
- static bool is_scoreboard_scan;
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8822B_2ANT_MAX)
- rsp_source = BT_INFO_SRC_8822B_2ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, length);
-
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
-
- if (i == length - 1) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "0x%02x]\n", tmp_buf[i]);
- } else {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "0x%02x, ",
- tmp_buf[i]);
- }
- }
-
- coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
- coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
- coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
-
- if (rsp_source != BT_INFO_SRC_8822B_2ANT_WIFI_FW) {
- /* if 0xff, it means BT is under WHCK test */
- coex_sta->bt_whck_test =
- ((coex_sta->bt_info == 0xff) ? true : false);
-
- coex_sta->bt_create_connection =
- ((coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? true :
- false);
-
- /* unit: %, value-100 to translate to unit: dBm */
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- coex_sta->c2h_bt_remote_name_req =
- ((coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? true :
- false);
-
- coex_sta->is_A2DP_3M =
- ((coex_sta->bt_info_c2h[rsp_source][2] & 0x10) ? true :
- false);
-
- coex_sta->acl_busy =
- ((coex_sta->bt_info_c2h[rsp_source][1] & 0x9) ? true :
- false);
-
- coex_sta->voice_over_HOGP =
- ((coex_sta->bt_info_ext & 0x10) ? true : false);
-
- coex_sta->c2h_bt_inquiry_page =
- ((coex_sta->bt_info & BT_INFO_8822B_2ANT_B_INQ_PAGE) ?
- true :
- false);
-
- coex_sta->a2dp_bit_pool =
- (((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) ==
- 0x49) ?
- (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) :
- 0);
-
- coex_sta->is_bt_a2dp_sink =
- (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? true :
- false;
-
- coex_sta->bt_retry_cnt =
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
-
- coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
-
- coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
-
- coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
-
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- if (coex_sta->c2h_bt_remote_name_req)
- coex_sta->cnt_remote_name_req++;
-
- if (coex_sta->bt_info_ext & BIT(1))
- coex_sta->cnt_reinit++;
-
- if (coex_sta->bt_info_ext & BIT(2)) {
- coex_sta->cnt_setup_link++;
- coex_sta->is_setup_link = true;
- coex_sta->bt_relink_downcount = 2;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Re-Link start in BT info!!\n");
- } else {
- coex_sta->is_setup_link = false;
- coex_sta->bt_relink_downcount = 0;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Re-Link stop in BT info!!\n");
- }
-
- if (coex_sta->bt_info_ext & BIT(3))
- coex_sta->cnt_ign_wlan_act++;
-
- if (coex_sta->bt_info_ext & BIT(6))
- coex_sta->cnt_role_switch++;
-
- if (coex_sta->bt_info_ext & BIT(7))
- coex_sta->is_bt_multi_link = true;
- else
- coex_sta->is_bt_multi_link = false;
-
- if (coex_sta->bt_create_connection) {
- coex_sta->cnt_page++;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY,
- &wifi_busy);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN,
- &wifi_scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK,
- &wifi_link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM,
- &wifi_roam);
-
- if ((wifi_link) || (wifi_roam) || (wifi_scan) ||
- (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) {
- is_scoreboard_scan = true;
- halbtc8822b2ant_post_state_to_bt(
- btcoexist,
- BT_8822B_2ANT_SCOREBOARD_SCAN, true);
-
- } else {
- halbtc8822b2ant_post_state_to_bt(
- btcoexist,
- BT_8822B_2ANT_SCOREBOARD_SCAN, false);
- }
- } else {
- if (is_scoreboard_scan) {
- halbtc8822b2ant_post_state_to_bt(
- btcoexist,
- BT_8822B_2ANT_SCOREBOARD_SCAN, false);
- is_scoreboard_scan = false;
- }
- }
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
-
- if ((!btcoexist->manual_control) &&
- (!btcoexist->stop_coex_dm)) {
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- /* Re-Init */
- if ((coex_sta->bt_info_ext & BIT(1))) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- if (wifi_connected)
- halbtc8822b2ant_update_wifi_ch_info(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- halbtc8822b2ant_update_wifi_ch_info(
- btcoexist,
- BTC_MEDIA_DISCONNECT);
- }
-
- /* If Ignore_WLanAct && not SetUp_Link */
- if ((coex_sta->bt_info_ext & BIT(3)) &&
- (!(coex_sta->bt_info_ext & BIT(2))) &&
- (!(coex_sta->bt_info_ext & BIT(6)))) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- halbtc8822b2ant_ignore_wlan_act(
- btcoexist, FORCE_EXEC, false);
- } else {
- if (coex_sta->bt_info_ext & BIT(2)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT ignore Wlan active because Re-link!!\n");
- } else if (coex_sta->bt_info_ext & BIT(6)) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST,
- DBG_LOUD,
- "[BTCoex], BT ignore Wlan active because Role-Switch!!\n");
- }
- }
- }
- }
-
- if ((coex_sta->bt_info_ext & BIT(5))) {
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
- coex_sta->bt_ble_scan_type =
- btcoexist->btc_get_ble_scan_type_from_bt(btcoexist);
-
- if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
- coex_sta->bt_ble_scan_para[0] =
- btcoexist->btc_get_ble_scan_para_from_bt(
- btcoexist, 0x1);
- if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
- coex_sta->bt_ble_scan_para[1] =
- btcoexist->btc_get_ble_scan_para_from_bt(
- btcoexist, 0x2);
- if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
- coex_sta->bt_ble_scan_para[2] =
- btcoexist->btc_get_ble_scan_para_from_bt(
- btcoexist, 0x4);
- }
-
- halbtc8822b2ant_update_bt_link_info(btcoexist);
-
- halbtc8822b2ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_btc8822b2ant_rf_status_notify(struct btc_coexist *btcoexist, u8 type)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RF Status notify\n");
-
- if (type == BTC_RF_ON) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RF is turned ON!!\n");
-
- btcoexist->stop_coex_dm = false;
- coex_sta->is_rf_state_off = false;
- } else if (type == BTC_RF_OFF) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], RF is turned OFF!!\n");
-
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_WLAN_OFF);
-
- halbtc8822b2ant_action_coex_all_off(btcoexist);
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE |
- BT_8822B_2ANT_SCOREBOARD_ONOFF |
- BT_8822B_2ANT_SCOREBOARD_SCAN |
- BT_8822B_2ANT_SCOREBOARD_UNDERTEST,
- false);
-
- btcoexist->stop_coex_dm = true;
- coex_sta->is_rf_state_off = true;
- }
-}
-
-void ex_btc8822b2ant_halt_notify(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "[BTCoex], Halt notify\n");
-
- halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_2ANT_PHASE_WLAN_OFF);
-
- ex_btc8822b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
- halbtc8822b2ant_post_state_to_bt(btcoexist,
- BT_8822B_2ANT_SCOREBOARD_ONOFF, false);
-}
-
-void ex_btc8822b2ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_under_5g = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "[BTCoex], Pnp notify\n");
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if ((pnp_state == BTC_WIFI_PNP_SLEEP) ||
- (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT)) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Pnp notify to SLEEP\n");
-
- /* Sinda 20150819, workaround for driver skip leave IPS/LPS to
- * speed up sleep time.
- * Driver do not leave IPS/LPS when driver is going to sleep,
- * so BTCoexistence think wifi is still under IPS/LPS.
- * BT should clear UnderIPS/UnderLPS state to avoid mismatch
- * state after wakeup.
- */
- coex_sta->under_ips = false;
- coex_sta->under_lps = false;
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, false);
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ONOFF, false);
-
- if (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) {
- if (wifi_under_5g)
- halbtc8822b2ant_set_ant_path(
- btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_5G_RUNTIME);
- else
- halbtc8822b2ant_set_ant_path(
- btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_2ANT_PHASE_2G_RUNTIME);
- } else {
- halbtc8822b2ant_set_ant_path(
- btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_2ANT_PHASE_WLAN_OFF);
- }
- } else if (pnp_state == BTC_WIFI_PNP_WAKE_UP) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Pnp notify to WAKE UP\n");
-
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ACTIVE, true);
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_ONOFF, true);
- }
-}
-
-void ex_btc8822b2ant_periodical(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- bool wifi_busy = false;
- u16 bt_scoreboard_val = 0;
- bool bt_relink_finish = false;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ************* Periodical *************\n");
-
- if (!btcoexist->auto_report_2ant)
- halbtc8822b2ant_query_bt_info(btcoexist);
-
- halbtc8822b2ant_monitor_bt_ctr(btcoexist);
- halbtc8822b2ant_monitor_wifi_ctr(btcoexist);
- halbtc8822b2ant_monitor_bt_enable_disable(btcoexist);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- halbtc8822b2ant_read_score_board(btcoexist, &bt_scoreboard_val);
-
- if (wifi_busy) {
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_UNDERTEST, true);
- /*for bt lps32 clock offset*/
- if (bt_scoreboard_val & BIT(6))
- halbtc8822b2ant_query_bt_info(btcoexist);
- } else {
- halbtc8822b2ant_post_state_to_bt(
- btcoexist, BT_8822B_2ANT_SCOREBOARD_UNDERTEST, false);
- }
-
- if (coex_sta->bt_relink_downcount != 0) {
- coex_sta->bt_relink_downcount--;
-
- if (coex_sta->bt_relink_downcount == 0) {
- coex_sta->is_setup_link = false;
- bt_relink_finish = true;
- }
- }
-
- /* for 4-way, DHCP, EAPOL packet */
- if (coex_sta->specific_pkt_period_cnt > 0) {
- coex_sta->specific_pkt_period_cnt--;
-
- if ((coex_sta->specific_pkt_period_cnt == 0) &&
- (coex_sta->wifi_is_high_pri_task))
- coex_sta->wifi_is_high_pri_task = false;
-
- RT_TRACE(
- rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
- (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"));
- }
-
- if (halbtc8822b2ant_is_wifibt_status_changed(btcoexist) ||
- (bt_relink_finish) || (coex_sta->is_set_ps_state_fail))
- halbtc8822b2ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_btc8822b2ant_antenna_detection(struct btc_coexist *btcoexist,
- u32 cent_freq, u32 offset, u32 span,
- u32 seconds)
-{
-}
-
-void ex_btc8822b2ant_display_ant_detection(struct btc_coexist *btcoexist) {}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* *******************************************
- * The following is for 8822B 2Ant BT Co-exist definition
- * ********************************************/
-#define BT_INFO_8822B_2ANT_B_FTP BIT(7)
-#define BT_INFO_8822B_2ANT_B_A2DP BIT(6)
-#define BT_INFO_8822B_2ANT_B_HID BIT(5)
-#define BT_INFO_8822B_2ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8822B_2ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8822B_2ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8822B_2ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8822B_2ANT_B_CONNECTION BIT(0)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT 2
-
-/* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation.
- * (default = 42)
- */
-#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 80
-/* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation.
- * (default = 46)
- */
-#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 80
-/* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation.
- * (default = 42)
- */
-#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 80
-/* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation.
- * (default = 46)
- */
-#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2 80
-#define BT_8822B_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */
-#define BT_8822B_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */
-#define BT_8822B_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */
-#define BT_8822B_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */
-#define BT_8822B_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */
-#define BT_8822B_2ANT_BT_SIR_THRES1 -15 /* unit: dB */
-#define BT_8822B_2ANT_BT_SIR_THRES2 -30 /* unit: dB */
-
-/* for Antenna detection */
-#define BT_8822B_2ANT_ANTDET_PSDTHRES_BACKGROUND 50
-#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
-#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52
-#define BT_8822B_2ANT_ANTDET_PSDTHRES_1ANT 40
-#define BT_8822B_2ANT_ANTDET_RETRY_INTERVAL \
- 10 /* retry timer if ant det is fail, unit: second */
-#define BT_8822B_2ANT_ANTDET_SWEEPPOINT_DELAY 60000
-#define BT_8822B_2ANT_ANTDET_ENABLE 0
-#define BT_8822B_2ANT_ANTDET_BTTXTIME 100
-#define BT_8822B_2ANT_ANTDET_BTTXCHANNEL 39
-#define BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT 50
-
-#define BT_8822B_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
-
-enum bt_8822b_2ant_signal_state {
- BT_8822B_2ANT_SIG_STA_SET_TO_LOW = 0x0,
- BT_8822B_2ANT_SIG_STA_SET_BY_HW = 0x0,
- BT_8822B_2ANT_SIG_STA_SET_TO_HIGH = 0x1,
- BT_8822B_2ANT_SIG_STA_MAX
-};
-
-enum bt_8822b_2ant_path_ctrl_owner {
- BT_8822B_2ANT_PCO_BTSIDE = 0x0,
- BT_8822B_2ANT_PCO_WLSIDE = 0x1,
- BT_8822B_2ANT_PCO_MAX
-};
-
-enum bt_8822b_2ant_gnt_ctrl_type {
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0,
- BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1,
- BT_8822B_2ANT_GNT_TYPE_MAX
-};
-
-enum bt_8822b_2ant_gnt_ctrl_block {
- BT_8822B_2ANT_GNT_BLOCK_RFC_BB = 0x0,
- BT_8822B_2ANT_GNT_BLOCK_RFC = 0x1,
- BT_8822B_2ANT_GNT_BLOCK_BB = 0x2,
- BT_8822B_2ANT_GNT_BLOCK_MAX
-};
-
-enum bt_8822b_2ant_lte_coex_table_type {
- BT_8822B_2ANT_CTT_WL_VS_LTE = 0x0,
- BT_8822B_2ANT_CTT_BT_VS_LTE = 0x1,
- BT_8822B_2ANT_CTT_MAX
-};
-
-enum bt_8822b_2ant_lte_break_table_type {
- BT_8822B_2ANT_LBTT_WL_BREAK_LTE = 0x0,
- BT_8822B_2ANT_LBTT_BT_BREAK_LTE = 0x1,
- BT_8822B_2ANT_LBTT_LTE_BREAK_WL = 0x2,
- BT_8822B_2ANT_LBTT_LTE_BREAK_BT = 0x3,
- BT_8822B_2ANT_LBTT_MAX
-};
-
-enum bt_info_src_8822b_2ant {
- BT_INFO_SRC_8822B_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8822B_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8822B_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8822B_2ANT_MAX
-};
-
-enum bt_8822b_2ant_bt_status {
- BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8822B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8822B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8822B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8822B_2ANT_BT_STATUS_MAX
-};
-
-enum bt_8822b_2ant_coex_algo {
- BT_8822B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8822B_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8822B_2ANT_COEX_ALGO_HID = 0x2,
- BT_8822B_2ANT_COEX_ALGO_A2DP = 0x3,
- BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8822B_2ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8822B_2ANT_COEX_ALGO_PANHS = 0x6,
- BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8822B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8822B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb,
- BT_8822B_2ANT_COEX_ALGO_A2DPSINK = 0xc,
- BT_8822B_2ANT_COEX_ALGO_MAX
-};
-
-enum bt_8822b_2ant_ext_ant_switch_type {
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0,
- BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1,
- BT_8822B_2ANT_EXT_ANT_SWITCH_NONE = 0x2,
- BT_8822B_2ANT_EXT_ANT_SWITCH_MAX
-};
-
-enum bt_8822b_2ant_ext_ant_switch_ctrl_type {
- BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0,
- BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1,
- BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2,
- BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3,
- BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4,
- BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_MAX
-};
-
-enum bt_8822b_2ant_ext_ant_switch_pos_type {
- BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT = 0x0,
- BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG = 0x1,
- BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA = 0x2,
- BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE = 0x3,
- BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX
-};
-
-enum bt_8822b_2ant_ext_band_switch_pos_type {
- BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLG = 0x0,
- BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLA = 0x1,
- BT_8822B_2ANT_EXT_BAND_SWITCH_TO_MAX
-};
-
-enum bt_8822b_2ant_int_block {
- BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0,
- BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1,
- BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2,
- BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_MAX
-};
-
-enum bt_8822b_2ant_phase {
- BT_8822B_2ANT_PHASE_COEX_INIT = 0x0,
- BT_8822B_2ANT_PHASE_WLANONLY_INIT = 0x1,
- BT_8822B_2ANT_PHASE_WLAN_OFF = 0x2,
- BT_8822B_2ANT_PHASE_2G_RUNTIME = 0x3,
- BT_8822B_2ANT_PHASE_5G_RUNTIME = 0x4,
- BT_8822B_2ANT_PHASE_BTMPMODE = 0x5,
- BT_8822B_2ANT_PHASE_ANTENNA_DET = 0x6,
- BT_8822B_2ANT_PHASE_COEX_POWERON = 0x7,
- BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8,
- BT_8822B_2ANT_PHASE_MAX
-};
-
-/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
-
-enum bt_8822b_2ant_scoreboard {
- BT_8822B_2ANT_SCOREBOARD_ACTIVE = BIT(0),
- BT_8822B_2ANT_SCOREBOARD_ONOFF = BIT(1),
- BT_8822B_2ANT_SCOREBOARD_SCAN = BIT(2),
- BT_8822B_2ANT_SCOREBOARD_UNDERTEST = BIT(3),
- BT_8822B_2ANT_SCOREBOARD_WLBUSY = BIT(6)
-};
-
-struct coex_dm_8822b_2ant {
- /* hw setting */
- u32 pre_ant_pos_type;
- u32 cur_ant_pos_type;
- /* fw mechanism */
- u8 pre_bt_dec_pwr_lvl;
- u8 cur_bt_dec_pwr_lvl;
- u8 pre_fw_dac_swing_lvl;
- u8 cur_fw_dac_swing_lvl;
- bool cur_ignore_wlan_act;
- bool pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- bool reset_tdma_adjust;
- bool pre_ps_tdma_on;
- bool cur_ps_tdma_on;
- bool pre_bt_auto_report;
- bool cur_bt_auto_report;
-
- /* sw mechanism */
- bool pre_rf_rx_lpf_shrink;
- bool cur_rf_rx_lpf_shrink;
- u32 bt_rf_0x1e_backup;
- bool pre_low_penalty_ra;
- bool cur_low_penalty_ra;
- bool pre_dac_swing_on;
- u32 pre_dac_swing_lvl;
- bool cur_dac_swing_on;
- u32 cur_dac_swing_lvl;
- bool pre_adc_back_off;
- bool cur_adc_back_off;
- bool pre_agc_table_en;
- bool cur_agc_table_en;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- bool limited_dig;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- bool need_recover0x948;
- u32 backup0x948;
-
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- bool is_switch_to_1dot5_ant;
- u8 switch_thres_offset;
- u32 arp_cnt;
-
- u32 pre_ext_ant_switch_status;
- u32 cur_ext_ant_switch_status;
-
- u8 pre_ext_band_switch_status;
- u8 cur_ext_band_switch_status;
-
- u8 pre_int_block_status;
- u8 cur_int_block_status;
-};
-
-struct coex_sta_8822b_2ant {
- bool bt_disabled;
- bool bt_link_exist;
- bool sco_exist;
- bool a2dp_exist;
- bool hid_exist;
- bool pan_exist;
-
- bool under_lps;
- bool under_ips;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- bool is_hi_pri_rx_overhead;
- u8 bt_rssi;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- u8 bt_info_c2h[BT_INFO_SRC_8822B_2ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_2ANT_MAX];
- bool bt_whck_test;
- bool c2h_bt_inquiry_page;
- bool c2h_bt_remote_name_req;
-
- u8 bt_info_ext;
- u8 bt_info_ext2;
- u32 pop_event_cnt;
- u8 scan_ap_num;
- u8 bt_retry_cnt;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_vht;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_vht;
-
- u32 acc_crc_ratio;
- u32 now_crc_ratio;
-
- bool cck_lock;
- bool pre_ccklock;
- bool cck_ever_lock;
-
- u8 coex_table_type;
- bool force_lps_ctrl;
-
- u8 dis_ver_info_cnt;
-
- u8 a2dp_bit_pool;
- u8 cut_version;
-
- bool concurrent_rx_mode_on;
-
- u16 score_board;
- u8 isolation_btween_wb; /* 0~ 50 */
- u8 wifi_coex_thres;
- u8 bt_coex_thres;
- u8 wifi_coex_thres2;
- u8 bt_coex_thres2;
-
- u8 num_of_profile;
- bool acl_busy;
- bool bt_create_connection;
- bool wifi_is_high_pri_task;
- u32 specific_pkt_period_cnt;
- u32 bt_coex_supported_feature;
- u32 bt_coex_supported_version;
-
- u8 bt_ble_scan_type;
- u32 bt_ble_scan_para[3];
-
- bool run_time_state;
- bool freeze_coexrun_by_btinfo;
-
- bool is_A2DP_3M;
- bool voice_over_HOGP;
- u8 bt_info;
- bool is_autoslot;
- u8 forbidden_slot;
- u8 hid_busy_num;
- u8 hid_pair_cnt;
-
- u32 cnt_remote_name_req;
- u32 cnt_setup_link;
- u32 cnt_reinit;
- u32 cnt_ign_wlan_act;
- u32 cnt_page;
- u32 cnt_role_switch;
-
- u16 bt_reg_vendor_ac;
- u16 bt_reg_vendor_ae;
-
- bool is_setup_link;
- u8 wl_noisy_level;
- u32 gnt_error_cnt;
-
- u8 bt_afh_map[10];
- u8 bt_relink_downcount;
- bool is_tdma_btautoslot;
- bool is_tdma_btautoslot_hang;
-
- bool is_esco_mode;
- u8 switch_band_notify_to;
- bool is_rf_state_off;
-
- bool is_hid_low_pri_tx_overhead;
- bool is_bt_multi_link;
- bool is_bt_a2dp_sink;
-
- bool is_set_ps_state_fail;
- u8 cnt_set_ps_state_fail;
-};
-
-#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_DPDT 0
-#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT 1
-
-struct rfe_type_8822b_2ant {
- u8 rfe_module_type;
- bool ext_ant_switch_exist;
- u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */
- /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */
- u8 ext_ant_switch_ctrl_polarity;
-
- bool ext_band_switch_exist;
- u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */
- u8 ext_band_switch_ctrl_polarity;
-
- /* If true: WLG at BTG, If false: WLG at WLAG */
- bool wlg_locate_at_btg;
-
- bool ext_ant_switch_diversity; /* If diversity on */
-};
-
-#define BT_8822B_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
-#define BT_8822B_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
-#define BT_8822B_2ANT_ANTDET_BUF_LEN 16
-
-struct psdscan_sta_8822b_2ant {
- u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
- u32 ant_det_bt_tx_time;
- u32 ant_det_pre_psdscan_peak_val;
- bool ant_det_is_ant_det_available;
- u32 ant_det_psd_scan_peak_val;
- bool ant_det_is_btreply_available;
- u32 ant_det_psd_scan_peak_freq;
-
- u8 ant_det_result;
- u8 ant_det_peak_val[BT_8822B_2ANT_ANTDET_BUF_LEN];
- u8 ant_det_peak_freq[BT_8822B_2ANT_ANTDET_BUF_LEN];
- u32 ant_det_try_count;
- u32 ant_det_fail_count;
- u32 ant_det_inteval_count;
- u32 ant_det_thres_offset;
-
- u32 real_cent_freq;
- s32 real_offset;
- u32 real_span;
-
- u32 psd_band_width; /* unit: Hz */
- u32 psd_point; /* 128/256/512/1024 */
- u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_start_point;
- u32 psd_stop_point;
- u32 psd_max_value_point;
- u32 psd_max_value;
- u32 psd_max_value2;
- /* filter loop_max_value that below BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT,
- * and average the rest
- */
- u32 psd_avg_value;
- /*max value in each loop */
- u32 psd_loop_max_value[BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT];
- u32 psd_start_base;
- u32 psd_avg_num; /* 1/8/16/32 */
- u32 psd_gen_count;
- bool is_ant_det_running;
- bool is_psd_show_max_only;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ********************************************/
-void ex_btc8822b2ant_power_on_setting(struct btc_coexist *btcoexist);
-void ex_btc8822b2ant_pre_load_firmware(struct btc_coexist *btcoexist);
-void ex_btc8822b2ant_init_hw_config(struct btc_coexist *btcoexist,
- bool wifi_only);
-void ex_btc8822b2ant_init_coex_dm(struct btc_coexist *btcoexist);
-void ex_btc8822b2ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b2ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b2ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b2ant_switchband_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b2ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b2ant_media_status_notify(struct btc_coexist *btcoexist,
- u8 type);
-void ex_btc8822b2ant_specific_packet_notify(struct btc_coexist *btcoexist,
- u8 type);
-void ex_btc8822b2ant_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
- u8 length);
-void ex_btc8822b2ant_rf_status_notify(struct btc_coexist *btcoexist, u8 type);
-void ex_btc8822b2ant_halt_notify(struct btc_coexist *btcoexist);
-void ex_btc8822b2ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state);
-void ex_btc8822b2ant_periodical(struct btc_coexist *btcoexist);
-void ex_btc8822b2ant_display_coex_info(struct btc_coexist *btcoexist,
- struct seq_file *m);
-void ex_btc8822b2ant_antenna_detection(struct btc_coexist *btcoexist,
- u32 cent_freq, u32 offset, u32 span,
- u32 seconds);
-void ex_btc8822b2ant_display_ant_detection(struct btc_coexist *btcoexist);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halbt_precomp.h"
-
-void ex_hal8822b_wifi_only_hw_config(struct wifi_only_cfg *wifionlycfg)
-{
- /*BB control*/
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x4c, 0x01800000, 0x2);
- /*SW control*/
- halwifionly_phy_set_bb_reg(wifionlycfg, 0xcb4, 0xff, 0x77);
- /*antenna mux switch */
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x974, 0x300, 0x3);
-
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x1990, 0x300, 0x0);
-
- halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x80000, 0x0);
- /*switch to WL side controller and gnt_wl gnt_bt debug signal */
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x70, 0xff000000, 0x0e);
- /*gnt_wl=1 , gnt_bt=0*/
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x1704, 0xffffffff, 0x7700);
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x1700, 0xffffffff, 0xc00f0038);
-}
-
-void ex_hal8822b_wifi_only_scannotify(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g)
-{
- hal8822b_wifi_only_switch_antenna(wifionlycfg, is_5g);
-}
-
-void ex_hal8822b_wifi_only_switchbandnotify(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g)
-{
- hal8822b_wifi_only_switch_antenna(wifionlycfg, is_5g);
-}
-
-void hal8822b_wifi_only_switch_antenna(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g)
-{
- if (is_5g)
- halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x1);
- else
- halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x2);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __INC_HAL8822BWIFIONLYHWCFG_H
-#define __INC_HAL8822BWIFIONLYHWCFG_H
-
-void ex_hal8822b_wifi_only_hw_config(struct wifi_only_cfg *wifionlycfg);
-void ex_hal8822b_wifi_only_scannotify(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g);
-void ex_hal8822b_wifi_only_switchbandnotify(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g);
-void hal8822b_wifi_only_switch_antenna(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- ******************************************************************************/
-
-#include "halbt_precomp.h"
-
-/***************************************************
- * Debug related function
- ***************************************************/
-
-static const char *const gl_btc_wifi_bw_string[] = {
- "11bg",
- "HT20",
- "HT40",
- "HT80",
- "HT160"
-};
-
-static const char *const gl_btc_wifi_freq_string[] = {
- "2.4G",
- "5G"
-};
-
-static bool halbtc_is_bt_coexist_available(struct btc_coexist *btcoexist)
-{
- if (!btcoexist->binded || !btcoexist->adapter)
- return false;
-
- return true;
-}
-
-static bool halbtc_is_wifi_busy(struct rtl_priv *rtlpriv)
-{
- if (rtlpriv->link_info.busytraffic)
- return true;
- else
- return false;
-}
-
-static void halbtc_dbg_init(void)
-{
-}
-
-/***************************************************
- * helper function
- ***************************************************/
-static bool is_any_client_connect_to_ap(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- struct rtl_sta_info *drv_priv;
- u8 cnt = 0;
-
- if (mac->opmode == NL80211_IFTYPE_ADHOC ||
- mac->opmode == NL80211_IFTYPE_MESH_POINT ||
- mac->opmode == NL80211_IFTYPE_AP) {
- if (in_interrupt() > 0) {
- list_for_each_entry(drv_priv, &rtlpriv->entry_list,
- list) {
- cnt++;
- }
- } else {
- spin_lock_bh(&rtlpriv->locks.entry_list_lock);
- list_for_each_entry(drv_priv, &rtlpriv->entry_list,
- list) {
- cnt++;
- }
- spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
- }
- }
- if (cnt > 0)
- return true;
- else
- return false;
-}
-
-static bool halbtc_legacy(struct rtl_priv *adapter)
-{
- struct rtl_priv *rtlpriv = adapter;
- struct rtl_mac *mac = rtl_mac(rtlpriv);
-
- bool is_legacy = false;
-
- if ((mac->mode == WIRELESS_MODE_B) || (mac->mode == WIRELESS_MODE_G))
- is_legacy = true;
-
- return is_legacy;
-}
-
-bool halbtc_is_wifi_uplink(struct rtl_priv *adapter)
-{
- struct rtl_priv *rtlpriv = adapter;
-
- if (rtlpriv->link_info.tx_busy_traffic)
- return true;
- else
- return false;
-}
-
-static u32 halbtc_get_wifi_bw(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv =
- (struct rtl_priv *)btcoexist->adapter;
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u32 wifi_bw = BTC_WIFI_BW_HT20;
-
- if (halbtc_legacy(rtlpriv)) {
- wifi_bw = BTC_WIFI_BW_LEGACY;
- } else {
- switch (rtlphy->current_chan_bw) {
- case HT_CHANNEL_WIDTH_20:
- wifi_bw = BTC_WIFI_BW_HT20;
- break;
- case HT_CHANNEL_WIDTH_20_40:
- wifi_bw = BTC_WIFI_BW_HT40;
- break;
- case HT_CHANNEL_WIDTH_80:
- wifi_bw = BTC_WIFI_BW_HT80;
- break;
- }
- }
-
- return wifi_bw;
-}
-
-static u8 halbtc_get_wifi_central_chnl(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 chnl = 1;
-
- if (rtlphy->current_channel != 0)
- chnl = rtlphy->current_channel;
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "%s:%d\n", __func__, chnl);
- return chnl;
-}
-
-static u8 rtl_get_hwpg_single_ant_path(struct rtl_priv *rtlpriv)
-{
- return rtlpriv->btcoexist.btc_info.single_ant_path;
-}
-
-static u8 rtl_get_hwpg_bt_type(struct rtl_priv *rtlpriv)
-{
- return rtlpriv->btcoexist.btc_info.bt_type;
-}
-
-static u8 rtl_get_hwpg_ant_num(struct rtl_priv *rtlpriv)
-{
- u8 num;
-
- if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2)
- num = 2;
- else
- num = 1;
-
- return num;
-}
-
-static u8 rtl_get_hwpg_package_type(struct rtl_priv *rtlpriv)
-{
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
-
- return rtlhal->package_type;
-}
-
-static
-u8 rtl_get_hwpg_rfe_type(struct rtl_priv *rtlpriv)
-{
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
-
- return rtlhal->rfe_type;
-}
-
-/* ************************************
- * Hal helper function
- * ************************************
- */
-static
-bool halbtc_is_hw_mailbox_exist(struct btc_coexist *btcoexist)
-{
- if (IS_HARDWARE_TYPE_8812(btcoexist->adapter))
- return false;
- else
- return true;
-}
-
-static
-bool halbtc_send_bt_mp_operation(struct btc_coexist *btcoexist, u8 op_code,
- u8 *cmd, u32 len, unsigned long wait_ms)
-{
- struct rtl_priv *rtlpriv;
- const u8 oper_ver = 0;
- u8 req_num;
-
- if (!halbtc_is_hw_mailbox_exist(btcoexist))
- return false;
-
- if (wait_ms) /* before h2c to avoid race condition */
- reinit_completion(&btcoexist->bt_mp_comp);
-
- rtlpriv = btcoexist->adapter;
-
- /*
- * fill req_num by op_code, and rtl_btc_btmpinfo_notify() use it
- * to know message type
- */
- switch (op_code) {
- case BT_OP_GET_BT_VERSION:
- req_num = BT_SEQ_GET_BT_VERSION;
- break;
- case BT_OP_GET_AFH_MAP_L:
- req_num = BT_SEQ_GET_AFH_MAP_L;
- break;
- case BT_OP_GET_AFH_MAP_M:
- req_num = BT_SEQ_GET_AFH_MAP_M;
- break;
- case BT_OP_GET_AFH_MAP_H:
- req_num = BT_SEQ_GET_AFH_MAP_H;
- break;
- case BT_OP_GET_BT_COEX_SUPPORTED_FEATURE:
- req_num = BT_SEQ_GET_BT_COEX_SUPPORTED_FEATURE;
- break;
- case BT_OP_GET_BT_COEX_SUPPORTED_VERSION:
- req_num = BT_SEQ_GET_BT_COEX_SUPPORTED_VERSION;
- break;
- case BT_OP_GET_BT_ANT_DET_VAL:
- req_num = BT_SEQ_GET_BT_ANT_DET_VAL;
- break;
- case BT_OP_GET_BT_BLE_SCAN_PARA:
- req_num = BT_SEQ_GET_BT_BLE_SCAN_PARA;
- break;
- case BT_OP_GET_BT_BLE_SCAN_TYPE:
- req_num = BT_SEQ_GET_BT_BLE_SCAN_TYPE;
- break;
- case BT_OP_WRITE_REG_ADDR:
- case BT_OP_WRITE_REG_VALUE:
- case BT_OP_READ_REG:
- default:
- req_num = BT_SEQ_DONT_CARE;
- break;
- }
-
- cmd[0] |= (oper_ver & 0x0f); /* Set OperVer */
- cmd[0] |= ((req_num << 4) & 0xf0); /* Set ReqNum */
- cmd[1] = op_code;
- rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->mac80211.hw, 0x67, len, cmd);
-
- /* wait? */
- if (!wait_ms)
- return true;
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "btmpinfo wait req_num=%d wait=%ld\n", req_num, wait_ms);
-
- if (in_interrupt())
- return false;
-
- if (wait_for_completion_timeout(&btcoexist->bt_mp_comp,
- msecs_to_jiffies(wait_ms)) == 0) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
- "btmpinfo wait (req_num=%d) timeout\n", req_num);
-
- return false; /* timeout */
- }
-
- return true;
-}
-
-static void halbtc_leave_lps(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv;
- bool ap_enable = false;
-
- rtlpriv = btcoexist->adapter;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
- "%s()<--dont leave lps under AP mode\n", __func__);
- return;
- }
-
- btcoexist->bt_info.bt_ctrl_lps = true;
- btcoexist->bt_info.bt_lps_on = false;
- rtl_lps_leave(rtlpriv->mac80211.hw);
-}
-
-static void halbtc_enter_lps(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv;
- bool ap_enable = false;
-
- rtlpriv = btcoexist->adapter;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
- "%s()<--dont enter lps under AP mode\n", __func__);
- return;
- }
-
- btcoexist->bt_info.bt_ctrl_lps = true;
- btcoexist->bt_info.bt_lps_on = true;
- rtl_lps_enter(rtlpriv->mac80211.hw);
-}
-
-static void halbtc_normal_lps(struct btc_coexist *btcoexist)
-{
- struct rtl_priv *rtlpriv;
-
- rtlpriv = btcoexist->adapter;
-
- if (btcoexist->bt_info.bt_ctrl_lps) {
- btcoexist->bt_info.bt_lps_on = false;
- rtl_lps_leave(rtlpriv->mac80211.hw);
- btcoexist->bt_info.bt_ctrl_lps = false;
- }
-}
-
-static void halbtc_leave_low_power(struct btc_coexist *btcoexist)
-{
-}
-
-static void halbtc_normal_low_power(struct btc_coexist *btcoexist)
-{
-}
-
-static void halbtc_disable_low_power(struct btc_coexist *btcoexist,
- bool low_pwr_disable)
-{
- /* TODO: original/leave 32k low power */
- btcoexist->bt_info.bt_disable_low_pwr = low_pwr_disable;
-}
-
-static void halbtc_aggregation_check(struct btc_coexist *btcoexist)
-{
- bool need_to_act = false;
- static unsigned long pre_time;
- unsigned long cur_time = 0;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- /* To void continuous deleteBA=>addBA=>deleteBA=>addBA
- * This function is not allowed to continuous called
- * It can only be called after 8 seconds
- */
-
- cur_time = jiffies;
- if (jiffies_to_msecs(cur_time - pre_time) <= 8000) {
- /* over 8 seconds you can execute this function again. */
- return;
- }
- pre_time = cur_time;
-
- if (btcoexist->bt_info.reject_agg_pkt) {
- need_to_act = true;
- btcoexist->bt_info.pre_reject_agg_pkt =
- btcoexist->bt_info.reject_agg_pkt;
- } else {
- if (btcoexist->bt_info.pre_reject_agg_pkt) {
- need_to_act = true;
- btcoexist->bt_info.pre_reject_agg_pkt =
- btcoexist->bt_info.reject_agg_pkt;
- }
-
- if (btcoexist->bt_info.pre_bt_ctrl_agg_buf_size !=
- btcoexist->bt_info.bt_ctrl_agg_buf_size) {
- need_to_act = true;
- btcoexist->bt_info.pre_bt_ctrl_agg_buf_size =
- btcoexist->bt_info.bt_ctrl_agg_buf_size;
- }
-
- if (btcoexist->bt_info.bt_ctrl_agg_buf_size) {
- if (btcoexist->bt_info.pre_agg_buf_size !=
- btcoexist->bt_info.agg_buf_size) {
- need_to_act = true;
- }
- btcoexist->bt_info.pre_agg_buf_size =
- btcoexist->bt_info.agg_buf_size;
- }
-
- if (need_to_act)
- rtl_rx_ampdu_apply(rtlpriv);
- }
-}
-
-static u32 halbtc_get_bt_patch_version(struct btc_coexist *btcoexist)
-{
- u8 cmd_buffer[4] = {0};
-
- if (btcoexist->bt_info.bt_real_fw_ver)
- goto label_done;
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- halbtc_send_bt_mp_operation(btcoexist, BT_OP_GET_BT_VERSION,
- cmd_buffer, 4, 200);
-
-label_done:
- return btcoexist->bt_info.bt_real_fw_ver;
-}
-
-static u32 halbtc_get_bt_coex_supported_feature(void *btc_context)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- u8 cmd_buffer[4] = {0};
-
- if (btcoexist->bt_info.bt_supported_feature)
- goto label_done;
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- halbtc_send_bt_mp_operation(btcoexist,
- BT_OP_GET_BT_COEX_SUPPORTED_FEATURE,
- cmd_buffer, 4, 200);
-
-label_done:
- return btcoexist->bt_info.bt_supported_feature;
-}
-
-static u32 halbtc_get_bt_coex_supported_version(void *btc_context)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- u8 cmd_buffer[4] = {0};
-
- if (btcoexist->bt_info.bt_supported_version)
- goto label_done;
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- halbtc_send_bt_mp_operation(btcoexist,
- BT_OP_GET_BT_COEX_SUPPORTED_VERSION,
- cmd_buffer, 4, 200);
-
-label_done:
- return btcoexist->bt_info.bt_supported_version;
-}
-
-static u32 halbtc_get_wifi_link_status(struct btc_coexist *btcoexist)
-{
- /* return value:
- * [31:16] => connected port number
- * [15:0] => port connected bit define
- */
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- u32 port_connected_status = 0, num_of_connected_port = 0;
-
- if (mac->opmode == NL80211_IFTYPE_STATION &&
- mac->link_state >= MAC80211_LINKED) {
- port_connected_status |= WIFI_STA_CONNECTED;
- num_of_connected_port++;
- }
- /* AP & ADHOC & MESH */
- if (is_any_client_connect_to_ap(btcoexist)) {
- port_connected_status |= WIFI_AP_CONNECTED;
- num_of_connected_port++;
- }
- /* TODO: P2P Connected Status */
-
- return (num_of_connected_port << 16) | port_connected_status;
-}
-
-static bool halbtc_get(void *void_btcoexist, u8 get_type, void *out_buf)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)void_btcoexist;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- bool *bool_tmp = (bool *)out_buf;
- int *s32_tmp = (int *)out_buf;
- u32 *u32_tmp = (u32 *)out_buf;
- u8 *u8_tmp = (u8 *)out_buf;
- bool tmp = false;
- bool ret = true;
-
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return false;
-
- switch (get_type) {
- case BTC_GET_BL_HS_OPERATION:
- *bool_tmp = false;
- ret = false;
- break;
- case BTC_GET_BL_HS_CONNECTING:
- *bool_tmp = false;
- ret = false;
- break;
- case BTC_GET_BL_WIFI_CONNECTED:
- if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
- rtlpriv->mac80211.link_state >= MAC80211_LINKED)
- tmp = true;
- if (is_any_client_connect_to_ap(btcoexist))
- tmp = true;
- *bool_tmp = tmp;
- break;
- case BTC_GET_BL_WIFI_BUSY:
- if (halbtc_is_wifi_busy(rtlpriv))
- *bool_tmp = true;
- else
- *bool_tmp = false;
- break;
- case BTC_GET_BL_WIFI_SCAN:
- if (mac->act_scanning)
- *bool_tmp = true;
- else
- *bool_tmp = false;
- break;
- case BTC_GET_BL_WIFI_LINK:
- if (mac->link_state == MAC80211_LINKING)
- *bool_tmp = true;
- else
- *bool_tmp = false;
- break;
- case BTC_GET_BL_WIFI_ROAM:
- if (mac->link_state == MAC80211_LINKING)
- *bool_tmp = true;
- else
- *bool_tmp = false;
- break;
- case BTC_GET_BL_WIFI_4_WAY_PROGRESS:
- *bool_tmp = rtlpriv->btcoexist.btc_info.in_4way;
- break;
- case BTC_GET_BL_WIFI_UNDER_5G:
- if (rtlhal->current_bandtype == BAND_ON_5G)
- *bool_tmp = true;
- else
- *bool_tmp = false;
- break;
- case BTC_GET_BL_WIFI_AP_MODE_ENABLE:
- if (mac->opmode == NL80211_IFTYPE_AP)
- *bool_tmp = true;
- else
- *bool_tmp = false;
- break;
- case BTC_GET_BL_WIFI_ENABLE_ENCRYPTION:
- if (rtlpriv->sec.pairwise_enc_algorithm == NO_ENCRYPTION)
- *bool_tmp = false;
- else
- *bool_tmp = true;
- break;
- case BTC_GET_BL_WIFI_UNDER_B_MODE:
- if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
- *bool_tmp = true;
- else
- *bool_tmp = false;
- break;
- case BTC_GET_BL_EXT_SWITCH:
- *bool_tmp = false;
- break;
- case BTC_GET_BL_WIFI_IS_IN_MP_MODE:
- *bool_tmp = false;
- break;
- case BTC_GET_BL_IS_ASUS_8723B:
- *bool_tmp = false;
- break;
- case BTC_GET_BL_RF4CE_CONNECTED:
- *bool_tmp = false;
- break;
- case BTC_GET_S4_WIFI_RSSI:
- *s32_tmp = rtlpriv->dm.undec_sm_pwdb;
- break;
- case BTC_GET_S4_HS_RSSI:
- *s32_tmp = 0;
- ret = false;
- break;
- case BTC_GET_U4_WIFI_BW:
- *u32_tmp = halbtc_get_wifi_bw(btcoexist);
- break;
- case BTC_GET_U4_WIFI_TRAFFIC_DIRECTION:
- if (halbtc_is_wifi_uplink(rtlpriv))
- *u32_tmp = BTC_WIFI_TRAFFIC_TX;
- else
- *u32_tmp = BTC_WIFI_TRAFFIC_RX;
- break;
- case BTC_GET_U4_WIFI_FW_VER:
- *u32_tmp = (rtlhal->fw_version << 16) | rtlhal->fw_subversion;
- break;
- case BTC_GET_U4_WIFI_LINK_STATUS:
- *u32_tmp = halbtc_get_wifi_link_status(btcoexist);
- break;
- case BTC_GET_U4_BT_PATCH_VER:
- *u32_tmp = halbtc_get_bt_patch_version(btcoexist);
- break;
- case BTC_GET_U4_VENDOR:
- *u32_tmp = BTC_VENDOR_OTHER;
- break;
- case BTC_GET_U4_SUPPORTED_VERSION:
- *u32_tmp = halbtc_get_bt_coex_supported_version(btcoexist);
- break;
- case BTC_GET_U4_SUPPORTED_FEATURE:
- *u32_tmp = halbtc_get_bt_coex_supported_feature(btcoexist);
- break;
- case BTC_GET_U4_WIFI_IQK_TOTAL:
- *u32_tmp = btcoexist->btc_phydm_query_phy_counter(btcoexist,
- "IQK_TOTAL");
- break;
- case BTC_GET_U4_WIFI_IQK_OK:
- *u32_tmp = btcoexist->btc_phydm_query_phy_counter(btcoexist,
- "IQK_OK");
- break;
- case BTC_GET_U4_WIFI_IQK_FAIL:
- *u32_tmp = btcoexist->btc_phydm_query_phy_counter(btcoexist,
- "IQK_FAIL");
- break;
- case BTC_GET_U1_WIFI_DOT11_CHNL:
- *u8_tmp = rtlphy->current_channel;
- break;
- case BTC_GET_U1_WIFI_CENTRAL_CHNL:
- *u8_tmp = halbtc_get_wifi_central_chnl(btcoexist);
- break;
- case BTC_GET_U1_WIFI_HS_CHNL:
- *u8_tmp = 0;
- ret = false;
- break;
- case BTC_GET_U1_AP_NUM:
- *u8_tmp = rtlpriv->btcoexist.btc_info.ap_num;
- break;
- case BTC_GET_U1_ANT_TYPE:
- *u8_tmp = (u8)BTC_ANT_TYPE_0;
- break;
- case BTC_GET_U1_IOT_PEER:
- *u8_tmp = 0;
- break;
-
- /************* 1Ant **************/
- case BTC_GET_U1_LPS_MODE:
- *u8_tmp = btcoexist->pwr_mode_val[0];
- break;
-
- default:
- ret = false;
- break;
- }
-
- return ret;
-}
-
-static bool halbtc_set(void *void_btcoexist, u8 set_type, void *in_buf)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)void_btcoexist;
- bool *bool_tmp = (bool *)in_buf;
- u8 *u8_tmp = (u8 *)in_buf;
- u32 *u32_tmp = (u32 *)in_buf;
- bool ret = true;
-
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return false;
-
- switch (set_type) {
- /* set some bool type variables. */
- case BTC_SET_BL_BT_DISABLE:
- btcoexist->bt_info.bt_disabled = *bool_tmp;
- break;
- case BTC_SET_BL_BT_TRAFFIC_BUSY:
- btcoexist->bt_info.bt_busy = *bool_tmp;
- break;
- case BTC_SET_BL_BT_LIMITED_DIG:
- btcoexist->bt_info.limited_dig = *bool_tmp;
- break;
- case BTC_SET_BL_FORCE_TO_ROAM:
- btcoexist->bt_info.force_to_roam = *bool_tmp;
- break;
- case BTC_SET_BL_TO_REJ_AP_AGG_PKT:
- btcoexist->bt_info.reject_agg_pkt = *bool_tmp;
- break;
- case BTC_SET_BL_BT_CTRL_AGG_SIZE:
- btcoexist->bt_info.bt_ctrl_agg_buf_size = *bool_tmp;
- break;
- case BTC_SET_BL_INC_SCAN_DEV_NUM:
- btcoexist->bt_info.increase_scan_dev_num = *bool_tmp;
- break;
- case BTC_SET_BL_BT_TX_RX_MASK:
- btcoexist->bt_info.bt_tx_rx_mask = *bool_tmp;
- break;
- case BTC_SET_BL_MIRACAST_PLUS_BT:
- btcoexist->bt_info.miracast_plus_bt = *bool_tmp;
- break;
- /* set some u1Byte type variables. */
- case BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON:
- btcoexist->bt_info.rssi_adjust_for_agc_table_on = *u8_tmp;
- break;
- case BTC_SET_U1_AGG_BUF_SIZE:
- btcoexist->bt_info.agg_buf_size = *u8_tmp;
- break;
-
- /* the following are some action which will be triggered */
- case BTC_SET_ACT_GET_BT_RSSI:
- ret = false;
- break;
- case BTC_SET_ACT_AGGREGATE_CTRL:
- halbtc_aggregation_check(btcoexist);
- break;
-
- /* 1Ant */
- case BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE:
- btcoexist->bt_info.rssi_adjust_for_1ant_coex_type = *u8_tmp;
- break;
- case BTC_SET_UI_SCAN_SIG_COMPENSATION:
- break;
- case BTC_SET_U1_LPS_VAL:
- btcoexist->bt_info.lps_val = *u8_tmp;
- break;
- case BTC_SET_U1_RPWM_VAL:
- btcoexist->bt_info.rpwm_val = *u8_tmp;
- break;
- /* the following are some action which will be triggered */
- case BTC_SET_ACT_LEAVE_LPS:
- halbtc_leave_lps(btcoexist);
- break;
- case BTC_SET_ACT_ENTER_LPS:
- halbtc_enter_lps(btcoexist);
- break;
- case BTC_SET_ACT_NORMAL_LPS:
- halbtc_normal_lps(btcoexist);
- break;
- case BTC_SET_ACT_DISABLE_LOW_POWER:
- halbtc_disable_low_power(btcoexist, *bool_tmp);
- break;
- case BTC_SET_ACT_UPDATE_RAMASK:
- btcoexist->bt_info.ra_mask = *u32_tmp;
- break;
- case BTC_SET_ACT_SEND_MIMO_PS:
- break;
- case BTC_SET_ACT_CTRL_BT_INFO: /*wait for 8812/8821*/
- break;
- case BTC_SET_ACT_CTRL_BT_COEX:
- break;
- case BTC_SET_ACT_CTRL_8723B_ANT:
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-static void halbtc_display_coex_statistics(struct btc_coexist *btcoexist,
- struct seq_file *m)
-{
-}
-
-static void halbtc_display_bt_link_info(struct btc_coexist *btcoexist,
- struct seq_file *m)
-{
-}
-
-static void halbtc_display_wifi_status(struct btc_coexist *btcoexist,
- struct seq_file *m)
-{
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- s32 wifi_rssi = 0, bt_hs_rssi = 0;
- bool scan = false, link = false, roam = false, wifi_busy = false;
- bool wifi_under_b_mode = false, wifi_under_5g = false;
- u32 wifi_bw = BTC_WIFI_BW_HT20;
- u32 wifi_traffic_dir = BTC_WIFI_TRAFFIC_TX;
- u32 wifi_freq = BTC_FREQ_2_4G;
- u32 wifi_link_status = 0x0;
- bool bt_hs_on = false, under_ips = false, under_lps = false;
- bool low_power = false, dc_mode = false;
- u8 wifi_chnl = 0, wifi_hs_chnl = 0;
- u8 ap_num = 0;
-
- wifi_link_status = halbtc_get_wifi_link_status(btcoexist);
- seq_printf(m, "\n %-35s = %d/ %d/ %d/ %d/ %d",
- "STA/vWifi/HS/p2pGo/p2pGc",
- ((wifi_link_status & WIFI_STA_CONNECTED) ? 1 : 0),
- ((wifi_link_status & WIFI_AP_CONNECTED) ? 1 : 0),
- ((wifi_link_status & WIFI_HS_CONNECTED) ? 1 : 0),
- ((wifi_link_status & WIFI_P2P_GO_CONNECTED) ? 1 : 0),
- ((wifi_link_status & WIFI_P2P_GC_CONNECTED) ? 1 : 0));
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifi_chnl);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifi_hs_chnl);
- seq_printf(m, "\n %-35s = %d / %d(%d)",
- "Dot11 channel / HsChnl(High Speed)",
- wifi_chnl, wifi_hs_chnl, bt_hs_on);
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi);
- seq_printf(m, "\n %-35s = %d/ %d",
- "Wifi rssi/ HS rssi",
- wifi_rssi - 100, bt_hs_rssi - 100);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- seq_printf(m, "\n %-35s = %d/ %d/ %d ",
- "Wifi link/ roam/ scan",
- link, roam, scan);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
- &wifi_traffic_dir);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
- wifi_freq = (wifi_under_5g ? BTC_FREQ_5G : BTC_FREQ_2_4G);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- seq_printf(m, "\n %-35s = %s / %s/ %s/ AP=%d ",
- "Wifi freq/ bw/ traffic",
- gl_btc_wifi_freq_string[wifi_freq],
- ((wifi_under_b_mode) ? "11b" :
- gl_btc_wifi_bw_string[wifi_bw]),
- ((!wifi_busy) ? "idle" : ((BTC_WIFI_TRAFFIC_TX ==
- wifi_traffic_dir) ? "uplink" :
- "downlink")),
- ap_num);
-
- /* power status */
- dc_mode = true; /*TODO*/
- under_ips = rtlpriv->psc.inactive_pwrstate == ERFOFF ? 1 : 0;
- under_lps = rtlpriv->psc.dot11_psmode == EACTIVE ? 0 : 1;
- low_power = false; /*TODO*/
- seq_printf(m, "\n %-35s = %s%s%s%s",
- "Power Status",
- (dc_mode ? "DC mode" : "AC mode"),
- (under_ips ? ", IPS ON" : ""),
- (under_lps ? ", LPS ON" : ""),
- (low_power ? ", 32k" : ""));
-
- seq_printf(m,
- "\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)",
- "Power mode cmd(lps/rpwm)",
- btcoexist->pwr_mode_val[0], btcoexist->pwr_mode_val[1],
- btcoexist->pwr_mode_val[2], btcoexist->pwr_mode_val[3],
- btcoexist->pwr_mode_val[4], btcoexist->pwr_mode_val[5],
- btcoexist->bt_info.lps_val,
- btcoexist->bt_info.rpwm_val);
-}
-
-/************************************************************
- * IO related function
- ************************************************************/
-static u8 halbtc_read_1byte(void *bt_context, u32 reg_addr)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- return rtl_read_byte(rtlpriv, reg_addr);
-}
-
-static u16 halbtc_read_2byte(void *bt_context, u32 reg_addr)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- return rtl_read_word(rtlpriv, reg_addr);
-}
-
-static u32 halbtc_read_4byte(void *bt_context, u32 reg_addr)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- return rtl_read_dword(rtlpriv, reg_addr);
-}
-
-static void halbtc_write_1byte(void *bt_context, u32 reg_addr, u32 data)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- rtl_write_byte(rtlpriv, reg_addr, data);
-}
-
-static void halbtc_bitmask_write_1byte(void *bt_context, u32 reg_addr,
- u32 bit_mask, u8 data)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 original_value, bit_shift = 0;
- u8 i;
-
- if (bit_mask != MASKDWORD) {/*if not "double word" write*/
- original_value = rtl_read_byte(rtlpriv, reg_addr);
- for (i = 0; i <= 7; i++) {
- if ((bit_mask >> i) & 0x1)
- break;
- }
- bit_shift = i;
- data = (original_value & (~bit_mask)) |
- ((data << bit_shift) & bit_mask);
- }
- rtl_write_byte(rtlpriv, reg_addr, data);
-}
-
-static void halbtc_write_2byte(void *bt_context, u32 reg_addr, u16 data)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- rtl_write_word(rtlpriv, reg_addr, data);
-}
-
-static void halbtc_write_4byte(void *bt_context, u32 reg_addr, u32 data)
-{
- struct btc_coexist *btcoexist =
- (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- rtl_write_dword(rtlpriv, reg_addr, data);
-}
-
-static void halbtc_write_local_reg_1byte(void *btc_context, u32 reg_addr,
- u8 data)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- if (btcoexist->chip_interface == BTC_INTF_SDIO)
- ;
- else if (btcoexist->chip_interface == BTC_INTF_PCI)
- rtl_write_byte(rtlpriv, reg_addr, data);
- else if (btcoexist->chip_interface == BTC_INTF_USB)
- rtl_write_byte(rtlpriv, reg_addr, data);
-}
-
-static void halbtc_set_bbreg(void *bt_context, u32 reg_addr, u32 bit_mask,
- u32 data)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- rtl_set_bbreg(rtlpriv->mac80211.hw, reg_addr, bit_mask, data);
-}
-
-static u32 halbtc_get_bbreg(void *bt_context, u32 reg_addr, u32 bit_mask)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- return rtl_get_bbreg(rtlpriv->mac80211.hw, reg_addr, bit_mask);
-}
-
-static void halbtc_set_rfreg(void *bt_context, u8 rf_path, u32 reg_addr,
- u32 bit_mask, u32 data)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- rtl_set_rfreg(rtlpriv->mac80211.hw, rf_path, reg_addr, bit_mask, data);
-}
-
-static u32 halbtc_get_rfreg(void *bt_context, u8 rf_path, u32 reg_addr,
- u32 bit_mask)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- return rtl_get_rfreg(rtlpriv->mac80211.hw, rf_path, reg_addr, bit_mask);
-}
-
-static void halbtc_fill_h2c_cmd(void *bt_context, u8 element_id,
- u32 cmd_len, u8 *cmd_buf)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->mac80211.hw, element_id,
- cmd_len, cmd_buf);
-}
-
-static void halbtc_send_wifi_port_id_cmd(void *bt_context)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- u8 cmd_buf[1] = {0}; /* port id [2:0] = 0 */
-
- rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->mac80211.hw, 0x71, 1,
- cmd_buf);
-}
-
-static void halbtc_set_default_port_id_cmd(void *bt_context)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct ieee80211_hw *hw = rtlpriv->mac80211.hw;
-
- if (!rtlpriv->cfg->ops->set_default_port_id_cmd)
- return;
-
- rtlpriv->cfg->ops->set_default_port_id_cmd(hw);
-}
-
-static
-void halbtc_set_bt_reg(void *btc_context, u8 reg_type, u32 offset, u32 set_val)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- u8 cmd_buffer1[4] = {0};
- u8 cmd_buffer2[4] = {0};
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- *((__le16 *)&cmd_buffer1[2]) = cpu_to_le16((u16)set_val);
- if (!halbtc_send_bt_mp_operation(btcoexist, BT_OP_WRITE_REG_VALUE,
- cmd_buffer1, 4, 200))
- return;
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- cmd_buffer2[2] = reg_type;
- *((u8 *)&cmd_buffer2[3]) = (u8)offset;
- halbtc_send_bt_mp_operation(btcoexist, BT_OP_WRITE_REG_ADDR,
- cmd_buffer2, 4, 200);
-}
-
-static void halbtc_display_dbg_msg(void *bt_context, u8 disp_type,
- struct seq_file *m)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
-
- switch (disp_type) {
- case BTC_DBG_DISP_COEX_STATISTICS:
- halbtc_display_coex_statistics(btcoexist, m);
- break;
- case BTC_DBG_DISP_BT_LINK_INFO:
- halbtc_display_bt_link_info(btcoexist, m);
- break;
- case BTC_DBG_DISP_WIFI_STATUS:
- halbtc_display_wifi_status(btcoexist, m);
- break;
- default:
- break;
- }
-}
-
-static u32 halbtc_get_bt_reg(void *btc_context, u8 reg_type, u32 offset)
-{
- return 0;
-}
-
-static
-u32 halbtc_get_phydm_version(void *btc_context)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
-
- if (rtlpriv->phydm.ops)
- return rtlpriv->phydm.ops->phydm_get_version(rtlpriv);
-
- return 0;
-}
-
-static
-void halbtc_phydm_modify_ra_pcr_threshold(void *btc_context,
- u8 ra_offset_direction,
- u8 ra_threshold_offset)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct rtl_phydm_ops *phydm_ops = rtlpriv->phydm.ops;
-
- if (phydm_ops)
- phydm_ops->phydm_modify_ra_pcr_threshold(rtlpriv,
- ra_offset_direction,
- ra_threshold_offset);
-}
-
-static
-u32 halbtc_phydm_query_phy_counter(void *btc_context, const char *info_type)
-{
- /* info_type may be strings below:
- * PHYDM_INFO_FA_OFDM, PHYDM_INFO_FA_CCK, PHYDM_INFO_CCA_OFDM,
- * PHYDM_INFO_CCA_CCK
- * IQK_TOTAL, IQK_OK, IQK_FAIL
- */
-
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- struct rtl_priv *rtlpriv = btcoexist->adapter;
- struct rtl_phydm_ops *phydm_ops = rtlpriv->phydm.ops;
-
- if (phydm_ops)
- return phydm_ops->phydm_query_counter(rtlpriv, info_type);
-
- return 0;
-}
-
-static u8 halbtc_get_ant_det_val_from_bt(void *btc_context)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- u8 cmd_buffer[4] = {0};
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- halbtc_send_bt_mp_operation(btcoexist, BT_OP_GET_BT_ANT_DET_VAL,
- cmd_buffer, 4, 200);
-
- /* need wait completion to return correct value */
-
- return btcoexist->bt_info.bt_ant_det_val;
-}
-
-static u8 halbtc_get_ble_scan_type_from_bt(void *btc_context)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- u8 cmd_buffer[4] = {0};
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- halbtc_send_bt_mp_operation(btcoexist, BT_OP_GET_BT_BLE_SCAN_TYPE,
- cmd_buffer, 4, 200);
-
- /* need wait completion to return correct value */
-
- return btcoexist->bt_info.bt_ble_scan_type;
-}
-
-static u32 halbtc_get_ble_scan_para_from_bt(void *btc_context, u8 scan_type)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- u8 cmd_buffer[4] = {0};
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- halbtc_send_bt_mp_operation(btcoexist, BT_OP_GET_BT_BLE_SCAN_PARA,
- cmd_buffer, 4, 200);
-
- /* need wait completion to return correct value */
-
- return btcoexist->bt_info.bt_ble_scan_para;
-}
-
-static bool halbtc_get_bt_afh_map_from_bt(void *btc_context, u8 map_type,
- u8 *afh_map)
-{
- struct btc_coexist *btcoexist = (struct btc_coexist *)btc_context;
- u8 cmd_buffer[2] = {0};
- bool ret;
- u32 *afh_map_l = (u32 *)afh_map;
- u32 *afh_map_m = (u32 *)(afh_map + 4);
- u16 *afh_map_h = (u16 *)(afh_map + 8);
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- ret = halbtc_send_bt_mp_operation(btcoexist, BT_OP_GET_AFH_MAP_L,
- cmd_buffer, 2, 200);
- if (!ret)
- goto exit;
-
- *afh_map_l = btcoexist->bt_info.afh_map_l;
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- ret = halbtc_send_bt_mp_operation(btcoexist, BT_OP_GET_AFH_MAP_M,
- cmd_buffer, 2, 200);
- if (!ret)
- goto exit;
-
- *afh_map_m = btcoexist->bt_info.afh_map_m;
-
- /* cmd_buffer[0] and [1] is filled by halbtc_send_bt_mp_operation() */
- ret = halbtc_send_bt_mp_operation(btcoexist, BT_OP_GET_AFH_MAP_H,
- cmd_buffer, 2, 200);
- if (!ret)
- goto exit;
-
- *afh_map_h = btcoexist->bt_info.afh_map_h;
-
-exit:
- return ret;
-}
-
-/*****************************************************************
- * Extern functions called by other module
- *****************************************************************/
-bool exhalbtc_initlize_variables(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return false;
-
- halbtc_dbg_init();
-
- btcoexist->btc_read_1byte = halbtc_read_1byte;
- btcoexist->btc_write_1byte = halbtc_write_1byte;
- btcoexist->btc_write_1byte_bitmask = halbtc_bitmask_write_1byte;
- btcoexist->btc_read_2byte = halbtc_read_2byte;
- btcoexist->btc_write_2byte = halbtc_write_2byte;
- btcoexist->btc_read_4byte = halbtc_read_4byte;
- btcoexist->btc_write_4byte = halbtc_write_4byte;
- btcoexist->btc_write_local_reg_1byte = halbtc_write_local_reg_1byte;
-
- btcoexist->btc_set_bb_reg = halbtc_set_bbreg;
- btcoexist->btc_get_bb_reg = halbtc_get_bbreg;
-
- btcoexist->btc_set_rf_reg = halbtc_set_rfreg;
- btcoexist->btc_get_rf_reg = halbtc_get_rfreg;
-
- btcoexist->btc_fill_h2c = halbtc_fill_h2c_cmd;
- btcoexist->btc_disp_dbg_msg = halbtc_display_dbg_msg;
-
- btcoexist->btc_get = halbtc_get;
- btcoexist->btc_set = halbtc_set;
- btcoexist->btc_set_bt_reg = halbtc_set_bt_reg;
- btcoexist->btc_get_bt_reg = halbtc_get_bt_reg;
-
- btcoexist->bt_info.bt_ctrl_buf_size = false;
- btcoexist->bt_info.agg_buf_size = 5;
-
- btcoexist->bt_info.increase_scan_dev_num = false;
-
- btcoexist->btc_get_bt_coex_supported_feature =
- halbtc_get_bt_coex_supported_feature;
- btcoexist->btc_get_bt_coex_supported_version =
- halbtc_get_bt_coex_supported_version;
- btcoexist->btc_get_bt_phydm_version = halbtc_get_phydm_version;
- btcoexist->btc_phydm_modify_ra_pcr_threshold =
- halbtc_phydm_modify_ra_pcr_threshold;
- btcoexist->btc_phydm_query_phy_counter = halbtc_phydm_query_phy_counter;
- btcoexist->btc_get_ant_det_val_from_bt = halbtc_get_ant_det_val_from_bt;
- btcoexist->btc_get_ble_scan_type_from_bt =
- halbtc_get_ble_scan_type_from_bt;
- btcoexist->btc_get_ble_scan_para_from_bt =
- halbtc_get_ble_scan_para_from_bt;
- btcoexist->btc_get_bt_afh_map_from_bt =
- halbtc_get_bt_afh_map_from_bt;
-
- init_completion(&btcoexist->bt_mp_comp);
-
- return true;
-}
-
-bool exhalbtc_initlize_variables_wifi_only(struct rtl_priv *rtlpriv)
-{
- struct wifi_only_cfg *wifionly_cfg = rtl_btc_wifi_only(rtlpriv);
- struct wifi_only_haldata *wifionly_haldata;
-
- if (!wifionly_cfg)
- return false;
-
- wifionly_cfg->adapter = rtlpriv;
-
- switch (rtlpriv->rtlhal.interface) {
- case INTF_PCI:
- wifionly_cfg->chip_interface = WIFIONLY_INTF_PCI;
- break;
- case INTF_USB:
- wifionly_cfg->chip_interface = WIFIONLY_INTF_USB;
- break;
- default:
- wifionly_cfg->chip_interface = WIFIONLY_INTF_UNKNOWN;
- break;
- }
-
- wifionly_haldata = &wifionly_cfg->haldata_info;
-
- wifionly_haldata->customer_id = CUSTOMER_NORMAL;
- wifionly_haldata->efuse_pg_antnum = rtl_get_hwpg_ant_num(rtlpriv);
- wifionly_haldata->efuse_pg_antpath =
- rtl_get_hwpg_single_ant_path(rtlpriv);
- wifionly_haldata->rfe_type = rtl_get_hwpg_rfe_type(rtlpriv);
- wifionly_haldata->ant_div_cfg = 0;
-
- return true;
-}
-
-bool exhalbtc_bind_bt_coex_withadapter(void *adapter)
-{
- struct rtl_priv *rtlpriv = adapter;
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
- u8 ant_num = 2, chip_type, single_ant_path = 0;
-
- if (!btcoexist)
- return false;
-
- if (btcoexist->binded)
- return false;
-
- switch (rtlpriv->rtlhal.interface) {
- case INTF_PCI:
- btcoexist->chip_interface = BTC_INTF_PCI;
- break;
- case INTF_USB:
- btcoexist->chip_interface = BTC_INTF_USB;
- break;
- default:
- btcoexist->chip_interface = BTC_INTF_UNKNOWN;
- break;
- }
-
- btcoexist->binded = true;
- btcoexist->statistics.cnt_bind++;
-
- btcoexist->adapter = adapter;
-
- btcoexist->stack_info.profile_notified = false;
-
- btcoexist->bt_info.bt_ctrl_agg_buf_size = false;
- btcoexist->bt_info.agg_buf_size = 5;
-
- btcoexist->bt_info.increase_scan_dev_num = false;
- btcoexist->bt_info.miracast_plus_bt = false;
-
- chip_type = rtl_get_hwpg_bt_type(rtlpriv);
- exhalbtc_set_chip_type(btcoexist, chip_type);
- ant_num = rtl_get_hwpg_ant_num(rtlpriv);
- exhalbtc_set_ant_num(rtlpriv, BT_COEX_ANT_TYPE_PG, ant_num);
-
- /* set default antenna position to main port */
- btcoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
-
- single_ant_path = rtl_get_hwpg_single_ant_path(rtlpriv);
- exhalbtc_set_single_ant_path(btcoexist, single_ant_path);
-
- if (rtl_get_hwpg_package_type(rtlpriv) == 0)
- btcoexist->board_info.tfbga_package = false;
- else if (rtl_get_hwpg_package_type(rtlpriv) == 1)
- btcoexist->board_info.tfbga_package = false;
- else
- btcoexist->board_info.tfbga_package = true;
-
- if (btcoexist->board_info.tfbga_package)
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Package Type = TFBGA\n");
- else
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "[BTCoex], Package Type = Non-TFBGA\n");
-
- btcoexist->board_info.rfe_type = rtl_get_hwpg_rfe_type(rtlpriv);
- btcoexist->board_info.ant_div_cfg = 0;
-
- return true;
-}
-
-void exhalbtc_power_on_setting(struct btc_coexist *btcoexist)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- btcoexist->statistics.cnt_power_on++;
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_power_on_setting(btcoexist);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_power_on_setting(btcoexist);
- }
-}
-
-void exhalbtc_pre_load_firmware(struct btc_coexist *btcoexist)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- btcoexist->statistics.cnt_pre_load_firmware++;
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_pre_load_firmware(btcoexist);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_pre_load_firmware(btcoexist);
- }
-}
-
-void exhalbtc_init_hw_config(struct btc_coexist *btcoexist, bool wifi_only)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- btcoexist->statistics.cnt_init_hw_config++;
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_init_hw_config(btcoexist, wifi_only);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_init_hw_config(btcoexist, wifi_only);
-
- halbtc_set_default_port_id_cmd(btcoexist);
- halbtc_send_wifi_port_id_cmd(btcoexist);
- }
-}
-
-void exhalbtc_init_hw_config_wifi_only(struct wifi_only_cfg *wifionly_cfg)
-{
- if (IS_HARDWARE_TYPE_8822B(wifionly_cfg->adapter))
- ex_hal8822b_wifi_only_hw_config(wifionly_cfg);
-}
-
-void exhalbtc_init_coex_dm(struct btc_coexist *btcoexist)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- btcoexist->statistics.cnt_init_coex_dm++;
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_init_coex_dm(btcoexist);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_init_coex_dm(btcoexist);
- }
-
- btcoexist->initilized = true;
-}
-
-void exhalbtc_ips_notify(struct btc_coexist *btcoexist, u8 type)
-{
- u8 ips_type;
-
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_ips_notify++;
- if (btcoexist->manual_control)
- return;
-
- if (type == ERFOFF)
- ips_type = BTC_IPS_ENTER;
- else
- ips_type = BTC_IPS_LEAVE;
-
- halbtc_leave_low_power(btcoexist);
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_ips_notify(btcoexist, ips_type);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_ips_notify(btcoexist, ips_type);
- }
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_lps_notify(struct btc_coexist *btcoexist, u8 type)
-{
- u8 lps_type;
-
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_lps_notify++;
- if (btcoexist->manual_control)
- return;
-
- if (type == EACTIVE)
- lps_type = BTC_LPS_DISABLE;
- else
- lps_type = BTC_LPS_ENABLE;
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_lps_notify(btcoexist, lps_type);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_lps_notify(btcoexist, lps_type);
- }
-}
-
-void exhalbtc_scan_notify(struct btc_coexist *btcoexist, u8 type)
-{
- u8 scan_type;
-
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_scan_notify++;
- if (btcoexist->manual_control)
- return;
-
- if (type)
- scan_type = BTC_SCAN_START;
- else
- scan_type = BTC_SCAN_FINISH;
-
- halbtc_leave_low_power(btcoexist);
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_scan_notify(btcoexist, scan_type);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_scan_notify(btcoexist, scan_type);
- }
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_scan_notify_wifi_only(struct wifi_only_cfg *wifionly_cfg,
- u8 is_5g)
-{
- if (IS_HARDWARE_TYPE_8822B(wifionly_cfg->adapter))
- ex_hal8822b_wifi_only_scannotify(wifionly_cfg, is_5g);
-}
-
-void exhalbtc_connect_notify(struct btc_coexist *btcoexist, u8 action)
-{
- u8 asso_type;
-
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_connect_notify++;
- if (btcoexist->manual_control)
- return;
-
- if (action)
- asso_type = BTC_ASSOCIATE_START;
- else
- asso_type = BTC_ASSOCIATE_FINISH;
-
- halbtc_leave_low_power(btcoexist);
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_connect_notify(btcoexist, asso_type);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_connect_notify(btcoexist, asso_type);
- }
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_mediastatus_notify(struct btc_coexist *btcoexist,
- enum rt_media_status media_status)
-{
- u8 status;
-
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_media_status_notify++;
- if (btcoexist->manual_control)
- return;
-
- if (media_status == RT_MEDIA_CONNECT)
- status = BTC_MEDIA_CONNECT;
- else
- status = BTC_MEDIA_DISCONNECT;
-
- halbtc_leave_low_power(btcoexist);
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_media_status_notify(btcoexist, status);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_media_status_notify(btcoexist, status);
- }
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_special_packet_notify(struct btc_coexist *btcoexist, u8 pkt_type)
-{
- u8 packet_type;
-
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_special_packet_notify++;
- if (btcoexist->manual_control)
- return;
-
- if (pkt_type == PACKET_DHCP) {
- packet_type = BTC_PACKET_DHCP;
- } else if (pkt_type == PACKET_EAPOL) {
- packet_type = BTC_PACKET_EAPOL;
- } else if (pkt_type == PACKET_ARP) {
- packet_type = BTC_PACKET_ARP;
- } else {
- packet_type = BTC_PACKET_UNKNOWN;
- return;
- }
-
- halbtc_leave_low_power(btcoexist);
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_specific_packet_notify(btcoexist,
- packet_type);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_specific_packet_notify(btcoexist,
- packet_type);
- }
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_bt_info_notify(struct btc_coexist *btcoexist,
- u8 *tmp_buf, u8 length)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_bt_info_notify++;
-
- halbtc_leave_low_power(btcoexist);
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_bt_info_notify(btcoexist, tmp_buf,
- length);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_bt_info_notify(btcoexist, tmp_buf,
- length);
- }
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_rf_status_notify(struct btc_coexist *btcoexist, u8 type)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_rf_status_notify(btcoexist, type);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_rf_status_notify(btcoexist, type);
- }
-}
-
-void exhalbtc_stack_operation_notify(struct btc_coexist *btcoexist, u8 type)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_stack_operation_notify++;
-}
-
-void exhalbtc_halt_notify(struct btc_coexist *btcoexist)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_halt_notify(btcoexist);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_halt_notify(btcoexist);
- }
-
- btcoexist->binded = false;
-}
-
-void exhalbtc_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- /* currently only 1ant we have to do the notification,
- * once pnp is notified to sleep state, we have to leave LPS that
- * we can sleep normally.
- */
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_pnp_notify(btcoexist, pnp_state);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_pnp_notify(btcoexist, pnp_state);
- }
-}
-
-void exhalbtc_coex_dm_switch(struct btc_coexist *btcoexist)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_coex_dm_switch++;
-
- halbtc_leave_low_power(btcoexist);
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_periodical(struct btc_coexist *btcoexist)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_periodical++;
-
- halbtc_leave_low_power(btcoexist);
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_periodical(btcoexist);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_periodical(btcoexist);
- }
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_dbg_control(struct btc_coexist *btcoexist,
- u8 code, u8 len, u8 *data)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
- btcoexist->statistics.cnt_dbg_ctrl++;
-
- halbtc_leave_low_power(btcoexist);
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_antenna_detection(struct btc_coexist *btcoexist, u32 cent_freq,
- u32 offset, u32 span, u32 seconds)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-}
-
-void exhalbtc_stack_update_profile_info(void)
-{
-}
-
-void exhalbtc_update_min_bt_rssi(struct btc_coexist *btcoexist, s8 bt_rssi)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- btcoexist->stack_info.min_bt_rssi = bt_rssi;
-}
-
-void exhalbtc_set_hci_version(struct btc_coexist *btcoexist, u16 hci_version)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- btcoexist->stack_info.hci_version = hci_version;
-}
-
-void exhalbtc_set_bt_patch_version(struct btc_coexist *btcoexist,
- u16 bt_hci_version, u16 bt_patch_version)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- btcoexist->bt_info.bt_real_fw_ver = bt_patch_version;
- btcoexist->bt_info.bt_hci_ver = bt_hci_version;
-}
-
-void exhalbtc_set_chip_type(struct btc_coexist *btcoexist, u8 chip_type)
-{
- switch (chip_type) {
- default:
- case BT_2WIRE:
- case BT_ISSC_3WIRE:
- case BT_ACCEL:
- case BT_RTL8756:
- btcoexist->board_info.bt_chip_type = BTC_CHIP_UNDEF;
- break;
- case BT_CSR_BC4:
- btcoexist->board_info.bt_chip_type = BTC_CHIP_CSR_BC4;
- break;
- case BT_CSR_BC8:
- btcoexist->board_info.bt_chip_type = BTC_CHIP_CSR_BC8;
- break;
- case BT_RTL8723A:
- btcoexist->board_info.bt_chip_type = BTC_CHIP_RTL8723A;
- break;
- case BT_RTL8821A:
- btcoexist->board_info.bt_chip_type = BTC_CHIP_RTL8821;
- break;
- case BT_RTL8723B:
- btcoexist->board_info.bt_chip_type = BTC_CHIP_RTL8723B;
- break;
- }
-}
-
-void exhalbtc_set_ant_num(struct rtl_priv *rtlpriv, u8 type, u8 ant_num)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- if (type == BT_COEX_ANT_TYPE_PG) {
- btcoexist->board_info.pg_ant_num = ant_num;
- btcoexist->board_info.btdm_ant_num = ant_num;
- } else if (type == BT_COEX_ANT_TYPE_ANTDIV) {
- btcoexist->board_info.btdm_ant_num = ant_num;
- } else if (type == BT_COEX_ANT_TYPE_DETECTED) {
- btcoexist->board_info.btdm_ant_num = ant_num;
- if (rtlpriv->cfg->mod_params->ant_sel == 1)
- btcoexist->board_info.btdm_ant_pos =
- BTC_ANTENNA_AT_AUX_PORT;
- else
- btcoexist->board_info.btdm_ant_pos =
- BTC_ANTENNA_AT_MAIN_PORT;
- }
-}
-
-/* Currently used by 8723b only, S0 or S1 */
-void exhalbtc_set_single_ant_path(struct btc_coexist *btcoexist,
- u8 single_ant_path)
-{
- btcoexist->board_info.single_ant_path = single_ant_path;
-}
-
-void exhalbtc_display_bt_coex_info(struct btc_coexist *btcoexist,
- struct seq_file *m)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- halbtc_leave_low_power(btcoexist);
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_display_coex_info(btcoexist, m);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_display_coex_info(btcoexist, m);
- }
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_switch_band_notify(struct btc_coexist *btcoexist, u8 type)
-{
- if (!halbtc_is_bt_coexist_available(btcoexist))
- return;
-
- if (btcoexist->manual_control)
- return;
-
- halbtc_leave_low_power(btcoexist);
-
- if (IS_HARDWARE_TYPE_8822B(btcoexist->adapter)) {
- if (btcoexist->board_info.btdm_ant_num == 1)
- ex_btc8822b1ant_switchband_notify(btcoexist, type);
- else if (btcoexist->board_info.btdm_ant_num == 2)
- ex_btc8822b2ant_switchband_notify(btcoexist, type);
- }
-
- halbtc_normal_low_power(btcoexist);
-}
-
-void exhalbtc_switch_band_notify_wifi_only(struct wifi_only_cfg *wifionly_cfg,
- u8 is_5g)
-{
- if (IS_HARDWARE_TYPE_8822B(wifionly_cfg->adapter))
- ex_hal8822b_wifi_only_switchbandnotify(wifionly_cfg, is_5g);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __HALBTC_OUT_SRC_H__
-#define __HALBTC_OUT_SRC_H__
-
-#include "../wifi.h"
-
-#define BTC_COEX_OFFLOAD 0
-
-#define NORMAL_EXEC false
-#define FORCE_EXEC true
-
-#define BTC_RF_OFF 0x0
-#define BTC_RF_ON 0x1
-
-#define BTC_RF_A RF90_PATH_A
-#define BTC_RF_B RF90_PATH_B
-#define BTC_RF_C RF90_PATH_C
-#define BTC_RF_D RF90_PATH_D
-
-#define BTC_SMSP SINGLEMAC_SINGLEPHY
-#define BTC_DMDP DUALMAC_DUALPHY
-#define BTC_DMSP DUALMAC_SINGLEPHY
-#define BTC_MP_UNKNOWN 0xff
-
-#define IN
-#define OUT
-
-#define BT_TMP_BUF_SIZE 100
-
-#define BT_COEX_ANT_TYPE_PG 0
-#define BT_COEX_ANT_TYPE_ANTDIV 1
-#define BT_COEX_ANT_TYPE_DETECTED 2
-
-#define BTC_MIMO_PS_STATIC 0
-#define BTC_MIMO_PS_DYNAMIC 1
-
-#define BTC_RATE_DISABLE 0
-#define BTC_RATE_ENABLE 1
-
-/* single Antenna definition */
-#define BTC_ANT_PATH_WIFI 0
-#define BTC_ANT_PATH_BT 1
-#define BTC_ANT_PATH_PTA 2
-#define BTC_ANT_PATH_WIFI5G 3
-#define BTC_ANT_PATH_AUTO 4
-/* dual Antenna definition */
-#define BTC_ANT_WIFI_AT_MAIN 0
-#define BTC_ANT_WIFI_AT_AUX 1
-#define BTC_ANT_WIFI_AT_DIVERSITY 2
-/* coupler Antenna definition */
-#define BTC_ANT_WIFI_AT_CPL_MAIN 0
-#define BTC_ANT_WIFI_AT_CPL_AUX 1
-
-enum btc_bt_reg_type {
- BTC_BT_REG_RF = 0,
- BTC_BT_REG_MODEM = 1,
- BTC_BT_REG_BLUEWIZE = 2,
- BTC_BT_REG_VENDOR = 3,
- BTC_BT_REG_LE = 4,
- BTC_BT_REG_MAX
-};
-
-enum btc_chip_interface {
- BTC_INTF_UNKNOWN = 0,
- BTC_INTF_PCI = 1,
- BTC_INTF_USB = 2,
- BTC_INTF_SDIO = 3,
- BTC_INTF_GSPI = 4,
- BTC_INTF_MAX
-};
-
-enum btc_chip_type {
- BTC_CHIP_UNDEF = 0,
- BTC_CHIP_CSR_BC4 = 1,
- BTC_CHIP_CSR_BC8 = 2,
- BTC_CHIP_RTL8723A = 3,
- BTC_CHIP_RTL8821 = 4,
- BTC_CHIP_RTL8723B = 5,
- BTC_CHIP_MAX
-};
-
-enum btc_msg_type {
- BTC_MSG_INTERFACE = 0x0,
- BTC_MSG_ALGORITHM = 0x1,
- BTC_MSG_MAX
-};
-
-/* following is for BTC_MSG_INTERFACE */
-#define INTF_INIT BIT0
-#define INTF_NOTIFY BIT2
-
-/* following is for BTC_ALGORITHM */
-#define ALGO_BT_RSSI_STATE BIT0
-#define ALGO_WIFI_RSSI_STATE BIT1
-#define ALGO_BT_MONITOR BIT2
-#define ALGO_TRACE BIT3
-#define ALGO_TRACE_FW BIT4
-#define ALGO_TRACE_FW_DETAIL BIT5
-#define ALGO_TRACE_FW_EXEC BIT6
-#define ALGO_TRACE_SW BIT7
-#define ALGO_TRACE_SW_DETAIL BIT8
-#define ALGO_TRACE_SW_EXEC BIT9
-
-/* following is for wifi link status */
-#define WIFI_STA_CONNECTED BIT0
-#define WIFI_AP_CONNECTED BIT1
-#define WIFI_HS_CONNECTED BIT2
-#define WIFI_P2P_GO_CONNECTED BIT3
-#define WIFI_P2P_GC_CONNECTED BIT4
-
-#define BTC_RSSI_HIGH(_rssi_) \
- ((_rssi_ == BTC_RSSI_STATE_HIGH || \
- _rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? true : false)
-#define BTC_RSSI_MEDIUM(_rssi_) \
- ((_rssi_ == BTC_RSSI_STATE_MEDIUM || \
- _rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? true : false)
-#define BTC_RSSI_LOW(_rssi_) \
- ((_rssi_ == BTC_RSSI_STATE_LOW || \
- _rssi_ == BTC_RSSI_STATE_STAY_LOW) ? true : false)
-
-enum btc_power_save_type {
- BTC_PS_WIFI_NATIVE = 0,
- BTC_PS_LPS_ON = 1,
- BTC_PS_LPS_OFF = 2,
- BTC_PS_LPS_MAX
-};
-
-struct btc_board_info {
- /* The following is some board information */
- u8 bt_chip_type;
- u8 pg_ant_num; /* pg ant number */
- u8 btdm_ant_num; /* ant number for btdm */
- u8 btdm_ant_num_by_ant_det;
- u8 btdm_ant_pos;
- u8 single_ant_path; /* current used for 8723b only, 1=>s0, 0=>s1 */
- bool tfbga_package;
- bool btdm_ant_det_finish;
-
- u8 rfe_type;
- u8 ant_div_cfg;
-};
-
-enum btc_dbg_opcode {
- BTC_DBG_SET_COEX_NORMAL = 0x0,
- BTC_DBG_SET_COEX_WIFI_ONLY = 0x1,
- BTC_DBG_SET_COEX_BT_ONLY = 0x2,
- BTC_DBG_MAX
-};
-
-enum btc_rssi_state {
- BTC_RSSI_STATE_HIGH = 0x0,
- BTC_RSSI_STATE_MEDIUM = 0x1,
- BTC_RSSI_STATE_LOW = 0x2,
- BTC_RSSI_STATE_STAY_HIGH = 0x3,
- BTC_RSSI_STATE_STAY_MEDIUM = 0x4,
- BTC_RSSI_STATE_STAY_LOW = 0x5,
- BTC_RSSI_MAX
-};
-
-enum btc_wifi_role {
- BTC_ROLE_STATION = 0x0,
- BTC_ROLE_AP = 0x1,
- BTC_ROLE_IBSS = 0x2,
- BTC_ROLE_HS_MODE = 0x3,
- BTC_ROLE_MAX
-};
-
-enum btc_wireless_freq {
- BTC_FREQ_2_4G = 0x0,
- BTC_FREQ_5G = 0x1,
- BTC_FREQ_MAX
-};
-
-enum btc_wifi_bw_mode {
- BTC_WIFI_BW_LEGACY = 0x0,
- BTC_WIFI_BW_HT20 = 0x1,
- BTC_WIFI_BW_HT40 = 0x2,
- BTC_WIFI_BW_HT80 = 0x3,
- BTC_WIFI_BW_MAX
-};
-
-enum btc_wifi_traffic_dir {
- BTC_WIFI_TRAFFIC_TX = 0x0,
- BTC_WIFI_TRAFFIC_RX = 0x1,
- BTC_WIFI_TRAFFIC_MAX
-};
-
-enum btc_wifi_pnp {
- BTC_WIFI_PNP_WAKE_UP = 0x0,
- BTC_WIFI_PNP_SLEEP = 0x1,
- BTC_WIFI_PNP_SLEEP_KEEP_ANT = 0x2,
- BTC_WIFI_PNP_MAX
-};
-
-enum btc_iot_peer {
- BTC_IOT_PEER_UNKNOWN = 0,
- BTC_IOT_PEER_REALTEK = 1,
- BTC_IOT_PEER_REALTEK_92SE = 2,
- BTC_IOT_PEER_BROADCOM = 3,
- BTC_IOT_PEER_RALINK = 4,
- BTC_IOT_PEER_ATHEROS = 5,
- BTC_IOT_PEER_CISCO = 6,
- BTC_IOT_PEER_MERU = 7,
- BTC_IOT_PEER_MARVELL = 8,
- BTC_IOT_PEER_REALTEK_SOFTAP = 9,
- BTC_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */
- BTC_IOT_PEER_AIRGO = 11,
- BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 12,
- BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 13,
- BTC_IOT_PEER_MAX,
-};
-
-/* for 8723b-d cut large current issue */
-enum bt_wifi_coex_state {
- BTC_WIFI_STAT_INIT,
- BTC_WIFI_STAT_IQK,
- BTC_WIFI_STAT_NORMAL_OFF,
- BTC_WIFI_STAT_MP_OFF,
- BTC_WIFI_STAT_NORMAL,
- BTC_WIFI_STAT_ANT_DIV,
- BTC_WIFI_STAT_MAX
-};
-
-enum bt_ant_type {
- BTC_ANT_TYPE_0,
- BTC_ANT_TYPE_1,
- BTC_ANT_TYPE_2,
- BTC_ANT_TYPE_3,
- BTC_ANT_TYPE_4,
- BTC_ANT_TYPE_MAX
-};
-
-enum btc_get_type {
- /* type bool */
- BTC_GET_BL_HS_OPERATION,
- BTC_GET_BL_HS_CONNECTING,
- BTC_GET_BL_WIFI_CONNECTED,
- BTC_GET_BL_WIFI_BUSY,
- BTC_GET_BL_WIFI_SCAN,
- BTC_GET_BL_WIFI_LINK,
- BTC_GET_BL_WIFI_DHCP,
- BTC_GET_BL_WIFI_SOFTAP_IDLE,
- BTC_GET_BL_WIFI_SOFTAP_LINKING,
- BTC_GET_BL_WIFI_IN_EARLY_SUSPEND,
- BTC_GET_BL_WIFI_ROAM,
- BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- BTC_GET_BL_WIFI_UNDER_5G,
- BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- BTC_GET_BL_EXT_SWITCH,
- BTC_GET_BL_WIFI_IS_IN_MP_MODE,
- BTC_GET_BL_IS_ASUS_8723B,
- BTC_GET_BL_FW_READY,
- BTC_GET_BL_RF4CE_CONNECTED,
-
- /* type s4Byte */
- BTC_GET_S4_WIFI_RSSI,
- BTC_GET_S4_HS_RSSI,
-
- /* type u32 */
- BTC_GET_U4_WIFI_BW,
- BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
- BTC_GET_U4_WIFI_FW_VER,
- BTC_GET_U4_WIFI_LINK_STATUS,
- BTC_GET_U4_BT_PATCH_VER,
- BTC_GET_U4_VENDOR,
- BTC_GET_U4_SUPPORTED_VERSION,
- BTC_GET_U4_SUPPORTED_FEATURE,
- BTC_GET_U4_WIFI_IQK_TOTAL,
- BTC_GET_U4_WIFI_IQK_OK,
- BTC_GET_U4_WIFI_IQK_FAIL,
-
- /* type u1Byte */
- BTC_GET_U1_WIFI_DOT11_CHNL,
- BTC_GET_U1_WIFI_CENTRAL_CHNL,
- BTC_GET_U1_WIFI_HS_CHNL,
- BTC_GET_U1_MAC_PHY_MODE,
- BTC_GET_U1_AP_NUM,
- BTC_GET_U1_ANT_TYPE,
- BTC_GET_U1_IOT_PEER,
-
- /* for 1Ant */
- BTC_GET_U1_LPS_MODE,
- BTC_GET_BL_BT_SCO_BUSY,
-
- /* for test mode */
- BTC_GET_DRIVER_TEST_CFG,
- BTC_GET_MAX
-};
-
-enum btc_vendor {
- BTC_VENDOR_LENOVO,
- BTC_VENDOR_ASUS,
- BTC_VENDOR_OTHER
-};
-
-enum btc_set_type {
- /* type bool */
- BTC_SET_BL_BT_DISABLE,
- BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE,
- BTC_SET_BL_BT_TRAFFIC_BUSY,
- BTC_SET_BL_BT_LIMITED_DIG,
- BTC_SET_BL_FORCE_TO_ROAM,
- BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- BTC_SET_BL_BT_CTRL_AGG_SIZE,
- BTC_SET_BL_INC_SCAN_DEV_NUM,
- BTC_SET_BL_BT_TX_RX_MASK,
- BTC_SET_BL_MIRACAST_PLUS_BT,
-
- /* type u1Byte */
- BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
- BTC_SET_UI_SCAN_SIG_COMPENSATION,
- BTC_SET_U1_AGG_BUF_SIZE,
-
- /* type trigger some action */
- BTC_SET_ACT_GET_BT_RSSI,
- BTC_SET_ACT_AGGREGATE_CTRL,
- BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
-
- /********* for 1Ant **********/
- /* type bool */
- BTC_SET_BL_BT_SCO_BUSY,
- /* type u1Byte */
- BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
- BTC_SET_U1_LPS_VAL,
- BTC_SET_U1_RPWM_VAL,
- BTC_SET_U1_1ANT_LPS,
- BTC_SET_U1_1ANT_RPWM,
- /* type trigger some action */
- BTC_SET_ACT_LEAVE_LPS,
- BTC_SET_ACT_ENTER_LPS,
- BTC_SET_ACT_NORMAL_LPS,
- BTC_SET_ACT_INC_FORCE_EXEC_PWR_CMD_CNT,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- BTC_SET_ACT_UPDATE_RAMASK,
- BTC_SET_ACT_SEND_MIMO_PS,
- /* BT Coex related */
- BTC_SET_ACT_CTRL_BT_INFO,
- BTC_SET_ACT_CTRL_BT_COEX,
- BTC_SET_ACT_CTRL_8723B_ANT,
- /***************************/
- BTC_SET_MAX
-};
-
-enum btc_dbg_disp_type {
- BTC_DBG_DISP_COEX_STATISTICS = 0x0,
- BTC_DBG_DISP_BT_LINK_INFO = 0x1,
- BTC_DBG_DISP_BT_FW_VER = 0x2,
- BTC_DBG_DISP_FW_PWR_MODE_CMD = 0x3,
- BTC_DBG_DISP_WIFI_STATUS = 0x04,
- BTC_DBG_DISP_MAX
-};
-
-enum btc_notify_type_ips {
- BTC_IPS_LEAVE = 0x0,
- BTC_IPS_ENTER = 0x1,
- BTC_IPS_MAX
-};
-
-enum btc_notify_type_lps {
- BTC_LPS_DISABLE = 0x0,
- BTC_LPS_ENABLE = 0x1,
- BTC_LPS_MAX
-};
-
-enum btc_notify_type_scan {
- BTC_SCAN_FINISH = 0x0,
- BTC_SCAN_START = 0x1,
- BTC_SCAN_START_2G = 0x2,
- BTC_SCAN_MAX
-};
-
-enum btc_notify_type_switchband {
- BTC_NOT_SWITCH = 0x0,
- BTC_SWITCH_TO_24G = 0x1,
- BTC_SWITCH_TO_5G = 0x2,
- BTC_SWITCH_TO_24G_NOFORSCAN = 0x3,
- BTC_SWITCH_MAX
-};
-
-enum btc_notify_type_associate {
- BTC_ASSOCIATE_FINISH = 0x0,
- BTC_ASSOCIATE_START = 0x1,
- BTC_ASSOCIATE_5G_FINISH = 0x2,
- BTC_ASSOCIATE_5G_START = 0x3,
- BTC_ASSOCIATE_MAX
-};
-
-enum btc_notify_type_media_status {
- BTC_MEDIA_DISCONNECT = 0x0,
- BTC_MEDIA_CONNECT = 0x1,
- BTC_MEDIA_MAX
-};
-
-enum btc_notify_type_special_packet {
- BTC_PACKET_UNKNOWN = 0x0,
- BTC_PACKET_DHCP = 0x1,
- BTC_PACKET_ARP = 0x2,
- BTC_PACKET_EAPOL = 0x3,
- BTC_PACKET_MAX
-};
-
-enum hci_ext_bt_operation {
- HCI_BT_OP_NONE = 0x0,
- HCI_BT_OP_INQUIRY_START = 0x1,
- HCI_BT_OP_INQUIRY_FINISH = 0x2,
- HCI_BT_OP_PAGING_START = 0x3,
- HCI_BT_OP_PAGING_SUCCESS = 0x4,
- HCI_BT_OP_PAGING_UNSUCCESS = 0x5,
- HCI_BT_OP_PAIRING_START = 0x6,
- HCI_BT_OP_PAIRING_FINISH = 0x7,
- HCI_BT_OP_BT_DEV_ENABLE = 0x8,
- HCI_BT_OP_BT_DEV_DISABLE = 0x9,
- HCI_BT_OP_MAX
-};
-
-enum btc_notify_type_stack_operation {
- BTC_STACK_OP_NONE = 0x0,
- BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1,
- BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2,
- BTC_STACK_OP_MAX
-};
-
-typedef u8 (*bfp_btc_r1)(void *btc_context, u32 reg_addr);
-
-typedef u16 (*bfp_btc_r2)(void *btc_context, u32 reg_addr);
-
-typedef u32 (*bfp_btc_r4)(void *btc_context, u32 reg_addr);
-
-typedef void (*bfp_btc_w1)(void *btc_context, u32 reg_addr, u32 data);
-
-typedef void (*bfp_btc_w1_bit_mak)(void *btc_context, u32 reg_addr,
- u32 bit_mask, u8 data1b);
-
-typedef void (*bfp_btc_w2)(void *btc_context, u32 reg_addr, u16 data);
-
-typedef void (*bfp_btc_w4)(void *btc_context, u32 reg_addr, u32 data);
-
-typedef void (*bfp_btc_local_reg_w1)(void *btc_context, u32 reg_addr, u8 data);
-typedef void (*bfp_btc_wr_1byte_bit_mask)(void *btc_context, u32 reg_addr,
- u8 bit_mask, u8 data);
-
-typedef void (*bfp_btc_set_bb_reg)(void *btc_context, u32 reg_addr,
- u32 bit_mask, u32 data);
-
-typedef u32 (*bfp_btc_get_bb_reg)(void *btc_context, u32 reg_addr,
- u32 bit_mask);
-
-typedef void (*bfp_btc_set_rf_reg)(void *btc_context, u8 rf_path, u32 reg_addr,
- u32 bit_mask, u32 data);
-
-typedef u32 (*bfp_btc_get_rf_reg)(void *btc_context, u8 rf_path,
- u32 reg_addr, u32 bit_mask);
-
-typedef void (*bfp_btc_fill_h2c)(void *btc_context, u8 element_id,
- u32 cmd_len, u8 *cmd_buffer);
-
-typedef bool (*bfp_btc_get)(void *btcoexist, u8 get_type, void *out_buf);
-
-typedef bool (*bfp_btc_set)(void *btcoexist, u8 set_type, void *in_buf);
-
-typedef u32 (*bfp_btc_get_bt_coex_supported_feature)(void *btcoexist);
-
-typedef u32 (*bfp_btc_get_bt_coex_supported_version)(void *btcoexist);
-
-typedef u32 (*bfp_btc_get_bt_phydm_version)(void *btcoexist);
-
-typedef void (*bfp_btc_phydm_modify_ra_pcr_threshold)(void *btcoexist,
- u8 ra_offset_direction,
- u8 ra_threshold_offset);
-
-typedef u32 (*bfp_btc_phydm_query_phy_counter)(void *btcoexist,
- const char *info_type);
-
-typedef u8 (*bfp_btc_get_ant_det_val_from_bt)(void *btcoexist);
-
-typedef u8 (*bfp_btc_get_ble_scan_type_from_bt)(void *btcoexist);
-
-typedef u32 (*bfp_btc_get_ble_scan_para_from_bt)(void *btcoexist, u8 scan_type);
-
-typedef bool (*bfp_btc_get_bt_afh_map_from_bt)(void *btcoexist, u8 map_type,
- u8 *afh_map);
-
-typedef void (*bfp_btc_set_bt_reg)(void *btc_context, u8 reg_type, u32 offset,
- u32 value);
-typedef u32 (*bfp_btc_get_bt_reg)(void *btc_context, u8 reg_type, u32 offset);
-
-typedef void (*bfp_btc_disp_dbg_msg)(void *btcoexist, u8 disp_type,
- struct seq_file *m);
-
-struct btc_bt_info {
- bool bt_disabled;
- u8 rssi_adjust_for_agc_table_on;
- u8 rssi_adjust_for_1ant_coex_type;
- bool pre_bt_ctrl_agg_buf_size;
- bool bt_busy;
- u8 pre_agg_buf_size;
- u8 agg_buf_size;
- bool limited_dig;
- bool pre_reject_agg_pkt;
- bool reject_agg_pkt;
- bool bt_ctrl_buf_size;
- bool increase_scan_dev_num;
- bool miracast_plus_bt;
- bool bt_ctrl_agg_buf_size;
- bool bt_tx_rx_mask;
- u16 bt_hci_ver;
- u16 bt_real_fw_ver;
- u8 bt_fw_ver;
- u32 bt_get_fw_ver;
-
- bool bt_disable_low_pwr;
-
- /* the following is for 1Ant solution */
- bool bt_ctrl_lps;
- bool bt_pwr_save_mode;
- bool bt_lps_on;
- bool force_to_roam;
- u8 force_exec_pwr_cmd_cnt;
- u8 lps_val;
- u8 rpwm_val;
- u32 ra_mask;
-
- u32 afh_map_l;
- u32 afh_map_m;
- u16 afh_map_h;
- u32 bt_supported_feature;
- u32 bt_supported_version;
- u8 bt_ant_det_val;
- u8 bt_ble_scan_type;
- u32 bt_ble_scan_para;
-};
-
-struct btc_stack_info {
- bool profile_notified;
- u16 hci_version; /* stack hci version */
- u8 num_of_link;
- bool bt_link_exist;
- bool sco_exist;
- bool acl_exist;
- bool a2dp_exist;
- bool hid_exist;
- u8 num_of_hid;
- bool pan_exist;
- bool unknown_acl_exist;
- s8 min_bt_rssi;
-};
-
-struct btc_statistics {
- u32 cnt_bind;
- u32 cnt_init_hw_config;
- u32 cnt_init_coex_dm;
- u32 cnt_ips_notify;
- u32 cnt_lps_notify;
- u32 cnt_scan_notify;
- u32 cnt_connect_notify;
- u32 cnt_media_status_notify;
- u32 cnt_special_packet_notify;
- u32 cnt_bt_info_notify;
- u32 cnt_periodical;
- u32 cnt_coex_dm_switch;
- u32 cnt_stack_operation_notify;
- u32 cnt_dbg_ctrl;
- u32 cnt_pre_load_firmware;
- u32 cnt_power_on;
-};
-
-struct btc_bt_link_info {
- bool bt_link_exist;
- bool bt_hi_pri_link_exist;
- bool sco_exist;
- bool sco_only;
- bool a2dp_exist;
- bool a2dp_only;
- bool hid_exist;
- bool hid_only;
- bool pan_exist;
- bool pan_only;
- bool slave_role;
- bool acl_busy;
-};
-
-enum btc_antenna_pos {
- BTC_ANTENNA_AT_MAIN_PORT = 0x1,
- BTC_ANTENNA_AT_AUX_PORT = 0x2,
-};
-
-enum btc_mp_h2c_op_code {
- BT_OP_GET_BT_VERSION = 0,
- BT_OP_WRITE_REG_ADDR = 12,
- BT_OP_WRITE_REG_VALUE = 13,
- BT_OP_READ_REG = 17,
- BT_OP_GET_AFH_MAP_L = 30,
- BT_OP_GET_AFH_MAP_M = 31,
- BT_OP_GET_AFH_MAP_H = 32,
- BT_OP_GET_BT_COEX_SUPPORTED_FEATURE = 42,
- BT_OP_GET_BT_COEX_SUPPORTED_VERSION = 43,
- BT_OP_GET_BT_ANT_DET_VAL = 44,
- BT_OP_GET_BT_BLE_SCAN_PARA = 45,
- BT_OP_GET_BT_BLE_SCAN_TYPE = 46,
- BT_OP_MAX
-};
-
-enum btc_mp_h2c_req_num {
- /* 4 bits only */
- BT_SEQ_DONT_CARE = 0,
- BT_SEQ_GET_BT_VERSION = 0xE,
- BT_SEQ_GET_AFH_MAP_L = 0x5,
- BT_SEQ_GET_AFH_MAP_M = 0x6,
- BT_SEQ_GET_AFH_MAP_H = 0x9,
- BT_SEQ_GET_BT_COEX_SUPPORTED_FEATURE = 0x7,
- BT_SEQ_GET_BT_COEX_SUPPORTED_VERSION = 0x8,
- BT_SEQ_GET_BT_ANT_DET_VAL = 0x2,
- BT_SEQ_GET_BT_BLE_SCAN_PARA = 0x3,
- BT_SEQ_GET_BT_BLE_SCAN_TYPE = 0x4,
-};
-
-struct btc_coexist {
- /* make sure only one adapter can bind the data context */
- bool binded;
- /* default adapter */
- void *adapter;
- struct btc_board_info board_info;
- /* some bt info referenced by non-bt module */
- struct btc_bt_info bt_info;
- struct btc_stack_info stack_info;
- enum btc_chip_interface chip_interface;
- struct btc_bt_link_info bt_link_info;
-
- /* boolean variables to replace BT_AUTO_REPORT_ONLY_XXXXY_ZANT
- * configuration parameters
- */
- bool auto_report_1ant;
- bool auto_report_2ant;
- bool dbg_mode_1ant;
- bool dbg_mode_2ant;
- bool initilized;
- bool stop_coex_dm;
- bool manual_control;
- struct btc_statistics statistics;
- u8 pwr_mode_val[10];
-
- struct completion bt_mp_comp;
-
- /* function pointers - io related */
- bfp_btc_r1 btc_read_1byte;
- bfp_btc_w1 btc_write_1byte;
- bfp_btc_w1_bit_mak btc_write_1byte_bitmask;
- bfp_btc_r2 btc_read_2byte;
- bfp_btc_w2 btc_write_2byte;
- bfp_btc_r4 btc_read_4byte;
- bfp_btc_w4 btc_write_4byte;
- bfp_btc_local_reg_w1 btc_write_local_reg_1byte;
-
- bfp_btc_set_bb_reg btc_set_bb_reg;
- bfp_btc_get_bb_reg btc_get_bb_reg;
-
- bfp_btc_set_rf_reg btc_set_rf_reg;
- bfp_btc_get_rf_reg btc_get_rf_reg;
-
- bfp_btc_fill_h2c btc_fill_h2c;
-
- bfp_btc_disp_dbg_msg btc_disp_dbg_msg;
-
- bfp_btc_get btc_get;
- bfp_btc_set btc_set;
-
- bfp_btc_set_bt_reg btc_set_bt_reg;
- bfp_btc_get_bt_reg btc_get_bt_reg;
-
- bfp_btc_get_bt_coex_supported_feature btc_get_bt_coex_supported_feature;
- bfp_btc_get_bt_coex_supported_version btc_get_bt_coex_supported_version;
- bfp_btc_get_bt_phydm_version btc_get_bt_phydm_version;
- bfp_btc_phydm_modify_ra_pcr_threshold btc_phydm_modify_ra_pcr_threshold;
- bfp_btc_phydm_query_phy_counter btc_phydm_query_phy_counter;
- bfp_btc_get_ant_det_val_from_bt btc_get_ant_det_val_from_bt;
- bfp_btc_get_ble_scan_type_from_bt btc_get_ble_scan_type_from_bt;
- bfp_btc_get_ble_scan_para_from_bt btc_get_ble_scan_para_from_bt;
- bfp_btc_get_bt_afh_map_from_bt btc_get_bt_afh_map_from_bt;
-
-};
-
-bool halbtc_is_wifi_uplink(struct rtl_priv *adapter);
-
-#define rtl_btc_coexist(rtlpriv) \
- ((struct btc_coexist *)((rtlpriv)->btcoexist.btc_context))
-#define rtl_btc_wifi_only(rtlpriv) \
- ((struct wifi_only_cfg *)((rtlpriv)->btcoexist.wifi_only_context))
-
-struct wifi_only_cfg;
-
-bool exhalbtc_initlize_variables(struct rtl_priv *rtlpriv);
-bool exhalbtc_initlize_variables_wifi_only(struct rtl_priv *rtlpriv);
-bool exhalbtc_bind_bt_coex_withadapter(void *adapter);
-void exhalbtc_power_on_setting(struct btc_coexist *btcoexist);
-void exhalbtc_pre_load_firmware(struct btc_coexist *btcoexist);
-void exhalbtc_init_hw_config(struct btc_coexist *btcoexist, bool wifi_only);
-void exhalbtc_init_hw_config_wifi_only(struct wifi_only_cfg *wifionly_cfg);
-void exhalbtc_init_coex_dm(struct btc_coexist *btcoexist);
-void exhalbtc_ips_notify(struct btc_coexist *btcoexist, u8 type);
-void exhalbtc_lps_notify(struct btc_coexist *btcoexist, u8 type);
-void exhalbtc_scan_notify(struct btc_coexist *btcoexist, u8 type);
-void exhalbtc_scan_notify_wifi_only(struct wifi_only_cfg *wifionly_cfg,
- u8 is_5g);
-void exhalbtc_connect_notify(struct btc_coexist *btcoexist, u8 action);
-void exhalbtc_mediastatus_notify(struct btc_coexist *btcoexist,
- enum rt_media_status media_status);
-void exhalbtc_special_packet_notify(struct btc_coexist *btcoexist, u8 pkt_type);
-void exhalbtc_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
- u8 length);
-void exhalbtc_rf_status_notify(struct btc_coexist *btcoexist, u8 type);
-void exhalbtc_stack_operation_notify(struct btc_coexist *btcoexist, u8 type);
-void exhalbtc_halt_notify(struct btc_coexist *btcoexist);
-void exhalbtc_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state);
-void exhalbtc_coex_dm_switch(struct btc_coexist *btcoexist);
-void exhalbtc_periodical(struct btc_coexist *btcoexist);
-void exhalbtc_dbg_control(struct btc_coexist *btcoexist, u8 code, u8 len,
- u8 *data);
-void exhalbtc_antenna_detection(struct btc_coexist *btcoexist, u32 cent_freq,
- u32 offset, u32 span, u32 seconds);
-void exhalbtc_stack_update_profile_info(void);
-void exhalbtc_set_hci_version(struct btc_coexist *btcoexist, u16 hci_version);
-void exhalbtc_set_bt_patch_version(struct btc_coexist *btcoexist,
- u16 bt_hci_version, u16 bt_patch_version);
-void exhalbtc_update_min_bt_rssi(struct btc_coexist *btcoexist, s8 bt_rssi);
-void exhalbtc_set_bt_exist(struct btc_coexist *btcoexist, bool bt_exist);
-void exhalbtc_set_chip_type(struct btc_coexist *btcoexist, u8 chip_type);
-void exhalbtc_set_ant_num(struct rtl_priv *rtlpriv, u8 type, u8 ant_num);
-void exhalbtc_display_bt_coex_info(struct btc_coexist *btcoexist,
- struct seq_file *m);
-void exhalbtc_switch_band_notify(struct btc_coexist *btcoexist, u8 type);
-void exhalbtc_switch_band_notify_wifi_only(struct wifi_only_cfg *wifionly_cfg,
- u8 is_5g);
-void exhalbtc_signal_compensation(struct btc_coexist *btcoexist,
- u8 *rssi_wifi, u8 *rssi_bt);
-void exhalbtc_lps_leave(struct btc_coexist *btcoexist);
-void exhalbtc_low_wifi_traffic_notify(struct btc_coexist *btcoexist);
-void exhalbtc_set_single_ant_path(struct btc_coexist *btcoexist,
- u8 single_ant_path);
-
-/* The following are used by wifi_only case */
-enum wifionly_chip_interface {
- WIFIONLY_INTF_UNKNOWN = 0,
- WIFIONLY_INTF_PCI = 1,
- WIFIONLY_INTF_USB = 2,
- WIFIONLY_INTF_SDIO = 3,
- WIFIONLY_INTF_MAX
-};
-
-enum wifionly_customer_id {
- CUSTOMER_NORMAL = 0,
- CUSTOMER_HP_1 = 1,
-};
-
-struct wifi_only_haldata {
- u16 customer_id;
- u8 efuse_pg_antnum;
- u8 efuse_pg_antpath;
- u8 rfe_type;
- u8 ant_div_cfg;
-};
-
-struct wifi_only_cfg {
- void *adapter;
- struct wifi_only_haldata haldata_info;
- enum wifionly_chip_interface chip_interface;
-};
-
-static inline
-void halwifionly_phy_set_bb_reg(struct wifi_only_cfg *wifi_conly_cfg,
- u32 regaddr, u32 bitmask, u32 data)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)wifi_conly_cfg->adapter;
-
- rtl_set_bbreg(rtlpriv->hw, regaddr, bitmask, data);
-}
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2013 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "../wifi.h"
-#include <linux/vmalloc.h>
-#include <linux/module.h>
-
-#include "rtl_btc.h"
-#include "halbt_precomp.h"
-
-static struct rtl_btc_ops rtl_btc_operation = {
- .btc_init_variables = rtl_btc_init_variables,
- .btc_init_variables_wifi_only = rtl_btc_init_variables_wifi_only,
- .btc_deinit_variables = rtl_btc_deinit_variables,
- .btc_init_hal_vars = rtl_btc_init_hal_vars,
- .btc_power_on_setting = rtl_btc_power_on_setting,
- .btc_init_hw_config = rtl_btc_init_hw_config,
- .btc_init_hw_config_wifi_only = rtl_btc_init_hw_config_wifi_only,
- .btc_ips_notify = rtl_btc_ips_notify,
- .btc_lps_notify = rtl_btc_lps_notify,
- .btc_scan_notify = rtl_btc_scan_notify,
- .btc_scan_notify_wifi_only = rtl_btc_scan_notify_wifi_only,
- .btc_connect_notify = rtl_btc_connect_notify,
- .btc_mediastatus_notify = rtl_btc_mediastatus_notify,
- .btc_periodical = rtl_btc_periodical,
- .btc_halt_notify = rtl_btc_halt_notify,
- .btc_btinfo_notify = rtl_btc_btinfo_notify,
- .btc_btmpinfo_notify = rtl_btc_btmpinfo_notify,
- .btc_is_limited_dig = rtl_btc_is_limited_dig,
- .btc_is_disable_edca_turbo = rtl_btc_is_disable_edca_turbo,
- .btc_is_bt_disabled = rtl_btc_is_bt_disabled,
- .btc_special_packet_notify = rtl_btc_special_packet_notify,
- .btc_switch_band_notify = rtl_btc_switch_band_notify,
- .btc_switch_band_notify_wifi_only = rtl_btc_switch_band_notify_wifionly,
- .btc_record_pwr_mode = rtl_btc_record_pwr_mode,
- .btc_get_lps_val = rtl_btc_get_lps_val,
- .btc_get_rpwm_val = rtl_btc_get_rpwm_val,
- .btc_is_bt_ctrl_lps = rtl_btc_is_bt_ctrl_lps,
- .btc_is_bt_lps_on = rtl_btc_is_bt_lps_on,
- .btc_get_ampdu_cfg = rtl_btc_get_ampdu_cfg,
- .btc_display_bt_coex_info = rtl_btc_display_bt_coex_info,
-};
-
-void rtl_btc_display_bt_coex_info(struct rtl_priv *rtlpriv, struct seq_file *m)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist) {
- seq_puts(m, "btc_coexist context is NULL!\n");
- return;
- }
-
- exhalbtc_display_bt_coex_info(btcoexist, m);
-}
-
-void rtl_btc_record_pwr_mode(struct rtl_priv *rtlpriv, u8 *buf, u8 len)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
- u8 safe_len;
-
- if (!btcoexist)
- return;
-
- safe_len = sizeof(btcoexist->pwr_mode_val);
-
- if (safe_len > len)
- safe_len = len;
-
- memcpy(btcoexist->pwr_mode_val, buf, safe_len);
-}
-
-u8 rtl_btc_get_lps_val(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return 0;
-
- return btcoexist->bt_info.lps_val;
-}
-
-u8 rtl_btc_get_rpwm_val(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return 0;
-
- return btcoexist->bt_info.rpwm_val;
-}
-
-bool rtl_btc_is_bt_ctrl_lps(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return false;
-
- return btcoexist->bt_info.bt_ctrl_lps;
-}
-
-bool rtl_btc_is_bt_lps_on(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return false;
-
- return btcoexist->bt_info.bt_lps_on;
-}
-
-void rtl_btc_get_ampdu_cfg(struct rtl_priv *rtlpriv, u8 *reject_agg,
- u8 *ctrl_agg_size, u8 *agg_size)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist) {
- *reject_agg = false;
- *ctrl_agg_size = false;
- return;
- }
-
- if (reject_agg)
- *reject_agg = btcoexist->bt_info.reject_agg_pkt;
- if (ctrl_agg_size)
- *ctrl_agg_size = btcoexist->bt_info.bt_ctrl_agg_buf_size;
- if (agg_size)
- *agg_size = btcoexist->bt_info.agg_buf_size;
-}
-
-static void rtl_btc_alloc_variable(struct rtl_priv *rtlpriv, bool wifi_only)
-{
- if (wifi_only)
- rtlpriv->btcoexist.wifi_only_context =
- kzalloc(sizeof(struct wifi_only_cfg), GFP_KERNEL);
- else
- rtlpriv->btcoexist.btc_context =
- kzalloc(sizeof(struct btc_coexist), GFP_KERNEL);
-}
-
-static void rtl_btc_free_variable(struct rtl_priv *rtlpriv)
-{
- kfree(rtlpriv->btcoexist.btc_context);
- rtlpriv->btcoexist.btc_context = NULL;
-
- kfree(rtlpriv->btcoexist.wifi_only_context);
- rtlpriv->btcoexist.wifi_only_context = NULL;
-}
-
-void rtl_btc_init_variables(struct rtl_priv *rtlpriv)
-{
- rtl_btc_alloc_variable(rtlpriv, false);
-
- exhalbtc_initlize_variables(rtlpriv);
- exhalbtc_bind_bt_coex_withadapter(rtlpriv);
-}
-
-void rtl_btc_init_variables_wifi_only(struct rtl_priv *rtlpriv)
-{
- rtl_btc_alloc_variable(rtlpriv, true);
-
- exhalbtc_initlize_variables_wifi_only(rtlpriv);
-}
-
-void rtl_btc_deinit_variables(struct rtl_priv *rtlpriv)
-{
- rtl_btc_free_variable(rtlpriv);
-}
-
-void rtl_btc_init_hal_vars(struct rtl_priv *rtlpriv)
-{
- /* move ant_num, bt_type and single_ant_path to
- * exhalbtc_bind_bt_coex_withadapter()
- */
-}
-
-void rtl_btc_power_on_setting(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- exhalbtc_power_on_setting(btcoexist);
-}
-
-void rtl_btc_init_hw_config(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- u8 bt_exist;
-
- bt_exist = rtl_get_hwpg_bt_exist(rtlpriv);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "%s, bt_exist is %d\n", __func__, bt_exist);
-
- if (!btcoexist)
- return;
-
- exhalbtc_init_hw_config(btcoexist, !bt_exist);
- exhalbtc_init_coex_dm(btcoexist);
-}
-
-void rtl_btc_init_hw_config_wifi_only(struct rtl_priv *rtlpriv)
-{
- struct wifi_only_cfg *wifionly_cfg = rtl_btc_wifi_only(rtlpriv);
-
- if (!wifionly_cfg)
- return;
-
- exhalbtc_init_hw_config_wifi_only(wifionly_cfg);
-}
-
-void rtl_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- exhalbtc_ips_notify(btcoexist, type);
-
- if (type == ERFON) {
- /*
- * In some situation, it doesn't scan after leaving IPS, and
- * this will cause btcoex in wrong state.
- */
- exhalbtc_scan_notify(btcoexist, 1);
- exhalbtc_scan_notify(btcoexist, 0);
- }
-}
-
-void rtl_btc_lps_notify(struct rtl_priv *rtlpriv, u8 type)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- exhalbtc_lps_notify(btcoexist, type);
-}
-
-void rtl_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- exhalbtc_scan_notify(btcoexist, scantype);
-}
-
-void rtl_btc_scan_notify_wifi_only(struct rtl_priv *rtlpriv, u8 scantype)
-{
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- struct wifi_only_cfg *wifionly_cfg = rtl_btc_wifi_only(rtlpriv);
- u8 is_5g = (rtlhal->current_bandtype == BAND_ON_5G);
-
- if (!wifionly_cfg)
- return;
-
- exhalbtc_scan_notify_wifi_only(wifionly_cfg, is_5g);
-}
-
-void rtl_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- exhalbtc_connect_notify(btcoexist, action);
-}
-
-void rtl_btc_mediastatus_notify(struct rtl_priv *rtlpriv,
- enum rt_media_status mstatus)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- exhalbtc_mediastatus_notify(btcoexist, mstatus);
-}
-
-void rtl_btc_periodical(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- /*rtl_bt_dm_monitor();*/
- exhalbtc_periodical(btcoexist);
-}
-
-void rtl_btc_halt_notify(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- exhalbtc_halt_notify(btcoexist);
-}
-
-void rtl_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 *tmp_buf, u8 length)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- exhalbtc_bt_info_notify(btcoexist, tmp_buf, length);
-}
-
-void rtl_btc_btmpinfo_notify(struct rtl_priv *rtlpriv, u8 *tmp_buf, u8 length)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
- u8 extid, seq, len;
- u16 bt_real_fw_ver;
- u8 bt_fw_ver;
- u8 *data;
-
- if (!btcoexist)
- return;
-
- if ((length < 4) || (!tmp_buf))
- return;
-
- extid = tmp_buf[0];
- /* not response from BT FW then exit*/
- if (extid != 1) /* C2H_TRIG_BY_BT_FW = 1 */
- return;
-
- len = tmp_buf[1] >> 4;
- seq = tmp_buf[2] >> 4;
- data = &tmp_buf[3];
-
- /* BT Firmware version response */
- switch (seq) {
- case BT_SEQ_GET_BT_VERSION:
- bt_real_fw_ver = tmp_buf[3] | (tmp_buf[4] << 8);
- bt_fw_ver = tmp_buf[5];
-
- btcoexist->bt_info.bt_real_fw_ver = bt_real_fw_ver;
- btcoexist->bt_info.bt_fw_ver = bt_fw_ver;
- break;
- case BT_SEQ_GET_AFH_MAP_L:
- btcoexist->bt_info.afh_map_l = le32_to_cpu(*(__le32 *)data);
- break;
- case BT_SEQ_GET_AFH_MAP_M:
- btcoexist->bt_info.afh_map_m = le32_to_cpu(*(__le32 *)data);
- break;
- case BT_SEQ_GET_AFH_MAP_H:
- btcoexist->bt_info.afh_map_h = le16_to_cpu(*(__le16 *)data);
- break;
- case BT_SEQ_GET_BT_COEX_SUPPORTED_FEATURE:
- btcoexist->bt_info.bt_supported_feature = tmp_buf[3] |
- (tmp_buf[4] << 8);
- break;
- case BT_SEQ_GET_BT_COEX_SUPPORTED_VERSION:
- btcoexist->bt_info.bt_supported_version = tmp_buf[3] |
- (tmp_buf[4] << 8);
- break;
- case BT_SEQ_GET_BT_ANT_DET_VAL:
- btcoexist->bt_info.bt_ant_det_val = tmp_buf[3];
- break;
- case BT_SEQ_GET_BT_BLE_SCAN_PARA:
- btcoexist->bt_info.bt_ble_scan_para = tmp_buf[3] |
- (tmp_buf[4] << 8) |
- (tmp_buf[5] << 16) |
- (tmp_buf[6] << 24);
- break;
- case BT_SEQ_GET_BT_BLE_SCAN_TYPE:
- btcoexist->bt_info.bt_ble_scan_type = tmp_buf[3];
- break;
- }
-
- RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
- "btmpinfo complete req_num=%d\n", seq);
-
- complete(&btcoexist->bt_mp_comp);
-}
-
-bool rtl_btc_is_limited_dig(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return false;
-
- return btcoexist->bt_info.limited_dig;
-}
-
-bool rtl_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv)
-{
- bool bt_change_edca = false;
- u32 cur_edca_val;
- u32 edca_bt_hs_uplink = 0x5ea42b, edca_bt_hs_downlink = 0x5ea42b;
- u32 edca_hs;
- u32 edca_addr = 0x504;
-
- cur_edca_val = rtl_read_dword(rtlpriv, edca_addr);
- if (halbtc_is_wifi_uplink(rtlpriv)) {
- if (cur_edca_val != edca_bt_hs_uplink) {
- edca_hs = edca_bt_hs_uplink;
- bt_change_edca = true;
- }
- } else {
- if (cur_edca_val != edca_bt_hs_downlink) {
- edca_hs = edca_bt_hs_downlink;
- bt_change_edca = true;
- }
- }
-
- if (bt_change_edca)
- rtl_write_dword(rtlpriv, edca_addr, edca_hs);
-
- return true;
-}
-
-bool rtl_btc_is_bt_disabled(struct rtl_priv *rtlpriv)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return true;
-
- /* It seems 'bt_disabled' is never be initialized or set. */
- if (btcoexist->bt_info.bt_disabled)
- return true;
- else
- return false;
-}
-
-void rtl_btc_special_packet_notify(struct rtl_priv *rtlpriv, u8 pkt_type)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
-
- if (!btcoexist)
- return;
-
- return exhalbtc_special_packet_notify(btcoexist, pkt_type);
-}
-
-void rtl_btc_switch_band_notify(struct rtl_priv *rtlpriv, u8 band_type,
- bool scanning)
-{
- struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
- u8 type = BTC_NOT_SWITCH;
-
- if (!btcoexist)
- return;
-
- switch (band_type) {
- case BAND_ON_2_4G:
- if (scanning)
- type = BTC_SWITCH_TO_24G;
- else
- type = BTC_SWITCH_TO_24G_NOFORSCAN;
- break;
-
- case BAND_ON_5G:
- type = BTC_SWITCH_TO_5G;
- break;
- }
-
- if (type != BTC_NOT_SWITCH)
- exhalbtc_switch_band_notify(btcoexist, type);
-}
-
-void rtl_btc_switch_band_notify_wifionly(struct rtl_priv *rtlpriv, u8 band_type,
- bool scanning)
-{
- struct wifi_only_cfg *wifionly_cfg = rtl_btc_wifi_only(rtlpriv);
- u8 is_5g = (band_type == BAND_ON_5G);
-
- if (!wifionly_cfg)
- return;
-
- exhalbtc_switch_band_notify_wifi_only(wifionly_cfg, is_5g);
-}
-
-struct rtl_btc_ops *rtl_btc_get_ops_pointer(void)
-{
- return &rtl_btc_operation;
-}
-
-enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- enum rt_media_status m_status = RT_MEDIA_DISCONNECT;
-
- u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0;
-
- if (bibss || rtlpriv->mac80211.link_state >= MAC80211_LINKED)
- m_status = RT_MEDIA_CONNECT;
-
- return m_status;
-}
-
-u8 rtl_get_hwpg_bt_exist(struct rtl_priv *rtlpriv)
-{
- return rtlpriv->btcoexist.btc_info.btcoexist;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2010 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_BTC_H__
-#define __RTL_BTC_H__
-
-#include "halbt_precomp.h"
-
-void rtl_btc_init_variables(struct rtl_priv *rtlpriv);
-void rtl_btc_init_variables_wifi_only(struct rtl_priv *rtlpriv);
-void rtl_btc_deinit_variables(struct rtl_priv *rtlpriv);
-void rtl_btc_init_hal_vars(struct rtl_priv *rtlpriv);
-void rtl_btc_power_on_setting(struct rtl_priv *rtlpriv);
-void rtl_btc_init_hw_config(struct rtl_priv *rtlpriv);
-void rtl_btc_init_hw_config_wifi_only(struct rtl_priv *rtlpriv);
-void rtl_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type);
-void rtl_btc_lps_notify(struct rtl_priv *rtlpriv, u8 type);
-void rtl_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype);
-void rtl_btc_scan_notify_wifi_only(struct rtl_priv *rtlpriv, u8 scantype);
-void rtl_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action);
-void rtl_btc_mediastatus_notify(struct rtl_priv *rtlpriv,
- enum rt_media_status mstatus);
-void rtl_btc_periodical(struct rtl_priv *rtlpriv);
-void rtl_btc_halt_notify(struct rtl_priv *rtlpriv);
-void rtl_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 *tmpbuf, u8 length);
-void rtl_btc_btmpinfo_notify(struct rtl_priv *rtlpriv, u8 *tmp_buf, u8 length);
-bool rtl_btc_is_limited_dig(struct rtl_priv *rtlpriv);
-bool rtl_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv);
-bool rtl_btc_is_bt_disabled(struct rtl_priv *rtlpriv);
-void rtl_btc_special_packet_notify(struct rtl_priv *rtlpriv, u8 pkt_type);
-void rtl_btc_switch_band_notify(struct rtl_priv *rtlpriv, u8 band_type,
- bool scanning);
-void rtl_btc_switch_band_notify_wifionly(struct rtl_priv *rtlpriv, u8 band_type,
- bool scanning);
-void rtl_btc_display_bt_coex_info(struct rtl_priv *rtlpriv, struct seq_file *m);
-void rtl_btc_record_pwr_mode(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
-u8 rtl_btc_get_lps_val(struct rtl_priv *rtlpriv);
-u8 rtl_btc_get_rpwm_val(struct rtl_priv *rtlpriv);
-bool rtl_btc_is_bt_ctrl_lps(struct rtl_priv *rtlpriv);
-bool rtl_btc_is_bt_lps_on(struct rtl_priv *rtlpriv);
-void rtl_btc_get_ampdu_cfg(struct rtl_priv *rtlpriv, u8 *reject_agg,
- u8 *ctrl_agg_size, u8 *agg_size);
-
-struct rtl_btc_ops *rtl_btc_get_ops_pointer(void);
-
-u8 rtl_get_hwpg_bt_exist(struct rtl_priv *rtlpriv);
-u8 rtl_get_hwpg_bt_type(struct rtl_priv *rtlpriv);
-u8 rtl_get_hwpg_ant_num(struct rtl_priv *rtlpriv);
-u8 rtl_get_hwpg_single_ant_path(struct rtl_priv *rtlpriv);
-u8 rtl_get_hwpg_package_type(struct rtl_priv *rtlpriv);
-
-enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "wifi.h"
-#include "cam.h"
-#include <linux/export.h>
-
-void rtl_cam_reset_sec_info(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtlpriv->sec.use_defaultkey = false;
- rtlpriv->sec.pairwise_enc_algorithm = NO_ENCRYPTION;
- rtlpriv->sec.group_enc_algorithm = NO_ENCRYPTION;
- memset(rtlpriv->sec.key_buf, 0, KEY_BUF_SIZE * MAX_KEY_LEN);
- memset(rtlpriv->sec.key_len, 0, KEY_BUF_SIZE);
- rtlpriv->sec.pairwise_key = NULL;
-}
-
-static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no,
- u8 *mac_addr, u8 *key_cont_128, u16 us_config)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- u32 target_command;
- u32 target_content = 0;
- int entry_i;
-
- RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_DMESG, "Key content :",
- key_cont_128, 16);
-
- /* 0-1 config + mac, 2-5 fill 128key,6-7 are reserved */
- for (entry_i = CAM_CONTENT_COUNT - 1; entry_i >= 0; entry_i--) {
- target_command = entry_i + CAM_CONTENT_COUNT * entry_no;
- target_command = target_command | BIT(31) | BIT(16);
-
- if (entry_i == 0) {
- target_content = (u32)(*(mac_addr + 0)) << 16 |
- (u32)(*(mac_addr + 1)) << 24 |
- (u32)us_config;
-
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
- target_content);
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
- target_command);
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "WRITE %x: %x\n",
- rtlpriv->cfg->maps[WCAMI], target_content);
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "The Key ID is %d\n", entry_no);
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "WRITE %x: %x\n",
- rtlpriv->cfg->maps[RWCAM], target_command);
-
- } else if (entry_i == 1) {
- target_content = (u32)(*(mac_addr + 5)) << 24 |
- (u32)(*(mac_addr + 4)) << 16 |
- (u32)(*(mac_addr + 3)) << 8 |
- (u32)(*(mac_addr + 2));
-
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
- target_content);
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
- target_command);
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "WRITE A4: %x\n", target_content);
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "WRITE A0: %x\n", target_command);
- } else {
- target_content =
- (u32)(*(key_cont_128 + (entry_i * 4 - 8) + 3)) <<
- 24 | (u32)(*(key_cont_128 + (entry_i * 4 - 8) + 2))
- << 16 |
- (u32)(*(key_cont_128 + (entry_i * 4 - 8) + 1)) << 8
- | (u32)(*(key_cont_128 + (entry_i * 4 - 8) + 0));
-
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
- target_content);
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
- target_command);
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "WRITE A4: %x\n", target_content);
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "WRITE A0: %x\n", target_command);
- }
- }
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "after set key, usconfig:%x\n", us_config);
-}
-
-u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
- u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
- u32 ul_default_key, u8 *key_content)
-{
- u32 us_config;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, ulUseDK=%x MacAddr %pM\n",
- ul_entry_idx, ul_key_id, ul_enc_alg,
- ul_default_key, mac_addr);
-
- if (ul_key_id == TOTAL_CAM_ENTRY) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "ulKeyId exceed!\n");
- return 0;
- }
-
- if (ul_default_key == 1)
- us_config = CFG_VALID | ((u16)(ul_enc_alg) << 2);
- else
- us_config = CFG_VALID | ((ul_enc_alg) << 2) | ul_key_id;
-
- rtl_cam_program_entry(hw, ul_entry_idx, mac_addr,
- (u8 *)key_content, us_config);
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "end\n");
-
- return 1;
-}
-
-int rtl_cam_delete_one_entry(struct ieee80211_hw *hw,
- u8 *mac_addr, u32 ul_key_id)
-{
- u32 ul_command;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "key_idx:%d\n", ul_key_id);
-
- ul_command = ul_key_id * CAM_CONTENT_COUNT;
- ul_command = ul_command | BIT(31) | BIT(16);
-
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], 0);
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "%s(): WRITE A4: %x\n", __func__, 0);
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "%s(): WRITE A0: %x\n", __func__, ul_command);
-
- return 0;
-}
-
-void rtl_cam_reset_all_entry(struct ieee80211_hw *hw)
-{
- u32 ul_command;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- ul_command = BIT(31) | BIT(30);
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
-}
-
-void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- u32 ul_command;
- u32 ul_content;
- u32 ul_enc_algo;
-
- switch (rtlpriv->sec.pairwise_enc_algorithm) {
- case WEP40_ENCRYPTION:
- ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
- break;
- case WEP104_ENCRYPTION:
- ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
- break;
- case TKIP_ENCRYPTION:
- ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
- break;
- case AESCCMP_ENCRYPTION:
- ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
- break;
- default:
- ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
- }
-
- ul_content = (uc_index & 3) | ((u16)(ul_enc_algo) << 2);
-
- ul_content |= BIT(15);
- ul_command = CAM_CONTENT_COUNT * uc_index;
- ul_command = ul_command | BIT(31) | BIT(16);
-
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "%s(): WRITE A4: %x\n", __func__, ul_content);
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "%s(): WRITE A0: %x\n", __func__, ul_command);
-}
-
-void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- u32 ul_command;
- u32 ul_content;
- u32 ul_encalgo;
- u8 entry_i;
-
- switch (rtlpriv->sec.pairwise_enc_algorithm) {
- case WEP40_ENCRYPTION:
- ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
- break;
- case WEP104_ENCRYPTION:
- ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
- break;
- case TKIP_ENCRYPTION:
- ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
- break;
- case AESCCMP_ENCRYPTION:
- ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
- break;
- default:
- ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
- }
-
- for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
- if (entry_i == 0) {
- ul_content =
- (uc_index & 0x03) | ((u16)(ul_encalgo) << 2);
- ul_content |= BIT(15);
- } else {
- ul_content = 0;
- }
-
- ul_command = CAM_CONTENT_COUNT * uc_index + entry_i;
- ul_command = ul_command | BIT(31) | BIT(16);
-
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "%s(): WRITE A4: %x\n", __func__, ul_content);
- RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
- "%s(): WRITE A0: %x\n", __func__, ul_command);
- }
-}
-
-u8 rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u32 bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> 4;
- u8 entry_idx = 0;
- u8 i, *addr;
-
- if (!sta_addr) {
- pr_err("sta_addr is NULL.\n");
- return TOTAL_CAM_ENTRY;
- }
- /* Does STA already exist? */
- for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
- addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
- if (ether_addr_equal_unaligned(addr, sta_addr))
- return i;
- }
- /* Get a free CAM entry. */
- for (entry_idx = 4; entry_idx < TOTAL_CAM_ENTRY; entry_idx++) {
- if ((bitmap & BIT(0)) == 0) {
- pr_err("-----hwsec_cam_bitmap: 0x%x entry_idx=%d\n",
- rtlpriv->sec.hwsec_cam_bitmap, entry_idx);
- rtlpriv->sec.hwsec_cam_bitmap |= BIT(0) << entry_idx;
- memcpy(rtlpriv->sec.hwsec_cam_sta_addr[entry_idx],
- sta_addr, ETH_ALEN);
- return entry_idx;
- }
- bitmap = bitmap >> 1;
- }
- return TOTAL_CAM_ENTRY;
-}
-
-void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u32 bitmap;
- u8 i, *addr;
-
- if (!sta_addr) {
- pr_err("sta_addr is NULL.\n");
- return;
- }
-
- if (is_zero_ether_addr(sta_addr)) {
- pr_err("sta_addr is %pM\n", sta_addr);
- return;
- }
- /* Does STA already exist? */
- for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
- addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
- bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> i;
- if (((bitmap & BIT(0)) == BIT(0)) &&
- (ether_addr_equal_unaligned(addr, sta_addr))) {
- /* Remove from HW Security CAM */
- eth_zero_addr(rtlpriv->sec.hwsec_cam_sta_addr[i]);
- rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i);
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "&&&&&&&&&del entry %d\n", i);
- }
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_CAM_H_
-#define __RTL_CAM_H_
-
-#define CAM_CONTENT_COUNT 8
-
-#define CFG_VALID BIT(15)
-
-#define PAIRWISE_KEYIDX 0
-#define CAM_PAIRWISE_KEY_POSITION 4
-
-#define CAM_CONFIG_NO_USEDK 0
-
-void rtl_cam_reset_all_entry(struct ieee80211_hw *hw);
-u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
- u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
- u32 ul_default_key, u8 *key_content);
-int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
- u32 ul_key_id);
-void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index);
-void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index);
-void rtl_cam_reset_sec_info(struct ieee80211_hw *hw);
-u8 rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr);
-void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "wifi.h"
-#include "core.h"
-#include "cam.h"
-#include "base.h"
-#include "ps.h"
-#include "pwrseqcmd.h"
-
-#include "btcoexist/rtl_btc.h"
-#include <linux/firmware.h>
-#include <linux/export.h>
-#include <net/cfg80211.h>
-
-u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
- 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
- 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
- 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
- 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
- 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
- 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
- 165, 167, 169, 171, 173, 175, 177 /* Band 4 */
-};
-
-u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
- 42, 58, 106, 122, 138, 155, 171
-};
-
-static void rtl_fw_do_work(const struct firmware *firmware, void *context,
- bool is_wow)
-{
- struct ieee80211_hw *hw = context;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- int err;
-
- RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
- "Firmware callback routine entered!\n");
- complete(&rtlpriv->firmware_loading_complete);
- if (!firmware) {
- if (rtlpriv->cfg->alt_fw_name) {
- err = request_firmware(&firmware,
- rtlpriv->cfg->alt_fw_name,
- rtlpriv->io.dev);
- pr_info("Loading alternative firmware %s\n",
- rtlpriv->cfg->alt_fw_name);
- if (!err)
- goto found_alt;
- }
- pr_err("Selected firmware is not available\n");
- rtlpriv->max_fw_size = 0;
- return;
- }
-found_alt:
- if (firmware->size > rtlpriv->max_fw_size) {
- pr_err("Firmware is too big!\n");
- release_firmware(firmware);
- return;
- }
- if (!is_wow) {
- memcpy(rtlpriv->rtlhal.pfirmware, firmware->data,
- firmware->size);
- rtlpriv->rtlhal.fwsize = firmware->size;
- } else {
- memcpy(rtlpriv->rtlhal.wowlan_firmware, firmware->data,
- firmware->size);
- rtlpriv->rtlhal.wowlan_fwsize = firmware->size;
- }
- rtlpriv->rtlhal.fwsize = firmware->size;
- release_firmware(firmware);
-}
-
-void rtl_fw_cb(const struct firmware *firmware, void *context)
-{
- rtl_fw_do_work(firmware, context, false);
-}
-
-void rtl_wowlan_fw_cb(const struct firmware *firmware, void *context)
-{
- rtl_fw_do_work(firmware, context, true);
-}
-
-/*mutex for start & stop is must here. */
-static int rtl_op_start(struct ieee80211_hw *hw)
-{
- int err = 0;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
-
- if (!is_hal_stop(rtlhal))
- return 0;
- if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
- return 0;
- mutex_lock(&rtlpriv->locks.conf_mutex);
- err = rtlpriv->intf_ops->adapter_start(hw);
- if (!err)
- rtl_watch_dog_timer_callback(&rtlpriv->works.watchdog_timer);
- mutex_unlock(&rtlpriv->locks.conf_mutex);
- return err;
-}
-
-static void rtl_op_stop(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- bool support_remote_wakeup = false;
-
- if (is_hal_stop(rtlhal))
- return;
-
- rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
- (u8 *)(&support_remote_wakeup));
- /* here is must, because adhoc do stop and start,
- * but stop with RFOFF may cause something wrong,
- * like adhoc TP
- */
- if (unlikely(ppsc->rfpwr_state == ERFOFF))
- rtl_ips_nic_on(hw);
-
- mutex_lock(&rtlpriv->locks.conf_mutex);
- /* if wowlan supported, DON'T clear connected info */
- if (!(support_remote_wakeup &&
- rtlhal->enter_pnp_sleep)) {
- mac->link_state = MAC80211_NOLINK;
- eth_zero_addr(mac->bssid);
- mac->vendor = PEER_UNKNOWN;
-
- /* reset sec info */
- rtl_cam_reset_sec_info(hw);
-
- rtl_deinit_deferred_work(hw);
- }
- rtlpriv->intf_ops->adapter_stop(hw);
-
- mutex_unlock(&rtlpriv->locks.conf_mutex);
-}
-
-static void rtl_op_tx(struct ieee80211_hw *hw,
- struct ieee80211_tx_control *control,
- struct sk_buff *skb)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_tcb_desc tcb_desc;
-
- memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
-
- if (unlikely(is_hal_stop(rtlhal) || ppsc->rfpwr_state != ERFON))
- goto err_free;
-
- if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
- goto err_free;
-
- if (!rtlpriv->intf_ops->waitq_insert(hw, control->sta, skb))
- rtlpriv->intf_ops->adapter_tx(hw, control->sta, skb, &tcb_desc);
- return;
-
-err_free:
- dev_kfree_skb_any(skb);
-}
-
-static int rtl_op_add_interface(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- int err = 0;
- u8 retry_limit = 0x30;
-
- if (mac->vif) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "vif has been set!! mac->vif = 0x%p\n", mac->vif);
- return -EOPNOTSUPP;
- }
-
- vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER;
-
- rtl_ips_nic_on(hw);
-
- mutex_lock(&rtlpriv->locks.conf_mutex);
- switch (ieee80211_vif_type_p2p(vif)) {
- case NL80211_IFTYPE_P2P_CLIENT:
- mac->p2p = P2P_ROLE_CLIENT;
- /*fall through*/
- case NL80211_IFTYPE_STATION:
- if (mac->beacon_enabled == 1) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "NL80211_IFTYPE_STATION\n");
- mac->beacon_enabled = 0;
- rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
- rtlpriv->cfg->maps[RTL_IBSS_INT_MASKS]);
- }
- break;
- case NL80211_IFTYPE_ADHOC:
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "NL80211_IFTYPE_ADHOC\n");
-
- mac->link_state = MAC80211_LINKED;
- rtlpriv->cfg->ops->set_bcn_reg(hw);
- if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
- mac->basic_rates = 0xfff;
- else
- mac->basic_rates = 0xff0;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
- (u8 *)(&mac->basic_rates));
-
- retry_limit = 0x07;
- break;
- case NL80211_IFTYPE_P2P_GO:
- mac->p2p = P2P_ROLE_GO;
- /*fall through*/
- case NL80211_IFTYPE_AP:
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "NL80211_IFTYPE_AP\n");
-
- mac->link_state = MAC80211_LINKED;
- rtlpriv->cfg->ops->set_bcn_reg(hw);
- if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
- mac->basic_rates = 0xfff;
- else
- mac->basic_rates = 0xff0;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
- (u8 *)(&mac->basic_rates));
-
- retry_limit = 0x07;
- break;
- case NL80211_IFTYPE_MESH_POINT:
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "NL80211_IFTYPE_MESH_POINT\n");
-
- mac->link_state = MAC80211_LINKED;
- rtlpriv->cfg->ops->set_bcn_reg(hw);
- if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
- mac->basic_rates = 0xfff;
- else
- mac->basic_rates = 0xff0;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
- (u8 *)(&mac->basic_rates));
-
- retry_limit = 0x07;
- break;
- default:
- pr_err("operation mode %d is not supported!\n",
- vif->type);
- err = -EOPNOTSUPP;
- goto out;
- }
-
- if (mac->p2p) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "p2p role %x\n", vif->type);
- mac->basic_rates = 0xff0;/*disable cck rate for p2p*/
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
- (u8 *)(&mac->basic_rates));
- }
- mac->vif = vif;
- mac->opmode = vif->type;
- rtlpriv->cfg->ops->set_network_type(hw, vif->type);
- memcpy(mac->mac_addr, vif->addr, ETH_ALEN);
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
-
- mac->retry_long = retry_limit;
- mac->retry_short = retry_limit;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
- (u8 *)(&retry_limit));
-out:
- mutex_unlock(&rtlpriv->locks.conf_mutex);
- return err;
-}
-
-static void rtl_op_remove_interface(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-
- mutex_lock(&rtlpriv->locks.conf_mutex);
-
- /* Free beacon resources */
- if (vif->type == NL80211_IFTYPE_AP ||
- vif->type == NL80211_IFTYPE_ADHOC ||
- vif->type == NL80211_IFTYPE_MESH_POINT) {
- if (mac->beacon_enabled == 1) {
- mac->beacon_enabled = 0;
- rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
- rtlpriv->cfg->maps[RTL_IBSS_INT_MASKS]);
- }
- }
-
- /*
- *Note: We assume NL80211_IFTYPE_UNSPECIFIED as
- *NO LINK for our hardware.
- */
- mac->p2p = 0;
- mac->vif = NULL;
- mac->link_state = MAC80211_NOLINK;
- eth_zero_addr(mac->bssid);
- mac->vendor = PEER_UNKNOWN;
- mac->opmode = NL80211_IFTYPE_UNSPECIFIED;
- rtlpriv->cfg->ops->set_network_type(hw, mac->opmode);
-
- mutex_unlock(&rtlpriv->locks.conf_mutex);
-}
-
-static int rtl_op_change_interface(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- enum nl80211_iftype new_type, bool p2p)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- int ret;
-
- rtl_op_remove_interface(hw, vif);
-
- vif->type = new_type;
- vif->p2p = p2p;
- ret = rtl_op_add_interface(hw, vif);
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "p2p %x\n", p2p);
- return ret;
-}
-
-#ifdef CONFIG_PM
-static u16 crc16_ccitt(u8 data, u16 crc)
-{
- u8 shift_in, data_bit, crc_bit11, crc_bit4, crc_bit15;
- u8 i;
- u16 result;
-
- for (i = 0; i < 8; i++) {
- crc_bit15 = !!(crc & BIT(15));
- data_bit = !!(data & BIT(i));
- shift_in = crc_bit15 ^ data_bit;
-
- result = crc << 1;
- if (shift_in == 0)
- result &= ~BIT(0);
- else
- result |= BIT(0);
-
- crc_bit11 = !!(crc & BIT(11)) ^ shift_in;
- if (crc_bit11 == 0)
- result &= ~BIT(12);
- else
- result |= BIT(12);
-
- crc_bit4 = !!(crc & BIT(4)) ^ shift_in;
- if (crc_bit4 == 0)
- result &= ~BIT(5);
- else
- result |= BIT(5);
-
- crc = result;
- }
-
- return crc;
-}
-
-static u16 _calculate_wol_pattern_crc(u8 *pattern, u16 len)
-{
- u16 crc = 0xffff;
- u32 i;
-
- for (i = 0; i < len; i++)
- crc = crc16_ccitt(pattern[i], crc);
-
- return ~crc;
-}
-
-static void _rtl_add_wowlan_patterns(struct ieee80211_hw *hw,
- struct cfg80211_wowlan *wow)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = &rtlpriv->mac80211;
- struct cfg80211_pkt_pattern *patterns = wow->patterns;
- struct rtl_wow_pattern rtl_pattern;
- const u8 *pattern_os, *mask_os;
- u8 mask[MAX_WOL_BIT_MASK_SIZE] = {0};
- u8 content[MAX_WOL_PATTERN_SIZE] = {0};
- u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
- u8 multicast_addr1[2] = {0x33, 0x33};
- u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
- u8 i, mask_len;
- u16 j, len;
-
- for (i = 0; i < wow->n_patterns; i++) {
- memset(&rtl_pattern, 0, sizeof(struct rtl_wow_pattern));
- memset(mask, 0, MAX_WOL_BIT_MASK_SIZE);
- if (patterns[i].pattern_len < 0 ||
- patterns[i].pattern_len > MAX_WOL_PATTERN_SIZE) {
- RT_TRACE(rtlpriv, COMP_POWER, DBG_WARNING,
- "Pattern[%d] is too long\n", i);
- continue;
- }
- pattern_os = patterns[i].pattern;
- mask_len = DIV_ROUND_UP(patterns[i].pattern_len, 8);
- mask_os = patterns[i].mask;
- RT_PRINT_DATA(rtlpriv, COMP_POWER, DBG_TRACE,
- "pattern content\n", pattern_os,
- patterns[i].pattern_len);
- RT_PRINT_DATA(rtlpriv, COMP_POWER, DBG_TRACE,
- "mask content\n", mask_os, mask_len);
- /* 1. unicast? multicast? or broadcast? */
- if (memcmp(pattern_os, broadcast_addr, 6) == 0)
- rtl_pattern.type = BROADCAST_PATTERN;
- else if (memcmp(pattern_os, multicast_addr1, 2) == 0 ||
- memcmp(pattern_os, multicast_addr2, 3) == 0)
- rtl_pattern.type = MULTICAST_PATTERN;
- else if (memcmp(pattern_os, mac->mac_addr, 6) == 0)
- rtl_pattern.type = UNICAST_PATTERN;
- else
- rtl_pattern.type = UNKNOWN_TYPE;
-
- /* 2. translate mask_from_os to mask_for_hw */
-
-/******************************************************************************
- * pattern from OS uses 'ethenet frame', like this:
-
- | 6 | 6 | 2 | 20 | Variable | 4 |
- |--------+--------+------+-----------+------------+-----|
- | 802.3 Mac Header | IP Header | TCP Packet | FCS |
- | DA | SA | Type |
-
- * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
-
- | 24 or 30 | 6 | 2 | 20 | Variable | 4 |
- |-------------------+--------+------+-----------+------------+-----|
- | 802.11 MAC Header | LLC | IP Header | TCP Packet | FCS |
- | Others | Tpye |
-
- * Therefore, we need translate mask_from_OS to mask_to_hw.
- * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
- * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
- * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
- ******************************************************************************/
-
- /* Shift 6 bits */
- for (j = 0; j < mask_len - 1; j++) {
- mask[j] = mask_os[j] >> 6;
- mask[j] |= (mask_os[j + 1] & 0x3F) << 2;
- }
- mask[j] = (mask_os[j] >> 6) & 0x3F;
- /* Set bit 0-5 to zero */
- mask[0] &= 0xC0;
-
- RT_PRINT_DATA(rtlpriv, COMP_POWER, DBG_TRACE,
- "mask to hw\n", mask, mask_len);
- for (j = 0; j < (MAX_WOL_BIT_MASK_SIZE + 1) / 4; j++) {
- rtl_pattern.mask[j] = mask[j * 4];
- rtl_pattern.mask[j] |= (mask[j * 4 + 1] << 8);
- rtl_pattern.mask[j] |= (mask[j * 4 + 2] << 16);
- rtl_pattern.mask[j] |= (mask[j * 4 + 3] << 24);
- }
-
- /* To get the wake up pattern from the mask.
- * We do not count first 12 bits which means
- * DA[6] and SA[6] in the pattern to match HW design.
- */
- len = 0;
- for (j = 12; j < patterns[i].pattern_len; j++) {
- if ((mask_os[j / 8] >> (j % 8)) & 0x01) {
- content[len] = pattern_os[j];
- len++;
- }
- }
-
- RT_PRINT_DATA(rtlpriv, COMP_POWER, DBG_TRACE,
- "pattern to hw\n", content, len);
- /* 3. calculate crc */
- rtl_pattern.crc = _calculate_wol_pattern_crc(content, len);
- RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
- "CRC_Remainder = 0x%x\n", rtl_pattern.crc);
-
- /* 4. write crc & mask_for_hw to hw */
- rtlpriv->cfg->ops->add_wowlan_pattern(hw, &rtl_pattern, i);
- }
- rtl_write_byte(rtlpriv, 0x698, wow->n_patterns);
-}
-
-static int rtl_op_suspend(struct ieee80211_hw *hw,
- struct cfg80211_wowlan *wow)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
-
- RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, "\n");
- if (WARN_ON(!wow))
- return -EINVAL;
-
- /* to resolve s4 can not wake up*/
- rtlhal->last_suspend_sec = ktime_get_real_seconds();
-
- if ((ppsc->wo_wlan_mode & WAKE_ON_PATTERN_MATCH) && wow->n_patterns)
- _rtl_add_wowlan_patterns(hw, wow);
-
- rtlhal->driver_is_goingto_unload = true;
- rtlhal->enter_pnp_sleep = true;
-
- rtl_lps_leave(hw);
- rtl_op_stop(hw);
- device_set_wakeup_enable(wiphy_dev(hw->wiphy), true);
- return 0;
-}
-
-static int rtl_op_resume(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-
- RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, "\n");
- rtlhal->driver_is_goingto_unload = false;
- rtlhal->enter_pnp_sleep = false;
- rtlhal->wake_from_pnp_sleep = true;
-
- /* to resovle s4 can not wake up*/
- if (ktime_get_real_seconds() - rtlhal->last_suspend_sec < 5)
- return -1;
-
- rtl_op_start(hw);
- device_set_wakeup_enable(wiphy_dev(hw->wiphy), false);
- ieee80211_resume_disconnect(mac->vif);
- rtlhal->wake_from_pnp_sleep = false;
- return 0;
-}
-#endif
-
-static int rtl_op_config(struct ieee80211_hw *hw, u32 changed)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct ieee80211_conf *conf = &hw->conf;
-
- if (mac->skip_scan)
- return 1;
-
- mutex_lock(&rtlpriv->locks.conf_mutex);
- if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) { /* BIT(2)*/
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "IEEE80211_CONF_CHANGE_LISTEN_INTERVAL\n");
- }
-
- /*For IPS */
- if (changed & IEEE80211_CONF_CHANGE_IDLE) {
- if (hw->conf.flags & IEEE80211_CONF_IDLE)
- rtl_ips_nic_off(hw);
- else
- rtl_ips_nic_on(hw);
- } else {
- /*
- *although rfoff may not cause by ips, but we will
- *check the reason in set_rf_power_state function
- */
- if (unlikely(ppsc->rfpwr_state == ERFOFF))
- rtl_ips_nic_on(hw);
- }
-
- /*For LPS */
- if ((changed & IEEE80211_CONF_CHANGE_PS) &&
- rtlpriv->psc.swctrl_lps && !rtlpriv->psc.fwctrl_lps) {
- cancel_delayed_work(&rtlpriv->works.ps_work);
- cancel_delayed_work(&rtlpriv->works.ps_rfon_wq);
- if (conf->flags & IEEE80211_CONF_PS) {
- rtlpriv->psc.sw_ps_enabled = true;
- /* sleep here is must, or we may recv the beacon and
- * cause mac80211 into wrong ps state, this will cause
- * power save nullfunc send fail, and further cause
- * pkt loss, So sleep must quickly but not immediately
- * because that will cause nullfunc send by mac80211
- * fail, and cause pkt loss, we have tested that 5mA
- * works very well
- */
- if (!rtlpriv->psc.multi_buffered)
- queue_delayed_work(rtlpriv->works.rtl_wq,
- &rtlpriv->works.ps_work,
- MSECS(5));
- } else {
- rtl_swlps_rf_awake(hw);
- rtlpriv->psc.sw_ps_enabled = false;
- }
- }
-
- if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "IEEE80211_CONF_CHANGE_RETRY_LIMITS %x\n",
- hw->conf.long_frame_max_tx_count);
- /* brought up everything changes (changed == ~0) indicates first
- * open, so use our default value instead of that of wiphy.
- */
- if (changed != ~0) {
- mac->retry_long = hw->conf.long_frame_max_tx_count;
- mac->retry_short = hw->conf.long_frame_max_tx_count;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
- (u8 *)(&hw->conf.long_frame_max_tx_count));
- }
- }
-
- if (changed & IEEE80211_CONF_CHANGE_CHANNEL &&
- !rtlpriv->proximity.proxim_on) {
- struct ieee80211_channel *channel = hw->conf.chandef.chan;
- enum nl80211_chan_width width = hw->conf.chandef.width;
- enum nl80211_channel_type channel_type = NL80211_CHAN_NO_HT;
- u8 wide_chan = (u8)channel->hw_value;
-
- /* channel_type is for 20&40M */
- if (width < NL80211_CHAN_WIDTH_80)
- channel_type =
- cfg80211_get_chandef_type(&hw->conf.chandef);
- if (mac->act_scanning)
- mac->n_channels++;
-
- if (rtlpriv->dm.supp_phymode_switch &&
- mac->link_state < MAC80211_LINKED &&
- !mac->act_scanning) {
- if (rtlpriv->cfg->ops->chk_switch_dmdp)
- rtlpriv->cfg->ops->chk_switch_dmdp(hw);
- }
-
- /*
- *because we should back channel to
- *current_network.chan in in scanning,
- *So if set_chan == current_network.chan
- *we should set it.
- *because mac80211 tell us wrong bw40
- *info for cisco1253 bw20, so we modify
- *it here based on UPPER & LOWER
- */
-
- if (width >= NL80211_CHAN_WIDTH_80) {
- if (width == NL80211_CHAN_WIDTH_80) {
- u32 center = hw->conf.chandef.center_freq1;
- u32 primary =
- (u32)hw->conf.chandef.chan->center_freq;
-
- rtlphy->current_chan_bw =
- HT_CHANNEL_WIDTH_80;
- mac->bw_80 = true;
- mac->bw_40 = true;
- if (center > primary) {
- mac->cur_80_prime_sc =
- PRIME_CHNL_OFFSET_LOWER;
- if (center - primary == 10) {
- mac->cur_40_prime_sc =
- PRIME_CHNL_OFFSET_UPPER;
-
- wide_chan += 2;
- } else if (center - primary == 30) {
- mac->cur_40_prime_sc =
- PRIME_CHNL_OFFSET_LOWER;
-
- wide_chan += 6;
- }
- } else {
- mac->cur_80_prime_sc =
- PRIME_CHNL_OFFSET_UPPER;
- if (primary - center == 10) {
- mac->cur_40_prime_sc =
- PRIME_CHNL_OFFSET_LOWER;
-
- wide_chan -= 2;
- } else if (primary - center == 30) {
- mac->cur_40_prime_sc =
- PRIME_CHNL_OFFSET_UPPER;
-
- wide_chan -= 6;
- }
- }
- }
- } else {
- switch (channel_type) {
- case NL80211_CHAN_HT20:
- case NL80211_CHAN_NO_HT:
- /* SC */
- mac->cur_40_prime_sc =
- PRIME_CHNL_OFFSET_DONT_CARE;
- rtlphy->current_chan_bw =
- HT_CHANNEL_WIDTH_20;
- mac->bw_40 = false;
- mac->bw_80 = false;
- break;
- case NL80211_CHAN_HT40MINUS:
- /* SC */
- mac->cur_40_prime_sc =
- PRIME_CHNL_OFFSET_UPPER;
- rtlphy->current_chan_bw =
- HT_CHANNEL_WIDTH_20_40;
- mac->bw_40 = true;
- mac->bw_80 = false;
-
- /*wide channel */
- wide_chan -= 2;
-
- break;
- case NL80211_CHAN_HT40PLUS:
- /* SC */
- mac->cur_40_prime_sc =
- PRIME_CHNL_OFFSET_LOWER;
- rtlphy->current_chan_bw =
- HT_CHANNEL_WIDTH_20_40;
- mac->bw_40 = true;
- mac->bw_80 = false;
-
- /*wide channel */
- wide_chan += 2;
-
- break;
- default:
- mac->bw_40 = false;
- mac->bw_80 = false;
- pr_err("switch case %#x not processed\n",
- channel_type);
- break;
- }
- }
-
- if (wide_chan <= 0)
- wide_chan = 1;
-
- /* In scanning, when before we offchannel we may send a ps=1
- * null to AP, and then we may send a ps = 0 null to AP quickly,
- * but first null may have caused AP to put lots of packet to
- * hw tx buffer. These packets must be tx'd before we go off
- * channel so we must delay more time to let AP flush these
- * packets before going offchannel, or dis-association or
- * delete BA will be caused by AP
- */
- if (rtlpriv->mac80211.offchan_delay) {
- rtlpriv->mac80211.offchan_delay = false;
- mdelay(50);
- }
-
- rtlphy->current_channel = wide_chan;
-
- rtlpriv->cfg->ops->switch_channel(hw);
- rtlpriv->cfg->ops->set_channel_access(hw);
- rtlpriv->cfg->ops->set_bw_mode(hw, channel_type);
- }
-
- mutex_unlock(&rtlpriv->locks.conf_mutex);
-
- return 0;
-}
-
-static void rtl_op_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed_flags,
- unsigned int *new_flags, u64 multicast)
-{
- bool update_rcr = false;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-
- *new_flags &= RTL_SUPPORTED_FILTERS;
- if (changed_flags == 0)
- return;
-
- /*TODO: we disable broadcase now, so enable here */
- if (changed_flags & FIF_ALLMULTI) {
- if (*new_flags & FIF_ALLMULTI) {
- mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AM] |
- rtlpriv->cfg->maps[MAC_RCR_AB];
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "Enable receive multicast frame\n");
- } else {
- mac->rx_conf &= ~(rtlpriv->cfg->maps[MAC_RCR_AM] |
- rtlpriv->cfg->maps[MAC_RCR_AB]);
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "Disable receive multicast frame\n");
- }
- update_rcr = true;
- }
-
- if (changed_flags & FIF_FCSFAIL) {
- if (*new_flags & FIF_FCSFAIL) {
- mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACRC32];
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "Enable receive FCS error frame\n");
- } else {
- mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACRC32];
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "Disable receive FCS error frame\n");
- }
- if (!update_rcr)
- update_rcr = true;
- }
-
- /* if ssid not set to hw don't check bssid
- * here just used for linked scanning, & linked
- * and nolink check bssid is set in set network_type
- */
- if (changed_flags & FIF_BCN_PRBRESP_PROMISC &&
- mac->link_state >= MAC80211_LINKED) {
- if (mac->opmode != NL80211_IFTYPE_AP &&
- mac->opmode != NL80211_IFTYPE_MESH_POINT) {
- if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
- rtlpriv->cfg->ops->set_chk_bssid(hw, false);
- else
- rtlpriv->cfg->ops->set_chk_bssid(hw, true);
- if (update_rcr)
- update_rcr = false;
- }
- }
-
- if (changed_flags & FIF_CONTROL) {
- if (*new_flags & FIF_CONTROL) {
- mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACF];
-
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "Enable receive control frame.\n");
- } else {
- mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACF];
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "Disable receive control frame.\n");
- }
- if (!update_rcr)
- update_rcr = true;
- }
-
- if (changed_flags & FIF_OTHER_BSS) {
- if (*new_flags & FIF_OTHER_BSS) {
- mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AAP];
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "Enable receive other BSS's frame.\n");
- } else {
- mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_AAP];
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "Disable receive other BSS's frame.\n");
- }
- if (!update_rcr)
- update_rcr = true;
- }
-
- if (update_rcr)
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
- (u8 *)(&mac->rx_conf));
-}
-
-static int rtl_op_sta_add(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_sta *sta)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_sta_info *sta_entry;
-
- if (sta) {
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- spin_lock_bh(&rtlpriv->locks.entry_list_lock);
- list_add_tail(&sta_entry->list, &rtlpriv->entry_list);
- spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
- if (rtlhal->current_bandtype == BAND_ON_2_4G) {
- sta_entry->wireless_mode = WIRELESS_MODE_G;
- if (sta->supp_rates[0] <= 0xf)
- sta_entry->wireless_mode = WIRELESS_MODE_B;
- if (sta->ht_cap.ht_supported)
- sta_entry->wireless_mode = WIRELESS_MODE_N_24G;
-
- if (vif->type == NL80211_IFTYPE_ADHOC)
- sta_entry->wireless_mode = WIRELESS_MODE_G;
- } else if (rtlhal->current_bandtype == BAND_ON_5G) {
- sta_entry->wireless_mode = WIRELESS_MODE_A;
- if (sta->ht_cap.ht_supported)
- sta_entry->wireless_mode = WIRELESS_MODE_N_5G;
- if (sta->vht_cap.vht_supported)
- sta_entry->wireless_mode = WIRELESS_MODE_AC_5G;
-
- if (vif->type == NL80211_IFTYPE_ADHOC)
- sta_entry->wireless_mode = WIRELESS_MODE_A;
- }
- /*disable cck rate for p2p*/
- if (mac->p2p)
- sta->supp_rates[0] &= 0xfffffff0;
-
- if (sta->ht_cap.ht_supported) {
- if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
- rtlphy->max_ht_chan_bw = HT_CHANNEL_WIDTH_20_40;
- else
- rtlphy->max_ht_chan_bw = HT_CHANNEL_WIDTH_20;
- }
-
- if (sta->vht_cap.vht_supported)
- rtlphy->max_vht_chan_bw = HT_CHANNEL_WIDTH_80;
-
- memcpy(sta_entry->mac_addr, sta->addr, ETH_ALEN);
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
- "Add sta addr is %pM\n", sta->addr);
- rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0, true);
-
- if (rtlpriv->phydm.ops)
- rtlpriv->phydm.ops->phydm_add_sta(rtlpriv, sta);
- }
-
- return 0;
-}
-
-static int rtl_op_sta_remove(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_sta *sta)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_sta_info *sta_entry;
-
- if (sta) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
- "Remove sta addr is %pM\n", sta->addr);
-
- if (rtlpriv->phydm.ops)
- rtlpriv->phydm.ops->phydm_del_sta(rtlpriv, sta);
-
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- sta_entry->wireless_mode = 0;
- sta_entry->ratr_index = 0;
- spin_lock_bh(&rtlpriv->locks.entry_list_lock);
- list_del(&sta_entry->list);
- spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
- }
- return 0;
-}
-
-static int _rtl_get_hal_qnum(u16 queue)
-{
- int qnum;
-
- switch (queue) {
- case 0:
- qnum = AC3_VO;
- break;
- case 1:
- qnum = AC2_VI;
- break;
- case 2:
- qnum = AC0_BE;
- break;
- case 3:
- qnum = AC1_BK;
- break;
- default:
- qnum = AC0_BE;
- break;
- }
- return qnum;
-}
-
-static void rtl_op_sta_statistics(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_sta *sta,
- struct station_info *sinfo)
-{
- /* nothing filled by driver, so mac80211 will update all info */
- sinfo->filled = 0;
-}
-
-static int rtl_op_set_frag_threshold(struct ieee80211_hw *hw, u32 value)
-{
- return -EOPNOTSUPP;
-}
-
-/*
- *for mac80211 VO = 0, VI = 1, BE = 2, BK = 3
- *for rtl819x BE = 0, BK = 1, VI = 2, VO = 3
- */
-static int rtl_op_conf_tx(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif, u16 queue,
- const struct ieee80211_tx_queue_params *param)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- int aci;
-
- if (queue >= AC_MAX) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "queue number %d is incorrect!\n", queue);
- return -EINVAL;
- }
-
- aci = _rtl_get_hal_qnum(queue);
- mac->ac[aci].aifs = param->aifs;
- mac->ac[aci].cw_min = cpu_to_le16(param->cw_min);
- mac->ac[aci].cw_max = cpu_to_le16(param->cw_max);
- mac->ac[aci].tx_op = cpu_to_le16(param->txop);
- memcpy(&mac->edca_param[aci], param, sizeof(*param));
- rtlpriv->cfg->ops->set_qos(hw, aci);
- return 0;
-}
-
-static void send_beacon_frame(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
- struct rtl_tcb_desc tcb_desc;
-
- if (skb) {
- memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
- rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
- }
-}
-
-static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_bss_conf *bss_conf,
- u32 changed)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
-
- mutex_lock(&rtlpriv->locks.conf_mutex);
- if (vif->type == NL80211_IFTYPE_ADHOC ||
- vif->type == NL80211_IFTYPE_AP ||
- vif->type == NL80211_IFTYPE_MESH_POINT) {
- if (changed & BSS_CHANGED_BEACON ||
- (changed & BSS_CHANGED_BEACON_ENABLED &&
- bss_conf->enable_beacon)) {
- if (mac->beacon_enabled == 0) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
- "BSS_CHANGED_BEACON_ENABLED\n");
-
- /*start hw beacon interrupt. */
- /*rtlpriv->cfg->ops->set_bcn_reg(hw); */
- mac->beacon_enabled = 1;
- rtlpriv->cfg->ops->update_interrupt_mask(hw,
- rtlpriv->cfg->maps
- [RTL_IBSS_INT_MASKS], 0);
-
- if (rtlpriv->cfg->ops->linked_set_reg)
- rtlpriv->cfg->ops->linked_set_reg(hw);
- send_beacon_frame(hw, vif);
- }
- }
- if ((changed & BSS_CHANGED_BEACON_ENABLED &&
- !bss_conf->enable_beacon)) {
- if (mac->beacon_enabled == 1) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
- "ADHOC DISABLE BEACON\n");
-
- mac->beacon_enabled = 0;
- rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
- rtlpriv->cfg->maps
- [RTL_IBSS_INT_MASKS]);
- }
- }
- if (changed & BSS_CHANGED_BEACON_INT) {
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_TRACE,
- "BSS_CHANGED_BEACON_INT\n");
- mac->beacon_interval = bss_conf->beacon_int;
- rtlpriv->cfg->ops->set_bcn_intv(hw);
- }
- }
-
- /*TODO: reference to enum ieee80211_bss_change */
- if (changed & BSS_CHANGED_ASSOC) {
- u8 mstatus;
-
- if (bss_conf->assoc) {
- struct ieee80211_sta *sta = NULL;
- u8 keep_alive = 10;
-
- mstatus = RT_MEDIA_CONNECT;
- /* we should reset all sec info & cam
- * before set cam after linked, we should not
- * reset in disassoc, that will cause tkip->wep
- * fail because some flag will be wrong
- * reset sec info
- */
- rtl_cam_reset_sec_info(hw);
- /* reset cam to fix wep fail issue
- * when change from wpa to wep
- */
- rtl_cam_reset_all_entry(hw);
-
- mac->link_state = MAC80211_LINKED;
- mac->cnt_after_linked = 0;
- mac->assoc_id = bss_conf->aid;
- memcpy(mac->bssid, bss_conf->bssid, ETH_ALEN);
-
- if (rtlpriv->cfg->ops->linked_set_reg)
- rtlpriv->cfg->ops->linked_set_reg(hw);
-
- rcu_read_lock();
- sta = ieee80211_find_sta(vif, (u8 *)bss_conf->bssid);
- if (!sta) {
- rcu_read_unlock();
- goto out;
- }
- RT_TRACE(rtlpriv, COMP_EASY_CONCURRENT, DBG_LOUD,
- "send PS STATIC frame\n");
- if (rtlpriv->dm.supp_phymode_switch) {
- if (sta->ht_cap.ht_supported)
- rtl_send_smps_action(hw, sta,
- IEEE80211_SMPS_STATIC);
- }
-
- if (rtlhal->current_bandtype == BAND_ON_5G) {
- mac->mode = WIRELESS_MODE_A;
- } else {
- if (sta->supp_rates[0] <= 0xf)
- mac->mode = WIRELESS_MODE_B;
- else
- mac->mode = WIRELESS_MODE_G;
- }
-
- if (sta->ht_cap.ht_supported) {
- if (rtlhal->current_bandtype == BAND_ON_2_4G)
- mac->mode = WIRELESS_MODE_N_24G;
- else
- mac->mode = WIRELESS_MODE_N_5G;
- }
-
- if (sta->vht_cap.vht_supported) {
- if (rtlhal->current_bandtype == BAND_ON_5G)
- mac->mode = WIRELESS_MODE_AC_5G;
- else
- mac->mode = WIRELESS_MODE_AC_24G;
- }
-
- if (vif->type == NL80211_IFTYPE_STATION)
- rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0,
- true);
- rcu_read_unlock();
-
- /* to avoid AP Disassociation caused by inactivity */
- rtlpriv->cfg->ops->set_hw_reg(hw,
- HW_VAR_KEEP_ALIVE,
- (u8 *)(&keep_alive));
-
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
- "BSS_CHANGED_ASSOC\n");
- } else {
- struct cfg80211_bss *bss = NULL;
-
- mstatus = RT_MEDIA_DISCONNECT;
-
- if (mac->link_state == MAC80211_LINKED)
- rtl_lps_leave(hw);
- if (ppsc->p2p_ps_info.p2p_ps_mode > P2P_PS_NONE)
- rtl_p2p_ps_cmd(hw, P2P_PS_DISABLE);
- mac->link_state = MAC80211_NOLINK;
-
- bss = cfg80211_get_bss(hw->wiphy, NULL,
- (u8 *)mac->bssid, NULL, 0,
- IEEE80211_BSS_TYPE_ESS,
- IEEE80211_PRIVACY_OFF);
-
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
- "bssid = %x-%x-%x-%x-%x-%x\n",
- mac->bssid[0], mac->bssid[1],
- mac->bssid[2], mac->bssid[3],
- mac->bssid[4], mac->bssid[5]);
-
- if (bss) {
- cfg80211_unlink_bss(hw->wiphy, bss);
- cfg80211_put_bss(hw->wiphy, bss);
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
- "cfg80211_unlink !!\n");
- }
-
- eth_zero_addr(mac->bssid);
- mac->vendor = PEER_UNKNOWN;
- mac->mode = 0;
-
- if (rtlpriv->dm.supp_phymode_switch) {
- if (rtlpriv->cfg->ops->chk_switch_dmdp)
- rtlpriv->cfg->ops->chk_switch_dmdp(hw);
- }
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
- "BSS_CHANGED_UN_ASSOC\n");
- }
- rtlpriv->cfg->ops->set_network_type(hw, vif->type);
- /* For FW LPS:
- * To tell firmware we have connected or disconnected
- */
- rtlpriv->cfg->ops->set_hw_reg(hw,
- HW_VAR_H2C_FW_JOINBSSRPT,
- (u8 *)(&mstatus));
- ppsc->report_linked = (mstatus == RT_MEDIA_CONNECT) ?
- true : false;
-
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_mediastatus_notify(
- rtlpriv, mstatus);
- }
-
- if (changed & BSS_CHANGED_ERP_CTS_PROT) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
- "BSS_CHANGED_ERP_CTS_PROT\n");
- mac->use_cts_protect = bss_conf->use_cts_prot;
- }
-
- if (changed & BSS_CHANGED_ERP_PREAMBLE) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
- "BSS_CHANGED_ERP_PREAMBLE use short preamble:%x\n",
- bss_conf->use_short_preamble);
-
- mac->short_preamble = bss_conf->use_short_preamble;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACK_PREAMBLE,
- (u8 *)(&mac->short_preamble));
- }
-
- if (changed & BSS_CHANGED_ERP_SLOT) {
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
- "BSS_CHANGED_ERP_SLOT\n");
-
- if (bss_conf->use_short_slot)
- mac->slot_time = RTL_SLOT_TIME_9;
- else
- mac->slot_time = RTL_SLOT_TIME_20;
-
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
- (u8 *)(&mac->slot_time));
- }
-
- if (changed & BSS_CHANGED_HT) {
- struct ieee80211_sta *sta = NULL;
-
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
- "BSS_CHANGED_HT\n");
-
- rcu_read_lock();
- sta = ieee80211_find_sta(vif, (u8 *)bss_conf->bssid);
- if (sta) {
- if (sta->ht_cap.ampdu_density >
- mac->current_ampdu_density)
- mac->current_ampdu_density =
- sta->ht_cap.ampdu_density;
- if (sta->ht_cap.ampdu_factor <
- mac->current_ampdu_factor)
- mac->current_ampdu_factor =
- sta->ht_cap.ampdu_factor;
-
- if (sta->ht_cap.ht_supported) {
- if (sta->ht_cap.cap &
- IEEE80211_HT_CAP_SUP_WIDTH_20_40)
- rtlphy->max_ht_chan_bw =
- HT_CHANNEL_WIDTH_20_40;
- else
- rtlphy->max_ht_chan_bw =
- HT_CHANNEL_WIDTH_20;
- }
- }
- rcu_read_unlock();
-
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SHORTGI_DENSITY,
- (u8 *)(&mac->max_mss_density));
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AMPDU_FACTOR,
- &mac->current_ampdu_factor);
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AMPDU_MIN_SPACE,
- &mac->current_ampdu_density);
- }
-
- if (changed & BSS_CHANGED_BANDWIDTH) {
- struct ieee80211_sta *sta = NULL;
-
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
- "BSS_CHANGED_BANDWIDTH\n");
-
- rcu_read_lock();
- sta = ieee80211_find_sta(vif, (u8 *)bss_conf->bssid);
-
- if (sta) {
- if (sta->ht_cap.ht_supported) {
- if (sta->ht_cap.cap &
- IEEE80211_HT_CAP_SUP_WIDTH_20_40)
- rtlphy->max_ht_chan_bw =
- HT_CHANNEL_WIDTH_20_40;
- else
- rtlphy->max_ht_chan_bw =
- HT_CHANNEL_WIDTH_20;
- }
-
- if (sta->vht_cap.vht_supported)
- rtlphy->max_vht_chan_bw = HT_CHANNEL_WIDTH_80;
- }
- rcu_read_unlock();
- }
-
- if (changed & BSS_CHANGED_BSSID) {
- u32 basic_rates;
- struct ieee80211_sta *sta = NULL;
-
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BSSID,
- (u8 *)bss_conf->bssid);
-
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
- "bssid: %pM\n", bss_conf->bssid);
-
- mac->vendor = PEER_UNKNOWN;
- memcpy(mac->bssid, bss_conf->bssid, ETH_ALEN);
-
- rcu_read_lock();
- sta = ieee80211_find_sta(vif, (u8 *)bss_conf->bssid);
- if (!sta) {
- rcu_read_unlock();
- goto out;
- }
-
- if (rtlhal->current_bandtype == BAND_ON_5G) {
- mac->mode = WIRELESS_MODE_A;
- } else {
- if (sta->supp_rates[0] <= 0xf)
- mac->mode = WIRELESS_MODE_B;
- else
- mac->mode = WIRELESS_MODE_G;
- }
-
- if (sta->ht_cap.ht_supported) {
- if (rtlhal->current_bandtype == BAND_ON_2_4G)
- mac->mode = WIRELESS_MODE_N_24G;
- else
- mac->mode = WIRELESS_MODE_N_5G;
- }
-
- if (sta->vht_cap.vht_supported) {
- if (rtlhal->current_bandtype == BAND_ON_5G)
- mac->mode = WIRELESS_MODE_AC_5G;
- else
- mac->mode = WIRELESS_MODE_AC_24G;
- }
-
- /* just station need it, because ibss & ap mode will
- * set in sta_add, and will be NULL here
- */
- if (vif->type == NL80211_IFTYPE_STATION) {
- struct rtl_sta_info *sta_entry;
-
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- sta_entry->wireless_mode = mac->mode;
- }
-
- if (sta->ht_cap.ht_supported) {
- mac->ht_enable = true;
-
- /* for cisco 1252 bw20 it's wrong
- * if (ht_cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) {
- * mac->bw_40 = true;
- * }
- */
- }
-
- if (sta->vht_cap.vht_supported)
- mac->vht_enable = true;
-
- if (changed & BSS_CHANGED_BASIC_RATES) {
- /* for 5G must << RATE_6M_INDEX = 4,
- * because 5G have no cck rate
- */
- if (rtlhal->current_bandtype == BAND_ON_5G)
- basic_rates = sta->supp_rates[1] << 4;
- else
- basic_rates = sta->supp_rates[0];
-
- mac->basic_rates = basic_rates;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
- (u8 *)(&basic_rates));
- }
- rcu_read_unlock();
- }
-out:
- mutex_unlock(&rtlpriv->locks.conf_mutex);
-}
-
-static u64 rtl_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u64 tsf;
-
- rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_CORRECT_TSF, (u8 *)(&tsf));
- return tsf;
-}
-
-static void rtl_op_set_tsf(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif, u64 tsf)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0;
-
- mac->tsf = tsf;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CORRECT_TSF, (u8 *)(&bibss));
-}
-
-static void rtl_op_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 tmp = 0;
-
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DUAL_TSF_RST, (u8 *)(&tmp));
-}
-
-static void rtl_op_sta_notify(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- enum sta_notify_cmd cmd,
- struct ieee80211_sta *sta)
-{
- switch (cmd) {
- case STA_NOTIFY_SLEEP:
- break;
- case STA_NOTIFY_AWAKE:
- break;
- default:
- break;
- }
-}
-
-static int rtl_op_ampdu_action(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_ampdu_params *params)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_sta *sta = params->sta;
- enum ieee80211_ampdu_mlme_action action = params->action;
- u16 tid = params->tid;
- u16 *ssn = ¶ms->ssn;
-
- switch (action) {
- case IEEE80211_AMPDU_TX_START:
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
- "IEEE80211_AMPDU_TX_START: TID:%d\n", tid);
- return rtl_tx_agg_start(hw, vif, sta, tid, ssn);
- case IEEE80211_AMPDU_TX_STOP_CONT:
- case IEEE80211_AMPDU_TX_STOP_FLUSH:
- case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
- "IEEE80211_AMPDU_TX_STOP: TID:%d\n", tid);
- return rtl_tx_agg_stop(hw, vif, sta, tid);
- case IEEE80211_AMPDU_TX_OPERATIONAL:
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
- "IEEE80211_AMPDU_TX_OPERATIONAL:TID:%d\n", tid);
- rtl_tx_agg_oper(hw, sta, tid);
- break;
- case IEEE80211_AMPDU_RX_START:
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
- "IEEE80211_AMPDU_RX_START:TID:%d\n", tid);
- return rtl_rx_agg_start(hw, sta, tid);
- case IEEE80211_AMPDU_RX_STOP:
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
- "IEEE80211_AMPDU_RX_STOP:TID:%d\n", tid);
- return rtl_rx_agg_stop(hw, sta, tid);
- default:
- pr_err("IEEE80211_AMPDU_ERR!!!!:\n");
- return -EOPNOTSUPP;
- }
- return 0;
-}
-
-static void rtl_op_sw_scan_start(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- const u8 *mac_addr)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n");
- mac->act_scanning = true;
- if (rtlpriv->link_info.higher_busytraffic) {
- mac->skip_scan = true;
- return;
- }
-
- if (rtlpriv->phydm.ops)
- rtlpriv->phydm.ops->phydm_pause_dig(rtlpriv, 1);
-
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_scan_notify(rtlpriv, 1);
- else if (rtlpriv->btcoexist.btc_ops)
- rtlpriv->btcoexist.btc_ops->btc_scan_notify_wifi_only(rtlpriv,
- 1);
-
- if (rtlpriv->dm.supp_phymode_switch) {
- if (rtlpriv->cfg->ops->chk_switch_dmdp)
- rtlpriv->cfg->ops->chk_switch_dmdp(hw);
- }
-
- if (mac->link_state == MAC80211_LINKED) {
- rtl_lps_leave(hw);
- mac->link_state = MAC80211_LINKED_SCANNING;
- } else {
- rtl_ips_nic_on(hw);
- }
-
- /* Dul mac */
- rtlpriv->rtlhal.load_imrandiqk_setting_for2g = false;
-
- rtlpriv->cfg->ops->led_control(hw, LED_CTL_SITE_SURVEY);
- rtlpriv->cfg->ops->scan_operation_backup(hw, SCAN_OPT_BACKUP_BAND0);
-}
-
-static void rtl_op_sw_scan_complete(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-
- RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n");
- mac->act_scanning = false;
- mac->skip_scan = false;
-
- rtlpriv->btcoexist.btc_info.ap_num = rtlpriv->scan_list.num;
-
- if (rtlpriv->link_info.higher_busytraffic)
- return;
-
- /* p2p will use 1/6/11 to scan */
- if (mac->n_channels == 3)
- mac->p2p_in_use = true;
- else
- mac->p2p_in_use = false;
- mac->n_channels = 0;
- /* Dul mac */
- rtlpriv->rtlhal.load_imrandiqk_setting_for2g = false;
-
- if (mac->link_state == MAC80211_LINKED_SCANNING) {
- mac->link_state = MAC80211_LINKED;
- if (mac->opmode == NL80211_IFTYPE_STATION) {
- /* fix fwlps issue */
- rtlpriv->cfg->ops->set_network_type(hw, mac->opmode);
- }
- }
-
- rtlpriv->cfg->ops->scan_operation_backup(hw, SCAN_OPT_RESTORE);
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_scan_notify(rtlpriv, 0);
- else if (rtlpriv->btcoexist.btc_ops)
- rtlpriv->btcoexist.btc_ops->btc_scan_notify_wifi_only(rtlpriv,
- 0);
-
- if (rtlpriv->phydm.ops)
- rtlpriv->phydm.ops->phydm_pause_dig(rtlpriv, 0);
-}
-
-static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
- struct ieee80211_vif *vif, struct ieee80211_sta *sta,
- struct ieee80211_key_conf *key)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 key_type = NO_ENCRYPTION;
- u8 key_idx;
- bool group_key = false;
- bool wep_only = false;
- int err = 0;
- u8 mac_addr[ETH_ALEN];
- u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-
- rtlpriv->btcoexist.btc_info.in_4way = false;
-
- if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "not open hw encryption\n");
- return -ENOSPC; /*User disabled HW-crypto */
- }
- /* To support IBSS, use sw-crypto for GTK */
- if ((vif->type == NL80211_IFTYPE_ADHOC ||
- vif->type == NL80211_IFTYPE_MESH_POINT) &&
- !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
- return -ENOSPC;
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "%s hardware based encryption for keyidx: %d, mac: %pM\n",
- cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
- sta ? sta->addr : bcast_addr);
- rtlpriv->sec.being_setkey = true;
- rtl_ips_nic_on(hw);
- mutex_lock(&rtlpriv->locks.conf_mutex);
- /* <1> get encryption alg */
-
- switch (key->cipher) {
- case WLAN_CIPHER_SUITE_WEP40:
- key_type = WEP40_ENCRYPTION;
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP40\n");
- break;
- case WLAN_CIPHER_SUITE_WEP104:
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP104\n");
- key_type = WEP104_ENCRYPTION;
- break;
- case WLAN_CIPHER_SUITE_TKIP:
- key_type = TKIP_ENCRYPTION;
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:TKIP\n");
- break;
- case WLAN_CIPHER_SUITE_CCMP:
- key_type = AESCCMP_ENCRYPTION;
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CCMP\n");
- break;
- case WLAN_CIPHER_SUITE_AES_CMAC:
- /* HW don't support CMAC encryption,
- * use software CMAC encryption
- */
- key_type = AESCMAC_ENCRYPTION;
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CMAC\n");
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "HW don't support CMAC encryption, use software CMAC encryption\n");
- err = -EOPNOTSUPP;
- goto out_unlock;
- default:
- pr_err("alg_err:%x!!!!:\n", key->cipher);
- goto out_unlock;
- }
- if (key_type == WEP40_ENCRYPTION ||
- key_type == WEP104_ENCRYPTION ||
- vif->type == NL80211_IFTYPE_ADHOC)
- rtlpriv->sec.use_defaultkey = true;
-
- /* <2> get key_idx */
- key_idx = (u8)(key->keyidx);
- if (key_idx > 3)
- goto out_unlock;
- /* <3> if pairwise key enable_hw_sec */
- group_key = !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE);
-
- /* wep always be group key, but there are two conditions:
- * 1) wep only: is just for wep enc, in this condition
- * rtlpriv->sec.pairwise_enc_algorithm == NO_ENCRYPTION
- * will be true & enable_hw_sec will be set when wep
- * ke setting.
- * 2) wep(group) + AES(pairwise): some AP like cisco
- * may use it, in this condition enable_hw_sec will not
- * be set when wep key setting.
- * we must reset sec_info after lingked before set key,
- * or some flag will be wrong
- */
- if (vif->type == NL80211_IFTYPE_AP ||
- vif->type == NL80211_IFTYPE_MESH_POINT) {
- if (!group_key || key_type == WEP40_ENCRYPTION ||
- key_type == WEP104_ENCRYPTION) {
- if (group_key)
- wep_only = true;
- rtlpriv->cfg->ops->enable_hw_sec(hw);
- }
- } else {
- if (!group_key || vif->type == NL80211_IFTYPE_ADHOC ||
- rtlpriv->sec.pairwise_enc_algorithm == NO_ENCRYPTION) {
- if (rtlpriv->sec.pairwise_enc_algorithm ==
- NO_ENCRYPTION &&
- (key_type == WEP40_ENCRYPTION ||
- key_type == WEP104_ENCRYPTION))
- wep_only = true;
- rtlpriv->sec.pairwise_enc_algorithm = key_type;
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "set enable_hw_sec, key_type:%x(OPEN:0 WEP40:1 TKIP:2 AES:4 WEP104:5)\n",
- key_type);
- rtlpriv->cfg->ops->enable_hw_sec(hw);
- }
- }
- /* <4> set key based on cmd */
- switch (cmd) {
- case SET_KEY:
- if (wep_only) {
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "set WEP(group/pairwise) key\n");
- /* Pairwise key with an assigned MAC address. */
- rtlpriv->sec.pairwise_enc_algorithm = key_type;
- rtlpriv->sec.group_enc_algorithm = key_type;
- /*set local buf about wep key. */
- memcpy(rtlpriv->sec.key_buf[key_idx],
- key->key, key->keylen);
- rtlpriv->sec.key_len[key_idx] = key->keylen;
- eth_zero_addr(mac_addr);
- } else if (group_key) { /* group key */
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "set group key\n");
- /* group key */
- rtlpriv->sec.group_enc_algorithm = key_type;
- /*set local buf about group key. */
- memcpy(rtlpriv->sec.key_buf[key_idx],
- key->key, key->keylen);
- rtlpriv->sec.key_len[key_idx] = key->keylen;
- memcpy(mac_addr, bcast_addr, ETH_ALEN);
- } else { /* pairwise key */
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "set pairwise key\n");
- if (!sta) {
- WARN_ONCE(true,
- "rtlwifi: pairwise key without mac_addr\n");
-
- err = -EOPNOTSUPP;
- goto out_unlock;
- }
- /* Pairwise key with an assigned MAC address. */
- rtlpriv->sec.pairwise_enc_algorithm = key_type;
- /*set local buf about pairwise key. */
- memcpy(rtlpriv->sec.key_buf[PAIRWISE_KEYIDX],
- key->key, key->keylen);
- rtlpriv->sec.key_len[PAIRWISE_KEYIDX] = key->keylen;
- rtlpriv->sec.pairwise_key =
- rtlpriv->sec.key_buf[PAIRWISE_KEYIDX];
- memcpy(mac_addr, sta->addr, ETH_ALEN);
- }
- rtlpriv->cfg->ops->set_key(hw, key_idx, mac_addr,
- group_key, key_type, wep_only,
- false);
- /* <5> tell mac80211 do something: */
- /*must use sw generate IV, or can not work !!!!. */
- key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
- key->hw_key_idx = key_idx;
- if (key_type == TKIP_ENCRYPTION)
- key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
- /*use software CCMP encryption for management frames (MFP) */
- if (key_type == AESCCMP_ENCRYPTION)
- key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
- break;
- case DISABLE_KEY:
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "disable key delete one entry\n");
- /*set local buf about wep key. */
- if (vif->type == NL80211_IFTYPE_AP ||
- vif->type == NL80211_IFTYPE_MESH_POINT) {
- if (sta)
- rtl_cam_del_entry(hw, sta->addr);
- }
- memset(rtlpriv->sec.key_buf[key_idx], 0, key->keylen);
- rtlpriv->sec.key_len[key_idx] = 0;
- eth_zero_addr(mac_addr);
- /*
- *mac80211 will delete entries one by one,
- *so don't use rtl_cam_reset_all_entry
- *or clear all entries here.
- */
- rtl_wait_tx_report_acked(hw, 500); /* wait 500ms for TX ack */
-
- rtl_cam_delete_one_entry(hw, mac_addr, key_idx);
- break;
- default:
- pr_err("cmd_err:%x!!!!:\n", cmd);
- }
-out_unlock:
- mutex_unlock(&rtlpriv->locks.conf_mutex);
- rtlpriv->sec.being_setkey = false;
- return err;
-}
-
-static void rtl_op_rfkill_poll(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- bool radio_state;
- bool blocked;
- u8 valid = 0;
-
- if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
- return;
-
- mutex_lock(&rtlpriv->locks.conf_mutex);
-
- /*if Radio On return true here */
- radio_state = rtlpriv->cfg->ops->radio_onoff_checking(hw, &valid);
-
- if (valid) {
- if (unlikely(radio_state != rtlpriv->rfkill.rfkill_state)) {
- rtlpriv->rfkill.rfkill_state = radio_state;
-
- RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
- "wireless radio switch turned %s\n",
- radio_state ? "on" : "off");
-
- blocked = (rtlpriv->rfkill.rfkill_state == 1) ? 0 : 1;
- wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
- }
- }
-
- mutex_unlock(&rtlpriv->locks.conf_mutex);
-}
-
-/* this function is called by mac80211 to flush tx buffer
- * before switch channel or power save, or tx buffer packet
- * maybe send after offchannel or rf sleep, this may cause
- * dis-association by AP
- */
-static void rtl_op_flush(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- u32 queues,
- bool drop)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- if (rtlpriv->intf_ops->flush)
- rtlpriv->intf_ops->flush(hw, queues, drop);
-}
-
-/* Description:
- * This routine deals with the Power Configuration CMD
- * parsing for RTL8723/RTL8188E Series IC.
- * Assumption:
- * We should follow specific format that was released from HW SD.
- */
-bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
- u8 faversion, u8 interface_type,
- struct wlan_pwr_cfg pwrcfgcmd[])
-{
- struct wlan_pwr_cfg cfg_cmd;
- bool polling_bit = false;
- u32 ary_idx = 0;
- u8 value = 0;
- u32 offset = 0;
- u32 polling_count = 0;
- u32 max_polling_cnt = 5000;
-
- do {
- cfg_cmd = pwrcfgcmd[ary_idx];
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "%s(): offset(%#x),cut_msk(%#x), famsk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
- __func__, GET_PWR_CFG_OFFSET(cfg_cmd),
- GET_PWR_CFG_CUT_MASK(cfg_cmd),
- GET_PWR_CFG_FAB_MASK(cfg_cmd),
- GET_PWR_CFG_INTF_MASK(cfg_cmd),
- GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd),
- GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd));
-
- if ((GET_PWR_CFG_FAB_MASK(cfg_cmd) & faversion) &&
- (GET_PWR_CFG_CUT_MASK(cfg_cmd) & cut_version) &&
- (GET_PWR_CFG_INTF_MASK(cfg_cmd) & interface_type)) {
- switch (GET_PWR_CFG_CMD(cfg_cmd)) {
- case PWR_CMD_READ:
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "%s(): PWR_CMD_READ\n", __func__);
- break;
- case PWR_CMD_WRITE:
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "%s(): PWR_CMD_WRITE\n", __func__);
- offset = GET_PWR_CFG_OFFSET(cfg_cmd);
-
- /*Read the value from system register*/
- value = rtl_read_byte(rtlpriv, offset);
- value &= (~(GET_PWR_CFG_MASK(cfg_cmd)));
- value |= (GET_PWR_CFG_VALUE(cfg_cmd) &
- GET_PWR_CFG_MASK(cfg_cmd));
-
- /*Write the value back to system register*/
- rtl_write_byte(rtlpriv, offset, value);
- break;
- case PWR_CMD_POLLING:
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "%s(): PWR_CMD_POLLING\n", __func__);
- polling_bit = false;
- offset = GET_PWR_CFG_OFFSET(cfg_cmd);
-
- do {
- value = rtl_read_byte(rtlpriv, offset);
-
- value &= GET_PWR_CFG_MASK(cfg_cmd);
- if (value ==
- (GET_PWR_CFG_VALUE(cfg_cmd) &
- GET_PWR_CFG_MASK(cfg_cmd)))
- polling_bit = true;
- else
- udelay(10);
-
- if (polling_count++ > max_polling_cnt)
- return false;
- } while (!polling_bit);
- break;
- case PWR_CMD_DELAY:
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "%s(): PWR_CMD_DELAY\n", __func__);
- if (GET_PWR_CFG_VALUE(cfg_cmd) ==
- PWRSEQ_DELAY_US)
- udelay(GET_PWR_CFG_OFFSET(cfg_cmd));
- else
- mdelay(GET_PWR_CFG_OFFSET(cfg_cmd));
- break;
- case PWR_CMD_END:
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "%s(): PWR_CMD_END\n", __func__);
- return true;
- default:
- WARN_ONCE(true,
- "rtlwifi: %s(): Unknown CMD!!\n",
- __func__);
- break;
- }
- }
- ary_idx++;
- } while (1);
-
- return true;
-}
-
-bool rtl_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl8192_tx_ring *ring;
- struct rtl_tx_desc *pdesc;
- unsigned long flags;
- struct sk_buff *pskb = NULL;
-
- ring = &rtlpci->tx_ring[BEACON_QUEUE];
-
- spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
- pskb = __skb_dequeue(&ring->queue);
- if (pskb)
- dev_kfree_skb_irq(pskb);
-
- /*this is wrong, fill_tx_cmddesc needs update*/
- pdesc = &ring->desc[0];
-
- rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
-
- __skb_queue_tail(&ring->queue, skb);
-
- spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
-
- rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
-
- return true;
-}
-
-const struct ieee80211_ops rtl_ops = {
- .start = rtl_op_start,
- .stop = rtl_op_stop,
- .tx = rtl_op_tx,
- .add_interface = rtl_op_add_interface,
- .remove_interface = rtl_op_remove_interface,
- .change_interface = rtl_op_change_interface,
-#ifdef CONFIG_PM
- .suspend = rtl_op_suspend,
- .resume = rtl_op_resume,
-#endif
- .config = rtl_op_config,
- .configure_filter = rtl_op_configure_filter,
- .set_key = rtl_op_set_key,
- .sta_statistics = rtl_op_sta_statistics,
- .set_frag_threshold = rtl_op_set_frag_threshold,
- .conf_tx = rtl_op_conf_tx,
- .bss_info_changed = rtl_op_bss_info_changed,
- .get_tsf = rtl_op_get_tsf,
- .set_tsf = rtl_op_set_tsf,
- .reset_tsf = rtl_op_reset_tsf,
- .sta_notify = rtl_op_sta_notify,
- .ampdu_action = rtl_op_ampdu_action,
- .sw_scan_start = rtl_op_sw_scan_start,
- .sw_scan_complete = rtl_op_sw_scan_complete,
- .rfkill_poll = rtl_op_rfkill_poll,
- .sta_add = rtl_op_sta_add,
- .sta_remove = rtl_op_sta_remove,
- .flush = rtl_op_flush,
-};
-
-bool rtl_btc_status_false(void)
-{
- return false;
-}
-
-void rtl_dm_diginit(struct ieee80211_hw *hw, u32 cur_igvalue)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
-
- dm_digtable->dig_enable_flag = true;
- dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
- dm_digtable->cur_igvalue = cur_igvalue;
- dm_digtable->pre_igvalue = 0;
- dm_digtable->cur_sta_cstate = DIG_STA_DISCONNECT;
- dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
- dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
- dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
- dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
- dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
- dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
- dm_digtable->rx_gain_max = DM_DIG_MAX;
- dm_digtable->rx_gain_min = DM_DIG_MIN;
- dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
- dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
- dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
- dm_digtable->pre_cck_cca_thres = 0xff;
- dm_digtable->cur_cck_cca_thres = 0x83;
- dm_digtable->forbidden_igi = DM_DIG_MIN;
- dm_digtable->large_fa_hit = 0;
- dm_digtable->recover_cnt = 0;
- dm_digtable->dig_min_0 = 0x25;
- dm_digtable->dig_min_1 = 0x25;
- dm_digtable->media_connect_0 = false;
- dm_digtable->media_connect_1 = false;
- rtlpriv->dm.dm_initialgain_enable = true;
- dm_digtable->bt30_cur_igi = 0x32;
- dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
- dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_CORE_H__
-#define __RTL_CORE_H__
-
-#define RTL_SUPPORTED_FILTERS \
- (FIF_ALLMULTI | FIF_CONTROL | \
- FIF_OTHER_BSS | \
- FIF_FCSFAIL | \
- FIF_BCN_PRBRESP_PROMISC)
-
-#define DM_DIG_THRESH_HIGH 40
-#define DM_DIG_THRESH_LOW 35
-#define DM_FALSEALARM_THRESH_LOW 400
-#define DM_FALSEALARM_THRESH_HIGH 1000
-
-#define DM_DIG_MAX 0x3e
-#define DM_DIG_MIN 0x1e
-#define DM_DIG_MAX_AP 0x32
-#define DM_DIG_BACKOFF_MAX 12
-#define DM_DIG_BACKOFF_MIN -4
-#define DM_DIG_BACKOFF_DEFAULT 10
-
-enum cck_packet_detection_threshold {
- CCK_PD_STAGE_LOWRSSI = 0,
- CCK_PD_STAGE_HIGHRSSI = 1,
- CCK_FA_STAGE_LOW = 2,
- CCK_FA_STAGE_HIGH = 3,
- CCK_PD_STAGE_MAX = 4,
-};
-
-enum dm_dig_ext_port_alg_e {
- DIG_EXT_PORT_STAGE_0 = 0,
- DIG_EXT_PORT_STAGE_1 = 1,
- DIG_EXT_PORT_STAGE_2 = 2,
- DIG_EXT_PORT_STAGE_3 = 3,
- DIG_EXT_PORT_STAGE_MAX = 4,
-};
-
-enum dm_dig_connect_e {
- DIG_STA_DISCONNECT,
- DIG_STA_CONNECT,
- DIG_STA_BEFORE_CONNECT,
- DIG_MULTISTA_DISCONNECT,
- DIG_MULTISTA_CONNECT,
- DIG_AP_DISCONNECT,
- DIG_AP_CONNECT,
- DIG_AP_ADD_STATION,
- DIG_CONNECT_MAX
-};
-
-extern const struct ieee80211_ops rtl_ops;
-void rtl_fw_cb(const struct firmware *firmware, void *context);
-void rtl_wowlan_fw_cb(const struct firmware *firmware, void *context);
-bool rtl_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb);
-bool rtl_btc_status_false(void);
-void rtl_dm_diginit(struct ieee80211_hw *hw, u32 cur_igval);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *****************************************************************************/
-
-#include "wifi.h"
-#include "cam.h"
-
-#include <linux/moduleparam.h>
-#include <linux/vmalloc.h>
-
-#ifdef CONFIG_RTLWIFI_DEBUG_ST
-void _rtl_dbg_trace(struct rtl_priv *rtlpriv, u64 comp, int level,
- const char *fmt, ...)
-{
- if (unlikely((comp & rtlpriv->cfg->mod_params->debug_mask) &&
- level <= rtlpriv->cfg->mod_params->debug_level)) {
- struct va_format vaf;
- va_list args;
-
- va_start(args, fmt);
-
- vaf.fmt = fmt;
- vaf.va = &args;
-
- pr_info(":<%lx> %pV", in_interrupt(), &vaf);
-
- va_end(args);
- }
-}
-
-void _rtl_dbg_print(struct rtl_priv *rtlpriv, u64 comp, int level,
- const char *fmt, ...)
-{
- if (unlikely((comp & rtlpriv->cfg->mod_params->debug_mask) &&
- level <= rtlpriv->cfg->mod_params->debug_level)) {
- struct va_format vaf;
- va_list args;
-
- va_start(args, fmt);
-
- vaf.fmt = fmt;
- vaf.va = &args;
-
- pr_info("%pV", &vaf);
-
- va_end(args);
- }
-}
-
-void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level,
- const char *titlestring,
- const void *hexdata, int hexdatalen)
-{
- if (unlikely(((comp) & rtlpriv->cfg->mod_params->debug_mask) &&
- ((level) <= rtlpriv->cfg->mod_params->debug_level))) {
- pr_info("In process \"%s\" (pid %i): %s\n",
- current->comm, current->pid, titlestring);
- print_hex_dump_bytes("", DUMP_PREFIX_NONE,
- hexdata, hexdatalen);
- }
-}
-
-struct rtl_debugfs_priv {
- struct rtl_priv *rtlpriv;
- int (*cb_read)(struct seq_file *m, void *v);
- ssize_t (*cb_write)(struct file *filp, const char __user *buffer,
- size_t count, loff_t *loff);
- u32 cb_data;
-};
-
-static struct dentry *debugfs_topdir;
-
-static int rtl_debug_get_common(struct seq_file *m, void *v)
-{
- struct rtl_debugfs_priv *debugfs_priv = m->private;
-
- return debugfs_priv->cb_read(m, v);
-}
-
-static int dl_debug_open_common(struct inode *inode, struct file *file)
-{
- return single_open(file, rtl_debug_get_common, inode->i_private);
-}
-
-static const struct file_operations file_ops_common = {
- .open = dl_debug_open_common,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int rtl_debug_get_mac_page(struct seq_file *m, void *v)
-{
- struct rtl_debugfs_priv *debugfs_priv = m->private;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
- u32 page = debugfs_priv->cb_data;
- int i, n;
- int max = 0xff;
-
- for (n = 0; n <= max; ) {
- seq_printf(m, "\n%8.8x ", n + page);
- for (i = 0; i < 4 && n <= max; i++, n += 4)
- seq_printf(m, "%8.8x ",
- rtl_read_dword(rtlpriv, (page | n)));
- }
- seq_puts(m, "\n");
- return 0;
-}
-
-#define RTL_DEBUG_IMPL_MAC_SERIES(page, addr) \
-static struct rtl_debugfs_priv rtl_debug_priv_mac_ ##page = { \
- .cb_read = rtl_debug_get_mac_page, \
- .cb_data = addr, \
-}
-
-RTL_DEBUG_IMPL_MAC_SERIES(0, 0x0000);
-RTL_DEBUG_IMPL_MAC_SERIES(1, 0x0100);
-RTL_DEBUG_IMPL_MAC_SERIES(2, 0x0200);
-RTL_DEBUG_IMPL_MAC_SERIES(3, 0x0300);
-RTL_DEBUG_IMPL_MAC_SERIES(4, 0x0400);
-RTL_DEBUG_IMPL_MAC_SERIES(5, 0x0500);
-RTL_DEBUG_IMPL_MAC_SERIES(6, 0x0600);
-RTL_DEBUG_IMPL_MAC_SERIES(7, 0x0700);
-RTL_DEBUG_IMPL_MAC_SERIES(10, 0x1000);
-RTL_DEBUG_IMPL_MAC_SERIES(11, 0x1100);
-RTL_DEBUG_IMPL_MAC_SERIES(12, 0x1200);
-RTL_DEBUG_IMPL_MAC_SERIES(13, 0x1300);
-RTL_DEBUG_IMPL_MAC_SERIES(14, 0x1400);
-RTL_DEBUG_IMPL_MAC_SERIES(15, 0x1500);
-RTL_DEBUG_IMPL_MAC_SERIES(16, 0x1600);
-RTL_DEBUG_IMPL_MAC_SERIES(17, 0x1700);
-
-static int rtl_debug_get_bb_page(struct seq_file *m, void *v)
-{
- struct rtl_debugfs_priv *debugfs_priv = m->private;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
- struct ieee80211_hw *hw = rtlpriv->hw;
- u32 page = debugfs_priv->cb_data;
- int i, n;
- int max = 0xff;
-
- for (n = 0; n <= max; ) {
- seq_printf(m, "\n%8.8x ", n + page);
- for (i = 0; i < 4 && n <= max; i++, n += 4)
- seq_printf(m, "%8.8x ",
- rtl_get_bbreg(hw, (page | n), 0xffffffff));
- }
- seq_puts(m, "\n");
- return 0;
-}
-
-#define RTL_DEBUG_IMPL_BB_SERIES(page, addr) \
-static struct rtl_debugfs_priv rtl_debug_priv_bb_ ##page = { \
- .cb_read = rtl_debug_get_bb_page, \
- .cb_data = addr, \
-}
-
-RTL_DEBUG_IMPL_BB_SERIES(8, 0x0800);
-RTL_DEBUG_IMPL_BB_SERIES(9, 0x0900);
-RTL_DEBUG_IMPL_BB_SERIES(a, 0x0a00);
-RTL_DEBUG_IMPL_BB_SERIES(b, 0x0b00);
-RTL_DEBUG_IMPL_BB_SERIES(c, 0x0c00);
-RTL_DEBUG_IMPL_BB_SERIES(d, 0x0d00);
-RTL_DEBUG_IMPL_BB_SERIES(e, 0x0e00);
-RTL_DEBUG_IMPL_BB_SERIES(f, 0x0f00);
-RTL_DEBUG_IMPL_BB_SERIES(18, 0x1800);
-RTL_DEBUG_IMPL_BB_SERIES(19, 0x1900);
-RTL_DEBUG_IMPL_BB_SERIES(1a, 0x1a00);
-RTL_DEBUG_IMPL_BB_SERIES(1b, 0x1b00);
-RTL_DEBUG_IMPL_BB_SERIES(1c, 0x1c00);
-RTL_DEBUG_IMPL_BB_SERIES(1d, 0x1d00);
-RTL_DEBUG_IMPL_BB_SERIES(1e, 0x1e00);
-RTL_DEBUG_IMPL_BB_SERIES(1f, 0x1f00);
-
-static int rtl_debug_get_reg_rf(struct seq_file *m, void *v)
-{
- struct rtl_debugfs_priv *debugfs_priv = m->private;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
- struct ieee80211_hw *hw = rtlpriv->hw;
- enum radio_path rfpath = debugfs_priv->cb_data;
- int i, n;
- int max = 0x40;
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- max = 0xff;
-
- seq_printf(m, "\nPATH(%d)", rfpath);
-
- for (n = 0; n <= max; ) {
- seq_printf(m, "\n%8.8x ", n);
- for (i = 0; i < 4 && n <= max; n += 1, i++)
- seq_printf(m, "%8.8x ",
- rtl_get_rfreg(hw, rfpath, n, 0xffffffff));
- }
- seq_puts(m, "\n");
- return 0;
-}
-
-#define RTL_DEBUG_IMPL_RF_SERIES(page, addr) \
-static struct rtl_debugfs_priv rtl_debug_priv_rf_ ##page = { \
- .cb_read = rtl_debug_get_reg_rf, \
- .cb_data = addr, \
-}
-
-RTL_DEBUG_IMPL_RF_SERIES(a, RF90_PATH_A);
-RTL_DEBUG_IMPL_RF_SERIES(b, RF90_PATH_B);
-
-static int rtl_debug_get_cam_register(struct seq_file *m, void *v)
-{
- struct rtl_debugfs_priv *debugfs_priv = m->private;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
- int start = debugfs_priv->cb_data;
- u32 target_cmd = 0;
- u32 target_val = 0;
- u8 entry_i = 0;
- u32 ulstatus;
- int i = 100, j = 0;
- int end = (start + 11 > TOTAL_CAM_ENTRY ? TOTAL_CAM_ENTRY : start + 11);
-
- /* This dump the current register page */
- seq_printf(m,
- "\n#################### SECURITY CAM (%d-%d) ##################\n",
- start, end - 1);
-
- for (j = start; j < end; j++) {
- seq_printf(m, "\nD: %2x > ", j);
- for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
- /* polling bit, and No Write enable, and address */
- target_cmd = entry_i + CAM_CONTENT_COUNT * j;
- target_cmd = target_cmd | BIT(31);
-
- /* Check polling bit is clear */
- while ((i--) >= 0) {
- ulstatus = rtl_read_dword(
- rtlpriv,
- rtlpriv->cfg->maps[RWCAM]);
- if (ulstatus & BIT(31))
- continue;
- else
- break;
- }
-
- rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
- target_cmd);
- target_val = rtl_read_dword(rtlpriv,
- rtlpriv->cfg->maps[RCAMO]);
- seq_printf(m, "%8.8x ", target_val);
- }
- }
- seq_puts(m, "\n");
- return 0;
-}
-
-#define RTL_DEBUG_IMPL_CAM_SERIES(page, addr) \
-static struct rtl_debugfs_priv rtl_debug_priv_cam_ ##page = { \
- .cb_read = rtl_debug_get_cam_register, \
- .cb_data = addr, \
-}
-
-RTL_DEBUG_IMPL_CAM_SERIES(1, 0);
-RTL_DEBUG_IMPL_CAM_SERIES(2, 11);
-RTL_DEBUG_IMPL_CAM_SERIES(3, 22);
-
-static int rtl_debug_get_btcoex(struct seq_file *m, void *v)
-{
- struct rtl_debugfs_priv *debugfs_priv = m->private;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
-
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_display_bt_coex_info(rtlpriv,
- m);
-
- seq_puts(m, "\n");
-
- return 0;
-}
-
-static struct rtl_debugfs_priv rtl_debug_priv_btcoex = {
- .cb_read = rtl_debug_get_btcoex,
- .cb_data = 0,
-};
-
-static ssize_t rtl_debugfs_set_write_reg(struct file *filp,
- const char __user *buffer,
- size_t count, loff_t *loff)
-{
- struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
- char tmp[32 + 1];
- int tmp_len;
- u32 addr, val, len;
- int num;
-
- if (count < 3)
- return -EFAULT;
-
- tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count);
-
- if (!buffer || copy_from_user(tmp, buffer, tmp_len))
- return count;
-
- tmp[tmp_len] = '\0';
-
- /* write BB/MAC register */
- num = sscanf(tmp, "%x %x %x", &addr, &val, &len);
-
- if (num != 3)
- return count;
-
- switch (len) {
- case 1:
- rtl_write_byte(rtlpriv, addr, (u8)val);
- break;
- case 2:
- rtl_write_word(rtlpriv, addr, (u16)val);
- break;
- case 4:
- rtl_write_dword(rtlpriv, addr, val);
- break;
- default:
- /*printk("error write length=%d", len);*/
- break;
- }
-
- return count;
-}
-
-static struct rtl_debugfs_priv rtl_debug_priv_write_reg = {
- .cb_write = rtl_debugfs_set_write_reg,
-};
-
-static ssize_t rtl_debugfs_set_write_h2c(struct file *filp,
- const char __user *buffer,
- size_t count, loff_t *loff)
-{
- struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
- struct ieee80211_hw *hw = rtlpriv->hw;
- char tmp[32 + 1];
- int tmp_len;
- u8 h2c_len, h2c_data_packed[8];
- int h2c_data[8]; /* idx 0: cmd */
- int i;
-
- if (count < 3)
- return -EFAULT;
-
- tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count);
-
- if (!buffer || copy_from_user(tmp, buffer, tmp_len))
- return count;
-
- tmp[tmp_len] = '\0';
-
- h2c_len = sscanf(tmp, "%X %X %X %X %X %X %X %X",
- &h2c_data[0], &h2c_data[1],
- &h2c_data[2], &h2c_data[3],
- &h2c_data[4], &h2c_data[5],
- &h2c_data[6], &h2c_data[7]);
-
- if (h2c_len <= 0)
- return count;
-
- for (i = 0; i < h2c_len; i++)
- h2c_data_packed[i] = (u8)h2c_data[i];
-
- rtlpriv->cfg->ops->fill_h2c_cmd(hw, h2c_data_packed[0],
- h2c_len - 1,
- &h2c_data_packed[1]);
-
- return count;
-}
-
-static struct rtl_debugfs_priv rtl_debug_priv_write_h2c = {
- .cb_write = rtl_debugfs_set_write_h2c,
-};
-
-static ssize_t rtl_debugfs_set_write_rfreg(struct file *filp,
- const char __user *buffer,
- size_t count, loff_t *loff)
-{
- struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
- struct ieee80211_hw *hw = rtlpriv->hw;
- char tmp[32 + 1];
- int tmp_len;
- int num;
- int path;
- u32 addr, bitmask, data;
-
- if (count < 3)
- return -EFAULT;
-
- tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count);
-
- if (!buffer || copy_from_user(tmp, buffer, tmp_len))
- return count;
-
- tmp[tmp_len] = '\0';
-
- num = sscanf(tmp, "%X %X %X %X",
- &path, &addr, &bitmask, &data);
-
- if (num != 4) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
- "Format is <path> <addr> <mask> <data>\n");
- return count;
- }
-
- rtl_set_rfreg(hw, path, addr, bitmask, data);
-
- return count;
-}
-
-static struct rtl_debugfs_priv rtl_debug_priv_write_rfreg = {
- .cb_write = rtl_debugfs_set_write_rfreg,
-};
-
-static int rtl_debugfs_close(struct inode *inode, struct file *filp)
-{
- return 0;
-}
-
-static ssize_t rtl_debugfs_common_write(struct file *filp,
- const char __user *buffer,
- size_t count, loff_t *loff)
-{
- struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
-
- return debugfs_priv->cb_write(filp, buffer, count, loff);
-}
-
-static const struct file_operations file_ops_common_write = {
- .owner = THIS_MODULE,
- .write = rtl_debugfs_common_write,
- .open = simple_open,
- .release = rtl_debugfs_close,
-};
-
-static ssize_t rtl_debugfs_phydm_cmd(struct file *filp,
- const char __user *buffer,
- size_t count, loff_t *loff)
-{
- struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
-
- char tmp[64];
-
- if (!rtlpriv->dbg.msg_buf)
- return -ENOMEM;
-
- if (!rtlpriv->phydm.ops)
- return -EFAULT;
-
- if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
- tmp[count] = '\0';
-
- rtlpriv->phydm.ops->phydm_debug_cmd(rtlpriv, tmp, count,
- rtlpriv->dbg.msg_buf,
- 80 * 25);
- }
-
- return count;
-}
-
-static int rtl_debug_get_phydm_cmd(struct seq_file *m, void *v)
-{
- struct rtl_debugfs_priv *debugfs_priv = m->private;
- struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
-
- if (rtlpriv->dbg.msg_buf)
- seq_puts(m, rtlpriv->dbg.msg_buf);
-
- return 0;
-}
-
-static int rtl_debugfs_open_rw(struct inode *inode, struct file *filp)
-{
- int ret = 0;
-
- if (filp->f_mode & FMODE_READ)
- ret = single_open(filp, rtl_debug_get_common, inode->i_private);
- else
- filp->private_data = inode->i_private;
-
- return ret;
-}
-
-static int rtl_debugfs_close_rw(struct inode *inode, struct file *filp)
-{
- if (filp->f_mode == FMODE_READ)
- single_release(inode, filp);
-
- return 0;
-}
-
-static struct rtl_debugfs_priv rtl_debug_priv_phydm_cmd = {
- .cb_read = rtl_debug_get_phydm_cmd,
- .cb_write = rtl_debugfs_phydm_cmd,
- .cb_data = 0,
-};
-
-static const struct file_operations file_ops_common_rw = {
- .owner = THIS_MODULE,
- .open = rtl_debugfs_open_rw,
- .release = rtl_debugfs_close_rw,
- .read = seq_read,
- .llseek = seq_lseek,
- .write = rtl_debugfs_common_write,
-};
-
-#define RTL_DEBUGFS_ADD_CORE(name, mode, fopname) \
- do { \
- rtl_debug_priv_ ##name.rtlpriv = rtlpriv; \
- debugfs_create_file(#name, mode, parent, \
- &rtl_debug_priv_ ##name, \
- &file_ops_ ##fopname); \
- } while (0)
-
-#define RTL_DEBUGFS_ADD(name) \
- RTL_DEBUGFS_ADD_CORE(name, S_IFREG | 0444, common)
-#define RTL_DEBUGFS_ADD_W(name) \
- RTL_DEBUGFS_ADD_CORE(name, S_IFREG | 0222, common_write)
-#define RTL_DEBUGFS_ADD_RW(name) \
- RTL_DEBUGFS_ADD_CORE(name, S_IFREG | 0666, common_rw)
-
-void rtl_debug_add_one(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- struct dentry *parent;
-
- rtlpriv->dbg.msg_buf = vzalloc(80 * 25);
-
- snprintf(rtlpriv->dbg.debugfs_name, 18, "%pMF", rtlefuse->dev_addr);
-
- rtlpriv->dbg.debugfs_dir =
- debugfs_create_dir(rtlpriv->dbg.debugfs_name, debugfs_topdir);
- if (!rtlpriv->dbg.debugfs_dir) {
- pr_err("Unable to init debugfs:/%s/%s\n", rtlpriv->cfg->name,
- rtlpriv->dbg.debugfs_name);
- return;
- }
-
- parent = rtlpriv->dbg.debugfs_dir;
-
- RTL_DEBUGFS_ADD(mac_0);
- RTL_DEBUGFS_ADD(mac_1);
- RTL_DEBUGFS_ADD(mac_2);
- RTL_DEBUGFS_ADD(mac_3);
- RTL_DEBUGFS_ADD(mac_4);
- RTL_DEBUGFS_ADD(mac_5);
- RTL_DEBUGFS_ADD(mac_6);
- RTL_DEBUGFS_ADD(mac_7);
- RTL_DEBUGFS_ADD(bb_8);
- RTL_DEBUGFS_ADD(bb_9);
- RTL_DEBUGFS_ADD(bb_a);
- RTL_DEBUGFS_ADD(bb_b);
- RTL_DEBUGFS_ADD(bb_c);
- RTL_DEBUGFS_ADD(bb_d);
- RTL_DEBUGFS_ADD(bb_e);
- RTL_DEBUGFS_ADD(bb_f);
- RTL_DEBUGFS_ADD(mac_10);
- RTL_DEBUGFS_ADD(mac_11);
- RTL_DEBUGFS_ADD(mac_12);
- RTL_DEBUGFS_ADD(mac_13);
- RTL_DEBUGFS_ADD(mac_14);
- RTL_DEBUGFS_ADD(mac_15);
- RTL_DEBUGFS_ADD(mac_16);
- RTL_DEBUGFS_ADD(mac_17);
- RTL_DEBUGFS_ADD(bb_18);
- RTL_DEBUGFS_ADD(bb_19);
- RTL_DEBUGFS_ADD(bb_1a);
- RTL_DEBUGFS_ADD(bb_1b);
- RTL_DEBUGFS_ADD(bb_1c);
- RTL_DEBUGFS_ADD(bb_1d);
- RTL_DEBUGFS_ADD(bb_1e);
- RTL_DEBUGFS_ADD(bb_1f);
- RTL_DEBUGFS_ADD(rf_a);
- RTL_DEBUGFS_ADD(rf_b);
-
- RTL_DEBUGFS_ADD(cam_1);
- RTL_DEBUGFS_ADD(cam_2);
- RTL_DEBUGFS_ADD(cam_3);
-
- RTL_DEBUGFS_ADD(btcoex);
-
- RTL_DEBUGFS_ADD_W(write_reg);
- RTL_DEBUGFS_ADD_W(write_h2c);
- RTL_DEBUGFS_ADD_W(write_rfreg);
-
- RTL_DEBUGFS_ADD_RW(phydm_cmd);
-}
-
-void rtl_debug_remove_one(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- debugfs_remove_recursive(rtlpriv->dbg.debugfs_dir);
- rtlpriv->dbg.debugfs_dir = NULL;
-
- vfree(rtlpriv->dbg.msg_buf);
-}
-
-void rtl_debugfs_add_topdir(void)
-{
- debugfs_topdir = debugfs_create_dir("rtlwifi", NULL);
-}
-
-void rtl_debugfs_remove_topdir(void)
-{
- debugfs_remove_recursive(debugfs_topdir);
-}
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *****************************************************************************/
-
-#ifndef __RTL_DEBUG_H__
-#define __RTL_DEBUG_H__
-
-/*--------------------------------------------------------------
- * Debug level
- *------------------------------------------------------------
- *
- *Fatal bug.
- *For example, Tx/Rx/IO locked up,
- *memory access violation,
- *resource allocation failed,
- *unexpected HW behavior, HW BUG
- *and so on.
- */
-/*#define DBG_EMERG 0 */
-
-/*Abnormal, rare, or unexpected cases.
- *For example, Packet/IO Ctl canceled,
- *device surprisingly removed and so on.
- */
-#define DBG_WARNING 2
-
-/*Normal case driver developer should
- *open, we can see link status like
- *assoc/AddBA/DHCP/adapter start and
- *so on basic and useful infromations.
- */
-#define DBG_DMESG 3
-
-/*Normal case with useful information
- *about current SW or HW state.
- *For example, Tx/Rx descriptor to fill,
- *Tx/Rx descriptor completed status,
- *SW protocol state change, dynamic
- *mechanism state change and so on.
- */
-#define DBG_LOUD 4
-
-/*Normal case with detail execution
- *flow or information.
- */
-#define DBG_TRACE 5
-
-/*--------------------------------------------------------------
- * Define the rt_trace components
- *--------------------------------------------------------------
- */
-#define COMP_ERR BIT(0)
-#define COMP_FW BIT(1)
-#define COMP_INIT BIT(2) /*For init/deinit */
-#define COMP_RECV BIT(3) /*For Rx. */
-#define COMP_SEND BIT(4) /*For Tx. */
-#define COMP_MLME BIT(5) /*For MLME. */
-#define COMP_SCAN BIT(6) /*For Scan. */
-#define COMP_INTR BIT(7) /*For interrupt Related. */
-#define COMP_LED BIT(8) /*For LED. */
-#define COMP_SEC BIT(9) /*For sec. */
-#define COMP_BEACON BIT(10) /*For beacon. */
-#define COMP_RATE BIT(11) /*For rate. */
-#define COMP_RXDESC BIT(12) /*For rx desc. */
-#define COMP_DIG BIT(13) /*For DIG */
-#define COMP_TXAGC BIT(14) /*For Tx power */
-#define COMP_HIPWR BIT(15) /*For High Power Mechanism */
-#define COMP_POWER BIT(16) /*For lps/ips/aspm. */
-#define COMP_POWER_TRACKING BIT(17) /*For TX POWER TRACKING */
-#define COMP_BB_POWERSAVING BIT(18)
-#define COMP_SWAS BIT(19) /*For SW Antenna Switch */
-#define COMP_RF BIT(20) /*For RF. */
-#define COMP_TURBO BIT(21) /*For EDCA TURBO. */
-#define COMP_RATR BIT(22)
-#define COMP_CMD BIT(23)
-#define COMP_EFUSE BIT(24)
-#define COMP_QOS BIT(25)
-#define COMP_MAC80211 BIT(26)
-#define COMP_REGD BIT(27)
-#define COMP_CHAN BIT(28)
-#define COMP_USB BIT(29)
-#define COMP_EASY_CONCURRENT COMP_USB /* reuse of this bit is OK */
-#define COMP_BT_COEXIST BIT(30)
-#define COMP_IQK BIT(31)
-#define COMP_TX_REPORT BIT_ULL(32)
-#define COMP_HALMAC BIT_ULL(34)
-#define COMP_PHYDM BIT_ULL(35)
-
-/*--------------------------------------------------------------
- * Define the rt_print components
- *--------------------------------------------------------------
- */
-/* Define EEPROM and EFUSE check module bit*/
-#define EEPROM_W BIT(0)
-#define EFUSE_PG BIT(1)
-#define EFUSE_READ_ALL BIT(2)
-
-/* Define init check for module bit*/
-#define INIT_EEPROM BIT(0)
-#define INIT_TXPOWER BIT(1)
-#define INIT_IQK BIT(2)
-#define INIT_RF BIT(3)
-
-/* Define PHY-BB/RF/MAC check module bit */
-#define PHY_BBR BIT(0)
-#define PHY_BBW BIT(1)
-#define PHY_RFR BIT(2)
-#define PHY_RFW BIT(3)
-#define PHY_MACR BIT(4)
-#define PHY_MACW BIT(5)
-#define PHY_ALLR BIT(6)
-#define PHY_ALLW BIT(7)
-#define PHY_TXPWR BIT(8)
-#define PHY_PWRDIFF BIT(9)
-
-/* Define Dynamic Mechanism check module bit --> FDM */
-#define WA_IOT BIT(0)
-#define DM_PWDB BIT(1)
-#define DM_MONITOR BIT(2)
-#define DM_DIG BIT(3)
-#define DM_EDCA_TURBO BIT(4)
-
-#define DM_PWDB BIT(1)
-
-enum dbgp_flag_e {
- FQOS = 0,
- FTX = 1,
- FRX = 2,
- FSEC = 3,
- FMGNT = 4,
- FMLME = 5,
- FRESOURCE = 6,
- FBEACON = 7,
- FISR = 8,
- FPHY = 9,
- FMP = 10,
- FEEPROM = 11,
- FPWR = 12,
- FDM = 13,
- FDBGCTRL = 14,
- FC2H = 15,
- FBT = 16,
- FINIT = 17,
- FIOCTL = 18,
- DBGP_TYPE_MAX
-};
-
-#ifdef CONFIG_RTLWIFI_DEBUG_ST
-
-struct rtl_priv;
-
-__printf(4, 5)
-void _rtl_dbg_trace(struct rtl_priv *rtlpriv, u64 comp, int level,
- const char *fmt, ...);
-
-__printf(4, 5)
-void _rtl_dbg_print(struct rtl_priv *rtlpriv, u64 comp, int level,
- const char *fmt, ...);
-
-void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level,
- const char *titlestring,
- const void *hexdata, int hexdatalen);
-
-#define RT_TRACE(rtlpriv, comp, level, fmt, ...) \
- _rtl_dbg_trace(rtlpriv, comp, level, \
- fmt, ##__VA_ARGS__)
-
-#define RTPRINT(rtlpriv, dbgtype, dbgflag, fmt, ...) \
- _rtl_dbg_print(rtlpriv, dbgtype, dbgflag, fmt, ##__VA_ARGS__)
-
-#define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
- _hexdatalen) \
- _rtl_dbg_print_data(rtlpriv, _comp, _level, \
- _titlestring, _hexdata, _hexdatalen)
-
-#else
-
-struct rtl_priv;
-
-__printf(4, 5)
-static inline void RT_TRACE(struct rtl_priv *rtlpriv,
- u64 comp, int level,
- const char *fmt, ...)
-{
-}
-
-__printf(4, 5)
-static inline void RTPRINT(struct rtl_priv *rtlpriv,
- int dbgtype, int dbgflag,
- const char *fmt, ...)
-{
-}
-
-static inline void RT_PRINT_DATA(struct rtl_priv *rtlpriv,
- u64 comp, int level,
- const char *titlestring,
- const void *hexdata, size_t hexdatalen)
-{
-}
-
-#endif
-
-#ifdef CONFIG_RTLWIFI_DEBUG_ST
-void rtl_debug_add_one(struct ieee80211_hw *hw);
-void rtl_debug_remove_one(struct ieee80211_hw *hw);
-void rtl_debugfs_add_topdir(void);
-void rtl_debugfs_remove_topdir(void);
-#else
-#define rtl_debug_add_one(hw)
-#define rtl_debug_remove_one(hw)
-#define rtl_debugfs_add_topdir()
-#define rtl_debugfs_remove_topdir()
-#endif
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "wifi.h"
-#include "efuse.h"
-#include "pci.h"
-#include <linux/export.h>
-
-static const u8 MAX_PGPKT_SIZE = 9;
-static const u8 PGPKT_DATA_SIZE = 8;
-static const int EFUSE_MAX_SIZE = 512;
-
-#define START_ADDRESS 0x1000
-#define REG_MCUFWDL 0x0080
-
-static const struct efuse_map RTL8712_SDIO_EFUSE_TABLE[] = {
- {0, 0, 0, 2},
- {0, 1, 0, 2},
- {0, 2, 0, 2},
- {1, 0, 0, 1},
- {1, 0, 1, 1},
- {1, 1, 0, 1},
- {1, 1, 1, 3},
- {1, 3, 0, 17},
- {3, 3, 1, 48},
- {10, 0, 0, 6},
- {10, 3, 0, 1},
- {10, 3, 1, 1},
- {11, 0, 0, 28}
-};
-
-static void efuse_shadow_read_1byte(struct ieee80211_hw *hw, u16 offset,
- u8 *value);
-static void efuse_shadow_read_2byte(struct ieee80211_hw *hw, u16 offset,
- u16 *value);
-static void efuse_shadow_read_4byte(struct ieee80211_hw *hw, u16 offset,
- u32 *value);
-static void efuse_shadow_write_1byte(struct ieee80211_hw *hw, u16 offset,
- u8 value);
-static void efuse_shadow_write_2byte(struct ieee80211_hw *hw, u16 offset,
- u16 value);
-static void efuse_shadow_write_4byte(struct ieee80211_hw *hw, u16 offset,
- u32 value);
-static int efuse_one_byte_write(struct ieee80211_hw *hw, u16 addr,
- u8 data);
-static void efuse_read_all_map(struct ieee80211_hw *hw, u8 *efuse);
-static int efuse_pg_packet_read(struct ieee80211_hw *hw, u8 offset,
- u8 *data);
-static int efuse_pg_packet_write(struct ieee80211_hw *hw, u8 offset,
- u8 word_en, u8 *data);
-static void efuse_word_enable_data_read(u8 word_en, u8 *sourdata,
- u8 *targetdata);
-static u8 enable_efuse_data_write(struct ieee80211_hw *hw,
- u16 efuse_addr, u8 word_en, u8 *data);
-static u16 efuse_get_current_size(struct ieee80211_hw *hw);
-static u8 efuse_calculate_word_cnts(u8 word_en);
-
-void efuse_initialize(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 bytetemp;
- u8 temp;
-
- bytetemp = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN] + 1);
- temp = bytetemp | 0x20;
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN] + 1, temp);
-
- bytetemp = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[SYS_ISO_CTRL] + 1);
- temp = bytetemp & 0xFE;
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[SYS_ISO_CTRL] + 1, temp);
-
- bytetemp = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3);
- temp = bytetemp | 0x80;
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3, temp);
-
- rtl_write_byte(rtlpriv, 0x2F8, 0x3);
-
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3, 0x72);
-}
-
-u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 data;
- u8 bytetemp;
- u8 temp;
- u32 k = 0;
- const u32 efuse_len =
- rtlpriv->cfg->maps[EFUSE_REAL_CONTENT_SIZE];
-
- if (address < efuse_len) {
- temp = address & 0xFF;
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
- temp);
- bytetemp = rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 2);
- temp = ((address >> 8) & 0x03) | (bytetemp & 0xFC);
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
- temp);
-
- bytetemp = rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
- temp = bytetemp & 0x7F;
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3,
- temp);
-
- bytetemp = rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
- while (!(bytetemp & 0x80)) {
- bytetemp =
- rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
- k++;
- if (k == 1000) {
- k = 0;
- break;
- }
- }
- data = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
- return data;
- }
- return 0xFF;
-}
-
-void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 bytetemp;
- u8 temp;
- u32 k = 0;
- const u32 efuse_len =
- rtlpriv->cfg->maps[EFUSE_REAL_CONTENT_SIZE];
-
- RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, "Addr=%x Data =%x\n",
- address, value);
-
- if (address < efuse_len) {
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL], value);
-
- temp = address & 0xFF;
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
- temp);
- bytetemp = rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 2);
-
- temp = ((address >> 8) & 0x03) | (bytetemp & 0xFC);
- rtl_write_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 2, temp);
-
- bytetemp = rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
- temp = bytetemp | 0x80;
- rtl_write_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 3, temp);
-
- bytetemp = rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
-
- while (bytetemp & 0x80) {
- bytetemp =
- rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
- k++;
- if (k == 100) {
- k = 0;
- break;
- }
- }
- }
-}
-
-void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u32 value32;
- u8 readbyte;
- u16 retry;
-
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
- (_offset & 0xff));
- readbyte = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2);
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
- ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
-
- readbyte = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3,
- (readbyte & 0x7f));
-
- retry = 0;
- value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
- while (!(((value32 >> 24) & 0xff) & 0x80) && (retry < 10000)) {
- value32 = rtl_read_dword(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL]);
- retry++;
- }
-
- udelay(50);
- value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
-
- *pbuf = (u8)(value32 & 0xff);
-}
-
-void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- u8 *efuse_tbl;
- u8 rtemp8[1];
- u16 efuse_addr = 0;
- u8 offset, wren;
- u8 u1temp = 0;
- u16 i;
- u16 j;
- const u16 efuse_max_section =
- rtlpriv->cfg->maps[EFUSE_MAX_SECTION_MAP];
- const u32 efuse_len =
- rtlpriv->cfg->maps[EFUSE_REAL_CONTENT_SIZE];
- u16 **efuse_word;
- u16 efuse_utilized = 0;
- u8 efuse_usage;
-
- if ((_offset + _size_byte) > rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]) {
- RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
- "%s(): Invalid offset(%#x) with read bytes(%#x)!!\n",
- __func__, _offset, _size_byte);
- return;
- }
-
- /* allocate memory for efuse_tbl and efuse_word */
- efuse_tbl = kzalloc(rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE],
- GFP_ATOMIC);
- if (!efuse_tbl)
- return;
- efuse_word = kcalloc(EFUSE_MAX_WORD_UNIT, sizeof(u16 *), GFP_ATOMIC);
- if (!efuse_word)
- goto out;
- for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
- efuse_word[i] = kcalloc(efuse_max_section, sizeof(u16),
- GFP_ATOMIC);
- if (!efuse_word[i])
- goto done;
- }
-
- for (i = 0; i < efuse_max_section; i++)
- for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
- efuse_word[j][i] = 0xFFFF;
-
- read_efuse_byte(hw, efuse_addr, rtemp8);
- if (*rtemp8 != 0xFF) {
- efuse_utilized++;
- RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
- "Addr=%d\n", efuse_addr);
- efuse_addr++;
- }
-
- while ((*rtemp8 != 0xFF) && (efuse_addr < efuse_len)) {
- /* Check PG header for section num. */
- if ((*rtemp8 & 0x1F) == 0x0F) {/* extended header */
- u1temp = ((*rtemp8 & 0xE0) >> 5);
- read_efuse_byte(hw, efuse_addr, rtemp8);
-
- if ((*rtemp8 & 0x0F) == 0x0F) {
- efuse_addr++;
- read_efuse_byte(hw, efuse_addr, rtemp8);
-
- if (*rtemp8 != 0xFF &&
- (efuse_addr < efuse_len)) {
- efuse_addr++;
- }
- continue;
- } else {
- offset = ((*rtemp8 & 0xF0) >> 1) | u1temp;
- wren = (*rtemp8 & 0x0F);
- efuse_addr++;
- }
- } else {
- offset = ((*rtemp8 >> 4) & 0x0f);
- wren = (*rtemp8 & 0x0f);
- }
-
- if (offset < efuse_max_section) {
- RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
- "offset-%d Worden=%x\n", offset, wren);
-
- for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
- if (!(wren & 0x01)) {
- RTPRINT(rtlpriv, FEEPROM,
- EFUSE_READ_ALL,
- "Addr=%d\n", efuse_addr);
-
- read_efuse_byte(hw, efuse_addr, rtemp8);
- efuse_addr++;
- efuse_utilized++;
- efuse_word[i][offset] =
- (*rtemp8 & 0xff);
-
- if (efuse_addr >= efuse_len)
- break;
-
- RTPRINT(rtlpriv, FEEPROM,
- EFUSE_READ_ALL,
- "Addr=%d\n", efuse_addr);
-
- read_efuse_byte(hw, efuse_addr, rtemp8);
- efuse_addr++;
- efuse_utilized++;
- efuse_word[i][offset] |=
- (((u16)*rtemp8 << 8) & 0xff00);
-
- if (efuse_addr >= efuse_len)
- break;
- }
-
- wren >>= 1;
- }
- }
-
- RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
- "Addr=%d\n", efuse_addr);
- read_efuse_byte(hw, efuse_addr, rtemp8);
- if (*rtemp8 != 0xFF && (efuse_addr < efuse_len)) {
- efuse_utilized++;
- efuse_addr++;
- }
- }
-
- for (i = 0; i < efuse_max_section; i++) {
- for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
- efuse_tbl[(i * 8) + (j * 2)] =
- (efuse_word[j][i] & 0xff);
- efuse_tbl[(i * 8) + ((j * 2) + 1)] =
- ((efuse_word[j][i] >> 8) & 0xff);
- }
- }
-
- for (i = 0; i < _size_byte; i++)
- pbuf[i] = efuse_tbl[_offset + i];
-
- rtlefuse->efuse_usedbytes = efuse_utilized;
- efuse_usage = (u8)((efuse_utilized * 100) / efuse_len);
- rtlefuse->efuse_usedpercentage = efuse_usage;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_EFUSE_BYTES,
- (u8 *)&efuse_utilized);
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_EFUSE_USAGE,
- &efuse_usage);
-done:
- for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++)
- kfree(efuse_word[i]);
- kfree(efuse_word);
-out:
- kfree(efuse_tbl);
-}
-
-bool efuse_shadow_update_chk(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- u8 section_idx, i, base;
- u16 words_need = 0, hdr_num = 0, totalbytes, efuse_used;
- bool wordchanged, result = true;
-
- for (section_idx = 0; section_idx < 16; section_idx++) {
- base = section_idx * 8;
- wordchanged = false;
-
- for (i = 0; i < 8; i = i + 2) {
- if ((rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] !=
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i]) ||
- (rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i + 1] !=
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i +
- 1])) {
- words_need++;
- wordchanged = true;
- }
- }
-
- if (wordchanged)
- hdr_num++;
- }
-
- totalbytes = hdr_num + words_need * 2;
- efuse_used = rtlefuse->efuse_usedbytes;
-
- if ((totalbytes + efuse_used) >=
- (EFUSE_MAX_SIZE - rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN]))
- result = false;
-
- RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
- "%s(): totalbytes(%#x), hdr_num(%#x), words_need(%#x), efuse_used(%d)\n",
- __func__, totalbytes, hdr_num, words_need, efuse_used);
-
- return result;
-}
-
-void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
- u16 offset, u32 *value)
-{
- if (type == 1)
- efuse_shadow_read_1byte(hw, offset, (u8 *)value);
- else if (type == 2)
- efuse_shadow_read_2byte(hw, offset, (u16 *)value);
- else if (type == 4)
- efuse_shadow_read_4byte(hw, offset, value);
-}
-
-void efuse_shadow_write(struct ieee80211_hw *hw, u8 type, u16 offset,
- u32 value)
-{
- if (type == 1)
- efuse_shadow_write_1byte(hw, offset, (u8)value);
- else if (type == 2)
- efuse_shadow_write_2byte(hw, offset, (u16)value);
- else if (type == 4)
- efuse_shadow_write_4byte(hw, offset, value);
-}
-
-bool efuse_shadow_update(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- u16 i, offset, base;
- u8 word_en = 0x0F;
- u8 first_pg = false;
-
- RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n");
-
- if (!efuse_shadow_update_chk(hw)) {
- efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]);
- memcpy(&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0],
- &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
- rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
-
- RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
- "efuse out of capacity!!\n");
- return false;
- }
- efuse_power_switch(hw, true, true);
-
- for (offset = 0; offset < 16; offset++) {
- word_en = 0x0F;
- base = offset * 8;
-
- for (i = 0; i < 8; i++) {
- if (first_pg) {
- word_en &= ~(BIT(i / 2));
-
- rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] =
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i];
- } else {
- if (rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] !=
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i]) {
- word_en &= ~(BIT(i / 2));
-
- rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] =
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i];
- }
- }
- }
- if (word_en != 0x0F) {
- u8 tmpdata[8];
-
- memcpy(tmpdata,
- &rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base],
- 8);
- RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD,
- "U-efuse\n", tmpdata, 8);
-
- if (!efuse_pg_packet_write(hw, (u8)offset, word_en,
- tmpdata)) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "PG section(%#x) fail!!\n", offset);
- break;
- }
- }
- }
-
- efuse_power_switch(hw, true, false);
- efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]);
-
- memcpy(&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0],
- &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
- rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
-
- RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n");
- return true;
-}
-
-void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
-
- if (rtlefuse->autoload_failflag)
- memset((&rtlefuse->efuse_map[EFUSE_INIT_MAP][0]),
- 0xFF, rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
- else
- efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]);
-
- memcpy(&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0],
- &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
- rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
-}
-
-void efuse_force_write_vendor_id(struct ieee80211_hw *hw)
-{
- u8 tmpdata[8] = { 0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF };
-
- efuse_power_switch(hw, true, true);
-
- efuse_pg_packet_write(hw, 1, 0xD, tmpdata);
-
- efuse_power_switch(hw, true, false);
-}
-
-void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx)
-{
-}
-
-static void efuse_shadow_read_1byte(struct ieee80211_hw *hw,
- u16 offset, u8 *value)
-{
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- *value = rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset];
-}
-
-static void efuse_shadow_read_2byte(struct ieee80211_hw *hw,
- u16 offset, u16 *value)
-{
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
-
- *value = rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset];
- *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] << 8;
-}
-
-static void efuse_shadow_read_4byte(struct ieee80211_hw *hw,
- u16 offset, u32 *value)
-{
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
-
- *value = rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset];
- *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] << 8;
- *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 2] << 16;
- *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 3] << 24;
-}
-
-static void efuse_shadow_write_1byte(struct ieee80211_hw *hw,
- u16 offset, u8 value)
-{
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
-
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset] = value;
-}
-
-static void efuse_shadow_write_2byte(struct ieee80211_hw *hw,
- u16 offset, u16 value)
-{
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
-
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset] = value & 0x00FF;
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] = value >> 8;
-}
-
-static void efuse_shadow_write_4byte(struct ieee80211_hw *hw,
- u16 offset, u32 value)
-{
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
-
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset] =
- (u8)(value & 0x000000FF);
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] =
- (u8)((value >> 8) & 0x0000FF);
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 2] =
- (u8)((value >> 16) & 0x00FF);
- rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 3] =
- (u8)((value >> 24) & 0xFF);
-}
-
-int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 tmpidx = 0;
- int result;
-
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
- (u8)(addr & 0xff));
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
- ((u8)((addr >> 8) & 0x03)) |
- (rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 2) &
- 0xFC));
-
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3, 0x72);
-
- while (!(0x80 & rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 3)) &&
- (tmpidx < 100)) {
- tmpidx++;
- }
-
- if (tmpidx < 100) {
- *data = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
- result = true;
- } else {
- *data = 0xff;
- result = false;
- }
- return result;
-}
-
-static int efuse_one_byte_write(struct ieee80211_hw *hw, u16 addr, u8 data)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 tmpidx = 0;
-
- RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
- "Addr = %x Data=%x\n", addr, data);
-
- rtl_write_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] + 1, (u8)(addr & 0xff));
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
- (rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_CTRL] +
- 2) & 0xFC) | (u8)((addr >> 8) & 0x03));
-
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL], data);
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3, 0xF2);
-
- while ((0x80 &
- rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3)) &&
- (tmpidx < 100)) {
- tmpidx++;
- }
-
- if (tmpidx < 100)
- return true;
- return false;
-}
-
-static void efuse_read_all_map(struct ieee80211_hw *hw, u8 *efuse)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- efuse_power_switch(hw, false, true);
- read_efuse(hw, 0, rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE], efuse);
- efuse_power_switch(hw, false, false);
-}
-
-static void efuse_read_data_case1(struct ieee80211_hw *hw, u16 *efuse_addr,
- u8 efuse_data, u8 offset, u8 *tmpdata,
- u8 *readstate)
-{
- bool dataempty = true;
- u8 hoffset;
- u8 tmpidx;
- u8 hworden;
- u8 word_cnts;
-
- hoffset = (efuse_data >> 4) & 0x0F;
- hworden = efuse_data & 0x0F;
- word_cnts = efuse_calculate_word_cnts(hworden);
-
- if (hoffset == offset) {
- for (tmpidx = 0; tmpidx < word_cnts * 2; tmpidx++) {
- if (efuse_one_byte_read(hw, *efuse_addr + 1 + tmpidx,
- &efuse_data)) {
- tmpdata[tmpidx] = efuse_data;
- if (efuse_data != 0xff)
- dataempty = false;
- }
- }
-
- if (!dataempty) {
- *readstate = PG_STATE_DATA;
- } else {
- *efuse_addr = *efuse_addr + (word_cnts * 2) + 1;
- *readstate = PG_STATE_HEADER;
- }
-
- } else {
- *efuse_addr = *efuse_addr + (word_cnts * 2) + 1;
- *readstate = PG_STATE_HEADER;
- }
-}
-
-static int efuse_pg_packet_read(struct ieee80211_hw *hw, u8 offset, u8 *data)
-{
- u8 readstate = PG_STATE_HEADER;
-
- bool continual = true;
-
- u8 efuse_data, word_cnts = 0;
- u16 efuse_addr = 0;
- u8 tmpdata[8];
-
- if (!data)
- return false;
- if (offset > 15)
- return false;
-
- memset(data, 0xff, PGPKT_DATA_SIZE * sizeof(u8));
- memset(tmpdata, 0xff, PGPKT_DATA_SIZE * sizeof(u8));
-
- while (continual && (efuse_addr < EFUSE_MAX_SIZE)) {
- if (readstate & PG_STATE_HEADER) {
- if (efuse_one_byte_read(hw, efuse_addr, &efuse_data) &&
- (efuse_data != 0xFF))
- efuse_read_data_case1(hw, &efuse_addr,
- efuse_data, offset,
- tmpdata, &readstate);
- else
- continual = false;
- } else if (readstate & PG_STATE_DATA) {
- efuse_word_enable_data_read(0, tmpdata, data);
- efuse_addr = efuse_addr + (word_cnts * 2) + 1;
- readstate = PG_STATE_HEADER;
- }
- }
-
- if ((data[0] == 0xff) && (data[1] == 0xff) &&
- (data[2] == 0xff) && (data[3] == 0xff) &&
- (data[4] == 0xff) && (data[5] == 0xff) &&
- (data[6] == 0xff) && (data[7] == 0xff))
- return false;
- return true;
-}
-
-static void efuse_write_data_case1(struct ieee80211_hw *hw, u16 *efuse_addr,
- u8 efuse_data, u8 offset,
- int *continual, u8 *write_state,
- struct pgpkt_struct *target_pkt,
- int *repeat_times, int *result, u8 word_en)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct pgpkt_struct tmp_pkt;
- int dataempty = true;
- u8 originaldata[8 * sizeof(u8)];
- u8 badworden = 0x0F;
- u8 match_word_en, tmp_word_en;
- u8 tmpindex;
- u8 tmp_header = efuse_data;
- u8 tmp_word_cnts;
-
- tmp_pkt.offset = (tmp_header >> 4) & 0x0F;
- tmp_pkt.word_en = tmp_header & 0x0F;
- tmp_word_cnts = efuse_calculate_word_cnts(tmp_pkt.word_en);
-
- if (tmp_pkt.offset != target_pkt->offset) {
- *efuse_addr = *efuse_addr + (tmp_word_cnts * 2) + 1;
- *write_state = PG_STATE_HEADER;
- } else {
- for (tmpindex = 0; tmpindex < (tmp_word_cnts * 2); tmpindex++) {
- if (efuse_one_byte_read(hw,
- (*efuse_addr + 1 + tmpindex),
- &efuse_data) &&
- (efuse_data != 0xFF))
- dataempty = false;
- }
-
- if (!dataempty) {
- *efuse_addr = *efuse_addr + (tmp_word_cnts * 2) + 1;
- *write_state = PG_STATE_HEADER;
- } else {
- match_word_en = 0x0F;
- if (!((target_pkt->word_en & BIT(0)) |
- (tmp_pkt.word_en & BIT(0))))
- match_word_en &= (~BIT(0));
-
- if (!((target_pkt->word_en & BIT(1)) |
- (tmp_pkt.word_en & BIT(1))))
- match_word_en &= (~BIT(1));
-
- if (!((target_pkt->word_en & BIT(2)) |
- (tmp_pkt.word_en & BIT(2))))
- match_word_en &= (~BIT(2));
-
- if (!((target_pkt->word_en & BIT(3)) |
- (tmp_pkt.word_en & BIT(3))))
- match_word_en &= (~BIT(3));
-
- if ((match_word_en & 0x0F) != 0x0F) {
- badworden =
- enable_efuse_data_write(hw,
- *efuse_addr + 1,
- tmp_pkt.word_en,
- target_pkt->data);
-
- if (0x0F != (badworden & 0x0F)) {
- u8 reorg_offset = offset;
- u8 reorg_worden = badworden;
-
- efuse_pg_packet_write(hw, reorg_offset,
- reorg_worden,
- originaldata);
- }
-
- tmp_word_en = 0x0F;
- if ((target_pkt->word_en & BIT(0)) ^
- (match_word_en & BIT(0)))
- tmp_word_en &= (~BIT(0));
-
- if ((target_pkt->word_en & BIT(1)) ^
- (match_word_en & BIT(1)))
- tmp_word_en &= (~BIT(1));
-
- if ((target_pkt->word_en & BIT(2)) ^
- (match_word_en & BIT(2)))
- tmp_word_en &= (~BIT(2));
-
- if ((target_pkt->word_en & BIT(3)) ^
- (match_word_en & BIT(3)))
- tmp_word_en &= (~BIT(3));
-
- if ((tmp_word_en & 0x0F) != 0x0F) {
- *efuse_addr =
- efuse_get_current_size(hw);
- target_pkt->offset = offset;
- target_pkt->word_en = tmp_word_en;
- } else {
- *continual = false;
- }
- *write_state = PG_STATE_HEADER;
- *repeat_times += 1;
- if (*repeat_times > EFUSE_REPEAT_THRESHOLD_) {
- *continual = false;
- *result = false;
- }
- } else {
- *efuse_addr += (2 * tmp_word_cnts) + 1;
- target_pkt->offset = offset;
- target_pkt->word_en = word_en;
- *write_state = PG_STATE_HEADER;
- }
- }
- }
- RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, "efuse PG_STATE_HEADER-1\n");
-}
-
-static void efuse_write_data_case2(struct ieee80211_hw *hw, u16 *efuse_addr,
- int *continual, u8 *write_state,
- struct pgpkt_struct target_pkt,
- int *repeat_times, int *result)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct pgpkt_struct tmp_pkt;
- u8 pg_header;
- u8 tmp_header;
- u8 originaldata[8 * sizeof(u8)];
- u8 tmp_word_cnts;
- u8 badworden = 0x0F;
-
- pg_header = ((target_pkt.offset << 4) & 0xf0) | target_pkt.word_en;
- efuse_one_byte_write(hw, *efuse_addr, pg_header);
- efuse_one_byte_read(hw, *efuse_addr, &tmp_header);
-
- if (tmp_header == pg_header) {
- *write_state = PG_STATE_DATA;
- } else if (tmp_header == 0xFF) {
- *write_state = PG_STATE_HEADER;
- *repeat_times += 1;
- if (*repeat_times > EFUSE_REPEAT_THRESHOLD_) {
- *continual = false;
- *result = false;
- }
- } else {
- tmp_pkt.offset = (tmp_header >> 4) & 0x0F;
- tmp_pkt.word_en = tmp_header & 0x0F;
-
- tmp_word_cnts = efuse_calculate_word_cnts(tmp_pkt.word_en);
-
- memset(originaldata, 0xff, 8 * sizeof(u8));
-
- if (efuse_pg_packet_read(hw, tmp_pkt.offset, originaldata)) {
- badworden = enable_efuse_data_write(hw,
- *efuse_addr + 1,
- tmp_pkt.word_en,
- originaldata);
-
- if (0x0F != (badworden & 0x0F)) {
- u8 reorg_offset = tmp_pkt.offset;
- u8 reorg_worden = badworden;
-
- efuse_pg_packet_write(hw, reorg_offset,
- reorg_worden,
- originaldata);
- *efuse_addr = efuse_get_current_size(hw);
- } else {
- *efuse_addr = *efuse_addr +
- (tmp_word_cnts * 2) + 1;
- }
- } else {
- *efuse_addr = *efuse_addr + (tmp_word_cnts * 2) + 1;
- }
-
- *write_state = PG_STATE_HEADER;
- *repeat_times += 1;
- if (*repeat_times > EFUSE_REPEAT_THRESHOLD_) {
- *continual = false;
- *result = false;
- }
-
- RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
- "efuse PG_STATE_HEADER-2\n");
- }
-}
-
-static int efuse_pg_packet_write(struct ieee80211_hw *hw,
- u8 offset, u8 word_en, u8 *data)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct pgpkt_struct target_pkt;
- u8 write_state = PG_STATE_HEADER;
- int continual = true, result = true;
- u16 efuse_addr = 0;
- u8 efuse_data;
- u8 target_word_cnts = 0;
- u8 badworden = 0x0F;
- static int repeat_times;
-
- if (efuse_get_current_size(hw) >= (EFUSE_MAX_SIZE -
- rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN])) {
- RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
- "%s error\n", __func__);
- return false;
- }
-
- target_pkt.offset = offset;
- target_pkt.word_en = word_en;
-
- memset(target_pkt.data, 0xFF, 8 * sizeof(u8));
-
- efuse_word_enable_data_read(word_en, data, target_pkt.data);
- target_word_cnts = efuse_calculate_word_cnts(target_pkt.word_en);
-
- RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, "efuse Power ON\n");
-
- while (continual && (efuse_addr < (EFUSE_MAX_SIZE -
- rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN]))) {
- if (write_state == PG_STATE_HEADER) {
- badworden = 0x0F;
- RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
- "efuse PG_STATE_HEADER\n");
-
- if (efuse_one_byte_read(hw, efuse_addr, &efuse_data) &&
- (efuse_data != 0xFF))
- efuse_write_data_case1(hw, &efuse_addr,
- efuse_data, offset,
- &continual,
- &write_state,
- &target_pkt,
- &repeat_times, &result,
- word_en);
- else
- efuse_write_data_case2(hw, &efuse_addr,
- &continual,
- &write_state,
- target_pkt,
- &repeat_times,
- &result);
-
- } else if (write_state == PG_STATE_DATA) {
- RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
- "efuse PG_STATE_DATA\n");
- badworden = 0x0f;
- badworden =
- enable_efuse_data_write(hw, efuse_addr + 1,
- target_pkt.word_en,
- target_pkt.data);
-
- if ((badworden & 0x0F) == 0x0F) {
- continual = false;
- } else {
- efuse_addr =
- efuse_addr + (2 * target_word_cnts) + 1;
-
- target_pkt.offset = offset;
- target_pkt.word_en = badworden;
- target_word_cnts =
- efuse_calculate_word_cnts(target_pkt.word_en);
- write_state = PG_STATE_HEADER;
- repeat_times++;
- if (repeat_times > EFUSE_REPEAT_THRESHOLD_) {
- continual = false;
- result = false;
- }
- RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
- "efuse PG_STATE_HEADER-3\n");
- }
- }
- }
-
- if (efuse_addr >= (EFUSE_MAX_SIZE -
- rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN])) {
- RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
- "efuse_addr(%#x) Out of size!!\n", efuse_addr);
- }
-
- return true;
-}
-
-static void efuse_word_enable_data_read(u8 word_en, u8 *sourdata,
- u8 *targetdata)
-{
- if (!(word_en & BIT(0))) {
- targetdata[0] = sourdata[0];
- targetdata[1] = sourdata[1];
- }
-
- if (!(word_en & BIT(1))) {
- targetdata[2] = sourdata[2];
- targetdata[3] = sourdata[3];
- }
-
- if (!(word_en & BIT(2))) {
- targetdata[4] = sourdata[4];
- targetdata[5] = sourdata[5];
- }
-
- if (!(word_en & BIT(3))) {
- targetdata[6] = sourdata[6];
- targetdata[7] = sourdata[7];
- }
-}
-
-static u8 enable_efuse_data_write(struct ieee80211_hw *hw,
- u16 efuse_addr, u8 word_en, u8 *data)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u16 tmpaddr;
- u16 start_addr = efuse_addr;
- u8 badworden = 0x0F;
- u8 tmpdata[8];
-
- memset(tmpdata, 0xff, PGPKT_DATA_SIZE);
- RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
- "word_en = %x efuse_addr=%x\n", word_en, efuse_addr);
-
- if (!(word_en & BIT(0))) {
- tmpaddr = start_addr;
- efuse_one_byte_write(hw, start_addr++, data[0]);
- efuse_one_byte_write(hw, start_addr++, data[1]);
-
- efuse_one_byte_read(hw, tmpaddr, &tmpdata[0]);
- efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[1]);
- if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
- badworden &= (~BIT(0));
- }
-
- if (!(word_en & BIT(1))) {
- tmpaddr = start_addr;
- efuse_one_byte_write(hw, start_addr++, data[2]);
- efuse_one_byte_write(hw, start_addr++, data[3]);
-
- efuse_one_byte_read(hw, tmpaddr, &tmpdata[2]);
- efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[3]);
- if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
- badworden &= (~BIT(1));
- }
-
- if (!(word_en & BIT(2))) {
- tmpaddr = start_addr;
- efuse_one_byte_write(hw, start_addr++, data[4]);
- efuse_one_byte_write(hw, start_addr++, data[5]);
-
- efuse_one_byte_read(hw, tmpaddr, &tmpdata[4]);
- efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[5]);
- if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
- badworden &= (~BIT(2));
- }
-
- if (!(word_en & BIT(3))) {
- tmpaddr = start_addr;
- efuse_one_byte_write(hw, start_addr++, data[6]);
- efuse_one_byte_write(hw, start_addr++, data[7]);
-
- efuse_one_byte_read(hw, tmpaddr, &tmpdata[6]);
- efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[7]);
- if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
- badworden &= (~BIT(3));
- }
-
- return badworden;
-}
-
-void efuse_power_switch(struct ieee80211_hw *hw, u8 write, u8 pwrstate)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- u8 tempval;
- u16 tmpv16;
-
- if (pwrstate && (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)) {
- if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192CE &&
- rtlhal->hw_type != HARDWARE_TYPE_RTL8192DE) {
- rtl_write_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_ACCESS], 0x69);
- } else {
- tmpv16 =
- rtl_read_word(rtlpriv,
- rtlpriv->cfg->maps[SYS_ISO_CTRL]);
- if (!(tmpv16 & rtlpriv->cfg->maps[EFUSE_PWC_EV12V])) {
- tmpv16 |= rtlpriv->cfg->maps[EFUSE_PWC_EV12V];
- rtl_write_word(rtlpriv,
- rtlpriv->cfg->maps[SYS_ISO_CTRL],
- tmpv16);
- }
- }
- tmpv16 = rtl_read_word(rtlpriv,
- rtlpriv->cfg->maps[SYS_FUNC_EN]);
- if (!(tmpv16 & rtlpriv->cfg->maps[EFUSE_FEN_ELDR])) {
- tmpv16 |= rtlpriv->cfg->maps[EFUSE_FEN_ELDR];
- rtl_write_word(rtlpriv,
- rtlpriv->cfg->maps[SYS_FUNC_EN], tmpv16);
- }
-
- tmpv16 = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[SYS_CLK]);
- if ((!(tmpv16 & rtlpriv->cfg->maps[EFUSE_LOADER_CLK_EN])) ||
- (!(tmpv16 & rtlpriv->cfg->maps[EFUSE_ANA8M]))) {
- tmpv16 |= (rtlpriv->cfg->maps[EFUSE_LOADER_CLK_EN] |
- rtlpriv->cfg->maps[EFUSE_ANA8M]);
- rtl_write_word(rtlpriv,
- rtlpriv->cfg->maps[SYS_CLK], tmpv16);
- }
- }
-
- if (pwrstate) {
- if (write) {
- tempval = rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_TEST] +
- 3);
-
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
- tempval &= ~(BIT(3) | BIT(4) | BIT(5) | BIT(6));
- tempval |= (VOLTAGE_V25 << 3);
- } else if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) {
- tempval &= 0x0F;
- tempval |= (VOLTAGE_V25 << 4);
- }
-
- rtl_write_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_TEST] + 3,
- (tempval | 0x80));
- }
-
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CLK],
- 0x03);
- }
- } else {
- if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192CE &&
- rtlhal->hw_type != HARDWARE_TYPE_RTL8192DE)
- rtl_write_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_ACCESS], 0);
-
- if (write) {
- tempval = rtl_read_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_TEST] +
- 3);
- rtl_write_byte(rtlpriv,
- rtlpriv->cfg->maps[EFUSE_TEST] + 3,
- (tempval & 0x7F));
- }
-
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CLK],
- 0x02);
- }
- }
-}
-
-static u16 efuse_get_current_size(struct ieee80211_hw *hw)
-{
- int continual = true;
- u16 efuse_addr = 0;
- u8 hworden;
- u8 efuse_data, word_cnts;
-
- while (continual && efuse_one_byte_read(hw, efuse_addr, &efuse_data) &&
- (efuse_addr < EFUSE_MAX_SIZE)) {
- if (efuse_data != 0xFF) {
- hworden = efuse_data & 0x0F;
- word_cnts = efuse_calculate_word_cnts(hworden);
- efuse_addr = efuse_addr + (word_cnts * 2) + 1;
- } else {
- continual = false;
- }
- }
-
- return efuse_addr;
-}
-
-static u8 efuse_calculate_word_cnts(u8 word_en)
-{
- u8 word_cnts = 0;
-
- if (!(word_en & BIT(0)))
- word_cnts++;
- if (!(word_en & BIT(1)))
- word_cnts++;
- if (!(word_en & BIT(2)))
- word_cnts++;
- if (!(word_en & BIT(3)))
- word_cnts++;
- return word_cnts;
-}
-
-int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv,
- int max_size, u8 *hwinfo, int *params)
-{
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
- struct device *dev = &rtlpcipriv->dev.pdev->dev;
- u16 eeprom_id;
- u16 i, usvalue;
-
- switch (rtlefuse->epromtype) {
- case EEPROM_BOOT_EFUSE:
- rtl_efuse_shadow_map_update(hw);
- break;
-
- case EEPROM_93C46:
- pr_err("RTL8XXX did not boot from eeprom, check it !!\n");
- return 1;
-
- default:
- dev_warn(dev, "no efuse data\n");
- return 1;
- }
-
- memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], max_size);
-
- RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
- hwinfo, max_size);
-
- eeprom_id = *((u16 *)&hwinfo[0]);
- if (eeprom_id != params[0]) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
- rtlefuse->autoload_failflag = true;
- } else {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
- rtlefuse->autoload_failflag = false;
- }
-
- if (rtlefuse->autoload_failflag)
- return 1;
-
- rtlefuse->eeprom_vid = *(u16 *)&hwinfo[params[1]];
- rtlefuse->eeprom_did = *(u16 *)&hwinfo[params[2]];
- rtlefuse->eeprom_svid = *(u16 *)&hwinfo[params[3]];
- rtlefuse->eeprom_smid = *(u16 *)&hwinfo[params[4]];
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "EEPROMId = 0x%4x\n", eeprom_id);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
-
- for (i = 0; i < 6; i += 2) {
- usvalue = *(u16 *)&hwinfo[params[5] + i];
- *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
- }
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
-
- rtlefuse->eeprom_channelplan = *&hwinfo[params[6]];
- rtlefuse->eeprom_version = *(u16 *)&hwinfo[params[7]];
- rtlefuse->txpwr_fromeprom = true;
- rtlefuse->eeprom_oemid = *&hwinfo[params[8]];
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
-
- /* set channel plan to world wide 13 */
- rtlefuse->channel_plan = params[9];
-
- return 0;
-}
-
-void rtl_fw_block_write(struct ieee80211_hw *hw, const u8 *buffer, u32 size)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 *pu4byteptr = (u8 *)buffer;
- u32 i;
-
- for (i = 0; i < size; i++)
- rtl_write_byte(rtlpriv, (START_ADDRESS + i), *(pu4byteptr + i));
-}
-
-void rtl_fw_page_write(struct ieee80211_hw *hw, u32 page, const u8 *buffer,
- u32 size)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 value8;
- u8 u8page = (u8)(page & 0x07);
-
- value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
-
- rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
- rtl_fw_block_write(hw, buffer, size);
-}
-
-void rtl_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
-{
- u32 fwlen = *pfwlen;
- u8 remain = (u8)(fwlen % 4);
-
- remain = (remain == 0) ? 0 : (4 - remain);
-
- while (remain > 0) {
- pfwbuf[fwlen] = 0;
- fwlen++;
- remain--;
- }
-
- *pfwlen = fwlen;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_EFUSE_H_
-#define __RTL_EFUSE_H_
-
-#define EFUSE_IC_ID_OFFSET 506
-
-#define EFUSE_MAX_WORD_UNIT 4
-
-#define EFUSE_INIT_MAP 0
-#define EFUSE_MODIFY_MAP 1
-
-#define PG_STATE_HEADER 0x01
-#define PG_STATE_WORD_0 0x02
-#define PG_STATE_WORD_1 0x04
-#define PG_STATE_WORD_2 0x08
-#define PG_STATE_WORD_3 0x10
-#define PG_STATE_DATA 0x20
-
-#define EFUSE_REPEAT_THRESHOLD_ 3
-#define EFUSE_ERROE_HANDLE 1
-
-struct efuse_map {
- u8 offset;
- u8 word_start;
- u8 byte_start;
- u8 byte_cnts;
-};
-
-struct pgpkt_struct {
- u8 offset;
- u8 word_en;
- u8 data[8];
-};
-
-enum efuse_data_item {
- EFUSE_CHIP_ID = 0,
- EFUSE_LDO_SETTING,
- EFUSE_CLK_SETTING,
- EFUSE_SDIO_SETTING,
- EFUSE_CCCR,
- EFUSE_SDIO_MODE,
- EFUSE_OCR,
- EFUSE_F0CIS,
- EFUSE_F1CIS,
- EFUSE_MAC_ADDR,
- EFUSE_EEPROM_VER,
- EFUSE_CHAN_PLAN,
- EFUSE_TXPW_TAB
-};
-
-enum {
- VOLTAGE_V25 = 0x03,
- LDOE25_SHIFT = 28,
-};
-
-struct efuse_priv {
- u8 id[2];
- u8 ldo_setting[2];
- u8 clk_setting[2];
- u8 cccr;
- u8 sdio_mode;
- u8 ocr[3];
- u8 cis0[17];
- u8 cis1[48];
- u8 mac_addr[6];
- u8 eeprom_verno;
- u8 channel_plan;
- u8 tx_power_b[14];
- u8 tx_power_g[14];
-};
-
-void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
-void efuse_initialize(struct ieee80211_hw *hw);
-u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address);
-int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data);
-void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value);
-void read_efuse(struct ieee80211_hw *hw, u16 _offset,
- u16 _size_byte, u8 *pbuf);
-void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
- u16 offset, u32 *value);
-void efuse_shadow_write(struct ieee80211_hw *hw, u8 type,
- u16 offset, u32 value);
-bool efuse_shadow_update(struct ieee80211_hw *hw);
-bool efuse_shadow_update_chk(struct ieee80211_hw *hw);
-void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw);
-void efuse_force_write_vendor_id(struct ieee80211_hw *hw);
-void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
-void efuse_power_switch(struct ieee80211_hw *hw, u8 write, u8 pwrstate);
-int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv,
- int max_size, u8 *hwinfo, int *params);
-void rtl_fill_dummy(u8 *pfwbuf, u32 *pfwlen);
-void rtl_fw_page_write(struct ieee80211_hw *hw, u32 page, const u8 *buffer,
- u32 size);
-void rtl_fw_block_write(struct ieee80211_hw *hw, const u8 *buffer, u32 size);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_2_PLATFORM_H_
-#define _HALMAC_2_PLATFORM_H_
-
-#include "../wifi.h"
-#include <asm/byteorder.h>
-
-#define HALMAC_PLATFORM_LITTLE_ENDIAN 1
-#define HALMAC_PLATFORM_BIG_ENDIAN 0
-
-/* Note : Named HALMAC_PLATFORM_LITTLE_ENDIAN / HALMAC_PLATFORM_BIG_ENDIAN
- * is not mandatory. But Little endian must be '1'. Big endian must be '0'
- */
-#if defined(__LITTLE_ENDIAN)
-#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_LITTLE_ENDIAN
-#elif defined(__BIG_ENDIAN)
-#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_BIG_ENDIAN
-#else
-#error
-#endif
-
-/* define the Platform SDIO Bus CLK */
-#define PLATFORM_SD_CLK 50000000 /*50MHz*/
-
-/* define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */
-/* Should be 8 Byte alignment */
-#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 16 /*Bytes*/
-
-#endif /* _HALMAC_2_PLATFORM_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_8822B_CFG_H_
-#define _HALMAC_8822B_CFG_H_
-
-#include "halmac_8822b_pwr_seq.h"
-#include "halmac_api_8822b.h"
-#include "halmac_api_8822b_usb.h"
-#include "halmac_api_8822b_sdio.h"
-#include "halmac_api_8822b_pcie.h"
-#include "../../halmac_bit2.h"
-#include "../../halmac_reg2.h"
-#include "../../halmac_api.h"
-
-#define HALMAC_TX_FIFO_SIZE_8822B 262144 /* 256k */
-#define HALMAC_TX_FIFO_SIZE_LA_8822B 131072 /* 128k */
-#define HALMAC_RX_FIFO_SIZE_8822B 24576 /* 24k */
-#define HALMAC_TX_PAGE_SIZE_8822B 128 /* PageSize 128Byte */
-#define HALMAC_TX_ALIGN_SIZE_8822B 8
-#define HALMAC_TX_PAGE_SIZE_2_POWER_8822B 7 /* 128 = 2^7 */
-#define HALMAC_SECURITY_CAM_ENTRY_NUM_8822B 64 /* CAM Entry size */
-#define HALMAC_TX_AGG_ALIGNMENT_SIZE_8822B 8
-#define HALMAC_TX_DESC_SIZE_8822B 48
-#define HALMAC_RX_DESC_SIZE_8822B 24
-#define HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B 120
-#define HALMAC_C2H_PKT_BUF_8822B 256
-#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B 80 /* align 8 Byte*/
-#define HALMAC_RX_FIFO_EXPANDING_UNIT_8822B \
- (HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + \
- HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE) /* align 8 Byte*/
-#define HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B \
- (HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + \
- HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B) /* align 8 Byte*/
-
-#define HALMAC_TX_FIFO_SIZE_EX_1_BLK_8822B 196608 /* 192k */
-#define HALMAC_RX_FIFO_SIZE_EX_1_BLK_8822B \
- ((((HALMAC_RX_FIFO_EXPANDING_UNIT_8822B << 8) - 1) >> 10) \
- << 10) /* < 56k*/
-#define HALMAC_RX_FIFO_SIZE_EX_1_BLK_MAX_8822B \
- ((((HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B << 8) - 1) >> 10) \
- << 10) /* 55k*/
-#define HALMAC_TX_FIFO_SIZE_EX_2_BLK_8822B 131072 /* 128k */
-#define HALMAC_RX_FIFO_SIZE_EX_2_BLK_8822B 155648 /* 152k */
-#define HALMAC_TX_FIFO_SIZE_EX_3_BLK_8822B 65536 /* 64k */
-#define HALMAC_RX_FIFO_SIZE_EX_3_BLK_8822B 221184 /* 216k */
-
-/* TXFIFO LAYOUT
- * HIGH_QUEUE
- * NORMAL_QUEUE
- * LOW_QUEUE
- * EXTRA_QUEUE
- * PUBLIC_QUEUE -- decided after all other queue are defined
- * GAP_QUEUE -- Used to separate AC queue and Rsvd page
- *
- * RSVD_DRIVER -- Driver used rsvd page area
- * RSVD_H2C_EXTRAINFO -- Extra Information for h2c
- * RSVD_H2C_QUEUE -- h2c queue in rsvd page
- * RSVD_CPU_INSTRUCTION -- extend fw code
- * RSVD_FW_TXBUFF -- fw used this area to send packet
- *
- * Symbol: HALMAC_MODE_QUEUE_UNIT_CHIP, ex: HALMAC_LB_2BULKOUT_FWCMD_PGNUM_8822B
- */
-#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_8822B \
- 16384 /*16K, only used in init case*/
-
-#define HALMAC_RSVD_DRV_PGNUM_8822B 16 /*2048*/
-#define HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B 32 /*4096*/
-#define HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B 8 /*1024*/
-#define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B 0 /*0*/
-#define HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B 4 /*512*/
-
-#define HALMAC_EFUSE_SIZE_8822B 1024 /* 0x400 */
-#define HALMAC_BT_EFUSE_SIZE_8822B 128 /* 0x80 */
-#define HALMAC_EEPROM_SIZE_8822B 0x300
-#define HALMAC_CR_TRX_ENABLE_8822B \
- (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | BIT_RXDMA_EN | \
- BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | BIT_MACTXEN | BIT_MACRXEN)
-
-#define HALMAC_BLK_DESC_NUM_8822B 0x3 /* Only for USB */
-
-/* AMPDU max time (unit : 32us) */
-#define HALMAC_AMPDU_MAX_TIME_8822B 0x70
-
-/* Protect mode control */
-#define HALMAC_PROT_RTS_LEN_TH_8822B 0xFF
-#define HALMAC_PROT_RTS_TX_TIME_TH_8822B 0x08
-#define HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B 0x20
-#define HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B 0x20
-
-/* Fast EDCA setting */
-#define HALMAC_FAST_EDCA_VO_TH_8822B 0x06
-#define HALMAC_FAST_EDCA_VI_TH_8822B 0x06
-#define HALMAC_FAST_EDCA_BE_TH_8822B 0x06
-#define HALMAC_FAST_EDCA_BK_TH_8822B 0x06
-
-/* BAR setting */
-#define HALMAC_BAR_RETRY_LIMIT_8822B 0x01
-#define HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B 0x08
-
-enum halmac_normal_rxagg_th_to_8822b {
- HALMAC_NORMAL_RXAGG_THRESHOLD_8822B = 0xFF,
- HALMAC_NORMAL_RXAGG_TIMEOUT_8822B = 0x01,
-};
-
-enum halmac_loopback_rxagg_th_to_8822b {
- HALMAC_LOOPBACK_RXAGG_THRESHOLD_8822B = 0xFF,
- HALMAC_LOOPBACK_RXAGG_TIMEOUT_8822B = 0x01,
-};
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "../halmac_88xx_cfg.h"
-#include "halmac_8822b_cfg.h"
-
-/**
- * ============ip sel item list============
- * HALMAC_IP_SEL_INTF_PHY
- * USB2 : usb2 phy, 1byte value
- * USB3 : usb3 phy, 2byte value
- * PCIE1 : pcie gen1 mdio, 2byte value
- * PCIE2 : pcie gen2 mdio, 2byte value
- * HALMAC_IP_SEL_MAC
- * USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value
- * HALMAC_IP_SEL_PCIE_DBI
- * USB2 USB3 : none
- * PCIE1, PCIE2 : pcie dbi, 1byte value
- */
-
-struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB2_PHY[] = {
- /* {offset, value, ip sel, cut mask, platform mask} */
- {0xFFFF, 0x00, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
- HALMAC_INTF_PHY_PLATFORM_ALL},
-};
-
-struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB3_PHY[] = {
- /* {offset, value, ip sel, cut mask, platform mask} */
- {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_D,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
- HALMAC_INTF_PHY_PLATFORM_ALL},
-};
-
-struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN1[] = {
- /* {offset, value, ip sel, cut mask, platform mask} */
- {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0008, 0x3596, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x002A, 0x1840, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
- HALMAC_INTF_PHY_PLATFORM_ALL},
-};
-
-struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN2[] = {
- /* {offset, value, ip sel, cut mask, platform mask} */
- {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0008, 0x3597, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0x002A, 0x3040, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
- HALMAC_INTF_PHY_PLATFORM_ALL},
- {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
- HALMAC_INTF_PHY_PLATFORM_ALL},
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "../halmac_88xx_cfg.h"
-#include "halmac_8822b_cfg.h"
-
-static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT[] = {
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
- {0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), 0}, /*SWR OCP = SWR OCP = 010 1382.40*/
- {0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), BIT(0)}, /*SWR OCP = 010 1382.40 */
- {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
- HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0),
- BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/
- {0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
- HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1,
- HALMAC_PWRSEQ_DELAY_MS}, /*Delay 1ms*/
- {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
- HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5),
- 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- (BIT(4) | BIT(3) | BIT(2)),
- 0}, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/
- {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), BIT(0)}, /* Disable USB suspend */
- {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, BIT(1),
- BIT(1)}, /* wait till 0x04[17] = 1 power ready*/
- {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), 0}, /* Enable USB suspend */
- {0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0}, /*0xFF1A = 0 to release resume signals*/
- {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(7), 0}, /* disable HWPDN 0x04[15]=0*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- (BIT(4) | BIT(3)), 0}, /* disable WL suspend*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), BIT(0)}, /* polling until return 0*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, BIT(0), 0},
- {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(3), BIT(3)}, /*Enable XTAL_CLK*/
- {0x10A8, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0}, /*NFC pad enabled*/
- {0x10A9, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xef}, /*NFC pad enabled*/
- {0x10AA, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x0c}, /*NFC pad enabled*/
- {0x0068, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO pad power down disabled*/
- {0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xF9}, /*PLL seting*/
- {0x0024, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(2), 0}, /*Improve TX EVM of CH13 and some 5G channles */
- {0x0074, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(5), BIT(5)}, /*PCIE WAKE# enabled*/
- {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
-};
-
-static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU[] = {
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
- {0x0003, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*0x02[10] = 0 Disable MCU Core*/
- {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(3), 0}, /*LPS option 0x93[3]=0 , SWR PFM*/
- {0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/
- {0x00EF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0}, /*0xEF[7:0] = 0 turn off RF*/
- {0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x30}, /*0xFF1A = 0x30 to block resume signals*/
- {0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), 0}, /*Enable rising edge triggering interrupt*/
- {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), 0}, /* Whole BB is reset */
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, BIT(1),
- 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
- {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(3), 0}, /* XTAL_CLK gated*/
- {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
- HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5),
- BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/
- {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
-};
-
-static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS[] = {
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(4) | BIT(3),
- (BIT(4) | BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
- HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4),
- BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/
- {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, 0xFF,
- 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(3) | BIT(4),
- BIT(3) | BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
- {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, BIT(0),
- BIT(0)}, /*Set SDIO suspend local register*/
- {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
- {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
-};
-
-static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU[] = {
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/
- {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
- {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_POLLING, BIT(1),
- BIT(1)}, /*wait power state to suspend*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
- {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
-};
-
-static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS[] = {
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(7),
- BIT(7)}, /*suspend enable and power down enable*/
- {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
- HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF,
- 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/
- {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(5), 0}, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
- HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4),
- BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/
- {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
- {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(5),
- 0}, /* 0: BT PAPE control ; 1: WL BB LNAON control*/
- {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(4),
- 0}, /* 0: BT GPIO[11:10] control ; 1: WL BB LNAON control*/
- {0x004F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* 0: BT Control*/
- {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(1),
- 0}, /* turn off BT_3DD_SYNC_B and BT_GPIO[18] */
- {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)}, /* GPIO[6] : Output mode*/
- {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /* turn off BT_GPIO[16] */
- {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /* GPIO[7] : Output mode*/
- {0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* GPIO[12] : Output mode */
- {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, BIT(0),
- BIT(0)}, /*Set SDIO suspend local register*/
- {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
- {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK,
- HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1),
- 0}, /*0x90[1]=0 , disable 32k clock*/
- {0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, 0xFF,
- 0}, /*0x90[1]=0 , disable 32k clock by indirect access*/
- {0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, 0xFF,
- 0x90}, /*0x90[1]=0 , disable 32k clock by indirect access*/
- {0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, 0xFF,
- 0x00}, /*0x90[1]=0 , disable 32k clock by indirect access*/
- {0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, 0xFF,
- 0x04}, /*0x90[1]=0 , disable 32k clock by indirect access*/
- {0x0081, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(7), 0}, /*0x80[15]clean fw init ready bit*/
- {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
-};
-
-static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU[] = {
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
- {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
- {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_POLLING, BIT(1),
- BIT(1)}, /*wait power state to suspend*/
- {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
- {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(3) | BIT(4) | BIT(7),
- 0}, /*clear suspend enable and power down enable*/
- {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0},
- {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
-};
-
-static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_LPS[] = {
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
- {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
- {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
- {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
- {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
- {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), BIT(0)}, /* enable 32K CLK*/
- {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x42}, /* LPS Option MAC OFF enable*/
- {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/
- {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
- {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xFF}, /*PCIe DMA stop*/
- {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xFF}, /*Tx Pause*/
- {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, 0xFF,
- 0}, /*Should be zero if no packet is transmitting*/
- {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, 0xFF,
- 0}, /*Should be zero if no packet is transmitting*/
- {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, 0xFF,
- 0}, /*Should be zero if no packet is transmitting*/
- {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, 0xFF,
- 0}, /*Should be zero if no packet is transmitting*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
- 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), 0}, /*Whole BB is reset*/
- {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x3F}, /*Reset MAC TRX*/
- {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), 0}, /*check if removed later*/
- {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
- {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
- {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, BIT(7),
- BIT(7)}, /*Polling 0x109[7]=0 TSF in 40M*/
- {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
- {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
-};
-
-static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS[] = {
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
- {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
- {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
- {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
- {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
- {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), BIT(0)}, /* enable 32K CLK*/
- {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x40}, /* LPS Option MAC OFF enable*/
- {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/
- {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
- {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xFF}, /*PCIe DMA stop*/
- {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xFF}, /*Tx Pause*/
- {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, 0xFF,
- 0}, /*Should be zero if no packet is transmitting*/
- {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, 0xFF,
- 0}, /*Should be zero if no packet is transmitting*/
- {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, 0xFF,
- 0}, /*Should be zero if no packet is transmitting*/
- {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, 0xFF,
- 0}, /*Should be zero if no packet is transmitting*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
- 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), 0}, /*Whole BB is reset*/
- {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x3F}, /*Reset MAC TRX*/
- {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), 0}, /*check if removed later*/
- {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
- {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
- {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, BIT(7),
- BIT(7)}, /*Polling 0x109[7]=1 TSF in 32K*/
- {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
- {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
-};
-
-static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_LPS_TO_ACT[] = {
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
- {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*SDIO RPWM*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
- 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
- {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
- HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*SDIO RPWM*/
- {0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x84}, /*USB RPWM*/
- {0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x84}, /*PCIe RPWM*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
- 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
- {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(4), 0}, /* switch TSF to 40M*/
- {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
- HALMAC_PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/
- {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), BIT(1)},
- {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xFF}, /*nable WMAC TRX*/
- {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1) | BIT(0), BIT(1) | BIT(0)}, /*nable BB macro*/
- {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0},
- {0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0x03}, /*clear RPWM INT*/
- {0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xFF}, /*clear FW INT*/
- {0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xFF}, /*clear FW INT*/
- {0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xFF}, /*clear FW INT*/
- {0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- 0xFF, 0xFF}, /*clear FW INT*/
- {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(1), 0}, /* disable reg use 32K CLK*/
- {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
- BIT(2), 0}, /*disable 32k calibration and thermal meter*/
- {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
- HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
-};
-
-/* Card Enable Array */
-struct halmac_wl_pwr_cfg_ *halmac_8822b_card_enable_flow[] = {
- HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU,
- HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, NULL};
-
-/* Card Disable Array */
-struct halmac_wl_pwr_cfg_ *halmac_8822b_card_disable_flow[] = {
- HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU,
- HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS, NULL};
-
-/* Suspend Array */
-struct halmac_wl_pwr_cfg_ *halmac_8822b_suspend_flow[] = {
- HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU,
- HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS, NULL};
-
-/* Resume Array */
-struct halmac_wl_pwr_cfg_ *halmac_8822b_resume_flow[] = {
- HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU,
- HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, NULL};
-
-/* HWPDN Array - HW behavior */
-struct halmac_wl_pwr_cfg_ *halmac_8822b_hwpdn_flow[] = {NULL};
-
-/* Enter LPS - FW behavior */
-struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_lps_flow[] = {
- HALMAC_RTL8822B_TRANS_ACT_TO_LPS, NULL};
-
-/* Enter Deep LPS - FW behavior */
-struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_deep_lps_flow[] = {
- HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS, NULL};
-
-/* Leave LPS -FW behavior */
-struct halmac_wl_pwr_cfg_ *halmac_8822b_leave_lps_flow[] = {
- HALMAC_RTL8822B_TRANS_LPS_TO_ACT, NULL};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef HALMAC_POWER_SEQUENCE_8822B
-#define HALMAC_POWER_SEQUENCE_8822B
-
-#include "../../halmac_pwr_seq_cmd.h"
-
-#define HALMAC_8822B_PWR_SEQ_VER "V17"
-extern struct halmac_wl_pwr_cfg_ *halmac_8822b_card_disable_flow[];
-extern struct halmac_wl_pwr_cfg_ *halmac_8822b_card_enable_flow[];
-extern struct halmac_wl_pwr_cfg_ *halmac_8822b_suspend_flow[];
-extern struct halmac_wl_pwr_cfg_ *halmac_8822b_resume_flow[];
-extern struct halmac_wl_pwr_cfg_ *halmac_8822b_hwpdn_flow[];
-extern struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_lps_flow[];
-extern struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_deep_lps_flow[];
-extern struct halmac_wl_pwr_cfg_ *halmac_8822b_leave_lps_flow[];
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halmac_8822b_cfg.h"
-#include "halmac_func_8822b.h"
-#include "../halmac_func_88xx.h"
-
-/**
- * halmac_mount_api_8822b() - attach functions to function pointer
- * @halmac_adapter
- *
- * SD1 internal use
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- */
-enum halmac_ret_status
-halmac_mount_api_8822b(struct halmac_adapter *halmac_adapter)
-{
- struct halmac_api *halmac_api =
- (struct halmac_api *)halmac_adapter->halmac_api;
-
- halmac_adapter->chip_id = HALMAC_CHIP_ID_8822B;
- halmac_adapter->hw_config_info.efuse_size = HALMAC_EFUSE_SIZE_8822B;
- halmac_adapter->hw_config_info.eeprom_size = HALMAC_EEPROM_SIZE_8822B;
- halmac_adapter->hw_config_info.bt_efuse_size =
- HALMAC_BT_EFUSE_SIZE_8822B;
- halmac_adapter->hw_config_info.cam_entry_num =
- HALMAC_SECURITY_CAM_ENTRY_NUM_8822B;
- halmac_adapter->hw_config_info.txdesc_size = HALMAC_TX_DESC_SIZE_8822B;
- halmac_adapter->hw_config_info.rxdesc_size = HALMAC_RX_DESC_SIZE_8822B;
- halmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_8822B;
- halmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_8822B;
- halmac_adapter->hw_config_info.page_size = HALMAC_TX_PAGE_SIZE_8822B;
- halmac_adapter->hw_config_info.tx_align_size =
- HALMAC_TX_ALIGN_SIZE_8822B;
- halmac_adapter->hw_config_info.page_size_2_power =
- HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
-
- halmac_adapter->txff_allocation.rsvd_drv_pg_num =
- HALMAC_RSVD_DRV_PGNUM_8822B;
-
- halmac_api->halmac_init_trx_cfg = halmac_init_trx_cfg_8822b;
- halmac_api->halmac_init_protocol_cfg = halmac_init_protocol_cfg_8822b;
- halmac_api->halmac_init_h2c = halmac_init_h2c_8822b;
-
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- halmac_api->halmac_tx_allowed_sdio =
- halmac_tx_allowed_sdio_88xx;
- halmac_api->halmac_cfg_tx_agg_align =
- halmac_cfg_tx_agg_align_sdio_not_support_88xx;
- halmac_api->halmac_mac_power_switch =
- halmac_mac_power_switch_8822b_sdio;
- halmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_sdio;
- halmac_api->halmac_interface_integration_tuning =
- halmac_interface_integration_tuning_8822b_sdio;
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
- halmac_api->halmac_mac_power_switch =
- halmac_mac_power_switch_8822b_usb;
- halmac_api->halmac_cfg_tx_agg_align =
- halmac_cfg_tx_agg_align_usb_not_support_88xx;
- halmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_usb;
- halmac_api->halmac_interface_integration_tuning =
- halmac_interface_integration_tuning_8822b_usb;
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
- halmac_api->halmac_mac_power_switch =
- halmac_mac_power_switch_8822b_pcie;
- halmac_api->halmac_cfg_tx_agg_align =
- halmac_cfg_tx_agg_align_pcie_not_support_88xx;
- halmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b;
- halmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_pcie;
- halmac_api->halmac_interface_integration_tuning =
- halmac_interface_integration_tuning_8822b_pcie;
- } else {
- halmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b_nc;
- }
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_trx_cfg_8822b() - config trx dma register
- * @halmac_adapter : the adapter of halmac
- * @halmac_trx_mode : trx mode selection
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_trx_cfg_8822b(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode)
-{
- u8 value8;
- u32 value32;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_TRX_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
- halmac_adapter->trx_mode = halmac_trx_mode;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_init_trx_cfg ==========>halmac_trx_mode = %d\n",
- halmac_trx_mode);
-
- status = halmac_txdma_queue_mapping_8822b(halmac_adapter,
- halmac_trx_mode);
-
- if (status != HALMAC_RET_SUCCESS) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_txdma_queue_mapping fail!\n");
- return status;
- }
-
- value8 = 0;
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
- value8 = HALMAC_CR_TRX_ENABLE_8822B;
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_H2CQ_CSR, BIT(31));
-
- status = halmac_priority_queue_config_8822b(halmac_adapter,
- halmac_trx_mode);
- if (halmac_adapter->txff_allocation.rx_fifo_expanding_mode !=
- HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RX_DRVINFO_SZ, 0xF);
-
- if (status != HALMAC_RET_SUCCESS) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_txdma_queue_mapping fail!\n");
- return status;
- }
-
- /* Config H2C packet buffer */
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_HEAD);
- value32 = (value32 & 0xFFFC0000) |
- (halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_HEAD, value32);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_READ_ADDR);
- value32 = (value32 & 0xFFFC0000) |
- (halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_READ_ADDR, value32);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_TAIL);
- value32 = (value32 & 0xFFFC0000) |
- ((halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B) +
- (HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B));
- HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_TAIL, value32);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
- value8 = (u8)((value8 & 0xFC) | 0x01);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
- value8 = (u8)((value8 & 0xFB) | 0x04);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
- value8 = (u8)((value8 & 0x7f) | 0x80);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
-
- halmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
- halmac_get_h2c_buff_free_space_88xx(halmac_adapter);
-
- if (halmac_adapter->h2c_buff_size !=
- halmac_adapter->h2c_buf_free_space) {
- pr_err("get h2c free space error!\n");
- return HALMAC_RET_GET_H2C_SPACE_ERR;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_init_trx_cfg <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_protocol_cfg_8822b() - config protocol register
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_protocol_cfg_8822b(struct halmac_adapter *halmac_adapter)
-{
- u32 value32;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_PROTOCOL_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]%s ==========>\n", __func__);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_AMPDU_MAX_TIME_V1,
- HALMAC_AMPDU_MAX_TIME_8822B);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
-
- value32 = HALMAC_PROT_RTS_LEN_TH_8822B |
- (HALMAC_PROT_RTS_TX_TIME_TH_8822B << 8) |
- (HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B << 16) |
- (HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B << 24);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_PROT_MODE_CTRL, value32);
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_BAR_MODE_CTRL + 2,
- HALMAC_BAR_RETRY_LIMIT_8822B |
- HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B << 8);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_VOVI_SETTING,
- HALMAC_FAST_EDCA_VO_TH_8822B);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_VOVI_SETTING + 2,
- HALMAC_FAST_EDCA_VI_TH_8822B);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_BEBK_SETTING,
- HALMAC_FAST_EDCA_BE_TH_8822B);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_BEBK_SETTING + 2,
- HALMAC_FAST_EDCA_BK_TH_8822B);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_h2c_8822b() - config h2c packet buffer
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_h2c_8822b(struct halmac_adapter *halmac_adapter)
-{
- u8 value8;
- u32 value32;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- value8 = 0;
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
- value8 = HALMAC_CR_TRX_ENABLE_8822B;
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_HEAD);
- value32 = (value32 & 0xFFFC0000) |
- (halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_HEAD, value32);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_READ_ADDR);
- value32 = (value32 & 0xFFFC0000) |
- (halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_READ_ADDR, value32);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_TAIL);
- value32 = (value32 & 0xFFFC0000) |
- ((halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B) +
- (HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B));
- HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_TAIL, value32);
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
- value8 = (u8)((value8 & 0xFC) | 0x01);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
- value8 = (u8)((value8 & 0xFB) | 0x04);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
- value8 = (u8)((value8 & 0x7f) | 0x80);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
-
- halmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
- << HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
- halmac_get_h2c_buff_free_space_88xx(halmac_adapter);
-
- if (halmac_adapter->h2c_buff_size !=
- halmac_adapter->h2c_buf_free_space) {
- pr_err("get h2c free space error!\n");
- return HALMAC_RET_GET_H2C_SPACE_ERR;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "h2c free space : %d\n",
- halmac_adapter->h2c_buf_free_space);
-
- return HALMAC_RET_SUCCESS;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_API_8822B_H_
-#define _HALMAC_API_8822B_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-enum halmac_ret_status
-halmac_mount_api_8822b(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_init_trx_cfg_8822b(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode);
-
-enum halmac_ret_status
-halmac_init_protocol_cfg_8822b(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_init_h2c_8822b(struct halmac_adapter *halmac_adapter);
-
-#endif /* _HALMAC_API_8822B_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "../halmac_88xx_cfg.h"
-#include "../halmac_api_88xx_pcie.h"
-#include "halmac_8822b_cfg.h"
-
-/**
- * halmac_mac_power_switch_8822b_pcie() - switch mac power
- * @halmac_adapter : the adapter of halmac
- * @halmac_power : power state
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_mac_power_switch_8822b_pcie(struct halmac_adapter *halmac_adapter,
- enum halmac_mac_power halmac_power)
-{
- u8 interface_mask;
- u8 value8;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_mac_power_switch_88xx_pcie halmac_power = %x ==========>\n",
- halmac_power);
- interface_mask = HALMAC_PWR_INTF_PCI_MSK;
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR);
- if (value8 == 0xEA)
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
- else
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
-
- /* Check if power switch is needed */
- if (halmac_power == HALMAC_MAC_POWER_ON &&
- halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_PWR, DBG_WARNING,
- "halmac_mac_power_switch power state unchange!\n");
- return HALMAC_RET_PWR_UNCHANGE;
- }
-
- if (halmac_power == HALMAC_MAC_POWER_OFF) {
- if (halmac_pwr_seq_parser_88xx(
- halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
- HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
- halmac_8822b_card_disable_flow) !=
- HALMAC_RET_SUCCESS) {
- pr_err("Handle power off cmd error\n");
- return HALMAC_RET_POWER_OFF_FAIL;
- }
-
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
- halmac_adapter->halmac_state.ps_state =
- HALMAC_PS_STATE_UNDEFINE;
- halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
- halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
- } else {
- if (halmac_pwr_seq_parser_88xx(
- halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
- HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
- halmac_8822b_card_enable_flow) !=
- HALMAC_RET_SUCCESS) {
- pr_err("Handle power on cmd error\n");
- return HALMAC_RET_POWER_ON_FAIL;
- }
-
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
- halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_mac_power_switch_88xx_pcie <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_pcie_switch_8822b() - pcie gen1/gen2 switch
- * @halmac_adapter : the adapter of halmac
- * @pcie_cfg : gen1/gen2 selection
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_pcie_switch_8822b(struct halmac_adapter *halmac_adapter,
- enum halmac_pcie_cfg pcie_cfg)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- u8 current_link_speed = 0;
- u32 count = 0;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PCIE_SWITCH);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- /* Link Control 2 Register[3:0] Target Link Speed
- * Defined encodings are:
- * 0001b Target Link 2.5 GT/s
- * 0010b Target Link 5.0 GT/s
- * 0100b Target Link 8.0 GT/s
- */
-
- if (pcie_cfg == HALMAC_PCIE_GEN1) {
- /* cfg 0xA0[3:0]=4'b0001 */
- halmac_dbi_write8_88xx(
- halmac_adapter, LINK_CTRL2_REG_OFFSET,
- (halmac_dbi_read8_88xx(halmac_adapter,
- LINK_CTRL2_REG_OFFSET) &
- 0xF0) | BIT(0));
-
- /* cfg 0x80C[17]=1 //PCIe DesignWave */
- halmac_dbi_write32_88xx(
- halmac_adapter, GEN2_CTRL_OFFSET,
- halmac_dbi_read32_88xx(halmac_adapter,
- GEN2_CTRL_OFFSET) |
- BIT(17));
-
- /* check link speed if GEN1 */
- /* cfg 0x82[3:0]=4'b0001 */
- current_link_speed =
- halmac_dbi_read8_88xx(halmac_adapter,
- LINK_STATUS_REG_OFFSET) &
- 0x0F;
- count = 2000;
-
- while (current_link_speed != GEN1_SPEED && count != 0) {
- usleep_range(50, 60);
- current_link_speed =
- halmac_dbi_read8_88xx(halmac_adapter,
- LINK_STATUS_REG_OFFSET) &
- 0x0F;
- count--;
- }
-
- if (current_link_speed != GEN1_SPEED) {
- pr_err("Speed change to GEN1 fail !\n");
- return HALMAC_RET_FAIL;
- }
-
- } else if (pcie_cfg == HALMAC_PCIE_GEN2) {
- /* cfg 0xA0[3:0]=4'b0010 */
- halmac_dbi_write8_88xx(
- halmac_adapter, LINK_CTRL2_REG_OFFSET,
- (halmac_dbi_read8_88xx(halmac_adapter,
- LINK_CTRL2_REG_OFFSET) &
- 0xF0) | BIT(1));
-
- /* cfg 0x80C[17]=1 //PCIe DesignWave */
- halmac_dbi_write32_88xx(
- halmac_adapter, GEN2_CTRL_OFFSET,
- halmac_dbi_read32_88xx(halmac_adapter,
- GEN2_CTRL_OFFSET) |
- BIT(17));
-
- /* check link speed if GEN2 */
- /* cfg 0x82[3:0]=4'b0010 */
- current_link_speed =
- halmac_dbi_read8_88xx(halmac_adapter,
- LINK_STATUS_REG_OFFSET) &
- 0x0F;
- count = 2000;
-
- while (current_link_speed != GEN2_SPEED && count != 0) {
- usleep_range(50, 60);
- current_link_speed =
- halmac_dbi_read8_88xx(halmac_adapter,
- LINK_STATUS_REG_OFFSET) &
- 0x0F;
- count--;
- }
-
- if (current_link_speed != GEN2_SPEED) {
- pr_err("Speed change to GEN1 fail !\n");
- return HALMAC_RET_FAIL;
- }
-
- } else {
- pr_err("Error Speed !\n");
- return HALMAC_RET_FAIL;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_pcie_switch_8822b_nc(struct halmac_adapter *halmac_adapter,
- enum halmac_pcie_cfg pcie_cfg)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PCIE_SWITCH);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_phy_cfg_8822b_pcie() - phy config
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_phy_cfg_8822b_pcie(struct halmac_adapter *halmac_adapter,
- enum halmac_intf_phy_platform platform)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PHY_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_phy_cfg ==========>\n");
-
- status = halmac_parse_intf_phy_88xx(halmac_adapter,
- HALMAC_RTL8822B_PCIE_PHY_GEN1,
- platform, HAL_INTF_PHY_PCIE_GEN1);
-
- if (status != HALMAC_RET_SUCCESS)
- return status;
-
- status = halmac_parse_intf_phy_88xx(halmac_adapter,
- HALMAC_RTL8822B_PCIE_PHY_GEN2,
- platform, HAL_INTF_PHY_PCIE_GEN2);
-
- if (status != HALMAC_RET_SUCCESS)
- return status;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_phy_cfg <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_interface_integration_tuning_8822b_pcie() - pcie interface fine tuning
- * @halmac_adapter : the adapter of halmac
- * Author : Rick Liu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_interface_integration_tuning_8822b_pcie(
- struct halmac_adapter *halmac_adapter)
-{
- return HALMAC_RET_SUCCESS;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_API_8822B_PCIE_H_
-#define _HALMAC_API_8822B_PCIE_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN1[];
-extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN2[];
-
-enum halmac_ret_status
-halmac_mac_power_switch_8822b_pcie(struct halmac_adapter *halmac_adapter,
- enum halmac_mac_power halmac_power);
-
-enum halmac_ret_status
-halmac_pcie_switch_8822b(struct halmac_adapter *halmac_adapter,
- enum halmac_pcie_cfg pcie_cfg);
-
-enum halmac_ret_status
-halmac_pcie_switch_8822b_nc(struct halmac_adapter *halmac_adapter,
- enum halmac_pcie_cfg pcie_cfg);
-
-enum halmac_ret_status
-halmac_phy_cfg_8822b_pcie(struct halmac_adapter *halmac_adapter,
- enum halmac_intf_phy_platform platform);
-
-enum halmac_ret_status halmac_interface_integration_tuning_8822b_pcie(
- struct halmac_adapter *halmac_adapter);
-
-#endif /* _HALMAC_API_8822B_PCIE_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halmac_8822b_cfg.h"
-
-/**
- * halmac_mac_power_switch_8822b_sdio() - switch mac power
- * @halmac_adapter : the adapter of halmac
- * @halmac_power : power state
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_mac_power_switch_8822b_sdio(struct halmac_adapter *halmac_adapter,
- enum halmac_mac_power halmac_power)
-{
- u8 interface_mask;
- u8 value8;
- u8 rpwm;
- u32 imr_backup;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "[TRACE]halmac_mac_power_switch_88xx_sdio==========>\n");
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "[TRACE]halmac_power = %x ==========>\n", halmac_power);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "[TRACE]8822B pwr seq ver = %s\n",
- HALMAC_8822B_PWR_SEQ_VER);
-
- interface_mask = HALMAC_PWR_INTF_SDIO_MSK;
-
- halmac_adapter->rpwm_record =
- HALMAC_REG_READ_8(halmac_adapter, REG_SDIO_HRPWM1);
-
- /* Check FW still exist or not */
- if (HALMAC_REG_READ_16(halmac_adapter, REG_MCUFW_CTRL) == 0xC078) {
- /* Leave 32K */
- rpwm = (u8)((halmac_adapter->rpwm_record ^ BIT(7)) & 0x80);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SDIO_HRPWM1, rpwm);
- }
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR);
- if (value8 == 0xEA)
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
- else
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
-
- /*Check if power switch is needed*/
- if (halmac_power == HALMAC_MAC_POWER_ON &&
- halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_PWR, DBG_WARNING,
- "[WARN]halmac_mac_power_switch power state unchange!\n");
- return HALMAC_RET_PWR_UNCHANGE;
- }
-
- imr_backup = HALMAC_REG_READ_32(halmac_adapter, REG_SDIO_HIMR);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR, 0);
-
- if (halmac_power == HALMAC_MAC_POWER_OFF) {
- if (halmac_pwr_seq_parser_88xx(
- halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
- HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
- halmac_8822b_card_disable_flow) !=
- HALMAC_RET_SUCCESS) {
- pr_err("[ERR]Handle power off cmd error\n");
- HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR,
- imr_backup);
- return HALMAC_RET_POWER_OFF_FAIL;
- }
-
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
- halmac_adapter->halmac_state.ps_state =
- HALMAC_PS_STATE_UNDEFINE;
- halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
- halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
- } else {
- if (halmac_pwr_seq_parser_88xx(
- halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
- HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
- halmac_8822b_card_enable_flow) !=
- HALMAC_RET_SUCCESS) {
- pr_err("[ERR]Handle power on cmd error\n");
- HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR,
- imr_backup);
- return HALMAC_RET_POWER_ON_FAIL;
- }
-
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
- halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
- }
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR, imr_backup);
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "[TRACE]halmac_mac_power_switch_88xx_sdio <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_phy_cfg_8822b_sdio() - phy config
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_phy_cfg_8822b_sdio(struct halmac_adapter *halmac_adapter,
- enum halmac_intf_phy_platform platform)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PHY_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_phy_cfg ==========>\n");
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "sdio no phy\n");
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_phy_cfg <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_interface_integration_tuning_8822b_sdio() - sdio interface fine tuning
- * @halmac_adapter : the adapter of halmac
- * Author : Ivan
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_interface_integration_tuning_8822b_sdio(
- struct halmac_adapter *halmac_adapter)
-{
- return HALMAC_RET_SUCCESS;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_API_8822B_SDIO_H_
-#define _HALMAC_API_8822B_SDIO_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-enum halmac_ret_status
-halmac_mac_power_switch_8822b_sdio(struct halmac_adapter *halmac_adapter,
- enum halmac_mac_power halmac_power);
-
-enum halmac_ret_status
-halmac_phy_cfg_8822b_sdio(struct halmac_adapter *halmac_adapter,
- enum halmac_intf_phy_platform platform);
-
-enum halmac_ret_status halmac_interface_integration_tuning_8822b_sdio(
- struct halmac_adapter *halmac_adapter);
-
-#endif /* _HALMAC_API_8822B_SDIO_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "../halmac_88xx_cfg.h"
-#include "halmac_8822b_cfg.h"
-
-/**
- * halmac_mac_power_switch_8822b_usb() - switch mac power
- * @halmac_adapter : the adapter of halmac
- * @halmac_power : power state
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_mac_power_switch_8822b_usb(struct halmac_adapter *halmac_adapter,
- enum halmac_mac_power halmac_power)
-{
- u8 interface_mask;
- u8 value8;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_mac_power_switch_88xx_usb halmac_power = %x ==========>\n",
- halmac_power);
-
- interface_mask = HALMAC_PWR_INTF_USB_MSK;
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR);
- if (value8 == 0xEA) {
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
- } else {
- if (BIT(0) ==
- (HALMAC_REG_READ_8(halmac_adapter, REG_SYS_STATUS1 + 1) &
- BIT(0)))
- halmac_adapter->halmac_state.mac_power =
- HALMAC_MAC_POWER_OFF;
- else
- halmac_adapter->halmac_state.mac_power =
- HALMAC_MAC_POWER_ON;
- }
-
- /*Check if power switch is needed*/
- if (halmac_power == HALMAC_MAC_POWER_ON &&
- halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_PWR, DBG_WARNING,
- "halmac_mac_power_switch power state unchange!\n");
- return HALMAC_RET_PWR_UNCHANGE;
- }
- if (halmac_power == HALMAC_MAC_POWER_OFF) {
- if (halmac_pwr_seq_parser_88xx(
- halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
- HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
- halmac_8822b_card_disable_flow) !=
- HALMAC_RET_SUCCESS) {
- pr_err("Handle power off cmd error\n");
- return HALMAC_RET_POWER_OFF_FAIL;
- }
-
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
- halmac_adapter->halmac_state.ps_state =
- HALMAC_PS_STATE_UNDEFINE;
- halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
- halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
- } else {
- if (halmac_pwr_seq_parser_88xx(
- halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
- HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
- halmac_8822b_card_enable_flow) !=
- HALMAC_RET_SUCCESS) {
- pr_err("Handle power on cmd error\n");
- return HALMAC_RET_POWER_ON_FAIL;
- }
-
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_SYS_STATUS1 + 1,
- HALMAC_REG_READ_8(halmac_adapter, REG_SYS_STATUS1 + 1) &
- ~(BIT(0)));
-
- halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
- halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_mac_power_switch_88xx_usb <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_phy_cfg_8822b_usb() - phy config
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_phy_cfg_8822b_usb(struct halmac_adapter *halmac_adapter,
- enum halmac_intf_phy_platform platform)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PHY_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_phy_cfg ==========>\n");
-
- status = halmac_parse_intf_phy_88xx(halmac_adapter,
- HALMAC_RTL8822B_USB2_PHY, platform,
- HAL_INTF_PHY_USB2);
-
- if (status != HALMAC_RET_SUCCESS)
- return status;
-
- status = halmac_parse_intf_phy_88xx(halmac_adapter,
- HALMAC_RTL8822B_USB3_PHY, platform,
- HAL_INTF_PHY_USB3);
-
- if (status != HALMAC_RET_SUCCESS)
- return status;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "halmac_phy_cfg <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_interface_integration_tuning_8822b_usb() - usb interface fine tuning
- * @halmac_adapter : the adapter of halmac
- * Author : Ivan
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_interface_integration_tuning_8822b_usb(
- struct halmac_adapter *halmac_adapter)
-{
- return HALMAC_RET_SUCCESS;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_API_8822B_USB_H_
-#define _HALMAC_API_8822B_USB_H_
-
-extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB2_PHY[];
-extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB3_PHY[];
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-enum halmac_ret_status
-halmac_mac_power_switch_8822b_usb(struct halmac_adapter *halmac_adapter,
- enum halmac_mac_power halmac_power);
-
-enum halmac_ret_status
-halmac_phy_cfg_8822b_usb(struct halmac_adapter *halmac_adapter,
- enum halmac_intf_phy_platform platform);
-
-enum halmac_ret_status halmac_interface_integration_tuning_8822b_usb(
- struct halmac_adapter *halmac_adapter);
-
-#endif /* _HALMAC_API_8822B_USB_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halmac_8822b_cfg.h"
-#include "halmac_func_8822b.h"
-
-/*SDIO RQPN Mapping*/
-static struct halmac_rqpn_ HALMAC_RQPN_SDIO_8822B[] = {
- /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
- {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
-};
-
-/*PCIE RQPN Mapping*/
-static struct halmac_rqpn_ HALMAC_RQPN_PCIE_8822B[] = {
- /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
- {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
-};
-
-/*USB 2 Bulkout RQPN Mapping*/
-static struct halmac_rqpn_ HALMAC_RQPN_2BULKOUT_8822B[] = {
- /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
- {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
- HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
- HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
- HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
-};
-
-/*USB 3 Bulkout RQPN Mapping*/
-static struct halmac_rqpn_ HALMAC_RQPN_3BULKOUT_8822B[] = {
- /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
- {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
-};
-
-/*USB 4 Bulkout RQPN Mapping*/
-static struct halmac_rqpn_ HALMAC_RQPN_4BULKOUT_8822B[] = {
- /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
- {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
- HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
-};
-
-/*SDIO Page Number*/
-static struct halmac_pg_num_ HALMAC_PG_NUM_SDIO_8822B[] = {
- /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
- {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1},
- {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
-};
-
-/*PCIE Page Number*/
-static struct halmac_pg_num_ HALMAC_PG_NUM_PCIE_8822B[] = {
- /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
- {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
-};
-
-/*USB 2 Bulkout Page Number*/
-static struct halmac_pg_num_ HALMAC_PG_NUM_2BULKOUT_8822B[] = {
- /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
- {HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1},
- {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1},
- {HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1},
- {HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1},
- {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024},
-};
-
-/*USB 3 Bulkout Page Number*/
-static struct halmac_pg_num_ HALMAC_PG_NUM_3BULKOUT_8822B[] = {
- /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
- {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
- {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1},
- {HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
- {HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
- {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024},
-};
-
-/*USB 4 Bulkout Page Number*/
-static struct halmac_pg_num_ HALMAC_PG_NUM_4BULKOUT_8822B[] = {
- /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
- {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
- {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
- {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
-};
-
-enum halmac_ret_status
-halmac_txdma_queue_mapping_8822b(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode)
-{
- u16 value16;
- void *driver_adapter = NULL;
- struct halmac_rqpn_ *curr_rqpn_sel = NULL;
- enum halmac_ret_status status;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- curr_rqpn_sel = HALMAC_RQPN_SDIO_8822B;
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
- curr_rqpn_sel = HALMAC_RQPN_PCIE_8822B;
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
- if (halmac_adapter->halmac_bulkout_num == 2) {
- curr_rqpn_sel = HALMAC_RQPN_2BULKOUT_8822B;
- } else if (halmac_adapter->halmac_bulkout_num == 3) {
- curr_rqpn_sel = HALMAC_RQPN_3BULKOUT_8822B;
- } else if (halmac_adapter->halmac_bulkout_num == 4) {
- curr_rqpn_sel = HALMAC_RQPN_4BULKOUT_8822B;
- } else {
- pr_err("[ERR]interface not support\n");
- return HALMAC_RET_NOT_SUPPORT;
- }
- } else {
- return HALMAC_RET_NOT_SUPPORT;
- }
-
- status = halmac_rqpn_parser_88xx(halmac_adapter, halmac_trx_mode,
- curr_rqpn_sel);
- if (status != HALMAC_RET_SUCCESS)
- return status;
-
- value16 = 0;
- value16 |= BIT_TXDMA_HIQ_MAP(
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]);
- value16 |= BIT_TXDMA_MGQ_MAP(
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]);
- value16 |= BIT_TXDMA_BKQ_MAP(
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]);
- value16 |= BIT_TXDMA_BEQ_MAP(
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]);
- value16 |= BIT_TXDMA_VIQ_MAP(
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]);
- value16 |= BIT_TXDMA_VOQ_MAP(
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_TXDMA_PQ_MAP, value16);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_priority_queue_config_8822b(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode)
-{
- u8 transfer_mode = 0;
- u8 value8;
- u32 counter;
- enum halmac_ret_status status;
- struct halmac_pg_num_ *curr_pg_num = NULL;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (halmac_adapter->txff_allocation.la_mode == HALMAC_LA_MODE_DISABLE) {
- if (halmac_adapter->txff_allocation.rx_fifo_expanding_mode ==
- HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) {
- halmac_adapter->txff_allocation.tx_fifo_pg_num =
- HALMAC_TX_FIFO_SIZE_8822B >>
- HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
- } else if (halmac_adapter->txff_allocation
- .rx_fifo_expanding_mode ==
- HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) {
- halmac_adapter->txff_allocation.tx_fifo_pg_num =
- HALMAC_TX_FIFO_SIZE_EX_1_BLK_8822B >>
- HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
- halmac_adapter->hw_config_info.tx_fifo_size =
- HALMAC_TX_FIFO_SIZE_EX_1_BLK_8822B;
- if (HALMAC_RX_FIFO_SIZE_EX_1_BLK_8822B <=
- HALMAC_RX_FIFO_SIZE_EX_1_BLK_MAX_8822B)
- halmac_adapter->hw_config_info.rx_fifo_size =
- HALMAC_RX_FIFO_SIZE_EX_1_BLK_8822B;
- else
- halmac_adapter->hw_config_info.rx_fifo_size =
- HALMAC_RX_FIFO_SIZE_EX_1_BLK_MAX_8822B;
- } else {
- halmac_adapter->txff_allocation.tx_fifo_pg_num =
- HALMAC_TX_FIFO_SIZE_8822B >>
- HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
- pr_err("[ERR]rx_fifo_expanding_mode = %d not support\n",
- halmac_adapter->txff_allocation
- .rx_fifo_expanding_mode);
- }
- } else {
- halmac_adapter->txff_allocation.tx_fifo_pg_num =
- HALMAC_TX_FIFO_SIZE_LA_8822B >>
- HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
- }
- halmac_adapter->txff_allocation.rsvd_pg_num =
- (halmac_adapter->txff_allocation.rsvd_drv_pg_num +
- HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B +
- HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B +
- HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B +
- HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B);
- if (halmac_adapter->txff_allocation.rsvd_pg_num >
- halmac_adapter->txff_allocation.tx_fifo_pg_num)
- return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
-
- halmac_adapter->txff_allocation.ac_q_pg_num =
- halmac_adapter->txff_allocation.tx_fifo_pg_num -
- halmac_adapter->txff_allocation.rsvd_pg_num;
- halmac_adapter->txff_allocation.rsvd_pg_bndy =
- halmac_adapter->txff_allocation.tx_fifo_pg_num -
- halmac_adapter->txff_allocation.rsvd_pg_num;
- halmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy =
- halmac_adapter->txff_allocation.tx_fifo_pg_num -
- HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B;
- halmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy =
- halmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy -
- HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B;
- halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy =
- halmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy -
- HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B;
- halmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy =
- halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy -
- HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B;
- halmac_adapter->txff_allocation.rsvd_drv_pg_bndy =
- halmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy -
- halmac_adapter->txff_allocation.rsvd_drv_pg_num;
-
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- curr_pg_num = HALMAC_PG_NUM_SDIO_8822B;
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
- curr_pg_num = HALMAC_PG_NUM_PCIE_8822B;
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
- if (halmac_adapter->halmac_bulkout_num == 2) {
- curr_pg_num = HALMAC_PG_NUM_2BULKOUT_8822B;
- } else if (halmac_adapter->halmac_bulkout_num == 3) {
- curr_pg_num = HALMAC_PG_NUM_3BULKOUT_8822B;
- } else if (halmac_adapter->halmac_bulkout_num == 4) {
- curr_pg_num = HALMAC_PG_NUM_4BULKOUT_8822B;
- } else {
- pr_err("[ERR]interface not support\n");
- return HALMAC_RET_NOT_SUPPORT;
- }
- } else {
- return HALMAC_RET_NOT_SUPPORT;
- }
-
- status = halmac_pg_num_parser_88xx(halmac_adapter, halmac_trx_mode,
- curr_pg_num);
- if (status != HALMAC_RET_SUCCESS)
- return status;
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_1,
- halmac_adapter->txff_allocation.high_queue_pg_num);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_2,
- halmac_adapter->txff_allocation.low_queue_pg_num);
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_FIFOPAGE_INFO_3,
- halmac_adapter->txff_allocation.normal_queue_pg_num);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_4,
- halmac_adapter->txff_allocation.extra_queue_pg_num);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_5,
- halmac_adapter->txff_allocation.pub_queue_pg_num);
-
- halmac_adapter->sdio_free_space.high_queue_number =
- halmac_adapter->txff_allocation.high_queue_pg_num;
- halmac_adapter->sdio_free_space.normal_queue_number =
- halmac_adapter->txff_allocation.normal_queue_pg_num;
- halmac_adapter->sdio_free_space.low_queue_number =
- halmac_adapter->txff_allocation.low_queue_pg_num;
- halmac_adapter->sdio_free_space.public_queue_number =
- halmac_adapter->txff_allocation.pub_queue_pg_num;
- halmac_adapter->sdio_free_space.extra_queue_number =
- halmac_adapter->txff_allocation.extra_queue_pg_num;
-
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_RQPN_CTRL_2,
- HALMAC_REG_READ_32(halmac_adapter, REG_RQPN_CTRL_2) | BIT(31));
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
- HALMAC_REG_WRITE_16(halmac_adapter, REG_BCNQ_BDNY_V1,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCNQ_PGBNDY_V1));
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2 + 2,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
- HALMAC_REG_WRITE_16(halmac_adapter, REG_BCNQ1_BDNY_V1,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCNQ_PGBNDY_V1));
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_RXFF_BNDY,
- halmac_adapter->hw_config_info.rx_fifo_size -
- HALMAC_C2H_PKT_BUF_8822B - 1);
-
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
- value8 = (u8)(
- HALMAC_REG_READ_8(halmac_adapter, REG_AUTO_LLT_V1) &
- ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM));
- value8 = (u8)(value8 | (HALMAC_BLK_DESC_NUM_8822B
- << BIT_SHIFT_BLK_DESC_NUM));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_AUTO_LLT_V1, value8);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_AUTO_LLT_V1 + 3,
- HALMAC_BLK_DESC_NUM_8822B);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1,
- HALMAC_REG_READ_8(halmac_adapter,
- REG_TXDMA_OFFSET_CHK + 1) |
- BIT(1));
- }
-
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_AUTO_LLT_V1,
- (u8)(HALMAC_REG_READ_8(halmac_adapter, REG_AUTO_LLT_V1) |
- BIT_AUTO_INIT_LLT_V1));
- counter = 1000;
- while (HALMAC_REG_READ_8(halmac_adapter, REG_AUTO_LLT_V1) &
- BIT_AUTO_INIT_LLT_V1) {
- counter--;
- if (counter == 0)
- return HALMAC_RET_INIT_LLT_FAIL;
- }
-
- if (halmac_trx_mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) {
- transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY;
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_WMAC_LBK_BUF_HD_V1,
- (u16)halmac_adapter->txff_allocation.rsvd_pg_bndy);
- } else if (halmac_trx_mode == HALMAC_TRX_MODE_LOOPBACK) {
- transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
- } else {
- transfer_mode = HALMAC_TRNSFER_NORMAL;
- }
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CR + 3, (u8)transfer_mode);
-
- return HALMAC_RET_SUCCESS;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_FUNC_8822B_H_
-#define _HALMAC_FUNC_8822B_H_
-
-#include "../../halmac_type.h"
-
-enum halmac_ret_status
-halmac_txdma_queue_mapping_8822b(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode);
-
-enum halmac_ret_status
-halmac_priority_queue_config_8822b(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode);
-
-#endif /* _HALMAC_FUNC_8822B_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_88XX_CFG_H_
-#define _HALMAC_88XX_CFG_H_
-
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-#include "../halmac_api.h"
-#include "../halmac_bit2.h"
-#include "../halmac_reg2.h"
-#include "../halmac_pwr_seq_cmd.h"
-#include "halmac_func_88xx.h"
-#include "halmac_api_88xx.h"
-#include "halmac_api_88xx_usb.h"
-#include "halmac_api_88xx_pcie.h"
-#include "halmac_api_88xx_sdio.h"
-
-#define HALMAC_SVN_VER_88XX "13359M"
-
-#define HALMAC_MAJOR_VER_88XX 0x0001 /* major version, ver_1 for async_api */
-/* For halmac_api num change or prototype change, increment prototype version.
- * Otherwise, increase minor version
- */
-#define HALMAC_PROTOTYPE_VER_88XX 0x0003 /* prototype version */
-#define HALMAC_MINOR_VER_88XX 0x0005 /* minor version */
-#define HALMAC_PATCH_VER_88XX 0x0000 /* patch version */
-
-#define HALMAC_C2H_DATA_OFFSET_88XX 10
-#define HALMAC_RX_AGG_ALIGNMENT_SIZE_88XX 8
-#define HALMAC_TX_AGG_ALIGNMENT_SIZE_88XX 8
-#define HALMAC_TX_AGG_BUFF_SIZE_88XX 32768
-
-#define HALMAC_EXTRA_INFO_BUFF_SIZE_88XX 4096 /*4K*/
-#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX 16384 /*16K*/
-#define HALMAC_FW_OFFLOAD_CMD_SIZE_88XX \
- 12 /*Fw config parameter cmd size, each 12 byte*/
-
-#define HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX 8
-#define HALMAC_H2C_CMD_SIZE_UNIT_88XX 32 /* Only support 32 byte packet now */
-
-#define HALMAC_NLO_INFO_SIZE_88XX 1024
-
-/* Download FW */
-#define HALMAC_FW_SIZE_MAX_88XX 0x40000
-#define HALMAC_FWHDR_SIZE_88XX 64
-#define HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX 8
-#define HALMAC_FW_MAX_DL_SIZE_88XX 0x2000 /* need power of 2 */
-/* Max dlfw size can not over 31K, because SDIO HW restriction */
-#define HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX 0x7C00
-
-#define DLFW_RESTORE_REG_NUM_88XX 9
-#define ID_INFORM_DLEMEM_RDY 0x80
-
-/* FW header information */
-#define HALMAC_FWHDR_OFFSET_VERSION_88XX 4
-#define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6
-#define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7
-#define HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX 24
-#define HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX 28
-#define HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX 32
-#define HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX 36
-#define HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX 48
-#define HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX 52
-#define HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX 56
-#define HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX 60
-
-/* HW memory address */
-#define HALMAC_OCPBASE_TXBUF_88XX 0x18780000
-#define HALMAC_OCPBASE_DMEM_88XX 0x00200000
-#define HALMAC_OCPBASE_IMEM_88XX 0x00000000
-
-/* define the SDIO Bus CLK threshold, for avoiding CMD53 fails that
- * result from SDIO CLK sync to ana_clk fail
- */
-#define HALMAC_SD_CLK_THRESHOLD_88XX 150000000 /* 150MHz */
-
-/* MAC clock */
-#define HALMAC_MAC_CLOCK_88XX 80 /* 80M */
-
-/* H2C/C2H*/
-#define HALMAC_H2C_CMD_SIZE_88XX 32
-#define HALMAC_H2C_CMD_HDR_SIZE_88XX 8
-
-#define HALMAC_PROTECTED_EFUSE_SIZE_88XX 0x60
-
-/* Function enable */
-#define HALMAC_FUNCTION_ENABLE_88XX 0xDC
-
-/* FIFO size & packet size */
-/* #define HALMAC_WOWLAN_PATTERN_SIZE 256 */
-
-/* CFEND rate */
-#define HALMAC_BASIC_CFEND_RATE_88XX 0x5
-#define HALMAC_STBC_CFEND_RATE_88XX 0xF
-
-/* Response rate */
-#define HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX 0xFFFFF
-#define HALMAC_RESPONSE_RATE_88XX HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX
-
-/* Spec SIFS */
-#define HALMAC_SIFS_CCK_PTCL_88XX 16
-#define HALMAC_SIFS_OFDM_PTCL_88XX 16
-
-/* Retry limit */
-#define HALMAC_LONG_RETRY_LIMIT_88XX 8
-#define HALMAC_SHORT_RETRY_LIMIT_88XX 7
-
-/* Slot, SIFS, PIFS time */
-#define HALMAC_SLOT_TIME_88XX 0x05
-#define HALMAC_PIFS_TIME_88XX 0x19
-#define HALMAC_SIFS_CCK_CTX_88XX 0xA
-#define HALMAC_SIFS_OFDM_CTX_88XX 0xA
-#define HALMAC_SIFS_CCK_TRX_88XX 0x10
-#define HALMAC_SIFS_OFDM_TRX_88XX 0x10
-
-/* TXOP limit */
-#define HALMAC_VO_TXOP_LIMIT_88XX 0x186
-#define HALMAC_VI_TXOP_LIMIT_88XX 0x3BC
-
-/* NAV */
-#define HALMAC_RDG_NAV_88XX 0x05
-#define HALMAC_TXOP_NAV_88XX 0x1B
-
-/* TSF */
-#define HALMAC_CCK_RX_TSF_88XX 0x30
-#define HALMAC_OFDM_RX_TSF_88XX 0x30
-
-/* Send beacon related */
-#define HALMAC_TBTT_PROHIBIT_88XX 0x04
-#define HALMAC_TBTT_HOLD_TIME_88XX 0x064
-#define HALMAC_DRIVER_EARLY_INT_88XX 0x04
-#define HALMAC_BEACON_DMA_TIM_88XX 0x02
-
-/* RX filter */
-#define HALMAC_RX_FILTER0_RECIVE_ALL_88XX 0xFFFFFFF
-#define HALMAC_RX_FILTER0_88XX HALMAC_RX_FILTER0_RECIVE_ALL_88XX
-#define HALMAC_RX_FILTER_RECIVE_ALL_88XX 0xFFFF
-#define HALMAC_RX_FILTER_88XX HALMAC_RX_FILTER_RECIVE_ALL_88XX
-
-/* RCR */
-#define HALMAC_RCR_CONFIG_88XX 0xE400631E
-
-/* Security config */
-#define HALMAC_SECURITY_CONFIG_88XX 0x01CC
-
-/* CCK rate ACK timeout */
-#define HALMAC_ACK_TO_CCK_88XX 0x40
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halmac_88xx_cfg.h"
-
-/**
- * halmac_init_adapter_para_88xx() - int halmac adapter
- * @halmac_adapter
- *
- * SD1 internal use
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : void
- */
-void halmac_init_adapter_para_88xx(struct halmac_adapter *halmac_adapter)
-{
- halmac_adapter->api_record.array_wptr = 0;
- halmac_adapter->hal_adapter_backup = halmac_adapter;
- halmac_adapter->hal_efuse_map = (u8 *)NULL;
- halmac_adapter->hal_efuse_map_valid = false;
- halmac_adapter->efuse_end = 0;
- halmac_adapter->hal_mac_addr[0].address_l_h.address_low = 0;
- halmac_adapter->hal_mac_addr[0].address_l_h.address_high = 0;
- halmac_adapter->hal_mac_addr[1].address_l_h.address_low = 0;
- halmac_adapter->hal_mac_addr[1].address_l_h.address_high = 0;
- halmac_adapter->hal_bss_addr[0].address_l_h.address_low = 0;
- halmac_adapter->hal_bss_addr[0].address_l_h.address_high = 0;
- halmac_adapter->hal_bss_addr[1].address_l_h.address_low = 0;
- halmac_adapter->hal_bss_addr[1].address_l_h.address_high = 0;
-
- halmac_adapter->low_clk = false;
- halmac_adapter->max_download_size = HALMAC_FW_MAX_DL_SIZE_88XX;
-
- /* Init LPS Option */
- halmac_adapter->fwlps_option.mode = 0x01; /*0:Active 1:LPS 2:WMMPS*/
- halmac_adapter->fwlps_option.awake_interval = 1;
- halmac_adapter->fwlps_option.enter_32K = 1;
- halmac_adapter->fwlps_option.clk_request = 0;
- halmac_adapter->fwlps_option.rlbm = 0;
- halmac_adapter->fwlps_option.smart_ps = 0;
- halmac_adapter->fwlps_option.awake_interval = 1;
- halmac_adapter->fwlps_option.all_queue_uapsd = 0;
- halmac_adapter->fwlps_option.pwr_state = 0;
- halmac_adapter->fwlps_option.low_pwr_rx_beacon = 0;
- halmac_adapter->fwlps_option.ant_auto_switch = 0;
- halmac_adapter->fwlps_option.ps_allow_bt_high_priority = 0;
- halmac_adapter->fwlps_option.protect_bcn = 0;
- halmac_adapter->fwlps_option.silence_period = 0;
- halmac_adapter->fwlps_option.fast_bt_connect = 0;
- halmac_adapter->fwlps_option.two_antenna_en = 0;
- halmac_adapter->fwlps_option.adopt_user_setting = 1;
- halmac_adapter->fwlps_option.drv_bcn_early_shift = 0;
-
- halmac_adapter->config_para_info.cfg_para_buf = NULL;
- halmac_adapter->config_para_info.para_buf_w = NULL;
- halmac_adapter->config_para_info.para_num = 0;
- halmac_adapter->config_para_info.full_fifo_mode = false;
- halmac_adapter->config_para_info.para_buf_size = 0;
- halmac_adapter->config_para_info.avai_para_buf_size = 0;
- halmac_adapter->config_para_info.offset_accumulation = 0;
- halmac_adapter->config_para_info.value_accumulation = 0;
- halmac_adapter->config_para_info.datapack_segment = 0;
-
- halmac_adapter->ch_sw_info.ch_info_buf = NULL;
- halmac_adapter->ch_sw_info.ch_info_buf_w = NULL;
- halmac_adapter->ch_sw_info.extra_info_en = 0;
- halmac_adapter->ch_sw_info.buf_size = 0;
- halmac_adapter->ch_sw_info.avai_buf_size = 0;
- halmac_adapter->ch_sw_info.total_size = 0;
- halmac_adapter->ch_sw_info.ch_num = 0;
-
- halmac_adapter->drv_info_size = 0;
-
- memset(halmac_adapter->api_record.api_array, HALMAC_API_STUFF,
- sizeof(halmac_adapter->api_record.api_array));
-
- halmac_adapter->txff_allocation.tx_fifo_pg_num = 0;
- halmac_adapter->txff_allocation.ac_q_pg_num = 0;
- halmac_adapter->txff_allocation.rsvd_pg_bndy = 0;
- halmac_adapter->txff_allocation.rsvd_drv_pg_bndy = 0;
- halmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = 0;
- halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = 0;
- halmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = 0;
- halmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = 0;
- halmac_adapter->txff_allocation.pub_queue_pg_num = 0;
- halmac_adapter->txff_allocation.high_queue_pg_num = 0;
- halmac_adapter->txff_allocation.low_queue_pg_num = 0;
- halmac_adapter->txff_allocation.normal_queue_pg_num = 0;
- halmac_adapter->txff_allocation.extra_queue_pg_num = 0;
-
- halmac_adapter->txff_allocation.la_mode = HALMAC_LA_MODE_DISABLE;
- halmac_adapter->txff_allocation.rx_fifo_expanding_mode =
- HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
-
- halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
- halmac_init_state_machine_88xx(halmac_adapter);
-}
-
-/**
- * halmac_init_adapter_dynamic_para_88xx() - int halmac adapter
- * @halmac_adapter
- *
- * SD1 internal use
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : void
- */
-void halmac_init_adapter_dynamic_para_88xx(
- struct halmac_adapter *halmac_adapter)
-{
- halmac_adapter->h2c_packet_seq = 0;
- halmac_adapter->h2c_buf_free_space = 0;
- halmac_adapter->gen_info_valid = false;
-}
-
-/**
- * halmac_init_state_machine_88xx() - init halmac software state machine
- * @halmac_adapter
- *
- * SD1 internal use.
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : void
- */
-void halmac_init_state_machine_88xx(struct halmac_adapter *halmac_adapter)
-{
- struct halmac_state *state = &halmac_adapter->halmac_state;
-
- halmac_init_offload_feature_state_machine_88xx(halmac_adapter);
-
- state->api_state = HALMAC_API_STATE_INIT;
-
- state->dlfw_state = HALMAC_DLFW_NONE;
- state->mac_power = HALMAC_MAC_POWER_OFF;
- state->ps_state = HALMAC_PS_STATE_UNDEFINE;
-}
-
-/**
- * halmac_mount_api_88xx() - attach functions to function pointer
- * @halmac_adapter
- *
- * SD1 internal use
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- */
-enum halmac_ret_status
-halmac_mount_api_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = halmac_adapter->driver_adapter;
- struct halmac_api *halmac_api = (struct halmac_api *)NULL;
-
- halmac_adapter->halmac_api =
- kzalloc(sizeof(struct halmac_api), GFP_KERNEL);
- if (!halmac_adapter->halmac_api)
- return HALMAC_RET_MALLOC_FAIL;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- HALMAC_SVN_VER_88XX "\n");
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "HALMAC_MAJOR_VER_88XX = %x\n", HALMAC_MAJOR_VER_88XX);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "HALMAC_PROTOTYPE_88XX = %x\n",
- HALMAC_PROTOTYPE_VER_88XX);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "HALMAC_MINOR_VER_88XX = %x\n", HALMAC_MINOR_VER_88XX);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "HALMAC_PATCH_VER_88XX = %x\n", HALMAC_PATCH_VER_88XX);
-
- /* Mount function pointer */
- halmac_api->halmac_download_firmware = halmac_download_firmware_88xx;
- halmac_api->halmac_free_download_firmware =
- halmac_free_download_firmware_88xx;
- halmac_api->halmac_get_fw_version = halmac_get_fw_version_88xx;
- halmac_api->halmac_cfg_mac_addr = halmac_cfg_mac_addr_88xx;
- halmac_api->halmac_cfg_bssid = halmac_cfg_bssid_88xx;
- halmac_api->halmac_cfg_multicast_addr = halmac_cfg_multicast_addr_88xx;
- halmac_api->halmac_pre_init_system_cfg =
- halmac_pre_init_system_cfg_88xx;
- halmac_api->halmac_init_system_cfg = halmac_init_system_cfg_88xx;
- halmac_api->halmac_init_edca_cfg = halmac_init_edca_cfg_88xx;
- halmac_api->halmac_cfg_operation_mode = halmac_cfg_operation_mode_88xx;
- halmac_api->halmac_cfg_ch_bw = halmac_cfg_ch_bw_88xx;
- halmac_api->halmac_cfg_bw = halmac_cfg_bw_88xx;
- halmac_api->halmac_init_wmac_cfg = halmac_init_wmac_cfg_88xx;
- halmac_api->halmac_init_mac_cfg = halmac_init_mac_cfg_88xx;
- halmac_api->halmac_init_sdio_cfg = halmac_init_sdio_cfg_88xx;
- halmac_api->halmac_init_usb_cfg = halmac_init_usb_cfg_88xx;
- halmac_api->halmac_init_pcie_cfg = halmac_init_pcie_cfg_88xx;
- halmac_api->halmac_deinit_sdio_cfg = halmac_deinit_sdio_cfg_88xx;
- halmac_api->halmac_deinit_usb_cfg = halmac_deinit_usb_cfg_88xx;
- halmac_api->halmac_deinit_pcie_cfg = halmac_deinit_pcie_cfg_88xx;
- halmac_api->halmac_dump_efuse_map = halmac_dump_efuse_map_88xx;
- halmac_api->halmac_dump_efuse_map_bt = halmac_dump_efuse_map_bt_88xx;
- halmac_api->halmac_write_efuse_bt = halmac_write_efuse_bt_88xx;
- halmac_api->halmac_dump_logical_efuse_map =
- halmac_dump_logical_efuse_map_88xx;
- halmac_api->halmac_pg_efuse_by_map = halmac_pg_efuse_by_map_88xx;
- halmac_api->halmac_get_efuse_size = halmac_get_efuse_size_88xx;
- halmac_api->halmac_get_efuse_available_size =
- halmac_get_efuse_available_size_88xx;
- halmac_api->halmac_get_c2h_info = halmac_get_c2h_info_88xx;
-
- halmac_api->halmac_get_logical_efuse_size =
- halmac_get_logical_efuse_size_88xx;
-
- halmac_api->halmac_write_logical_efuse =
- halmac_write_logical_efuse_88xx;
- halmac_api->halmac_read_logical_efuse = halmac_read_logical_efuse_88xx;
-
- halmac_api->halmac_cfg_fwlps_option = halmac_cfg_fwlps_option_88xx;
- halmac_api->halmac_cfg_fwips_option = halmac_cfg_fwips_option_88xx;
- halmac_api->halmac_enter_wowlan = halmac_enter_wowlan_88xx;
- halmac_api->halmac_leave_wowlan = halmac_leave_wowlan_88xx;
- halmac_api->halmac_enter_ps = halmac_enter_ps_88xx;
- halmac_api->halmac_leave_ps = halmac_leave_ps_88xx;
- halmac_api->halmac_h2c_lb = halmac_h2c_lb_88xx;
- halmac_api->halmac_debug = halmac_debug_88xx;
- halmac_api->halmac_cfg_parameter = halmac_cfg_parameter_88xx;
- halmac_api->halmac_update_datapack = halmac_update_datapack_88xx;
- halmac_api->halmac_run_datapack = halmac_run_datapack_88xx;
- halmac_api->halmac_cfg_drv_info = halmac_cfg_drv_info_88xx;
- halmac_api->halmac_send_bt_coex = halmac_send_bt_coex_88xx;
- halmac_api->halmac_verify_platform_api =
- halmac_verify_platform_api_88xx;
- halmac_api->halmac_update_packet = halmac_update_packet_88xx;
- halmac_api->halmac_bcn_ie_filter = halmac_bcn_ie_filter_88xx;
- halmac_api->halmac_cfg_txbf = halmac_cfg_txbf_88xx;
- halmac_api->halmac_cfg_mumimo = halmac_cfg_mumimo_88xx;
- halmac_api->halmac_cfg_sounding = halmac_cfg_sounding_88xx;
- halmac_api->halmac_del_sounding = halmac_del_sounding_88xx;
- halmac_api->halmac_su_bfer_entry_init = halmac_su_bfer_entry_init_88xx;
- halmac_api->halmac_su_bfee_entry_init = halmac_su_bfee_entry_init_88xx;
- halmac_api->halmac_mu_bfer_entry_init = halmac_mu_bfer_entry_init_88xx;
- halmac_api->halmac_mu_bfee_entry_init = halmac_mu_bfee_entry_init_88xx;
- halmac_api->halmac_su_bfer_entry_del = halmac_su_bfer_entry_del_88xx;
- halmac_api->halmac_su_bfee_entry_del = halmac_su_bfee_entry_del_88xx;
- halmac_api->halmac_mu_bfer_entry_del = halmac_mu_bfer_entry_del_88xx;
- halmac_api->halmac_mu_bfee_entry_del = halmac_mu_bfee_entry_del_88xx;
-
- halmac_api->halmac_add_ch_info = halmac_add_ch_info_88xx;
- halmac_api->halmac_add_extra_ch_info = halmac_add_extra_ch_info_88xx;
- halmac_api->halmac_ctrl_ch_switch = halmac_ctrl_ch_switch_88xx;
- halmac_api->halmac_p2pps = halmac_p2pps_88xx;
- halmac_api->halmac_clear_ch_info = halmac_clear_ch_info_88xx;
- halmac_api->halmac_send_general_info = halmac_send_general_info_88xx;
-
- halmac_api->halmac_start_iqk = halmac_start_iqk_88xx;
- halmac_api->halmac_ctrl_pwr_tracking = halmac_ctrl_pwr_tracking_88xx;
- halmac_api->halmac_psd = halmac_psd_88xx;
- halmac_api->halmac_cfg_la_mode = halmac_cfg_la_mode_88xx;
- halmac_api->halmac_cfg_rx_fifo_expanding_mode =
- halmac_cfg_rx_fifo_expanding_mode_88xx;
-
- halmac_api->halmac_config_security = halmac_config_security_88xx;
- halmac_api->halmac_get_used_cam_entry_num =
- halmac_get_used_cam_entry_num_88xx;
- halmac_api->halmac_read_cam_entry = halmac_read_cam_entry_88xx;
- halmac_api->halmac_write_cam = halmac_write_cam_88xx;
- halmac_api->halmac_clear_cam_entry = halmac_clear_cam_entry_88xx;
-
- halmac_api->halmac_get_hw_value = halmac_get_hw_value_88xx;
- halmac_api->halmac_set_hw_value = halmac_set_hw_value_88xx;
-
- halmac_api->halmac_cfg_drv_rsvd_pg_num =
- halmac_cfg_drv_rsvd_pg_num_88xx;
- halmac_api->halmac_get_chip_version = halmac_get_chip_version_88xx;
-
- halmac_api->halmac_query_status = halmac_query_status_88xx;
- halmac_api->halmac_reset_feature = halmac_reset_feature_88xx;
- halmac_api->halmac_check_fw_status = halmac_check_fw_status_88xx;
- halmac_api->halmac_dump_fw_dmem = halmac_dump_fw_dmem_88xx;
- halmac_api->halmac_cfg_max_dl_size = halmac_cfg_max_dl_size_88xx;
-
- halmac_api->halmac_dump_fifo = halmac_dump_fifo_88xx;
- halmac_api->halmac_get_fifo_size = halmac_get_fifo_size_88xx;
-
- halmac_api->halmac_chk_txdesc = halmac_chk_txdesc_88xx;
- halmac_api->halmac_dl_drv_rsvd_page = halmac_dl_drv_rsvd_page_88xx;
- halmac_api->halmac_cfg_csi_rate = halmac_cfg_csi_rate_88xx;
-
- halmac_api->halmac_sdio_cmd53_4byte = halmac_sdio_cmd53_4byte_88xx;
- halmac_api->halmac_txfifo_is_empty = halmac_txfifo_is_empty_88xx;
-
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- halmac_api->halmac_cfg_rx_aggregation =
- halmac_cfg_rx_aggregation_88xx_sdio;
- halmac_api->halmac_init_interface_cfg =
- halmac_init_sdio_cfg_88xx;
- halmac_api->halmac_deinit_interface_cfg =
- halmac_deinit_sdio_cfg_88xx;
- halmac_api->halmac_reg_read_8 = halmac_reg_read_8_sdio_88xx;
- halmac_api->halmac_reg_write_8 = halmac_reg_write_8_sdio_88xx;
- halmac_api->halmac_reg_read_16 = halmac_reg_read_16_sdio_88xx;
- halmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_88xx;
- halmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_88xx;
- halmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_88xx;
- halmac_api->halmac_reg_read_indirect_32 =
- halmac_reg_read_indirect_32_sdio_88xx;
- halmac_api->halmac_reg_sdio_cmd53_read_n =
- halmac_reg_read_nbyte_sdio_88xx;
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
- halmac_api->halmac_cfg_rx_aggregation =
- halmac_cfg_rx_aggregation_88xx_usb;
- halmac_api->halmac_init_interface_cfg =
- halmac_init_usb_cfg_88xx;
- halmac_api->halmac_deinit_interface_cfg =
- halmac_deinit_usb_cfg_88xx;
- halmac_api->halmac_reg_read_8 = halmac_reg_read_8_usb_88xx;
- halmac_api->halmac_reg_write_8 = halmac_reg_write_8_usb_88xx;
- halmac_api->halmac_reg_read_16 = halmac_reg_read_16_usb_88xx;
- halmac_api->halmac_reg_write_16 = halmac_reg_write_16_usb_88xx;
- halmac_api->halmac_reg_read_32 = halmac_reg_read_32_usb_88xx;
- halmac_api->halmac_reg_write_32 = halmac_reg_write_32_usb_88xx;
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
- halmac_api->halmac_cfg_rx_aggregation =
- halmac_cfg_rx_aggregation_88xx_pcie;
- halmac_api->halmac_init_interface_cfg =
- halmac_init_pcie_cfg_88xx;
- halmac_api->halmac_deinit_interface_cfg =
- halmac_deinit_pcie_cfg_88xx;
- halmac_api->halmac_reg_read_8 = halmac_reg_read_8_pcie_88xx;
- halmac_api->halmac_reg_write_8 = halmac_reg_write_8_pcie_88xx;
- halmac_api->halmac_reg_read_16 = halmac_reg_read_16_pcie_88xx;
- halmac_api->halmac_reg_write_16 = halmac_reg_write_16_pcie_88xx;
- halmac_api->halmac_reg_read_32 = halmac_reg_read_32_pcie_88xx;
- halmac_api->halmac_reg_write_32 = halmac_reg_write_32_pcie_88xx;
- } else {
- pr_err("Set halmac io function Error!!\n");
- }
-
- halmac_api->halmac_set_bulkout_num = halmac_set_bulkout_num_88xx;
- halmac_api->halmac_get_sdio_tx_addr = halmac_get_sdio_tx_addr_88xx;
- halmac_api->halmac_get_usb_bulkout_id = halmac_get_usb_bulkout_id_88xx;
- halmac_api->halmac_timer_2s = halmac_timer_2s_88xx;
- halmac_api->halmac_fill_txdesc_checksum =
- halmac_fill_txdesc_check_sum_88xx;
-
- if (halmac_adapter->chip_id == HALMAC_CHIP_ID_8822B) {
- /*mount 8822b function and data*/
- halmac_mount_api_8822b(halmac_adapter);
-
- } else if (halmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) {
- } else if (halmac_adapter->chip_id == HALMAC_CHIP_ID_8814B) {
- } else if (halmac_adapter->chip_id == HALMAC_CHIP_ID_8197F) {
- } else {
- pr_err("Chip ID undefine!!\n");
- return HALMAC_RET_CHIP_NOT_SUPPORT;
- }
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_download_firmware_88xx() - download Firmware
- * @halmac_adapter : the adapter of halmac
- * @hamacl_fw : firmware bin
- * @halmac_fw_size : firmware size
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_download_firmware_88xx(struct halmac_adapter *halmac_adapter,
- u8 *hamacl_fw, u32 halmac_fw_size)
-{
- u8 value8;
- u8 *file_ptr;
- u32 dest;
- u16 value16;
- u32 restore_index = 0;
- u32 halmac_h2c_ver = 0, fw_h2c_ver = 0;
- u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- struct halmac_restore_info restore_info[DLFW_RESTORE_REG_NUM_88XX];
- u32 temp;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DOWNLOAD_FIRMWARE);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s start!!\n", __func__);
-
- if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX ||
- halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) {
- pr_err("FW size error!\n");
- return HALMAC_RET_FW_SIZE_ERR;
- }
-
- fw_h2c_ver = le32_to_cpu(
- *((__le32 *)
- (hamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX)));
- halmac_h2c_ver = H2C_FORMAT_VERSION;
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac h2c/c2h format = %x, fw h2c/c2h format = %x!!\n",
- halmac_h2c_ver, fw_h2c_ver);
- if (fw_h2c_ver != halmac_h2c_ver)
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_WARNING,
- "[WARN]H2C/C2H version between HALMAC and FW is compatible!!\n");
-
- halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_SYS_FUNC_EN + 1);
- value8 = (u8)(value8 & ~(BIT(2)));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SYS_FUNC_EN + 1,
- value8); /* Disable CPU reset */
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_RSV_CTRL + 1);
- value8 = (u8)(value8 & ~(BIT(0)));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RSV_CTRL + 1, value8);
-
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_TXDMA_PQ_MAP + 1;
- restore_info[restore_index].value =
- HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_PQ_MAP + 1);
- restore_index++;
- value8 = HALMAC_DMA_MAPPING_HIGH << 6;
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_PQ_MAP + 1,
- value8); /* set HIQ to hi priority */
-
- /* DLFW only use HIQ, map HIQ to hi priority */
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] =
- HALMAC_DMA_MAPPING_HIGH;
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_CR;
- restore_info[restore_index].value =
- HALMAC_REG_READ_8(halmac_adapter, REG_CR);
- restore_index++;
- restore_info[restore_index].length = 4;
- restore_info[restore_index].mac_register = REG_H2CQ_CSR;
- restore_info[restore_index].value = BIT(31);
- restore_index++;
- value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN;
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_H2CQ_CSR, BIT(31));
-
- /* Config hi priority queue and public priority queue page number
- * (only for DLFW)
- */
- restore_info[restore_index].length = 2;
- restore_info[restore_index].mac_register = REG_FIFOPAGE_INFO_1;
- restore_info[restore_index].value =
- HALMAC_REG_READ_16(halmac_adapter, REG_FIFOPAGE_INFO_1);
- restore_index++;
- restore_info[restore_index].length = 4;
- restore_info[restore_index].mac_register = REG_RQPN_CTRL_2;
- restore_info[restore_index].value =
- HALMAC_REG_READ_32(halmac_adapter, REG_RQPN_CTRL_2) | BIT(31);
- restore_index++;
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_1, 0x200);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_RQPN_CTRL_2,
- restore_info[restore_index - 1].value);
-
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- HALMAC_REG_READ_32(halmac_adapter, REG_SDIO_FREE_TXPG);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_TX_CTRL,
- 0x00000000);
- }
-
- halmac_adapter->fw_version.version = le16_to_cpu(
- *((__le16 *)(hamacl_fw + HALMAC_FWHDR_OFFSET_VERSION_88XX)));
- halmac_adapter->fw_version.sub_version =
- *(hamacl_fw + HALMAC_FWHDR_OFFSET_SUBVERSION_88XX);
- halmac_adapter->fw_version.sub_index =
- *(hamacl_fw + HALMAC_FWHDR_OFFSET_SUBINDEX_88XX);
- halmac_adapter->fw_version.h2c_version = (u16)fw_h2c_ver;
-
- dmem_pkt_size = le32_to_cpu(*((__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX)));
- iram_pkt_size = le32_to_cpu(*((__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX)));
- if (((*(hamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4)) != 0)
- eram_pkt_size =
- le32_to_cpu(*((__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX)));
-
- dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
- iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
- if (eram_pkt_size != 0)
- eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
-
- if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size +
- iram_pkt_size + eram_pkt_size)) {
- pr_err("FW size mismatch the real fw size!\n");
- goto DLFW_FAIL;
- }
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR + 1);
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_CR + 1;
- restore_info[restore_index].value = value8;
- restore_index++;
- value8 = (u8)(value8 | BIT(0));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CR + 1,
- value8); /* Enable SW TX beacon */
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_BCN_CTRL);
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_BCN_CTRL;
- restore_info[restore_index].value = value8;
- restore_index++;
- value8 = (u8)((value8 & (~BIT(3))) | BIT(4));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_BCN_CTRL,
- value8); /* Disable beacon related functions */
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_FWHW_TXQ_CTRL + 2);
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_FWHW_TXQ_CTRL + 2;
- restore_info[restore_index].value = value8;
- restore_index++;
- value8 = (u8)(value8 & ~(BIT(6)));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_FWHW_TXQ_CTRL + 2,
- value8); /* Disable ptcl tx bcnq */
-
- restore_info[restore_index].length = 2;
- restore_info[restore_index].mac_register = REG_FIFOPAGE_CTRL_2;
- restore_info[restore_index].value =
- HALMAC_REG_READ_16(halmac_adapter, REG_FIFOPAGE_CTRL_2) |
- BIT(15);
- restore_index++;
- value16 = 0x8000;
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- value16); /* Set beacon header to 0 */
-
- value16 = (u16)(HALMAC_REG_READ_16(halmac_adapter, REG_MCUFW_CTRL) &
- 0x3800);
- value16 |= BIT(0);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MCUFW_CTRL,
- value16); /* MCU/FW setting */
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CPU_DMEM_CON + 2);
- value8 &= ~(BIT(0));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CPU_DMEM_CON + 2, value8);
- value8 |= BIT(0);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CPU_DMEM_CON + 2, value8);
-
- /* Download to DMEM */
- file_ptr = hamacl_fw + HALMAC_FWHDR_SIZE_88XX;
- temp = le32_to_cpu(*((__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX))) &
- ~(BIT(31));
- if (halmac_dlfw_to_mem_88xx(halmac_adapter, file_ptr, temp,
- dmem_pkt_size) != HALMAC_RET_SUCCESS)
- goto DLFW_END;
-
- /* Download to IMEM */
- file_ptr = hamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size;
- temp = le32_to_cpu(*((__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX))) &
- ~(BIT(31));
- if (halmac_dlfw_to_mem_88xx(halmac_adapter, file_ptr, temp,
- iram_pkt_size) != HALMAC_RET_SUCCESS)
- goto DLFW_END;
-
- /* Download to EMEM */
- if (eram_pkt_size != 0) {
- file_ptr = hamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size +
- iram_pkt_size;
- dest = le32_to_cpu((*((__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX)))) &
- ~(BIT(31));
- if (halmac_dlfw_to_mem_88xx(halmac_adapter, file_ptr, dest,
- eram_pkt_size) !=
- HALMAC_RET_SUCCESS)
- goto DLFW_END;
- }
-
- halmac_init_offload_feature_state_machine_88xx(halmac_adapter);
-DLFW_END:
-
- halmac_restore_mac_register_88xx(halmac_adapter, restore_info,
- DLFW_RESTORE_REG_NUM_88XX);
-
- if (halmac_dlfw_end_flow_88xx(halmac_adapter) != HALMAC_RET_SUCCESS)
- goto DLFW_FAIL;
-
- halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-
-DLFW_FAIL:
-
- /* Disable FWDL_EN */
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_MCUFW_CTRL,
- (u8)(HALMAC_REG_READ_8(halmac_adapter, REG_MCUFW_CTRL) &
- ~(BIT(0))));
-
- return HALMAC_RET_DLFW_FAIL;
-}
-
-/**
- * halmac_free_download_firmware_88xx() - download specific memory firmware
- * @halmac_adapter
- * @dlfw_mem : memory selection
- * @hamacl_fw : firmware bin
- * @halmac_fw_size : firmware size
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- */
-enum halmac_ret_status
-halmac_free_download_firmware_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_dlfw_mem dlfw_mem, u8 *hamacl_fw,
- u32 halmac_fw_size)
-{
- u8 tx_pause_backup;
- u8 *file_ptr;
- u32 dest;
- u16 bcn_head_backup;
- u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_DLFW_FAIL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]%s ==========>\n", __func__);
-
- if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX ||
- halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) {
- pr_err("[ERR]FW size error!\n");
- return HALMAC_RET_FW_SIZE_ERR;
- }
-
- dmem_pkt_size =
- le32_to_cpu(*(__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX));
- iram_pkt_size =
- le32_to_cpu(*(__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX));
- if (((*(hamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4)) != 0)
- eram_pkt_size =
- le32_to_cpu(*(__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX));
-
- dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
- iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
- if (eram_pkt_size != 0)
- eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
-
- if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size +
- iram_pkt_size + eram_pkt_size)) {
- pr_err("[ERR]FW size mismatch the real fw size!\n");
- return HALMAC_RET_DLFW_FAIL;
- }
-
- tx_pause_backup = HALMAC_REG_READ_8(halmac_adapter, REG_TXPAUSE);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TXPAUSE,
- tx_pause_backup | BIT(7));
-
- bcn_head_backup =
- HALMAC_REG_READ_16(halmac_adapter, REG_FIFOPAGE_CTRL_2) |
- BIT(15);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2, 0x8000);
-
- if (eram_pkt_size != 0) {
- file_ptr = hamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size +
- iram_pkt_size;
- dest = le32_to_cpu(*((__le32 *)(hamacl_fw +
- HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) &
- ~(BIT(31));
- status = halmac_dlfw_to_mem_88xx(halmac_adapter, file_ptr, dest,
- eram_pkt_size);
- if (status != HALMAC_RET_SUCCESS)
- goto DL_FREE_FW_END;
- }
-
- status = halmac_free_dl_fw_end_flow_88xx(halmac_adapter);
-
-DL_FREE_FW_END:
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TXPAUSE, tx_pause_backup);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- bcn_head_backup);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]%s <==========\n", __func__);
-
- return status;
-}
-
-/**
- * halmac_get_fw_version_88xx() - get FW version
- * @halmac_adapter : the adapter of halmac
- * @fw_version : fw version info
- * Author : Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_get_fw_version_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_fw_version *fw_version)
-{
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_adapter->halmac_state.dlfw_state == 0)
- return HALMAC_RET_DLFW_FAIL;
-
- fw_version->version = halmac_adapter->fw_version.version;
- fw_version->sub_version = halmac_adapter->fw_version.sub_version;
- fw_version->sub_index = halmac_adapter->fw_version.sub_index;
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_mac_addr_88xx() - config mac address
- * @halmac_adapter : the adapter of halmac
- * @halmac_port :0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
- * @hal_address : mac address
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_mac_addr_88xx(struct halmac_adapter *halmac_adapter, u8 halmac_port,
- union halmac_wlan_addr *hal_address)
-{
- u16 mac_address_H;
- u32 mac_address_L;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]%s ==========>\n", __func__);
-
- if (halmac_port >= HALMAC_PORTIDMAX) {
- pr_err("[ERR]port index > 5\n");
- return HALMAC_RET_PORT_NOT_SUPPORT;
- }
-
- mac_address_L = le32_to_cpu(hal_address->address_l_h.le_address_low);
- mac_address_H = le16_to_cpu(hal_address->address_l_h.le_address_high);
-
- halmac_adapter->hal_mac_addr[halmac_port].address_l_h.address_low =
- mac_address_L;
- halmac_adapter->hal_mac_addr[halmac_port].address_l_h.address_high =
- mac_address_H;
-
- switch (halmac_port) {
- case HALMAC_PORTID0:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MACID, mac_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MACID + 4,
- mac_address_H);
- break;
-
- case HALMAC_PORTID1:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MACID1, mac_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MACID1 + 4,
- mac_address_H);
- break;
-
- case HALMAC_PORTID2:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MACID2, mac_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MACID2 + 4,
- mac_address_H);
- break;
-
- case HALMAC_PORTID3:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MACID3, mac_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MACID3 + 4,
- mac_address_H);
- break;
-
- case HALMAC_PORTID4:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MACID4, mac_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MACID4 + 4,
- mac_address_H);
- break;
-
- default:
-
- break;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_bssid_88xx() - config BSSID
- * @halmac_adapter : the adapter of halmac
- * @halmac_port :0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
- * @hal_address : bssid
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_bssid_88xx(struct halmac_adapter *halmac_adapter, u8 halmac_port,
- union halmac_wlan_addr *hal_address)
-{
- u16 bssid_address_H;
- u32 bssid_address_L;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]%s ==========>\n", __func__);
-
- if (halmac_port >= HALMAC_PORTIDMAX) {
- pr_err("[ERR]port index > 5\n");
- return HALMAC_RET_PORT_NOT_SUPPORT;
- }
-
- bssid_address_L = le32_to_cpu(hal_address->address_l_h.le_address_low);
- bssid_address_H = le16_to_cpu(hal_address->address_l_h.le_address_high);
-
- halmac_adapter->hal_bss_addr[halmac_port].address_l_h.address_low =
- bssid_address_L;
- halmac_adapter->hal_bss_addr[halmac_port].address_l_h.address_high =
- bssid_address_H;
-
- switch (halmac_port) {
- case HALMAC_PORTID0:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_BSSID, bssid_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_BSSID + 4,
- bssid_address_H);
- break;
-
- case HALMAC_PORTID1:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_BSSID1,
- bssid_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_BSSID1 + 4,
- bssid_address_H);
- break;
-
- case HALMAC_PORTID2:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_BSSID2,
- bssid_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_BSSID2 + 4,
- bssid_address_H);
- break;
-
- case HALMAC_PORTID3:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_BSSID3,
- bssid_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_BSSID3 + 4,
- bssid_address_H);
- break;
-
- case HALMAC_PORTID4:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_BSSID4,
- bssid_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_BSSID4 + 4,
- bssid_address_H);
- break;
-
- default:
-
- break;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_multicast_addr_88xx() - config multicast address
- * @halmac_adapter : the adapter of halmac
- * @hal_address : multicast address
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_multicast_addr_88xx(struct halmac_adapter *halmac_adapter,
- union halmac_wlan_addr *hal_address)
-{
- u16 address_H;
- u32 address_L;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_CFG_MULTICAST_ADDR);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- address_L = le32_to_cpu(hal_address->address_l_h.le_address_low);
- address_H = le16_to_cpu(hal_address->address_l_h.le_address_high);
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MAR, address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MAR + 4, address_H);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_pre_init_system_cfg_88xx() - pre-init system config
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_pre_init_system_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- u32 value32, counter;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- bool enable_bb;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_PRE_INIT_SYSTEM_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_pre_init_system_cfg ==========>\n");
-
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_SDIO_HSUS_CTRL,
- HALMAC_REG_READ_8(halmac_adapter, REG_SDIO_HSUS_CTRL) &
- ~(BIT(0)));
- counter = 10000;
- while (!(HALMAC_REG_READ_8(halmac_adapter, REG_SDIO_HSUS_CTRL) &
- 0x02)) {
- counter--;
- if (counter == 0)
- return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
- }
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
- if (HALMAC_REG_READ_8(halmac_adapter, REG_SYS_CFG2 + 3) ==
- 0x20) /* usb3.0 */
- HALMAC_REG_WRITE_8(
- halmac_adapter, 0xFE5B,
- HALMAC_REG_READ_8(halmac_adapter, 0xFE5B) |
- BIT(4));
- }
-
- /* Config PIN Mux */
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_PAD_CTRL1);
- value32 = value32 & (~(BIT(28) | BIT(29)));
- value32 = value32 | BIT(28) | BIT(29);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_PAD_CTRL1, value32);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_LED_CFG);
- value32 = value32 & (~(BIT(25) | BIT(26)));
- HALMAC_REG_WRITE_32(halmac_adapter, REG_LED_CFG, value32);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_GPIO_MUXCFG);
- value32 = value32 & (~(BIT(2)));
- value32 = value32 | BIT(2);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_GPIO_MUXCFG, value32);
-
- enable_bb = false;
- halmac_set_hw_value_88xx(halmac_adapter, HALMAC_HW_EN_BB_RF,
- &enable_bb);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_pre_init_system_cfg <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_system_cfg_88xx() - init system config
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_system_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_SYSTEM_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_init_system_cfg ==========>\n");
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SYS_FUNC_EN + 1,
- HALMAC_FUNCTION_ENABLE_88XX);
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_SYS_SDIO_CTRL,
- (u32)(HALMAC_REG_READ_32(halmac_adapter, REG_SYS_SDIO_CTRL) |
- BIT_LTE_MUX_CTRL_PATH));
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_CPU_DMEM_CON,
- (u32)(HALMAC_REG_READ_32(halmac_adapter, REG_CPU_DMEM_CON) |
- BIT_WL_PLATFORM_RST));
-
- /* halmac_api->halmac_init_h2c(halmac_adapter); */
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_init_system_cfg <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_edca_cfg_88xx() - init EDCA config
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_edca_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- u8 value8;
- u32 value32;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_EDCA_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- /* Clear TX pause */
- HALMAC_REG_WRITE_16(halmac_adapter, REG_TXPAUSE, 0x0000);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SLOT, HALMAC_SLOT_TIME_88XX);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PIFS, HALMAC_PIFS_TIME_88XX);
- value32 = HALMAC_SIFS_CCK_CTX_88XX |
- (HALMAC_SIFS_OFDM_CTX_88XX << BIT_SHIFT_SIFS_OFDM_CTX) |
- (HALMAC_SIFS_CCK_TRX_88XX << BIT_SHIFT_SIFS_CCK_TRX) |
- (HALMAC_SIFS_OFDM_TRX_88XX << BIT_SHIFT_SIFS_OFDM_TRX);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_SIFS, value32);
-
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_EDCA_VO_PARAM,
- HALMAC_REG_READ_32(halmac_adapter, REG_EDCA_VO_PARAM) & 0xFFFF);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_EDCA_VO_PARAM + 2,
- HALMAC_VO_TXOP_LIMIT_88XX);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_EDCA_VI_PARAM + 2,
- HALMAC_VI_TXOP_LIMIT_88XX);
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_RD_NAV_NXT,
- HALMAC_RDG_NAV_88XX | (HALMAC_TXOP_NAV_88XX << 16));
- HALMAC_REG_WRITE_16(halmac_adapter, REG_RXTSF_OFFSET_CCK,
- HALMAC_CCK_RX_TSF_88XX |
- (HALMAC_OFDM_RX_TSF_88XX) << 8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_RD_CTRL + 1);
- value8 |=
- (BIT_VOQ_RD_INIT_EN | BIT_VIQ_RD_INIT_EN | BIT_BEQ_RD_INIT_EN);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RD_CTRL + 1, value8);
-
- /* Set beacon cotnrol - enable TSF and other related functions */
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_BCN_CTRL,
- (u8)(HALMAC_REG_READ_8(halmac_adapter, REG_BCN_CTRL) |
- BIT_EN_BCN_FUNCTION));
-
- /* Set send beacon related registers */
- HALMAC_REG_WRITE_32(halmac_adapter, REG_TBTT_PROHIBIT,
- HALMAC_TBTT_PROHIBIT_88XX |
- (HALMAC_TBTT_HOLD_TIME_88XX
- << BIT_SHIFT_TBTT_HOLD_TIME_AP));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_DRVERLYINT,
- HALMAC_DRIVER_EARLY_INT_88XX);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_BCNDMATIM,
- HALMAC_BEACON_DMA_TIM_88XX);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_wmac_cfg_88xx() - init wmac config
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_wmac_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_WMAC_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_RXFLTMAP0,
- HALMAC_RX_FILTER0_88XX);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_RXFLTMAP,
- HALMAC_RX_FILTER_88XX);
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_RCR, HALMAC_RCR_CONFIG_88XX);
-
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_TCR + 1,
- (u8)(HALMAC_REG_READ_8(halmac_adapter, REG_TCR + 1) | 0x30));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TCR + 2, 0x30);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TCR + 1, 0x00);
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_WMAC_OPTION_FUNCTION + 8,
- 0x30810041);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_WMAC_OPTION_FUNCTION + 4,
- 0x50802080);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_mac_cfg_88xx() - config page1~page7 register
- * @halmac_adapter : the adapter of halmac
- * @mode : trx mode
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_mac_cfg_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode mode)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_MAC_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>mode = %d\n", __func__,
- mode);
-
- status = halmac_api->halmac_init_trx_cfg(halmac_adapter, mode);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_init_trx_cfg error = %x\n", status);
- return status;
- }
- status = halmac_api->halmac_init_protocol_cfg(halmac_adapter);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_init_protocol_cfg_88xx error = %x\n", status);
- return status;
- }
-
- status = halmac_init_edca_cfg_88xx(halmac_adapter);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_init_edca_cfg_88xx error = %x\n", status);
- return status;
- }
-
- status = halmac_init_wmac_cfg_88xx(halmac_adapter);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_init_wmac_cfg_88xx error = %x\n", status);
- return status;
- }
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return status;
-}
-
-/**
- * halmac_cfg_operation_mode_88xx() - config operation mode
- * @halmac_adapter : the adapter of halmac
- * @wireless_mode : 802.11 standard(b/g/n/ac)
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_operation_mode_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_wireless_mode wireless_mode)
-{
- void *driver_adapter = NULL;
- enum halmac_wireless_mode wireless_mode_local =
- HALMAC_WIRELESS_MODE_UNDEFINE;
-
- wireless_mode_local = wireless_mode;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_CFG_OPERATION_MODE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>wireless_mode = %d\n", __func__,
- wireless_mode);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_ch_bw_88xx() - config channel & bandwidth
- * @halmac_adapter : the adapter of halmac
- * @channel : WLAN channel, support 2.4G & 5G
- * @pri_ch_idx : primary channel index, idx1, idx2, idx3, idx4
- * @bw : band width, 20, 40, 80, 160, 5 ,10
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_ch_bw_88xx(struct halmac_adapter *halmac_adapter, u8 channel,
- enum halmac_pri_ch_idx pri_ch_idx, enum halmac_bw bw)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_CH_BW);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>ch = %d, idx=%d, bw=%d\n", __func__,
- channel, pri_ch_idx, bw);
-
- halmac_cfg_pri_ch_idx_88xx(halmac_adapter, pri_ch_idx);
-
- halmac_cfg_bw_88xx(halmac_adapter, bw);
-
- halmac_cfg_ch_88xx(halmac_adapter, channel);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_cfg_ch_88xx(struct halmac_adapter *halmac_adapter,
- u8 channel)
-{
- u8 value8;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_CH_BW);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>ch = %d\n", __func__, channel);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CCK_CHECK);
- value8 = value8 & (~(BIT(7)));
-
- if (channel > 35)
- value8 = value8 | BIT(7);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CCK_CHECK, value8);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_cfg_pri_ch_idx_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_pri_ch_idx pri_ch_idx)
-{
- u8 txsc_40 = 0, txsc_20 = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_CH_BW);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========> idx=%d\n", __func__,
- pri_ch_idx);
-
- txsc_20 = pri_ch_idx;
- if (txsc_20 == HALMAC_CH_IDX_1 || txsc_20 == HALMAC_CH_IDX_3)
- txsc_40 = 9;
- else
- txsc_40 = 10;
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_DATA_SC,
- BIT_TXSC_20M(txsc_20) | BIT_TXSC_40M(txsc_40));
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_bw_88xx() - config bandwidth
- * @halmac_adapter : the adapter of halmac
- * @bw : band width, 20, 40, 80, 160, 5 ,10
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_cfg_bw_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_bw bw)
-{
- u32 value32;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_BW);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>bw=%d\n", __func__, bw);
-
- /* RF mode */
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_WMAC_TRXPTCL_CTL);
- value32 = value32 & (~(BIT(7) | BIT(8)));
-
- switch (bw) {
- case HALMAC_BW_80:
- value32 = value32 | BIT(7);
- break;
- case HALMAC_BW_40:
- value32 = value32 | BIT(8);
- break;
- case HALMAC_BW_20:
- case HALMAC_BW_10:
- case HALMAC_BW_5:
- break;
- default:
- pr_err("%s switch case not support\n", __func__);
- break;
- }
- HALMAC_REG_WRITE_32(halmac_adapter, REG_WMAC_TRXPTCL_CTL, value32);
-
- /* MAC CLK */
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_AFE_CTRL1);
- value32 = (value32 & (~(BIT(20) | BIT(21)))) |
- (HALMAC_MAC_CLOCK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_AFE_CTRL1, value32);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_USTIME_TSF,
- HALMAC_MAC_CLOCK_88XX);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_USTIME_EDCA,
- HALMAC_MAC_CLOCK_88XX);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_dump_efuse_map_88xx() - dump "physical" efuse map
- * @halmac_adapter : the adapter of halmac
- * @cfg : dump efuse method
- * Author : Ivan Lin/KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_dump_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_read_cfg cfg)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.efuse_state_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DUMP_EFUSE_MAP);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>cfg=%d\n", __func__, cfg);
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (halmac_query_efuse_curr_state_88xx(halmac_adapter) !=
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF)
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_WARNING,
- "[WARN]Dump efuse in suspend mode\n");
-
- *process_status = HALMAC_CMD_PROCESS_IDLE;
- halmac_adapter->event_trigger.physical_efuse_map = 1;
-
- status = halmac_func_switch_efuse_bank_88xx(halmac_adapter,
- HALMAC_EFUSE_BANK_WIFI);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_dump_efuse_88xx(halmac_adapter, cfg);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_read_efuse error = %x\n", status);
- return status;
- }
-
- if (halmac_adapter->hal_efuse_map_valid) {
- *process_status = HALMAC_CMD_PROCESS_DONE;
-
- PLATFORM_EVENT_INDICATION(
- driver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,
- *process_status, halmac_adapter->hal_efuse_map,
- halmac_adapter->hw_config_info.efuse_size);
- halmac_adapter->event_trigger.physical_efuse_map = 0;
- }
-
- if (halmac_transition_efuse_state_88xx(
- halmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_dump_efuse_map_bt_88xx() - dump "BT physical" efuse map
- * @halmac_adapter : the adapter of halmac
- * @halmac_efuse_bank : bt efuse bank
- * @bt_efuse_map_size : bt efuse map size. get from halmac_get_efuse_size API
- * @bt_efuse_map : bt efuse map
- * Author : Soar / Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_dump_efuse_map_bt_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_bank halmac_efuse_bank,
- u32 bt_efuse_map_size, u8 *bt_efuse_map)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.efuse_state_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DUMP_EFUSE_MAP_BT);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (halmac_adapter->hw_config_info.bt_efuse_size != bt_efuse_map_size)
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
-
- if ((halmac_efuse_bank >= HALMAC_EFUSE_BANK_MAX) ||
- halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI) {
- pr_err("Undefined BT bank\n");
- return HALMAC_RET_EFUSE_BANK_INCORRECT;
- }
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (halmac_query_efuse_curr_state_88xx(halmac_adapter) !=
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- status = halmac_func_switch_efuse_bank_88xx(halmac_adapter,
- halmac_efuse_bank);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_read_hw_efuse_88xx(halmac_adapter, 0, bt_efuse_map_size,
- bt_efuse_map);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_read_hw_efuse_88xx error = %x\n", status);
- return status;
- }
-
- if (halmac_transition_efuse_state_88xx(
- halmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_write_efuse_bt_88xx() - write "BT physical" efuse offset
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : offset
- * @halmac_value : Write value
- * @bt_efuse_map : bt efuse map
- * Author : Soar
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_write_efuse_bt_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_value,
- enum halmac_efuse_bank halmac_efuse_bank)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.efuse_state_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_WRITE_EFUSE_BT);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s ==========>\n", __func__);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "offset : %X value : %X Bank : %X\n", halmac_offset,
- halmac_value, halmac_efuse_bank);
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (halmac_query_efuse_curr_state_88xx(halmac_adapter) !=
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (halmac_offset >= halmac_adapter->hw_config_info.efuse_size) {
- pr_err("Offset is too large\n");
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if (halmac_efuse_bank > HALMAC_EFUSE_BANK_MAX ||
- halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI) {
- pr_err("Undefined BT bank\n");
- return HALMAC_RET_EFUSE_BANK_INCORRECT;
- }
-
- status = halmac_func_switch_efuse_bank_88xx(halmac_adapter,
- halmac_efuse_bank);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_func_write_efuse_88xx(halmac_adapter, halmac_offset,
- halmac_value);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_func_write_efuse error = %x\n", status);
- return status;
- }
-
- if (halmac_transition_efuse_state_88xx(
- halmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_efuse_available_size_88xx() - get efuse available size
- * @halmac_adapter : the adapter of halmac
- * @halmac_size : physical efuse available size
- * Author : Soar
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_get_efuse_available_size_88xx(struct halmac_adapter *halmac_adapter,
- u32 *halmac_size)
-{
- enum halmac_ret_status status;
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- status = halmac_dump_logical_efuse_map_88xx(halmac_adapter,
- HALMAC_EFUSE_R_DRV);
-
- if (status != HALMAC_RET_SUCCESS)
- return status;
-
- *halmac_size = halmac_adapter->hw_config_info.efuse_size -
- HALMAC_PROTECTED_EFUSE_SIZE_88XX -
- halmac_adapter->efuse_end;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_efuse_size_88xx() - get "physical" efuse size
- * @halmac_adapter : the adapter of halmac
- * @halmac_size : physical efuse size
- * Author : Ivan Lin/KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_get_efuse_size_88xx(struct halmac_adapter *halmac_adapter,
- u32 *halmac_size)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_GET_EFUSE_SIZE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- *halmac_size = halmac_adapter->hw_config_info.efuse_size;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_logical_efuse_size_88xx() - get "logical" efuse size
- * @halmac_adapter : the adapter of halmac
- * @halmac_size : logical efuse size
- * Author : Ivan Lin/KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_get_logical_efuse_size_88xx(struct halmac_adapter *halmac_adapter,
- u32 *halmac_size)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_GET_LOGICAL_EFUSE_SIZE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- *halmac_size = halmac_adapter->hw_config_info.eeprom_size;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_dump_logical_efuse_map_88xx() - dump "logical" efuse map
- * @halmac_adapter : the adapter of halmac
- * @cfg : dump efuse method
- * Author : Soar
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_dump_logical_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_read_cfg cfg)
-{
- u8 *eeprom_map = NULL;
- u32 eeprom_size = halmac_adapter->hw_config_info.eeprom_size;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.efuse_state_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_DUMP_LOGICAL_EFUSE_MAP);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s ==========>cfg = %d\n", __func__, cfg);
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (halmac_query_efuse_curr_state_88xx(halmac_adapter) !=
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF)
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_WARNING,
- "[WARN]Dump logical efuse in suspend mode\n");
-
- *process_status = HALMAC_CMD_PROCESS_IDLE;
- halmac_adapter->event_trigger.logical_efuse_map = 1;
-
- status = halmac_func_switch_efuse_bank_88xx(halmac_adapter,
- HALMAC_EFUSE_BANK_WIFI);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_dump_efuse_88xx(halmac_adapter, cfg);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_eeprom_parser_88xx error = %x\n", status);
- return status;
- }
-
- if (halmac_adapter->hal_efuse_map_valid) {
- *process_status = HALMAC_CMD_PROCESS_DONE;
-
- eeprom_map = kzalloc(eeprom_size, GFP_KERNEL);
- if (!eeprom_map) {
- /* out of memory */
- return HALMAC_RET_MALLOC_FAIL;
- }
- memset(eeprom_map, 0xFF, eeprom_size);
-
- if (halmac_eeprom_parser_88xx(halmac_adapter,
- halmac_adapter->hal_efuse_map,
- eeprom_map) != HALMAC_RET_SUCCESS) {
- kfree(eeprom_map);
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- }
-
- PLATFORM_EVENT_INDICATION(
- driver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE,
- *process_status, eeprom_map, eeprom_size);
- halmac_adapter->event_trigger.logical_efuse_map = 0;
-
- kfree(eeprom_map);
- }
-
- if (halmac_transition_efuse_state_88xx(
- halmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_read_logical_efuse_88xx() - read logical efuse map 1 byte
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : offset
- * @value : 1 byte efuse value
- * Author : Soar
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_read_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 *value)
-{
- u8 *eeprom_map = NULL;
- u32 eeprom_size = halmac_adapter->hw_config_info.eeprom_size;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.efuse_state_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_READ_LOGICAL_EFUSE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (halmac_offset >= eeprom_size) {
- pr_err("Offset is too large\n");
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
- if (halmac_query_efuse_curr_state_88xx(halmac_adapter) !=
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- status = halmac_func_switch_efuse_bank_88xx(halmac_adapter,
- HALMAC_EFUSE_BANK_WIFI);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- eeprom_map = kzalloc(eeprom_size, GFP_KERNEL);
- if (!eeprom_map) {
- /* out of memory */
- return HALMAC_RET_MALLOC_FAIL;
- }
- memset(eeprom_map, 0xFF, eeprom_size);
-
- status = halmac_read_logical_efuse_map_88xx(halmac_adapter, eeprom_map);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_read_logical_efuse_map error = %x\n", status);
- kfree(eeprom_map);
- return status;
- }
-
- *value = *(eeprom_map + halmac_offset);
-
- if (halmac_transition_efuse_state_88xx(
- halmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS) {
- kfree(eeprom_map);
- return HALMAC_RET_ERROR_STATE;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- kfree(eeprom_map);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_write_logical_efuse_88xx() - write "logical" efuse offset
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : offset
- * @halmac_value : value
- * Author : Soar
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_write_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_value)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.efuse_state_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_WRITE_LOGICAL_EFUSE);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (halmac_offset >= halmac_adapter->hw_config_info.eeprom_size) {
- pr_err("Offset is too large\n");
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (halmac_query_efuse_curr_state_88xx(halmac_adapter) !=
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- status = halmac_func_switch_efuse_bank_88xx(halmac_adapter,
- HALMAC_EFUSE_BANK_WIFI);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_func_write_logical_efuse_88xx(
- halmac_adapter, halmac_offset, halmac_value);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_write_logical_efuse error = %x\n", status);
- return status;
- }
-
- if (halmac_transition_efuse_state_88xx(
- halmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_pg_efuse_by_map_88xx() - pg logical efuse by map
- * @halmac_adapter : the adapter of halmac
- * @pg_efuse_info : efuse map information
- * @cfg : dump efuse method
- * Author : Soar
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_pg_efuse_by_map_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- enum halmac_efuse_read_cfg cfg)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.efuse_state_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PG_EFUSE_BY_MAP);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (pg_efuse_info->efuse_map_size !=
- halmac_adapter->hw_config_info.eeprom_size) {
- pr_err("efuse_map_size is incorrect, should be %d bytes\n",
- halmac_adapter->hw_config_info.eeprom_size);
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if ((pg_efuse_info->efuse_map_size & 0xF) > 0) {
- pr_err("efuse_map_size should be multiple of 16\n");
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if (pg_efuse_info->efuse_mask_size !=
- pg_efuse_info->efuse_map_size >> 4) {
- pr_err("efuse_mask_size is incorrect, should be %d bytes\n",
- pg_efuse_info->efuse_map_size >> 4);
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if (!pg_efuse_info->efuse_map) {
- pr_err("efuse_map is NULL\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- if (!pg_efuse_info->efuse_mask) {
- pr_err("efuse_mask is NULL\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (halmac_query_efuse_curr_state_88xx(halmac_adapter) !=
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- status = halmac_func_switch_efuse_bank_88xx(halmac_adapter,
- HALMAC_EFUSE_BANK_WIFI);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_func_pg_efuse_by_map_88xx(halmac_adapter, pg_efuse_info,
- cfg);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_pg_efuse_by_map error = %x\n", status);
- return status;
- }
-
- if (halmac_transition_efuse_state_88xx(
- halmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_EFUSE, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_c2h_info_88xx() - process halmac C2H packet
- * @halmac_adapter : the adapter of halmac
- * @halmac_buf : RX Packet pointer
- * @halmac_size : RX Packet size
- * Author : KaiYuan Chang/Ivan Lin
- *
- * Used to process c2h packet info from RX path. After receiving the packet,
- * user need to call this api and pass the packet pointer.
- *
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_get_c2h_info_88xx(struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
- u32 halmac_size)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_GET_C2H_INFO);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- /* Check if it is C2H packet */
- if (GET_RX_DESC_C2H(halmac_buf)) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "C2H packet, start parsing!\n");
-
- status = halmac_parse_c2h_packet_88xx(halmac_adapter,
- halmac_buf, halmac_size);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_parse_c2h_packet_88xx error = %x\n",
- status);
- return status;
- }
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_cfg_fwlps_option_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_fwlps_option *lps_option)
-{
- void *driver_adapter = NULL;
- struct halmac_fwlps_option *hal_fwlps_option;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_FWLPS_OPTION);
-
- driver_adapter = halmac_adapter->driver_adapter;
- hal_fwlps_option = &halmac_adapter->fwlps_option;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- hal_fwlps_option->mode = lps_option->mode;
- hal_fwlps_option->clk_request = lps_option->clk_request;
- hal_fwlps_option->rlbm = lps_option->rlbm;
- hal_fwlps_option->smart_ps = lps_option->smart_ps;
- hal_fwlps_option->awake_interval = lps_option->awake_interval;
- hal_fwlps_option->all_queue_uapsd = lps_option->all_queue_uapsd;
- hal_fwlps_option->pwr_state = lps_option->pwr_state;
- hal_fwlps_option->low_pwr_rx_beacon = lps_option->low_pwr_rx_beacon;
- hal_fwlps_option->ant_auto_switch = lps_option->ant_auto_switch;
- hal_fwlps_option->ps_allow_bt_high_priority =
- lps_option->ps_allow_bt_high_priority;
- hal_fwlps_option->protect_bcn = lps_option->protect_bcn;
- hal_fwlps_option->silence_period = lps_option->silence_period;
- hal_fwlps_option->fast_bt_connect = lps_option->fast_bt_connect;
- hal_fwlps_option->two_antenna_en = lps_option->two_antenna_en;
- hal_fwlps_option->adopt_user_setting = lps_option->adopt_user_setting;
- hal_fwlps_option->drv_bcn_early_shift = lps_option->drv_bcn_early_shift;
- hal_fwlps_option->enter_32K = lps_option->enter_32K;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_cfg_fwips_option_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_fwips_option *ips_option)
-{
- void *driver_adapter = NULL;
- struct halmac_fwips_option *ips_option_local;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_FWIPS_OPTION);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- ips_option_local = ips_option;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_enter_wowlan_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_wowlan_option *wowlan_option)
-{
- void *driver_adapter = NULL;
- struct halmac_wowlan_option *wowlan_option_local;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_ENTER_WOWLAN);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- wowlan_option_local = wowlan_option;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_leave_wowlan_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_LEAVE_WOWLAN);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_enter_ps_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_ps_state ps_state)
-{
- u8 rpwm;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_ENTER_PS);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (ps_state == halmac_adapter->halmac_state.ps_state) {
- pr_err("power state is already in PS State!!\n");
- return HALMAC_RET_SUCCESS;
- }
-
- if (ps_state == HALMAC_PS_STATE_LPS) {
- status = halmac_send_h2c_set_pwr_mode_88xx(
- halmac_adapter, &halmac_adapter->fwlps_option);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_set_pwr_mode_88xx error = %x!!\n",
- status);
- return status;
- }
- } else if (ps_state == HALMAC_PS_STATE_IPS) {
- }
-
- halmac_adapter->halmac_state.ps_state = ps_state;
-
- /* Enter 32K */
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- if (halmac_adapter->fwlps_option.enter_32K) {
- rpwm = (u8)(((halmac_adapter->rpwm_record ^ (BIT(7))) |
- (BIT(0))) &
- 0x81);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SDIO_HRPWM1,
- rpwm);
- halmac_adapter->low_clk = true;
- }
- } else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
- if (halmac_adapter->fwlps_option.enter_32K) {
- rpwm = (u8)(((halmac_adapter->rpwm_record ^ (BIT(7))) |
- (BIT(0))) &
- 0x81);
- HALMAC_REG_WRITE_8(halmac_adapter, 0xFE58, rpwm);
- halmac_adapter->low_clk = true;
- }
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_leave_ps_88xx(struct halmac_adapter *halmac_adapter)
-{
- u8 rpwm, cpwm;
- u32 counter;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- struct halmac_fwlps_option fw_lps_option;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_LEAVE_PS);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (halmac_adapter->halmac_state.ps_state == HALMAC_PS_STATE_ACT) {
- pr_err("power state is already in active!!\n");
- return HALMAC_RET_SUCCESS;
- }
-
- if (halmac_adapter->low_clk) {
- cpwm = HALMAC_REG_READ_8(halmac_adapter, REG_SDIO_HRPWM1);
- rpwm = (u8)(
- ((halmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(6))) &
- 0xC0);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SDIO_HRPWM1, rpwm);
-
- cpwm = (u8)((cpwm ^ BIT(7)) & BIT(7));
- counter = 100;
- while (cpwm !=
- (HALMAC_REG_READ_8(halmac_adapter, REG_SDIO_HRPWM1) &
- BIT(7))) {
- usleep_range(50, 60);
- counter--;
- if (counter == 0)
- return HALMAC_RET_CHANGE_PS_FAIL;
- }
- halmac_adapter->low_clk = false;
- }
-
- memcpy(&fw_lps_option, &halmac_adapter->fwlps_option,
- sizeof(struct halmac_fwlps_option));
- fw_lps_option.mode = 0;
-
- status = halmac_send_h2c_set_pwr_mode_88xx(halmac_adapter,
- &fw_lps_option);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_set_pwr_mode_88xx error!!=%x\n",
- status);
- return status;
- }
-
- halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * (debug API)halmac_h2c_lb_88xx() - send h2c loopback packet
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_h2c_lb_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_H2C_LB);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_debug_88xx() - dump information for debugging
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_debug_88xx(struct halmac_adapter *halmac_adapter)
-{
- u8 temp8 = 0;
- u32 i = 0, temp32 = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEBUG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- /* Dump CCCR, it needs new platform api */
-
- /*Dump SDIO Local Register, use CMD52*/
- for (i = 0x10250000; i < 0x102500ff; i++) {
- temp8 = PLATFORM_SDIO_CMD52_READ(halmac_adapter, i);
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_debug: sdio[%x]=%x\n", i, temp8);
- }
-
- /*Dump MAC Register*/
- for (i = 0x0000; i < 0x17ff; i++) {
- temp8 = PLATFORM_SDIO_CMD52_READ(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT,
- DBG_DMESG, "halmac_debug: mac[%x]=%x\n",
- i, temp8);
- }
-
- /*Check RX Fifo status*/
- i = REG_RXFF_PTR_V1;
- temp8 = PLATFORM_SDIO_CMD52_READ(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_debug: mac[%x]=%x\n", i, temp8);
- i = REG_RXFF_WTR_V1;
- temp8 = PLATFORM_SDIO_CMD52_READ(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_debug: mac[%x]=%x\n", i, temp8);
- i = REG_RXFF_PTR_V1;
- temp8 = PLATFORM_SDIO_CMD52_READ(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_debug: mac[%x]=%x\n", i, temp8);
- i = REG_RXFF_WTR_V1;
- temp8 = PLATFORM_SDIO_CMD52_READ(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_debug: mac[%x]=%x\n", i, temp8);
- } else {
- /*Dump MAC Register*/
- for (i = 0x0000; i < 0x17fc; i += 4) {
- temp32 = HALMAC_REG_READ_32(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT,
- DBG_DMESG, "halmac_debug: mac[%x]=%x\n",
- i, temp32);
- }
-
- /*Check RX Fifo status*/
- i = REG_RXFF_PTR_V1;
- temp32 = HALMAC_REG_READ_32(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_debug: mac[%x]=%x\n", i, temp32);
- i = REG_RXFF_WTR_V1;
- temp32 = HALMAC_REG_READ_32(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_debug: mac[%x]=%x\n", i, temp32);
- i = REG_RXFF_PTR_V1;
- temp32 = HALMAC_REG_READ_32(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_debug: mac[%x]=%x\n", i, temp32);
- i = REG_RXFF_WTR_V1;
- temp32 = HALMAC_REG_READ_32(halmac_adapter, i);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_debug: mac[%x]=%x\n", i, temp32);
- }
-
- /* TODO: Add check register code, including MAC CLK, CPU CLK */
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_parameter_88xx() - config parameter by FW
- * @halmac_adapter : the adapter of halmac
- * @para_info : cmd id, content
- * @full_fifo : parameter information
- *
- * If msk_en = true, the format of array is {reg_info, mask, value}.
- * If msk_en =_FAUSE, the format of array is {reg_info, value}
- * The format of reg_info is
- * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg
- * reg_info[27:24]=rf_path, 0: path_A, 1: path_B
- * if rf_reg=0(MAC_BB reg), rf_path is meaningless.
- * ref_info[15:0]=offset
- *
- * Example: msk_en = false
- * {0x8100000a, 0x00001122}
- * =>Set RF register, path_B, offset 0xA to 0x00001122
- * {0x00000824, 0x11224433}
- * =>Set MAC_BB register, offset 0x800 to 0x11224433
- *
- * Note : full fifo mode only for init flow
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_parameter_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_phy_parameter_info *para_info,
- u8 full_fifo)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.cfg_para_state_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- if (halmac_adapter->fw_version.h2c_version < 4)
- return HALMAC_RET_FW_NO_SUPPORT;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_PARAMETER);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- if (halmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) {
- pr_err("%s Fail due to DLFW NONE!!\n", __func__);
- return HALMAC_RET_DLFW_FAIL;
- }
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait event(cfg para)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (halmac_query_cfg_para_curr_state_88xx(halmac_adapter) !=
- HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE &&
- halmac_query_cfg_para_curr_state_88xx(halmac_adapter) !=
- HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Not idle state(cfg para)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- *process_status = HALMAC_CMD_PROCESS_IDLE;
-
- ret_status = halmac_send_h2c_phy_parameter_88xx(halmac_adapter,
- para_info, full_fifo);
-
- if (ret_status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_phy_parameter_88xx Fail!! = %x\n",
- ret_status);
- return ret_status;
- }
-
- return ret_status;
-}
-
-/**
- * halmac_update_packet_88xx() - send specific packet to FW
- * @halmac_adapter : the adapter of halmac
- * @pkt_id : packet id, to know the purpose of this packet
- * @pkt : packet
- * @pkt_size : packet size
- *
- * Note : TX_DESC is not included in the pkt
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_update_packet_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_packet_id pkt_id, u8 *pkt, u32 pkt_size)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.update_packet_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- if (halmac_adapter->fw_version.h2c_version < 4)
- return HALMAC_RET_FW_NO_SUPPORT;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_UPDATE_PACKET);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait event(update_packet)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- *process_status = HALMAC_CMD_PROCESS_SENDING;
-
- status = halmac_send_h2c_update_packet_88xx(halmac_adapter, pkt_id, pkt,
- pkt_size);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_update_packet_88xx packet = %x, fail = %x!!\n",
- pkt_id, status);
- return status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_bcn_ie_filter_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_bcn_ie_info *bcn_ie_info)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- if (halmac_adapter->fw_version.h2c_version < 4)
- return HALMAC_RET_FW_NO_SUPPORT;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_BCN_IE_FILTER);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- status = halmac_send_h2c_update_bcn_parse_info_88xx(halmac_adapter,
- bcn_ie_info);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_update_bcn_parse_info_88xx fail = %x\n",
- status);
- return status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_update_datapack_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_data_type halmac_data_type,
- struct halmac_phy_parameter_info *para_info)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- if (halmac_adapter->fw_version.h2c_version < 4)
- return HALMAC_RET_FW_NO_SUPPORT;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_data_type halmac_data_type)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- if (halmac_adapter->fw_version.h2c_version < 4)
- return HALMAC_RET_FW_NO_SUPPORT;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_RUN_DATAPACK);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- ret_status = halmac_send_h2c_run_datapack_88xx(halmac_adapter,
- halmac_data_type);
-
- if (ret_status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_run_datapack_88xx Fail, datatype = %x, status = %x!!\n",
- halmac_data_type, ret_status);
- return ret_status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "halmac_update_datapack_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_drv_info_88xx() - config driver info
- * @halmac_adapter : the adapter of halmac
- * @halmac_drv_info : driver information selection
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_drv_info_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_drv_info halmac_drv_info)
-{
- u8 drv_info_size = 0;
- u8 phy_status_en = 0;
- u8 sniffer_en = 0;
- u8 plcp_hdr_en = 0;
- u32 value32;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_DRV_INFO);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "halmac_cfg_drv_info = %d\n", halmac_drv_info);
-
- switch (halmac_drv_info) {
- case HALMAC_DRV_INFO_NONE:
- drv_info_size = 0;
- phy_status_en = 0;
- sniffer_en = 0;
- plcp_hdr_en = 0;
- break;
- case HALMAC_DRV_INFO_PHY_STATUS:
- drv_info_size = 4;
- phy_status_en = 1;
- sniffer_en = 0;
- plcp_hdr_en = 0;
- break;
- case HALMAC_DRV_INFO_PHY_SNIFFER:
- drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */
- phy_status_en = 1;
- sniffer_en = 1;
- plcp_hdr_en = 0;
- break;
- case HALMAC_DRV_INFO_PHY_PLCP:
- drv_info_size = 6; /* phy status 4byte, plcp header 2byte */
- phy_status_en = 1;
- sniffer_en = 0;
- plcp_hdr_en = 1;
- break;
- default:
- status = HALMAC_RET_SW_CASE_NOT_SUPPORT;
- pr_err("%s error = %x\n", __func__, status);
- return status;
- }
-
- if (halmac_adapter->txff_allocation.rx_fifo_expanding_mode !=
- HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
- drv_info_size = 0xF;
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RX_DRVINFO_SZ, drv_info_size);
-
- halmac_adapter->drv_info_size = drv_info_size;
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_RCR);
- value32 = (value32 & (~BIT_APP_PHYSTS));
- if (phy_status_en == 1)
- value32 = value32 | BIT_APP_PHYSTS;
- HALMAC_REG_WRITE_32(halmac_adapter, REG_RCR, value32);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter,
- REG_WMAC_OPTION_FUNCTION + 4);
- value32 = (value32 & (~(BIT(8) | BIT(9))));
- if (sniffer_en == 1)
- value32 = value32 | BIT(9);
- if (plcp_hdr_en == 1)
- value32 = value32 | BIT(8);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_WMAC_OPTION_FUNCTION + 4,
- value32);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_send_bt_coex_88xx(struct halmac_adapter *halmac_adapter, u8 *bt_buf,
- u32 bt_size, u8 ack)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_SEND_BT_COEX);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- ret_status = halmac_send_bt_coex_cmd_88xx(halmac_adapter, bt_buf,
- bt_size, ack);
-
- if (ret_status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_bt_coex_cmd_88xx Fail = %x!!\n",
- ret_status);
- return ret_status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * (debug API)halmac_verify_platform_api_88xx() - verify platform api
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_verify_platform_api_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_VERIFY_PLATFORM_API);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- ret_status = halmac_verify_io_88xx(halmac_adapter);
-
- if (ret_status != HALMAC_RET_SUCCESS)
- return ret_status;
-
- if (halmac_adapter->txff_allocation.la_mode != HALMAC_LA_MODE_FULL)
- ret_status = halmac_verify_send_rsvd_page_88xx(halmac_adapter);
-
- if (ret_status != HALMAC_RET_SUCCESS)
- return ret_status;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return ret_status;
-}
-
-enum halmac_ret_status
-halmac_send_original_h2c_88xx(struct halmac_adapter *halmac_adapter,
- u8 *original_h2c, u16 *seq, u8 ack)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_SEND_ORIGINAL_H2C);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- status = halmac_func_send_original_h2c_88xx(halmac_adapter,
- original_h2c, seq, ack);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_original_h2c FAIL = %x!!\n", status);
- return status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_timer_2s_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_fill_txdesc_check_sum_88xx() - fill in tx desc check sum
- * @halmac_adapter : the adapter of halmac
- * @cur_desc : tx desc packet
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_fill_txdesc_check_sum_88xx(struct halmac_adapter *halmac_adapter,
- u8 *cur_desc)
-{
- u16 chk_result = 0;
- u16 *data = (u16 *)NULL;
- u32 i;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_FILL_TXDESC_CHECKSUM);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (!cur_desc) {
- pr_err("%s NULL PTR", __func__);
- return HALMAC_RET_NULL_POINTER;
- }
-
- SET_TX_DESC_TXDESC_CHECKSUM(cur_desc, 0x0000);
-
- data = (u16 *)(cur_desc);
-
- /* HW clculates only 32byte */
- for (i = 0; i < 8; i++)
- chk_result ^= (*(data + 2 * i) ^ *(data + (2 * i + 1)));
-
- SET_TX_DESC_TXDESC_CHECKSUM(cur_desc, chk_result);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_dump_fifo_88xx() - dump fifo data
- * @halmac_adapter : the adapter of halmac
- * @halmac_fifo_sel : FIFO selection
- * @halmac_start_addr : start address of selected FIFO
- * @halmac_fifo_dump_size : dump size of selected FIFO
- * @fifo_map : FIFO data
- *
- * Note : before dump fifo, user need to call halmac_get_fifo_size to
- * get fifo size. Then input this size to halmac_dump_fifo.
- *
- * Author : Ivan Lin/KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_dump_fifo_88xx(struct halmac_adapter *halmac_adapter,
- enum hal_fifo_sel halmac_fifo_sel, u32 halmac_start_addr,
- u32 halmac_fifo_dump_size, u8 *fifo_map)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DUMP_FIFO);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (halmac_fifo_sel == HAL_FIFO_SEL_TX &&
- (halmac_start_addr + halmac_fifo_dump_size) >
- halmac_adapter->hw_config_info.tx_fifo_size) {
- pr_err("TX fifo dump size is too large\n");
- return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
- }
-
- if (halmac_fifo_sel == HAL_FIFO_SEL_RX &&
- (halmac_start_addr + halmac_fifo_dump_size) >
- halmac_adapter->hw_config_info.rx_fifo_size) {
- pr_err("RX fifo dump size is too large\n");
- return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
- }
-
- if ((halmac_fifo_dump_size & (4 - 1)) != 0) {
- pr_err("halmac_fifo_dump_size shall 4byte align\n");
- return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
- }
-
- if (!fifo_map) {
- pr_err("fifo_map address is NULL\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- status = halmac_buffer_read_88xx(halmac_adapter, halmac_start_addr,
- halmac_fifo_dump_size, halmac_fifo_sel,
- fifo_map);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_buffer_read_88xx error = %x\n", status);
- return status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_fifo_size_88xx() - get fifo size
- * @halmac_adapter : the adapter of halmac
- * @halmac_fifo_sel : FIFO selection
- * Author : Ivan Lin/KaiYuan Chang
- * Return : u32
- * More details of status code can be found in prototype document
- */
-u32 halmac_get_fifo_size_88xx(struct halmac_adapter *halmac_adapter,
- enum hal_fifo_sel halmac_fifo_sel)
-{
- u32 fifo_size = 0;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_GET_FIFO_SIZE);
-
- if (halmac_fifo_sel == HAL_FIFO_SEL_TX)
- fifo_size = halmac_adapter->hw_config_info.tx_fifo_size;
- else if (halmac_fifo_sel == HAL_FIFO_SEL_RX)
- fifo_size = halmac_adapter->hw_config_info.rx_fifo_size;
- else if (halmac_fifo_sel == HAL_FIFO_SEL_RSVD_PAGE)
- fifo_size =
- ((halmac_adapter->hw_config_info.tx_fifo_size >> 7) -
- halmac_adapter->txff_allocation.rsvd_pg_bndy)
- << 7;
- else if (halmac_fifo_sel == HAL_FIFO_SEL_REPORT)
- fifo_size = 65536;
- else if (halmac_fifo_sel == HAL_FIFO_SEL_LLT)
- fifo_size = 65536;
-
- return fifo_size;
-}
-
-/**
- * halmac_cfg_txbf_88xx() - enable/disable specific user's txbf
- * @halmac_adapter : the adapter of halmac
- * @userid : su bfee userid = 0 or 1 to apply TXBF
- * @bw : the sounding bandwidth
- * @txbf_en : 0: disable TXBF, 1: enable TXBF
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_txbf_88xx(struct halmac_adapter *halmac_adapter, u8 userid,
- enum halmac_bw bw, u8 txbf_en)
-{
- u16 temp42C = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TXBF);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (txbf_en) {
- switch (bw) {
- case HALMAC_BW_80:
- temp42C |= BIT_R_TXBF0_80M;
- /* fall through */
- case HALMAC_BW_40:
- temp42C |= BIT_R_TXBF0_40M;
- /* fall through */
- case HALMAC_BW_20:
- temp42C |= BIT_R_TXBF0_20M;
- break;
- default:
- pr_err("%s invalid TXBF BW setting 0x%x of userid %d\n",
- __func__, bw, userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
- }
-
- switch (userid) {
- case 0:
- temp42C |=
- HALMAC_REG_READ_16(halmac_adapter, REG_TXBF_CTRL) &
- ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_TXBF_CTRL, temp42C);
- break;
- case 1:
- temp42C |=
- HALMAC_REG_READ_16(halmac_adapter, REG_TXBF_CTRL + 2) &
- ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_TXBF_CTRL + 2, temp42C);
- break;
- default:
- pr_err("%s invalid userid %d\n", __func__, userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s, txbf_en = %x <==========\n", __func__,
- txbf_en);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_mumimo_88xx() -config mumimo
- * @halmac_adapter : the adapter of halmac
- * @cfgmu : parameters to configure MU PPDU Tx/Rx
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_mumimo_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_cfg_mumimo_para *cfgmu)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- u8 i, idx, id0, id1, gid, mu_tab_sel;
- u8 mu_tab_valid = 0;
- u32 gid_valid[6] = {0};
- u8 temp14C0 = 0;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_MUMIMO);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (cfgmu->role == HAL_BFEE) {
- /*config MU BFEE*/
- temp14C0 = HALMAC_REG_READ_8(halmac_adapter, REG_MU_TX_CTL) &
- ~BIT_MASK_R_MU_TABLE_VALID;
- /*enable MU table 0 and 1, disable MU TX*/
- HALMAC_REG_WRITE_8(halmac_adapter, REG_MU_TX_CTL,
- (temp14C0 | BIT(0) | BIT(1)) & ~(BIT(7)));
-
- /*config GID valid table and user position table*/
- mu_tab_sel =
- HALMAC_REG_READ_8(halmac_adapter, REG_MU_TX_CTL + 1) &
- ~(BIT(0) | BIT(1) | BIT(2));
- for (i = 0; i < 2; i++) {
- HALMAC_REG_WRITE_8(halmac_adapter, REG_MU_TX_CTL + 1,
- mu_tab_sel | i);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MU_STA_GID_VLD,
- cfgmu->given_gid_tab[i]);
- HALMAC_REG_WRITE_32(halmac_adapter,
- REG_MU_STA_USER_POS_INFO,
- cfgmu->given_user_pos[i * 2]);
- HALMAC_REG_WRITE_32(halmac_adapter,
- REG_MU_STA_USER_POS_INFO + 4,
- cfgmu->given_user_pos[i * 2 + 1]);
- }
- } else {
- /*config MU BFER*/
- if (!cfgmu->mu_tx_en) {
- HALMAC_REG_WRITE_8(halmac_adapter, REG_MU_TX_CTL,
- HALMAC_REG_READ_8(halmac_adapter,
- REG_MU_TX_CTL) &
- ~(BIT(7)));
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s disable mu tx <==========\n", __func__);
- return HALMAC_RET_SUCCESS;
- }
-
- /*Transform BB grouping bitmap[14:0] to MAC GID_valid table*/
- for (idx = 0; idx < 15; idx++) {
- if (idx < 5) {
- /*group_bitmap bit0~4, MU_STA0 with MUSTA1~5*/
- id0 = 0;
- id1 = (u8)(idx + 1);
- } else if (idx < 9) {
- /*group_bitmap bit5~8, MU_STA1 with MUSTA2~5*/
- id0 = 1;
- id1 = (u8)(idx - 3);
- } else if (idx < 12) {
- /*group_bitmap bit9~11, MU_STA2 with MUSTA3~5*/
- id0 = 2;
- id1 = (u8)(idx - 6);
- } else if (idx < 14) {
- /*group_bitmap bit12~13, MU_STA3 with MUSTA4~5*/
- id0 = 3;
- id1 = (u8)(idx - 8);
- } else {
- /*group_bitmap bit14, MU_STA4 with MUSTA5*/
- id0 = 4;
- id1 = (u8)(idx - 9);
- }
- if (cfgmu->grouping_bitmap & BIT(idx)) {
- /*Pair 1*/
- gid = (idx << 1) + 1;
- gid_valid[id0] |= (BIT(gid));
- gid_valid[id1] |= (BIT(gid));
- /*Pair 2*/
- gid += 1;
- gid_valid[id0] |= (BIT(gid));
- gid_valid[id1] |= (BIT(gid));
- } else {
- /*Pair 1*/
- gid = (idx << 1) + 1;
- gid_valid[id0] &= ~(BIT(gid));
- gid_valid[id1] &= ~(BIT(gid));
- /*Pair 2*/
- gid += 1;
- gid_valid[id0] &= ~(BIT(gid));
- gid_valid[id1] &= ~(BIT(gid));
- }
- }
-
- /*set MU STA GID valid TABLE*/
- mu_tab_sel =
- HALMAC_REG_READ_8(halmac_adapter, REG_MU_TX_CTL + 1) &
- ~(BIT(0) | BIT(1) | BIT(2));
- for (idx = 0; idx < 6; idx++) {
- HALMAC_REG_WRITE_8(halmac_adapter, REG_MU_TX_CTL + 1,
- idx | mu_tab_sel);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MU_STA_GID_VLD,
- gid_valid[idx]);
- }
-
- /*To validate the sounding successful MU STA and enable MU TX*/
- for (i = 0; i < 6; i++) {
- if (cfgmu->sounding_sts[i])
- mu_tab_valid |= BIT(i);
- }
- HALMAC_REG_WRITE_8(halmac_adapter, REG_MU_TX_CTL,
- mu_tab_valid | BIT(7));
- }
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_sounding_88xx() - configure general sounding
- * @halmac_adapter : the adapter of halmac
- * @role : driver's role, BFer or BFee
- * @datarate : set ndpa tx rate if driver is BFer, or set csi response rate
- * if driver is BFee
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_sounding_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_snd_role role,
- enum halmac_data_rate datarate)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_SOUNDING);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- switch (role) {
- case HAL_BFER:
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_TXBF_CTRL,
- HALMAC_REG_READ_32(halmac_adapter, REG_TXBF_CTRL) |
- BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER |
- BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_NDPA_RATE, datarate);
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_NDPA_OPT_CTRL,
- HALMAC_REG_READ_8(halmac_adapter, REG_NDPA_OPT_CTRL) &
- (~(BIT(0) | BIT(1))));
- /*service file length 2 bytes; fix non-STA1 csi start offset */
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SND_PTCL_CTRL + 1,
- 0x2 | BIT(7));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SND_PTCL_CTRL + 2, 0x2);
- break;
- case HAL_BFEE:
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SND_PTCL_CTRL, 0xDB);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SND_PTCL_CTRL + 3, 0x50);
- /*use ndpa rx rate to decide csi rate*/
- HALMAC_REG_WRITE_8(halmac_adapter, REG_BBPSF_CTRL + 3,
- HALMAC_OFDM54 | BIT(6));
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_RRSR,
- HALMAC_REG_READ_16(halmac_adapter, REG_RRSR) |
- BIT(datarate));
- /*RXFF do not accept BF Rpt Poll, avoid CSI crc error*/
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_RXFLTMAP1,
- HALMAC_REG_READ_8(halmac_adapter, REG_RXFLTMAP1) &
- (~(BIT(4))));
- /*FWFF do not accept BF Rpt Poll, avoid CSI crc error*/
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_RXFLTMAP4,
- HALMAC_REG_READ_8(halmac_adapter, REG_RXFLTMAP4) &
- (~(BIT(4))));
- break;
- default:
- pr_err("%s invalid role\n", __func__);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_del_sounding_88xx() - reset general sounding
- * @halmac_adapter : the adapter of halmac
- * @role : driver's role, BFer or BFee
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_del_sounding_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_snd_role role)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEL_SOUNDING);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- switch (role) {
- case HAL_BFER:
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TXBF_CTRL + 3, 0);
- break;
- case HAL_BFEE:
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SND_PTCL_CTRL, 0);
- break;
- default:
- pr_err("%s invalid role\n", __func__);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_su_bfee_entry_init_88xx() - config SU beamformee's registers
- * @halmac_adapter : the adapter of halmac
- * @userid : SU bfee userid = 0 or 1 to be added
- * @paid : partial AID of this bfee
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_su_bfee_entry_init_88xx(struct halmac_adapter *halmac_adapter, u8 userid,
- u16 paid)
-{
- u16 temp42C = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_SU_BFEE_ENTRY_INIT);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- switch (userid) {
- case 0:
- temp42C = HALMAC_REG_READ_16(halmac_adapter, REG_TXBF_CTRL) &
- ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |
- BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_TXBF_CTRL,
- temp42C | paid);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_ASSOCIATED_BFMEE_SEL,
- paid);
- break;
- case 1:
- temp42C =
- HALMAC_REG_READ_16(halmac_adapter, REG_TXBF_CTRL + 2) &
- ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |
- BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_TXBF_CTRL + 2,
- temp42C | paid);
- HALMAC_REG_WRITE_16(halmac_adapter,
- REG_ASSOCIATED_BFMEE_SEL + 2,
- paid | BIT(9));
- break;
- default:
- pr_err("%s invalid userid %d\n", __func__,
- userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_su_bfee_entry_init_88xx() - config SU beamformer's registers
- * @halmac_adapter : the adapter of halmac
- * @su_bfer_init : parameters to configure SU BFER entry
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_su_bfer_entry_init_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_su_bfer_init_para *su_bfer_init)
-{
- u16 mac_address_H;
- u32 mac_address_L;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_SU_BFER_ENTRY_INIT);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- /* mac_address_L = bfer_address.address_l_h.address_low; */
- /* mac_address_H = bfer_address.address_l_h.address_high; */
-
- mac_address_L = le32_to_cpu(
- su_bfer_init->bfer_address.address_l_h.le_address_low);
- mac_address_H = le16_to_cpu(
- su_bfer_init->bfer_address.address_l_h.le_address_high);
-
- switch (su_bfer_init->userid) {
- case 0:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_ASSOCIATED_BFMER0_INFO,
- mac_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter,
- REG_ASSOCIATED_BFMER0_INFO + 4,
- mac_address_H);
- HALMAC_REG_WRITE_16(halmac_adapter,
- REG_ASSOCIATED_BFMER0_INFO + 6,
- su_bfer_init->paid);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_TX_CSI_RPT_PARAM_BW20,
- su_bfer_init->csi_para);
- break;
- case 1:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_ASSOCIATED_BFMER1_INFO,
- mac_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter,
- REG_ASSOCIATED_BFMER1_INFO + 4,
- mac_address_H);
- HALMAC_REG_WRITE_16(halmac_adapter,
- REG_ASSOCIATED_BFMER1_INFO + 6,
- su_bfer_init->paid);
- HALMAC_REG_WRITE_16(halmac_adapter,
- REG_TX_CSI_RPT_PARAM_BW20 + 2,
- su_bfer_init->csi_para);
- break;
- default:
- pr_err("%s invalid userid %d\n", __func__,
- su_bfer_init->userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_mu_bfee_entry_init_88xx() - config MU beamformee's registers
- * @halmac_adapter : the adapter of halmac
- * @mu_bfee_init : parameters to configure MU BFEE entry
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_mu_bfee_entry_init_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_mu_bfee_init_para *mu_bfee_init)
-{
- u16 temp168X = 0, temp14C0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_MU_BFEE_ENTRY_INIT);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- temp168X |= mu_bfee_init->paid | BIT(9);
- HALMAC_REG_WRITE_16(halmac_adapter, (0x1680 + mu_bfee_init->userid * 2),
- temp168X);
-
- temp14C0 = HALMAC_REG_READ_16(halmac_adapter, REG_MU_TX_CTL) &
- ~(BIT(8) | BIT(9) | BIT(10));
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MU_TX_CTL,
- temp14C0 | ((mu_bfee_init->userid - 2) << 8));
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MU_STA_GID_VLD, 0);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MU_STA_USER_POS_INFO,
- mu_bfee_init->user_position_l);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_MU_STA_USER_POS_INFO + 4,
- mu_bfee_init->user_position_h);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_mu_bfer_entry_init_88xx() - config MU beamformer's registers
- * @halmac_adapter : the adapter of halmac
- * @mu_bfer_init : parameters to configure MU BFER entry
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_mu_bfer_entry_init_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_mu_bfer_init_para *mu_bfer_init)
-{
- u16 temp1680 = 0;
- u16 mac_address_H;
- u32 mac_address_L;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_MU_BFER_ENTRY_INIT);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- mac_address_L =
- le32_to_cpu(mu_bfer_init->bfer_address.address_l_h.le_address_low);
- mac_address_H =
- le16_to_cpu(mu_bfer_init->bfer_address.address_l_h.le_address_high);
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_ASSOCIATED_BFMER0_INFO,
- mac_address_L);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4,
- mac_address_H);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 6,
- mu_bfer_init->paid);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_TX_CSI_RPT_PARAM_BW20,
- mu_bfer_init->csi_para);
-
- temp1680 = HALMAC_REG_READ_16(halmac_adapter, 0x1680) & 0xC000;
- temp1680 |= mu_bfer_init->my_aid | (mu_bfer_init->csi_length_sel << 12);
- HALMAC_REG_WRITE_16(halmac_adapter, 0x1680, temp1680);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_su_bfee_entry_del_88xx() - reset SU beamformee's registers
- * @halmac_adapter : the adapter of halmac
- * @userid : the SU BFee userid to be deleted
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_su_bfee_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_SU_BFEE_ENTRY_DEL);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- switch (userid) {
- case 0:
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_TXBF_CTRL,
- HALMAC_REG_READ_16(halmac_adapter, REG_TXBF_CTRL) &
- ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |
- BIT_R_TXBF0_40M | BIT_R_TXBF0_80M));
- HALMAC_REG_WRITE_16(halmac_adapter, REG_ASSOCIATED_BFMEE_SEL,
- 0);
- break;
- case 1:
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_TXBF_CTRL + 2,
- HALMAC_REG_READ_16(halmac_adapter, REG_TXBF_CTRL + 2) &
- ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |
- BIT_R_TXBF0_40M | BIT_R_TXBF0_80M));
- HALMAC_REG_WRITE_16(halmac_adapter,
- REG_ASSOCIATED_BFMEE_SEL + 2, 0);
- break;
- default:
- pr_err("%s invalid userid %d\n", __func__,
- userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_su_bfee_entry_del_88xx() - reset SU beamformer's registers
- * @halmac_adapter : the adapter of halmac
- * @userid : the SU BFer userid to be deleted
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_su_bfer_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_SU_BFER_ENTRY_DEL);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- switch (userid) {
- case 0:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_ASSOCIATED_BFMER0_INFO,
- 0);
- HALMAC_REG_WRITE_32(halmac_adapter,
- REG_ASSOCIATED_BFMER0_INFO + 4, 0);
- break;
- case 1:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_ASSOCIATED_BFMER1_INFO,
- 0);
- HALMAC_REG_WRITE_32(halmac_adapter,
- REG_ASSOCIATED_BFMER1_INFO + 4, 0);
- break;
- default:
- pr_err("%s invalid userid %d\n", __func__,
- userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_mu_bfee_entry_del_88xx() - reset MU beamformee's registers
- * @halmac_adapter : the adapter of halmac
- * @userid : the MU STA userid to be deleted
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_mu_bfee_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_MU_BFEE_ENTRY_DEL);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_16(halmac_adapter, 0x1680 + userid * 2, 0);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_MU_TX_CTL,
- HALMAC_REG_READ_8(halmac_adapter, REG_MU_TX_CTL) &
- ~(BIT(userid - 2)));
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_mu_bfer_entry_del_88xx() -reset MU beamformer's registers
- * @halmac_adapter : the adapter of halmac
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_mu_bfer_entry_del_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_MU_BFER_ENTRY_DEL);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_ASSOCIATED_BFMER0_INFO, 0);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
- HALMAC_REG_WRITE_16(halmac_adapter, 0x1680, 0);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_MU_TX_CTL, 0);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_add_ch_info_88xx() -add channel information
- * @halmac_adapter : the adapter of halmac
- * @ch_info : channel information
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_add_ch_info_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ch_info *ch_info)
-{
- void *driver_adapter = NULL;
- struct halmac_cs_info *ch_sw_info;
- enum halmac_scan_cmd_construct_state state_scan;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- ch_sw_info = &halmac_adapter->ch_sw_info;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]%s ==========>\n", __func__);
-
- if (halmac_adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) {
- pr_err("[ERR]%s: gen_info is not send to FW!!!!\n", __func__);
- return HALMAC_RET_GEN_INFO_NOT_SENT;
- }
-
- state_scan = halmac_query_scan_curr_state_88xx(halmac_adapter);
- if (state_scan != HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED &&
- state_scan != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_WARNING,
- "[WARN]Scan machine fail(add ch info)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (!ch_sw_info->ch_info_buf) {
- ch_sw_info->ch_info_buf =
- kzalloc(HALMAC_EXTRA_INFO_BUFF_SIZE_88XX, GFP_KERNEL);
- if (!ch_sw_info->ch_info_buf)
- return HALMAC_RET_NULL_POINTER;
- ch_sw_info->ch_info_buf_w = ch_sw_info->ch_info_buf;
- ch_sw_info->buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
- ch_sw_info->avai_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
- ch_sw_info->total_size = 0;
- ch_sw_info->extra_info_en = 0;
- ch_sw_info->ch_num = 0;
- }
-
- if (ch_sw_info->extra_info_en == 1) {
- pr_err("[ERR]%s: construct sequence wrong!!\n", __func__);
- return HALMAC_RET_CH_SW_SEQ_WRONG;
- }
-
- if (ch_sw_info->avai_buf_size < 4) {
- pr_err("[ERR]%s: no available buffer!!\n", __func__);
- return HALMAC_RET_CH_SW_NO_BUF;
- }
-
- if (halmac_transition_scan_state_88xx(
- halmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- CHANNEL_INFO_SET_CHANNEL(ch_sw_info->ch_info_buf_w, ch_info->channel);
- CHANNEL_INFO_SET_PRI_CH_IDX(ch_sw_info->ch_info_buf_w,
- ch_info->pri_ch_idx);
- CHANNEL_INFO_SET_BANDWIDTH(ch_sw_info->ch_info_buf_w, ch_info->bw);
- CHANNEL_INFO_SET_TIMEOUT(ch_sw_info->ch_info_buf_w, ch_info->timeout);
- CHANNEL_INFO_SET_ACTION_ID(ch_sw_info->ch_info_buf_w,
- ch_info->action_id);
- CHANNEL_INFO_SET_CH_EXTRA_INFO(ch_sw_info->ch_info_buf_w,
- ch_info->extra_info);
-
- ch_sw_info->avai_buf_size = ch_sw_info->avai_buf_size - 4;
- ch_sw_info->total_size = ch_sw_info->total_size + 4;
- ch_sw_info->ch_num++;
- ch_sw_info->extra_info_en = ch_info->extra_info;
- ch_sw_info->ch_info_buf_w = ch_sw_info->ch_info_buf_w + 4;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_add_extra_ch_info_88xx() -add extra channel information
- * @halmac_adapter : the adapter of halmac
- * @ch_extra_info : extra channel information
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_add_extra_ch_info_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ch_extra_info *ch_extra_info)
-{
- void *driver_adapter = NULL;
- struct halmac_cs_info *ch_sw_info;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_ADD_EXTRA_CH_INFO);
-
- driver_adapter = halmac_adapter->driver_adapter;
- ch_sw_info = &halmac_adapter->ch_sw_info;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (!ch_sw_info->ch_info_buf) {
- pr_err("%s: NULL==ch_sw_info->ch_info_buf!!\n", __func__);
- return HALMAC_RET_CH_SW_SEQ_WRONG;
- }
-
- if (ch_sw_info->extra_info_en == 0) {
- pr_err("%s: construct sequence wrong!!\n", __func__);
- return HALMAC_RET_CH_SW_SEQ_WRONG;
- }
-
- if (ch_sw_info->avai_buf_size <
- (u32)(ch_extra_info->extra_info_size + 2)) {
- /* +2: ch_extra_info_id, ch_extra_info, ch_extra_info_size
- * are totally 2Byte
- */
- pr_err("%s: no available buffer!!\n", __func__);
- return HALMAC_RET_CH_SW_NO_BUF;
- }
-
- if (halmac_query_scan_curr_state_88xx(halmac_adapter) !=
- HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Scan machine fail(add extra ch info)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (halmac_transition_scan_state_88xx(
- halmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(ch_sw_info->ch_info_buf_w,
- ch_extra_info->extra_action_id);
- CH_EXTRA_INFO_SET_CH_EXTRA_INFO(ch_sw_info->ch_info_buf_w,
- ch_extra_info->extra_info);
- CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(ch_sw_info->ch_info_buf_w,
- ch_extra_info->extra_info_size);
- memcpy(ch_sw_info->ch_info_buf_w + 2, ch_extra_info->extra_info_data,
- ch_extra_info->extra_info_size);
-
- ch_sw_info->avai_buf_size = ch_sw_info->avai_buf_size -
- (2 + ch_extra_info->extra_info_size);
- ch_sw_info->total_size =
- ch_sw_info->total_size + (2 + ch_extra_info->extra_info_size);
- ch_sw_info->extra_info_en = ch_extra_info->extra_info;
- ch_sw_info->ch_info_buf_w = ch_sw_info->ch_info_buf_w +
- (2 + ch_extra_info->extra_info_size);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_ctrl_ch_switch_88xx() -send channel switch cmd
- * @halmac_adapter : the adapter of halmac
- * @cs_option : channel switch config
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_ctrl_ch_switch_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ch_switch_option *cs_option)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- enum halmac_scan_cmd_construct_state state_scan;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.scan_state_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- if (halmac_adapter->fw_version.h2c_version < 4)
- return HALMAC_RET_FW_NO_SUPPORT;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CTRL_CH_SWITCH);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s cs_option->switch_en = %d==========>\n", __func__,
- cs_option->switch_en);
-
- if (!cs_option->switch_en)
- *process_status = HALMAC_CMD_PROCESS_IDLE;
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING ||
- *process_status == HALMAC_CMD_PROCESS_RCVD) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait event(ctrl ch switch)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- state_scan = halmac_query_scan_curr_state_88xx(halmac_adapter);
- if (cs_option->switch_en) {
- if (state_scan != HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C,
- DBG_DMESG,
- "%s(on) invalid in state %x\n",
- __func__, state_scan);
- return HALMAC_RET_ERROR_STATE;
- }
- } else {
- if (state_scan != HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) {
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s(off) invalid in state %x\n", __func__,
- state_scan);
- return HALMAC_RET_ERROR_STATE;
- }
- }
-
- status = halmac_func_ctrl_ch_switch_88xx(halmac_adapter, cs_option);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_ctrl_ch_switch FAIL = %x!!\n", status);
- return status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_clear_ch_info_88xx() -clear channel information
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_clear_ch_info_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CLEAR_CH_INFO);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (halmac_query_scan_curr_state_88xx(halmac_adapter) ==
- HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Scan machine fail(clear ch info)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (halmac_transition_scan_state_88xx(
- halmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- kfree(halmac_adapter->ch_sw_info.ch_info_buf);
- halmac_adapter->ch_sw_info.ch_info_buf = NULL;
- halmac_adapter->ch_sw_info.ch_info_buf_w = NULL;
- halmac_adapter->ch_sw_info.extra_info_en = 0;
- halmac_adapter->ch_sw_info.buf_size = 0;
- halmac_adapter->ch_sw_info.avai_buf_size = 0;
- halmac_adapter->ch_sw_info.total_size = 0;
- halmac_adapter->ch_sw_info.ch_num = 0;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_p2pps_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_p2pps *p2p_ps)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- if (halmac_adapter->fw_version.h2c_version < 6)
- return HALMAC_RET_FW_NO_SUPPORT;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- status = halmac_func_p2pps_88xx(halmac_adapter, p2p_ps);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("[ERR]halmac_p2pps FAIL = %x!!\n", status);
- return status;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_func_p2pps_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_p2pps *p2p_ps)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = halmac_adapter->driver_adapter;
- struct halmac_api *halmac_api;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]halmac_p2pps !!\n");
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- P2PPS_SET_OFFLOAD_EN(h2c_buff, p2p_ps->offload_en);
- P2PPS_SET_ROLE(h2c_buff, p2p_ps->role);
- P2PPS_SET_CTWINDOW_EN(h2c_buff, p2p_ps->ctwindow_en);
- P2PPS_SET_NOA_EN(h2c_buff, p2p_ps->noa_en);
- P2PPS_SET_NOA_SEL(h2c_buff, p2p_ps->noa_sel);
- P2PPS_SET_ALLSTASLEEP(h2c_buff, p2p_ps->all_sta_sleep);
- P2PPS_SET_DISCOVERY(h2c_buff, p2p_ps->discovery);
- P2PPS_SET_P2P_PORT_ID(h2c_buff, p2p_ps->p2p_port_id);
- P2PPS_SET_P2P_GROUP(h2c_buff, p2p_ps->p2p_group);
- P2PPS_SET_P2P_MACID(h2c_buff, p2p_ps->p2p_macid);
-
- P2PPS_SET_CTWINDOW_LENGTH(h2c_buff, p2p_ps->ctwindow_length);
-
- P2PPS_SET_NOA_DURATION_PARA(h2c_buff, p2p_ps->noa_duration_para);
- P2PPS_SET_NOA_INTERVAL_PARA(h2c_buff, p2p_ps->noa_interval_para);
- P2PPS_SET_NOA_START_TIME_PARA(h2c_buff, p2p_ps->noa_start_time_para);
- P2PPS_SET_NOA_COUNT_PARA(h2c_buff, p2p_ps->noa_count_para);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_P2PPS;
- h2c_header_info.content_size = 24;
- h2c_header_info.ack = false;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, false);
-
- if (status != HALMAC_RET_SUCCESS)
- pr_err("[ERR]halmac_send_h2c_p2pps_88xx Fail = %x!!\n", status);
-
- return status;
-}
-
-/**
- * halmac_send_general_info_88xx() -send general information to FW
- * @halmac_adapter : the adapter of halmac
- * @general_info : general information
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_send_general_info_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_general_info *general_info)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- if (halmac_adapter->fw_version.h2c_version < 4)
- return HALMAC_RET_FW_NO_SUPPORT;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_SEND_GENERAL_INFO);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (halmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) {
- pr_err("%s Fail due to DLFW NONE!!\n", __func__);
- return HALMAC_RET_DLFW_FAIL;
- }
-
- status = halmac_func_send_general_info_88xx(halmac_adapter,
- general_info);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_general_info error = %x\n", status);
- return status;
- }
-
- if (halmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE)
- halmac_adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;
-
- halmac_adapter->gen_info_valid = true;
- memcpy(&halmac_adapter->general_info, general_info,
- sizeof(struct halmac_general_info));
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_start_iqk_88xx() -trigger FW IQK
- * @halmac_adapter : the adapter of halmac
- * @iqk_para : IQK parameter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_start_iqk_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_iqk_para_ *iqk_para)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_num = 0;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.iqk_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_START_IQK);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait event(iqk)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- *process_status = HALMAC_CMD_PROCESS_SENDING;
-
- IQK_SET_CLEAR(h2c_buff, iqk_para->clear);
- IQK_SET_SEGMENT_IQK(h2c_buff, iqk_para->segment_iqk);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_IQK;
- h2c_header_info.content_size = 1;
- h2c_header_info.ack = true;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_num);
-
- halmac_adapter->halmac_state.iqk_set.seq_num = h2c_seq_num;
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_ctrl_pwr_tracking_88xx() -trigger FW power tracking
- * @halmac_adapter : the adapter of halmac
- * @pwr_tracking_opt : power tracking option
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_ctrl_pwr_tracking_88xx(
- struct halmac_adapter *halmac_adapter,
- struct halmac_pwr_tracking_option *pwr_tracking_opt)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.power_tracking_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CTRL_PWR_TRACKING);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "halmac_start_iqk_88xx ==========>\n");
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait event(pwr tracking)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- *process_status = HALMAC_CMD_PROCESS_SENDING;
-
- POWER_TRACKING_SET_TYPE(h2c_buff, pwr_tracking_opt->type);
- POWER_TRACKING_SET_BBSWING_INDEX(h2c_buff,
- pwr_tracking_opt->bbswing_index);
- POWER_TRACKING_SET_ENABLE_A(
- h2c_buff,
- pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].enable);
- POWER_TRACKING_SET_TX_PWR_INDEX_A(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A]
- .tx_pwr_index);
- POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A]
- .pwr_tracking_offset_value);
- POWER_TRACKING_SET_TSSI_VALUE_A(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A]
- .tssi_value);
- POWER_TRACKING_SET_ENABLE_B(
- h2c_buff,
- pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].enable);
- POWER_TRACKING_SET_TX_PWR_INDEX_B(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B]
- .tx_pwr_index);
- POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B]
- .pwr_tracking_offset_value);
- POWER_TRACKING_SET_TSSI_VALUE_B(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B]
- .tssi_value);
- POWER_TRACKING_SET_ENABLE_C(
- h2c_buff,
- pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].enable);
- POWER_TRACKING_SET_TX_PWR_INDEX_C(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C]
- .tx_pwr_index);
- POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C]
- .pwr_tracking_offset_value);
- POWER_TRACKING_SET_TSSI_VALUE_C(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C]
- .tssi_value);
- POWER_TRACKING_SET_ENABLE_D(
- h2c_buff,
- pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].enable);
- POWER_TRACKING_SET_TX_PWR_INDEX_D(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D]
- .tx_pwr_index);
- POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D]
- .pwr_tracking_offset_value);
- POWER_TRACKING_SET_TSSI_VALUE_D(
- h2c_buff, pwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D]
- .tssi_value);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_POWER_TRACKING;
- h2c_header_info.content_size = 20;
- h2c_header_info.ack = true;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
-
- halmac_adapter->halmac_state.power_tracking_set.seq_num = h2c_seq_mum;
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "halmac_start_iqk_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_query_status_88xx() -query the offload feature status
- * @halmac_adapter : the adapter of halmac
- * @feature_id : feature_id
- * @process_status : feature_status
- * @data : data buffer
- * @size : data size
- *
- * Note :
- * If user wants to know the data size, use can allocate zero
- * size buffer first. If this size less than the data size, halmac
- * will return HALMAC_RET_BUFFER_TOO_SMALL. User need to
- * re-allocate data buffer with correct data size.
- *
- * Author : Ivan Lin/KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_query_status_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_feature_id feature_id,
- enum halmac_cmd_process_status *process_status,
- u8 *data, u32 *size)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_QUERY_STATE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- if (!process_status) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "null pointer!!\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- switch (feature_id) {
- case HALMAC_FEATURE_CFG_PARA:
- status = halmac_query_cfg_para_status_88xx(
- halmac_adapter, process_status, data, size);
- break;
- case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
- status = halmac_query_dump_physical_efuse_status_88xx(
- halmac_adapter, process_status, data, size);
- break;
- case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
- status = halmac_query_dump_logical_efuse_status_88xx(
- halmac_adapter, process_status, data, size);
- break;
- case HALMAC_FEATURE_CHANNEL_SWITCH:
- status = halmac_query_channel_switch_status_88xx(
- halmac_adapter, process_status, data, size);
- break;
- case HALMAC_FEATURE_UPDATE_PACKET:
- status = halmac_query_update_packet_status_88xx(
- halmac_adapter, process_status, data, size);
- break;
- case HALMAC_FEATURE_IQK:
- status = halmac_query_iqk_status_88xx(
- halmac_adapter, process_status, data, size);
- break;
- case HALMAC_FEATURE_POWER_TRACKING:
- status = halmac_query_power_tracking_status_88xx(
- halmac_adapter, process_status, data, size);
- break;
- case HALMAC_FEATURE_PSD:
- status = halmac_query_psd_status_88xx(
- halmac_adapter, process_status, data, size);
- break;
- default:
- pr_err("%s invalid feature id %d\n", __func__,
- feature_id);
- return HALMAC_RET_INVALID_FEATURE_ID;
- }
-
- return status;
-}
-
-/**
- * halmac_reset_feature_88xx() -reset async api cmd status
- * @halmac_adapter : the adapter of halmac
- * @feature_id : feature_id
- * Author : Ivan Lin/KaiYuan Chang
- * Return : enum halmac_ret_status.
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reset_feature_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_feature_id feature_id)
-{
- void *driver_adapter = NULL;
- struct halmac_state *state = &halmac_adapter->halmac_state;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_RESET_FEATURE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- switch (feature_id) {
- case HALMAC_FEATURE_CFG_PARA:
- state->cfg_para_state_set.process_status =
- HALMAC_CMD_PROCESS_IDLE;
- state->cfg_para_state_set.cfg_para_cmd_construct_state =
- HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE;
- break;
- case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
- case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
- state->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->efuse_state_set.efuse_cmd_construct_state =
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE;
- break;
- case HALMAC_FEATURE_CHANNEL_SWITCH:
- state->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->scan_state_set.scan_cmd_construct_state =
- HALMAC_SCAN_CMD_CONSTRUCT_IDLE;
- break;
- case HALMAC_FEATURE_UPDATE_PACKET:
- state->update_packet_set.process_status =
- HALMAC_CMD_PROCESS_IDLE;
- break;
- case HALMAC_FEATURE_ALL:
- state->cfg_para_state_set.process_status =
- HALMAC_CMD_PROCESS_IDLE;
- state->cfg_para_state_set.cfg_para_cmd_construct_state =
- HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE;
- state->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->efuse_state_set.efuse_cmd_construct_state =
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE;
- state->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->scan_state_set.scan_cmd_construct_state =
- HALMAC_SCAN_CMD_CONSTRUCT_IDLE;
- state->update_packet_set.process_status =
- HALMAC_CMD_PROCESS_IDLE;
- break;
- default:
- pr_err("%s invalid feature id %d\n", __func__,
- feature_id);
- return HALMAC_RET_INVALID_FEATURE_ID;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_check_fw_status_88xx() -check fw status
- * @halmac_adapter : the adapter of halmac
- * @fw_status : fw status
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_check_fw_status_88xx(struct halmac_adapter *halmac_adapter,
- bool *fw_status)
-{
- u32 value32 = 0, value32_backup = 0, i = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CHECK_FW_STATUS);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- value32 = PLATFORM_REG_READ_32(driver_adapter, REG_FW_DBG6);
-
- if (value32 != 0) {
- pr_err("halmac_check_fw_status REG_FW_DBG6 !=0\n");
- *fw_status = false;
- return status;
- }
-
- value32_backup = PLATFORM_REG_READ_32(driver_adapter, REG_FW_DBG7);
-
- for (i = 0; i <= 10; i++) {
- value32 = PLATFORM_REG_READ_32(driver_adapter, REG_FW_DBG7);
- if (value32_backup != value32)
- break;
-
- if (i == 10) {
- pr_err("halmac_check_fw_status Polling FW PC fail\n");
- *fw_status = false;
- return status;
- }
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_dump_fw_dmem_88xx(struct halmac_adapter *halmac_adapter, u8 *dmem,
- u32 *size)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DUMP_FW_DMEM);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return status;
-}
-
-/**
- * halmac_cfg_max_dl_size_88xx() - config max download FW size
- * @halmac_adapter : the adapter of halmac
- * @size : max download fw size
- *
- * Halmac uses this setting to set max packet size for
- * download FW.
- * If user has not called this API, halmac use default
- * setting for download FW
- * Note1 : size need multiple of 2
- * Note2 : max size is 31K
- *
- * Author : Ivan Lin/KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_max_dl_size_88xx(struct halmac_adapter *halmac_adapter, u32 size)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_MAX_DL_SIZE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_FW, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX) {
- pr_err("size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX!\n");
- return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
- }
-
- if ((size & (2 - 1)) != 0) {
- pr_err("size is not power of 2!\n");
- return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
- }
-
- halmac_adapter->max_download_size = size;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_FW, DBG_DMESG,
- "Cfg max size is : %X\n", size);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_FW, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_psd_88xx() - trigger fw psd
- * @halmac_adapter : the adapter of halmac
- * @start_psd : start PSD
- * @end_psd : end PSD
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_psd_88xx(struct halmac_adapter *halmac_adapter,
- u16 start_psd, u16 end_psd)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.psd_set.process_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- if (halmac_fw_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PSD);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (*process_status == HALMAC_CMD_PROCESS_SENDING) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Wait event(psd)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- kfree(halmac_adapter->halmac_state.psd_set.data);
- halmac_adapter->halmac_state.psd_set.data = (u8 *)NULL;
-
- halmac_adapter->halmac_state.psd_set.data_size = 0;
- halmac_adapter->halmac_state.psd_set.segment_size = 0;
-
- *process_status = HALMAC_CMD_PROCESS_SENDING;
-
- PSD_SET_START_PSD(h2c_buff, start_psd);
- PSD_SET_END_PSD(h2c_buff, end_psd);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_PSD;
- h2c_header_info.content_size = 4;
- h2c_header_info.ack = true;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_la_mode_88xx() - config la mode
- * @halmac_adapter : the adapter of halmac
- * @la_mode :
- * disable : no TXFF space reserved for LA debug
- * partial : partial TXFF space is reserved for LA debug
- * full : all TXFF space is reserved for LA debug
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_la_mode_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_la_mode la_mode)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_LA_MODE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>la_mode = %d\n", __func__,
- la_mode);
-
- halmac_adapter->txff_allocation.la_mode = la_mode;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_rx_fifo_expanding_mode_88xx() - rx fifo expanding
- * @halmac_adapter : the adapter of halmac
- * @la_mode :
- * disable : normal mode
- * 1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block
- * 2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block
- * 3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block
- * Author : Soar
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_cfg_rx_fifo_expanding_mode_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>rx_fifo_expanding_mode = %d\n", __func__,
- rx_fifo_expanding_mode);
-
- halmac_adapter->txff_allocation.rx_fifo_expanding_mode =
- rx_fifo_expanding_mode;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_config_security_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_security_setting *sec_setting)
-{
- struct halmac_api *halmac_api;
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_CR,
- (u16)(HALMAC_REG_READ_16(halmac_adapter, REG_CR) |
- BIT_MAC_SEC_EN));
-
- if (sec_setting->tx_encryption == 1)
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_SECCFG,
- HALMAC_REG_READ_8(halmac_adapter, REG_SECCFG) | BIT(2));
- else
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_SECCFG,
- HALMAC_REG_READ_8(halmac_adapter, REG_SECCFG) &
- ~(BIT(2)));
-
- if (sec_setting->rx_decryption == 1)
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_SECCFG,
- HALMAC_REG_READ_8(halmac_adapter, REG_SECCFG) | BIT(3));
- else
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_SECCFG,
- HALMAC_REG_READ_8(halmac_adapter, REG_SECCFG) &
- ~(BIT(3)));
-
- if (sec_setting->bip_enable == 1) {
- if (halmac_adapter->chip_id == HALMAC_CHIP_ID_8822B)
- return HALMAC_RET_BIP_NO_SUPPORT;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-u8 halmac_get_used_cam_entry_num_88xx(struct halmac_adapter *halmac_adapter,
- enum hal_security_type sec_type)
-{
- u8 entry_num;
- void *driver_adapter = NULL;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- switch (sec_type) {
- case HAL_SECURITY_TYPE_WEP40:
- case HAL_SECURITY_TYPE_WEP104:
- case HAL_SECURITY_TYPE_TKIP:
- case HAL_SECURITY_TYPE_AES128:
- case HAL_SECURITY_TYPE_GCMP128:
- case HAL_SECURITY_TYPE_GCMSMS4:
- case HAL_SECURITY_TYPE_BIP:
- entry_num = 1;
- break;
- case HAL_SECURITY_TYPE_WAPI:
- case HAL_SECURITY_TYPE_AES256:
- case HAL_SECURITY_TYPE_GCMP256:
- entry_num = 2;
- break;
- default:
- entry_num = 0;
- break;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return entry_num;
-}
-
-enum halmac_ret_status
-halmac_write_cam_88xx(struct halmac_adapter *halmac_adapter, u32 entry_index,
- struct halmac_cam_entry_info *cam_entry_info)
-{
- u32 i;
- u32 command = 0x80010000;
- struct halmac_api *halmac_api;
- void *driver_adapter = NULL;
- struct halmac_cam_entry_format *cam_entry_format = NULL;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "[TRACE]%s ==========>\n", __func__);
-
- if (entry_index >= halmac_adapter->hw_config_info.cam_entry_num)
- return HALMAC_RET_ENTRY_INDEX_ERROR;
-
- if (cam_entry_info->key_id > 3)
- return HALMAC_RET_FAIL;
-
- cam_entry_format = kzalloc(sizeof(*cam_entry_format), GFP_KERNEL);
- if (!cam_entry_format)
- return HALMAC_RET_NULL_POINTER;
-
- cam_entry_format->key_id = cam_entry_info->key_id;
- cam_entry_format->valid = cam_entry_info->valid;
- memcpy(cam_entry_format->mac_address, cam_entry_info->mac_address, 6);
- memcpy(cam_entry_format->key, cam_entry_info->key, 16);
-
- switch (cam_entry_info->security_type) {
- case HAL_SECURITY_TYPE_NONE:
- cam_entry_format->type = 0;
- break;
- case HAL_SECURITY_TYPE_WEP40:
- cam_entry_format->type = 1;
- break;
- case HAL_SECURITY_TYPE_WEP104:
- cam_entry_format->type = 5;
- break;
- case HAL_SECURITY_TYPE_TKIP:
- cam_entry_format->type = 2;
- break;
- case HAL_SECURITY_TYPE_AES128:
- cam_entry_format->type = 4;
- break;
- case HAL_SECURITY_TYPE_WAPI:
- cam_entry_format->type = 6;
- break;
- case HAL_SECURITY_TYPE_AES256:
- cam_entry_format->type = 4;
- cam_entry_format->ext_sectype = 1;
- break;
- case HAL_SECURITY_TYPE_GCMP128:
- cam_entry_format->type = 7;
- break;
- case HAL_SECURITY_TYPE_GCMP256:
- case HAL_SECURITY_TYPE_GCMSMS4:
- cam_entry_format->type = 7;
- cam_entry_format->ext_sectype = 1;
- break;
- case HAL_SECURITY_TYPE_BIP:
- cam_entry_format->type = cam_entry_info->unicast == 1 ? 4 : 0;
- cam_entry_format->mgnt = 1;
- cam_entry_format->grp = cam_entry_info->unicast == 1 ? 0 : 1;
- break;
- default:
- kfree(cam_entry_format);
- return HALMAC_RET_FAIL;
- }
-
- for (i = 0; i < 8; i++) {
- HALMAC_REG_WRITE_32(halmac_adapter, REG_CAMWRITE,
- *((u32 *)cam_entry_format + i));
- HALMAC_REG_WRITE_32(halmac_adapter, REG_CAMCMD,
- command | ((entry_index << 3) + i));
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "[TRACE]1 - CAM entry format : %X\n",
- *((u32 *)cam_entry_format + i));
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "[TRACE]1 - REG_CAMCMD : %X\n",
- command | ((entry_index << 3) + i));
- }
-
- if (cam_entry_info->security_type == HAL_SECURITY_TYPE_WAPI ||
- cam_entry_info->security_type == HAL_SECURITY_TYPE_AES256 ||
- cam_entry_info->security_type == HAL_SECURITY_TYPE_GCMP256 ||
- cam_entry_info->security_type == HAL_SECURITY_TYPE_GCMSMS4) {
- cam_entry_format->mic = 1;
- memcpy(cam_entry_format->key, cam_entry_info->key_ext, 16);
-
- for (i = 0; i < 8; i++) {
- HALMAC_REG_WRITE_32(halmac_adapter, REG_CAMWRITE,
- *((u32 *)cam_entry_format + i));
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_CAMCMD,
- command | (((entry_index + 1) << 3) + i));
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON,
- DBG_DMESG,
- "[TRACE]2 - CAM entry format : %X\n",
- *((u32 *)cam_entry_format + i));
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "[TRACE]2 - REG_CAMCMD : %X\n",
- command | (((entry_index + 1) << 3) + i));
- }
- }
-
- kfree(cam_entry_format);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "[TRACE]%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_read_cam_entry_88xx(struct halmac_adapter *halmac_adapter,
- u32 entry_index,
- struct halmac_cam_entry_format *content)
-{
- u32 i;
- u32 command = 0x80000000;
- struct halmac_api *halmac_api;
- void *driver_adapter = NULL;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (entry_index >= halmac_adapter->hw_config_info.cam_entry_num)
- return HALMAC_RET_ENTRY_INDEX_ERROR;
-
- for (i = 0; i < 8; i++) {
- HALMAC_REG_WRITE_32(halmac_adapter, REG_CAMCMD,
- command | ((entry_index << 3) + i));
- *((u32 *)content + i) =
- HALMAC_REG_READ_32(halmac_adapter, REG_CAMREAD);
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_clear_cam_entry_88xx(struct halmac_adapter *halmac_adapter,
- u32 entry_index)
-{
- u32 i;
- u32 command = 0x80010000;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- struct halmac_cam_entry_format *cam_entry_format;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]halmac_clear_security_cam_88xx ==========>\n");
-
- if (entry_index >= halmac_adapter->hw_config_info.cam_entry_num)
- return HALMAC_RET_ENTRY_INDEX_ERROR;
-
- cam_entry_format = kzalloc(sizeof(*cam_entry_format), GFP_KERNEL);
- if (!cam_entry_format)
- return HALMAC_RET_NULL_POINTER;
-
- for (i = 0; i < 8; i++) {
- HALMAC_REG_WRITE_32(halmac_adapter, REG_CAMWRITE,
- *((u32 *)cam_entry_format + i));
- HALMAC_REG_WRITE_32(halmac_adapter, REG_CAMCMD,
- command | ((entry_index << 3) + i));
- }
-
- kfree(cam_entry_format);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]halmac_clear_security_cam_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_hw_value_88xx() -get hw config value
- * @halmac_adapter : the adapter of halmac
- * @hw_id : hw id for driver to query
- * @pvalue : hw value, reference table to get data type
- * Author : KaiYuan Chang / Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_get_hw_value_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_hw_id hw_id, void *pvalue)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_GET_HW_VALUE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (!pvalue) {
- pr_err("%s (!pvalue)==========>\n", __func__);
- return HALMAC_RET_NULL_POINTER;
- }
-
- switch (hw_id) {
- case HALMAC_HW_RQPN_MAPPING:
- ((struct halmac_rqpn_map *)pvalue)->dma_map_vo =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
- ((struct halmac_rqpn_map *)pvalue)->dma_map_vi =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
- ((struct halmac_rqpn_map *)pvalue)->dma_map_be =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
- ((struct halmac_rqpn_map *)pvalue)->dma_map_bk =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
- ((struct halmac_rqpn_map *)pvalue)->dma_map_mg =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
- ((struct halmac_rqpn_map *)pvalue)->dma_map_hi =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
- break;
- case HALMAC_HW_EFUSE_SIZE:
- *(u32 *)pvalue = halmac_adapter->hw_config_info.efuse_size;
- break;
- case HALMAC_HW_EEPROM_SIZE:
- *(u32 *)pvalue = halmac_adapter->hw_config_info.eeprom_size;
- break;
- case HALMAC_HW_BT_BANK_EFUSE_SIZE:
- *(u32 *)pvalue = halmac_adapter->hw_config_info.bt_efuse_size;
- break;
- case HALMAC_HW_BT_BANK1_EFUSE_SIZE:
- case HALMAC_HW_BT_BANK2_EFUSE_SIZE:
- *(u32 *)pvalue = 0;
- break;
- case HALMAC_HW_TXFIFO_SIZE:
- *(u32 *)pvalue = halmac_adapter->hw_config_info.tx_fifo_size;
- break;
- case HALMAC_HW_RSVD_PG_BNDY:
- *(u16 *)pvalue =
- halmac_adapter->txff_allocation.rsvd_drv_pg_bndy;
- break;
- case HALMAC_HW_CAM_ENTRY_NUM:
- *(u8 *)pvalue = halmac_adapter->hw_config_info.cam_entry_num;
- break;
- case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE: /*Remove later*/
- status = halmac_dump_logical_efuse_map_88xx(halmac_adapter,
- HALMAC_EFUSE_R_DRV);
- if (status != HALMAC_RET_SUCCESS)
- return status;
- *(u32 *)pvalue = halmac_adapter->hw_config_info.efuse_size -
- HALMAC_PROTECTED_EFUSE_SIZE_88XX -
- halmac_adapter->efuse_end;
- break;
- case HALMAC_HW_IC_VERSION:
- *(u8 *)pvalue = halmac_adapter->chip_version;
- break;
- case HALMAC_HW_PAGE_SIZE:
- *(u32 *)pvalue = halmac_adapter->hw_config_info.page_size;
- break;
- case HALMAC_HW_TX_AGG_ALIGN_SIZE:
- *(u16 *)pvalue = halmac_adapter->hw_config_info.tx_align_size;
- break;
- case HALMAC_HW_RX_AGG_ALIGN_SIZE:
- *(u8 *)pvalue = 8;
- break;
- case HALMAC_HW_DRV_INFO_SIZE:
- *(u8 *)pvalue = halmac_adapter->drv_info_size;
- break;
- case HALMAC_HW_TXFF_ALLOCATION:
- memcpy(pvalue, &halmac_adapter->txff_allocation,
- sizeof(struct halmac_txff_allocation));
- break;
- case HALMAC_HW_TX_DESC_SIZE:
- *(u32 *)pvalue = halmac_adapter->hw_config_info.txdesc_size;
- break;
- case HALMAC_HW_RX_DESC_SIZE:
- *(u32 *)pvalue = halmac_adapter->hw_config_info.rxdesc_size;
- break;
- default:
- return HALMAC_RET_PARA_NOT_SUPPORT;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_set_hw_value_88xx() -set hw config value
- * @halmac_adapter : the adapter of halmac
- * @hw_id : hw id for driver to config
- * @pvalue : hw value, reference table to get data type
- * Author : KaiYuan Chang / Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_set_hw_value_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_hw_id hw_id, void *pvalue)
-{
- void *driver_adapter = NULL;
- enum halmac_ret_status status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_GET_HW_VALUE);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (!pvalue) {
- pr_err("%s (!pvalue)==========>\n", __func__);
- return HALMAC_RET_NULL_POINTER;
- }
-
- switch (hw_id) {
- case HALMAC_HW_USB_MODE:
- status = halmac_set_usb_mode_88xx(
- halmac_adapter, *(enum halmac_usb_mode *)pvalue);
- if (status != HALMAC_RET_SUCCESS)
- return status;
- break;
- case HALMAC_HW_SEQ_EN:
- break;
- case HALMAC_HW_BANDWIDTH:
- halmac_cfg_bw_88xx(halmac_adapter, *(enum halmac_bw *)pvalue);
- break;
- case HALMAC_HW_CHANNEL:
- halmac_cfg_ch_88xx(halmac_adapter, *(u8 *)pvalue);
- break;
- case HALMAC_HW_PRI_CHANNEL_IDX:
- halmac_cfg_pri_ch_idx_88xx(halmac_adapter,
- *(enum halmac_pri_ch_idx *)pvalue);
- break;
- case HALMAC_HW_EN_BB_RF:
- halmac_enable_bb_rf_88xx(halmac_adapter, *(u8 *)pvalue);
- break;
- case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD:
- halmac_config_sdio_tx_page_threshold_88xx(
- halmac_adapter,
- (struct halmac_tx_page_threshold_info *)pvalue);
- break;
- case HALMAC_HW_AMPDU_CONFIG:
- halmac_config_ampdu_88xx(halmac_adapter,
- (struct halmac_ampdu_config *)pvalue);
- break;
- default:
- return HALMAC_RET_PARA_NOT_SUPPORT;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver
- * @halmac_adapter : the adapter of halmac
- * @pg_num : page number
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_drv_rsvd_pg_num pg_num)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_CFG_DRV_RSVD_PG_NUM);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>pg_num = %d\n", __func__,
- pg_num);
-
- switch (pg_num) {
- case HALMAC_RSVD_PG_NUM16:
- halmac_adapter->txff_allocation.rsvd_drv_pg_num = 16;
- break;
- case HALMAC_RSVD_PG_NUM24:
- halmac_adapter->txff_allocation.rsvd_drv_pg_num = 24;
- break;
- case HALMAC_RSVD_PG_NUM32:
- halmac_adapter->txff_allocation.rsvd_drv_pg_num = 32;
- break;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_get_chip_version_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ver *version)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s ==========>\n", __func__);
- version->major_ver = (u8)HALMAC_MAJOR_VER_88XX;
- version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER_88XX;
- version->minor_ver = (u8)HALMAC_MINOR_VER_88XX;
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_chk_txdesc_88xx() -check if the tx packet format is incorrect
- * @halmac_adapter : the adapter of halmac
- * @halmac_buf : tx Packet buffer, tx desc is included
- * @halmac_size : tx packet size
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_chk_txdesc_88xx(struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
- u32 halmac_size)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (GET_TX_DESC_BMC(halmac_buf))
- if (GET_TX_DESC_AGG_EN(halmac_buf))
- pr_err("TxDesc: Agg should not be set when BMC\n");
-
- if (halmac_size < (GET_TX_DESC_TXPKTSIZE(halmac_buf) +
- GET_TX_DESC_OFFSET(halmac_buf)))
- pr_err("TxDesc: PktSize too small\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_dl_drv_rsvd_page_88xx() - download packet to rsvd page
- * @halmac_adapter : the adapter of halmac
- * @pg_offset : page offset of driver's rsvd page
- * @halmac_buf : data to be downloaded, tx_desc is not included
- * @halmac_size : data size to be downloaded
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_dl_drv_rsvd_page_88xx(struct halmac_adapter *halmac_adapter,
- u8 pg_offset, u8 *halmac_buf, u32 halmac_size)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status ret_status;
- u16 drv_pg_bndy = 0;
- u32 dl_pg_num = 0;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DL_DRV_RSVD_PG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- /*check boundary and size valid*/
- dl_pg_num = halmac_size / halmac_adapter->hw_config_info.page_size +
- ((halmac_size &
- (halmac_adapter->hw_config_info.page_size - 1)) ?
- 1 :
- 0);
- if (pg_offset + dl_pg_num >
- halmac_adapter->txff_allocation.rsvd_drv_pg_num) {
- pr_err("[ERROR] driver download offset or size error ==========>\n");
- return HALMAC_RET_DRV_DL_ERR;
- }
-
- /*update to target download boundary*/
- drv_pg_bndy =
- halmac_adapter->txff_allocation.rsvd_drv_pg_bndy + pg_offset;
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(drv_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
-
- ret_status = halmac_download_rsvd_page_88xx(halmac_adapter, halmac_buf,
- halmac_size);
-
- /*restore to original bundary*/
- if (ret_status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_download_rsvd_page_88xx Fail = %x!!\n",
- ret_status);
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
- return ret_status;
- }
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s < ==========\n", __func__);
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_csi_rate_88xx() - config CSI frame Tx rate
- * @halmac_adapter : the adapter of halmac
- * @rssi : rssi in decimal value
- * @current_rate : current CSI frame rate
- * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate
- * @new_rate : API returns the final CSI frame rate
- * Author : chunchu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_csi_rate_88xx(struct halmac_adapter *halmac_adapter, u8 rssi,
- u8 current_rate, u8 fixrate_en, u8 *new_rate)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- u32 temp_csi_setting;
- u16 current_rrsr;
- enum halmac_ret_status ret_status;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_CSI_RATE);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_SND, DBG_DMESG,
- "<%s ==========>\n", __func__);
-
- temp_csi_setting = HALMAC_REG_READ_32(halmac_adapter, REG_BBPSF_CTRL) &
- ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE);
-
- current_rrsr = HALMAC_REG_READ_16(halmac_adapter, REG_RRSR);
-
- if (rssi >= 40) {
- if (current_rate != HALMAC_OFDM54) {
- HALMAC_REG_WRITE_16(halmac_adapter, REG_RRSR,
- current_rrsr | BIT(HALMAC_OFDM54));
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_BBPSF_CTRL,
- temp_csi_setting |
- BIT_WMAC_CSI_RATE(HALMAC_OFDM54));
- }
- *new_rate = HALMAC_OFDM54;
- ret_status = HALMAC_RET_SUCCESS;
- } else {
- if (current_rate != HALMAC_OFDM24) {
- HALMAC_REG_WRITE_16(halmac_adapter, REG_RRSR,
- current_rrsr &
- ~(BIT(HALMAC_OFDM54)));
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_BBPSF_CTRL,
- temp_csi_setting |
- BIT_WMAC_CSI_RATE(HALMAC_OFDM24));
- }
- *new_rate = HALMAC_OFDM24;
- ret_status = HALMAC_RET_SUCCESS;
- }
-
- return ret_status;
-}
-
-/**
- * halmac_sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO
- * @halmac_adapter : the adapter of halmac
- * @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation
- * Author : Ivan Lin/KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_sdio_cmd53_4byte_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_sdio_cmd53_4byte_mode cmd53_4byte_mode)
-{
- halmac_adapter->sdio_cmd53_4byte = cmd53_4byte_mode;
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_txfifo_is_empty_88xx() -check if txfifo is empty
- * @halmac_adapter : the adapter of halmac
- * Author : Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_txfifo_is_empty_88xx(struct halmac_adapter *halmac_adapter, u32 chk_num)
-{
- u32 counter;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- counter = (chk_num <= 10) ? 10 : chk_num;
- do {
- if (HALMAC_REG_READ_8(halmac_adapter, REG_TXPKT_EMPTY) != 0xFF)
- return HALMAC_RET_TXFIFO_NO_EMPTY;
-
- if ((HALMAC_REG_READ_8(halmac_adapter, REG_TXPKT_EMPTY + 1) &
- 0x07) != 0x07)
- return HALMAC_RET_TXFIFO_NO_EMPTY;
- counter--;
-
- } while (counter != 0);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_COMMON, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_API_88XX_H_
-#define _HALMAC_API_88XX_H_
-
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-
-void halmac_init_state_machine_88xx(struct halmac_adapter *halmac_adapter);
-
-void halmac_init_adapter_para_88xx(struct halmac_adapter *halmac_adapter);
-
-void halmac_init_adapter_dynamic_para_88xx(
- struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_mount_api_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_download_firmware_88xx(struct halmac_adapter *halmac_adapter,
- u8 *hamacl_fw, u32 halmac_fw_size);
-
-enum halmac_ret_status
-halmac_free_download_firmware_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_dlfw_mem dlfw_mem, u8 *hamacl_fw,
- u32 halmac_fw_size);
-
-enum halmac_ret_status
-halmac_get_fw_version_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_fw_version *fw_version);
-
-enum halmac_ret_status
-halmac_cfg_mac_addr_88xx(struct halmac_adapter *halmac_adapter, u8 halmac_port,
- union halmac_wlan_addr *hal_address);
-
-enum halmac_ret_status
-halmac_cfg_bssid_88xx(struct halmac_adapter *halmac_adapter, u8 halmac_port,
- union halmac_wlan_addr *hal_address);
-
-enum halmac_ret_status
-halmac_cfg_multicast_addr_88xx(struct halmac_adapter *halmac_adapter,
- union halmac_wlan_addr *hal_address);
-
-enum halmac_ret_status
-halmac_pre_init_system_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_init_system_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_cfg_rx_aggregation_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_rxagg_cfg halmac_rxagg_cfg);
-
-enum halmac_ret_status
-halmac_init_edca_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_cfg_operation_mode_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_wireless_mode wireless_mode);
-
-enum halmac_ret_status
-halmac_cfg_ch_bw_88xx(struct halmac_adapter *halmac_adapter, u8 channel,
- enum halmac_pri_ch_idx pri_ch_idx, enum halmac_bw bw);
-
-enum halmac_ret_status halmac_cfg_ch_88xx(struct halmac_adapter *halmac_adapter,
- u8 channel);
-
-enum halmac_ret_status
-halmac_cfg_pri_ch_idx_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_pri_ch_idx pri_ch_idx);
-
-enum halmac_ret_status halmac_cfg_bw_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_bw bw);
-
-enum halmac_ret_status
-halmac_init_wmac_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_init_mac_cfg_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode mode);
-
-enum halmac_ret_status
-halmac_dump_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_read_cfg cfg);
-
-enum halmac_ret_status
-halmac_dump_efuse_map_bt_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_bank halmac_efuse_bank,
- u32 bt_efuse_map_size, u8 *bt_efuse_map);
-
-enum halmac_ret_status
-halmac_write_efuse_bt_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_value,
- enum halmac_efuse_bank halmac_efuse_bank);
-
-enum halmac_ret_status
-halmac_pg_efuse_by_map_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- enum halmac_efuse_read_cfg cfg);
-
-enum halmac_ret_status
-halmac_get_efuse_size_88xx(struct halmac_adapter *halmac_adapter,
- u32 *halmac_size);
-
-enum halmac_ret_status
-halmac_get_efuse_available_size_88xx(struct halmac_adapter *halmac_adapter,
- u32 *halmac_size);
-
-enum halmac_ret_status
-halmac_get_c2h_info_88xx(struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
- u32 halmac_size);
-
-enum halmac_ret_status
-halmac_get_logical_efuse_size_88xx(struct halmac_adapter *halmac_adapter,
- u32 *halmac_size);
-
-enum halmac_ret_status
-halmac_dump_logical_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_read_cfg cfg);
-
-enum halmac_ret_status
-halmac_write_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_value);
-
-enum halmac_ret_status
-halmac_read_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 *value);
-
-enum halmac_ret_status
-halmac_cfg_fwlps_option_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_fwlps_option *lps_option);
-
-enum halmac_ret_status
-halmac_cfg_fwips_option_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_fwips_option *ips_option);
-
-enum halmac_ret_status
-halmac_enter_wowlan_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_wowlan_option *wowlan_option);
-
-enum halmac_ret_status
-halmac_leave_wowlan_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_enter_ps_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_ps_state ps_state);
-
-enum halmac_ret_status
-halmac_leave_ps_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_h2c_lb_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status halmac_debug_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_cfg_parameter_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_phy_parameter_info *para_info,
- u8 full_fifo);
-
-enum halmac_ret_status
-halmac_update_packet_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_packet_id pkt_id, u8 *pkt, u32 pkt_size);
-
-enum halmac_ret_status
-halmac_bcn_ie_filter_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_bcn_ie_info *bcn_ie_info);
-
-enum halmac_ret_status
-halmac_send_original_h2c_88xx(struct halmac_adapter *halmac_adapter,
- u8 *original_h2c, u16 *seq, u8 ack);
-
-enum halmac_ret_status
-halmac_update_datapack_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_data_type halmac_data_type,
- struct halmac_phy_parameter_info *para_info);
-
-enum halmac_ret_status
-halmac_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_data_type halmac_data_type);
-
-enum halmac_ret_status
-halmac_cfg_drv_info_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_drv_info halmac_drv_info);
-
-enum halmac_ret_status
-halmac_send_bt_coex_88xx(struct halmac_adapter *halmac_adapter, u8 *bt_buf,
- u32 bt_size, u8 ack);
-
-enum halmac_ret_status
-halmac_verify_platform_api_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_timer_2s_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_fill_txdesc_check_sum_88xx(struct halmac_adapter *halmac_adapter,
- u8 *cur_desc);
-
-enum halmac_ret_status
-halmac_dump_fifo_88xx(struct halmac_adapter *halmac_adapter,
- enum hal_fifo_sel halmac_fifo_sel, u32 halmac_start_addr,
- u32 halmac_fifo_dump_size, u8 *fifo_map);
-
-u32 halmac_get_fifo_size_88xx(struct halmac_adapter *halmac_adapter,
- enum hal_fifo_sel halmac_fifo_sel);
-
-enum halmac_ret_status
-halmac_cfg_txbf_88xx(struct halmac_adapter *halmac_adapter, u8 userid,
- enum halmac_bw bw, u8 txbf_en);
-
-enum halmac_ret_status
-halmac_cfg_mumimo_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_cfg_mumimo_para *cfgmu);
-
-enum halmac_ret_status
-halmac_cfg_sounding_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_snd_role role,
- enum halmac_data_rate datarate);
-
-enum halmac_ret_status
-halmac_del_sounding_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_snd_role role);
-
-enum halmac_ret_status
-halmac_su_bfee_entry_init_88xx(struct halmac_adapter *halmac_adapter, u8 userid,
- u16 paid);
-
-enum halmac_ret_status
-halmac_su_bfer_entry_init_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_su_bfer_init_para *su_bfer_init);
-
-enum halmac_ret_status
-halmac_mu_bfee_entry_init_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_mu_bfee_init_para *mu_bfee_init);
-
-enum halmac_ret_status
-halmac_mu_bfer_entry_init_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_mu_bfer_init_para *mu_bfer_init);
-
-enum halmac_ret_status
-halmac_su_bfee_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid);
-
-enum halmac_ret_status
-halmac_su_bfer_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid);
-
-enum halmac_ret_status
-halmac_mu_bfee_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid);
-
-enum halmac_ret_status
-halmac_mu_bfer_entry_del_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_add_ch_info_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ch_info *ch_info);
-
-enum halmac_ret_status
-halmac_add_extra_ch_info_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ch_extra_info *ch_extra_info);
-
-enum halmac_ret_status
-halmac_ctrl_ch_switch_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ch_switch_option *cs_option);
-
-enum halmac_ret_status halmac_p2pps_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_p2pps *p2p_ps);
-
-enum halmac_ret_status
-halmac_func_p2pps_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_p2pps *p2p_ps);
-
-enum halmac_ret_status
-halmac_clear_ch_info_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_send_general_info_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_general_info *general_info);
-
-enum halmac_ret_status
-halmac_start_iqk_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_iqk_para_ *iqk_para);
-
-enum halmac_ret_status halmac_ctrl_pwr_tracking_88xx(
- struct halmac_adapter *halmac_adapter,
- struct halmac_pwr_tracking_option *pwr_tracking_opt);
-
-enum halmac_ret_status
-halmac_query_status_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_feature_id feature_id,
- enum halmac_cmd_process_status *process_status,
- u8 *data, u32 *size);
-
-enum halmac_ret_status
-halmac_reset_feature_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_feature_id feature_id);
-
-enum halmac_ret_status
-halmac_check_fw_status_88xx(struct halmac_adapter *halmac_adapter,
- bool *fw_status);
-
-enum halmac_ret_status
-halmac_dump_fw_dmem_88xx(struct halmac_adapter *halmac_adapter, u8 *dmem,
- u32 *size);
-
-enum halmac_ret_status
-halmac_cfg_max_dl_size_88xx(struct halmac_adapter *halmac_adapter, u32 size);
-
-enum halmac_ret_status halmac_psd_88xx(struct halmac_adapter *halmac_adapter,
- u16 start_psd, u16 end_psd);
-
-enum halmac_ret_status
-halmac_cfg_la_mode_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_la_mode la_mode);
-
-enum halmac_ret_status halmac_cfg_rx_fifo_expanding_mode_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode);
-
-enum halmac_ret_status
-halmac_config_security_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_security_setting *sec_setting);
-
-u8 halmac_get_used_cam_entry_num_88xx(struct halmac_adapter *halmac_adapter,
- enum hal_security_type sec_type);
-
-enum halmac_ret_status
-halmac_write_cam_88xx(struct halmac_adapter *halmac_adapter, u32 entry_index,
- struct halmac_cam_entry_info *cam_entry_info);
-
-enum halmac_ret_status
-halmac_read_cam_entry_88xx(struct halmac_adapter *halmac_adapter,
- u32 entry_index,
- struct halmac_cam_entry_format *content);
-
-enum halmac_ret_status
-halmac_clear_cam_entry_88xx(struct halmac_adapter *halmac_adapter,
- u32 entry_index);
-
-enum halmac_ret_status
-halmac_get_hw_value_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_hw_id hw_id, void *pvalue);
-
-enum halmac_ret_status
-halmac_set_hw_value_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_hw_id hw_id, void *pvalue);
-
-enum halmac_ret_status
-halmac_cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_drv_rsvd_pg_num pg_num);
-
-enum halmac_ret_status
-halmac_get_chip_version_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ver *version);
-
-enum halmac_ret_status
-halmac_chk_txdesc_88xx(struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
- u32 halmac_size);
-
-enum halmac_ret_status
-halmac_dl_drv_rsvd_page_88xx(struct halmac_adapter *halmac_adapter,
- u8 pg_offset, u8 *halmac_buf, u32 halmac_size);
-
-enum halmac_ret_status
-halmac_cfg_csi_rate_88xx(struct halmac_adapter *halmac_adapter, u8 rssi,
- u8 current_rate, u8 fixrate_en, u8 *new_rate);
-
-enum halmac_ret_status halmac_sdio_cmd53_4byte_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_sdio_cmd53_4byte_mode cmd53_4byte_mode);
-
-enum halmac_ret_status
-halmac_txfifo_is_empty_88xx(struct halmac_adapter *halmac_adapter, u32 chk_num);
-
-#endif /* _HALMAC_API_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halmac_88xx_cfg.h"
-
-/**
- * halmac_init_pcie_cfg_88xx() - init PCIe
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_PCIE_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_deinit_pcie_cfg_88xx() - deinit PCIE
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_deinit_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEINIT_PCIE_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_rx_aggregation_88xx_pcie() - config rx aggregation
- * @halmac_adapter : the adapter of halmac
- * @halmac_rx_agg_mode
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_rx_aggregation_88xx_pcie(struct halmac_adapter *halmac_adapter,
- struct halmac_rxagg_cfg *phalmac_rxagg_cfg)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_CFG_RX_AGGREGATION);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_8_pcie_88xx() - read 1byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u8 halmac_reg_read_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- return PLATFORM_REG_READ_8(driver_adapter, halmac_offset);
-}
-
-/**
- * halmac_reg_write_8_pcie_88xx() - write 1byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_data : register value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reg_write_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- PLATFORM_REG_WRITE_8(driver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_16_pcie_88xx() - read 2byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u16 halmac_reg_read_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- return PLATFORM_REG_READ_16(driver_adapter, halmac_offset);
-}
-
-/**
- * halmac_reg_write_16_pcie_88xx() - write 2byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_data : register value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reg_write_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u16 halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- PLATFORM_REG_WRITE_16(driver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_32_pcie_88xx() - read 4byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u32 halmac_reg_read_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- return PLATFORM_REG_READ_32(driver_adapter, halmac_offset);
-}
-
-/**
- * halmac_reg_write_32_pcie_88xx() - write 4byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_data : register value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reg_write_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u32 halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- PLATFORM_REG_WRITE_32(driver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_tx_agg_align_pcie_88xx() -config sdio bus tx agg alignment
- * @halmac_adapter : the adapter of halmac
- * @enable : function enable(1)/disable(0)
- * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
- * Author : Soar Tu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_cfg_tx_agg_align_pcie_not_support_88xx(
- struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size)
-{
- struct halmac_api *halmac_api;
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s not support\n", __func__);
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_API_88XX_PCIE_H_
-#define _HALMAC_API_88XX_PCIE_H_
-
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-
-#define LINK_CTRL2_REG_OFFSET 0xA0
-#define GEN2_CTRL_OFFSET 0x80C
-#define LINK_STATUS_REG_OFFSET 0x82
-#define GEN1_SPEED 0x01
-#define GEN2_SPEED 0x02
-
-enum halmac_ret_status
-halmac_init_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_deinit_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_cfg_rx_aggregation_88xx_pcie(struct halmac_adapter *halmac_adapter,
- struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
-
-u8 halmac_reg_read_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-enum halmac_ret_status
-halmac_reg_write_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_data);
-
-u16 halmac_reg_read_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-enum halmac_ret_status
-halmac_reg_write_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u16 halmac_data);
-
-u32 halmac_reg_read_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-enum halmac_ret_status
-halmac_reg_write_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u32 halmac_data);
-
-enum halmac_ret_status halmac_cfg_tx_agg_align_pcie_not_support_88xx(
- struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size);
-
-#endif /* _HALMAC_API_88XX_PCIE_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halmac_88xx_cfg.h"
-
-/**
- * halmac_init_sdio_cfg_88xx() - init SDIO
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_SDIO_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_REG_READ_32(halmac_adapter, REG_SDIO_FREE_TXPG);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_TX_CTRL, 0x00000000);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_deinit_sdio_cfg_88xx() - deinit SDIO
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_deinit_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEINIT_SDIO_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_rx_aggregation_88xx_sdio() - config rx aggregation
- * @halmac_adapter : the adapter of halmac
- * @halmac_rx_agg_mode
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_rx_aggregation_88xx_sdio(struct halmac_adapter *halmac_adapter,
- struct halmac_rxagg_cfg *phalmac_rxagg_cfg)
-{
- u8 value8;
- u8 size = 0, timeout = 0, agg_enable = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_CFG_RX_AGGREGATION);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- agg_enable = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_PQ_MAP);
-
- switch (phalmac_rxagg_cfg->mode) {
- case HALMAC_RX_AGG_MODE_NONE:
- agg_enable &= ~(BIT_RXDMA_AGG_EN);
- break;
- case HALMAC_RX_AGG_MODE_DMA:
- case HALMAC_RX_AGG_MODE_USB:
- agg_enable |= BIT_RXDMA_AGG_EN;
- break;
- default:
- pr_err("halmac_cfg_rx_aggregation_88xx_usb switch case not support\n");
- agg_enable &= ~BIT_RXDMA_AGG_EN;
- break;
- }
-
- if (!phalmac_rxagg_cfg->threshold.drv_define) {
- size = 0xFF;
- timeout = 0x01;
- } else {
- size = phalmac_rxagg_cfg->threshold.size;
- timeout = phalmac_rxagg_cfg->threshold.timeout;
- }
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_RXDMA_AGG_PG_TH,
- (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO)));
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_RXDMA_MODE);
- if ((agg_enable & BIT_RXDMA_AGG_EN) != 0)
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RXDMA_MODE,
- value8 | BIT_DMA_MODE);
- else
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RXDMA_MODE,
- value8 & ~(BIT_DMA_MODE));
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_8_sdio_88xx() - read 1byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u8 halmac_reg_read_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if ((halmac_offset & 0xFFFF0000) == 0)
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
- &halmac_offset);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s error = %x\n", __func__, status);
- return status;
- }
-
- return PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
-}
-
-/**
- * halmac_reg_write_8_sdio_88xx() - write 1byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_data : register value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reg_write_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if ((halmac_offset & 0xFFFF0000) == 0)
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
- &halmac_offset);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s error = %x\n", __func__, status);
- return status;
- }
-
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_16_sdio_88xx() - read 2byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u16 halmac_reg_read_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- union {
- u16 word;
- u8 byte[2];
- __le16 le_word;
- } value16 = {0x0000};
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if ((halmac_offset & 0xFFFF0000) == 0)
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
- &halmac_offset);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s error = %x\n", __func__, status);
- return status;
- }
-
- if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
- (halmac_offset & (2 - 1)) != 0 ||
- halmac_adapter->sdio_cmd53_4byte ==
- HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
- halmac_adapter->sdio_cmd53_4byte ==
- HALMAC_SDIO_CMD53_4BYTE_MODE_R) {
- value16.byte[0] =
- PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
- value16.byte[1] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
- halmac_offset + 1);
- value16.word = le16_to_cpu(value16.le_word);
- } else {
-#if (PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX)
- if ((halmac_offset & 0xffffef00) == 0x00000000) {
- value16.byte[0] = PLATFORM_SDIO_CMD52_READ(
- driver_adapter, halmac_offset);
- value16.byte[1] = PLATFORM_SDIO_CMD52_READ(
- driver_adapter, halmac_offset + 1);
- value16.word = le16_to_cpu(value16.word);
- } else {
- value16.word = PLATFORM_SDIO_CMD53_READ_16(
- driver_adapter, halmac_offset);
- }
-#else
- value16.word = PLATFORM_SDIO_CMD53_READ_16(driver_adapter,
- halmac_offset);
-#endif
- }
-
- return value16.word;
-}
-
-/**
- * halmac_reg_write_16_sdio_88xx() - write 2byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_data : register value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reg_write_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u16 halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if ((halmac_offset & 0xFFFF0000) == 0)
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
- &halmac_offset);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s error = %x\n", __func__, status);
- return status;
- }
-
- if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
- (halmac_offset & (2 - 1)) != 0 ||
- halmac_adapter->sdio_cmd53_4byte ==
- HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
- halmac_adapter->sdio_cmd53_4byte ==
- HALMAC_SDIO_CMD53_4BYTE_MODE_W) {
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
- (u8)(halmac_data & 0xFF));
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 1,
- (u8)((halmac_data & 0xFF00) >> 8));
- } else {
- PLATFORM_SDIO_CMD53_WRITE_16(driver_adapter, halmac_offset,
- halmac_data);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_32_sdio_88xx() - read 4byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u32 halmac_reg_read_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- u32 halmac_offset_old = 0;
-
- union {
- u32 dword;
- u8 byte[4];
- __le32 le_dword;
- } value32 = {0x00000000};
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- halmac_offset_old = halmac_offset;
-
- if ((halmac_offset & 0xFFFF0000) == 0)
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
- &halmac_offset);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s error = %x\n", __func__, status);
- return status;
- }
-
- if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
- (halmac_offset & (4 - 1)) != 0) {
- value32.byte[0] =
- PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
- value32.byte[1] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
- halmac_offset + 1);
- value32.byte[2] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
- halmac_offset + 2);
- value32.byte[3] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
- halmac_offset + 3);
- value32.dword = le32_to_cpu(value32.le_dword);
- } else {
-#if (PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX)
- if ((halmac_offset_old & 0xffffef00) == 0x00000000) {
- value32.byte[0] = PLATFORM_SDIO_CMD52_READ(
- driver_adapter, halmac_offset);
- value32.byte[1] = PLATFORM_SDIO_CMD52_READ(
- driver_adapter, halmac_offset + 1);
- value32.byte[2] = PLATFORM_SDIO_CMD52_READ(
- driver_adapter, halmac_offset + 2);
- value32.byte[3] = PLATFORM_SDIO_CMD52_READ(
- driver_adapter, halmac_offset + 3);
- value32.dword = le32_to_cpu(value32.dword);
- } else {
- value32.dword = PLATFORM_SDIO_CMD53_READ_32(
- driver_adapter, halmac_offset);
- }
-#else
- value32.dword = PLATFORM_SDIO_CMD53_READ_32(driver_adapter,
- halmac_offset);
-#endif
- }
-
- return value32.dword;
-}
-
-/**
- * halmac_reg_write_32_sdio_88xx() - write 4byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_data : register value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reg_write_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u32 halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if ((halmac_offset & 0xFFFF0000) == 0)
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
- &halmac_offset);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s error = %x\n", __func__, status);
- return status;
- }
-
- if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
- (halmac_offset & (4 - 1)) != 0) {
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
- (u8)(halmac_data & 0xFF));
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 1,
- (u8)((halmac_data & 0xFF00) >> 8));
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 2,
- (u8)((halmac_data & 0xFF0000) >> 16));
- PLATFORM_SDIO_CMD52_WRITE(
- driver_adapter, halmac_offset + 3,
- (u8)((halmac_data & 0xFF000000) >> 24));
- } else {
- PLATFORM_SDIO_CMD53_WRITE_32(driver_adapter, halmac_offset,
- halmac_data);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_nbyte_sdio_88xx() - read n byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_size : register value size
- * @halmac_data : register value
- * Author : Soar
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u8 halmac_reg_read_nbyte_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u32 halmac_size,
- u8 *halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if ((halmac_offset & 0xFFFF0000) == 0) {
- pr_err("halmac_offset error = 0x%x\n", halmac_offset);
- return HALMAC_RET_FAIL;
- }
-
- status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
- &halmac_offset);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s error = %x\n", __func__, status);
- return status;
- }
-
- if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) {
- pr_err("halmac_state error = 0x%x\n",
- halmac_adapter->halmac_state.mac_power);
- return HALMAC_RET_FAIL;
- }
-
- PLATFORM_SDIO_CMD53_READ_N(driver_adapter, halmac_offset, halmac_size,
- halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet
- * @halmac_adapter : the adapter of halmac
- * @halmac_buf : tx packet, include txdesc
- * @halmac_size : tx packet size
- * @pcmd53_addr : cmd53 addr value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_get_sdio_tx_addr_88xx(struct halmac_adapter *halmac_adapter,
- u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr)
-{
- u32 four_byte_len;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_queue_select queue_sel;
- enum halmac_dma_mapping dma_mapping;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_GET_SDIO_TX_ADDR);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (!halmac_buf) {
- pr_err("halmac_buf is NULL!!\n");
- return HALMAC_RET_DATA_BUF_NULL;
- }
-
- if (halmac_size == 0) {
- pr_err("halmac_size is 0!!\n");
- return HALMAC_RET_DATA_SIZE_INCORRECT;
- }
-
- queue_sel = (enum halmac_queue_select)GET_TX_DESC_QSEL(halmac_buf);
-
- switch (queue_sel) {
- case HALMAC_QUEUE_SELECT_VO:
- case HALMAC_QUEUE_SELECT_VO_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
- break;
- case HALMAC_QUEUE_SELECT_VI:
- case HALMAC_QUEUE_SELECT_VI_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
- break;
- case HALMAC_QUEUE_SELECT_BE:
- case HALMAC_QUEUE_SELECT_BE_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
- break;
- case HALMAC_QUEUE_SELECT_BK:
- case HALMAC_QUEUE_SELECT_BK_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
- break;
- case HALMAC_QUEUE_SELECT_MGNT:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
- break;
- case HALMAC_QUEUE_SELECT_HIGH:
- case HALMAC_QUEUE_SELECT_BCN:
- case HALMAC_QUEUE_SELECT_CMD:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
- break;
- default:
- pr_err("Qsel is out of range\n");
- return HALMAC_RET_QSEL_INCORRECT;
- }
-
- four_byte_len = (halmac_size >> 2) + ((halmac_size & (4 - 1)) ? 1 : 0);
-
- switch (dma_mapping) {
- case HALMAC_DMA_MAPPING_HIGH:
- *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH;
- break;
- case HALMAC_DMA_MAPPING_NORMAL:
- *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL;
- break;
- case HALMAC_DMA_MAPPING_LOW:
- *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW;
- break;
- case HALMAC_DMA_MAPPING_EXTRA:
- *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA;
- break;
- default:
- pr_err("DmaMapping is out of range\n");
- return HALMAC_RET_DMA_MAP_INCORRECT;
- }
-
- *pcmd53_addr = (*pcmd53_addr << 13) |
- (four_byte_len & HALMAC_SDIO_4BYTE_LEN_MASK);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_tx_agg_align_sdio_88xx() -config sdio bus tx agg alignment
- * @halmac_adapter : the adapter of halmac
- * @enable : function enable(1)/disable(0)
- * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
- * Author : Soar Tu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_tx_agg_align_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u8 enable, u16 align_size)
-{
- struct halmac_api *halmac_api;
- void *driver_adapter = NULL;
- u8 i, align_size_ok = 0;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if ((align_size & 0xF000) != 0) {
- pr_err("Align size is out of range\n");
- return HALMAC_RET_FAIL;
- }
-
- for (i = 3; i <= 11; i++) {
- if (align_size == 1 << i) {
- align_size_ok = 1;
- break;
- }
- }
- if (align_size_ok == 0) {
- pr_err("Align size is not 2^3 ~ 2^11\n");
- return HALMAC_RET_FAIL;
- }
-
- /*Keep sdio tx agg alignment size for driver query*/
- halmac_adapter->hw_config_info.tx_align_size = align_size;
-
- if (enable)
- HALMAC_REG_WRITE_16(halmac_adapter, REG_RQPN_CTRL_2,
- 0x8000 | align_size);
- else
- HALMAC_REG_WRITE_16(halmac_adapter, REG_RQPN_CTRL_2,
- align_size);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_cfg_tx_agg_align_sdio_not_support_88xx(
- struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size)
-{
- struct halmac_api *halmac_api;
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s not support\n", __func__);
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_tx_allowed_sdio_88xx() - check tx status
- * @halmac_adapter : the adapter of halmac
- * @halmac_buf : tx packet, include txdesc
- * @halmac_size : tx packet size, include txdesc
- * Author : Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_tx_allowed_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u8 *halmac_buf, u32 halmac_size)
-{
- u8 *curr_packet;
- u16 *curr_free_space;
- u32 i, counter;
- u32 tx_agg_num, packet_size = 0;
- u32 tx_required_page_num, total_required_page_num = 0;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- void *driver_adapter = NULL;
- enum halmac_dma_mapping dma_mapping;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_TX_ALLOWED_SDIO);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(halmac_buf);
- curr_packet = halmac_buf;
-
- tx_agg_num = tx_agg_num == 0 ? 1 : tx_agg_num;
-
- switch ((enum halmac_queue_select)GET_TX_DESC_QSEL(curr_packet)) {
- case HALMAC_QUEUE_SELECT_VO:
- case HALMAC_QUEUE_SELECT_VO_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
- break;
- case HALMAC_QUEUE_SELECT_VI:
- case HALMAC_QUEUE_SELECT_VI_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
- break;
- case HALMAC_QUEUE_SELECT_BE:
- case HALMAC_QUEUE_SELECT_BE_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
- break;
- case HALMAC_QUEUE_SELECT_BK:
- case HALMAC_QUEUE_SELECT_BK_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
- break;
- case HALMAC_QUEUE_SELECT_MGNT:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
- break;
- case HALMAC_QUEUE_SELECT_HIGH:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
- break;
- case HALMAC_QUEUE_SELECT_BCN:
- case HALMAC_QUEUE_SELECT_CMD:
- return HALMAC_RET_SUCCESS;
- default:
- pr_err("Qsel is out of range\n");
- return HALMAC_RET_QSEL_INCORRECT;
- }
-
- switch (dma_mapping) {
- case HALMAC_DMA_MAPPING_HIGH:
- curr_free_space =
- &halmac_adapter->sdio_free_space.high_queue_number;
- break;
- case HALMAC_DMA_MAPPING_NORMAL:
- curr_free_space =
- &halmac_adapter->sdio_free_space.normal_queue_number;
- break;
- case HALMAC_DMA_MAPPING_LOW:
- curr_free_space =
- &halmac_adapter->sdio_free_space.low_queue_number;
- break;
- case HALMAC_DMA_MAPPING_EXTRA:
- curr_free_space =
- &halmac_adapter->sdio_free_space.extra_queue_number;
- break;
- default:
- pr_err("DmaMapping is out of range\n");
- return HALMAC_RET_DMA_MAP_INCORRECT;
- }
-
- for (i = 0; i < tx_agg_num; i++) {
- packet_size = GET_TX_DESC_TXPKTSIZE(curr_packet) +
- GET_TX_DESC_OFFSET(curr_packet) +
- (GET_TX_DESC_PKT_OFFSET(curr_packet) << 3);
- tx_required_page_num =
- (packet_size >>
- halmac_adapter->hw_config_info.page_size_2_power) +
- ((packet_size &
- (halmac_adapter->hw_config_info.page_size - 1)) ?
- 1 :
- 0);
- total_required_page_num += tx_required_page_num;
-
- packet_size = HALMAC_ALIGN(packet_size, 8);
-
- curr_packet += packet_size;
- }
-
- counter = 10;
- do {
- if ((u32)(*curr_free_space +
- halmac_adapter->sdio_free_space.public_queue_number) >
- total_required_page_num) {
- if (*curr_free_space >= total_required_page_num) {
- *curr_free_space -=
- (u16)total_required_page_num;
- } else {
- halmac_adapter->sdio_free_space
- .public_queue_number -=
- (u16)(total_required_page_num -
- *curr_free_space);
- *curr_free_space = 0;
- }
-
- status = halmac_check_oqt_88xx(halmac_adapter,
- tx_agg_num, halmac_buf);
-
- if (status != HALMAC_RET_SUCCESS)
- return status;
-
- break;
- }
-
- halmac_update_sdio_free_page_88xx(halmac_adapter);
-
- counter--;
- if (counter == 0)
- return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
- } while (1);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_indirect_32_sdio_88xx() - read MAC reg by SDIO reg
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : Soar
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u32 halmac_reg_read_indirect_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- u8 rtemp;
- u32 counter = 1000;
- void *driver_adapter = NULL;
-
- union {
- u32 dword;
- u8 byte[4];
- } value32 = {0x00000000};
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- PLATFORM_SDIO_CMD53_WRITE_32(
- driver_adapter,
- (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
- (REG_SDIO_INDIRECT_REG_CFG & HALMAC_SDIO_LOCAL_MSK),
- halmac_offset | BIT(19) | BIT(17));
-
- do {
- rtemp = PLATFORM_SDIO_CMD52_READ(
- driver_adapter,
- (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
- ((REG_SDIO_INDIRECT_REG_CFG + 2) &
- HALMAC_SDIO_LOCAL_MSK));
- counter--;
- } while ((rtemp & BIT(4)) != 0 && counter > 0);
-
- value32.dword = PLATFORM_SDIO_CMD53_READ_32(
- driver_adapter,
- (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
- (REG_SDIO_INDIRECT_REG_DATA & HALMAC_SDIO_LOCAL_MSK));
-
- return value32.dword;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_API_88XX_SDIO_H_
-#define _HALMAC_API_88XX_SDIO_H_
-
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-
-enum halmac_ret_status
-halmac_init_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_deinit_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_cfg_rx_aggregation_88xx_sdio(struct halmac_adapter *halmac_adapter,
- struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
-
-u8 halmac_reg_read_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-enum halmac_ret_status
-halmac_reg_write_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_data);
-
-u16 halmac_reg_read_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-enum halmac_ret_status
-halmac_reg_write_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u16 halmac_data);
-
-u32 halmac_reg_read_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-enum halmac_ret_status
-halmac_reg_write_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u32 halmac_data);
-
-enum halmac_ret_status
-halmac_get_sdio_tx_addr_88xx(struct halmac_adapter *halmac_adapter,
- u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr);
-
-enum halmac_ret_status
-halmac_cfg_tx_agg_align_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u8 enable, u16 align_size);
-
-enum halmac_ret_status halmac_cfg_tx_agg_align_sdio_not_support_88xx(
- struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size);
-
-enum halmac_ret_status
-halmac_tx_allowed_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u8 *halmac_buf, u32 halmac_size);
-
-u32 halmac_reg_read_indirect_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-u8 halmac_reg_read_nbyte_sdio_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u32 halmac_size,
- u8 *halmac_data);
-
-#endif /* _HALMAC_API_88XX_SDIO_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halmac_88xx_cfg.h"
-
-/**
- * halmac_init_usb_cfg_88xx() - init USB
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_usb_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
- u8 value8 = 0;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_USB_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- value8 |= (BIT_DMA_MODE |
- (0x3 << BIT_SHIFT_BURST_CNT)); /* burst number = 4 */
-
- if (PLATFORM_REG_READ_8(driver_adapter, REG_SYS_CFG2 + 3) ==
- 0x20) { /* usb3.0 */
- value8 |= (HALMAC_USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE);
- } else {
- if ((PLATFORM_REG_READ_8(driver_adapter, REG_USB_USBSTAT) &
- 0x3) == 0x1) /* usb2.0 */
- value8 |= HALMAC_USB_BURST_SIZE_2_0_HSPEED
- << BIT_SHIFT_BURST_SIZE;
- else /* usb1.1 */
- value8 |= HALMAC_USB_BURST_SIZE_2_0_FSPEED
- << BIT_SHIFT_BURST_SIZE;
- }
-
- PLATFORM_REG_WRITE_8(driver_adapter, REG_RXDMA_MODE, value8);
- PLATFORM_REG_WRITE_16(
- driver_adapter, REG_TXDMA_OFFSET_CHK,
- PLATFORM_REG_READ_16(driver_adapter, REG_TXDMA_OFFSET_CHK) |
- BIT_DROP_DATA_EN);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_deinit_usb_cfg_88xx() - deinit USB
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_deinit_usb_cfg_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEINIT_USB_CFG);
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_rx_aggregation_88xx_usb() - config rx aggregation
- * @halmac_adapter : the adapter of halmac
- * @halmac_rx_agg_mode
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_cfg_rx_aggregation_88xx_usb(struct halmac_adapter *halmac_adapter,
- struct halmac_rxagg_cfg *phalmac_rxagg_cfg)
-{
- u8 dma_usb_agg;
- u8 size = 0, timeout = 0, agg_enable = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_CFG_RX_AGGREGATION);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- dma_usb_agg =
- HALMAC_REG_READ_8(halmac_adapter, REG_RXDMA_AGG_PG_TH + 3);
- agg_enable = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_PQ_MAP);
-
- switch (phalmac_rxagg_cfg->mode) {
- case HALMAC_RX_AGG_MODE_NONE:
- agg_enable &= ~BIT_RXDMA_AGG_EN;
- break;
- case HALMAC_RX_AGG_MODE_DMA:
- agg_enable |= BIT_RXDMA_AGG_EN;
- dma_usb_agg |= BIT(7);
- break;
-
- case HALMAC_RX_AGG_MODE_USB:
- agg_enable |= BIT_RXDMA_AGG_EN;
- dma_usb_agg &= ~BIT(7);
- break;
- default:
- pr_err("%s switch case not support\n", __func__);
- agg_enable &= ~BIT_RXDMA_AGG_EN;
- break;
- }
-
- if (!phalmac_rxagg_cfg->threshold.drv_define) {
- if (PLATFORM_REG_READ_8(driver_adapter, REG_SYS_CFG2 + 3) ==
- 0x20) {
- /* usb3.0 */
- size = 0x5;
- timeout = 0xA;
- } else {
- /* usb2.0 */
- size = 0x5;
- timeout = 0x20;
- }
- } else {
- size = phalmac_rxagg_cfg->threshold.size;
- timeout = phalmac_rxagg_cfg->threshold.timeout;
- }
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RXDMA_AGG_PG_TH + 3,
- dma_usb_agg);
- HALMAC_REG_WRITE_16(halmac_adapter, REG_RXDMA_AGG_PG_TH,
- (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO)));
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_8_usb_88xx() - read 1byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u8 halmac_reg_read_8_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- return PLATFORM_REG_READ_8(driver_adapter, halmac_offset);
-}
-
-/**
- * halmac_reg_write_8_usb_88xx() - write 1byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_data : register value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reg_write_8_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- PLATFORM_REG_WRITE_8(driver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_16_usb_88xx() - read 2byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u16 halmac_reg_read_16_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- union {
- u16 word;
- u8 byte[2];
- } value16 = {0x0000};
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- value16.word = PLATFORM_REG_READ_16(driver_adapter, halmac_offset);
-
- return value16.word;
-}
-
-/**
- * halmac_reg_write_16_usb_88xx() - write 2byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_data : register value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reg_write_16_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u16 halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- PLATFORM_REG_WRITE_16(driver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_32_usb_88xx() - read 4byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-u32 halmac_reg_read_32_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- union {
- u32 dword;
- u8 byte[4];
- } value32 = {0x00000000};
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- value32.dword = PLATFORM_REG_READ_32(driver_adapter, halmac_offset);
-
- return value32.dword;
-}
-
-/**
- * halmac_reg_write_32_usb_88xx() - write 4byte register
- * @halmac_adapter : the adapter of halmac
- * @halmac_offset : register offset
- * @halmac_data : register value
- * Author : KaiYuan Chang/Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_reg_write_32_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u32 halmac_data)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- PLATFORM_REG_WRITE_32(driver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_set_bulkout_num_usb_88xx() - inform bulk-out num
- * @halmac_adapter : the adapter of halmac
- * @bulkout_num : usb bulk-out number
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_set_bulkout_num_88xx(struct halmac_adapter *halmac_adapter,
- u8 bulkout_num)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_SET_BULKOUT_NUM);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- halmac_adapter->halmac_bulkout_num = bulkout_num;
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_usb_bulkout_id_usb_88xx() - get bulk out id for the TX packet
- * @halmac_adapter : the adapter of halmac
- * @halmac_buf : tx packet, include txdesc
- * @halmac_size : tx packet size
- * @bulkout_id : usb bulk-out id
- * Author : KaiYuan Chang
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_get_usb_bulkout_id_88xx(struct halmac_adapter *halmac_adapter,
- u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_queue_select queue_sel;
- enum halmac_dma_mapping dma_mapping;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter,
- HALMAC_API_GET_USB_BULKOUT_ID);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- if (!halmac_buf) {
- pr_err("halmac_buf is NULL!!\n");
- return HALMAC_RET_DATA_BUF_NULL;
- }
-
- if (halmac_size == 0) {
- pr_err("halmac_size is 0!!\n");
- return HALMAC_RET_DATA_SIZE_INCORRECT;
- }
-
- queue_sel = (enum halmac_queue_select)GET_TX_DESC_QSEL(halmac_buf);
-
- switch (queue_sel) {
- case HALMAC_QUEUE_SELECT_VO:
- case HALMAC_QUEUE_SELECT_VO_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
- break;
- case HALMAC_QUEUE_SELECT_VI:
- case HALMAC_QUEUE_SELECT_VI_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
- break;
- case HALMAC_QUEUE_SELECT_BE:
- case HALMAC_QUEUE_SELECT_BE_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
- break;
- case HALMAC_QUEUE_SELECT_BK:
- case HALMAC_QUEUE_SELECT_BK_V2:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
- break;
- case HALMAC_QUEUE_SELECT_MGNT:
- dma_mapping =
- halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
- break;
- case HALMAC_QUEUE_SELECT_HIGH:
- case HALMAC_QUEUE_SELECT_BCN:
- case HALMAC_QUEUE_SELECT_CMD:
- dma_mapping = HALMAC_DMA_MAPPING_HIGH;
- break;
- default:
- pr_err("Qsel is out of range\n");
- return HALMAC_RET_QSEL_INCORRECT;
- }
-
- switch (dma_mapping) {
- case HALMAC_DMA_MAPPING_HIGH:
- *bulkout_id = 0;
- break;
- case HALMAC_DMA_MAPPING_NORMAL:
- *bulkout_id = 1;
- break;
- case HALMAC_DMA_MAPPING_LOW:
- *bulkout_id = 2;
- break;
- case HALMAC_DMA_MAPPING_EXTRA:
- *bulkout_id = 3;
- break;
- default:
- pr_err("DmaMapping is out of range\n");
- return HALMAC_RET_DMA_MAP_INCORRECT;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_tx_agg_align_usb_88xx() -config sdio bus tx agg alignment
- * @halmac_adapter : the adapter of halmac
- * @enable : function enable(1)/disable(0)
- * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
- * Author : Soar Tu
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_cfg_tx_agg_align_usb_not_support_88xx(
- struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size)
-{
- struct halmac_api *halmac_api;
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s not support\n", __func__);
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_API_88XX_USB_H_
-#define _HALMAC_API_88XX_USB_H_
-
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-
-enum halmac_ret_status
-halmac_init_usb_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_deinit_usb_cfg_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_cfg_rx_aggregation_88xx_usb(struct halmac_adapter *halmac_adapter,
- struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
-
-u8 halmac_reg_read_8_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-enum halmac_ret_status
-halmac_reg_write_8_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u8 halmac_data);
-
-u16 halmac_reg_read_16_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-enum halmac_ret_status
-halmac_reg_write_16_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u16 halmac_data);
-
-u32 halmac_reg_read_32_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
-
-enum halmac_ret_status
-halmac_reg_write_32_usb_88xx(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset, u32 halmac_data);
-
-enum halmac_ret_status
-halmac_set_bulkout_num_88xx(struct halmac_adapter *halmac_adapter,
- u8 bulkout_num);
-
-enum halmac_ret_status
-halmac_get_usb_bulkout_id_88xx(struct halmac_adapter *halmac_adapter,
- u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id);
-
-enum halmac_ret_status halmac_cfg_tx_agg_align_usb_not_support_88xx(
- struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size);
-
-#endif /* _HALMAC_API_88XX_USB_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halmac_88xx_cfg.h"
-
-static enum halmac_ret_status
-halmac_dump_efuse_fw_88xx(struct halmac_adapter *halmac_adapter);
-
-static enum halmac_ret_status
-halmac_dump_efuse_drv_88xx(struct halmac_adapter *halmac_adapter);
-
-static enum halmac_ret_status
-halmac_update_eeprom_mask_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- u8 *eeprom_mask_updated);
-
-static enum halmac_ret_status
-halmac_check_efuse_enough_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- u8 *eeprom_mask_updated);
-
-static enum halmac_ret_status
-halmac_program_efuse_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- u8 *eeprom_mask_updated);
-
-static enum halmac_ret_status
-halmac_pwr_sub_seq_parer_88xx(struct halmac_adapter *halmac_adapter, u8 cut,
- u8 fab, u8 intf,
- struct halmac_wl_pwr_cfg_ *pwr_sub_seq_cfg);
-
-static enum halmac_ret_status
-halmac_parse_c2h_debug_88xx(struct halmac_adapter *halmac_adapter, u8 *c2h_buf,
- u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_scan_status_rpt_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_psd_data_88xx(struct halmac_adapter *halmac_adapter, u8 *c2h_buf,
- u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_efuse_data_88xx(struct halmac_adapter *halmac_adapter, u8 *c2h_buf,
- u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_88xx(struct halmac_adapter *halmac_adapter, u8 *c2h_buf,
- u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_enqueue_para_buff_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_phy_parameter_info *para_info,
- u8 *curr_buff_wptr, bool *end_cmd);
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_phy_efuse_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_cfg_para_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_gen_cfg_para_h2c_88xx(struct halmac_adapter *halmac_adapter,
- u8 *h2c_buff);
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_update_packet_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_update_datapack_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_channel_switch_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_iqk_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size);
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_power_tracking_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size);
-
-void halmac_init_offload_feature_state_machine_88xx(
- struct halmac_adapter *halmac_adapter)
-{
- struct halmac_state *state = &halmac_adapter->halmac_state;
-
- state->efuse_state_set.efuse_cmd_construct_state =
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE;
- state->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->efuse_state_set.seq_num = halmac_adapter->h2c_packet_seq;
-
- state->cfg_para_state_set.cfg_para_cmd_construct_state =
- HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE;
- state->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->cfg_para_state_set.seq_num = halmac_adapter->h2c_packet_seq;
-
- state->scan_state_set.scan_cmd_construct_state =
- HALMAC_SCAN_CMD_CONSTRUCT_IDLE;
- state->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->scan_state_set.seq_num = halmac_adapter->h2c_packet_seq;
-
- state->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->update_packet_set.seq_num = halmac_adapter->h2c_packet_seq;
-
- state->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->iqk_set.seq_num = halmac_adapter->h2c_packet_seq;
-
- state->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->power_tracking_set.seq_num = halmac_adapter->h2c_packet_seq;
-
- state->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- state->psd_set.seq_num = halmac_adapter->h2c_packet_seq;
- state->psd_set.data_size = 0;
- state->psd_set.segment_size = 0;
- state->psd_set.data = NULL;
-}
-
-enum halmac_ret_status
-halmac_dump_efuse_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_read_cfg cfg)
-{
- u32 chk_h2c_init;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api =
- (struct halmac_api *)halmac_adapter->halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.efuse_state_set.process_status;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- *process_status = HALMAC_CMD_PROCESS_SENDING;
-
- if (halmac_transition_efuse_state_88xx(
- halmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- if (cfg == HALMAC_EFUSE_R_AUTO) {
- chk_h2c_init = HALMAC_REG_READ_32(halmac_adapter,
- REG_H2C_PKT_READADDR);
- if (halmac_adapter->halmac_state.dlfw_state ==
- HALMAC_DLFW_NONE ||
- chk_h2c_init == 0)
- status = halmac_dump_efuse_drv_88xx(halmac_adapter);
- else
- status = halmac_dump_efuse_fw_88xx(halmac_adapter);
- } else if (cfg == HALMAC_EFUSE_R_FW) {
- status = halmac_dump_efuse_fw_88xx(halmac_adapter);
- } else {
- status = halmac_dump_efuse_drv_88xx(halmac_adapter);
- }
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_read_efuse error = %x\n", status);
- return status;
- }
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_func_read_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
- u32 size, u8 *efuse_map)
-{
- void *driver_adapter = NULL;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- if (!efuse_map) {
- pr_err("Malloc for dump efuse map error\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- if (halmac_adapter->hal_efuse_map_valid)
- memcpy(efuse_map, halmac_adapter->hal_efuse_map + offset, size);
- else if (halmac_read_hw_efuse_88xx(halmac_adapter, offset, size,
- efuse_map) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_EFUSE_R_FAIL;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_read_hw_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
- u32 size, u8 *efuse_map)
-{
- u8 value8;
- u32 value32;
- u32 address;
- u32 tmp32, counter;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- /* Read efuse no need 2.5V LDO */
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_LDO_EFUSE_CTRL + 3);
- if (value8 & BIT(7))
- HALMAC_REG_WRITE_8(halmac_adapter, REG_LDO_EFUSE_CTRL + 3,
- (u8)(value8 & ~(BIT(7))));
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_EFUSE_CTRL);
-
- for (address = offset; address < offset + size; address++) {
- value32 = value32 &
- ~((BIT_MASK_EF_DATA) |
- (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR));
- value32 = value32 |
- ((address & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_EFUSE_CTRL,
- value32 & (~BIT_EF_FLAG));
-
- counter = 1000000;
- do {
- udelay(1);
- tmp32 = HALMAC_REG_READ_32(halmac_adapter,
- REG_EFUSE_CTRL);
- counter--;
- if (counter == 0) {
- pr_err("HALMAC_RET_EFUSE_R_FAIL\n");
- return HALMAC_RET_EFUSE_R_FAIL;
- }
- } while ((tmp32 & BIT_EF_FLAG) == 0);
-
- *(efuse_map + address - offset) =
- (u8)(tmp32 & BIT_MASK_EF_DATA);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_dump_efuse_drv_88xx(struct halmac_adapter *halmac_adapter)
-{
- u8 *efuse_map = NULL;
- u32 efuse_size;
- void *driver_adapter = NULL;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- efuse_size = halmac_adapter->hw_config_info.efuse_size;
-
- if (!halmac_adapter->hal_efuse_map) {
- halmac_adapter->hal_efuse_map = kzalloc(efuse_size, GFP_KERNEL);
- if (!halmac_adapter->hal_efuse_map)
- return HALMAC_RET_MALLOC_FAIL;
- }
-
- efuse_map = kzalloc(efuse_size, GFP_KERNEL);
- if (!efuse_map)
- return HALMAC_RET_MALLOC_FAIL;
-
- if (halmac_read_hw_efuse_88xx(halmac_adapter, 0, efuse_size,
- efuse_map) != HALMAC_RET_SUCCESS) {
- kfree(efuse_map);
- return HALMAC_RET_EFUSE_R_FAIL;
- }
-
- spin_lock(&halmac_adapter->efuse_lock);
- memcpy(halmac_adapter->hal_efuse_map, efuse_map, efuse_size);
- halmac_adapter->hal_efuse_map_valid = true;
- spin_unlock(&halmac_adapter->efuse_lock);
-
- kfree(efuse_map);
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_dump_efuse_fw_88xx(struct halmac_adapter *halmac_adapter)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = NULL;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE;
- h2c_header_info.content_size = 0;
- h2c_header_info.ack = true;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
- halmac_adapter->halmac_state.efuse_state_set.seq_num = h2c_seq_mum;
-
- if (!halmac_adapter->hal_efuse_map) {
- halmac_adapter->hal_efuse_map = kzalloc(
- halmac_adapter->hw_config_info.efuse_size, GFP_KERNEL);
- if (!halmac_adapter->hal_efuse_map)
- return HALMAC_RET_MALLOC_FAIL;
- }
-
- if (!halmac_adapter->hal_efuse_map_valid) {
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX,
- true);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_read_efuse_fw Fail = %x!!\n", status);
- return status;
- }
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_func_write_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
- u8 value)
-{
- const u8 wite_protect_code = 0x69;
- u32 value32, tmp32, counter;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- spin_lock(&halmac_adapter->efuse_lock);
- halmac_adapter->hal_efuse_map_valid = false;
- spin_unlock(&halmac_adapter->efuse_lock);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PMC_DBG_CTRL2 + 3,
- wite_protect_code);
-
- /* Enable 2.5V LDO */
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_LDO_EFUSE_CTRL + 3,
- (u8)(HALMAC_REG_READ_8(halmac_adapter, REG_LDO_EFUSE_CTRL + 3) |
- BIT(7)));
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_EFUSE_CTRL);
- value32 =
- value32 &
- ~((BIT_MASK_EF_DATA) | (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR));
- value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) |
- (value & BIT_MASK_EF_DATA);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_EFUSE_CTRL,
- value32 | BIT_EF_FLAG);
-
- counter = 1000000;
- do {
- udelay(1);
- tmp32 = HALMAC_REG_READ_32(halmac_adapter, REG_EFUSE_CTRL);
- counter--;
- if (counter == 0) {
- pr_err("halmac_write_efuse Fail !!\n");
- return HALMAC_RET_EFUSE_W_FAIL;
- }
- } while ((tmp32 & BIT_EF_FLAG) == BIT_EF_FLAG);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PMC_DBG_CTRL2 + 3, 0x00);
-
- /* Disable 2.5V LDO */
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_LDO_EFUSE_CTRL + 3,
- (u8)(HALMAC_REG_READ_8(halmac_adapter, REG_LDO_EFUSE_CTRL + 3) &
- ~(BIT(7))));
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_func_switch_efuse_bank_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_bank efuse_bank)
-{
- u8 reg_value;
- struct halmac_api *halmac_api;
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (halmac_transition_efuse_state_88xx(
- halmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_BUSY) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- reg_value = HALMAC_REG_READ_8(halmac_adapter, REG_LDO_EFUSE_CTRL + 1);
-
- if (efuse_bank == (reg_value & (BIT(0) | BIT(1))))
- return HALMAC_RET_SUCCESS;
-
- reg_value &= ~(BIT(0) | BIT(1));
- reg_value |= efuse_bank;
- HALMAC_REG_WRITE_8(halmac_adapter, REG_LDO_EFUSE_CTRL + 1, reg_value);
-
- if ((HALMAC_REG_READ_8(halmac_adapter, REG_LDO_EFUSE_CTRL + 1) &
- (BIT(0) | BIT(1))) != efuse_bank)
- return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_eeprom_parser_88xx(struct halmac_adapter *halmac_adapter,
- u8 *physical_efuse_map, u8 *logical_efuse_map)
-{
- u8 j;
- u8 value8;
- u8 block_index;
- u8 valid_word_enable, word_enable;
- u8 efuse_read_header, efuse_read_header2 = 0;
- u32 eeprom_index;
- u32 efuse_index = 0;
- u32 eeprom_size = halmac_adapter->hw_config_info.eeprom_size;
- void *driver_adapter = NULL;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- memset(logical_efuse_map, 0xFF, eeprom_size);
-
- do {
- value8 = *(physical_efuse_map + efuse_index);
- efuse_read_header = value8;
-
- if ((efuse_read_header & 0x1f) == 0x0f) {
- efuse_index++;
- value8 = *(physical_efuse_map + efuse_index);
- efuse_read_header2 = value8;
- block_index = ((efuse_read_header2 & 0xF0) >> 1) |
- ((efuse_read_header >> 5) & 0x07);
- word_enable = efuse_read_header2 & 0x0F;
- } else {
- block_index = (efuse_read_header & 0xF0) >> 4;
- word_enable = efuse_read_header & 0x0F;
- }
-
- if (efuse_read_header == 0xff)
- break;
-
- efuse_index++;
-
- if (efuse_index >= halmac_adapter->hw_config_info.efuse_size -
- HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1)
- return HALMAC_RET_EEPROM_PARSING_FAIL;
-
- for (j = 0; j < 4; j++) {
- valid_word_enable =
- (u8)((~(word_enable >> j)) & BIT(0));
- if (valid_word_enable != 1)
- continue;
-
- eeprom_index = (block_index << 3) + (j << 1);
-
- if ((eeprom_index + 1) > eeprom_size) {
- pr_err("Error: EEPROM addr exceeds eeprom_size:0x%X, at eFuse 0x%X\n",
- eeprom_size, efuse_index - 1);
- if ((efuse_read_header & 0x1f) == 0x0f)
- pr_err("Error: EEPROM header: 0x%X, 0x%X,\n",
- efuse_read_header,
- efuse_read_header2);
- else
- pr_err("Error: EEPROM header: 0x%X,\n",
- efuse_read_header);
-
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- }
-
- value8 = *(physical_efuse_map + efuse_index);
- *(logical_efuse_map + eeprom_index) = value8;
-
- eeprom_index++;
- efuse_index++;
-
- if (efuse_index >
- halmac_adapter->hw_config_info.efuse_size -
- HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1)
- return HALMAC_RET_EEPROM_PARSING_FAIL;
-
- value8 = *(physical_efuse_map + efuse_index);
- *(logical_efuse_map + eeprom_index) = value8;
-
- efuse_index++;
-
- if (efuse_index >
- halmac_adapter->hw_config_info.efuse_size -
- HALMAC_PROTECTED_EFUSE_SIZE_88XX)
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- }
- } while (1);
-
- halmac_adapter->efuse_end = efuse_index;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_read_logical_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
- u8 *map)
-{
- u8 *efuse_map = NULL;
- u32 efuse_size;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
- efuse_size = halmac_adapter->hw_config_info.efuse_size;
-
- if (!halmac_adapter->hal_efuse_map_valid) {
- efuse_map = kzalloc(efuse_size, GFP_KERNEL);
- if (!efuse_map)
- return HALMAC_RET_MALLOC_FAIL;
-
- status = halmac_func_read_efuse_88xx(halmac_adapter, 0,
- efuse_size, efuse_map);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("[ERR]halmac_read_efuse error = %x\n", status);
- kfree(efuse_map);
- return status;
- }
-
- if (!halmac_adapter->hal_efuse_map) {
- halmac_adapter->hal_efuse_map =
- kzalloc(efuse_size, GFP_KERNEL);
- if (!halmac_adapter->hal_efuse_map) {
- kfree(efuse_map);
- return HALMAC_RET_MALLOC_FAIL;
- }
- }
-
- spin_lock(&halmac_adapter->efuse_lock);
- memcpy(halmac_adapter->hal_efuse_map, efuse_map, efuse_size);
- halmac_adapter->hal_efuse_map_valid = true;
- spin_unlock(&halmac_adapter->efuse_lock);
-
- kfree(efuse_map);
- }
-
- if (halmac_eeprom_parser_88xx(halmac_adapter,
- halmac_adapter->hal_efuse_map,
- map) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_EEPROM_PARSING_FAIL;
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_func_write_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
- u32 offset, u8 value)
-{
- u8 pg_efuse_byte1, pg_efuse_byte2;
- u8 pg_block, pg_block_index;
- u8 pg_efuse_header, pg_efuse_header2;
- u8 *eeprom_map = NULL;
- u32 eeprom_size = halmac_adapter->hw_config_info.eeprom_size;
- u32 efuse_end, pg_efuse_num;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- eeprom_map = kzalloc(eeprom_size, GFP_KERNEL);
- if (!eeprom_map)
- return HALMAC_RET_MALLOC_FAIL;
- memset(eeprom_map, 0xFF, eeprom_size);
-
- status = halmac_read_logical_efuse_map_88xx(halmac_adapter, eeprom_map);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("[ERR]halmac_read_logical_efuse_map_88xx error = %x\n",
- status);
- kfree(eeprom_map);
- return status;
- }
-
- if (*(eeprom_map + offset) != value) {
- efuse_end = halmac_adapter->efuse_end;
- pg_block = (u8)(offset >> 3);
- pg_block_index = (u8)((offset & (8 - 1)) >> 1);
-
- if (offset > 0x7f) {
- pg_efuse_header =
- (((pg_block & 0x07) << 5) & 0xE0) | 0x0F;
- pg_efuse_header2 =
- (u8)(((pg_block & 0x78) << 1) +
- ((0x1 << pg_block_index) ^ 0x0F));
- } else {
- pg_efuse_header =
- (u8)((pg_block << 4) +
- ((0x01 << pg_block_index) ^ 0x0F));
- }
-
- if ((offset & 1) == 0) {
- pg_efuse_byte1 = value;
- pg_efuse_byte2 = *(eeprom_map + offset + 1);
- } else {
- pg_efuse_byte1 = *(eeprom_map + offset - 1);
- pg_efuse_byte2 = value;
- }
-
- if (offset > 0x7f) {
- pg_efuse_num = 4;
- if (halmac_adapter->hw_config_info.efuse_size <=
- (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX +
- halmac_adapter->efuse_end)) {
- kfree(eeprom_map);
- return HALMAC_RET_EFUSE_NOT_ENOUGH;
- }
- halmac_func_write_efuse_88xx(halmac_adapter, efuse_end,
- pg_efuse_header);
- halmac_func_write_efuse_88xx(halmac_adapter,
- efuse_end + 1,
- pg_efuse_header2);
- halmac_func_write_efuse_88xx(
- halmac_adapter, efuse_end + 2, pg_efuse_byte1);
- status = halmac_func_write_efuse_88xx(
- halmac_adapter, efuse_end + 3, pg_efuse_byte2);
- } else {
- pg_efuse_num = 3;
- if (halmac_adapter->hw_config_info.efuse_size <=
- (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX +
- halmac_adapter->efuse_end)) {
- kfree(eeprom_map);
- return HALMAC_RET_EFUSE_NOT_ENOUGH;
- }
- halmac_func_write_efuse_88xx(halmac_adapter, efuse_end,
- pg_efuse_header);
- halmac_func_write_efuse_88xx(
- halmac_adapter, efuse_end + 1, pg_efuse_byte1);
- status = halmac_func_write_efuse_88xx(
- halmac_adapter, efuse_end + 2, pg_efuse_byte2);
- }
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("[ERR]halmac_write_logical_efuse error = %x\n",
- status);
- kfree(eeprom_map);
- return status;
- }
- }
-
- kfree(eeprom_map);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_func_pg_efuse_by_map_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- enum halmac_efuse_read_cfg cfg)
-{
- u8 *eeprom_mask_updated = NULL;
- u32 eeprom_mask_size = halmac_adapter->hw_config_info.eeprom_size >> 4;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- eeprom_mask_updated = kzalloc(eeprom_mask_size, GFP_KERNEL);
- if (!eeprom_mask_updated)
- return HALMAC_RET_MALLOC_FAIL;
-
- status = halmac_update_eeprom_mask_88xx(halmac_adapter, pg_efuse_info,
- eeprom_mask_updated);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("[ERR]halmac_update_eeprom_mask_88xx error = %x\n",
- status);
- kfree(eeprom_mask_updated);
- return status;
- }
-
- status = halmac_check_efuse_enough_88xx(halmac_adapter, pg_efuse_info,
- eeprom_mask_updated);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("[ERR]halmac_check_efuse_enough_88xx error = %x\n",
- status);
- kfree(eeprom_mask_updated);
- return status;
- }
-
- status = halmac_program_efuse_88xx(halmac_adapter, pg_efuse_info,
- eeprom_mask_updated);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("[ERR]halmac_program_efuse_88xx error = %x\n", status);
- kfree(eeprom_mask_updated);
- return status;
- }
-
- kfree(eeprom_mask_updated);
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_update_eeprom_mask_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- u8 *eeprom_mask_updated)
-{
- u8 *eeprom_map = NULL;
- u32 eeprom_size = halmac_adapter->hw_config_info.eeprom_size;
- u8 *eeprom_map_pg, *eeprom_mask;
- u16 i, j;
- u16 map_byte_offset, mask_byte_offset;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- void *driver_adapter = NULL;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- eeprom_map = kzalloc(eeprom_size, GFP_KERNEL);
- if (!eeprom_map)
- return HALMAC_RET_MALLOC_FAIL;
-
- memset(eeprom_map, 0xFF, eeprom_size);
- memset(eeprom_mask_updated, 0x00, pg_efuse_info->efuse_mask_size);
-
- status = halmac_read_logical_efuse_map_88xx(halmac_adapter, eeprom_map);
-
- if (status != HALMAC_RET_SUCCESS) {
- kfree(eeprom_map);
- return status;
- }
-
- eeprom_map_pg = pg_efuse_info->efuse_map;
- eeprom_mask = pg_efuse_info->efuse_mask;
-
- for (i = 0; i < pg_efuse_info->efuse_mask_size; i++)
- *(eeprom_mask_updated + i) = *(eeprom_mask + i);
-
- for (i = 0; i < pg_efuse_info->efuse_map_size; i = i + 16) {
- for (j = 0; j < 16; j = j + 2) {
- map_byte_offset = i + j;
- mask_byte_offset = i >> 4;
- if (*(eeprom_map_pg + map_byte_offset) ==
- *(eeprom_map + map_byte_offset)) {
- if (*(eeprom_map_pg + map_byte_offset + 1) ==
- *(eeprom_map + map_byte_offset + 1)) {
- switch (j) {
- case 0:
- *(eeprom_mask_updated +
- mask_byte_offset) =
- *(eeprom_mask_updated +
- mask_byte_offset) &
- (BIT(4) ^ 0xFF);
- break;
- case 2:
- *(eeprom_mask_updated +
- mask_byte_offset) =
- *(eeprom_mask_updated +
- mask_byte_offset) &
- (BIT(5) ^ 0xFF);
- break;
- case 4:
- *(eeprom_mask_updated +
- mask_byte_offset) =
- *(eeprom_mask_updated +
- mask_byte_offset) &
- (BIT(6) ^ 0xFF);
- break;
- case 6:
- *(eeprom_mask_updated +
- mask_byte_offset) =
- *(eeprom_mask_updated +
- mask_byte_offset) &
- (BIT(7) ^ 0xFF);
- break;
- case 8:
- *(eeprom_mask_updated +
- mask_byte_offset) =
- *(eeprom_mask_updated +
- mask_byte_offset) &
- (BIT(0) ^ 0xFF);
- break;
- case 10:
- *(eeprom_mask_updated +
- mask_byte_offset) =
- *(eeprom_mask_updated +
- mask_byte_offset) &
- (BIT(1) ^ 0xFF);
- break;
- case 12:
- *(eeprom_mask_updated +
- mask_byte_offset) =
- *(eeprom_mask_updated +
- mask_byte_offset) &
- (BIT(2) ^ 0xFF);
- break;
- case 14:
- *(eeprom_mask_updated +
- mask_byte_offset) =
- *(eeprom_mask_updated +
- mask_byte_offset) &
- (BIT(3) ^ 0xFF);
- break;
- default:
- break;
- }
- }
- }
- }
- }
-
- kfree(eeprom_map);
-
- return status;
-}
-
-static enum halmac_ret_status
-halmac_check_efuse_enough_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- u8 *eeprom_mask_updated)
-{
- u8 pre_word_enb, word_enb;
- u8 pg_efuse_header, pg_efuse_header2;
- u8 pg_block;
- u16 i, j;
- u32 efuse_end;
- u32 tmp_eeprom_offset, pg_efuse_num = 0;
-
- efuse_end = halmac_adapter->efuse_end;
-
- for (i = 0; i < pg_efuse_info->efuse_map_size; i = i + 8) {
- tmp_eeprom_offset = i;
-
- if ((tmp_eeprom_offset & 7) > 0) {
- pre_word_enb =
- (*(eeprom_mask_updated + (i >> 4)) & 0x0F);
- word_enb = pre_word_enb ^ 0x0F;
- } else {
- pre_word_enb = (*(eeprom_mask_updated + (i >> 4)) >> 4);
- word_enb = pre_word_enb ^ 0x0F;
- }
-
- pg_block = (u8)(tmp_eeprom_offset >> 3);
-
- if (pre_word_enb > 0) {
- if (tmp_eeprom_offset > 0x7f) {
- pg_efuse_header =
- (((pg_block & 0x07) << 5) & 0xE0) |
- 0x0F;
- pg_efuse_header2 = (u8)(
- ((pg_block & 0x78) << 1) + word_enb);
- } else {
- pg_efuse_header =
- (u8)((pg_block << 4) + word_enb);
- }
-
- if (tmp_eeprom_offset > 0x7f) {
- pg_efuse_num++;
- pg_efuse_num++;
- efuse_end = efuse_end + 2;
- for (j = 0; j < 4; j++) {
- if (((pre_word_enb >> j) & 0x1) > 0) {
- pg_efuse_num++;
- pg_efuse_num++;
- efuse_end = efuse_end + 2;
- }
- }
- } else {
- pg_efuse_num++;
- efuse_end = efuse_end + 1;
- for (j = 0; j < 4; j++) {
- if (((pre_word_enb >> j) & 0x1) > 0) {
- pg_efuse_num++;
- pg_efuse_num++;
- efuse_end = efuse_end + 2;
- }
- }
- }
- }
- }
-
- if (halmac_adapter->hw_config_info.efuse_size <=
- (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX +
- halmac_adapter->efuse_end))
- return HALMAC_RET_EFUSE_NOT_ENOUGH;
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_program_efuse_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- u8 *eeprom_mask_updated)
-{
- u8 pre_word_enb, word_enb;
- u8 pg_efuse_header, pg_efuse_header2;
- u8 pg_block;
- u16 i, j;
- u32 efuse_end;
- u32 tmp_eeprom_offset;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- efuse_end = halmac_adapter->efuse_end;
-
- for (i = 0; i < pg_efuse_info->efuse_map_size; i = i + 8) {
- tmp_eeprom_offset = i;
-
- if (((tmp_eeprom_offset >> 3) & 1) > 0) {
- pre_word_enb =
- (*(eeprom_mask_updated + (i >> 4)) & 0x0F);
- word_enb = pre_word_enb ^ 0x0F;
- } else {
- pre_word_enb = (*(eeprom_mask_updated + (i >> 4)) >> 4);
- word_enb = pre_word_enb ^ 0x0F;
- }
-
- pg_block = (u8)(tmp_eeprom_offset >> 3);
-
- if (pre_word_enb <= 0)
- continue;
-
- if (tmp_eeprom_offset > 0x7f) {
- pg_efuse_header =
- (((pg_block & 0x07) << 5) & 0xE0) | 0x0F;
- pg_efuse_header2 =
- (u8)(((pg_block & 0x78) << 1) + word_enb);
- } else {
- pg_efuse_header = (u8)((pg_block << 4) + word_enb);
- }
-
- if (tmp_eeprom_offset > 0x7f) {
- halmac_func_write_efuse_88xx(halmac_adapter, efuse_end,
- pg_efuse_header);
- status = halmac_func_write_efuse_88xx(halmac_adapter,
- efuse_end + 1,
- pg_efuse_header2);
- efuse_end = efuse_end + 2;
- for (j = 0; j < 4; j++) {
- if (((pre_word_enb >> j) & 0x1) > 0) {
- halmac_func_write_efuse_88xx(
- halmac_adapter, efuse_end,
- *(pg_efuse_info->efuse_map +
- tmp_eeprom_offset +
- (j << 1)));
- status = halmac_func_write_efuse_88xx(
- halmac_adapter, efuse_end + 1,
- *(pg_efuse_info->efuse_map +
- tmp_eeprom_offset + (j << 1) +
- 1));
- efuse_end = efuse_end + 2;
- }
- }
- } else {
- status = halmac_func_write_efuse_88xx(
- halmac_adapter, efuse_end, pg_efuse_header);
- efuse_end = efuse_end + 1;
- for (j = 0; j < 4; j++) {
- if (((pre_word_enb >> j) & 0x1) > 0) {
- halmac_func_write_efuse_88xx(
- halmac_adapter, efuse_end,
- *(pg_efuse_info->efuse_map +
- tmp_eeprom_offset +
- (j << 1)));
- status = halmac_func_write_efuse_88xx(
- halmac_adapter, efuse_end + 1,
- *(pg_efuse_info->efuse_map +
- tmp_eeprom_offset + (j << 1) +
- 1));
- efuse_end = efuse_end + 2;
- }
- }
- }
- }
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_dlfw_to_mem_88xx(struct halmac_adapter *halmac_adapter, u8 *ram_code,
- u32 dest, u32 code_size)
-{
- u8 *code_ptr;
- u8 first_part;
- u32 mem_offset;
- u32 pkt_size_tmp, send_pkt_size;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- code_ptr = ram_code;
- mem_offset = 0;
- first_part = 1;
- pkt_size_tmp = code_size;
-
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_DDMA_CH0CTRL,
- HALMAC_REG_READ_32(halmac_adapter, REG_DDMA_CH0CTRL) |
- BIT_DDMACH0_RESET_CHKSUM_STS);
-
- while (pkt_size_tmp != 0) {
- if (pkt_size_tmp >= halmac_adapter->max_download_size)
- send_pkt_size = halmac_adapter->max_download_size;
- else
- send_pkt_size = pkt_size_tmp;
-
- if (halmac_send_fwpkt_88xx(
- halmac_adapter, code_ptr + mem_offset,
- send_pkt_size) != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_fwpkt_88xx fail!!\n");
- return HALMAC_RET_DLFW_FAIL;
- }
-
- if (halmac_iddma_dlfw_88xx(
- halmac_adapter,
- HALMAC_OCPBASE_TXBUF_88XX +
- halmac_adapter->hw_config_info.txdesc_size,
- dest + mem_offset, send_pkt_size,
- first_part) != HALMAC_RET_SUCCESS) {
- pr_err("halmac_iddma_dlfw_88xx fail!!\n");
- return HALMAC_RET_DLFW_FAIL;
- }
-
- first_part = 0;
- mem_offset += send_pkt_size;
- pkt_size_tmp -= send_pkt_size;
- }
-
- if (halmac_check_fw_chksum_88xx(halmac_adapter, dest) !=
- HALMAC_RET_SUCCESS) {
- pr_err("halmac_check_fw_chksum_88xx fail!!\n");
- return HALMAC_RET_DLFW_FAIL;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_send_fwpkt_88xx(struct halmac_adapter *halmac_adapter, u8 *ram_code,
- u32 code_size)
-{
- if (halmac_download_rsvd_page_88xx(halmac_adapter, ram_code,
- code_size) != HALMAC_RET_SUCCESS) {
- pr_err("PLATFORM_SEND_RSVD_PAGE 0 error!!\n");
- return HALMAC_RET_DL_RSVD_PAGE_FAIL;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_iddma_dlfw_88xx(struct halmac_adapter *halmac_adapter, u32 source,
- u32 dest, u32 length, u8 first)
-{
- u32 counter;
- u32 ch0_control = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN);
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- counter = HALMC_DDMA_POLLING_COUNT;
- while (HALMAC_REG_READ_32(halmac_adapter, REG_DDMA_CH0CTRL) &
- BIT_DDMACH0_OWN) {
- counter--;
- if (counter == 0) {
- pr_err("%s error-1!!\n", __func__);
- return HALMAC_RET_DDMA_FAIL;
- }
- }
-
- ch0_control |= (length & BIT_MASK_DDMACH0_DLEN);
- if (first == 0)
- ch0_control |= BIT_DDMACH0_CHKSUM_CONT;
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_DDMA_CH0SA, source);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_DDMA_CH0DA, dest);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_DDMA_CH0CTRL, ch0_control);
-
- counter = HALMC_DDMA_POLLING_COUNT;
- while (HALMAC_REG_READ_32(halmac_adapter, REG_DDMA_CH0CTRL) &
- BIT_DDMACH0_OWN) {
- counter--;
- if (counter == 0) {
- pr_err("%s error-2!!\n", __func__);
- return HALMAC_RET_DDMA_FAIL;
- }
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_check_fw_chksum_88xx(struct halmac_adapter *halmac_adapter,
- u32 memory_address)
-{
- u8 mcu_fw_ctrl;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- mcu_fw_ctrl = HALMAC_REG_READ_8(halmac_adapter, REG_MCUFW_CTRL);
-
- if (HALMAC_REG_READ_32(halmac_adapter, REG_DDMA_CH0CTRL) &
- BIT_DDMACH0_CHKSUM_STS) {
- if (memory_address < HALMAC_OCPBASE_DMEM_88XX) {
- mcu_fw_ctrl |= BIT_IMEM_DW_OK;
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_MCUFW_CTRL,
- (u8)(mcu_fw_ctrl & ~(BIT_IMEM_CHKSUM_OK)));
- } else {
- mcu_fw_ctrl |= BIT_DMEM_DW_OK;
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_MCUFW_CTRL,
- (u8)(mcu_fw_ctrl & ~(BIT_DMEM_CHKSUM_OK)));
- }
-
- pr_err("%s error!!\n", __func__);
-
- status = HALMAC_RET_FW_CHECKSUM_FAIL;
- } else {
- if (memory_address < HALMAC_OCPBASE_DMEM_88XX) {
- mcu_fw_ctrl |= BIT_IMEM_DW_OK;
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_MCUFW_CTRL,
- (u8)(mcu_fw_ctrl | BIT_IMEM_CHKSUM_OK));
- } else {
- mcu_fw_ctrl |= BIT_DMEM_DW_OK;
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_MCUFW_CTRL,
- (u8)(mcu_fw_ctrl | BIT_DMEM_CHKSUM_OK));
- }
-
- status = HALMAC_RET_SUCCESS;
- }
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_dlfw_end_flow_88xx(struct halmac_adapter *halmac_adapter)
-{
- u8 value8;
- u32 counter;
- void *driver_adapter = halmac_adapter->driver_adapter;
- struct halmac_api *halmac_api =
- (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_TXDMA_STATUS, BIT(2));
-
- /* Check IMEM & DMEM checksum is OK or not */
- if ((HALMAC_REG_READ_8(halmac_adapter, REG_MCUFW_CTRL) & 0x50) == 0x50)
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MCUFW_CTRL,
- (u16)(HALMAC_REG_READ_16(halmac_adapter,
- REG_MCUFW_CTRL) |
- BIT_FW_DW_RDY));
- else
- return HALMAC_RET_DLFW_FAIL;
-
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_MCUFW_CTRL,
- (u8)(HALMAC_REG_READ_8(halmac_adapter, REG_MCUFW_CTRL) &
- ~(BIT(0))));
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_RSV_CTRL + 1);
- value8 = (u8)(value8 | BIT(0));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RSV_CTRL + 1, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_SYS_FUNC_EN + 1);
- value8 = (u8)(value8 | BIT(2));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SYS_FUNC_EN + 1,
- value8); /* Release MCU reset */
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Download Finish, Reset CPU\n");
-
- counter = 10000;
- while (HALMAC_REG_READ_16(halmac_adapter, REG_MCUFW_CTRL) != 0xC078) {
- if (counter == 0) {
- pr_err("Check 0x80 = 0xC078 fail\n");
- if ((HALMAC_REG_READ_32(halmac_adapter, REG_FW_DBG7) &
- 0xFFFFFF00) == 0xFAAAAA00)
- pr_err("Key fail\n");
- return HALMAC_RET_DLFW_FAIL;
- }
- counter--;
- usleep_range(50, 60);
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Check 0x80 = 0xC078 counter = %d\n", counter);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_free_dl_fw_end_flow_88xx(struct halmac_adapter *halmac_adapter)
-{
- u32 counter;
- struct halmac_api *halmac_api =
- (struct halmac_api *)halmac_adapter->halmac_api;
-
- counter = 100;
- while (HALMAC_REG_READ_8(halmac_adapter, REG_HMETFR + 3) != 0) {
- counter--;
- if (counter == 0) {
- pr_err("[ERR]0x1CF != 0\n");
- return HALMAC_RET_DLFW_FAIL;
- }
- usleep_range(50, 60);
- }
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_HMETFR + 3,
- ID_INFORM_DLEMEM_RDY);
-
- counter = 10000;
- while (HALMAC_REG_READ_8(halmac_adapter, REG_C2HEVT_3 + 3) !=
- ID_INFORM_DLEMEM_RDY) {
- counter--;
- if (counter == 0) {
- pr_err("[ERR]0x1AF != 0x80\n");
- return HALMAC_RET_DLFW_FAIL;
- }
- usleep_range(50, 60);
- }
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_C2HEVT_3 + 3, 0);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_pwr_seq_parser_88xx(struct halmac_adapter *halmac_adapter, u8 cut,
- u8 fab, u8 intf,
- struct halmac_wl_pwr_cfg_ **pp_pwr_seq_cfg)
-{
- u32 seq_idx = 0;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- struct halmac_wl_pwr_cfg_ *seq_cmd;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- do {
- seq_cmd = pp_pwr_seq_cfg[seq_idx];
-
- if (!seq_cmd)
- break;
-
- status = halmac_pwr_sub_seq_parer_88xx(halmac_adapter, cut, fab,
- intf, seq_cmd);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("[Err]pwr sub seq parser fail, status = 0x%X!\n",
- status);
- return status;
- }
-
- seq_idx++;
- } while (1);
-
- return status;
-}
-
-static enum halmac_ret_status
-halmac_pwr_sub_seq_parer_do_cmd_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_wl_pwr_cfg_ *sub_seq_cmd,
- bool *reti)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- u8 value, flag;
- u8 polling_bit;
- u32 polling_count;
- static u32 poll_to_static;
- u32 offset;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
- *reti = true;
-
- switch (sub_seq_cmd->cmd) {
- case HALMAC_PWR_CMD_WRITE:
- if (sub_seq_cmd->base == HALMAC_PWR_BASEADDR_SDIO)
- offset = sub_seq_cmd->offset | SDIO_LOCAL_OFFSET;
- else
- offset = sub_seq_cmd->offset;
-
- value = HALMAC_REG_READ_8(halmac_adapter, offset);
- value = (u8)(value & (u8)(~(sub_seq_cmd->msk)));
- value = (u8)(value |
- (u8)(sub_seq_cmd->value & sub_seq_cmd->msk));
-
- HALMAC_REG_WRITE_8(halmac_adapter, offset, value);
- break;
- case HALMAC_PWR_CMD_POLLING:
- polling_bit = 0;
- polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT;
- flag = 0;
-
- if (sub_seq_cmd->base == HALMAC_PWR_BASEADDR_SDIO)
- offset = sub_seq_cmd->offset | SDIO_LOCAL_OFFSET;
- else
- offset = sub_seq_cmd->offset;
-
- do {
- polling_count--;
- value = HALMAC_REG_READ_8(halmac_adapter, offset);
- value = (u8)(value & sub_seq_cmd->msk);
-
- if (value == (sub_seq_cmd->value & sub_seq_cmd->msk)) {
- polling_bit = 1;
- continue;
- }
-
- if (polling_count != 0) {
- usleep_range(50, 60);
- continue;
- }
-
- if (halmac_adapter->halmac_interface ==
- HALMAC_INTERFACE_PCIE &&
- flag == 0) {
- /* For PCIE + USB package poll power bit
- * timeout issue
- */
- poll_to_static++;
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_PWR,
- DBG_WARNING,
- "[WARN]PCIE polling timeout : %d!!\n",
- poll_to_static);
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_SYS_PW_CTRL,
- HALMAC_REG_READ_8(halmac_adapter,
- REG_SYS_PW_CTRL) |
- BIT(3));
- HALMAC_REG_WRITE_8(
- halmac_adapter, REG_SYS_PW_CTRL,
- HALMAC_REG_READ_8(halmac_adapter,
- REG_SYS_PW_CTRL) &
- ~BIT(3));
- polling_bit = 0;
- polling_count =
- HALMAC_POLLING_READY_TIMEOUT_COUNT;
- flag = 1;
- } else {
- pr_err("[ERR]Pwr cmd polling timeout!!\n");
- pr_err("[ERR]Pwr cmd offset : %X!!\n",
- sub_seq_cmd->offset);
- pr_err("[ERR]Pwr cmd value : %X!!\n",
- sub_seq_cmd->value);
- pr_err("[ERR]Pwr cmd msk : %X!!\n",
- sub_seq_cmd->msk);
- pr_err("[ERR]Read offset = %X value = %X!!\n",
- offset, value);
- return HALMAC_RET_PWRSEQ_POLLING_FAIL;
- }
- } while (!polling_bit);
- break;
- case HALMAC_PWR_CMD_DELAY:
- if (sub_seq_cmd->value == HALMAC_PWRSEQ_DELAY_US)
- udelay(sub_seq_cmd->offset);
- else
- usleep_range(1000 * sub_seq_cmd->offset,
- 1000 * sub_seq_cmd->offset + 100);
-
- break;
- case HALMAC_PWR_CMD_READ:
- break;
- case HALMAC_PWR_CMD_END:
- return HALMAC_RET_SUCCESS;
- default:
- return HALMAC_RET_PWRSEQ_CMD_INCORRECT;
- }
-
- *reti = false;
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_pwr_sub_seq_parer_88xx(struct halmac_adapter *halmac_adapter, u8 cut,
- u8 fab, u8 intf,
- struct halmac_wl_pwr_cfg_ *pwr_sub_seq_cfg)
-{
- struct halmac_wl_pwr_cfg_ *sub_seq_cmd;
- bool reti;
- enum halmac_ret_status status;
-
- for (sub_seq_cmd = pwr_sub_seq_cfg;; sub_seq_cmd++) {
- if ((sub_seq_cmd->interface_msk & intf) &&
- (sub_seq_cmd->fab_msk & fab) &&
- (sub_seq_cmd->cut_msk & cut)) {
- status = halmac_pwr_sub_seq_parer_do_cmd_88xx(
- halmac_adapter, sub_seq_cmd, &reti);
-
- if (reti)
- return status;
- }
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_get_h2c_buff_free_space_88xx(struct halmac_adapter *halmac_adapter)
-{
- u32 hw_wptr, fw_rptr;
- struct halmac_api *halmac_api =
- (struct halmac_api *)halmac_adapter->halmac_api;
-
- hw_wptr = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_PKT_WRITEADDR) &
- BIT_MASK_H2C_WR_ADDR;
- fw_rptr = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_PKT_READADDR) &
- BIT_MASK_H2C_READ_ADDR;
-
- if (hw_wptr >= fw_rptr)
- halmac_adapter->h2c_buf_free_space =
- halmac_adapter->h2c_buff_size - (hw_wptr - fw_rptr);
- else
- halmac_adapter->h2c_buf_free_space = fw_rptr - hw_wptr;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_send_h2c_pkt_88xx(struct halmac_adapter *halmac_adapter, u8 *hal_h2c_cmd,
- u32 size, bool ack)
-{
- u32 counter = 100;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- while (halmac_adapter->h2c_buf_free_space <=
- HALMAC_H2C_CMD_SIZE_UNIT_88XX) {
- halmac_get_h2c_buff_free_space_88xx(halmac_adapter);
- counter--;
- if (counter == 0) {
- pr_err("h2c free space is not enough!!\n");
- return HALMAC_RET_H2C_SPACE_FULL;
- }
- }
-
- /* Send TxDesc + H2C_CMD */
- if (!PLATFORM_SEND_H2C_PKT(driver_adapter, hal_h2c_cmd, size)) {
- pr_err("Send H2C_CMD pkt error!!\n");
- return HALMAC_RET_SEND_H2C_FAIL;
- }
-
- halmac_adapter->h2c_buf_free_space -= HALMAC_H2C_CMD_SIZE_UNIT_88XX;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "H2C free space : %d\n",
- halmac_adapter->h2c_buf_free_space);
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_download_rsvd_page_88xx(struct halmac_adapter *halmac_adapter,
- u8 *hal_buf, u32 size)
-{
- u8 restore[3];
- u8 value8;
- u32 counter;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (size == 0) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "Rsvd page packet size is zero!!\n");
- return HALMAC_RET_ZERO_LEN_RSVD_PACKET;
- }
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_FIFOPAGE_CTRL_2 + 1);
- value8 = (u8)(value8 | BIT(7));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_FIFOPAGE_CTRL_2 + 1, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR + 1);
- restore[0] = value8;
- value8 = (u8)(value8 | BIT(0));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CR + 1, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_BCN_CTRL);
- restore[1] = value8;
- value8 = (u8)((value8 & ~(BIT(3))) | BIT(4));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_BCN_CTRL, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_FWHW_TXQ_CTRL + 2);
- restore[2] = value8;
- value8 = (u8)(value8 & ~(BIT(6)));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8);
-
- if (!PLATFORM_SEND_RSVD_PAGE(driver_adapter, hal_buf, size)) {
- pr_err("PLATFORM_SEND_RSVD_PAGE 1 error!!\n");
- status = HALMAC_RET_DL_RSVD_PAGE_FAIL;
- }
-
- /* Check Bcn_Valid_Bit */
- counter = 1000;
- while (!(HALMAC_REG_READ_8(halmac_adapter, REG_FIFOPAGE_CTRL_2 + 1) &
- BIT(7))) {
- udelay(10);
- counter--;
- if (counter == 0) {
- pr_err("Polling Bcn_Valid_Fail error!!\n");
- status = HALMAC_RET_POLLING_BCN_VALID_FAIL;
- break;
- }
- }
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_FIFOPAGE_CTRL_2 + 1);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_FIFOPAGE_CTRL_2 + 1,
- (value8 | BIT(7)));
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_FWHW_TXQ_CTRL + 2, restore[2]);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_BCN_CTRL, restore[1]);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_CR + 1, restore[0]);
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_set_h2c_header_88xx(struct halmac_adapter *halmac_adapter,
- u8 *hal_h2c_hdr, u16 *seq, bool ack)
-{
- void *driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s!!\n", __func__);
-
- H2C_CMD_HEADER_SET_CATEGORY(hal_h2c_hdr, 0x00);
- H2C_CMD_HEADER_SET_TOTAL_LEN(hal_h2c_hdr, 16);
-
- spin_lock(&halmac_adapter->h2c_seq_lock);
- H2C_CMD_HEADER_SET_SEQ_NUM(hal_h2c_hdr, halmac_adapter->h2c_packet_seq);
- *seq = halmac_adapter->h2c_packet_seq;
- halmac_adapter->h2c_packet_seq++;
- spin_unlock(&halmac_adapter->h2c_seq_lock);
-
- if (ack)
- H2C_CMD_HEADER_SET_ACK(hal_h2c_hdr, 1);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_set_fw_offload_h2c_header_88xx(
- struct halmac_adapter *halmac_adapter, u8 *hal_h2c_hdr,
- struct halmac_h2c_header_info *h2c_header_info, u16 *seq_num)
-{
- void *driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s!!\n", __func__);
-
- FW_OFFLOAD_H2C_SET_TOTAL_LEN(hal_h2c_hdr,
- 8 + h2c_header_info->content_size);
- FW_OFFLOAD_H2C_SET_SUB_CMD_ID(hal_h2c_hdr, h2c_header_info->sub_cmd_id);
-
- FW_OFFLOAD_H2C_SET_CATEGORY(hal_h2c_hdr, 0x01);
- FW_OFFLOAD_H2C_SET_CMD_ID(hal_h2c_hdr, 0xFF);
-
- spin_lock(&halmac_adapter->h2c_seq_lock);
- FW_OFFLOAD_H2C_SET_SEQ_NUM(hal_h2c_hdr, halmac_adapter->h2c_packet_seq);
- *seq_num = halmac_adapter->h2c_packet_seq;
- halmac_adapter->h2c_packet_seq++;
- spin_unlock(&halmac_adapter->h2c_seq_lock);
-
- if (h2c_header_info->ack)
- FW_OFFLOAD_H2C_SET_ACK(hal_h2c_hdr, 1);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_send_h2c_set_pwr_mode_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_fwlps_option *hal_fw_lps_opt)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX];
- u8 *h2c_header, *h2c_cmd;
- u16 seq = 0;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s!!\n", __func__);
-
- h2c_header = h2c_buff;
- h2c_cmd = h2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
-
- memset(h2c_buff, 0x00, HALMAC_H2C_CMD_SIZE_88XX);
-
- SET_PWR_MODE_SET_CMD_ID(h2c_cmd, CMD_ID_SET_PWR_MODE);
- SET_PWR_MODE_SET_CLASS(h2c_cmd, CLASS_SET_PWR_MODE);
- SET_PWR_MODE_SET_MODE(h2c_cmd, hal_fw_lps_opt->mode);
- SET_PWR_MODE_SET_CLK_REQUEST(h2c_cmd, hal_fw_lps_opt->clk_request);
- SET_PWR_MODE_SET_RLBM(h2c_cmd, hal_fw_lps_opt->rlbm);
- SET_PWR_MODE_SET_SMART_PS(h2c_cmd, hal_fw_lps_opt->smart_ps);
- SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_cmd,
- hal_fw_lps_opt->awake_interval);
- SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_cmd,
- hal_fw_lps_opt->all_queue_uapsd);
- SET_PWR_MODE_SET_PWR_STATE(h2c_cmd, hal_fw_lps_opt->pwr_state);
- SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_cmd,
- hal_fw_lps_opt->ant_auto_switch);
- SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(
- h2c_cmd, hal_fw_lps_opt->ps_allow_bt_high_priority);
- SET_PWR_MODE_SET_PROTECT_BCN(h2c_cmd, hal_fw_lps_opt->protect_bcn);
- SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_cmd,
- hal_fw_lps_opt->silence_period);
- SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_cmd,
- hal_fw_lps_opt->fast_bt_connect);
- SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_cmd,
- hal_fw_lps_opt->two_antenna_en);
- SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_cmd,
- hal_fw_lps_opt->adopt_user_setting);
- SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(
- h2c_cmd, hal_fw_lps_opt->drv_bcn_early_shift);
-
- halmac_set_h2c_header_88xx(halmac_adapter, h2c_header, &seq, true);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s Fail = %x!!\n", __func__, status);
- return status;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_func_send_original_h2c_88xx(struct halmac_adapter *halmac_adapter,
- u8 *original_h2c, u16 *seq, u8 ack)
-{
- u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u8 *h2c_header, *h2c_cmd;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "halmac_send_original_h2c ==========>\n");
-
- h2c_header = H2c_buff;
- h2c_cmd = h2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
- memcpy(h2c_cmd, original_h2c, 8); /* Original H2C 8 byte */
-
- halmac_set_h2c_header_88xx(halmac_adapter, h2c_header, seq, ack);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, H2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, ack);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_original_h2c Fail = %x!!\n", status);
- return status;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "halmac_send_original_h2c <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_media_status_rpt_88xx(struct halmac_adapter *halmac_adapter, u8 op_mode,
- u8 mac_id_ind, u8 mac_id, u8 mac_id_end)
-{
- u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u8 *h2c_header, *h2c_cmd;
- u16 seq = 0;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "halmac_send_h2c_set_pwr_mode_88xx!!\n");
-
- h2c_header = H2c_buff;
- h2c_cmd = h2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
-
- memset(H2c_buff, 0x00, HALMAC_H2C_CMD_SIZE_88XX);
-
- MEDIA_STATUS_RPT_SET_CMD_ID(h2c_cmd, CMD_ID_MEDIA_STATUS_RPT);
- MEDIA_STATUS_RPT_SET_CLASS(h2c_cmd, CLASS_MEDIA_STATUS_RPT);
- MEDIA_STATUS_RPT_SET_OP_MODE(h2c_cmd, op_mode);
- MEDIA_STATUS_RPT_SET_MACID_IN(h2c_cmd, mac_id_ind);
- MEDIA_STATUS_RPT_SET_MACID(h2c_cmd, mac_id);
- MEDIA_STATUS_RPT_SET_MACID_END(h2c_cmd, mac_id_end);
-
- halmac_set_h2c_header_88xx(halmac_adapter, h2c_header, &seq, true);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, H2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s Fail = %x!!\n", __func__, status);
- return status;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_send_h2c_update_packet_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_packet_id pkt_id, u8 *pkt,
- u32 pkt_size)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation
- .rsvd_h2c_extra_info_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
-
- ret_status =
- halmac_download_rsvd_page_88xx(halmac_adapter, pkt, pkt_size);
-
- if (ret_status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_download_rsvd_page_88xx Fail = %x!!\n",
- ret_status);
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
- return ret_status;
- }
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
-
- UPDATE_PACKET_SET_SIZE(
- h2c_buff,
- pkt_size + halmac_adapter->hw_config_info.txdesc_size);
- UPDATE_PACKET_SET_PACKET_ID(h2c_buff, pkt_id);
- UPDATE_PACKET_SET_PACKET_LOC(
- h2c_buff,
- halmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy -
- halmac_adapter->txff_allocation.rsvd_pg_bndy);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PACKET;
- h2c_header_info.content_size = 8;
- h2c_header_info.ack = true;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
- halmac_adapter->halmac_state.update_packet_set.seq_num = h2c_seq_mum;
-
- ret_status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (ret_status != HALMAC_RET_SUCCESS) {
- pr_err("%s Fail = %x!!\n", __func__, ret_status);
- return ret_status;
- }
-
- return ret_status;
-}
-
-enum halmac_ret_status
-halmac_send_h2c_phy_parameter_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_phy_parameter_info *para_info,
- bool full_fifo)
-{
- bool drv_trigger_send = false;
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- u32 info_size = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- struct halmac_config_para_info *config_para_info;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
- config_para_info = &halmac_adapter->config_para_info;
-
- if (!config_para_info->cfg_para_buf) {
- if (full_fifo)
- config_para_info->para_buf_size =
- HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX;
- else
- config_para_info->para_buf_size =
- HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
-
- config_para_info->cfg_para_buf =
- kzalloc(config_para_info->para_buf_size, GFP_KERNEL);
-
- if (config_para_info->cfg_para_buf) {
- memset(config_para_info->cfg_para_buf, 0x00,
- config_para_info->para_buf_size);
- config_para_info->full_fifo_mode = full_fifo;
- config_para_info->para_buf_w =
- config_para_info->cfg_para_buf;
- config_para_info->para_num = 0;
- config_para_info->avai_para_buf_size =
- config_para_info->para_buf_size;
- config_para_info->value_accumulation = 0;
- config_para_info->offset_accumulation = 0;
- } else {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C,
- DBG_DMESG,
- "Allocate cfg_para_buf fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- }
-
- if (halmac_transition_cfg_para_state_88xx(
- halmac_adapter,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- halmac_enqueue_para_buff_88xx(halmac_adapter, para_info,
- config_para_info->para_buf_w,
- &drv_trigger_send);
-
- if (para_info->cmd_id != HALMAC_PARAMETER_CMD_END) {
- config_para_info->para_num++;
- config_para_info->para_buf_w += HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
- config_para_info->avai_para_buf_size =
- config_para_info->avai_para_buf_size -
- HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
- }
-
- if ((config_para_info->avai_para_buf_size -
- halmac_adapter->hw_config_info.txdesc_size) >
- HALMAC_FW_OFFLOAD_CMD_SIZE_88XX &&
- !drv_trigger_send)
- return HALMAC_RET_SUCCESS;
-
- if (config_para_info->para_num == 0) {
- kfree(config_para_info->cfg_para_buf);
- config_para_info->cfg_para_buf = NULL;
- config_para_info->para_buf_w = NULL;
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_WARNING,
- "no cfg parameter element!!\n");
-
- if (halmac_transition_cfg_para_state_88xx(
- halmac_adapter,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- return HALMAC_RET_SUCCESS;
- }
-
- if (halmac_transition_cfg_para_state_88xx(
- halmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- halmac_adapter->halmac_state.cfg_para_state_set.process_status =
- HALMAC_CMD_PROCESS_SENDING;
-
- if (config_para_info->full_fifo_mode)
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2, 0);
- else
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation
- .rsvd_h2c_extra_info_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
-
- info_size =
- config_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
-
- status = halmac_download_rsvd_page_88xx(
- halmac_adapter, (u8 *)config_para_info->cfg_para_buf,
- info_size);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_download_rsvd_page_88xx Fail!!\n");
- } else {
- halmac_gen_cfg_para_h2c_88xx(halmac_adapter, h2c_buff);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAMETER;
- h2c_header_info.content_size = 4;
- h2c_header_info.ack = true;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info,
- &h2c_seq_mum);
-
- halmac_adapter->halmac_state.cfg_para_state_set.seq_num =
- h2c_seq_mum;
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX,
- true);
-
- if (status != HALMAC_RET_SUCCESS)
- pr_err("halmac_send_h2c_pkt_88xx Fail!!\n");
-
- HALMAC_RT_TRACE(
- driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "config parameter time = %d\n",
- HALMAC_REG_READ_32(halmac_adapter, REG_FW_DBG6));
- }
-
- kfree(config_para_info->cfg_para_buf);
- config_para_info->cfg_para_buf = NULL;
- config_para_info->para_buf_w = NULL;
-
- /* Restore bcn head */
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
-
- if (halmac_transition_cfg_para_state_88xx(
- halmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- if (!drv_trigger_send) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "Buffer full trigger sending H2C!!\n");
- return HALMAC_RET_PARA_SENDING;
- }
-
- return status;
-}
-
-static enum halmac_ret_status
-halmac_enqueue_para_buff_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_phy_parameter_info *para_info,
- u8 *curr_buff_wptr, bool *end_cmd)
-{
- struct halmac_config_para_info *config_para_info =
- &halmac_adapter->config_para_info;
-
- *end_cmd = false;
-
- PHY_PARAMETER_INFO_SET_LENGTH(curr_buff_wptr,
- HALMAC_FW_OFFLOAD_CMD_SIZE_88XX);
- PHY_PARAMETER_INFO_SET_IO_CMD(curr_buff_wptr, para_info->cmd_id);
-
- switch (para_info->cmd_id) {
- case HALMAC_PARAMETER_CMD_BB_W8:
- case HALMAC_PARAMETER_CMD_BB_W16:
- case HALMAC_PARAMETER_CMD_BB_W32:
- case HALMAC_PARAMETER_CMD_MAC_W8:
- case HALMAC_PARAMETER_CMD_MAC_W16:
- case HALMAC_PARAMETER_CMD_MAC_W32:
- PHY_PARAMETER_INFO_SET_IO_ADDR(
- curr_buff_wptr, para_info->content.MAC_REG_W.offset);
- PHY_PARAMETER_INFO_SET_DATA(curr_buff_wptr,
- para_info->content.MAC_REG_W.value);
- PHY_PARAMETER_INFO_SET_MASK(curr_buff_wptr,
- para_info->content.MAC_REG_W.msk);
- PHY_PARAMETER_INFO_SET_MSK_EN(
- curr_buff_wptr, para_info->content.MAC_REG_W.msk_en);
- config_para_info->value_accumulation +=
- para_info->content.MAC_REG_W.value;
- config_para_info->offset_accumulation +=
- para_info->content.MAC_REG_W.offset;
- break;
- case HALMAC_PARAMETER_CMD_RF_W:
- /*In rf register, the address is only 1 byte*/
- PHY_PARAMETER_INFO_SET_RF_ADDR(
- curr_buff_wptr, para_info->content.RF_REG_W.offset);
- PHY_PARAMETER_INFO_SET_RF_PATH(
- curr_buff_wptr, para_info->content.RF_REG_W.rf_path);
- PHY_PARAMETER_INFO_SET_DATA(curr_buff_wptr,
- para_info->content.RF_REG_W.value);
- PHY_PARAMETER_INFO_SET_MASK(curr_buff_wptr,
- para_info->content.RF_REG_W.msk);
- PHY_PARAMETER_INFO_SET_MSK_EN(
- curr_buff_wptr, para_info->content.RF_REG_W.msk_en);
- config_para_info->value_accumulation +=
- para_info->content.RF_REG_W.value;
- config_para_info->offset_accumulation +=
- (para_info->content.RF_REG_W.offset +
- (para_info->content.RF_REG_W.rf_path << 8));
- break;
- case HALMAC_PARAMETER_CMD_DELAY_US:
- case HALMAC_PARAMETER_CMD_DELAY_MS:
- PHY_PARAMETER_INFO_SET_DELAY_VALUE(
- curr_buff_wptr,
- para_info->content.DELAY_TIME.delay_time);
- break;
- case HALMAC_PARAMETER_CMD_END:
- *end_cmd = true;
- break;
- default:
- pr_err(" halmac_send_h2c_phy_parameter_88xx illegal cmd_id!!\n");
- break;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_gen_cfg_para_h2c_88xx(struct halmac_adapter *halmac_adapter,
- u8 *h2c_buff)
-{
- struct halmac_config_para_info *config_para_info =
- &halmac_adapter->config_para_info;
-
- CFG_PARAMETER_SET_NUM(h2c_buff, config_para_info->para_num);
-
- if (config_para_info->full_fifo_mode) {
- CFG_PARAMETER_SET_INIT_CASE(h2c_buff, 0x1);
- CFG_PARAMETER_SET_PHY_PARAMETER_LOC(h2c_buff, 0);
- } else {
- CFG_PARAMETER_SET_INIT_CASE(h2c_buff, 0x0);
- CFG_PARAMETER_SET_PHY_PARAMETER_LOC(
- h2c_buff,
- halmac_adapter->txff_allocation
- .rsvd_h2c_extra_info_pg_bndy -
- halmac_adapter->txff_allocation.rsvd_pg_bndy);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_send_h2c_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_data_type halmac_data_type)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = NULL;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s!!\n", __func__);
-
- RUN_DATAPACK_SET_DATAPACK_ID(h2c_buff, halmac_data_type);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_RUN_DATAPACK;
- h2c_header_info.content_size = 4;
- h2c_header_info.ack = true;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_send_bt_coex_cmd_88xx(struct halmac_adapter *halmac_adapter, u8 *bt_buf,
- u32 bt_size, u8 ack)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = NULL;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s!!\n", __func__);
-
- memcpy(h2c_buff + 8, bt_buf, bt_size);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_BT_COEX;
- h2c_header_info.content_size = (u16)bt_size;
- h2c_header_info.ack = ack;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, ack);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_func_ctrl_ch_switch_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ch_switch_option *cs_option)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- enum halmac_cmd_process_status *process_status =
- &halmac_adapter->halmac_state.scan_state_set.process_status;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "halmac_ctrl_ch_switch!!\n");
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (halmac_transition_scan_state_88xx(
- halmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- *process_status = HALMAC_CMD_PROCESS_SENDING;
-
- if (cs_option->switch_en != 0) {
- HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation
- .rsvd_h2c_extra_info_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
-
- status = halmac_download_rsvd_page_88xx(
- halmac_adapter, halmac_adapter->ch_sw_info.ch_info_buf,
- halmac_adapter->ch_sw_info.total_size);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_download_rsvd_page_88xx Fail = %x!!\n",
- status);
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation
- .rsvd_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
- return status;
- }
-
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_FIFOPAGE_CTRL_2,
- (u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
- BIT_MASK_BCN_HEAD_1_V1));
- }
-
- CHANNEL_SWITCH_SET_SWITCH_START(h2c_buff, cs_option->switch_en);
- CHANNEL_SWITCH_SET_CHANNEL_NUM(h2c_buff,
- halmac_adapter->ch_sw_info.ch_num);
- CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(
- h2c_buff,
- halmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy -
- halmac_adapter->txff_allocation.rsvd_pg_bndy);
- CHANNEL_SWITCH_SET_DEST_CH_EN(h2c_buff, cs_option->dest_ch_en);
- CHANNEL_SWITCH_SET_DEST_CH(h2c_buff, cs_option->dest_ch);
- CHANNEL_SWITCH_SET_PRI_CH_IDX(h2c_buff, cs_option->dest_pri_ch_idx);
- CHANNEL_SWITCH_SET_ABSOLUTE_TIME(h2c_buff, cs_option->absolute_time_en);
- CHANNEL_SWITCH_SET_TSF_LOW(h2c_buff, cs_option->tsf_low);
- CHANNEL_SWITCH_SET_PERIODIC_OPTION(h2c_buff,
- cs_option->periodic_option);
- CHANNEL_SWITCH_SET_NORMAL_CYCLE(h2c_buff, cs_option->normal_cycle);
- CHANNEL_SWITCH_SET_NORMAL_PERIOD(h2c_buff, cs_option->normal_period);
- CHANNEL_SWITCH_SET_SLOW_PERIOD(h2c_buff, cs_option->phase_2_period);
- CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(
- h2c_buff, halmac_adapter->ch_sw_info.total_size);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_CHANNEL_SWITCH;
- h2c_header_info.content_size = 20;
- h2c_header_info.ack = true;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
- halmac_adapter->halmac_state.scan_state_set.seq_num = h2c_seq_mum;
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (status != HALMAC_RET_SUCCESS)
- pr_err("halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
-
- kfree(halmac_adapter->ch_sw_info.ch_info_buf);
- halmac_adapter->ch_sw_info.ch_info_buf = NULL;
- halmac_adapter->ch_sw_info.ch_info_buf_w = NULL;
- halmac_adapter->ch_sw_info.extra_info_en = 0;
- halmac_adapter->ch_sw_info.buf_size = 0;
- halmac_adapter->ch_sw_info.avai_buf_size = 0;
- halmac_adapter->ch_sw_info.total_size = 0;
- halmac_adapter->ch_sw_info.ch_num = 0;
-
- if (halmac_transition_scan_state_88xx(halmac_adapter,
- HALMAC_SCAN_CMD_CONSTRUCT_IDLE) !=
- HALMAC_RET_SUCCESS)
- return HALMAC_RET_ERROR_STATE;
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_func_send_general_info_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_general_info *general_info)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = NULL;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "halmac_send_general_info!!\n");
-
- GENERAL_INFO_SET_REF_TYPE(h2c_buff, general_info->rfe_type);
- GENERAL_INFO_SET_RF_TYPE(h2c_buff, general_info->rf_type);
- GENERAL_INFO_SET_FW_TX_BOUNDARY(
- h2c_buff,
- halmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy -
- halmac_adapter->txff_allocation.rsvd_pg_bndy);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO;
- h2c_header_info.content_size = 4;
- h2c_header_info.ack = false;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (status != HALMAC_RET_SUCCESS)
- pr_err("halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
-
- return status;
-}
-
-enum halmac_ret_status halmac_send_h2c_update_bcn_parse_info_88xx(
- struct halmac_adapter *halmac_adapter,
- struct halmac_bcn_ie_info *bcn_ie_info)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u16 h2c_seq_mum = 0;
- void *driver_adapter = halmac_adapter->driver_adapter;
- struct halmac_h2c_header_info h2c_header_info;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s!!\n", __func__);
-
- UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_buff, bcn_ie_info->func_en);
- UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_buff, bcn_ie_info->size_th);
- UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_buff, bcn_ie_info->timeout);
-
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(
- h2c_buff, (u32)(bcn_ie_info->ie_bmp[0]));
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(
- h2c_buff, (u32)(bcn_ie_info->ie_bmp[1]));
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(
- h2c_buff, (u32)(bcn_ie_info->ie_bmp[2]));
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(
- h2c_buff, (u32)(bcn_ie_info->ie_bmp[3]));
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(
- h2c_buff, (u32)(bcn_ie_info->ie_bmp[4]));
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO;
- h2c_header_info.content_size = 24;
- h2c_header_info.ack = true;
- halmac_set_fw_offload_h2c_header_88xx(halmac_adapter, h2c_buff,
- &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, true);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_pkt_88xx Fail =%x !!\n", status);
- return status;
- }
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_send_h2c_ps_tuning_para_88xx(struct halmac_adapter *halmac_adapter)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = {0};
- u8 *h2c_header, *h2c_cmd;
- u16 seq = 0;
- void *driver_adapter = NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "%s!!\n", __func__);
-
- h2c_header = h2c_buff;
- h2c_cmd = h2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
-
- halmac_set_h2c_header_88xx(halmac_adapter, h2c_header, &seq, false);
-
- status = halmac_send_h2c_pkt_88xx(halmac_adapter, h2c_buff,
- HALMAC_H2C_CMD_SIZE_88XX, false);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- return status;
-}
-
-enum halmac_ret_status
-halmac_parse_c2h_packet_88xx(struct halmac_adapter *halmac_adapter,
- u8 *halmac_buf, u32 halmac_size)
-{
- u8 c2h_cmd, c2h_sub_cmd_id;
- u8 *c2h_buf = halmac_buf + halmac_adapter->hw_config_info.rxdesc_size;
- u32 c2h_size = halmac_size - halmac_adapter->hw_config_info.rxdesc_size;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- c2h_cmd = (u8)C2H_HDR_GET_CMD_ID(c2h_buf);
-
- /* FW offload C2H cmd is 0xFF */
- if (c2h_cmd != 0xFF) {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "C2H_PKT not for FwOffloadC2HFormat!!\n");
- return HALMAC_RET_C2H_NOT_HANDLED;
- }
-
- /* Get C2H sub cmd ID */
- c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_buf);
-
- switch (c2h_sub_cmd_id) {
- case C2H_SUB_CMD_ID_C2H_DBG:
- status = halmac_parse_c2h_debug_88xx(halmac_adapter, c2h_buf,
- c2h_size);
- break;
- case C2H_SUB_CMD_ID_H2C_ACK_HDR:
- status = halmac_parse_h2c_ack_88xx(halmac_adapter, c2h_buf,
- c2h_size);
- break;
- case C2H_SUB_CMD_ID_BT_COEX_INFO:
- status = HALMAC_RET_C2H_NOT_HANDLED;
- break;
- case C2H_SUB_CMD_ID_SCAN_STATUS_RPT:
- status = halmac_parse_scan_status_rpt_88xx(halmac_adapter,
- c2h_buf, c2h_size);
- break;
- case C2H_SUB_CMD_ID_PSD_DATA:
- status = halmac_parse_psd_data_88xx(halmac_adapter, c2h_buf,
- c2h_size);
- break;
-
- case C2H_SUB_CMD_ID_EFUSE_DATA:
- status = halmac_parse_efuse_data_88xx(halmac_adapter, c2h_buf,
- c2h_size);
- break;
- default:
- pr_err("c2h_sub_cmd_id switch case out of boundary!!\n");
- pr_err("[ERR]c2h pkt : %.8X %.8X!!\n", *(u32 *)c2h_buf,
- *(u32 *)(c2h_buf + 4));
- status = HALMAC_RET_C2H_NOT_HANDLED;
- break;
- }
-
- return status;
-}
-
-static enum halmac_ret_status
-halmac_parse_c2h_debug_88xx(struct halmac_adapter *halmac_adapter, u8 *c2h_buf,
- u32 c2h_size)
-{
- void *driver_adapter = NULL;
- u8 *c2h_buf_local = (u8 *)NULL;
- u32 c2h_size_local = 0;
- u8 dbg_content_length = 0;
- u8 dbg_seq_num = 0;
-
- driver_adapter = halmac_adapter->driver_adapter;
- c2h_buf_local = c2h_buf;
- c2h_size_local = c2h_size;
-
- dbg_content_length = (u8)C2H_HDR_GET_LEN((u8 *)c2h_buf_local);
-
- if (dbg_content_length > C2H_DBG_CONTENT_MAX_LENGTH)
- return HALMAC_RET_SUCCESS;
-
- *(c2h_buf_local + C2H_DBG_HEADER_LENGTH + dbg_content_length - 2) =
- '\n';
- dbg_seq_num = (u8)(*(c2h_buf_local + C2H_DBG_HEADER_LENGTH));
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[RTKFW, SEQ=%d]: %s", dbg_seq_num,
- (char *)(c2h_buf_local + C2H_DBG_HEADER_LENGTH + 1));
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_scan_status_rpt_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size)
-{
- u8 h2c_return_code;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status;
-
- h2c_return_code = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_buf);
- process_status = (enum halmac_h2c_return_code)h2c_return_code ==
- HALMAC_H2C_RETURN_SUCCESS ?
- HALMAC_CMD_PROCESS_DONE :
- HALMAC_CMD_PROCESS_ERROR;
-
- PLATFORM_EVENT_INDICATION(driver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH,
- process_status, NULL, 0);
-
- halmac_adapter->halmac_state.scan_state_set.process_status =
- process_status;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]scan status : %X\n", process_status);
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_psd_data_88xx(struct halmac_adapter *halmac_adapter, u8 *c2h_buf,
- u32 c2h_size)
-{
- u8 segment_id = 0, segment_size = 0, h2c_seq = 0;
- u16 total_size;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status;
- struct halmac_psd_state_set *psd_set =
- &halmac_adapter->halmac_state.psd_set;
-
- h2c_seq = (u8)PSD_DATA_GET_H2C_SEQ(c2h_buf);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]Seq num : h2c -> %d c2h -> %d\n",
- psd_set->seq_num, h2c_seq);
- if (h2c_seq != psd_set->seq_num) {
- pr_err("[ERR]Seq num mismatch : h2c -> %d c2h -> %d\n",
- psd_set->seq_num, h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (psd_set->process_status != HALMAC_CMD_PROCESS_SENDING) {
- pr_err("[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(c2h_buf);
- segment_id = (u8)PSD_DATA_GET_SEGMENT_ID(c2h_buf);
- segment_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(c2h_buf);
- psd_set->data_size = total_size;
-
- if (!psd_set->data) {
- psd_set->data = kzalloc(psd_set->data_size, GFP_KERNEL);
- if (!psd_set->data)
- return HALMAC_RET_MALLOC_FAIL;
- }
-
- if (segment_id == 0)
- psd_set->segment_size = segment_size;
-
- memcpy(psd_set->data + segment_id * psd_set->segment_size,
- c2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size);
-
- if (!PSD_DATA_GET_END_SEGMENT(c2h_buf))
- return HALMAC_RET_SUCCESS;
-
- process_status = HALMAC_CMD_PROCESS_DONE;
- psd_set->process_status = process_status;
-
- PLATFORM_EVENT_INDICATION(driver_adapter, HALMAC_FEATURE_PSD,
- process_status, psd_set->data,
- psd_set->data_size);
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_efuse_data_88xx(struct halmac_adapter *halmac_adapter, u8 *c2h_buf,
- u32 c2h_size)
-{
- u8 segment_id = 0, segment_size = 0, h2c_seq = 0;
- u8 *eeprom_map = NULL;
- u32 eeprom_size = halmac_adapter->hw_config_info.eeprom_size;
- u8 h2c_return_code = 0;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status;
-
- h2c_seq = (u8)EFUSE_DATA_GET_H2C_SEQ(c2h_buf);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]Seq num : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.efuse_state_set.seq_num,
- h2c_seq);
- if (h2c_seq != halmac_adapter->halmac_state.efuse_state_set.seq_num) {
- pr_err("[ERR]Seq num mismatch : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.efuse_state_set.seq_num,
- h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (halmac_adapter->halmac_state.efuse_state_set.process_status !=
- HALMAC_CMD_PROCESS_SENDING) {
- pr_err("[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- segment_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(c2h_buf);
- segment_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(c2h_buf);
- if (segment_id == 0)
- halmac_adapter->efuse_segment_size = segment_size;
-
- eeprom_map = kzalloc(eeprom_size, GFP_KERNEL);
- if (!eeprom_map)
- return HALMAC_RET_MALLOC_FAIL;
- memset(eeprom_map, 0xFF, eeprom_size);
-
- spin_lock(&halmac_adapter->efuse_lock);
- memcpy(halmac_adapter->hal_efuse_map +
- segment_id * halmac_adapter->efuse_segment_size,
- c2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size);
- spin_unlock(&halmac_adapter->efuse_lock);
-
- if (!EFUSE_DATA_GET_END_SEGMENT(c2h_buf)) {
- kfree(eeprom_map);
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code =
- halmac_adapter->halmac_state.efuse_state_set.fw_return_code;
-
- if ((enum halmac_h2c_return_code)h2c_return_code ==
- HALMAC_H2C_RETURN_SUCCESS) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- halmac_adapter->halmac_state.efuse_state_set.process_status =
- process_status;
-
- spin_lock(&halmac_adapter->efuse_lock);
- halmac_adapter->hal_efuse_map_valid = true;
- spin_unlock(&halmac_adapter->efuse_lock);
-
- if (halmac_adapter->event_trigger.physical_efuse_map == 1) {
- PLATFORM_EVENT_INDICATION(
- driver_adapter,
- HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,
- process_status, halmac_adapter->hal_efuse_map,
- halmac_adapter->hw_config_info.efuse_size);
- halmac_adapter->event_trigger.physical_efuse_map = 0;
- }
-
- if (halmac_adapter->event_trigger.logical_efuse_map == 1) {
- if (halmac_eeprom_parser_88xx(
- halmac_adapter,
- halmac_adapter->hal_efuse_map,
- eeprom_map) != HALMAC_RET_SUCCESS) {
- kfree(eeprom_map);
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- }
- PLATFORM_EVENT_INDICATION(
- driver_adapter,
- HALMAC_FEATURE_DUMP_LOGICAL_EFUSE,
- process_status, eeprom_map, eeprom_size);
- halmac_adapter->event_trigger.logical_efuse_map = 0;
- }
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- halmac_adapter->halmac_state.efuse_state_set.process_status =
- process_status;
-
- if (halmac_adapter->event_trigger.physical_efuse_map == 1) {
- PLATFORM_EVENT_INDICATION(
- driver_adapter,
- HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,
- process_status,
- &halmac_adapter->halmac_state.efuse_state_set
- .fw_return_code,
- 1);
- halmac_adapter->event_trigger.physical_efuse_map = 0;
- }
-
- if (halmac_adapter->event_trigger.logical_efuse_map == 1) {
- if (halmac_eeprom_parser_88xx(
- halmac_adapter,
- halmac_adapter->hal_efuse_map,
- eeprom_map) != HALMAC_RET_SUCCESS) {
- kfree(eeprom_map);
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- }
- PLATFORM_EVENT_INDICATION(
- driver_adapter,
- HALMAC_FEATURE_DUMP_LOGICAL_EFUSE,
- process_status,
- &halmac_adapter->halmac_state.efuse_state_set
- .fw_return_code,
- 1);
- halmac_adapter->event_trigger.logical_efuse_map = 0;
- }
- }
-
- kfree(eeprom_map);
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_88xx(struct halmac_adapter *halmac_adapter, u8 *c2h_buf,
- u32 c2h_size)
-{
- u8 h2c_cmd_id, h2c_sub_cmd_id;
- u8 h2c_return_code;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "Ack for C2H!!\n");
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_buf);
- if ((enum halmac_h2c_return_code)h2c_return_code !=
- HALMAC_H2C_RETURN_SUCCESS)
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "C2H_PKT Status Error!! Status = %d\n",
- h2c_return_code);
-
- h2c_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_buf);
-
- if (h2c_cmd_id != 0xFF) {
- pr_err("original h2c ack is not handled!!\n");
- status = HALMAC_RET_C2H_NOT_HANDLED;
- } else {
- h2c_sub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_buf);
-
- switch (h2c_sub_cmd_id) {
- case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK:
- status = halmac_parse_h2c_ack_phy_efuse_88xx(
- halmac_adapter, c2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_CFG_PARAMETER_ACK:
- status = halmac_parse_h2c_ack_cfg_para_88xx(
- halmac_adapter, c2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_UPDATE_PACKET_ACK:
- status = halmac_parse_h2c_ack_update_packet_88xx(
- halmac_adapter, c2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK:
- status = halmac_parse_h2c_ack_update_datapack_88xx(
- halmac_adapter, c2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_RUN_DATAPACK_ACK:
- status = halmac_parse_h2c_ack_run_datapack_88xx(
- halmac_adapter, c2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK:
- status = halmac_parse_h2c_ack_channel_switch_88xx(
- halmac_adapter, c2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_IQK_ACK:
- status = halmac_parse_h2c_ack_iqk_88xx(
- halmac_adapter, c2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_POWER_TRACKING_ACK:
- status = halmac_parse_h2c_ack_power_tracking_88xx(
- halmac_adapter, c2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_PSD_ACK:
- break;
- default:
- pr_err("h2c_sub_cmd_id switch case out of boundary!!\n");
- status = HALMAC_RET_C2H_NOT_HANDLED;
- break;
- }
- }
-
- return status;
-}
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_phy_efuse_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- void *driver_adapter = halmac_adapter->driver_adapter;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(c2h_buf);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]Seq num : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.efuse_state_set.seq_num,
- h2c_seq);
- if (h2c_seq != halmac_adapter->halmac_state.efuse_state_set.seq_num) {
- pr_err("[ERR]Seq num mismatch : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.efuse_state_set.seq_num,
- h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (halmac_adapter->halmac_state.efuse_state_set.process_status !=
- HALMAC_CMD_PROCESS_SENDING) {
- pr_err("[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_buf);
- halmac_adapter->halmac_state.efuse_state_set.fw_return_code =
- h2c_return_code;
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_cfg_para_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- u32 offset_accu = 0, value_accu = 0;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status =
- HALMAC_CMD_PROCESS_UNDEFINE;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(c2h_buf);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "Seq num : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.cfg_para_state_set.seq_num,
- h2c_seq);
- if (h2c_seq !=
- halmac_adapter->halmac_state.cfg_para_state_set.seq_num) {
- pr_err("Seq num mismatch : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.cfg_para_state_set.seq_num,
- h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (halmac_adapter->halmac_state.cfg_para_state_set.process_status !=
- HALMAC_CMD_PROCESS_SENDING) {
- pr_err("Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_buf);
- halmac_adapter->halmac_state.cfg_para_state_set.fw_return_code =
- h2c_return_code;
- offset_accu = CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(c2h_buf);
- value_accu = CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(c2h_buf);
-
- if ((offset_accu !=
- halmac_adapter->config_para_info.offset_accumulation) ||
- (value_accu !=
- halmac_adapter->config_para_info.value_accumulation)) {
- pr_err("[C2H]offset_accu : %x, value_accu : %x!!\n",
- offset_accu, value_accu);
- pr_err("[Adapter]offset_accu : %x, value_accu : %x!!\n",
- halmac_adapter->config_para_info.offset_accumulation,
- halmac_adapter->config_para_info.value_accumulation);
- process_status = HALMAC_CMD_PROCESS_ERROR;
- }
-
- if ((enum halmac_h2c_return_code)h2c_return_code ==
- HALMAC_H2C_RETURN_SUCCESS &&
- process_status != HALMAC_CMD_PROCESS_ERROR) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- halmac_adapter->halmac_state.cfg_para_state_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(driver_adapter,
- HALMAC_FEATURE_CFG_PARA,
- process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- halmac_adapter->halmac_state.cfg_para_state_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(
- driver_adapter, HALMAC_FEATURE_CFG_PARA, process_status,
- &halmac_adapter->halmac_state.cfg_para_state_set
- .fw_return_code,
- 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_update_packet_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(c2h_buf);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]Seq num : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.update_packet_set.seq_num,
- h2c_seq);
- if (h2c_seq != halmac_adapter->halmac_state.update_packet_set.seq_num) {
- pr_err("[ERR]Seq num mismatch : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.update_packet_set.seq_num,
- h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (halmac_adapter->halmac_state.update_packet_set.process_status !=
- HALMAC_CMD_PROCESS_SENDING) {
- pr_err("[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_buf);
- halmac_adapter->halmac_state.update_packet_set.fw_return_code =
- h2c_return_code;
-
- if ((enum halmac_h2c_return_code)h2c_return_code ==
- HALMAC_H2C_RETURN_SUCCESS) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- halmac_adapter->halmac_state.update_packet_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(driver_adapter,
- HALMAC_FEATURE_UPDATE_PACKET,
- process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- halmac_adapter->halmac_state.update_packet_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(
- driver_adapter, HALMAC_FEATURE_UPDATE_PACKET,
- process_status,
- &halmac_adapter->halmac_state.update_packet_set
- .fw_return_code,
- 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_update_datapack_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size)
-{
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status =
- HALMAC_CMD_PROCESS_UNDEFINE;
-
- PLATFORM_EVENT_INDICATION(driver_adapter,
- HALMAC_FEATURE_UPDATE_DATAPACK,
- process_status, NULL, 0);
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size)
-{
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status =
- HALMAC_CMD_PROCESS_UNDEFINE;
-
- PLATFORM_EVENT_INDICATION(driver_adapter, HALMAC_FEATURE_RUN_DATAPACK,
- process_status, NULL, 0);
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_channel_switch_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(c2h_buf);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]Seq num : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.scan_state_set.seq_num,
- h2c_seq);
- if (h2c_seq != halmac_adapter->halmac_state.scan_state_set.seq_num) {
- pr_err("[ERR]Seq num misactch : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.scan_state_set.seq_num,
- h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (halmac_adapter->halmac_state.scan_state_set.process_status !=
- HALMAC_CMD_PROCESS_SENDING) {
- pr_err("[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_buf);
- halmac_adapter->halmac_state.scan_state_set.fw_return_code =
- h2c_return_code;
-
- if ((enum halmac_h2c_return_code)h2c_return_code ==
- HALMAC_H2C_RETURN_SUCCESS) {
- process_status = HALMAC_CMD_PROCESS_RCVD;
- halmac_adapter->halmac_state.scan_state_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(driver_adapter,
- HALMAC_FEATURE_CHANNEL_SWITCH,
- process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- halmac_adapter->halmac_state.scan_state_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(
- driver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH,
- process_status, &halmac_adapter->halmac_state
- .scan_state_set.fw_return_code,
- 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_iqk_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(c2h_buf);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]Seq num : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq);
- if (h2c_seq != halmac_adapter->halmac_state.iqk_set.seq_num) {
- pr_err("[ERR]Seq num misactch : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (halmac_adapter->halmac_state.iqk_set.process_status !=
- HALMAC_CMD_PROCESS_SENDING) {
- pr_err("[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_buf);
- halmac_adapter->halmac_state.iqk_set.fw_return_code = h2c_return_code;
-
- if ((enum halmac_h2c_return_code)h2c_return_code ==
- HALMAC_H2C_RETURN_SUCCESS) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- halmac_adapter->halmac_state.iqk_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(driver_adapter, HALMAC_FEATURE_IQK,
- process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- halmac_adapter->halmac_state.iqk_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(
- driver_adapter, HALMAC_FEATURE_IQK, process_status,
- &halmac_adapter->halmac_state.iqk_set.fw_return_code,
- 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_parse_h2c_ack_power_tracking_88xx(struct halmac_adapter *halmac_adapter,
- u8 *c2h_buf, u32 c2h_size)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- void *driver_adapter = halmac_adapter->driver_adapter;
- enum halmac_cmd_process_status process_status;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(c2h_buf);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_H2C, DBG_DMESG,
- "[TRACE]Seq num : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.power_tracking_set.seq_num,
- h2c_seq);
- if (h2c_seq !=
- halmac_adapter->halmac_state.power_tracking_set.seq_num) {
- pr_err("[ERR]Seq num mismatch : h2c -> %d c2h -> %d\n",
- halmac_adapter->halmac_state.power_tracking_set.seq_num,
- h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (halmac_adapter->halmac_state.power_tracking_set.process_status !=
- HALMAC_CMD_PROCESS_SENDING) {
- pr_err("[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_buf);
- halmac_adapter->halmac_state.power_tracking_set.fw_return_code =
- h2c_return_code;
-
- if ((enum halmac_h2c_return_code)h2c_return_code ==
- HALMAC_H2C_RETURN_SUCCESS) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- halmac_adapter->halmac_state.power_tracking_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(driver_adapter,
- HALMAC_FEATURE_POWER_TRACKING,
- process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- halmac_adapter->halmac_state.power_tracking_set.process_status =
- process_status;
- PLATFORM_EVENT_INDICATION(
- driver_adapter, HALMAC_FEATURE_POWER_TRACKING,
- process_status,
- &halmac_adapter->halmac_state.power_tracking_set
- .fw_return_code,
- 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_convert_to_sdio_bus_offset_88xx(struct halmac_adapter *halmac_adapter,
- u32 *halmac_offset)
-{
- void *driver_adapter = NULL;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- switch ((*halmac_offset) & 0xFFFF0000) {
- case WLAN_IOREG_OFFSET:
- *halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) |
- (*halmac_offset & HALMAC_WLAN_MAC_REG_MSK);
- break;
- case SDIO_LOCAL_OFFSET:
- *halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
- (*halmac_offset & HALMAC_SDIO_LOCAL_MSK);
- break;
- default:
- *halmac_offset = 0xFFFFFFFF;
- pr_err("Unknown base address!!\n");
- return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_update_sdio_free_page_88xx(struct halmac_adapter *halmac_adapter)
-{
- u32 free_page = 0, free_page2 = 0, free_page3 = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- struct halmac_sdio_free_space *sdio_free_space;
- u8 data[12] = {0};
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- sdio_free_space = &halmac_adapter->sdio_free_space;
- /*need to use HALMAC_REG_READ_N, 20160316, Soar*/
- HALMAC_REG_SDIO_CMD53_READ_N(halmac_adapter, REG_SDIO_FREE_TXPG, 12,
- data);
- free_page =
- data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
- free_page2 =
- data[4] | (data[5] << 8) | (data[6] << 16) | (data[7] << 24);
- free_page3 =
- data[8] | (data[9] << 8) | (data[10] << 16) | (data[11] << 24);
-
- sdio_free_space->high_queue_number =
- (u16)BIT_GET_HIQ_FREEPG_V1(free_page);
- sdio_free_space->normal_queue_number =
- (u16)BIT_GET_MID_FREEPG_V1(free_page);
- sdio_free_space->low_queue_number =
- (u16)BIT_GET_LOW_FREEPG_V1(free_page2);
- sdio_free_space->public_queue_number =
- (u16)BIT_GET_PUB_FREEPG_V1(free_page2);
- sdio_free_space->extra_queue_number =
- (u16)BIT_GET_EXQ_FREEPG_V1(free_page3);
- sdio_free_space->ac_oqt_number = (u8)((free_page3 >> 16) & 0xFF);
- sdio_free_space->non_ac_oqt_number = (u8)((free_page3 >> 24) & 0xFF);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_update_oqt_free_space_88xx(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- struct halmac_sdio_free_space *sdio_free_space;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- sdio_free_space = &halmac_adapter->sdio_free_space;
-
- sdio_free_space->ac_oqt_number = HALMAC_REG_READ_8(
- halmac_adapter, REG_SDIO_OQT_FREE_TXPG_V1 + 2);
- sdio_free_space->ac_empty =
- HALMAC_REG_READ_8(halmac_adapter, REG_TXPKT_EMPTY);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s <==========\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_efuse_cmd_construct_state
-halmac_query_efuse_curr_state_88xx(struct halmac_adapter *halmac_adapter)
-{
- return halmac_adapter->halmac_state.efuse_state_set
- .efuse_cmd_construct_state;
-}
-
-enum halmac_ret_status halmac_transition_efuse_state_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_cmd_construct_state dest_state)
-{
- struct halmac_efuse_state_set *efuse_state =
- &halmac_adapter->halmac_state.efuse_state_set;
-
- if (efuse_state->efuse_cmd_construct_state !=
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE &&
- efuse_state->efuse_cmd_construct_state !=
- HALMAC_EFUSE_CMD_CONSTRUCT_BUSY &&
- efuse_state->efuse_cmd_construct_state !=
- HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT)
- return HALMAC_RET_ERROR_STATE;
-
- if (efuse_state->efuse_cmd_construct_state == dest_state)
- return HALMAC_RET_ERROR_STATE;
-
- if (dest_state == HALMAC_EFUSE_CMD_CONSTRUCT_BUSY) {
- if (efuse_state->efuse_cmd_construct_state ==
- HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT)
- return HALMAC_RET_ERROR_STATE;
- } else if (dest_state == HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT) {
- if (efuse_state->efuse_cmd_construct_state ==
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)
- return HALMAC_RET_ERROR_STATE;
- }
-
- efuse_state->efuse_cmd_construct_state = dest_state;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_cfg_para_cmd_construct_state
-halmac_query_cfg_para_curr_state_88xx(struct halmac_adapter *halmac_adapter)
-{
- return halmac_adapter->halmac_state.cfg_para_state_set
- .cfg_para_cmd_construct_state;
-}
-
-enum halmac_ret_status halmac_transition_cfg_para_state_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cfg_para_cmd_construct_state dest_state)
-{
- struct halmac_cfg_para_state_set *cfg_para =
- &halmac_adapter->halmac_state.cfg_para_state_set;
-
- if (cfg_para->cfg_para_cmd_construct_state !=
- HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE &&
- cfg_para->cfg_para_cmd_construct_state !=
- HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING &&
- cfg_para->cfg_para_cmd_construct_state !=
- HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT)
- return HALMAC_RET_ERROR_STATE;
-
- if (dest_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE) {
- if (cfg_para->cfg_para_cmd_construct_state ==
- HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING)
- return HALMAC_RET_ERROR_STATE;
- } else if (dest_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING) {
- if (cfg_para->cfg_para_cmd_construct_state ==
- HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT)
- return HALMAC_RET_ERROR_STATE;
- } else if (dest_state == HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT) {
- if (cfg_para->cfg_para_cmd_construct_state ==
- HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE ||
- cfg_para->cfg_para_cmd_construct_state ==
- HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT)
- return HALMAC_RET_ERROR_STATE;
- }
-
- cfg_para->cfg_para_cmd_construct_state = dest_state;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_scan_cmd_construct_state
-halmac_query_scan_curr_state_88xx(struct halmac_adapter *halmac_adapter)
-{
- return halmac_adapter->halmac_state.scan_state_set
- .scan_cmd_construct_state;
-}
-
-enum halmac_ret_status halmac_transition_scan_state_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_scan_cmd_construct_state dest_state)
-{
- struct halmac_scan_state_set *scan =
- &halmac_adapter->halmac_state.scan_state_set;
-
- if (scan->scan_cmd_construct_state > HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT)
- return HALMAC_RET_ERROR_STATE;
-
- if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_IDLE) {
- if (scan->scan_cmd_construct_state ==
- HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED ||
- scan->scan_cmd_construct_state ==
- HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING)
- return HALMAC_RET_ERROR_STATE;
- } else if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED) {
- if (scan->scan_cmd_construct_state ==
- HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT)
- return HALMAC_RET_ERROR_STATE;
- } else if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING) {
- if (scan->scan_cmd_construct_state ==
- HALMAC_SCAN_CMD_CONSTRUCT_IDLE ||
- scan->scan_cmd_construct_state ==
- HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT)
- return HALMAC_RET_ERROR_STATE;
- } else if (dest_state == HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) {
- if (scan->scan_cmd_construct_state !=
- HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING &&
- scan->scan_cmd_construct_state !=
- HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED)
- return HALMAC_RET_ERROR_STATE;
- }
-
- scan->scan_cmd_construct_state = dest_state;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_query_cfg_para_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size)
-{
- struct halmac_cfg_para_state_set *cfg_para_state_set =
- &halmac_adapter->halmac_state.cfg_para_state_set;
-
- *process_status = cfg_para_state_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_query_dump_physical_efuse_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size)
-{
- void *driver_adapter = NULL;
- struct halmac_efuse_state_set *efuse_state_set =
- &halmac_adapter->halmac_state.efuse_state_set;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- *process_status = efuse_state_set->process_status;
-
- if (!data)
- return HALMAC_RET_NULL_POINTER;
-
- if (!size)
- return HALMAC_RET_NULL_POINTER;
-
- if (*process_status == HALMAC_CMD_PROCESS_DONE) {
- if (*size < halmac_adapter->hw_config_info.efuse_size) {
- *size = halmac_adapter->hw_config_info.efuse_size;
- return HALMAC_RET_BUFFER_TOO_SMALL;
- }
-
- *size = halmac_adapter->hw_config_info.efuse_size;
- memcpy(data, halmac_adapter->hal_efuse_map, *size);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_query_dump_logical_efuse_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size)
-{
- u8 *eeprom_map = NULL;
- u32 eeprom_size = halmac_adapter->hw_config_info.eeprom_size;
- void *driver_adapter = NULL;
- struct halmac_efuse_state_set *efuse_state_set =
- &halmac_adapter->halmac_state.efuse_state_set;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- *process_status = efuse_state_set->process_status;
-
- if (!data)
- return HALMAC_RET_NULL_POINTER;
-
- if (!size)
- return HALMAC_RET_NULL_POINTER;
-
- if (*process_status == HALMAC_CMD_PROCESS_DONE) {
- if (*size < eeprom_size) {
- *size = eeprom_size;
- return HALMAC_RET_BUFFER_TOO_SMALL;
- }
-
- *size = eeprom_size;
-
- eeprom_map = kzalloc(eeprom_size, GFP_KERNEL);
- if (!eeprom_map)
- return HALMAC_RET_MALLOC_FAIL;
- memset(eeprom_map, 0xFF, eeprom_size);
-
- if (halmac_eeprom_parser_88xx(
- halmac_adapter, halmac_adapter->hal_efuse_map,
- eeprom_map) != HALMAC_RET_SUCCESS) {
- kfree(eeprom_map);
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- }
-
- memcpy(data, eeprom_map, *size);
-
- kfree(eeprom_map);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_query_channel_switch_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size)
-{
- struct halmac_scan_state_set *scan_state_set =
- &halmac_adapter->halmac_state.scan_state_set;
-
- *process_status = scan_state_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_query_update_packet_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size)
-{
- struct halmac_update_packet_state_set *update_packet_set =
- &halmac_adapter->halmac_state.update_packet_set;
-
- *process_status = update_packet_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_query_iqk_status_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status,
- u8 *data, u32 *size)
-{
- struct halmac_iqk_state_set *iqk_set =
- &halmac_adapter->halmac_state.iqk_set;
-
- *process_status = iqk_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status halmac_query_power_tracking_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size)
-{
- struct halmac_power_tracking_state_set *power_tracking_state_set =
- &halmac_adapter->halmac_state.power_tracking_set;
- ;
-
- *process_status = power_tracking_state_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_query_psd_status_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status,
- u8 *data, u32 *size)
-{
- void *driver_adapter = NULL;
- struct halmac_psd_state_set *psd_set =
- &halmac_adapter->halmac_state.psd_set;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- *process_status = psd_set->process_status;
-
- if (!data)
- return HALMAC_RET_NULL_POINTER;
-
- if (!size)
- return HALMAC_RET_NULL_POINTER;
-
- if (*process_status == HALMAC_CMD_PROCESS_DONE) {
- if (*size < psd_set->data_size) {
- *size = psd_set->data_size;
- return HALMAC_RET_BUFFER_TOO_SMALL;
- }
-
- *size = psd_set->data_size;
- memcpy(data, psd_set->data, *size);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_verify_io_88xx(struct halmac_adapter *halmac_adapter)
-{
- u8 value8, wvalue8;
- u32 value32, value32_2, wvalue32;
- u32 halmac_offset;
- void *driver_adapter = NULL;
- enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- halmac_offset = REG_PAGE5_DUMMY;
- if ((halmac_offset & 0xFFFF0000) == 0)
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- ret_status = halmac_convert_to_sdio_bus_offset_88xx(
- halmac_adapter, &halmac_offset);
-
- /* Verify CMD52 R/W */
- wvalue8 = 0xab;
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
- wvalue8);
-
- value8 =
- PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
-
- if (value8 != wvalue8) {
- pr_err("cmd52 r/w fail write = %X read = %X\n", wvalue8,
- value8);
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT,
- DBG_DMESG, "cmd52 r/w ok\n");
- }
-
- /* Verify CMD53 R/W */
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset, 0xaa);
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 1,
- 0xbb);
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 2,
- 0xcc);
- PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 3,
- 0xdd);
-
- value32 = PLATFORM_SDIO_CMD53_READ_32(driver_adapter,
- halmac_offset);
-
- if (value32 != 0xddccbbaa) {
- pr_err("cmd53 r fail : read = %X\n", value32);
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT,
- DBG_DMESG, "cmd53 r ok\n");
- }
-
- wvalue32 = 0x11223344;
- PLATFORM_SDIO_CMD53_WRITE_32(driver_adapter, halmac_offset,
- wvalue32);
-
- value32 = PLATFORM_SDIO_CMD53_READ_32(driver_adapter,
- halmac_offset);
-
- if (value32 != wvalue32) {
- pr_err("cmd53 w fail\n");
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT,
- DBG_DMESG, "cmd53 w ok\n");
- }
-
- value32 = PLATFORM_SDIO_CMD53_READ_32(
- driver_adapter,
- halmac_offset + 2); /* value32 should be 0x33441122 */
-
- wvalue32 = 0x11225566;
- PLATFORM_SDIO_CMD53_WRITE_32(driver_adapter, halmac_offset,
- wvalue32);
-
- value32_2 = PLATFORM_SDIO_CMD53_READ_32(
- driver_adapter,
- halmac_offset + 2); /* value32 should be 0x55661122 */
- if (value32_2 == value32) {
- pr_err("cmd52 is used for HAL_SDIO_CMD53_READ_32\n");
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT,
- DBG_DMESG, "cmd53 is correctly used\n");
- }
- } else {
- wvalue32 = 0x77665511;
- PLATFORM_REG_WRITE_32(driver_adapter, REG_PAGE5_DUMMY,
- wvalue32);
-
- value32 = PLATFORM_REG_READ_32(driver_adapter, REG_PAGE5_DUMMY);
- if (value32 != wvalue32) {
- pr_err("reg rw\n");
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT,
- DBG_DMESG, "reg rw ok\n");
- }
- }
-
- return ret_status;
-}
-
-enum halmac_ret_status
-halmac_verify_send_rsvd_page_88xx(struct halmac_adapter *halmac_adapter)
-{
- u8 *rsvd_buf = NULL;
- u8 *rsvd_page = NULL;
- u32 i;
- u32 h2c_pkt_verify_size = 64, h2c_pkt_verify_payload = 0xab;
- void *driver_adapter = NULL;
- enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- rsvd_buf = kzalloc(h2c_pkt_verify_size, GFP_KERNEL);
-
- if (!rsvd_buf)
- return HALMAC_RET_MALLOC_FAIL;
-
- memset(rsvd_buf, (u8)h2c_pkt_verify_payload, h2c_pkt_verify_size);
-
- ret_status = halmac_download_rsvd_page_88xx(halmac_adapter, rsvd_buf,
- h2c_pkt_verify_size);
-
- if (ret_status != HALMAC_RET_SUCCESS) {
- kfree(rsvd_buf);
- return ret_status;
- }
-
- rsvd_page = kzalloc(h2c_pkt_verify_size +
- halmac_adapter->hw_config_info.txdesc_size,
- GFP_KERNEL);
-
- if (!rsvd_page) {
- kfree(rsvd_buf);
- return HALMAC_RET_MALLOC_FAIL;
- }
-
- ret_status = halmac_dump_fifo_88xx(
- halmac_adapter, HAL_FIFO_SEL_RSVD_PAGE, 0,
- h2c_pkt_verify_size +
- halmac_adapter->hw_config_info.txdesc_size,
- rsvd_page);
-
- if (ret_status != HALMAC_RET_SUCCESS) {
- kfree(rsvd_buf);
- kfree(rsvd_page);
- return ret_status;
- }
-
- for (i = 0; i < h2c_pkt_verify_size; i++) {
- if (*(rsvd_buf + i) !=
- *(rsvd_page +
- (i + halmac_adapter->hw_config_info.txdesc_size))) {
- pr_err("[ERR]Compare RSVD page Fail\n");
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- }
- }
-
- kfree(rsvd_buf);
- kfree(rsvd_page);
-
- return ret_status;
-}
-
-void halmac_power_save_cb_88xx(void *cb_data)
-{
- void *driver_adapter = NULL;
- struct halmac_adapter *halmac_adapter = (struct halmac_adapter *)NULL;
-
- halmac_adapter = (struct halmac_adapter *)cb_data;
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
- "%s\n", __func__);
-}
-
-enum halmac_ret_status
-halmac_buffer_read_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
- u32 size, enum hal_fifo_sel halmac_fifo_sel,
- u8 *fifo_map)
-{
- u32 start_page, value_read;
- u32 i, counter = 0, residue;
- struct halmac_api *halmac_api;
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (halmac_fifo_sel == HAL_FIFO_SEL_RSVD_PAGE)
- offset = offset +
- (halmac_adapter->txff_allocation.rsvd_pg_bndy << 7);
-
- start_page = offset >> 12;
- residue = offset & (4096 - 1);
-
- if (halmac_fifo_sel == HAL_FIFO_SEL_TX ||
- halmac_fifo_sel == HAL_FIFO_SEL_RSVD_PAGE)
- start_page += 0x780;
- else if (halmac_fifo_sel == HAL_FIFO_SEL_RX)
- start_page += 0x700;
- else if (halmac_fifo_sel == HAL_FIFO_SEL_REPORT)
- start_page += 0x660;
- else if (halmac_fifo_sel == HAL_FIFO_SEL_LLT)
- start_page += 0x650;
- else
- return HALMAC_RET_NOT_SUPPORT;
-
- value_read = HALMAC_REG_READ_16(halmac_adapter, REG_PKTBUF_DBG_CTRL);
-
- do {
- HALMAC_REG_WRITE_16(halmac_adapter, REG_PKTBUF_DBG_CTRL,
- (u16)(start_page | (value_read & 0xF000)));
-
- for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) {
- *(u32 *)(fifo_map + counter) =
- HALMAC_REG_READ_32(halmac_adapter, i);
- *(u32 *)(fifo_map + counter) =
- le32_to_cpu(*(__le32 *)(fifo_map + counter));
- counter += 4;
- if (size == counter)
- goto HALMAC_BUF_READ_OK;
- }
-
- residue = 0;
- start_page++;
- } while (1);
-
-HALMAC_BUF_READ_OK:
- HALMAC_REG_WRITE_16(halmac_adapter, REG_PKTBUF_DBG_CTRL,
- (u16)value_read);
-
- return HALMAC_RET_SUCCESS;
-}
-
-void halmac_restore_mac_register_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_restore_info *restore_info,
- u32 restore_num)
-{
- u8 value_length;
- u32 i;
- u32 mac_register;
- u32 mac_value;
- struct halmac_api *halmac_api;
- struct halmac_restore_info *curr_restore_info = restore_info;
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- for (i = 0; i < restore_num; i++) {
- mac_register = curr_restore_info->mac_register;
- mac_value = curr_restore_info->value;
- value_length = curr_restore_info->length;
-
- if (value_length == 1)
- HALMAC_REG_WRITE_8(halmac_adapter, mac_register,
- (u8)mac_value);
- else if (value_length == 2)
- HALMAC_REG_WRITE_16(halmac_adapter, mac_register,
- (u16)mac_value);
- else if (value_length == 4)
- HALMAC_REG_WRITE_32(halmac_adapter, mac_register,
- mac_value);
-
- curr_restore_info++;
- }
-}
-
-void halmac_api_record_id_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_api_id api_id)
-{
-}
-
-enum halmac_ret_status
-halmac_set_usb_mode_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_usb_mode usb_mode)
-{
- u32 usb_temp;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- enum halmac_usb_mode current_usb_mode;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- current_usb_mode =
- HALMAC_REG_READ_8(halmac_adapter, REG_SYS_CFG2 + 3) == 0x20 ?
- HALMAC_USB_MODE_U3 :
- HALMAC_USB_MODE_U2;
-
- /*check if HW supports usb2_usb3 swtich*/
- usb_temp = HALMAC_REG_READ_32(halmac_adapter, REG_PAD_CTRL2);
- if (!BIT_GET_USB23_SW_MODE_V1(usb_temp) &&
- !(usb_temp & BIT_USB3_USB2_TRANSITION)) {
- pr_err("HALMAC_HW_USB_MODE usb mode HW unsupport\n");
- return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT;
- }
-
- if (usb_mode == current_usb_mode) {
- pr_err("HALMAC_HW_USB_MODE usb mode unchange\n");
- return HALMAC_RET_USB_MODE_UNCHANGE;
- }
-
- usb_temp &= ~(BIT_USB23_SW_MODE_V1(0x3));
-
- if (usb_mode == HALMAC_USB_MODE_U2) {
- /* usb3 to usb2 */
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_PAD_CTRL2,
- usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) |
- BIT_RSM_EN_V1);
- } else {
- /* usb2 to usb3 */
- HALMAC_REG_WRITE_32(
- halmac_adapter, REG_PAD_CTRL2,
- usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) |
- BIT_RSM_EN_V1);
- }
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PAD_CTRL2 + 1,
- 4); /* set counter down timer 4x64 ms */
- HALMAC_REG_WRITE_16(
- halmac_adapter, REG_SYS_PW_CTRL,
- HALMAC_REG_READ_16(halmac_adapter, REG_SYS_PW_CTRL) |
- BIT_APFM_OFFMAC);
- usleep_range(1000, 1100);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_PAD_CTRL2,
- HALMAC_REG_READ_32(halmac_adapter, REG_PAD_CTRL2) |
- BIT_NO_PDN_CHIPOFF_V1);
-
- return HALMAC_RET_SUCCESS;
-}
-
-void halmac_enable_bb_rf_88xx(struct halmac_adapter *halmac_adapter, u8 enable)
-{
- u8 value8;
- u32 value32;
- struct halmac_api *halmac_api;
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (enable == 1) {
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_SYS_FUNC_EN);
- value8 = value8 | BIT(0) | BIT(1);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SYS_FUNC_EN, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_RF_CTRL);
- value8 = value8 | BIT(0) | BIT(1) | BIT(2);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RF_CTRL, value8);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_WLRF1);
- value32 = value32 | BIT(24) | BIT(25) | BIT(26);
- HALMAC_REG_WRITE_32(halmac_adapter, REG_WLRF1, value32);
- } else {
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_SYS_FUNC_EN);
- value8 = value8 & (~(BIT(0) | BIT(1)));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_SYS_FUNC_EN, value8);
-
- value8 = HALMAC_REG_READ_8(halmac_adapter, REG_RF_CTRL);
- value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2)));
- HALMAC_REG_WRITE_8(halmac_adapter, REG_RF_CTRL, value8);
-
- value32 = HALMAC_REG_READ_32(halmac_adapter, REG_WLRF1);
- value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26)));
- HALMAC_REG_WRITE_32(halmac_adapter, REG_WLRF1, value32);
- }
-}
-
-void halmac_config_sdio_tx_page_threshold_88xx(
- struct halmac_adapter *halmac_adapter,
- struct halmac_tx_page_threshold_info *threshold_info)
-{
- struct halmac_api *halmac_api;
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- switch (threshold_info->dma_queue_sel) {
- case HALMAC_MAP2_HQ:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_TQPNT1,
- threshold_info->threshold);
- break;
- case HALMAC_MAP2_NQ:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_TQPNT2,
- threshold_info->threshold);
- break;
- case HALMAC_MAP2_LQ:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_TQPNT3,
- threshold_info->threshold);
- break;
- case HALMAC_MAP2_EXQ:
- HALMAC_REG_WRITE_32(halmac_adapter, REG_TQPNT4,
- threshold_info->threshold);
- break;
- default:
- break;
- }
-}
-
-void halmac_config_ampdu_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ampdu_config *ampdu_config)
-{
- struct halmac_api *halmac_api;
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PROT_MODE_CTRL + 2,
- ampdu_config->max_agg_num);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PROT_MODE_CTRL + 3,
- ampdu_config->max_agg_num);
-};
-
-enum halmac_ret_status
-halmac_check_oqt_88xx(struct halmac_adapter *halmac_adapter, u32 tx_agg_num,
- u8 *halmac_buf)
-{
- u32 counter = 10;
-
- /*S0, S1 are not allowed to use, 0x4E4[0] should be 0. Soar 20160323*/
- /*no need to check non_ac_oqt_number. HI and MGQ blocked will cause
- *protocal issue before H_OQT being full
- */
- switch ((enum halmac_queue_select)GET_TX_DESC_QSEL(halmac_buf)) {
- case HALMAC_QUEUE_SELECT_VO:
- case HALMAC_QUEUE_SELECT_VO_V2:
- case HALMAC_QUEUE_SELECT_VI:
- case HALMAC_QUEUE_SELECT_VI_V2:
- case HALMAC_QUEUE_SELECT_BE:
- case HALMAC_QUEUE_SELECT_BE_V2:
- case HALMAC_QUEUE_SELECT_BK:
- case HALMAC_QUEUE_SELECT_BK_V2:
- counter = 10;
- do {
- if (halmac_adapter->sdio_free_space.ac_empty > 0) {
- halmac_adapter->sdio_free_space.ac_empty -= 1;
- break;
- }
-
- if (halmac_adapter->sdio_free_space.ac_oqt_number >=
- tx_agg_num) {
- halmac_adapter->sdio_free_space.ac_oqt_number -=
- (u8)tx_agg_num;
- break;
- }
-
- halmac_update_oqt_free_space_88xx(halmac_adapter);
-
- counter--;
- if (counter == 0)
- return HALMAC_RET_OQT_NOT_ENOUGH;
- } while (1);
- break;
- default:
- break;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_rqpn_parser_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode,
- struct halmac_rqpn_ *rqpn_table)
-{
- u8 search_flag;
- u32 i;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- search_flag = 0;
- for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {
- if (halmac_trx_mode == rqpn_table[i].mode) {
- halmac_adapter
- ->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] =
- rqpn_table[i].dma_map_vo;
- halmac_adapter
- ->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] =
- rqpn_table[i].dma_map_vi;
- halmac_adapter
- ->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] =
- rqpn_table[i].dma_map_be;
- halmac_adapter
- ->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] =
- rqpn_table[i].dma_map_bk;
- halmac_adapter
- ->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] =
- rqpn_table[i].dma_map_mg;
- halmac_adapter
- ->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] =
- rqpn_table[i].dma_map_hi;
- search_flag = 1;
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT,
- DBG_DMESG, "%s done\n", __func__);
- break;
- }
- }
-
- if (search_flag == 0) {
- pr_err("HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n");
- return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_pg_num_parser_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode,
- struct halmac_pg_num_ *pg_num_table)
-{
- u8 search_flag;
- u16 HPQ_num = 0, lpq_nnum = 0, NPQ_num = 0, GAPQ_num = 0;
- u16 EXPQ_num = 0, PUBQ_num = 0;
- u32 i = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- search_flag = 0;
- for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {
- if (halmac_trx_mode == pg_num_table[i].mode) {
- HPQ_num = pg_num_table[i].hq_num;
- lpq_nnum = pg_num_table[i].lq_num;
- NPQ_num = pg_num_table[i].nq_num;
- EXPQ_num = pg_num_table[i].exq_num;
- GAPQ_num = pg_num_table[i].gap_num;
- PUBQ_num = halmac_adapter->txff_allocation.ac_q_pg_num -
- HPQ_num - lpq_nnum - NPQ_num - EXPQ_num -
- GAPQ_num;
- search_flag = 1;
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT,
- DBG_DMESG, "%s done\n", __func__);
- break;
- }
- }
-
- if (search_flag == 0) {
- pr_err("HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n");
- return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
- }
-
- if (halmac_adapter->txff_allocation.ac_q_pg_num <
- HPQ_num + lpq_nnum + NPQ_num + EXPQ_num + GAPQ_num)
- return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
-
- halmac_adapter->txff_allocation.high_queue_pg_num = HPQ_num;
- halmac_adapter->txff_allocation.low_queue_pg_num = lpq_nnum;
- halmac_adapter->txff_allocation.normal_queue_pg_num = NPQ_num;
- halmac_adapter->txff_allocation.extra_queue_pg_num = EXPQ_num;
- halmac_adapter->txff_allocation.pub_queue_pg_num = PUBQ_num;
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_parse_intf_phy_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_intf_phy_para_ *intf_phy_para,
- enum halmac_intf_phy_platform platform,
- enum hal_intf_phy intf_phy)
-{
- u16 value;
- u16 curr_cut;
- u16 offset;
- u16 ip_sel;
- struct halmac_intf_phy_para_ *curr_phy_para;
- struct halmac_api *halmac_api;
- void *driver_adapter = NULL;
- u8 result = HALMAC_RET_SUCCESS;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- switch (halmac_adapter->chip_version) {
- case HALMAC_CHIP_VER_A_CUT:
- curr_cut = (u16)HALMAC_INTF_PHY_CUT_A;
- break;
- case HALMAC_CHIP_VER_B_CUT:
- curr_cut = (u16)HALMAC_INTF_PHY_CUT_B;
- break;
- case HALMAC_CHIP_VER_C_CUT:
- curr_cut = (u16)HALMAC_INTF_PHY_CUT_C;
- break;
- case HALMAC_CHIP_VER_D_CUT:
- curr_cut = (u16)HALMAC_INTF_PHY_CUT_D;
- break;
- case HALMAC_CHIP_VER_E_CUT:
- curr_cut = (u16)HALMAC_INTF_PHY_CUT_E;
- break;
- case HALMAC_CHIP_VER_F_CUT:
- curr_cut = (u16)HALMAC_INTF_PHY_CUT_F;
- break;
- case HALMAC_CHIP_VER_TEST:
- curr_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP;
- break;
- default:
- return HALMAC_RET_FAIL;
- }
-
- for (curr_phy_para = intf_phy_para;; curr_phy_para++) {
- if (!(curr_phy_para->cut & curr_cut) ||
- !(curr_phy_para->plaform & (u16)platform))
- continue;
-
- offset = curr_phy_para->offset;
- value = curr_phy_para->value;
- ip_sel = curr_phy_para->ip_sel;
-
- if (offset == 0xFFFF)
- break;
-
- if (ip_sel == HALMAC_IP_SEL_MAC) {
- HALMAC_REG_WRITE_8(halmac_adapter, (u32)offset,
- (u8)value);
- } else if (intf_phy == HAL_INTF_PHY_USB2) {
- result = halmac_usbphy_write_88xx(halmac_adapter,
- (u8)offset, value,
- HAL_INTF_PHY_USB2);
-
- if (result != HALMAC_RET_SUCCESS)
- pr_err("[ERR]Write USB2PHY fail!\n");
-
- } else if (intf_phy == HAL_INTF_PHY_USB3) {
- result = halmac_usbphy_write_88xx(halmac_adapter,
- (u8)offset, value,
- HAL_INTF_PHY_USB3);
-
- if (result != HALMAC_RET_SUCCESS)
- pr_err("[ERR]Write USB3PHY fail!\n");
-
- } else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1) {
- if (ip_sel == HALMAC_IP_SEL_INTF_PHY)
- result = halmac_mdio_write_88xx(
- halmac_adapter, (u8)offset, value,
- HAL_INTF_PHY_PCIE_GEN1);
- else
- result = halmac_dbi_write8_88xx(
- halmac_adapter, offset, (u8)value);
-
- if (result != HALMAC_RET_SUCCESS)
- pr_err("[ERR]MDIO write GEN1 fail!\n");
-
- } else if (intf_phy == HAL_INTF_PHY_PCIE_GEN2) {
- if (ip_sel == HALMAC_IP_SEL_INTF_PHY)
- result = halmac_mdio_write_88xx(
- halmac_adapter, (u8)offset, value,
- HAL_INTF_PHY_PCIE_GEN2);
- else
- result = halmac_dbi_write8_88xx(
- halmac_adapter, offset, (u8)value);
-
- if (result != HALMAC_RET_SUCCESS)
- pr_err("[ERR]MDIO write GEN2 fail!\n");
- } else {
- pr_err("[ERR]Parse intf phy cfg error!\n");
- }
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-enum halmac_ret_status
-halmac_dbi_write32_88xx(struct halmac_adapter *halmac_adapter, u16 addr,
- u32 data)
-{
- u8 tmp_u1b = 0;
- u32 count = 0;
- u16 write_addr = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_32(halmac_adapter, REG_DBI_WDATA_V1, data);
-
- write_addr = ((addr & 0x0ffc) | (0x000F << 12));
- HALMAC_REG_WRITE_16(halmac_adapter, REG_DBI_FLAG_V1, write_addr);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_DBI, DBG_DMESG,
- "WriteAddr = %x\n", write_addr);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_DBI_FLAG_V1 + 2, 0x01);
- tmp_u1b = HALMAC_REG_READ_8(halmac_adapter, REG_DBI_FLAG_V1 + 2);
-
- count = 20;
- while (tmp_u1b && count != 0) {
- udelay(10);
- tmp_u1b =
- HALMAC_REG_READ_8(halmac_adapter, REG_DBI_FLAG_V1 + 2);
- count--;
- }
-
- if (tmp_u1b) {
- pr_err("DBI write fail!\n");
- return HALMAC_RET_FAIL;
- } else {
- return HALMAC_RET_SUCCESS;
- }
-}
-
-u32 halmac_dbi_read32_88xx(struct halmac_adapter *halmac_adapter, u16 addr)
-{
- u16 read_addr = addr & 0x0ffc;
- u8 tmp_u1b = 0;
- u32 count = 0;
- u32 ret = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_DBI_FLAG_V1, read_addr);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_DBI_FLAG_V1 + 2, 0x2);
- tmp_u1b = HALMAC_REG_READ_8(halmac_adapter, REG_DBI_FLAG_V1 + 2);
-
- count = 20;
- while (tmp_u1b && count != 0) {
- udelay(10);
- tmp_u1b =
- HALMAC_REG_READ_8(halmac_adapter, REG_DBI_FLAG_V1 + 2);
- count--;
- }
-
- if (tmp_u1b) {
- ret = 0xFFFF;
- pr_err("DBI read fail!\n");
- } else {
- ret = HALMAC_REG_READ_32(halmac_adapter, REG_DBI_RDATA_V1);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_DBI, DBG_DMESG,
- "Read Value = %x\n", ret);
- }
-
- return ret;
-}
-
-enum halmac_ret_status
-halmac_dbi_write8_88xx(struct halmac_adapter *halmac_adapter, u16 addr, u8 data)
-{
- u8 tmp_u1b = 0;
- u32 count = 0;
- u16 write_addr = 0;
- u16 remainder = addr & (4 - 1);
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_DBI_WDATA_V1 + remainder, data);
-
- write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12)));
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_DBI_FLAG_V1, write_addr);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_DBI, DBG_DMESG,
- "WriteAddr = %x\n", write_addr);
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_DBI_FLAG_V1 + 2, 0x01);
-
- tmp_u1b = HALMAC_REG_READ_8(halmac_adapter, REG_DBI_FLAG_V1 + 2);
-
- count = 20;
- while (tmp_u1b && count != 0) {
- udelay(10);
- tmp_u1b =
- HALMAC_REG_READ_8(halmac_adapter, REG_DBI_FLAG_V1 + 2);
- count--;
- }
-
- if (tmp_u1b) {
- pr_err("DBI write fail!\n");
- return HALMAC_RET_FAIL;
- } else {
- return HALMAC_RET_SUCCESS;
- }
-}
-
-u8 halmac_dbi_read8_88xx(struct halmac_adapter *halmac_adapter, u16 addr)
-{
- u16 read_addr = addr & 0x0ffc;
- u8 tmp_u1b = 0;
- u32 count = 0;
- u8 ret = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_DBI_FLAG_V1, read_addr);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_DBI_FLAG_V1 + 2, 0x2);
-
- tmp_u1b = HALMAC_REG_READ_8(halmac_adapter, REG_DBI_FLAG_V1 + 2);
-
- count = 20;
- while (tmp_u1b && count != 0) {
- udelay(10);
- tmp_u1b =
- HALMAC_REG_READ_8(halmac_adapter, REG_DBI_FLAG_V1 + 2);
- count--;
- }
-
- if (tmp_u1b) {
- ret = 0xFF;
- pr_err("DBI read fail!\n");
- } else {
- ret = HALMAC_REG_READ_8(halmac_adapter,
- REG_DBI_RDATA_V1 + (addr & (4 - 1)));
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_DBI, DBG_DMESG,
- "Read Value = %x\n", ret);
- }
-
- return ret;
-}
-
-enum halmac_ret_status
-halmac_mdio_write_88xx(struct halmac_adapter *halmac_adapter, u8 addr, u16 data,
- u8 speed)
-{
- u8 tmp_u1b = 0;
- u32 count = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- u8 real_addr = 0;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_REG_WRITE_16(halmac_adapter, REG_MDIO_V1, data);
-
- /* address : 5bit */
- real_addr = (addr & 0x1F);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG, real_addr);
-
- if (speed == HAL_INTF_PHY_PCIE_GEN1) {
- /* GEN1 page 0 */
- if (addr < 0x20) {
- /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b00 */
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG + 3,
- 0x00);
-
- /* GEN1 page 1 */
- } else {
- /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b01 */
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG + 3,
- 0x01);
- }
-
- } else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
- /* GEN2 page 0 */
- if (addr < 0x20) {
- /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b10 */
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG + 3,
- 0x02);
-
- /* GEN2 page 1 */
- } else {
- /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b11 */
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG + 3,
- 0x03);
- }
- } else {
- pr_err("Error Speed !\n");
- }
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG,
- HALMAC_REG_READ_8(halmac_adapter, REG_PCIE_MIX_CFG) |
- BIT_MDIO_WFLAG_V1);
-
- tmp_u1b = HALMAC_REG_READ_8(halmac_adapter, REG_PCIE_MIX_CFG) &
- BIT_MDIO_WFLAG_V1;
- count = 20;
-
- while (tmp_u1b && count != 0) {
- udelay(10);
- tmp_u1b = HALMAC_REG_READ_8(halmac_adapter, REG_PCIE_MIX_CFG) &
- BIT_MDIO_WFLAG_V1;
- count--;
- }
-
- if (tmp_u1b) {
- pr_err("MDIO write fail!\n");
- return HALMAC_RET_FAIL;
- } else {
- return HALMAC_RET_SUCCESS;
- }
-}
-
-u16 halmac_mdio_read_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
- u8 speed
-
- )
-{
- u16 ret = 0;
- u8 tmp_u1b = 0;
- u32 count = 0;
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- u8 real_addr = 0;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- /* address : 5bit */
- real_addr = (addr & 0x1F);
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG, real_addr);
-
- if (speed == HAL_INTF_PHY_PCIE_GEN1) {
- /* GEN1 page 0 */
- if (addr < 0x20) {
- /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b00 */
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG + 3,
- 0x00);
-
- /* GEN1 page 1 */
- } else {
- /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b01 */
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG + 3,
- 0x01);
- }
-
- } else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
- /* GEN2 page 0 */
- if (addr < 0x20) {
- /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b10 */
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG + 3,
- 0x02);
-
- /* GEN2 page 1 */
- } else {
- /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b11 */
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG + 3,
- 0x03);
- }
- } else {
- pr_err("Error Speed !\n");
- }
-
- HALMAC_REG_WRITE_8(halmac_adapter, REG_PCIE_MIX_CFG,
- HALMAC_REG_READ_8(halmac_adapter, REG_PCIE_MIX_CFG) |
- BIT_MDIO_RFLAG_V1);
-
- tmp_u1b = HALMAC_REG_READ_8(halmac_adapter, REG_PCIE_MIX_CFG) &
- BIT_MDIO_RFLAG_V1;
- count = 20;
-
- while (tmp_u1b && count != 0) {
- udelay(10);
- tmp_u1b = HALMAC_REG_READ_8(halmac_adapter, REG_PCIE_MIX_CFG) &
- BIT_MDIO_RFLAG_V1;
- count--;
- }
-
- if (tmp_u1b) {
- ret = 0xFFFF;
- pr_err("MDIO read fail!\n");
-
- } else {
- ret = HALMAC_REG_READ_16(halmac_adapter, REG_MDIO_V1 + 2);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_MDIO, DBG_DMESG,
- "Read Value = %x\n", ret);
- }
-
- return ret;
-}
-
-enum halmac_ret_status
-halmac_usbphy_write_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
- u16 data, u8 speed)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (speed == HAL_INTF_PHY_USB3) {
- HALMAC_REG_WRITE_8(halmac_adapter, 0xff0d, (u8)data);
- HALMAC_REG_WRITE_8(halmac_adapter, 0xff0e, (u8)(data >> 8));
- HALMAC_REG_WRITE_8(halmac_adapter, 0xff0c, addr | BIT(7));
- } else if (speed == HAL_INTF_PHY_USB2) {
- HALMAC_REG_WRITE_8(halmac_adapter, 0xfe41, (u8)data);
- HALMAC_REG_WRITE_8(halmac_adapter, 0xfe40, addr);
- HALMAC_REG_WRITE_8(halmac_adapter, 0xfe42, 0x81);
- } else {
- pr_err("[ERR]Error USB Speed !\n");
- return HALMAC_RET_NOT_SUPPORT;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-u16 halmac_usbphy_read_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
- u8 speed)
-{
- void *driver_adapter = NULL;
- struct halmac_api *halmac_api;
- u16 value = 0;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- if (speed == HAL_INTF_PHY_USB3) {
- HALMAC_REG_WRITE_8(halmac_adapter, 0xff0c, addr | BIT(6));
- value = (u16)(HALMAC_REG_READ_32(halmac_adapter, 0xff0c) >> 8);
- } else if (speed == HAL_INTF_PHY_USB2) {
- if ((addr >= 0xE0) /*&& (addr <= 0xFF)*/)
- addr -= 0x20;
- if ((addr >= 0xC0) && (addr <= 0xDF)) {
- HALMAC_REG_WRITE_8(halmac_adapter, 0xfe40, addr);
- HALMAC_REG_WRITE_8(halmac_adapter, 0xfe42, 0x81);
- value = HALMAC_REG_READ_8(halmac_adapter, 0xfe43);
- } else {
- pr_err("[ERR]Error USB2PHY offset!\n");
- return HALMAC_RET_NOT_SUPPORT;
- }
- } else {
- pr_err("[ERR]Error USB Speed !\n");
- return HALMAC_RET_NOT_SUPPORT;
- }
-
- return value;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_FUNC_88XX_H_
-#define _HALMAC_FUNC_88XX_H_
-
-#include "../halmac_type.h"
-
-void halmac_init_offload_feature_state_machine_88xx(
- struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_send_h2c_pkt_88xx(struct halmac_adapter *halmac_adapter, u8 *hal_buff,
- u32 size, bool ack);
-
-enum halmac_ret_status
-halmac_download_rsvd_page_88xx(struct halmac_adapter *halmac_adapter,
- u8 *hal_buf, u32 size);
-
-enum halmac_ret_status
-halmac_set_h2c_header_88xx(struct halmac_adapter *halmac_adapter,
- u8 *hal_h2c_hdr, u16 *seq, bool ack);
-
-enum halmac_ret_status halmac_set_fw_offload_h2c_header_88xx(
- struct halmac_adapter *halmac_adapter, u8 *hal_h2c_hdr,
- struct halmac_h2c_header_info *h2c_header_info, u16 *seq_num);
-
-enum halmac_ret_status
-halmac_dump_efuse_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_read_cfg cfg);
-
-enum halmac_ret_status
-halmac_func_read_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
- u32 size, u8 *efuse_map);
-
-enum halmac_ret_status
-halmac_func_write_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
- u8 value);
-
-enum halmac_ret_status
-halmac_func_switch_efuse_bank_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_bank efuse_bank);
-
-enum halmac_ret_status
-halmac_read_logical_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
- u8 *map);
-
-enum halmac_ret_status
-halmac_func_write_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
- u32 offset, u8 value);
-
-enum halmac_ret_status
-halmac_func_pg_efuse_by_map_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- enum halmac_efuse_read_cfg cfg);
-
-enum halmac_ret_status
-halmac_eeprom_parser_88xx(struct halmac_adapter *halmac_adapter,
- u8 *physical_efuse_map, u8 *logical_efuse_map);
-
-enum halmac_ret_status
-halmac_read_hw_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
- u32 size, u8 *efuse_map);
-
-enum halmac_ret_status
-halmac_dlfw_to_mem_88xx(struct halmac_adapter *halmac_adapter, u8 *ram_code,
- u32 dest, u32 code_size);
-
-enum halmac_ret_status
-halmac_send_fwpkt_88xx(struct halmac_adapter *halmac_adapter, u8 *ram_code,
- u32 code_size);
-
-enum halmac_ret_status
-halmac_iddma_dlfw_88xx(struct halmac_adapter *halmac_adapter, u32 source,
- u32 dest, u32 length, u8 first);
-
-enum halmac_ret_status
-halmac_check_fw_chksum_88xx(struct halmac_adapter *halmac_adapter,
- u32 memory_address);
-
-enum halmac_ret_status
-halmac_dlfw_end_flow_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_free_dl_fw_end_flow_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_pwr_seq_parser_88xx(struct halmac_adapter *halmac_adapter, u8 cut,
- u8 fab, u8 intf,
- struct halmac_wl_pwr_cfg_ **pp_pwr_seq_cfg
-
- );
-
-enum halmac_ret_status
-halmac_get_h2c_buff_free_space_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_send_h2c_set_pwr_mode_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_fwlps_option *hal_fw_lps_opt);
-
-enum halmac_ret_status
-halmac_func_send_original_h2c_88xx(struct halmac_adapter *halmac_adapter,
- u8 *original_h2c, u16 *seq, u8 ack);
-
-enum halmac_ret_status
-halmac_media_status_rpt_88xx(struct halmac_adapter *halmac_adapter, u8 op_mode,
- u8 mac_id_ind, u8 mac_id, u8 mac_id_end);
-
-enum halmac_ret_status halmac_send_h2c_update_datapack_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_data_type halmac_data_type,
- struct halmac_phy_parameter_info *para_info);
-
-enum halmac_ret_status
-halmac_send_h2c_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_data_type halmac_data_type);
-
-enum halmac_ret_status
-halmac_send_bt_coex_cmd_88xx(struct halmac_adapter *halmac_adapter, u8 *bt_buf,
- u32 bt_size, u8 ack);
-
-enum halmac_ret_status
-halmac_func_ctrl_ch_switch_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ch_switch_option *cs_option);
-
-enum halmac_ret_status
-halmac_func_send_general_info_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_general_info *general_info);
-
-enum halmac_ret_status
-halmac_send_h2c_ps_tuning_para_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_parse_c2h_packet_88xx(struct halmac_adapter *halmac_adapter,
- u8 *halmac_buf, u32 halmac_size);
-
-enum halmac_ret_status
-halmac_send_h2c_update_packet_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_packet_id pkt_id, u8 *pkt,
- u32 pkt_size);
-
-enum halmac_ret_status
-halmac_send_h2c_phy_parameter_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_phy_parameter_info *para_info,
- bool full_fifo);
-
-enum halmac_ret_status
-halmac_dump_physical_efuse_fw_88xx(struct halmac_adapter *halmac_adapter,
- u32 offset, u32 size, u8 *efuse_map);
-
-enum halmac_ret_status halmac_send_h2c_update_bcn_parse_info_88xx(
- struct halmac_adapter *halmac_adapter,
- struct halmac_bcn_ie_info *bcn_ie_info);
-
-enum halmac_ret_status
-halmac_convert_to_sdio_bus_offset_88xx(struct halmac_adapter *halmac_adapter,
- u32 *halmac_offset);
-
-enum halmac_ret_status
-halmac_update_sdio_free_page_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_update_oqt_free_space_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_efuse_cmd_construct_state
-halmac_query_efuse_curr_state_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status halmac_transition_efuse_state_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_cmd_construct_state dest_state);
-
-enum halmac_cfg_para_cmd_construct_state
-halmac_query_cfg_para_curr_state_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status halmac_transition_cfg_para_state_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cfg_para_cmd_construct_state dest_state);
-
-enum halmac_scan_cmd_construct_state
-halmac_query_scan_curr_state_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status halmac_transition_scan_state_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_scan_cmd_construct_state dest_state);
-
-enum halmac_ret_status halmac_query_cfg_para_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
-
-enum halmac_ret_status halmac_query_dump_physical_efuse_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
-
-enum halmac_ret_status halmac_query_dump_logical_efuse_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
-
-enum halmac_ret_status halmac_query_channel_switch_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
-
-enum halmac_ret_status halmac_query_update_packet_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
-
-enum halmac_ret_status
-halmac_query_iqk_status_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status,
- u8 *data, u32 *size);
-
-enum halmac_ret_status halmac_query_power_tracking_status_88xx(
- struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
-
-enum halmac_ret_status
-halmac_query_psd_status_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_cmd_process_status *process_status,
- u8 *data, u32 *size);
-
-enum halmac_ret_status
-halmac_verify_io_88xx(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status
-halmac_verify_send_rsvd_page_88xx(struct halmac_adapter *halmac_adapter);
-
-void halmac_power_save_cb_88xx(void *cb_data);
-
-enum halmac_ret_status
-halmac_buffer_read_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
- u32 size, enum hal_fifo_sel halmac_fifo_sel,
- u8 *fifo_map);
-
-void halmac_restore_mac_register_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_restore_info *restore_info,
- u32 restore_num);
-
-void halmac_api_record_id_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_api_id api_id);
-
-enum halmac_ret_status
-halmac_set_usb_mode_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_usb_mode usb_mode);
-
-void halmac_enable_bb_rf_88xx(struct halmac_adapter *halmac_adapter, u8 enable);
-
-void halmac_config_sdio_tx_page_threshold_88xx(
- struct halmac_adapter *halmac_adapter,
- struct halmac_tx_page_threshold_info *threshold_info);
-
-enum halmac_ret_status
-halmac_rqpn_parser_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode,
- struct halmac_rqpn_ *pwr_seq_cfg);
-
-enum halmac_ret_status
-halmac_check_oqt_88xx(struct halmac_adapter *halmac_adapter, u32 tx_agg_num,
- u8 *halmac_buf);
-
-enum halmac_ret_status
-halmac_pg_num_parser_88xx(struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode halmac_trx_mode,
- struct halmac_pg_num_ *pg_num_table);
-
-enum halmac_ret_status
-halmac_parse_intf_phy_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_intf_phy_para_ *intf_phy_para,
- enum halmac_intf_phy_platform platform,
- enum hal_intf_phy intf_phy);
-
-enum halmac_ret_status
-halmac_dbi_write32_88xx(struct halmac_adapter *halmac_adapter, u16 addr,
- u32 data);
-
-u32 halmac_dbi_read32_88xx(struct halmac_adapter *halmac_adapter, u16 addr);
-
-enum halmac_ret_status
-halmac_dbi_write8_88xx(struct halmac_adapter *halmac_adapter, u16 addr,
- u8 data);
-
-u8 halmac_dbi_read8_88xx(struct halmac_adapter *halmac_adapter, u16 addr);
-
-u16 halmac_mdio_read_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
- u8 speed
-
- );
-
-enum halmac_ret_status
-halmac_mdio_write_88xx(struct halmac_adapter *halmac_adapter, u8 addr, u16 data,
- u8 speed);
-
-void halmac_config_ampdu_88xx(struct halmac_adapter *halmac_adapter,
- struct halmac_ampdu_config *ampdu_config);
-
-enum halmac_ret_status
-halmac_usbphy_write_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
- u16 data, u8 speed);
-
-u16 halmac_usbphy_read_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
- u8 speed);
-#endif /* _HALMAC_FUNC_88XX_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "halmac_2_platform.h"
-#include "halmac_type.h"
-#include "halmac_88xx/halmac_api_88xx.h"
-#include "halmac_88xx/halmac_88xx_cfg.h"
-
-#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h"
-
-static enum halmac_ret_status
-halmac_check_platform_api(void *driver_adapter,
- enum halmac_interface halmac_interface,
- struct halmac_platform_api *halmac_platform_api)
-{
- void *adapter_local = NULL;
-
- adapter_local = driver_adapter;
-
- if (!halmac_platform_api)
- return HALMAC_RET_PLATFORM_API_NULL;
-
- if (halmac_interface == HALMAC_INTERFACE_SDIO) {
- if (!halmac_platform_api->SDIO_CMD52_READ) {
- pr_err("(!halmac_platform_api->SDIO_CMD52_READ)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->SDIO_CMD53_READ_8) {
- pr_err("(!halmac_platform_api->SDIO_CMD53_READ_8)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->SDIO_CMD53_READ_16) {
- pr_err("(!halmac_platform_api->SDIO_CMD53_READ_16)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->SDIO_CMD53_READ_32) {
- pr_err("(!halmac_platform_api->SDIO_CMD53_READ_32)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->SDIO_CMD53_READ_N) {
- pr_err("(!halmac_platform_api->SDIO_CMD53_READ_N)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->SDIO_CMD52_WRITE) {
- pr_err("(!halmac_platform_api->SDIO_CMD52_WRITE)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->SDIO_CMD53_WRITE_8) {
- pr_err("(!halmac_platform_api->SDIO_CMD53_WRITE_8)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->SDIO_CMD53_WRITE_16) {
- pr_err("(!halmac_platform_api->SDIO_CMD53_WRITE_16)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->SDIO_CMD53_WRITE_32) {
- pr_err("(!halmac_platform_api->SDIO_CMD53_WRITE_32)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- }
-
- if (halmac_interface == HALMAC_INTERFACE_USB ||
- halmac_interface == HALMAC_INTERFACE_PCIE) {
- if (!halmac_platform_api->REG_READ_8) {
- pr_err("(!halmac_platform_api->REG_READ_8)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->REG_READ_16) {
- pr_err("(!halmac_platform_api->REG_READ_16)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->REG_READ_32) {
- pr_err("(!halmac_platform_api->REG_READ_32)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->REG_WRITE_8) {
- pr_err("(!halmac_platform_api->REG_WRITE_8)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->REG_WRITE_16) {
- pr_err("(!halmac_platform_api->REG_WRITE_16)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- if (!halmac_platform_api->REG_WRITE_32) {
- pr_err("(!halmac_platform_api->REG_WRITE_32)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
- }
-
- if (!halmac_platform_api->EVENT_INDICATION) {
- pr_err("(!halmac_platform_api->EVENT_INDICATION)\n");
- return HALMAC_RET_PLATFORM_API_NULL;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_convert_to_sdio_bus_offset(u32 *halmac_offset)
-{
- switch ((*halmac_offset) & 0xFFFF0000) {
- case WLAN_IOREG_OFFSET:
- *halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) |
- (*halmac_offset & HALMAC_WLAN_MAC_REG_MSK);
- break;
- case SDIO_LOCAL_OFFSET:
- *halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
- (*halmac_offset & HALMAC_SDIO_LOCAL_MSK);
- break;
- default:
- *halmac_offset = 0xFFFFFFFF;
- return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-static u8
-platform_reg_read_8_sdio(void *driver_adapter,
- struct halmac_platform_api *halmac_platform_api,
- u32 offset)
-{
- u32 halmac_offset = offset;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- if ((halmac_offset & 0xFFFF0000) == 0)
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset(&halmac_offset);
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("%s error = %x\n", __func__, status);
- return status;
- }
-
- return halmac_platform_api->SDIO_CMD52_READ(driver_adapter,
- halmac_offset);
-}
-
-static enum halmac_ret_status
-platform_reg_write_8_sdio(void *driver_adapter,
- struct halmac_platform_api *halmac_platform_api,
- u32 offset, u8 data)
-{
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
- u32 halmac_offset = offset;
-
- if ((halmac_offset & 0xFFFF0000) == 0)
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset(&halmac_offset);
-
- if (status != HALMAC_RET_SUCCESS) {
- pr_err("halmac_reg_write_8_sdio_88xx error = %x\n", status);
- return status;
- }
- halmac_platform_api->SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
- data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-static enum halmac_ret_status
-halmac_get_chip_info(void *driver_adapter,
- struct halmac_platform_api *halmac_platform_api,
- enum halmac_interface halmac_interface,
- struct halmac_adapter *halmac_adapter)
-{
- struct halmac_api *halmac_api = (struct halmac_api *)NULL;
- u8 chip_id, chip_version;
- u32 polling_count;
-
- halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- /* Get Chip_id and Chip_version */
- if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
- platform_reg_write_8_sdio(
- driver_adapter, halmac_platform_api, REG_SDIO_HSUS_CTRL,
- platform_reg_read_8_sdio(driver_adapter,
- halmac_platform_api,
- REG_SDIO_HSUS_CTRL) &
- ~(BIT(0)));
-
- polling_count = 10000;
- while (!(platform_reg_read_8_sdio(driver_adapter,
- halmac_platform_api,
- REG_SDIO_HSUS_CTRL) &
- 0x02)) {
- polling_count--;
- if (polling_count == 0)
- return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
- }
-
- chip_id = platform_reg_read_8_sdio(
- driver_adapter, halmac_platform_api, REG_SYS_CFG2);
- chip_version = platform_reg_read_8_sdio(driver_adapter,
- halmac_platform_api,
- REG_SYS_CFG1 + 1) >>
- 4;
- } else {
- chip_id = halmac_platform_api->REG_READ_8(driver_adapter,
- REG_SYS_CFG2);
- chip_version = halmac_platform_api->REG_READ_8(
- driver_adapter, REG_SYS_CFG1 + 1) >>
- 4;
- }
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]Chip id : 0x%X\n", chip_id);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]Chip version : 0x%X\n", chip_version);
-
- halmac_adapter->chip_version = (enum halmac_chip_ver)chip_version;
-
- if (chip_id == HALMAC_CHIP_ID_HW_DEF_8822B)
- halmac_adapter->chip_id = HALMAC_CHIP_ID_8822B;
- else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8821C)
- halmac_adapter->chip_id = HALMAC_CHIP_ID_8821C;
- else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8814B)
- halmac_adapter->chip_id = HALMAC_CHIP_ID_8814B;
- else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8197F)
- halmac_adapter->chip_id = HALMAC_CHIP_ID_8197F;
- else
- halmac_adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE;
-
- if (halmac_adapter->chip_id == HALMAC_CHIP_ID_UNDEFINE)
- return HALMAC_RET_CHIP_NOT_SUPPORT;
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_adapter() - init halmac_adapter
- * @driver_adapter : the adapter of caller
- * @halmac_platform_api : the platform APIs which is used in halmac APIs
- * @halmac_interface : bus interface
- * @pp_halmac_adapter : the adapter of halmac
- * @pp_halmac_api : the function pointer of APIs, caller shall call APIs by
- * function pointer
- * Author : KaiYuan Chang / Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_init_adapter(void *driver_adapter,
- struct halmac_platform_api *halmac_platform_api,
- enum halmac_interface halmac_interface,
- struct halmac_adapter **pp_halmac_adapter,
- struct halmac_api **pp_halmac_api)
-{
- struct halmac_adapter *halmac_adapter = (struct halmac_adapter *)NULL;
- enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-
- union {
- u32 i;
- u8 x[4];
- } ENDIAN_CHECK = {0x01000000};
-
- status = halmac_check_platform_api(driver_adapter, halmac_interface,
- halmac_platform_api);
- if (status != HALMAC_RET_SUCCESS)
- return status;
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- HALMAC_SVN_VER "\n");
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "HALMAC_MAJOR_VER = %x\n", HALMAC_MAJOR_VER);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "HALMAC_PROTOTYPE_VER = %x\n", HALMAC_PROTOTYPE_VER);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "HALMAC_MINOR_VER = %x\n", HALMAC_MINOR_VER);
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "HALMAC_PATCH_VER = %x\n", HALMAC_PATCH_VER);
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_init_adapter_88xx ==========>\n");
-
- /* Check endian setting - Little endian : 1, Big endian : 0*/
- if (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) {
- pr_err("Endian setting Err!!\n");
- return HALMAC_RET_ENDIAN_ERR;
- }
-
- halmac_adapter = kzalloc(sizeof(*halmac_adapter), GFP_KERNEL);
- if (!halmac_adapter) {
- /* out of memory */
- return HALMAC_RET_MALLOC_FAIL;
- }
-
- /* return halmac adapter address to caller */
- *pp_halmac_adapter = halmac_adapter;
-
- /* Record caller info */
- halmac_adapter->halmac_platform_api = halmac_platform_api;
- halmac_adapter->driver_adapter = driver_adapter;
- halmac_interface = halmac_interface == HALMAC_INTERFACE_AXI ?
- HALMAC_INTERFACE_PCIE :
- halmac_interface;
- halmac_adapter->halmac_interface = halmac_interface;
-
- spin_lock_init(&halmac_adapter->efuse_lock);
- spin_lock_init(&halmac_adapter->h2c_seq_lock);
-
- /*Get Chip*/
- if (halmac_get_chip_info(driver_adapter, halmac_platform_api,
- halmac_interface,
- halmac_adapter) != HALMAC_RET_SUCCESS) {
- pr_err("HALMAC_RET_CHIP_NOT_SUPPORT\n");
- return HALMAC_RET_CHIP_NOT_SUPPORT;
- }
-
- /* Assign function pointer to halmac API */
- halmac_init_adapter_para_88xx(halmac_adapter);
- status = halmac_mount_api_88xx(halmac_adapter);
-
- /* Return halmac API function pointer */
- *pp_halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "halmac_init_adapter_88xx <==========\n");
-
- return status;
-}
-
-/**
- * halmac_halt_api() - stop halmac_api action
- * @halmac_adapter : the adapter of halmac
- * Author : Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_halt_api(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
- struct halmac_platform_api *halmac_platform_api =
- (struct halmac_platform_api *)NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
- halmac_platform_api = halmac_adapter->halmac_platform_api;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
- halmac_adapter->halmac_state.api_state = HALMAC_API_STATE_HALT;
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "%s ==========>\n", __func__);
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_deinit_adapter() - deinit halmac adapter
- * @halmac_adapter : the adapter of halmac
- * Author : KaiYuan Chang / Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status
-halmac_deinit_adapter(struct halmac_adapter *halmac_adapter)
-{
- void *driver_adapter = NULL;
-
- if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
- return HALMAC_RET_ADAPTER_INVALID;
-
- driver_adapter = halmac_adapter->driver_adapter;
-
- HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
- "[TRACE]halmac_deinit_adapter_88xx ==========>\n");
-
- kfree(halmac_adapter->hal_efuse_map);
- halmac_adapter->hal_efuse_map = (u8 *)NULL;
-
- kfree(halmac_adapter->halmac_state.psd_set.data);
- halmac_adapter->halmac_state.psd_set.data = (u8 *)NULL;
-
- kfree(halmac_adapter->halmac_api);
- halmac_adapter->halmac_api = NULL;
-
- halmac_adapter->hal_adapter_backup = NULL;
- kfree(halmac_adapter);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_version() - get HALMAC version
- * @version : return version of major, prototype and minor information
- * Author : KaiYuan Chang / Ivan Lin
- * Return : enum halmac_ret_status
- * More details of status code can be found in prototype document
- */
-enum halmac_ret_status halmac_get_version(struct halmac_ver *version)
-{
- version->major_ver = (u8)HALMAC_MAJOR_VER;
- version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;
- version->minor_ver = (u8)HALMAC_MINOR_VER;
-
- return HALMAC_RET_SUCCESS;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_API_H_
-#define _HALMAC_API_H_
-
-#define HALMAC_SVN_VER "13348M"
-
-#define HALMAC_MAJOR_VER 0x0001 /* major version, ver_1 for async_api */
-/* For halmac_api num change or prototype change, increment prototype version.
- * Otherwise, increase minor version
- */
-#define HALMAC_PROTOTYPE_VER 0x0003 /* prototype version */
-#define HALMAC_MINOR_VER 0x0005 /* minor version */
-#define HALMAC_PATCH_VER 0x0000 /* patch version */
-
-#include "halmac_2_platform.h"
-#include "halmac_type.h"
-
-#include "halmac_usb_reg.h"
-#include "halmac_sdio_reg.h"
-
-#include "halmac_bit2.h"
-#include "halmac_reg2.h"
-
-#include "halmac_tx_desc_nic.h"
-#include "halmac_rx_desc_nic.h"
-#include "halmac_tx_bd_nic.h"
-#include "halmac_rx_bd_nic.h"
-#include "halmac_fw_offload_c2h_nic.h"
-#include "halmac_fw_offload_h2c_nic.h"
-#include "halmac_h2c_extra_info_nic.h"
-#include "halmac_original_c2h_nic.h"
-#include "halmac_original_h2c_nic.h"
-
-#include "halmac_tx_desc_chip.h"
-#include "halmac_rx_desc_chip.h"
-#include "halmac_tx_bd_chip.h"
-#include "halmac_rx_bd_chip.h"
-#include "halmac_88xx/halmac_88xx_cfg.h"
-
-#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h"
-#include "halmac_reg_8822b.h"
-#include "halmac_bit_8822b.h"
-
-enum halmac_ret_status
-halmac_init_adapter(void *driver_adapter,
- struct halmac_platform_api *halmac_platform_api,
- enum halmac_interface halmac_interface,
- struct halmac_adapter **pp_halmac_adapter,
- struct halmac_api **pp_halmac_api);
-
-enum halmac_ret_status
-halmac_deinit_adapter(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status halmac_halt_api(struct halmac_adapter *halmac_adapter);
-
-enum halmac_ret_status halmac_get_version(struct halmac_ver *version);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __RTL_WLAN_BITDEF_H__
-#define __RTL_WLAN_BITDEF_H__
-
-/*-------------------------Modification Log-----------------------------------
- * Base on MAC_Register.doc SVN391
- *-------------------------Modification Log-----------------------------------
- */
-
-/*--------------------------Include File--------------------------------------*/
-/*--------------------------Include File--------------------------------------*/
-
-/* 3 ============Programming guide Start===================== */
-/*
- * 1. For all bit define, it should be prefixed by "BIT_"
- * 2. For all bit mask, it should be prefixed by "BIT_MASK_"
- * 3. For all bit shift, it should be prefixed by "BIT_SHIFT_"
- * 4. For other case, prefix is not needed
- *
- * Example:
- * #define BIT_SHIFT_MAX_TXDMA 16
- * #define BIT_MASK_MAX_TXDMA 0x7
- * #define BIT_MAX_TXDMA(x) \
- * (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA)
- * #define BIT_GET_MAX_TXDMA(x) \
- * (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA)
- *
- */
-/* 3 ============Programming guide End===================== */
-
-#define CPU_OPT_WIDTH 0x1F
-
-#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10
-#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff
-#define BIT_WATCH_DOG_RECORD_V1(x) \
- (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1)
-#define BIT_GET_WATCH_DOG_RECORD_V1(x) \
- (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1)
-
-#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9)
-
-#define BIT_ISO_MD2PP BIT(0)
-
-#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0
-#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL
-#define BIT_R_WMAC_IPV6_MYIPAD(x) \
- (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD)
-#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) \
- (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_SHIFT_SDIO_INT_TIMEOUT 16
-#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff
-#define BIT_SDIO_INT_TIMEOUT(x) \
- (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT)
-#define BIT_GET_SDIO_INT_TIMEOUT(x) \
- (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_PWC_EV12V BIT(15)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_IO_ERR_STATUS BIT(15)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_PWC_EV25V BIT(14)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_PA33V_EN BIT(13)
-#define BIT_PA12V_EN BIT(12)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_UA33V_EN BIT(11)
-#define BIT_UA12V_EN BIT(10)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_RFDIO BIT(9)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_REPLY_ERRCRC_IN_DATA BIT(9)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_EB2CORE BIT(8)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_EN_CMD53_OVERLAP BIT(8)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_DIOE BIT(7)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_REPLY_ERR_IN_R5 BIT(7)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_WLPON2PP BIT(6)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_R18A_EN BIT(6)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_IP2MAC_WA2PP BIT(5)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_INIT_CMD_EN BIT(5)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_PD2CORE BIT(4)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_PA2PCIE BIT(3)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_UD2CORE BIT(2)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_EN_RXDMA_MASK_INT BIT(2)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_UA2USB BIT(1)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_EN_MASK_TIMER BIT(1)
-
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-
-#define BIT_ISO_WD2PP BIT(0)
-
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-
-#define BIT_CMD_ERR_STOP_INT_EN BIT(0)
-
-/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */
-
-#define BIT_FEN_MREGEN BIT(15)
-#define BIT_FEN_HWPDN BIT(14)
-
-/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */
-
-#define BIT_EN_25_1 BIT(13)
-
-/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */
-
-#define BIT_FEN_ELDR BIT(12)
-#define BIT_FEN_DCORE BIT(11)
-#define BIT_FEN_CPUEN BIT(10)
-#define BIT_FEN_DIOE BIT(9)
-#define BIT_FEN_PCIED BIT(8)
-#define BIT_FEN_PPLL BIT(7)
-#define BIT_FEN_PCIEA BIT(6)
-#define BIT_FEN_DIO_PCIE BIT(5)
-#define BIT_FEN_USBD BIT(4)
-#define BIT_FEN_UPLL BIT(3)
-#define BIT_FEN_USBA BIT(2)
-
-/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */
-
-#define BIT_FEN_BB_GLB_RSTN BIT(1)
-#define BIT_FEN_BBRSTB BIT(0)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_SOP_EABM BIT(31)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_SOP_ACKF BIT(30)
-#define BIT_SOP_ERCK BIT(29)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_SOP_ESWR BIT(28)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_SOP_PWMM BIT(27)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_SOP_EECK BIT(26)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_SOP_EXTL BIT(24)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_SYM_OP_RING_12M BIT(22)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_ROP_SWPR BIT(21)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_DIS_HW_LPLDM BIT(20)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_OPT_SWRST_WLMCU BIT(19)
-#define BIT_RDY_SYSPWR BIT(17)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_EN_WLON BIT(16)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_APDM_HPDN BIT(15)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_AFSM_PCIE_SUS_EN BIT(12)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_AFSM_WLSUS_EN BIT(11)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_APFM_SWLPS BIT(10)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_APFM_OFFMAC BIT(9)
-#define BIT_APFN_ONMAC BIT(8)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_CHIP_PDN_EN BIT(7)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_RDY_MACDIS BIT(6)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_RING_CLK_12M_EN BIT(4)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_PFM_WOWL BIT(3)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_PFM_LDKP BIT(2)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_WL_HCI_ALD BIT(1)
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_PFM_LDALL BIT(0)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_LDO_DUMMY BIT(15)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_CPU_CLK_EN BIT(14)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_SYMREG_CLK_EN BIT(13)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_HCI_CLK_EN BIT(12)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_MAC_CLK_EN BIT(11)
-#define BIT_SEC_CLK_EN BIT(10)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_PHY_SSC_RSTB BIT(9)
-#define BIT_EXT_32K_EN BIT(8)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_WL_CLK_TEST BIT(7)
-#define BIT_OP_SPS_PWM_EN BIT(6)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_LOADER_CLK_EN BIT(5)
-#define BIT_MACSLP BIT(4)
-#define BIT_WAKEPAD_EN BIT(3)
-#define BIT_ROMD16V_EN BIT(2)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_CKANA12M_EN BIT(1)
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_CNTD16V_EN BIT(0)
-
-/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
-
-#define BIT_SHIFT_VPDIDX 8
-#define BIT_MASK_VPDIDX 0xff
-#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX)
-#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX)
-
-#define BIT_SHIFT_EEM1_0 6
-#define BIT_MASK_EEM1_0 0x3
-#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0)
-#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0)
-
-#define BIT_AUTOLOAD_SUS BIT(5)
-
-/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
-
-#define BIT_EERPOMSEL BIT(4)
-
-/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
-
-#define BIT_EECS_V1 BIT(3)
-#define BIT_EESK_V1 BIT(2)
-#define BIT_EEDI_V1 BIT(1)
-#define BIT_EEDO_V1 BIT(0)
-
-/* 2 REG_EE_VPD (Offset 0x000C) */
-
-#define BIT_SHIFT_VPD_DATA 0
-#define BIT_MASK_VPD_DATA 0xffffffffL
-#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA)
-#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_C2_L_BIT0 BIT(31)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SHIFT_C1_L 29
-#define BIT_MASK_C1_L 0x3
-#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L)
-#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SHIFT_REG_FREQ_L 25
-#define BIT_MASK_REG_FREQ_L 0x7
-#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L)
-#define BIT_GET_REG_FREQ_L(x) \
- (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L)
-
-#define BIT_REG_EN_DUTY BIT(24)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SHIFT_REG_MODE 22
-#define BIT_MASK_REG_MODE 0x3
-#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE)
-#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_REG_EN_SP BIT(21)
-#define BIT_REG_AUTO_L BIT(20)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SW18_SELD_BIT0 BIT(19)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SW18_POWOCP BIT(18)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SHIFT_OCP_L1 15
-#define BIT_MASK_OCP_L1 0x7
-#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1)
-#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SHIFT_CF_L 13
-#define BIT_MASK_CF_L 0x3
-#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L)
-#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SW18_FPWM BIT(11)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SW18_SWEN BIT(9)
-#define BIT_SW18_LDEN BIT(8)
-#define BIT_MAC_ID_EN BIT(7)
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_AFE_BGEN BIT(0)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_POW_ZCD_L BIT(31)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_CRCERR_MSK BIT(31)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_AUTOZCD_L BIT(30)
-#define BIT_SDIO_HSISR3_IND_MSK BIT(30)
-#define BIT_SDIO_HSISR2_IND_MSK BIT(29)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_REG_DELAY 28
-#define BIT_MASK_REG_DELAY 0x3
-#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY)
-#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_HEISR_IND_MSK BIT(28)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_CTWEND_MSK BIT(27)
-#define BIT_SDIO_ATIMEND_E_MSK BIT(26)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIIO_ATIMEND_MSK BIT(25)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_OCPINT_MSK BIT(24)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_V15ADJ_L1_V1 24
-#define BIT_MASK_V15ADJ_L1_V1 0x7
-#define BIT_V15ADJ_L1_V1(x) \
- (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1)
-#define BIT_GET_V15ADJ_L1_V1(x) \
- (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_PSTIMEOUT_MSK BIT(23)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_GTINT4_MSK BIT(22)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_GTINT3_MSK BIT(21)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_HSISR_IND_MSK BIT(20)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_VOL_L1_V1 20
-#define BIT_MASK_VOL_L1_V1 0xf
-#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1)
-#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_CPWM2_MSK BIT(19)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_CPWM1_MSK BIT(18)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_C2HCMD_INT_MSK BIT(17)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_IN_L1_V1 17
-#define BIT_MASK_IN_L1_V1 0x7
-#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1)
-#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_BCNERLY_INT_MSK BIT(16)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_TBOX_L1 15
-#define BIT_MASK_TBOX_L1 0x3
-#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1)
-#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SW18_SEL BIT(13)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SW18_SD BIT(10)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_TXBCNERR_MSK BIT(7)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_R3_L 7
-#define BIT_MASK_R3_L 0x3
-#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L)
-#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_TXBCNOK_MSK BIT(6)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_R2 5
-#define BIT_MASK_SW18_R2 0x3
-#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2)
-#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_RXFOVW_MSK BIT(5)
-#define BIT_SDIO_TXFOVW_MSK BIT(4)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_R1 3
-#define BIT_MASK_SW18_R1 0x3
-#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1)
-#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_RXERR_MSK BIT(3)
-#define BIT_SDIO_TXERR_MSK BIT(2)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_SDIO_AVAL_MSK BIT(1)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_C3_L_C3 1
-#define BIT_MASK_C3_L_C3 0x3
-#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3)
-#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3)
-
-/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-
-#define BIT_RX_REQUEST_MSK BIT(0)
-
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_C2_L_BIT1 BIT(0)
-
-/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */
-
-#define BIT_SPS18_OCP_DIS BIT(31)
-
-/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-
-#define BIT_SDIO_CRCERR BIT(31)
-
-/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-
-#define BIT_SDIO_HSISR3_IND BIT(30)
-#define BIT_SDIO_HSISR2_IND BIT(29)
-#define BIT_SDIO_HEISR_IND BIT(28)
-
-/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-
-#define BIT_SDIO_CTWEND BIT(27)
-#define BIT_SDIO_ATIMEND_E BIT(26)
-#define BIT_SDIO_ATIMEND BIT(25)
-#define BIT_SDIO_OCPINT BIT(24)
-#define BIT_SDIO_PSTIMEOUT BIT(23)
-#define BIT_SDIO_GTINT4 BIT(22)
-#define BIT_SDIO_GTINT3 BIT(21)
-#define BIT_SDIO_HSISR_IND BIT(20)
-#define BIT_SDIO_CPWM2 BIT(19)
-#define BIT_SDIO_CPWM1 BIT(18)
-#define BIT_SDIO_C2HCMD_INT BIT(17)
-
-/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */
-
-#define BIT_SHIFT_SPS18_OCP_TH 16
-#define BIT_MASK_SPS18_OCP_TH 0x7fff
-#define BIT_SPS18_OCP_TH(x) \
- (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH)
-#define BIT_GET_SPS18_OCP_TH(x) \
- (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH)
-
-/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-
-#define BIT_SDIO_BCNERLY_INT BIT(16)
-#define BIT_SDIO_TXBCNERR BIT(7)
-#define BIT_SDIO_TXBCNOK BIT(6)
-#define BIT_SDIO_RXFOVW BIT(5)
-#define BIT_SDIO_TXFOVW BIT(4)
-#define BIT_SDIO_RXERR BIT(3)
-#define BIT_SDIO_TXERR BIT(2)
-#define BIT_SDIO_AVAL BIT(1)
-
-/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */
-
-#define BIT_SHIFT_OCP_WINDOW 0
-#define BIT_MASK_OCP_WINDOW 0xffff
-#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW)
-#define BIT_GET_OCP_WINDOW(x) \
- (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW)
-
-/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-
-#define BIT_RX_REQUEST BIT(0)
-
-/* 2 REG_RSV_CTRL (Offset 0x001C) */
-
-#define BIT_HREG_DBG BIT(23)
-
-/* 2 REG_RSV_CTRL (Offset 0x001C) */
-
-#define BIT_WLMCUIOIF BIT(8)
-
-/* 2 REG_RSV_CTRL (Offset 0x001C) */
-
-#define BIT_LOCK_ALL_EN BIT(7)
-
-/* 2 REG_RSV_CTRL (Offset 0x001C) */
-
-#define BIT_R_DIS_PRST BIT(6)
-
-/* 2 REG_RSV_CTRL (Offset 0x001C) */
-
-#define BIT_WLOCK_1C_B6 BIT(5)
-
-/* 2 REG_RSV_CTRL (Offset 0x001C) */
-
-#define BIT_WLOCK_40 BIT(4)
-#define BIT_WLOCK_08 BIT(3)
-#define BIT_WLOCK_04 BIT(2)
-#define BIT_WLOCK_00 BIT(1)
-#define BIT_WLOCK_ALL BIT(0)
-
-/* 2 REG_SDIO_RX_REQ_LEN (Offset 0x1025001C) */
-
-#define BIT_SHIFT_RX_REQ_LEN_V1 0
-#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff
-#define BIT_RX_REQ_LEN_V1(x) \
- (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1)
-#define BIT_GET_RX_REQ_LEN_V1(x) \
- (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1)
-
-/* 2 REG_RF_CTRL (Offset 0x001F) */
-
-#define BIT_RF_SDMRSTB BIT(2)
-
-/* 2 REG_RF_CTRL (Offset 0x001F) */
-
-#define BIT_RF_RSTB BIT(1)
-
-/* 2 REG_RF_CTRL (Offset 0x001F) */
-
-#define BIT_RF_EN BIT(0)
-
-/* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */
-
-#define BIT_SHIFT_FREE_TXPG_SEQ 0
-#define BIT_MASK_FREE_TXPG_SEQ 0xff
-#define BIT_FREE_TXPG_SEQ(x) \
- (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ)
-#define BIT_GET_FREE_TXPG_SEQ(x) \
- (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_SHIFT_LPLDH12_RSV 29
-#define BIT_MASK_LPLDH12_RSV 0x7
-#define BIT_LPLDH12_RSV(x) \
- (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV)
-#define BIT_GET_LPLDH12_RSV(x) \
- (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_LPLDH12_SLP BIT(28)
-
-#define BIT_SHIFT_LPLDH12_VADJ 24
-#define BIT_MASK_LPLDH12_VADJ 0xf
-#define BIT_LPLDH12_VADJ(x) \
- (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ)
-#define BIT_GET_LPLDH12_VADJ(x) \
- (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_LDH12_EN BIT(16)
-
-/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */
-
-#define BIT_SHIFT_MID_FREEPG_V1 16
-#define BIT_MASK_MID_FREEPG_V1 0xfff
-#define BIT_MID_FREEPG_V1(x) \
- (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1)
-#define BIT_GET_MID_FREEPG_V1(x) \
- (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_WLBBOFF_BIG_PWC_EN BIT(14)
-#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13)
-#define BIT_WLMACOFF_BIG_PWC_EN BIT(12)
-#define BIT_WLPON_PWC_EN BIT(11)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_POW_REGU_P1 BIT(10)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_LDOV12W_EN BIT(8)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_EX_XTAL_DRV_DIGI BIT(7)
-#define BIT_EX_XTAL_DRV_USB BIT(6)
-#define BIT_EX_XTAL_DRV_AFE BIT(5)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_EX_XTAL_DRV_RF2 BIT(4)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_EX_XTAL_DRV_RF1 BIT(3)
-#define BIT_POW_REGU_P0 BIT(2)
-
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-
-#define BIT_POW_PLL_LDO BIT(0)
-
-/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */
-
-#define BIT_SHIFT_HIQ_FREEPG_V1 0
-#define BIT_MASK_HIQ_FREEPG_V1 0xfff
-#define BIT_HIQ_FREEPG_V1(x) \
- (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1)
-#define BIT_GET_HIQ_FREEPG_V1(x) \
- (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_AGPIO_GPE BIT(31)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_CAP_XI 25
-#define BIT_MASK_XTAL_CAP_XI 0x3f
-#define BIT_XTAL_CAP_XI(x) \
- (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI)
-#define BIT_GET_XTAL_CAP_XI(x) \
- (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_DRV_DIGI 23
-#define BIT_MASK_XTAL_DRV_DIGI 0x3
-#define BIT_XTAL_DRV_DIGI(x) \
- (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI)
-#define BIT_GET_XTAL_DRV_DIGI(x) \
- (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI)
-
-#define BIT_XTAL_DRV_USB_BIT1 BIT(22)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_MAC_CLK_SEL 20
-#define BIT_MASK_MAC_CLK_SEL 0x3
-#define BIT_MAC_CLK_SEL(x) \
- (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL)
-#define BIT_GET_MAC_CLK_SEL(x) \
- (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_XTAL_DRV_USB_BIT0 BIT(19)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_DRV_AFE 17
-#define BIT_MASK_XTAL_DRV_AFE 0x3
-#define BIT_XTAL_DRV_AFE(x) \
- (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE)
-#define BIT_GET_XTAL_DRV_AFE(x) \
- (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE)
-
-/* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */
-
-#define BIT_SHIFT_PUB_FREEPG_V1 16
-#define BIT_MASK_PUB_FREEPG_V1 0xfff
-#define BIT_PUB_FREEPG_V1(x) \
- (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1)
-#define BIT_GET_PUB_FREEPG_V1(x) \
- (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_DRV_RF2 15
-#define BIT_MASK_XTAL_DRV_RF2 0x3
-#define BIT_XTAL_DRV_RF2(x) \
- (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2)
-#define BIT_GET_XTAL_DRV_RF2(x) \
- (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_DRV_RF1 13
-#define BIT_MASK_XTAL_DRV_RF1 0x3
-#define BIT_XTAL_DRV_RF1(x) \
- (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1)
-#define BIT_GET_XTAL_DRV_RF1(x) \
- (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_XTAL_DELAY_DIGI BIT(12)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_XTAL_DELAY_USB BIT(11)
-#define BIT_XTAL_DELAY_AFE BIT(10)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_LDO_VREF 7
-#define BIT_MASK_XTAL_LDO_VREF 0x7
-#define BIT_XTAL_LDO_VREF(x) \
- (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF)
-#define BIT_GET_XTAL_LDO_VREF(x) \
- (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_XTAL_XQSEL_RF BIT(6)
-#define BIT_XTAL_XQSEL BIT(5)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GMN_V2 3
-#define BIT_MASK_XTAL_GMN_V2 0x3
-#define BIT_XTAL_GMN_V2(x) \
- (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2)
-#define BIT_GET_XTAL_GMN_V2(x) \
- (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GMP_V2 1
-#define BIT_MASK_XTAL_GMP_V2 0x3
-#define BIT_XTAL_GMP_V2(x) \
- (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2)
-#define BIT_GET_XTAL_GMP_V2(x) \
- (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_XTAL_EN BIT(0)
-
-/* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */
-
-#define BIT_SHIFT_LOW_FREEPG_V1 0
-#define BIT_MASK_LOW_FREEPG_V1 0xfff
-#define BIT_LOW_FREEPG_V1(x) \
- (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1)
-#define BIT_GET_LOW_FREEPG_V1(x) \
- (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG_C3_V4 30
-#define BIT_MASK_REG_C3_V4 0x3
-#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4)
-#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4)
-
-#define BIT_REG_CP_BIT1 BIT(29)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG_RS_V4 26
-#define BIT_MASK_REG_RS_V4 0x7
-#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4)
-#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4)
-
-/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */
-
-#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24
-#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff
-#define BIT_NOAC_OQT_FREEPG_V1(x) \
- (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1)
-#define BIT_GET_NOAC_OQT_FREEPG_V1(x) \
- (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG__CS 24
-#define BIT_MASK_REG__CS 0x3
-#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS)
-#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG_CP_OFFSET 21
-#define BIT_MASK_REG_CP_OFFSET 0x7
-#define BIT_REG_CP_OFFSET(x) \
- (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET)
-#define BIT_GET_REG_CP_OFFSET(x) \
- (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_CP_BIAS 18
-#define BIT_MASK_CP_BIAS 0x7
-#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS)
-#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_REG_IDOUBLE_V2 BIT(17)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_EN_SYN BIT(16)
-
-#define BIT_SHIFT_AC_OQT_FREEPG_V1 16
-#define BIT_MASK_AC_OQT_FREEPG_V1 0xff
-#define BIT_AC_OQT_FREEPG_V1(x) \
- (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1)
-#define BIT_GET_AC_OQT_FREEPG_V1(x) \
- (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_MCCO 14
-#define BIT_MASK_MCCO 0x3
-#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO)
-#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG_LDO_SEL 12
-#define BIT_MASK_REG_LDO_SEL 0x3
-#define BIT_REG_LDO_SEL(x) \
- (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL)
-#define BIT_GET_REG_LDO_SEL(x) \
- (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL)
-
-#define BIT_REG_KVCO_V2 BIT(10)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_AGPIO_GPO BIT(9)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_AGPIO_DRV 7
-#define BIT_MASK_AGPIO_DRV 0x3
-#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV)
-#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_XTAL_CAP_XO 1
-#define BIT_MASK_XTAL_CAP_XO 0x3f
-#define BIT_XTAL_CAP_XO(x) \
- (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO)
-#define BIT_GET_XTAL_CAP_XO(x) \
- (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO)
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_POW_PLL BIT(0)
-
-/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */
-
-#define BIT_SHIFT_EXQ_FREEPG_V1 0
-#define BIT_MASK_EXQ_FREEPG_V1 0xfff
-#define BIT_EXQ_FREEPG_V1(x) \
- (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1)
-#define BIT_GET_EXQ_FREEPG_V1(x) \
- (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1)
-
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_PS 7
-#define BIT_MASK_PS 0x7
-#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS)
-#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS)
-
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_PSEN BIT(6)
-#define BIT_DOGENB BIT(5)
-
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_REG_MBIAS BIT(4)
-
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_REG_R3_V4 1
-#define BIT_MASK_REG_R3_V4 0x7
-#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4)
-#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4)
-
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_REG_CP_BIT0 BIT(0)
-
-/* 2 REG_EFUSE_CTRL (Offset 0x0030) */
-
-#define BIT_EF_FLAG BIT(31)
-
-#define BIT_SHIFT_EF_PGPD 28
-#define BIT_MASK_EF_PGPD 0x7
-#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD)
-#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD)
-
-#define BIT_SHIFT_EF_RDT 24
-#define BIT_MASK_EF_RDT 0xf
-#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT)
-#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT)
-
-#define BIT_SHIFT_EF_PGTS 20
-#define BIT_MASK_EF_PGTS 0xf
-#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS)
-#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS)
-
-/* 2 REG_EFUSE_CTRL (Offset 0x0030) */
-
-#define BIT_EF_PDWN BIT(19)
-
-/* 2 REG_EFUSE_CTRL (Offset 0x0030) */
-
-#define BIT_EF_ALDEN BIT(18)
-
-/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */
-
-#define BIT_SHIFT_HTSFR1 16
-#define BIT_MASK_HTSFR1 0xffff
-#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1)
-#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1)
-
-/* 2 REG_EFUSE_CTRL (Offset 0x0030) */
-
-#define BIT_SHIFT_EF_ADDR 8
-#define BIT_MASK_EF_ADDR 0x3ff
-#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR)
-#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR)
-
-#define BIT_SHIFT_EF_DATA 0
-#define BIT_MASK_EF_DATA 0xff
-#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA)
-#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA)
-
-/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */
-
-#define BIT_SHIFT_HTSFR0 0
-#define BIT_MASK_HTSFR0 0xffff
-#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0)
-#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0)
-
-/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_LDOE25_EN BIT(31)
-
-/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_LDOE25_V12ADJ_L 27
-#define BIT_MASK_LDOE25_V12ADJ_L 0xf
-#define BIT_LDOE25_V12ADJ_L(x) \
- (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L)
-#define BIT_GET_LDOE25_V12ADJ_L(x) \
- (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L)
-
-/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_EF_CRES_SEL BIT(26)
-
-/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_EF_SCAN_START_V1 16
-#define BIT_MASK_EF_SCAN_START_V1 0x3ff
-#define BIT_EF_SCAN_START_V1(x) \
- (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1)
-#define BIT_GET_EF_SCAN_START_V1(x) \
- (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1)
-
-/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_EF_SCAN_END 12
-#define BIT_MASK_EF_SCAN_END 0xf
-#define BIT_EF_SCAN_END(x) \
- (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END)
-#define BIT_GET_EF_SCAN_END(x) \
- (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END)
-
-/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_EF_PD_DIS BIT(11)
-
-/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_EF_CELL_SEL 8
-#define BIT_MASK_EF_CELL_SEL 0x3
-#define BIT_EF_CELL_SEL(x) \
- (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL)
-#define BIT_GET_EF_CELL_SEL(x) \
- (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL)
-
-/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_EF_TRPT BIT(7)
-
-#define BIT_SHIFT_EF_TTHD 0
-#define BIT_MASK_EF_TTHD 0x7f
-#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD)
-#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SHIFT_DBG_SEL_V1 16
-#define BIT_MASK_DBG_SEL_V1 0xff
-#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1)
-#define BIT_GET_DBG_SEL_V1(x) \
- (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SHIFT_DBG_SEL_BYTE 14
-#define BIT_MASK_DBG_SEL_BYTE 0x3
-#define BIT_DBG_SEL_BYTE(x) \
- (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE)
-#define BIT_GET_DBG_SEL_BYTE(x) \
- (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SHIFT_STD_L1_V1 12
-#define BIT_MASK_STD_L1_V1 0x3
-#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1)
-#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SYSON_DBG_PAD_E2 BIT(11)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SYSON_LED_PAD_E2 BIT(10)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SYSON_GPEE_PAD_E2 BIT(9)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SYSON_PCI_PAD_E2 BIT(8)
-
-#define BIT_SHIFT_MATCH_CNT 8
-#define BIT_MASK_MATCH_CNT 0xff
-#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT)
-#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_AUTO_SW_LDO_VOL_EN BIT(7)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SHIFT_SYSON_SPS0WWV_WT 4
-#define BIT_MASK_SYSON_SPS0WWV_WT 0x3
-#define BIT_SYSON_SPS0WWV_WT(x) \
- (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT)
-#define BIT_GET_SYSON_SPS0WWV_WT(x) \
- (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SHIFT_SYSON_SPS0LDO_WT 2
-#define BIT_MASK_SYSON_SPS0LDO_WT 0x3
-#define BIT_SYSON_SPS0LDO_WT(x) \
- (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT)
-#define BIT_GET_SYSON_SPS0LDO_WT(x) \
- (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT)
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-
-#define BIT_SHIFT_SYSON_RCLK_SCALE 0
-#define BIT_MASK_SYSON_RCLK_SCALE 0x3
-#define BIT_SYSON_RCLK_SCALE(x) \
- (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE)
-#define BIT_GET_SYSON_RCLK_SCALE(x) \
- (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE)
-
-/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */
-
-#define BIT_SYS_CLK BIT(0)
-
-/* 2 REG_CAL_TIMER (Offset 0x003C) */
-
-#define BIT_SHIFT_CAL_SCAL 0
-#define BIT_MASK_CAL_SCAL 0xff
-#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL)
-#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL)
-
-/* 2 REG_ACLK_MON (Offset 0x003E) */
-
-#define BIT_SHIFT_RCLK_MON 5
-#define BIT_MASK_RCLK_MON 0x7ff
-#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON)
-#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON)
-
-#define BIT_CAL_EN BIT(4)
-
-#define BIT_SHIFT_DPSTU 2
-#define BIT_MASK_DPSTU 0x3
-#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU)
-#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU)
-
-#define BIT_SUS_16X BIT(1)
-
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
-
-#define BIT_INDIRECT_REG_RDY BIT(20)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_FSPI_EN BIT(19)
-
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
-
-#define BIT_INDIRECT_REG_R BIT(19)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_WL_RTS_EXT_32K_SEL BIT(18)
-
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
-
-#define BIT_INDIRECT_REG_W BIT(18)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_WLGP_SPI_EN BIT(16)
-
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
-
-#define BIT_SHIFT_INDIRECT_REG_SIZE 16
-#define BIT_MASK_INDIRECT_REG_SIZE 0x3
-#define BIT_INDIRECT_REG_SIZE(x) \
- (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE)
-#define BIT_GET_INDIRECT_REG_SIZE(x) \
- (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_SIC_LBK BIT(15)
-#define BIT_ENHTP BIT(14)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_ENSIC BIT(12)
-#define BIT_SIC_SWRST BIT(11)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_PO_WIFI_PTA_PINS BIT(10)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_PO_BT_PTA_PINS BIT(9)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_ENUART BIT(8)
-
-#define BIT_SHIFT_BTMODE 6
-#define BIT_MASK_BTMODE 0x3
-#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE)
-#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE)
-
-#define BIT_ENBT BIT(5)
-#define BIT_EROM_EN BIT(4)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_WLRFE_6_7_EN BIT(3)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_WLRFE_4_5_EN BIT(2)
-
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-
-#define BIT_SHIFT_GPIOSEL 0
-#define BIT_MASK_GPIOSEL 0x3
-#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL)
-#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL)
-
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
-
-#define BIT_SHIFT_INDIRECT_REG_ADDR 0
-#define BIT_MASK_INDIRECT_REG_ADDR 0xffff
-#define BIT_INDIRECT_REG_ADDR(x) \
- (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR)
-#define BIT_GET_INDIRECT_REG_ADDR(x) \
- (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR)
-
-/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */
-
-#define BIT_SHIFT_GPIO_MOD_7_TO_0 24
-#define BIT_MASK_GPIO_MOD_7_TO_0 0xff
-#define BIT_GPIO_MOD_7_TO_0(x) \
- (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0)
-#define BIT_GET_GPIO_MOD_7_TO_0(x) \
- (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0)
-
-#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16
-#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff
-#define BIT_GPIO_IO_SEL_7_TO_0(x) \
- (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)
-#define BIT_GET_GPIO_IO_SEL_7_TO_0(x) \
- (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0)
-
-#define BIT_SHIFT_GPIO_OUT_7_TO_0 8
-#define BIT_MASK_GPIO_OUT_7_TO_0 0xff
-#define BIT_GPIO_OUT_7_TO_0(x) \
- (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0)
-#define BIT_GET_GPIO_OUT_7_TO_0(x) \
- (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0)
-
-#define BIT_SHIFT_GPIO_IN_7_TO_0 0
-#define BIT_MASK_GPIO_IN_7_TO_0 0xff
-#define BIT_GPIO_IN_7_TO_0(x) \
- (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0)
-#define BIT_GET_GPIO_IN_7_TO_0(x) \
- (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0)
-
-/* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */
-
-#define BIT_SHIFT_INDIRECT_REG_DATA 0
-#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL
-#define BIT_INDIRECT_REG_DATA(x) \
- (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA)
-#define BIT_GET_INDIRECT_REG_DATA(x) \
- (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA)
-
-/* 2 REG_GPIO_INTM (Offset 0x0048) */
-
-#define BIT_SHIFT_MUXDBG_SEL 30
-#define BIT_MASK_MUXDBG_SEL 0x3
-#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL)
-#define BIT_GET_MUXDBG_SEL(x) \
- (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL)
-
-/* 2 REG_GPIO_INTM (Offset 0x0048) */
-
-#define BIT_EXTWOL_SEL BIT(17)
-
-/* 2 REG_GPIO_INTM (Offset 0x0048) */
-
-#define BIT_EXTWOL_EN BIT(16)
-
-/* 2 REG_GPIO_INTM (Offset 0x0048) */
-
-#define BIT_GPIOF_INT_MD BIT(15)
-#define BIT_GPIOE_INT_MD BIT(14)
-#define BIT_GPIOD_INT_MD BIT(13)
-#define BIT_GPIOC_INT_MD BIT(12)
-#define BIT_GPIOB_INT_MD BIT(11)
-#define BIT_GPIOA_INT_MD BIT(10)
-#define BIT_GPIO9_INT_MD BIT(9)
-#define BIT_GPIO8_INT_MD BIT(8)
-#define BIT_GPIO7_INT_MD BIT(7)
-#define BIT_GPIO6_INT_MD BIT(6)
-#define BIT_GPIO5_INT_MD BIT(5)
-#define BIT_GPIO4_INT_MD BIT(4)
-#define BIT_GPIO3_INT_MD BIT(3)
-#define BIT_GPIO2_INT_MD BIT(2)
-#define BIT_GPIO1_INT_MD BIT(1)
-#define BIT_GPIO0_INT_MD BIT(0)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_GPIO3_WL_CTRL_EN BIT(27)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_LNAON_SEL_EN BIT(26)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_PAPE_SEL_EN BIT(25)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_DPDT_WLBT_SEL BIT(24)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_DPDT_SEL_EN BIT(23)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_GPIO13_14_WL_CTRL_EN BIT(22)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_LED2DIS BIT(21)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_LED2PL BIT(20)
-#define BIT_LED2SV BIT(19)
-
-#define BIT_SHIFT_LED2CM 16
-#define BIT_MASK_LED2CM 0x7
-#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM)
-#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM)
-
-#define BIT_LED1DIS BIT(15)
-#define BIT_LED1PL BIT(12)
-#define BIT_LED1SV BIT(11)
-
-#define BIT_SHIFT_LED1CM 8
-#define BIT_MASK_LED1CM 0x7
-#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM)
-#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM)
-
-#define BIT_LED0DIS BIT(7)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5
-#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3
-#define BIT_AFE_LDO_SWR_CHECK(x) \
- (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK)
-#define BIT_GET_AFE_LDO_SWR_CHECK(x) \
- (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK)
-
-/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_LED0PL BIT(4)
-#define BIT_LED0SV BIT(3)
-
-#define BIT_SHIFT_LED0CM 0
-#define BIT_MASK_LED0CM 0x7
-#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM)
-#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_PDNINT_EN BIT(31)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_NFC_INT_PAD_EN BIT(30)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_SPS_OCP_INT_EN BIT(29)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_PWMERR_INT_EN BIT(28)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIOF_INT_EN BIT(27)
-#define BIT_FS_GPIOE_INT_EN BIT(26)
-#define BIT_FS_GPIOD_INT_EN BIT(25)
-#define BIT_FS_GPIOC_INT_EN BIT(24)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIOB_INT_EN BIT(23)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIOA_INT_EN BIT(22)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO9_INT_EN BIT(21)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO8_INT_EN BIT(20)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO7_INT_EN BIT(19)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO6_INT_EN BIT(18)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO5_INT_EN BIT(17)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO4_INT_EN BIT(16)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO3_INT_EN BIT(15)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO2_INT_EN BIT(14)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO1_INT_EN BIT(13)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO0_INT_EN BIT(12)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_HCI_SUS_EN BIT(11)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_HCI_RES_EN BIT(10)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_HCI_RESET_EN BIT(9)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_GEN1GEN2_SWITCH BIT(5)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_HCI_TXDMA_REQ_HIMR BIT(4)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_USB_LPMRSM_MSK BIT(1)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_USB_LPMINT_MSK BIT(0)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_PDNINT BIT(31)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_SPS_OCP_INT BIT(29)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_PWMERR_INT BIT(28)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIOF_INT BIT(27)
-#define BIT_FS_GPIOE_INT BIT(26)
-#define BIT_FS_GPIOD_INT BIT(25)
-#define BIT_FS_GPIOC_INT BIT(24)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIOB_INT BIT(23)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIOA_INT BIT(22)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO9_INT BIT(21)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO8_INT BIT(20)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO7_INT BIT(19)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO6_INT BIT(18)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO5_INT BIT(17)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO4_INT BIT(16)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO3_INT BIT(15)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO2_INT BIT(14)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO1_INT BIT(13)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO0_INT BIT(12)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_HCI_SUS_INT BIT(11)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_HCI_RES_INT BIT(10)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_HCI_RESET_INT BIT(9)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_ACT2RECOVERY BIT(6)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_HCI_TXDMA_REQ_HISR BIT(4)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_32K_ENTER_SETTING_INT BIT(2)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_USB_LPMRSM_INT BIT(1)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_USB_LPMINT_INT BIT(0)
-
-/* 2 REG_HSIMR (Offset 0x0058) */
-
-#define BIT_GPIOF_INT_EN BIT(31)
-#define BIT_GPIOE_INT_EN BIT(30)
-#define BIT_GPIOD_INT_EN BIT(29)
-#define BIT_GPIOC_INT_EN BIT(28)
-#define BIT_GPIOB_INT_EN BIT(27)
-#define BIT_GPIOA_INT_EN BIT(26)
-#define BIT_GPIO9_INT_EN BIT(25)
-#define BIT_GPIO8_INT_EN BIT(24)
-#define BIT_GPIO7_INT_EN BIT(23)
-#define BIT_GPIO6_INT_EN BIT(22)
-#define BIT_GPIO5_INT_EN BIT(21)
-#define BIT_GPIO4_INT_EN BIT(20)
-#define BIT_GPIO3_INT_EN BIT(19)
-
-/* 2 REG_HSIMR (Offset 0x0058) */
-
-#define BIT_GPIO1_INT_EN BIT(17)
-#define BIT_GPIO0_INT_EN BIT(16)
-
-/* 2 REG_HSIMR (Offset 0x0058) */
-
-#define BIT_GPIO2_INT_EN_V1 BIT(16)
-
-/* 2 REG_HSIMR (Offset 0x0058) */
-
-#define BIT_PDNINT_EN BIT(7)
-
-/* 2 REG_HSIMR (Offset 0x0058) */
-
-#define BIT_RON_INT_EN BIT(6)
-
-/* 2 REG_HSIMR (Offset 0x0058) */
-
-#define BIT_SPS_OCP_INT_EN BIT(5)
-
-/* 2 REG_HSIMR (Offset 0x0058) */
-
-#define BIT_GPIO15_0_INT_EN BIT(0)
-
-/* 2 REG_HSISR (Offset 0x005C) */
-
-#define BIT_GPIOF_INT BIT(31)
-#define BIT_GPIOE_INT BIT(30)
-#define BIT_GPIOD_INT BIT(29)
-#define BIT_GPIOC_INT BIT(28)
-#define BIT_GPIOB_INT BIT(27)
-#define BIT_GPIOA_INT BIT(26)
-#define BIT_GPIO9_INT BIT(25)
-#define BIT_GPIO8_INT BIT(24)
-#define BIT_GPIO7_INT BIT(23)
-
-/* 2 REG_HSISR (Offset 0x005C) */
-
-#define BIT_GPIO6_INT BIT(22)
-#define BIT_GPIO5_INT BIT(21)
-#define BIT_GPIO4_INT BIT(20)
-#define BIT_GPIO3_INT BIT(19)
-
-/* 2 REG_HSISR (Offset 0x005C) */
-
-#define BIT_GPIO1_INT BIT(17)
-#define BIT_GPIO0_INT BIT(16)
-
-/* 2 REG_HSISR (Offset 0x005C) */
-
-#define BIT_GPIO2_INT_V1 BIT(16)
-
-/* 2 REG_HSISR (Offset 0x005C) */
-
-#define BIT_PDNINT BIT(7)
-
-/* 2 REG_HSISR (Offset 0x005C) */
-
-#define BIT_RON_INT BIT(6)
-
-/* 2 REG_HSISR (Offset 0x005C) */
-
-#define BIT_SPS_OCP_INT BIT(5)
-
-/* 2 REG_HSISR (Offset 0x005C) */
-
-#define BIT_GPIO15_0_INT BIT(0)
-#define BIT_MCUFWDL_EN BIT(0)
-
-/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */
-
-#define BIT_SHIFT_GPIO_MOD_15_TO_8 24
-#define BIT_MASK_GPIO_MOD_15_TO_8 0xff
-#define BIT_GPIO_MOD_15_TO_8(x) \
- (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8)
-#define BIT_GET_GPIO_MOD_15_TO_8(x) \
- (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8)
-
-#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16
-#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff
-#define BIT_GPIO_IO_SEL_15_TO_8(x) \
- (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)
-#define BIT_GET_GPIO_IO_SEL_15_TO_8(x) \
- (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8)
-
-#define BIT_SHIFT_GPIO_OUT_15_TO_8 8
-#define BIT_MASK_GPIO_OUT_15_TO_8 0xff
-#define BIT_GPIO_OUT_15_TO_8(x) \
- (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8)
-#define BIT_GET_GPIO_OUT_15_TO_8(x) \
- (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8)
-
-#define BIT_SHIFT_GPIO_IN_15_TO_8 0
-#define BIT_MASK_GPIO_IN_15_TO_8 0xff
-#define BIT_GPIO_IN_15_TO_8(x) \
- (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8)
-#define BIT_GET_GPIO_IN_15_TO_8(x) \
- (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8)
-
-/* 2 REG_SDIO_H2C (Offset 0x10250060) */
-
-#define BIT_SHIFT_SDIO_H2C_MSG 0
-#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL
-#define BIT_SDIO_H2C_MSG(x) \
- (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG)
-#define BIT_GET_SDIO_H2C_MSG(x) \
- (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_PAPE_WLBT_SEL BIT(29)
-#define BIT_LNAON_WLBT_SEL BIT(28)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_BTGP_GPG3_FEN BIT(26)
-#define BIT_BTGP_GPG2_FEN BIT(25)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_BTGP_JTAG_EN BIT(24)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_BTGP_UART0_EN BIT(22)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_BTGP_UART1_EN BIT(21)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_BTGP_SPI_EN BIT(20)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_BTGP_GPIO_E2 BIT(19)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_BTGP_GPIO_EN BIT(18)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_SHIFT_BTGP_GPIO_SL 16
-#define BIT_MASK_BTGP_GPIO_SL 0x3
-#define BIT_BTGP_GPIO_SL(x) \
- (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL)
-#define BIT_GET_BTGP_GPIO_SL(x) \
- (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_PAD_SDIO_SR BIT(14)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_GPIO14_OUTPUT_PL BIT(13)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_HOST_WAKE_PAD_SL BIT(11)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_PAD_LNAON_SR BIT(10)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_PAD_LNAON_E2 BIT(9)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_SW_LNAON_G_SEL_DATA BIT(8)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_SW_LNAON_A_SEL_DATA BIT(7)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_PAD_PAPE_SR BIT(6)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_PAD_PAPE_E2 BIT(5)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_SW_PAPE_G_SEL_DATA BIT(4)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_SW_PAPE_A_SEL_DATA BIT(3)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_PAD_DPDT_SR BIT(2)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_PAD_DPDT_PAD_E2 BIT(1)
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_SW_DPDT_SEL_DATA BIT(0)
-
-/* 2 REG_SDIO_C2H (Offset 0x10250064) */
-
-#define BIT_SHIFT_SDIO_C2H_MSG 0
-#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL
-#define BIT_SDIO_C2H_MSG(x) \
- (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG)
-#define BIT_GET_SDIO_C2H_MSG(x) \
- (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_ISO_BD2PP BIT(31)
-#define BIT_LDOV12B_EN BIT(30)
-#define BIT_CKEN_BTGPS BIT(29)
-#define BIT_FEN_BTGPS BIT(28)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_MULRW BIT(27)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_BTCPU_BOOTSEL BIT(27)
-#define BIT_SPI_SPEEDUP BIT(26)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24)
-#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_EN_CPL_TIMEOUT_PS BIT(22)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_ISO_BTPON2PP BIT(22)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_REG_TXDMA_FAIL_PS BIT(21)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_EN_HWENTR_L1 BIT(19)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_BT_HWROF_EN BIT(19)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_EN_ADV_CLKGATE BIT(18)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_BT_FUNC_EN BIT(18)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_BT_HWPDN_SL BIT(17)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_BT_DISN_EN BIT(16)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_BT_PDN_PULL_EN BIT(15)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_WL_PDN_PULL_EN BIT(14)
-#define BIT_EXTERNAL_REQUEST_PL BIT(13)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_ISO_BA2PP BIT(11)
-#define BIT_BT_AFE_LDO_EN BIT(10)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_BT_AFE_PLL_EN BIT(9)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_BT_DIG_CLK_EN BIT(8)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_WL_DRV_EXIST_IDX BIT(5)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_DOP_EHPAD BIT(4)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_WL_HWROF_EN BIT(3)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_WL_FUNC_EN BIT(2)
-
-/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-
-#define BIT_WL_HWPDN_SL BIT(1)
-#define BIT_WL_HWPDN_EN BIT(0)
-
-/* 2 REG_SDM_DEBUG (Offset 0x006C) */
-
-#define BIT_SHIFT_WLCLK_PHASE 0
-#define BIT_MASK_WLCLK_PHASE 0x1f
-#define BIT_WLCLK_PHASE(x) \
- (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE)
-#define BIT_GET_WLCLK_PHASE(x) \
- (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE)
-
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-
-#define BIT_DBG_GNT_WL_BT BIT(27)
-
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-
-#define BIT_LTE_MUX_CTRL_PATH BIT(26)
-
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-
-#define BIT_LTE_COEX_UART BIT(25)
-
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-
-#define BIT_3W_LTE_WL_GPIO BIT(24)
-
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-
-#define BIT_SDIO_INT_POLARITY BIT(19)
-#define BIT_SDIO_INT BIT(18)
-
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-
-#define BIT_SDIO_OFF_EN BIT(17)
-
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-
-#define BIT_SDIO_ON_EN BIT(16)
-
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-
-#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10)
-#define BIT_PCIE_WAIT_TIME BIT(9)
-
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-
-#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_SHIFT_TSFT_SEL 29
-#define BIT_MASK_TSFT_SEL 0x7
-#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL)
-#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_SHIFT_RPWM 24
-#define BIT_MASK_RPWM 0xff
-#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM)
-#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM)
-
-#define BIT_ROM_DLEN BIT(19)
-
-#define BIT_SHIFT_ROM_PGE 16
-#define BIT_MASK_ROM_PGE 0x7
-#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE)
-#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_USB_HOST_PWR_OFF_EN BIT(12)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_SYM_LPS_BLOCK_EN BIT(11)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_USB_LPM_ACT_EN BIT(10)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_USB_LPM_NY BIT(9)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_USB_SUS_DIS BIT(8)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_SHIFT_SDIO_PAD_E 5
-#define BIT_MASK_SDIO_PAD_E 0x7
-#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E)
-#define BIT_GET_SDIO_PAD_E(x) \
- (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_USB_LPPLL_EN BIT(4)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_ROP_SW15 BIT(2)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_PCI_CKRDY_OPT BIT(1)
-
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-
-#define BIT_PCI_VAUX_EN BIT(0)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_ZCD_HW_AUTO_EN BIT(27)
-#define BIT_ZCD_REGSEL BIT(26)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21
-#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f
-#define BIT_AUTO_ZCD_IN_CODE(x) \
- (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE)
-#define BIT_GET_AUTO_ZCD_IN_CODE(x) \
- (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_ZCD_CODE_IN_L 16
-#define BIT_MASK_ZCD_CODE_IN_L 0x1f
-#define BIT_ZCD_CODE_IN_L(x) \
- (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L)
-#define BIT_GET_ZCD_CODE_IN_L(x) \
- (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_LDO_HV5_DUMMY 14
-#define BIT_MASK_LDO_HV5_DUMMY 0x3
-#define BIT_LDO_HV5_DUMMY(x) \
- (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY)
-#define BIT_GET_LDO_HV5_DUMMY(x) \
- (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12
-#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3
-#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) \
- (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) \
- << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1)
-#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) \
- (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & \
- BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10
-#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3
-#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) \
- (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) \
- << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1)
-#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) \
- (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & \
- BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8
-#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3
-#define BIT_REG_LOAD33_BIT0_TO_BIT1(x) \
- (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) \
- << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1)
-#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) \
- (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & \
- BIT_MASK_REG_LOAD33_BIT0_TO_BIT1)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_REG_BYPASS_L BIT(7)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_REG_LDOF_L BIT(6)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_REG_TYPE_L_V1 BIT(5)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_ARENB_L BIT(3)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_CFC_L 1
-#define BIT_MASK_CFC_L 0x3
-#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L)
-#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L)
-
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_REG_OCPS_L_V1 BIT(0)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_ANA_PORT_EN BIT(22)
-#define BIT_MAC_PORT_EN BIT(21)
-#define BIT_BOOT_FSPI_EN BIT(20)
-#define BIT_FW_INIT_RDY BIT(15)
-#define BIT_FW_DW_RDY BIT(14)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_SHIFT_CPU_CLK_SEL 12
-#define BIT_MASK_CPU_CLK_SEL 0x3
-#define BIT_CPU_CLK_SEL(x) \
- (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL)
-#define BIT_GET_CPU_CLK_SEL(x) \
- (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_CCLK_CHG_MASK BIT(11)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_EMEM_TXBUF_DW_RDY BIT(9)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_EMEM_CHKSUM_OK BIT(8)
-#define BIT_EMEM_DW_OK BIT(7)
-#define BIT_TOGGLING BIT(7)
-#define BIT_DMEM_CHKSUM_OK BIT(6)
-#define BIT_ACK BIT(6)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_DMEM_DW_OK BIT(5)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_IMEM_CHKSUM_OK BIT(4)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_IMEM_DW_OK BIT(3)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2)
-
-/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1)
-
-/* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */
-
-#define BIT_32K_PERMISSION BIT(0)
-
-/* 2 REG_MCU_TST_CFG (Offset 0x0084) */
-
-#define BIT_SHIFT_LBKTST 0
-#define BIT_MASK_LBKTST 0xffff
-#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST)
-#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST)
-
-/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */
-
-#define BIT_PAD_CLK_XHGE_EN BIT(3)
-#define BIT_INTER_CLK_EN BIT(2)
-#define BIT_EN_RPT_TXCRC BIT(1)
-#define BIT_DIS_RXDMA_STS BIT(0)
-
-/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */
-
-#define BIT_INTR_CTRL BIT(4)
-#define BIT_SDIO_VOLTAGE BIT(3)
-#define BIT_BYPASS_INIT BIT(2)
-
-/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */
-
-#define BIT_HCI_RESUME_RDY BIT(1)
-#define BIT_HCI_SUS_REQ BIT(0)
-
-/* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */
-
-#define BIT_SHIFT_HOST_MSG_E1 16
-#define BIT_MASK_HOST_MSG_E1 0xffff
-#define BIT_HOST_MSG_E1(x) \
- (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1)
-#define BIT_GET_HOST_MSG_E1(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1)
-
-#define BIT_SHIFT_HOST_MSG_E0 0
-#define BIT_MASK_HOST_MSG_E0 0xffff
-#define BIT_HOST_MSG_E0(x) \
- (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0)
-#define BIT_GET_HOST_MSG_E0(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0)
-
-/* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */
-
-#define BIT_SHIFT_CMDIN_2RESP_TIMER 0
-#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff
-#define BIT_CMDIN_2RESP_TIMER(x) \
- (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER)
-#define BIT_GET_CMDIN_2RESP_TIMER(x) \
- (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER)
-
-/* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */
-
-#define BIT_SHIFT_SDIO_CMD_CRC_V1 0
-#define BIT_MASK_SDIO_CMD_CRC_V1 0xff
-#define BIT_SDIO_CMD_CRC_V1(x) \
- (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1)
-#define BIT_GET_SDIO_CMD_CRC_V1(x) \
- (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1)
-
-/* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */
-
-#define BIT_SHIFT_HOST_MSG_E3 16
-#define BIT_MASK_HOST_MSG_E3 0xffff
-#define BIT_HOST_MSG_E3(x) \
- (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3)
-#define BIT_GET_HOST_MSG_E3(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3)
-
-#define BIT_SHIFT_HOST_MSG_E2 0
-#define BIT_MASK_HOST_MSG_E2 0xffff
-#define BIT_HOST_MSG_E2(x) \
- (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2)
-#define BIT_GET_HOST_MSG_E2(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WLLPSOP_EABM BIT(31)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WLLPSOP_ACKF BIT(30)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WLLPSOP_DLDM BIT(29)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WLLPSOP_ESWR BIT(28)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WLLPSOP_PWMM BIT(27)
-#define BIT_WLLPSOP_EECK BIT(26)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WLLPSOP_WLMACOFF BIT(25)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WLLPSOP_EXTAL BIT(24)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WL_SYNPON_VOLTSPDN BIT(23)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WLLPSOP_WLBBOFF BIT(22)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WLLPSOP_WLMEM_DS BIT(21)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12
-#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf
-#define BIT_LPLDH12_VADJ_STEP_DN(x) \
- (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) \
- << BIT_SHIFT_LPLDH12_VADJ_STEP_DN)
-#define BIT_GET_LPLDH12_VADJ_STEP_DN(x) \
- (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & \
- BIT_MASK_LPLDH12_VADJ_STEP_DN)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8
-#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7
-#define BIT_V15ADJ_L1_STEP_DN(x) \
- (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN)
-#define BIT_GET_V15ADJ_L1_STEP_DN(x) \
- (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN)
-
-#define BIT_REGU_32K_CLK_EN BIT(1)
-#define BIT_DRV_WLAN_INT_CLR BIT(1)
-
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-
-#define BIT_WL_LPS_EN BIT(0)
-
-/* 2 REG_SDIO_HSISR (Offset 0x10250090) */
-
-#define BIT_DRV_WLAN_INT BIT(0)
-
-/* 2 REG_SDIO_HSIMR (Offset 0x10250091) */
-
-#define BIT_HISR_MASK BIT(0)
-
-/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
-
-#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31)
-
-/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
-
-#define BIT_ORDER_SDM BIT(30)
-#define BIT_RFE_SEL_SDM BIT(29)
-
-#define BIT_SHIFT_REF_SEL 25
-#define BIT_MASK_REF_SEL 0xf
-#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL)
-#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL)
-
-/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
-
-#define BIT_SHIFT_F0F_SDM 12
-#define BIT_MASK_F0F_SDM 0x1fff
-#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM)
-#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM)
-
-/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
-
-#define BIT_SHIFT_F0N_SDM 9
-#define BIT_MASK_F0N_SDM 0x7
-#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM)
-#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM)
-
-/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
-
-#define BIT_SHIFT_DIVN_SDM 3
-#define BIT_MASK_DIVN_SDM 0x3f
-#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM)
-#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM)
-
-/* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */
-
-#define BIT_WLGP_DBC1EN BIT(15)
-
-#define BIT_SHIFT_WLGP_DBC1 8
-#define BIT_MASK_WLGP_DBC1 0xf
-#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1)
-#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1)
-
-#define BIT_WLGP_DBC0EN BIT(7)
-
-#define BIT_SHIFT_WLGP_DBC0 0
-#define BIT_MASK_WLGP_DBC0 0xf
-#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0)
-#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0)
-
-/* 2 REG_RPWM2 (Offset 0x009C) */
-
-#define BIT_SHIFT_RPWM2 16
-#define BIT_MASK_RPWM2 0xffff
-#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2)
-#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2)
-
-/* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */
-
-#define BIT_SHIFT_FSM_MON_SEL 24
-#define BIT_MASK_FSM_MON_SEL 0x7
-#define BIT_FSM_MON_SEL(x) \
- (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL)
-#define BIT_GET_FSM_MON_SEL(x) \
- (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL)
-
-#define BIT_DOP_ELDO BIT(23)
-#define BIT_FSM_MON_UPD BIT(15)
-
-#define BIT_SHIFT_FSM_PAR 0
-#define BIT_MASK_FSM_PAR 0x7fff
-#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR)
-#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR)
-
-/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */
-
-#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0
-#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7
-#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \
- (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) \
- << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1)
-#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \
- (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & \
- BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1)
-
-/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */
-
-#define BIT_BT_INT_EN BIT(31)
-
-#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16
-#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff
-#define BIT_RD_WR_WIFI_BT_INFO(x) \
- (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO)
-#define BIT_GET_RD_WR_WIFI_BT_INFO(x) \
- (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO)
-
-/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */
-
-#define BIT_PMC_WR_OVF BIT(8)
-
-#define BIT_SHIFT_WLPMC_ERRINT 0
-#define BIT_MASK_WLPMC_ERRINT 0xff
-#define BIT_WLPMC_ERRINT(x) \
- (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT)
-#define BIT_GET_WLPMC_ERRINT(x) \
- (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT)
-
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
-
-#define BIT_SHIFT_SEL_V 30
-#define BIT_MASK_SEL_V 0x3
-#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V)
-#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V)
-
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
-
-#define BIT_TXFIFO_TH_INT BIT(30)
-
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
-
-#define BIT_SEL_LDO_PC BIT(29)
-
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
-
-#define BIT_SHIFT_CK_MON_SEL 26
-#define BIT_MASK_CK_MON_SEL 0x7
-#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL)
-#define BIT_GET_CK_MON_SEL(x) \
- (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL)
-
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
-
-#define BIT_CK_MON_EN BIT(25)
-#define BIT_FREF_EDGE BIT(24)
-#define BIT_CK320M_EN BIT(23)
-#define BIT_CK_5M_EN BIT(22)
-#define BIT_TESTEN BIT(21)
-
-/* 2 REG_HIMR0 (Offset 0x00B0) */
-
-#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31)
-#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30)
-#define BIT_PSTIMEOUT_MSK BIT(29)
-#define BIT_GTINT4_MSK BIT(28)
-#define BIT_GTINT3_MSK BIT(27)
-#define BIT_TXBCN0ERR_MSK BIT(26)
-#define BIT_TXBCN0OK_MSK BIT(25)
-#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24)
-#define BIT_BCNDMAINT0_MSK BIT(20)
-#define BIT_BCNDERR0_MSK BIT(16)
-#define BIT_HSISR_IND_ON_INT_MSK BIT(15)
-
-/* 2 REG_HIMR0 (Offset 0x00B0) */
-
-#define BIT_BCNDMAINT_E_MSK BIT(14)
-
-/* 2 REG_HIMR0 (Offset 0x00B0) */
-
-#define BIT_CTWEND_MSK BIT(12)
-#define BIT_HISR1_IND_MSK BIT(11)
-
-/* 2 REG_HIMR0 (Offset 0x00B0) */
-
-#define BIT_C2HCMD_MSK BIT(10)
-#define BIT_CPWM2_MSK BIT(9)
-#define BIT_CPWM_MSK BIT(8)
-#define BIT_HIGHDOK_MSK BIT(7)
-#define BIT_MGTDOK_MSK BIT(6)
-#define BIT_BKDOK_MSK BIT(5)
-#define BIT_BEDOK_MSK BIT(4)
-#define BIT_VIDOK_MSK BIT(3)
-#define BIT_VODOK_MSK BIT(2)
-#define BIT_RDU_MSK BIT(1)
-#define BIT_RXOK_MSK BIT(0)
-
-/* 2 REG_HISR0 (Offset 0x00B4) */
-
-#define BIT_TIMEOUT_INTERRUPT2 BIT(31)
-
-/* 2 REG_HISR0 (Offset 0x00B4) */
-
-#define BIT_TIMEOUT_INTERRUTP1 BIT(30)
-
-/* 2 REG_HISR0 (Offset 0x00B4) */
-
-#define BIT_PSTIMEOUT BIT(29)
-#define BIT_GTINT4 BIT(28)
-#define BIT_GTINT3 BIT(27)
-#define BIT_TXBCN0ERR BIT(26)
-#define BIT_TXBCN0OK BIT(25)
-#define BIT_TSF_BIT32_TOGGLE BIT(24)
-#define BIT_BCNDMAINT0 BIT(20)
-#define BIT_BCNDERR0 BIT(16)
-#define BIT_HSISR_IND_ON_INT BIT(15)
-
-/* 2 REG_HISR0 (Offset 0x00B4) */
-
-#define BIT_BCNDMAINT_E BIT(14)
-
-/* 2 REG_HISR0 (Offset 0x00B4) */
-
-#define BIT_CTWEND BIT(12)
-
-/* 2 REG_HISR0 (Offset 0x00B4) */
-
-#define BIT_HISR1_IND_INT BIT(11)
-#define BIT_C2HCMD BIT(10)
-#define BIT_CPWM2 BIT(9)
-#define BIT_CPWM BIT(8)
-#define BIT_HIGHDOK BIT(7)
-#define BIT_MGTDOK BIT(6)
-#define BIT_BKDOK BIT(5)
-#define BIT_BEDOK BIT(4)
-#define BIT_VIDOK BIT(3)
-#define BIT_VODOK BIT(2)
-#define BIT_RDU BIT(1)
-#define BIT_RXOK BIT(0)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_BTON_STS_UPDATE_MASK BIT(29)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_MCU_ERR_MASK BIT(28)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_BCNDMAINT7__MSK BIT(27)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_BCNDMAINT6__MSK BIT(26)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_BCNDMAINT5__MSK BIT(25)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_BCNDMAINT4__MSK BIT(24)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_BCNDMAINT3_MSK BIT(23)
-#define BIT_BCNDMAINT2_MSK BIT(22)
-#define BIT_BCNDMAINT1_MSK BIT(21)
-#define BIT_BCNDERR7_MSK BIT(20)
-#define BIT_BCNDERR6_MSK BIT(19)
-#define BIT_BCNDERR5_MSK BIT(18)
-#define BIT_BCNDERR4_MSK BIT(17)
-#define BIT_BCNDERR3_MSK BIT(16)
-#define BIT_BCNDERR2_MSK BIT(15)
-#define BIT_BCNDERR1_MSK BIT(14)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_ATIMEND_E_MSK BIT(13)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_ATIMEND__MSK BIT(12)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_TXERR_MSK BIT(11)
-#define BIT_RXERR_MSK BIT(10)
-#define BIT_TXFOVW_MSK BIT(9)
-#define BIT_FOVW_MSK BIT(8)
-
-/* 2 REG_HIMR1 (Offset 0x00B8) */
-
-#define BIT_CPU_MGQ_TXDONE_MSK BIT(5)
-#define BIT_PS_TIMER_C_MSK BIT(4)
-#define BIT_PS_TIMER_B_MSK BIT(3)
-#define BIT_PS_TIMER_A_MSK BIT(2)
-#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1)
-
-/* 2 REG_HISR1 (Offset 0x00BC) */
-
-#define BIT_BTON_STS_UPDATE_INT BIT(29)
-
-/* 2 REG_HISR1 (Offset 0x00BC) */
-
-#define BIT_MCU_ERR BIT(28)
-
-/* 2 REG_HISR1 (Offset 0x00BC) */
-
-#define BIT_BCNDMAINT7 BIT(27)
-#define BIT_BCNDMAINT6 BIT(26)
-#define BIT_BCNDMAINT5 BIT(25)
-#define BIT_BCNDMAINT4 BIT(24)
-#define BIT_BCNDMAINT3 BIT(23)
-#define BIT_BCNDMAINT2 BIT(22)
-#define BIT_BCNDMAINT1 BIT(21)
-#define BIT_BCNDERR7 BIT(20)
-#define BIT_BCNDERR6 BIT(19)
-#define BIT_BCNDERR5 BIT(18)
-#define BIT_BCNDERR4 BIT(17)
-#define BIT_BCNDERR3 BIT(16)
-#define BIT_BCNDERR2 BIT(15)
-#define BIT_BCNDERR1 BIT(14)
-
-/* 2 REG_HISR1 (Offset 0x00BC) */
-
-#define BIT_ATIMEND_E BIT(13)
-
-/* 2 REG_HISR1 (Offset 0x00BC) */
-
-#define BIT_ATIMEND BIT(12)
-#define BIT_TXERR_INT BIT(11)
-#define BIT_RXERR_INT BIT(10)
-#define BIT_TXFOVW BIT(9)
-#define BIT_FOVW BIT(8)
-
-/* 2 REG_HISR1 (Offset 0x00BC) */
-
-#define BIT_CPU_MGQ_TXDONE BIT(5)
-#define BIT_PS_TIMER_C BIT(4)
-#define BIT_PS_TIMER_B BIT(3)
-#define BIT_PS_TIMER_A BIT(2)
-#define BIT_CPUMGQ_TX_TIMER BIT(1)
-
-/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */
-
-#define BIT_HR_FF_OVF BIT(6)
-#define BIT_HR_FF_UDN BIT(5)
-#define BIT_TXDMA_BUSY_ERR BIT(4)
-#define BIT_TXDMA_VLD_ERR BIT(3)
-#define BIT_QSEL_UNKNOWN_ERR BIT(2)
-#define BIT_QSEL_MIS_ERR BIT(1)
-
-/* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */
-
-#define BIT_SHIFT_DEBUG_ST 0
-#define BIT_MASK_DEBUG_ST 0xffffffffL
-#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST)
-#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST)
-
-/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */
-
-#define BIT_SDIO_OVERRD_ERR BIT(0)
-
-/* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C1) */
-
-#define BIT_SHIFT_CMD_CRC_ERR_CNT 0
-#define BIT_MASK_CMD_CRC_ERR_CNT 0xff
-#define BIT_CMD_CRC_ERR_CNT(x) \
- (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT)
-#define BIT_GET_CMD_CRC_ERR_CNT(x) \
- (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT)
-
-/* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C2) */
-
-#define BIT_SHIFT_DATA_CRC_ERR_CNT 0
-#define BIT_MASK_DATA_CRC_ERR_CNT 0xff
-#define BIT_DATA_CRC_ERR_CNT(x) \
- (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT)
-#define BIT_GET_DATA_CRC_ERR_CNT(x) \
- (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_USB3_USB2_TRANSITION BIT(20)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_SHIFT_USB23_SW_MODE_V1 18
-#define BIT_MASK_USB23_SW_MODE_V1 0x3
-#define BIT_USB23_SW_MODE_V1(x) \
- (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1)
-#define BIT_GET_USB23_SW_MODE_V1(x) \
- (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_NO_PDN_CHIPOFF_V1 BIT(17)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_RSM_EN_V1 BIT(16)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_LD_B12V_EN BIT(7)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_EECS_IOSEL_V1 BIT(6)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_EECS_DATA_O_V1 BIT(5)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_EECS_DATA_I_V1 BIT(4)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_EESK_IOSEL_V1 BIT(2)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_EESK_DATA_O_V1 BIT(1)
-
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-
-#define BIT_EESK_DATA_I_V1 BIT(0)
-
-/* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */
-
-#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0
-#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL
-#define BIT_SDIO_CMD_ERR_CONTENT(x) \
- (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) \
- << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)
-#define BIT_GET_SDIO_CMD_ERR_CONTENT(x) \
- (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & \
- BIT_MASK_SDIO_CMD_ERR_CONTENT)
-
-/* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */
-
-#define BIT_D3_CRC_ERR BIT(4)
-#define BIT_D2_CRC_ERR BIT(3)
-#define BIT_D1_CRC_ERR BIT(2)
-#define BIT_D0_CRC_ERR BIT(1)
-#define BIT_CMD_CRC_ERR BIT(0)
-
-/* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */
-
-#define BIT_SHIFT_SDIO_DATA_CRC 0
-#define BIT_MASK_SDIO_DATA_CRC 0xff
-#define BIT_SDIO_DATA_CRC(x) \
- (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC)
-#define BIT_GET_SDIO_DATA_CRC(x) \
- (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC)
-
-/* 2 REG_SDIO_DATA_REPLY_TIME (Offset 0x102500CB) */
-
-#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0
-#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7
-#define BIT_SDIO_DATA_REPLY_TIME(x) \
- (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) \
- << BIT_SHIFT_SDIO_DATA_REPLY_TIME)
-#define BIT_GET_SDIO_DATA_REPLY_TIME(x) \
- (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & \
- BIT_MASK_SDIO_DATA_REPLY_TIME)
-
-/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
-
-#define BIT_SHIFT_EFUSE_BURN_GNT 24
-#define BIT_MASK_EFUSE_BURN_GNT 0xff
-#define BIT_EFUSE_BURN_GNT(x) \
- (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT)
-#define BIT_GET_EFUSE_BURN_GNT(x) \
- (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT)
-
-/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
-
-#define BIT_STOP_WL_PMC BIT(9)
-#define BIT_STOP_SYM_PMC BIT(8)
-
-/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
-
-#define BIT_REG_RST_WLPMC BIT(5)
-#define BIT_REG_RST_PD12N BIT(4)
-#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3)
-#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2)
-
-#define BIT_SHIFT_SYSON_REG_ARB 0
-#define BIT_MASK_SYSON_REG_ARB 0x3
-#define BIT_SYSON_REG_ARB(x) \
- (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB)
-#define BIT_GET_SYSON_REG_ARB(x) \
- (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB)
-
-/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_BIST_USB_DIS BIT(27)
-
-/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_BIST_PCI_DIS BIT(26)
-
-/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_BIST_BT_DIS BIT(25)
-
-/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_BIST_WL_DIS BIT(24)
-
-/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_SHIFT_BIST_RPT_SEL 16
-#define BIT_MASK_BIST_RPT_SEL 0xf
-#define BIT_BIST_RPT_SEL(x) \
- (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL)
-#define BIT_GET_BIST_RPT_SEL(x) \
- (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL)
-
-/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_BIST_RESUME_PS BIT(4)
-
-/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_BIST_RESUME BIT(3)
-#define BIT_BIST_NORMAL BIT(2)
-
-/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_BIST_RSTN BIT(1)
-#define BIT_BIST_CLK_EN BIT(0)
-
-/* 2 REG_BIST_RPT (Offset 0x00D4) */
-
-#define BIT_SHIFT_MBIST_REPORT 0
-#define BIT_MASK_MBIST_REPORT 0xffffffffL
-#define BIT_MBIST_REPORT(x) \
- (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT)
-#define BIT_GET_MBIST_REPORT(x) \
- (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT)
-
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-
-#define BIT_UMEM_RME BIT(31)
-
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-
-#define BIT_SHIFT_BT_SPRAM 28
-#define BIT_MASK_BT_SPRAM 0x3
-#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM)
-#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM)
-
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-
-#define BIT_SHIFT_BT_ROM 24
-#define BIT_MASK_BT_ROM 0xf
-#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM)
-#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM)
-
-#define BIT_SHIFT_PCI_DPRAM 10
-#define BIT_MASK_PCI_DPRAM 0x3
-#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM)
-#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM)
-
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-
-#define BIT_SHIFT_PCI_SPRAM 8
-#define BIT_MASK_PCI_SPRAM 0x3
-#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM)
-#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM)
-
-#define BIT_SHIFT_USB_SPRAM 6
-#define BIT_MASK_USB_SPRAM 0x3
-#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM)
-#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM)
-
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-
-#define BIT_SHIFT_USB_SPRF 4
-#define BIT_MASK_USB_SPRF 0x3
-#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF)
-#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF)
-
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-
-#define BIT_SHIFT_MCU_ROM 0
-#define BIT_MASK_MCU_ROM 0xf
-#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM)
-#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM)
-
-/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
-
-#define BIT_SYN_AGPIO BIT(20)
-
-/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
-
-#define BIT_XTAL_LP BIT(4)
-#define BIT_XTAL_GM_SEP BIT(3)
-
-/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
-
-#define BIT_SHIFT_XTAL_SEL_TOK 0
-#define BIT_MASK_XTAL_SEL_TOK 0x7
-#define BIT_XTAL_SEL_TOK(x) \
- (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK)
-#define BIT_GET_XTAL_SEL_TOK(x) \
- (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK)
-
-/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-
-#define BIT_RD_SEL BIT(31)
-
-/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-
-#define BIT_USB_SIE_INTF_WE_V1 BIT(30)
-#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29)
-#define BIT_USB_SIE_SELECT BIT(28)
-
-/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-
-#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16
-#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff
-#define BIT_USB_SIE_INTF_ADDR_V1(x) \
- (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) \
- << BIT_SHIFT_USB_SIE_INTF_ADDR_V1)
-#define BIT_GET_USB_SIE_INTF_ADDR_V1(x) \
- (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & \
- BIT_MASK_USB_SIE_INTF_ADDR_V1)
-
-/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-
-#define BIT_SHIFT_USB_SIE_INTF_RD 8
-#define BIT_MASK_USB_SIE_INTF_RD 0xff
-#define BIT_USB_SIE_INTF_RD(x) \
- (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD)
-#define BIT_GET_USB_SIE_INTF_RD(x) \
- (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD)
-
-#define BIT_SHIFT_USB_SIE_INTF_WD 0
-#define BIT_MASK_USB_SIE_INTF_WD 0xff
-#define BIT_USB_SIE_INTF_WD(x) \
- (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD)
-#define BIT_GET_USB_SIE_INTF_WD(x) \
- (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD)
-
-/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */
-
-#define BIT_PCIE_MIO_BYIOREG BIT(13)
-#define BIT_PCIE_MIO_RE BIT(12)
-
-#define BIT_SHIFT_PCIE_MIO_WE 8
-#define BIT_MASK_PCIE_MIO_WE 0xf
-#define BIT_PCIE_MIO_WE(x) \
- (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE)
-#define BIT_GET_PCIE_MIO_WE(x) \
- (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE)
-
-#define BIT_SHIFT_PCIE_MIO_ADDR 0
-#define BIT_MASK_PCIE_MIO_ADDR 0xff
-#define BIT_PCIE_MIO_ADDR(x) \
- (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR)
-#define BIT_GET_PCIE_MIO_ADDR(x) \
- (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR)
-
-/* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */
-
-#define BIT_SHIFT_PCIE_MIO_DATA 0
-#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL
-#define BIT_PCIE_MIO_DATA(x) \
- (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA)
-#define BIT_GET_PCIE_MIO_DATA(x) \
- (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA)
-
-/* 2 REG_WLRF1 (Offset 0x00EC) */
-
-#define BIT_SHIFT_WLRF1_CTRL 24
-#define BIT_MASK_WLRF1_CTRL 0xff
-#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL)
-#define BIT_GET_WLRF1_CTRL(x) \
- (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_SHIFT_TRP_ICFG 28
-#define BIT_MASK_TRP_ICFG 0xf
-#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG)
-#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_RF_TYPE_ID BIT(27)
-#define BIT_BD_HCI_SEL BIT(26)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_BD_PKG_SEL BIT(25)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_SPSLDO_SEL BIT(24)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_RTL_ID BIT(23)
-#define BIT_PAD_HWPD_IDN BIT(22)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_TESTMODE BIT(20)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_SHIFT_VENDOR_ID 16
-#define BIT_MASK_VENDOR_ID 0xf
-#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
-#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_SHIFT_CHIP_VER 12
-#define BIT_MASK_CHIP_VER 0xf
-#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
-#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_BD_MAC3 BIT(11)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_BD_MAC1 BIT(10)
-#define BIT_BD_MAC2 BIT(9)
-#define BIT_SIC_IDLE BIT(8)
-#define BIT_SW_OFFLOAD_EN BIT(7)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_OCP_SHUTDN BIT(6)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_V15_VLD BIT(5)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_PCIRSTB BIT(4)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_PCLK_VLD BIT(3)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_UCLK_VLD BIT(2)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_ACLK_VLD BIT(1)
-
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_XCLK_VLD BIT(0)
-
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_RF_RL_ID 28
-#define BIT_MASK_RF_RL_ID 0xf
-#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID)
-#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID)
-
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_HPHY_ICFG BIT(19)
-
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_SEL_0XC0 16
-#define BIT_MASK_SEL_0XC0 0x3
-#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0)
-#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0)
-
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_HCI_SEL_V3 12
-#define BIT_MASK_HCI_SEL_V3 0x7
-#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3)
-#define BIT_GET_HCI_SEL_V3(x) \
- (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3)
-
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_USB_OPERATION_MODE BIT(10)
-#define BIT_BT_PDN BIT(9)
-#define BIT_AUTO_WLPON BIT(8)
-
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_WL_MODE BIT(7)
-
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_PKG_SEL_HCI BIT(6)
-
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_PAD_HCI_SEL_V1 3
-#define BIT_MASK_PAD_HCI_SEL_V1 0x7
-#define BIT_PAD_HCI_SEL_V1(x) \
- (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1)
-#define BIT_GET_PAD_HCI_SEL_V1(x) \
- (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1)
-
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_EFS_HCI_SEL_V1 0
-#define BIT_MASK_EFS_HCI_SEL_V1 0x7
-#define BIT_EFS_HCI_SEL_V1(x) \
- (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1)
-#define BIT_GET_EFS_HCI_SEL_V1(x) \
- (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1)
-
-/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */
-
-#define BIT_SIO_ALDN BIT(19)
-#define BIT_USB_ALDN BIT(18)
-#define BIT_PCI_ALDN BIT(17)
-#define BIT_SYS_ALDN BIT(16)
-
-#define BIT_SHIFT_EPVID1 8
-#define BIT_MASK_EPVID1 0xff
-#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1)
-#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1)
-
-#define BIT_SHIFT_EPVID0 0
-#define BIT_MASK_EPVID0 0xff
-#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0)
-#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0)
-
-/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
-
-#define BIT_HCI_SEL_EMBEDDED BIT(8)
-
-/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
-
-#define BIT_SHIFT_HW_ID 0
-#define BIT_MASK_HW_ID 0xff
-#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID)
-#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID)
-
-/* 2 REG_CR (Offset 0x0100) */
-
-#define BIT_SHIFT_LBMODE 24
-#define BIT_MASK_LBMODE 0x1f
-#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE)
-#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE)
-
-#define BIT_SHIFT_NETYPE1 18
-#define BIT_MASK_NETYPE1 0x3
-#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1)
-#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1)
-
-#define BIT_SHIFT_NETYPE0 16
-#define BIT_MASK_NETYPE0 0x3
-#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0)
-#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0)
-
-/* 2 REG_CR (Offset 0x0100) */
-
-#define BIT_I2C_MAILBOX_EN BIT(12)
-#define BIT_SHCUT_EN BIT(11)
-
-/* 2 REG_CR (Offset 0x0100) */
-
-#define BIT_32K_CAL_TMR_EN BIT(10)
-#define BIT_MAC_SEC_EN BIT(9)
-#define BIT_ENSWBCN BIT(8)
-#define BIT_MACRXEN BIT(7)
-#define BIT_MACTXEN BIT(6)
-#define BIT_SCHEDULE_EN BIT(5)
-#define BIT_PROTOCOL_EN BIT(4)
-#define BIT_RXDMA_EN BIT(3)
-#define BIT_TXDMA_EN BIT(2)
-#define BIT_HCI_RXDMA_EN BIT(1)
-#define BIT_HCI_TXDMA_EN BIT(0)
-
-/* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */
-
-#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0
-#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff
-#define BIT_PKT_BUFF_ACCESS_CTRL(x) \
- (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) \
- << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)
-#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) \
- (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & \
- BIT_MASK_PKT_BUFF_ACCESS_CTRL)
-
-/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */
-
-#define BIT_TSF_CLK_STABLE BIT(15)
-
-#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4
-#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7
-#define BIT_I2C_M_BUS_GNT_FW(x) \
- (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW)
-#define BIT_GET_I2C_M_BUS_GNT_FW(x) \
- (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW)
-
-#define BIT_I2C_M_GNT_FW BIT(3)
-
-#define BIT_SHIFT_I2C_M_SPEED 1
-#define BIT_MASK_I2C_M_SPEED 0x3
-#define BIT_I2C_M_SPEED(x) \
- (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED)
-#define BIT_GET_I2C_M_SPEED(x) \
- (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED)
-
-#define BIT_I2C_M_UNLOCK BIT(0)
-
-/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
-
-#define BIT_SHIFT_TXDMA_HIQ_MAP 14
-#define BIT_MASK_TXDMA_HIQ_MAP 0x3
-#define BIT_TXDMA_HIQ_MAP(x) \
- (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
-#define BIT_GET_TXDMA_HIQ_MAP(x) \
- (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP)
-
-#define BIT_SHIFT_TXDMA_MGQ_MAP 12
-#define BIT_MASK_TXDMA_MGQ_MAP 0x3
-#define BIT_TXDMA_MGQ_MAP(x) \
- (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
-#define BIT_GET_TXDMA_MGQ_MAP(x) \
- (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP)
-
-#define BIT_SHIFT_TXDMA_BKQ_MAP 10
-#define BIT_MASK_TXDMA_BKQ_MAP 0x3
-#define BIT_TXDMA_BKQ_MAP(x) \
- (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
-#define BIT_GET_TXDMA_BKQ_MAP(x) \
- (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP)
-
-#define BIT_SHIFT_TXDMA_BEQ_MAP 8
-#define BIT_MASK_TXDMA_BEQ_MAP 0x3
-#define BIT_TXDMA_BEQ_MAP(x) \
- (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
-#define BIT_GET_TXDMA_BEQ_MAP(x) \
- (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP)
-
-#define BIT_SHIFT_TXDMA_VIQ_MAP 6
-#define BIT_MASK_TXDMA_VIQ_MAP 0x3
-#define BIT_TXDMA_VIQ_MAP(x) \
- (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
-#define BIT_GET_TXDMA_VIQ_MAP(x) \
- (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP)
-
-#define BIT_SHIFT_TXDMA_VOQ_MAP 4
-#define BIT_MASK_TXDMA_VOQ_MAP 0x3
-#define BIT_TXDMA_VOQ_MAP(x) \
- (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
-#define BIT_GET_TXDMA_VOQ_MAP(x) \
- (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP)
-
-#define BIT_RXDMA_AGG_EN BIT(2)
-#define BIT_RXSHFT_EN BIT(1)
-#define BIT_RXDMA_ARBBW_EN BIT(0)
-
-/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
-
-#define BIT_SHIFT_RXFFOVFL_RSV_V2 8
-#define BIT_MASK_RXFFOVFL_RSV_V2 0xf
-#define BIT_RXFFOVFL_RSV_V2(x) \
- (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2)
-#define BIT_GET_RXFFOVFL_RSV_V2(x) \
- (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2)
-
-/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
-
-#define BIT_SHIFT_TXPKTBUF_PGBNDY 0
-#define BIT_MASK_TXPKTBUF_PGBNDY 0xff
-#define BIT_TXPKTBUF_PGBNDY(x) \
- (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY)
-#define BIT_GET_TXPKTBUF_PGBNDY(x) \
- (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY)
-
-/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
-
-#define BIT_SHIFT_RXFF0_BNDY_V2 0
-#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff
-#define BIT_RXFF0_BNDY_V2(x) \
- (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2)
-#define BIT_GET_RXFF0_BNDY_V2(x) \
- (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2)
-
-#define BIT_SHIFT_RXFF0_RDPTR_V2 0
-#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff
-#define BIT_RXFF0_RDPTR_V2(x) \
- (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2)
-#define BIT_GET_RXFF0_RDPTR_V2(x) \
- (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2)
-
-#define BIT_SHIFT_RXFF0_WTPTR_V2 0
-#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff
-#define BIT_RXFF0_WTPTR_V2(x) \
- (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2)
-#define BIT_GET_RXFF0_WTPTR_V2(x) \
- (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2)
-
-/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */
-
-#define BIT_SHIFT_I2C_M_STATUS 8
-#define BIT_MASK_I2C_M_STATUS 0xf
-#define BIT_I2C_M_STATUS(x) \
- (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS)
-#define BIT_GET_I2C_M_STATUS(x) \
- (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS)
-
-/* 2 REG_FE1IMR (Offset 0x0120) */
-
-#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28)
-#define BIT_FS_RXDONE3_INT_EN BIT(27)
-#define BIT_FS_RXDONE2_INT_EN BIT(26)
-#define BIT_FS_RX_BCN_P4_INT_EN BIT(25)
-#define BIT_FS_RX_BCN_P3_INT_EN BIT(24)
-#define BIT_FS_RX_BCN_P2_INT_EN BIT(23)
-#define BIT_FS_RX_BCN_P1_INT_EN BIT(22)
-#define BIT_FS_RX_BCN_P0_INT_EN BIT(21)
-#define BIT_FS_RX_UMD0_INT_EN BIT(20)
-#define BIT_FS_RX_UMD1_INT_EN BIT(19)
-#define BIT_FS_RX_BMD0_INT_EN BIT(18)
-#define BIT_FS_RX_BMD1_INT_EN BIT(17)
-#define BIT_FS_RXDONE_INT_EN BIT(16)
-#define BIT_FS_WWLAN_INT_EN BIT(15)
-#define BIT_FS_SOUND_DONE_INT_EN BIT(14)
-#define BIT_FS_LP_STBY_INT_EN BIT(13)
-#define BIT_FS_TRL_MTR_INT_EN BIT(12)
-#define BIT_FS_BF1_PRETO_INT_EN BIT(11)
-#define BIT_FS_BF0_PRETO_INT_EN BIT(10)
-#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9)
-
-/* 2 REG_FE1IMR (Offset 0x0120) */
-
-#define BIT_FS_LTE_COEX_EN BIT(6)
-
-/* 2 REG_FE1IMR (Offset 0x0120) */
-
-#define BIT_FS_WLACTOFF_INT_EN BIT(5)
-#define BIT_FS_WLACTON_INT_EN BIT(4)
-#define BIT_FS_BTCMD_INT_EN BIT(3)
-
-/* 2 REG_FE1IMR (Offset 0x0120) */
-
-#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2)
-
-/* 2 REG_FE1IMR (Offset 0x0120) */
-
-#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1)
-
-/* 2 REG_FE1IMR (Offset 0x0120) */
-
-#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0)
-
-/* 2 REG_FE1ISR (Offset 0x0124) */
-
-#define BIT_FS_RXDMA2_DONE_INT BIT(28)
-#define BIT_FS_RXDONE3_INT BIT(27)
-#define BIT_FS_RXDONE2_INT BIT(26)
-#define BIT_FS_RX_BCN_P4_INT BIT(25)
-#define BIT_FS_RX_BCN_P3_INT BIT(24)
-#define BIT_FS_RX_BCN_P2_INT BIT(23)
-#define BIT_FS_RX_BCN_P1_INT BIT(22)
-#define BIT_FS_RX_BCN_P0_INT BIT(21)
-#define BIT_FS_RX_UMD0_INT BIT(20)
-#define BIT_FS_RX_UMD1_INT BIT(19)
-#define BIT_FS_RX_BMD0_INT BIT(18)
-#define BIT_FS_RX_BMD1_INT BIT(17)
-#define BIT_FS_RXDONE_INT BIT(16)
-#define BIT_FS_WWLAN_INT BIT(15)
-#define BIT_FS_SOUND_DONE_INT BIT(14)
-#define BIT_FS_LP_STBY_INT BIT(13)
-#define BIT_FS_TRL_MTR_INT BIT(12)
-#define BIT_FS_BF1_PRETO_INT BIT(11)
-#define BIT_FS_BF0_PRETO_INT BIT(10)
-#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9)
-
-/* 2 REG_FE1ISR (Offset 0x0124) */
-
-#define BIT_FS_LTE_COEX_INT BIT(6)
-
-/* 2 REG_FE1ISR (Offset 0x0124) */
-
-#define BIT_FS_WLACTOFF_INT BIT(5)
-#define BIT_FS_WLACTON_INT BIT(4)
-#define BIT_FS_BCN_RX_INT_INT BIT(3)
-
-/* 2 REG_FE1ISR (Offset 0x0124) */
-
-#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2)
-
-/* 2 REG_FE1ISR (Offset 0x0124) */
-
-#define BIT_FS_TRPC_TO_INT BIT(1)
-
-/* 2 REG_FE1ISR (Offset 0x0124) */
-
-#define BIT_FS_RPC_O_T_INT BIT(0)
-
-/* 2 REG_CPWM (Offset 0x012C) */
-
-#define BIT_CPWM_TOGGLING BIT(31)
-
-#define BIT_SHIFT_CPWM_MOD 24
-#define BIT_MASK_CPWM_MOD 0x7f
-#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD)
-#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_SIFS_OVERSPEC_INT_EN BIT(14)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_DDMA1_LP_INT_EN BIT(11)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_DDMA1_HP_INT_EN BIT(10)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_DDMA0_LP_INT_EN BIT(9)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_DDMA0_HP_INT_EN BIT(8)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TRXRPT_INT_EN BIT(7)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_C2H_W_READY_INT_EN BIT(6)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_HRCV_INT_EN BIT(5)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_H2CCMD_INT_EN BIT(4)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXPKTIN_INT_EN BIT(3)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_ERRORHDL_INT_EN BIT(2)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXCCX_INT_EN BIT(1)
-
-/* 2 REG_FWIMR (Offset 0x0130) */
-
-#define BIT_FS_TXCLOSE_INT_EN BIT(0)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNOK_MB7_INT BIT(31)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNOK_MB6_INT BIT(30)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNOK_MB5_INT BIT(29)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNOK_MB4_INT BIT(28)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNOK_MB3_INT BIT(27)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNOK_MB2_INT BIT(26)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNOK_MB1_INT BIT(25)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNOK_MB0_INT BIT(24)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNERR_MB7_INT BIT(23)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNERR_MB6_INT BIT(22)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNERR_MB5_INT BIT(21)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNERR_MB4_INT BIT(20)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNERR_MB3_INT BIT(19)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNERR_MB2_INT BIT(18)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNERR_MB1_INT BIT(17)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXBCNERR_MB0_INT BIT(16)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_CPU_MGQ_TXDONE_INT BIT(15)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_SIFS_OVERSPEC_INT BIT(14)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_MGNTQFF_TO_INT BIT(12)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_DDMA1_LP_INT BIT(11)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_DDMA1_HP_INT BIT(10)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_DDMA0_LP_INT BIT(9)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_DDMA0_HP_INT BIT(8)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TRXRPT_INT BIT(7)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_C2H_W_READY_INT BIT(6)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_HRCV_INT BIT(5)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_H2CCMD_INT BIT(4)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXPKTIN_INT BIT(3)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_ERRORHDL_INT BIT(2)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXCCX_INT BIT(1)
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_TXCLOSE_INT BIT(0)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_PS_TIMER_C_INT_EN BIT(19)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_PS_TIMER_B_INT_EN BIT(18)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_PS_TIMER_A_INT_EN BIT(17)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_PS_TIMEOUT2_EN BIT(15)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_PS_TIMEOUT1_EN BIT(14)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_PS_TIMEOUT0_EN BIT(13)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_GTINT8_EN BIT(8)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_GTINT7_EN BIT(7)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_GTINT6_EN BIT(6)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_GTINT5_EN BIT(5)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_GTINT4_EN BIT(4)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_GTINT3_EN BIT(3)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_GTINT2_EN BIT(2)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_GTINT1_EN BIT(1)
-
-/* 2 REG_FTIMR (Offset 0x0138) */
-
-#define BIT_FS_GTINT0_EN BIT(0)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_PS_TIMER_C_EARLY__INT BIT(23)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_PS_TIMER_B_EARLY__INT BIT(22)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_PS_TIMER_A_EARLY__INT BIT(21)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_PS_TIMER_C_INT BIT(19)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_PS_TIMER_B_INT BIT(18)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_PS_TIMER_A_INT BIT(17)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_CPUMGQ_TX_TIMER_INT BIT(16)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_PS_TIMEOUT2_INT BIT(15)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_PS_TIMEOUT1_INT BIT(14)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_PS_TIMEOUT0_INT BIT(13)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_GTINT8_INT BIT(8)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_GTINT7_INT BIT(7)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_GTINT6_INT BIT(6)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_GTINT5_INT BIT(5)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_GTINT4_INT BIT(4)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_GTINT3_INT BIT(3)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_GTINT2_INT BIT(2)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_GTINT1_INT BIT(1)
-
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_FS_GTINT0_INT BIT(0)
-
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-
-#define BIT_SHIFT_PKTBUF_WRITE_EN 24
-#define BIT_MASK_PKTBUF_WRITE_EN 0xff
-#define BIT_PKTBUF_WRITE_EN(x) \
- (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN)
-#define BIT_GET_PKTBUF_WRITE_EN(x) \
- (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN)
-
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-
-#define BIT_TXRPTBUF_DBG BIT(23)
-
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-
-#define BIT_TXPKTBUF_DBG_V2 BIT(20)
-
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-
-#define BIT_RXPKTBUF_DBG BIT(16)
-
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-
-#define BIT_SHIFT_PKTBUF_DBG_ADDR 0
-#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff
-#define BIT_PKTBUF_DBG_ADDR(x) \
- (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR)
-#define BIT_GET_PKTBUF_DBG_ADDR(x) \
- (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR)
-
-/* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */
-
-#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0
-#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_L(x) \
- (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L)
-#define BIT_GET_PKTBUF_DBG_DATA_L(x) \
- (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L)
-
-/* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */
-
-#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0
-#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_H(x) \
- (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H)
-#define BIT_GET_PKTBUF_DBG_DATA_H(x) \
- (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H)
-
-/* 2 REG_CPWM2 (Offset 0x014C) */
-
-#define BIT_SHIFT_L0S_TO_RCVY_NUM 16
-#define BIT_MASK_L0S_TO_RCVY_NUM 0xff
-#define BIT_L0S_TO_RCVY_NUM(x) \
- (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM)
-#define BIT_GET_L0S_TO_RCVY_NUM(x) \
- (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM)
-
-#define BIT_CPWM2_TOGGLING BIT(15)
-
-#define BIT_SHIFT_CPWM2_MOD 0
-#define BIT_MASK_CPWM2_MOD 0x7fff
-#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD)
-#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD)
-
-/* 2 REG_TC0_CTRL (Offset 0x0150) */
-
-#define BIT_TC0INT_EN BIT(26)
-#define BIT_TC0MODE BIT(25)
-#define BIT_TC0EN BIT(24)
-
-#define BIT_SHIFT_TC0DATA 0
-#define BIT_MASK_TC0DATA 0xffffff
-#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA)
-#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA)
-
-/* 2 REG_TC1_CTRL (Offset 0x0154) */
-
-#define BIT_TC1INT_EN BIT(26)
-#define BIT_TC1MODE BIT(25)
-#define BIT_TC1EN BIT(24)
-
-#define BIT_SHIFT_TC1DATA 0
-#define BIT_MASK_TC1DATA 0xffffff
-#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA)
-#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA)
-
-/* 2 REG_TC2_CTRL (Offset 0x0158) */
-
-#define BIT_TC2INT_EN BIT(26)
-#define BIT_TC2MODE BIT(25)
-#define BIT_TC2EN BIT(24)
-
-#define BIT_SHIFT_TC2DATA 0
-#define BIT_MASK_TC2DATA 0xffffff
-#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA)
-#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA)
-
-/* 2 REG_TC3_CTRL (Offset 0x015C) */
-
-#define BIT_TC3INT_EN BIT(26)
-#define BIT_TC3MODE BIT(25)
-#define BIT_TC3EN BIT(24)
-
-#define BIT_SHIFT_TC3DATA 0
-#define BIT_MASK_TC3DATA 0xffffff
-#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA)
-#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA)
-
-/* 2 REG_TC4_CTRL (Offset 0x0160) */
-
-#define BIT_TC4INT_EN BIT(26)
-#define BIT_TC4MODE BIT(25)
-#define BIT_TC4EN BIT(24)
-
-#define BIT_SHIFT_TC4DATA 0
-#define BIT_MASK_TC4DATA 0xffffff
-#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA)
-#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA)
-
-/* 2 REG_TCUNIT_BASE (Offset 0x0164) */
-
-#define BIT_SHIFT_TCUNIT_BASE 0
-#define BIT_MASK_TCUNIT_BASE 0x3fff
-#define BIT_TCUNIT_BASE(x) \
- (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE)
-#define BIT_GET_TCUNIT_BASE(x) \
- (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE)
-
-/* 2 REG_TC5_CTRL (Offset 0x0168) */
-
-#define BIT_TC5INT_EN BIT(26)
-
-/* 2 REG_TC5_CTRL (Offset 0x0168) */
-
-#define BIT_TC5MODE BIT(25)
-#define BIT_TC5EN BIT(24)
-
-#define BIT_SHIFT_TC5DATA 0
-#define BIT_MASK_TC5DATA 0xffffff
-#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA)
-#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA)
-
-/* 2 REG_TC6_CTRL (Offset 0x016C) */
-
-#define BIT_TC6INT_EN BIT(26)
-
-/* 2 REG_TC6_CTRL (Offset 0x016C) */
-
-#define BIT_TC6MODE BIT(25)
-#define BIT_TC6EN BIT(24)
-
-#define BIT_SHIFT_TC6DATA 0
-#define BIT_MASK_TC6DATA 0xffffff
-#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA)
-#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA)
-
-/* 2 REG_MBIST_FAIL (Offset 0x0170) */
-
-#define BIT_SHIFT_8051_MBIST_FAIL 26
-#define BIT_MASK_8051_MBIST_FAIL 0x7
-#define BIT_8051_MBIST_FAIL(x) \
- (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL)
-#define BIT_GET_8051_MBIST_FAIL(x) \
- (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL)
-
-#define BIT_SHIFT_USB_MBIST_FAIL 24
-#define BIT_MASK_USB_MBIST_FAIL 0x3
-#define BIT_USB_MBIST_FAIL(x) \
- (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL)
-#define BIT_GET_USB_MBIST_FAIL(x) \
- (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL)
-
-#define BIT_SHIFT_PCIE_MBIST_FAIL 16
-#define BIT_MASK_PCIE_MBIST_FAIL 0x3f
-#define BIT_PCIE_MBIST_FAIL(x) \
- (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL)
-#define BIT_GET_PCIE_MBIST_FAIL(x) \
- (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL)
-
-/* 2 REG_MBIST_FAIL (Offset 0x0170) */
-
-#define BIT_SHIFT_MAC_MBIST_FAIL 0
-#define BIT_MASK_MAC_MBIST_FAIL 0xfff
-#define BIT_MAC_MBIST_FAIL(x) \
- (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL)
-#define BIT_GET_MAC_MBIST_FAIL(x) \
- (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL)
-
-/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
-
-#define BIT_SHIFT_8051_MBIST_START_PAUSE 26
-#define BIT_MASK_8051_MBIST_START_PAUSE 0x7
-#define BIT_8051_MBIST_START_PAUSE(x) \
- (((x) & BIT_MASK_8051_MBIST_START_PAUSE) \
- << BIT_SHIFT_8051_MBIST_START_PAUSE)
-#define BIT_GET_8051_MBIST_START_PAUSE(x) \
- (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & \
- BIT_MASK_8051_MBIST_START_PAUSE)
-
-#define BIT_SHIFT_USB_MBIST_START_PAUSE 24
-#define BIT_MASK_USB_MBIST_START_PAUSE 0x3
-#define BIT_USB_MBIST_START_PAUSE(x) \
- (((x) & BIT_MASK_USB_MBIST_START_PAUSE) \
- << BIT_SHIFT_USB_MBIST_START_PAUSE)
-#define BIT_GET_USB_MBIST_START_PAUSE(x) \
- (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & \
- BIT_MASK_USB_MBIST_START_PAUSE)
-
-#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16
-#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f
-#define BIT_PCIE_MBIST_START_PAUSE(x) \
- (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) \
- << BIT_SHIFT_PCIE_MBIST_START_PAUSE)
-#define BIT_GET_PCIE_MBIST_START_PAUSE(x) \
- (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & \
- BIT_MASK_PCIE_MBIST_START_PAUSE)
-
-/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
-
-#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0
-#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff
-#define BIT_MAC_MBIST_START_PAUSE(x) \
- (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) \
- << BIT_SHIFT_MAC_MBIST_START_PAUSE)
-#define BIT_GET_MAC_MBIST_START_PAUSE(x) \
- (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & \
- BIT_MASK_MAC_MBIST_START_PAUSE)
-
-/* 2 REG_MBIST_DONE (Offset 0x0178) */
-
-#define BIT_SHIFT_8051_MBIST_DONE 26
-#define BIT_MASK_8051_MBIST_DONE 0x7
-#define BIT_8051_MBIST_DONE(x) \
- (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE)
-#define BIT_GET_8051_MBIST_DONE(x) \
- (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE)
-
-#define BIT_SHIFT_USB_MBIST_DONE 24
-#define BIT_MASK_USB_MBIST_DONE 0x3
-#define BIT_USB_MBIST_DONE(x) \
- (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE)
-#define BIT_GET_USB_MBIST_DONE(x) \
- (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE)
-
-#define BIT_SHIFT_PCIE_MBIST_DONE 16
-#define BIT_MASK_PCIE_MBIST_DONE 0x3f
-#define BIT_PCIE_MBIST_DONE(x) \
- (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE)
-#define BIT_GET_PCIE_MBIST_DONE(x) \
- (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE)
-
-/* 2 REG_MBIST_DONE (Offset 0x0178) */
-
-#define BIT_SHIFT_MAC_MBIST_DONE 0
-#define BIT_MASK_MAC_MBIST_DONE 0xfff
-#define BIT_MAC_MBIST_DONE(x) \
- (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE)
-#define BIT_GET_MAC_MBIST_DONE(x) \
- (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE)
-
-/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */
-
-#define BIT_SHIFT_MBIST_FAIL_NRML 0
-#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL
-#define BIT_MBIST_FAIL_NRML(x) \
- (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML)
-#define BIT_GET_MBIST_FAIL_NRML(x) \
- (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML)
-
-/* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */
-
-#define BIT_SHIFT_IPS_CFG_ADDR 0
-#define BIT_MASK_IPS_CFG_ADDR 0xff
-#define BIT_IPS_CFG_ADDR(x) \
- (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR)
-#define BIT_GET_IPS_CFG_ADDR(x) \
- (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR)
-
-/* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */
-
-#define BIT_SHIFT_IPS_CFG_DATA 0
-#define BIT_MASK_IPS_CFG_DATA 0xffffffffL
-#define BIT_IPS_CFG_DATA(x) \
- (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA)
-#define BIT_GET_IPS_CFG_DATA(x) \
- (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA)
-
-/* 2 REG_TMETER (Offset 0x0190) */
-
-#define BIT_TEMP_VALID BIT(31)
-
-#define BIT_SHIFT_TEMP_VALUE 24
-#define BIT_MASK_TEMP_VALUE 0x3f
-#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE)
-#define BIT_GET_TEMP_VALUE(x) \
- (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE)
-
-#define BIT_SHIFT_REG_TMETER_TIMER 8
-#define BIT_MASK_REG_TMETER_TIMER 0xfff
-#define BIT_REG_TMETER_TIMER(x) \
- (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER)
-#define BIT_GET_REG_TMETER_TIMER(x) \
- (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER)
-
-#define BIT_SHIFT_REG_TEMP_DELTA 2
-#define BIT_MASK_REG_TEMP_DELTA 0x3f
-#define BIT_REG_TEMP_DELTA(x) \
- (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA)
-#define BIT_GET_REG_TEMP_DELTA(x) \
- (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA)
-
-#define BIT_REG_TMETER_EN BIT(0)
-
-/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
-
-#define BIT_SHIFT_OSC_32K_CLKGEN_0 16
-#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff
-#define BIT_OSC_32K_CLKGEN_0(x) \
- (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0)
-#define BIT_GET_OSC_32K_CLKGEN_0(x) \
- (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0)
-
-/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
-
-#define BIT_SHIFT_OSC_32K_RES_COMP 4
-#define BIT_MASK_OSC_32K_RES_COMP 0x3
-#define BIT_OSC_32K_RES_COMP(x) \
- (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP)
-#define BIT_GET_OSC_32K_RES_COMP(x) \
- (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP)
-
-#define BIT_OSC_32K_OUT_SEL BIT(3)
-
-/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
-
-#define BIT_ISO_WL_2_OSC_32K BIT(1)
-
-/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
-
-#define BIT_POW_CKGEN BIT(0)
-
-/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
-
-#define BIT_CAL_32K_REG_WR BIT(31)
-#define BIT_CAL_32K_DBG_SEL BIT(22)
-
-#define BIT_SHIFT_CAL_32K_REG_ADDR 16
-#define BIT_MASK_CAL_32K_REG_ADDR 0x3f
-#define BIT_CAL_32K_REG_ADDR(x) \
- (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR)
-#define BIT_GET_CAL_32K_REG_ADDR(x) \
- (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR)
-
-/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
-
-#define BIT_SHIFT_CAL_32K_REG_DATA 0
-#define BIT_MASK_CAL_32K_REG_DATA 0xffff
-#define BIT_CAL_32K_REG_DATA(x) \
- (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA)
-#define BIT_GET_CAL_32K_REG_DATA(x) \
- (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA)
-
-/* 2 REG_C2HEVT (Offset 0x01A0) */
-
-#define BIT_SHIFT_C2HEVT_MSG 0
-#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL
-#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG)
-#define BIT_GET_C2HEVT_MSG(x) \
- (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG)
-
-/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */
-
-#define BIT_SHIFT_SW_DEFINED_PAGE1 0
-#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL
-#define BIT_SW_DEFINED_PAGE1(x) \
- (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1)
-#define BIT_GET_SW_DEFINED_PAGE1(x) \
- (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1)
-
-/* 2 REG_MCUTST_I (Offset 0x01C0) */
-
-#define BIT_SHIFT_MCUDMSG_I 0
-#define BIT_MASK_MCUDMSG_I 0xffffffffL
-#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I)
-#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I)
-
-/* 2 REG_MCUTST_II (Offset 0x01C4) */
-
-#define BIT_SHIFT_MCUDMSG_II 0
-#define BIT_MASK_MCUDMSG_II 0xffffffffL
-#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II)
-#define BIT_GET_MCUDMSG_II(x) \
- (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II)
-
-/* 2 REG_FMETHR (Offset 0x01C8) */
-
-#define BIT_FMSG_INT BIT(31)
-
-#define BIT_SHIFT_FW_MSG 0
-#define BIT_MASK_FW_MSG 0xffffffffL
-#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG)
-#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG)
-
-/* 2 REG_HMETFR (Offset 0x01CC) */
-
-#define BIT_SHIFT_HRCV_MSG 24
-#define BIT_MASK_HRCV_MSG 0xff
-#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG)
-#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG)
-
-#define BIT_INT_BOX3 BIT(3)
-#define BIT_INT_BOX2 BIT(2)
-#define BIT_INT_BOX1 BIT(1)
-#define BIT_INT_BOX0 BIT(0)
-
-/* 2 REG_HMEBOX0 (Offset 0x01D0) */
-
-#define BIT_SHIFT_HOST_MSG_0 0
-#define BIT_MASK_HOST_MSG_0 0xffffffffL
-#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0)
-#define BIT_GET_HOST_MSG_0(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0)
-
-/* 2 REG_HMEBOX1 (Offset 0x01D4) */
-
-#define BIT_SHIFT_HOST_MSG_1 0
-#define BIT_MASK_HOST_MSG_1 0xffffffffL
-#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1)
-#define BIT_GET_HOST_MSG_1(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1)
-
-/* 2 REG_HMEBOX2 (Offset 0x01D8) */
-
-#define BIT_SHIFT_HOST_MSG_2 0
-#define BIT_MASK_HOST_MSG_2 0xffffffffL
-#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2)
-#define BIT_GET_HOST_MSG_2(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2)
-
-/* 2 REG_HMEBOX3 (Offset 0x01DC) */
-
-#define BIT_SHIFT_HOST_MSG_3 0
-#define BIT_MASK_HOST_MSG_3 0xffffffffL
-#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3)
-#define BIT_GET_HOST_MSG_3(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3)
-
-/* 2 REG_LLT_INIT (Offset 0x01E0) */
-
-#define BIT_SHIFT_LLTE_RWM 30
-#define BIT_MASK_LLTE_RWM 0x3
-#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM)
-#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM)
-
-/* 2 REG_LLT_INIT (Offset 0x01E0) */
-
-#define BIT_SHIFT_LLTINI_PDATA_V1 16
-#define BIT_MASK_LLTINI_PDATA_V1 0xfff
-#define BIT_LLTINI_PDATA_V1(x) \
- (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1)
-#define BIT_GET_LLTINI_PDATA_V1(x) \
- (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1)
-
-/* 2 REG_LLT_INIT (Offset 0x01E0) */
-
-#define BIT_SHIFT_LLTINI_HDATA_V1 0
-#define BIT_MASK_LLTINI_HDATA_V1 0xfff
-#define BIT_LLTINI_HDATA_V1(x) \
- (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1)
-#define BIT_GET_LLTINI_HDATA_V1(x) \
- (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1)
-
-/* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */
-
-#define BIT_SHIFT_LLTINI_ADDR_V1 0
-#define BIT_MASK_LLTINI_ADDR_V1 0xfff
-#define BIT_LLTINI_ADDR_V1(x) \
- (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1)
-#define BIT_GET_LLTINI_ADDR_V1(x) \
- (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1)
-
-/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
-
-#define BIT_SHIFT_BB_WRITE_READ 30
-#define BIT_MASK_BB_WRITE_READ 0x3
-#define BIT_BB_WRITE_READ(x) \
- (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ)
-#define BIT_GET_BB_WRITE_READ(x) \
- (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ)
-
-/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
-
-#define BIT_SHIFT_BB_WRITE_EN 12
-#define BIT_MASK_BB_WRITE_EN 0xf
-#define BIT_BB_WRITE_EN(x) \
- (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN)
-#define BIT_GET_BB_WRITE_EN(x) \
- (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN)
-
-#define BIT_SHIFT_BB_ADDR 2
-#define BIT_MASK_BB_ADDR 0x1ff
-#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR)
-#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR)
-
-/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
-
-#define BIT_BB_ERRACC BIT(0)
-
-/* 2 REG_BB_ACCESS_DATA (Offset 0x01EC) */
-
-#define BIT_SHIFT_BB_DATA 0
-#define BIT_MASK_BB_DATA 0xffffffffL
-#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA)
-#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA)
-
-/* 2 REG_HMEBOX_E0 (Offset 0x01F0) */
-
-#define BIT_SHIFT_HMEBOX_E0 0
-#define BIT_MASK_HMEBOX_E0 0xffffffffL
-#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0)
-#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0)
-
-/* 2 REG_HMEBOX_E1 (Offset 0x01F4) */
-
-#define BIT_SHIFT_HMEBOX_E1 0
-#define BIT_MASK_HMEBOX_E1 0xffffffffL
-#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1)
-#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1)
-
-/* 2 REG_HMEBOX_E2 (Offset 0x01F8) */
-
-#define BIT_SHIFT_HMEBOX_E2 0
-#define BIT_MASK_HMEBOX_E2 0xffffffffL
-#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2)
-#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2)
-
-/* 2 REG_HMEBOX_E3 (Offset 0x01FC) */
-
-#define BIT_LD_RQPN BIT(31)
-
-#define BIT_SHIFT_HMEBOX_E3 0
-#define BIT_MASK_HMEBOX_E3 0xffffffffL
-#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3)
-#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3)
-
-/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */
-
-#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16
-#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff
-#define BIT_TX_OQT_HE_FREE_SPACE_V1(x) \
- (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) \
- << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1)
-#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) \
- (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & \
- BIT_MASK_TX_OQT_HE_FREE_SPACE_V1)
-
-/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */
-
-#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0
-#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff
-#define BIT_TX_OQT_NL_FREE_SPACE_V1(x) \
- (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) \
- << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1)
-#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) \
- (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & \
- BIT_MASK_TX_OQT_NL_FREE_SPACE_V1)
-
-/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
-
-#define BIT_BCN_VALID_1_V1 BIT(31)
-
-/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
-
-#define BIT_SHIFT_BCN_HEAD_1_V1 16
-#define BIT_MASK_BCN_HEAD_1_V1 0xfff
-#define BIT_BCN_HEAD_1_V1(x) \
- (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1)
-#define BIT_GET_BCN_HEAD_1_V1(x) \
- (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1)
-
-#define BIT_BCN_VALID_V1 BIT(15)
-
-/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
-
-#define BIT_SHIFT_BCN_HEAD_V1 0
-#define BIT_MASK_BCN_HEAD_V1 0xfff
-#define BIT_BCN_HEAD_V1(x) \
- (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1)
-#define BIT_GET_BCN_HEAD_V1(x) \
- (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1)
-
-/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
-
-#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24
-#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff
-#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \
- (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) \
- << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
-#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \
- (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & \
- BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
-
-/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
-
-#define BIT_SHIFT_LLT_FREE_PAGE_V1 8
-#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff
-#define BIT_LLT_FREE_PAGE_V1(x) \
- (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1)
-#define BIT_GET_LLT_FREE_PAGE_V1(x) \
- (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1)
-
-/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */
-
-#define BIT_SHIFT_BLK_DESC_NUM 4
-#define BIT_MASK_BLK_DESC_NUM 0xf
-#define BIT_BLK_DESC_NUM(x) \
- (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM)
-#define BIT_GET_BLK_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM)
-
-/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
-
-#define BIT_R_BCN_HEAD_SEL BIT(3)
-#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2)
-#define BIT_LLT_DBG_SEL BIT(1)
-#define BIT_AUTO_INIT_LLT_V1 BIT(0)
-
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
-
-#define BIT_EM_CHKSUM_FIN BIT(31)
-#define BIT_EMN_PCIE_DMA_MOD BIT(30)
-
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
-
-#define BIT_EN_TXQUE_CLR BIT(29)
-#define BIT_EN_PCIE_FIFO_MODE BIT(28)
-
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
-
-#define BIT_SHIFT_PG_UNDER_TH_V1 16
-#define BIT_MASK_PG_UNDER_TH_V1 0xfff
-#define BIT_PG_UNDER_TH_V1(x) \
- (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1)
-#define BIT_GET_PG_UNDER_TH_V1(x) \
- (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1)
-
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
-
-#define BIT_RESTORE_H2C_ADDRESS BIT(15)
-
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
-
-#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13)
-#define BIT_RST_RDPTR BIT(12)
-#define BIT_RST_WRPTR BIT(11)
-#define BIT_CHK_PG_TH_EN BIT(10)
-#define BIT_DROP_DATA_EN BIT(9)
-#define BIT_CHECK_OFFSET_EN BIT(8)
-
-#define BIT_SHIFT_CHECK_OFFSET 0
-#define BIT_MASK_CHECK_OFFSET 0xff
-#define BIT_CHECK_OFFSET(x) \
- (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET)
-#define BIT_GET_CHECK_OFFSET(x) \
- (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET)
-
-/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
-
-#define BIT_HI_OQT_UDN BIT(17)
-#define BIT_HI_OQT_OVF BIT(16)
-#define BIT_PAYLOAD_CHKSUM_ERR BIT(15)
-#define BIT_PAYLOAD_UDN BIT(14)
-#define BIT_PAYLOAD_OVF BIT(13)
-#define BIT_DSC_CHKSUM_FAIL BIT(12)
-#define BIT_UNKNOWN_QSEL BIT(11)
-#define BIT_EP_QSEL_DIFF BIT(10)
-#define BIT_TX_OFFS_UNMATCH BIT(9)
-#define BIT_TXOQT_UDN BIT(8)
-#define BIT_TXOQT_OVF BIT(7)
-#define BIT_TXDMA_SFF_UDN BIT(6)
-#define BIT_TXDMA_SFF_OVF BIT(5)
-#define BIT_LLT_NULL_PG BIT(4)
-#define BIT_PAGE_UDN BIT(3)
-#define BIT_PAGE_OVF BIT(2)
-#define BIT_TXFF_PG_UDN BIT(1)
-#define BIT_TXFF_PG_OVF BIT(0)
-
-/* 2 REG_TQPNT1 (Offset 0x0218) */
-
-#define BIT_SHIFT_HPQ_HIGH_TH_V1 16
-#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff
-#define BIT_HPQ_HIGH_TH_V1(x) \
- (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1)
-#define BIT_GET_HPQ_HIGH_TH_V1(x) \
- (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1)
-
-/* 2 REG_TQPNT1 (Offset 0x0218) */
-
-#define BIT_SHIFT_HPQ_LOW_TH_V1 0
-#define BIT_MASK_HPQ_LOW_TH_V1 0xfff
-#define BIT_HPQ_LOW_TH_V1(x) \
- (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1)
-#define BIT_GET_HPQ_LOW_TH_V1(x) \
- (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1)
-
-/* 2 REG_TQPNT2 (Offset 0x021C) */
-
-#define BIT_SHIFT_NPQ_HIGH_TH_V1 16
-#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff
-#define BIT_NPQ_HIGH_TH_V1(x) \
- (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1)
-#define BIT_GET_NPQ_HIGH_TH_V1(x) \
- (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1)
-
-/* 2 REG_TQPNT2 (Offset 0x021C) */
-
-#define BIT_SHIFT_NPQ_LOW_TH_V1 0
-#define BIT_MASK_NPQ_LOW_TH_V1 0xfff
-#define BIT_NPQ_LOW_TH_V1(x) \
- (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1)
-#define BIT_GET_NPQ_LOW_TH_V1(x) \
- (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1)
-
-/* 2 REG_TQPNT3 (Offset 0x0220) */
-
-#define BIT_SHIFT_LPQ_HIGH_TH_V1 16
-#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff
-#define BIT_LPQ_HIGH_TH_V1(x) \
- (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1)
-#define BIT_GET_LPQ_HIGH_TH_V1(x) \
- (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1)
-
-/* 2 REG_TQPNT3 (Offset 0x0220) */
-
-#define BIT_SHIFT_LPQ_LOW_TH_V1 0
-#define BIT_MASK_LPQ_LOW_TH_V1 0xfff
-#define BIT_LPQ_LOW_TH_V1(x) \
- (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1)
-#define BIT_GET_LPQ_LOW_TH_V1(x) \
- (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1)
-
-/* 2 REG_TQPNT4 (Offset 0x0224) */
-
-#define BIT_SHIFT_EXQ_HIGH_TH_V1 16
-#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff
-#define BIT_EXQ_HIGH_TH_V1(x) \
- (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1)
-#define BIT_GET_EXQ_HIGH_TH_V1(x) \
- (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1)
-
-/* 2 REG_TQPNT4 (Offset 0x0224) */
-
-#define BIT_SHIFT_EXQ_LOW_TH_V1 0
-#define BIT_MASK_EXQ_LOW_TH_V1 0xfff
-#define BIT_EXQ_LOW_TH_V1(x) \
- (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1)
-#define BIT_GET_EXQ_LOW_TH_V1(x) \
- (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1)
-
-/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
-
-#define BIT_SHIFT_TXPKTNUM_H 16
-#define BIT_MASK_TXPKTNUM_H 0xffff
-#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H)
-#define BIT_GET_TXPKTNUM_H(x) \
- (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H)
-
-/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
-
-#define BIT_SHIFT_TXPKTNUM_V2 0
-#define BIT_MASK_TXPKTNUM_V2 0xffff
-#define BIT_TXPKTNUM_V2(x) \
- (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2)
-#define BIT_GET_TXPKTNUM_V2(x) \
- (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2)
-
-/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */
-
-#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19)
-#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18)
-#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17)
-#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16)
-
-/* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */
-
-#define BIT_SHIFT_HPQ_AVAL_PG_V1 16
-#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff
-#define BIT_HPQ_AVAL_PG_V1(x) \
- (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1)
-#define BIT_GET_HPQ_AVAL_PG_V1(x) \
- (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1)
-
-#define BIT_SHIFT_HPQ_V1 0
-#define BIT_MASK_HPQ_V1 0xfff
-#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1)
-#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1)
-
-/* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */
-
-#define BIT_SHIFT_LPQ_AVAL_PG_V1 16
-#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff
-#define BIT_LPQ_AVAL_PG_V1(x) \
- (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1)
-#define BIT_GET_LPQ_AVAL_PG_V1(x) \
- (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1)
-
-#define BIT_SHIFT_LPQ_V1 0
-#define BIT_MASK_LPQ_V1 0xfff
-#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1)
-#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1)
-
-/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */
-
-#define BIT_SHIFT_NPQ_AVAL_PG_V1 16
-#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff
-#define BIT_NPQ_AVAL_PG_V1(x) \
- (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1)
-#define BIT_GET_NPQ_AVAL_PG_V1(x) \
- (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1)
-
-/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */
-
-#define BIT_SHIFT_NPQ_V1 0
-#define BIT_MASK_NPQ_V1 0xfff
-#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1)
-#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1)
-
-/* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */
-
-#define BIT_SHIFT_EXQ_AVAL_PG_V1 16
-#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff
-#define BIT_EXQ_AVAL_PG_V1(x) \
- (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1)
-#define BIT_GET_EXQ_AVAL_PG_V1(x) \
- (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1)
-
-#define BIT_SHIFT_EXQ_V1 0
-#define BIT_MASK_EXQ_V1 0xfff
-#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1)
-#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1)
-
-/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */
-
-#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16
-#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff
-#define BIT_PUBQ_AVAL_PG_V1(x) \
- (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1)
-#define BIT_GET_PUBQ_AVAL_PG_V1(x) \
- (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1)
-
-#define BIT_SHIFT_PUBQ_V1 0
-#define BIT_MASK_PUBQ_V1 0xfff
-#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1)
-#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1)
-
-/* 2 REG_H2C_HEAD (Offset 0x0244) */
-
-#define BIT_SHIFT_H2C_HEAD 0
-#define BIT_MASK_H2C_HEAD 0x3ffff
-#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD)
-#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD)
-
-/* 2 REG_H2C_TAIL (Offset 0x0248) */
-
-#define BIT_SHIFT_H2C_TAIL 0
-#define BIT_MASK_H2C_TAIL 0x3ffff
-#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL)
-#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL)
-
-/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */
-
-#define BIT_SHIFT_H2C_READ_ADDR 0
-#define BIT_MASK_H2C_READ_ADDR 0x3ffff
-#define BIT_H2C_READ_ADDR(x) \
- (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR)
-#define BIT_GET_H2C_READ_ADDR(x) \
- (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR)
-
-/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */
-
-#define BIT_SHIFT_H2C_WR_ADDR 0
-#define BIT_MASK_H2C_WR_ADDR 0x3ffff
-#define BIT_H2C_WR_ADDR(x) \
- (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR)
-#define BIT_GET_H2C_WR_ADDR(x) \
- (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR)
-
-/* 2 REG_H2C_INFO (Offset 0x0254) */
-
-#define BIT_H2C_SPACE_VLD BIT(3)
-#define BIT_H2C_WR_ADDR_RST BIT(2)
-
-#define BIT_SHIFT_H2C_LEN_SEL 0
-#define BIT_MASK_H2C_LEN_SEL 0x3
-#define BIT_H2C_LEN_SEL(x) \
- (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL)
-#define BIT_GET_H2C_LEN_SEL(x) \
- (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL)
-
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
-
-#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24
-#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff
-#define BIT_RXDMA_AGG_OLD_MOD(x) \
- (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD)
-#define BIT_GET_RXDMA_AGG_OLD_MOD(x) \
- (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD)
-
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
-
-#define BIT_SHIFT_PKT_NUM_WOL 16
-#define BIT_MASK_PKT_NUM_WOL 0xff
-#define BIT_PKT_NUM_WOL(x) \
- (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL)
-#define BIT_GET_PKT_NUM_WOL(x) \
- (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL)
-
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
-
-#define BIT_SHIFT_DMA_AGG_TO 8
-#define BIT_MASK_DMA_AGG_TO 0xf
-#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO)
-#define BIT_GET_DMA_AGG_TO(x) \
- (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO)
-
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
-
-#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0
-#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf
-#define BIT_RXDMA_AGG_PG_TH_V1(x) \
- (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1)
-#define BIT_GET_RXDMA_AGG_PG_TH_V1(x) \
- (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1)
-
-/* 2 REG_RXPKT_NUM (Offset 0x0284) */
-
-#define BIT_SHIFT_RXPKT_NUM 24
-#define BIT_MASK_RXPKT_NUM 0xff
-#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM)
-#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM)
-
-/* 2 REG_RXPKT_NUM (Offset 0x0284) */
-
-#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20
-#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf
-#define BIT_FW_UPD_RDPTR19_TO_16(x) \
- (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) \
- << BIT_SHIFT_FW_UPD_RDPTR19_TO_16)
-#define BIT_GET_FW_UPD_RDPTR19_TO_16(x) \
- (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & \
- BIT_MASK_FW_UPD_RDPTR19_TO_16)
-
-/* 2 REG_RXPKT_NUM (Offset 0x0284) */
-
-#define BIT_RXDMA_REQ BIT(19)
-#define BIT_RW_RELEASE_EN BIT(18)
-#define BIT_RXDMA_IDLE BIT(17)
-#define BIT_RXPKT_RELEASE_POLL BIT(16)
-
-#define BIT_SHIFT_FW_UPD_RDPTR 0
-#define BIT_MASK_FW_UPD_RDPTR 0xffff
-#define BIT_FW_UPD_RDPTR(x) \
- (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR)
-#define BIT_GET_FW_UPD_RDPTR(x) \
- (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR)
-
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
-
-#define BIT_C2H_PKT_OVF BIT(7)
-
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
-
-#define BIT_AGG_CONFGI_ISSUE BIT(6)
-
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
-
-#define BIT_FW_POLL_ISSUE BIT(5)
-#define BIT_RX_DATA_UDN BIT(4)
-#define BIT_RX_SFF_UDN BIT(3)
-#define BIT_RX_SFF_OVF BIT(2)
-
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
-
-#define BIT_RXPKT_OVF BIT(0)
-
-/* 2 REG_RXDMA_DPR (Offset 0x028C) */
-
-#define BIT_SHIFT_RDE_DEBUG 0
-#define BIT_MASK_RDE_DEBUG 0xffffffffL
-#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG)
-#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG)
-
-/* 2 REG_RXDMA_MODE (Offset 0x0290) */
-
-#define BIT_SHIFT_PKTNUM_TH_V2 24
-#define BIT_MASK_PKTNUM_TH_V2 0x1f
-#define BIT_PKTNUM_TH_V2(x) \
- (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2)
-#define BIT_GET_PKTNUM_TH_V2(x) \
- (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2)
-
-#define BIT_TXBA_BREAK_USBAGG BIT(23)
-
-#define BIT_SHIFT_PKTLEN_PARA 16
-#define BIT_MASK_PKTLEN_PARA 0x7
-#define BIT_PKTLEN_PARA(x) \
- (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA)
-#define BIT_GET_PKTLEN_PARA(x) \
- (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA)
-
-/* 2 REG_RXDMA_MODE (Offset 0x0290) */
-
-#define BIT_SHIFT_BURST_SIZE 4
-#define BIT_MASK_BURST_SIZE 0x3
-#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE)
-#define BIT_GET_BURST_SIZE(x) \
- (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE)
-
-#define BIT_SHIFT_BURST_CNT 2
-#define BIT_MASK_BURST_CNT 0x3
-#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT)
-#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT)
-
-/* 2 REG_RXDMA_MODE (Offset 0x0290) */
-
-#define BIT_DMA_MODE BIT(1)
-
-/* 2 REG_C2H_PKT (Offset 0x0294) */
-
-#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24
-#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf
-#define BIT_R_C2H_STR_ADDR_16_TO_19(x) \
- (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) \
- << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19)
-#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) \
- (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & \
- BIT_MASK_R_C2H_STR_ADDR_16_TO_19)
-
-#define BIT_SHIFT_MDIO_PHY_ADDR 24
-#define BIT_MASK_MDIO_PHY_ADDR 0x1f
-#define BIT_MDIO_PHY_ADDR(x) \
- (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR)
-#define BIT_GET_MDIO_PHY_ADDR(x) \
- (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR)
-
-/* 2 REG_C2H_PKT (Offset 0x0294) */
-
-#define BIT_R_C2H_PKT_REQ BIT(16)
-#define BIT_RX_CLOSE_EN BIT(15)
-#define BIT_STOP_BCNQ BIT(14)
-#define BIT_STOP_MGQ BIT(13)
-#define BIT_STOP_VOQ BIT(12)
-#define BIT_STOP_VIQ BIT(11)
-#define BIT_STOP_BEQ BIT(10)
-#define BIT_STOP_BKQ BIT(9)
-#define BIT_STOP_RXQ BIT(8)
-#define BIT_STOP_HI7Q BIT(7)
-#define BIT_STOP_HI6Q BIT(6)
-#define BIT_STOP_HI5Q BIT(5)
-#define BIT_STOP_HI4Q BIT(4)
-#define BIT_STOP_HI3Q BIT(3)
-#define BIT_STOP_HI2Q BIT(2)
-#define BIT_STOP_HI1Q BIT(1)
-
-#define BIT_SHIFT_R_C2H_STR_ADDR 0
-#define BIT_MASK_R_C2H_STR_ADDR 0xffff
-#define BIT_R_C2H_STR_ADDR(x) \
- (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR)
-#define BIT_GET_R_C2H_STR_ADDR(x) \
- (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR)
-
-#define BIT_STOP_HI0Q BIT(0)
-
-/* 2 REG_FWFF_C2H (Offset 0x0298) */
-
-#define BIT_SHIFT_C2H_DMA_ADDR 0
-#define BIT_MASK_C2H_DMA_ADDR 0x3ffff
-#define BIT_C2H_DMA_ADDR(x) \
- (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR)
-#define BIT_GET_C2H_DMA_ADDR(x) \
- (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR)
-
-/* 2 REG_FWFF_CTRL (Offset 0x029C) */
-
-#define BIT_FWFF_DMAPKT_REQ BIT(31)
-
-#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16
-#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff
-#define BIT_FWFF_DMA_PKT_NUM(x) \
- (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM)
-#define BIT_GET_FWFF_DMA_PKT_NUM(x) \
- (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM)
-
-#define BIT_SHIFT_FWFF_STR_ADDR 0
-#define BIT_MASK_FWFF_STR_ADDR 0xffff
-#define BIT_FWFF_STR_ADDR(x) \
- (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR)
-#define BIT_GET_FWFF_STR_ADDR(x) \
- (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR)
-
-/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
-
-#define BIT_SHIFT_FWFF_PKT_QUEUED 16
-#define BIT_MASK_FWFF_PKT_QUEUED 0xff
-#define BIT_FWFF_PKT_QUEUED(x) \
- (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED)
-#define BIT_GET_FWFF_PKT_QUEUED(x) \
- (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED)
-
-/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
-
-#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0
-#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff
-#define BIT_FWFF_PKT_STR_ADDR(x) \
- (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR)
-#define BIT_GET_FWFF_PKT_STR_ADDR(x) \
- (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR)
-
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
-
-#define BIT_PCIEIO_PERSTB_SEL BIT(31)
-
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
-
-#define BIT_SHIFT_PCIE_MAX_RXDMA 28
-#define BIT_MASK_PCIE_MAX_RXDMA 0x7
-#define BIT_PCIE_MAX_RXDMA(x) \
- (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA)
-#define BIT_GET_PCIE_MAX_RXDMA(x) \
- (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA)
-
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
-
-#define BIT_SHIFT_PCIE_MAX_TXDMA 24
-#define BIT_MASK_PCIE_MAX_TXDMA 0x7
-#define BIT_PCIE_MAX_TXDMA(x) \
- (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA)
-#define BIT_GET_PCIE_MAX_TXDMA(x) \
- (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA)
-
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
-
-#define BIT_PCIE_RST_TRXDMA_INTF BIT(20)
-
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
-
-#define BIT_PCIE_EN_SWENT_L23 BIT(17)
-
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
-
-#define BIT_PCIE_EN_HWEXT_L1 BIT(16)
-
-/* 2 REG_INT_MIG (Offset 0x0304) */
-
-#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28
-#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf
-#define BIT_TXTTIMER_MATCH_NUM(x) \
- (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM)
-#define BIT_GET_TXTTIMER_MATCH_NUM(x) \
- (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM)
-
-#define BIT_SHIFT_TXPKT_NUM_MATCH 24
-#define BIT_MASK_TXPKT_NUM_MATCH 0xf
-#define BIT_TXPKT_NUM_MATCH(x) \
- (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH)
-#define BIT_GET_TXPKT_NUM_MATCH(x) \
- (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH)
-
-#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20
-#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf
-#define BIT_RXTTIMER_MATCH_NUM(x) \
- (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM)
-#define BIT_GET_RXTTIMER_MATCH_NUM(x) \
- (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM)
-
-#define BIT_SHIFT_RXPKT_NUM_MATCH 16
-#define BIT_MASK_RXPKT_NUM_MATCH 0xf
-#define BIT_RXPKT_NUM_MATCH(x) \
- (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH)
-#define BIT_GET_RXPKT_NUM_MATCH(x) \
- (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH)
-
-#define BIT_SHIFT_MIGRATE_TIMER 0
-#define BIT_MASK_MIGRATE_TIMER 0xffff
-#define BIT_MIGRATE_TIMER(x) \
- (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER)
-#define BIT_GET_MIGRATE_TIMER(x) \
- (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER)
-
-/* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */
-
-#define BIT_SHIFT_BCNQ_TXBD_DESA 0
-#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_BCNQ_TXBD_DESA(x) \
- (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA)
-#define BIT_GET_BCNQ_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA)
-
-/* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */
-
-#define BIT_SHIFT_MGQ_TXBD_DESA 0
-#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_MGQ_TXBD_DESA(x) \
- (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA)
-#define BIT_GET_MGQ_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA)
-
-/* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */
-
-#define BIT_SHIFT_VOQ_TXBD_DESA 0
-#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_VOQ_TXBD_DESA(x) \
- (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA)
-#define BIT_GET_VOQ_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA)
-
-/* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */
-
-#define BIT_SHIFT_VIQ_TXBD_DESA 0
-#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_VIQ_TXBD_DESA(x) \
- (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA)
-#define BIT_GET_VIQ_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA)
-
-/* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */
-
-#define BIT_SHIFT_BEQ_TXBD_DESA 0
-#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_BEQ_TXBD_DESA(x) \
- (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA)
-#define BIT_GET_BEQ_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA)
-
-/* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */
-
-#define BIT_SHIFT_BKQ_TXBD_DESA 0
-#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_BKQ_TXBD_DESA(x) \
- (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA)
-#define BIT_GET_BKQ_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA)
-
-/* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */
-
-#define BIT_SHIFT_RXQ_RXBD_DESA 0
-#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL
-#define BIT_RXQ_RXBD_DESA(x) \
- (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA)
-#define BIT_GET_RXQ_RXBD_DESA(x) \
- (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA)
-
-/* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */
-
-#define BIT_SHIFT_HI0Q_TXBD_DESA 0
-#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI0Q_TXBD_DESA(x) \
- (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA)
-#define BIT_GET_HI0Q_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA)
-
-/* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */
-
-#define BIT_SHIFT_HI1Q_TXBD_DESA 0
-#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI1Q_TXBD_DESA(x) \
- (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA)
-#define BIT_GET_HI1Q_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA)
-
-/* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */
-
-#define BIT_SHIFT_HI2Q_TXBD_DESA 0
-#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI2Q_TXBD_DESA(x) \
- (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA)
-#define BIT_GET_HI2Q_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA)
-
-/* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */
-
-#define BIT_SHIFT_HI3Q_TXBD_DESA 0
-#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI3Q_TXBD_DESA(x) \
- (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA)
-#define BIT_GET_HI3Q_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA)
-
-/* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */
-
-#define BIT_SHIFT_HI4Q_TXBD_DESA 0
-#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI4Q_TXBD_DESA(x) \
- (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA)
-#define BIT_GET_HI4Q_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA)
-
-/* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */
-
-#define BIT_SHIFT_HI5Q_TXBD_DESA 0
-#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI5Q_TXBD_DESA(x) \
- (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA)
-#define BIT_GET_HI5Q_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA)
-
-/* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */
-
-#define BIT_SHIFT_HI6Q_TXBD_DESA 0
-#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI6Q_TXBD_DESA(x) \
- (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA)
-#define BIT_GET_HI6Q_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA)
-
-/* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */
-
-#define BIT_SHIFT_HI7Q_TXBD_DESA 0
-#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI7Q_TXBD_DESA(x) \
- (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA)
-#define BIT_GET_HI7Q_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA)
-
-/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */
-
-#define BIT_PCIE_MGQ_FLAG BIT(14)
-
-/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */
-
-#define BIT_SHIFT_MGQ_DESC_MODE 12
-#define BIT_MASK_MGQ_DESC_MODE 0x3
-#define BIT_MGQ_DESC_MODE(x) \
- (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE)
-#define BIT_GET_MGQ_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE)
-
-#define BIT_SHIFT_MGQ_DESC_NUM 0
-#define BIT_MASK_MGQ_DESC_NUM 0xfff
-#define BIT_MGQ_DESC_NUM(x) \
- (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM)
-#define BIT_GET_MGQ_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM)
-
-/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
-
-#define BIT_SYS_32_64 BIT(15)
-
-#define BIT_SHIFT_BCNQ_DESC_MODE 13
-#define BIT_MASK_BCNQ_DESC_MODE 0x3
-#define BIT_BCNQ_DESC_MODE(x) \
- (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE)
-#define BIT_GET_BCNQ_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE)
-
-/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
-
-#define BIT_PCIE_BCNQ_FLAG BIT(12)
-
-/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
-
-#define BIT_SHIFT_RXQ_DESC_NUM 0
-#define BIT_MASK_RXQ_DESC_NUM 0xfff
-#define BIT_RXQ_DESC_NUM(x) \
- (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM)
-#define BIT_GET_RXQ_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM)
-
-/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */
-
-#define BIT_PCIE_VOQ_FLAG BIT(14)
-
-/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */
-
-#define BIT_SHIFT_VOQ_DESC_MODE 12
-#define BIT_MASK_VOQ_DESC_MODE 0x3
-#define BIT_VOQ_DESC_MODE(x) \
- (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE)
-#define BIT_GET_VOQ_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE)
-
-#define BIT_SHIFT_VOQ_DESC_NUM 0
-#define BIT_MASK_VOQ_DESC_NUM 0xfff
-#define BIT_VOQ_DESC_NUM(x) \
- (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM)
-#define BIT_GET_VOQ_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM)
-
-/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */
-
-#define BIT_PCIE_VIQ_FLAG BIT(14)
-
-/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */
-
-#define BIT_SHIFT_VIQ_DESC_MODE 12
-#define BIT_MASK_VIQ_DESC_MODE 0x3
-#define BIT_VIQ_DESC_MODE(x) \
- (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE)
-#define BIT_GET_VIQ_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE)
-
-#define BIT_SHIFT_VIQ_DESC_NUM 0
-#define BIT_MASK_VIQ_DESC_NUM 0xfff
-#define BIT_VIQ_DESC_NUM(x) \
- (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM)
-#define BIT_GET_VIQ_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM)
-
-/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */
-
-#define BIT_PCIE_BEQ_FLAG BIT(14)
-
-/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */
-
-#define BIT_SHIFT_BEQ_DESC_MODE 12
-#define BIT_MASK_BEQ_DESC_MODE 0x3
-#define BIT_BEQ_DESC_MODE(x) \
- (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE)
-#define BIT_GET_BEQ_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE)
-
-#define BIT_SHIFT_BEQ_DESC_NUM 0
-#define BIT_MASK_BEQ_DESC_NUM 0xfff
-#define BIT_BEQ_DESC_NUM(x) \
- (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM)
-#define BIT_GET_BEQ_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM)
-
-/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */
-
-#define BIT_PCIE_BKQ_FLAG BIT(14)
-
-/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */
-
-#define BIT_SHIFT_BKQ_DESC_MODE 12
-#define BIT_MASK_BKQ_DESC_MODE 0x3
-#define BIT_BKQ_DESC_MODE(x) \
- (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE)
-#define BIT_GET_BKQ_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE)
-
-#define BIT_SHIFT_BKQ_DESC_NUM 0
-#define BIT_MASK_BKQ_DESC_NUM 0xfff
-#define BIT_BKQ_DESC_NUM(x) \
- (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM)
-#define BIT_GET_BKQ_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM)
-
-/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */
-
-#define BIT_HI0Q_FLAG BIT(14)
-
-#define BIT_SHIFT_HI0Q_DESC_MODE 12
-#define BIT_MASK_HI0Q_DESC_MODE 0x3
-#define BIT_HI0Q_DESC_MODE(x) \
- (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE)
-#define BIT_GET_HI0Q_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE)
-
-#define BIT_SHIFT_HI0Q_DESC_NUM 0
-#define BIT_MASK_HI0Q_DESC_NUM 0xfff
-#define BIT_HI0Q_DESC_NUM(x) \
- (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM)
-#define BIT_GET_HI0Q_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM)
-
-/* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */
-
-#define BIT_HI1Q_FLAG BIT(14)
-
-#define BIT_SHIFT_HI1Q_DESC_MODE 12
-#define BIT_MASK_HI1Q_DESC_MODE 0x3
-#define BIT_HI1Q_DESC_MODE(x) \
- (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE)
-#define BIT_GET_HI1Q_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE)
-
-#define BIT_SHIFT_HI1Q_DESC_NUM 0
-#define BIT_MASK_HI1Q_DESC_NUM 0xfff
-#define BIT_HI1Q_DESC_NUM(x) \
- (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM)
-#define BIT_GET_HI1Q_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM)
-
-/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */
-
-#define BIT_HI2Q_FLAG BIT(14)
-
-#define BIT_SHIFT_HI2Q_DESC_MODE 12
-#define BIT_MASK_HI2Q_DESC_MODE 0x3
-#define BIT_HI2Q_DESC_MODE(x) \
- (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE)
-#define BIT_GET_HI2Q_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE)
-
-#define BIT_SHIFT_HI2Q_DESC_NUM 0
-#define BIT_MASK_HI2Q_DESC_NUM 0xfff
-#define BIT_HI2Q_DESC_NUM(x) \
- (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM)
-#define BIT_GET_HI2Q_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM)
-
-/* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */
-
-#define BIT_HI3Q_FLAG BIT(14)
-
-#define BIT_SHIFT_HI3Q_DESC_MODE 12
-#define BIT_MASK_HI3Q_DESC_MODE 0x3
-#define BIT_HI3Q_DESC_MODE(x) \
- (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE)
-#define BIT_GET_HI3Q_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE)
-
-#define BIT_SHIFT_HI3Q_DESC_NUM 0
-#define BIT_MASK_HI3Q_DESC_NUM 0xfff
-#define BIT_HI3Q_DESC_NUM(x) \
- (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM)
-#define BIT_GET_HI3Q_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM)
-
-/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */
-
-#define BIT_HI4Q_FLAG BIT(14)
-
-#define BIT_SHIFT_HI4Q_DESC_MODE 12
-#define BIT_MASK_HI4Q_DESC_MODE 0x3
-#define BIT_HI4Q_DESC_MODE(x) \
- (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE)
-#define BIT_GET_HI4Q_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE)
-
-#define BIT_SHIFT_HI4Q_DESC_NUM 0
-#define BIT_MASK_HI4Q_DESC_NUM 0xfff
-#define BIT_HI4Q_DESC_NUM(x) \
- (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM)
-#define BIT_GET_HI4Q_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM)
-
-/* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */
-
-#define BIT_HI5Q_FLAG BIT(14)
-
-#define BIT_SHIFT_HI5Q_DESC_MODE 12
-#define BIT_MASK_HI5Q_DESC_MODE 0x3
-#define BIT_HI5Q_DESC_MODE(x) \
- (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE)
-#define BIT_GET_HI5Q_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE)
-
-#define BIT_SHIFT_HI5Q_DESC_NUM 0
-#define BIT_MASK_HI5Q_DESC_NUM 0xfff
-#define BIT_HI5Q_DESC_NUM(x) \
- (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM)
-#define BIT_GET_HI5Q_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM)
-
-/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */
-
-#define BIT_HI6Q_FLAG BIT(14)
-
-#define BIT_SHIFT_HI6Q_DESC_MODE 12
-#define BIT_MASK_HI6Q_DESC_MODE 0x3
-#define BIT_HI6Q_DESC_MODE(x) \
- (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE)
-#define BIT_GET_HI6Q_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE)
-
-#define BIT_SHIFT_HI6Q_DESC_NUM 0
-#define BIT_MASK_HI6Q_DESC_NUM 0xfff
-#define BIT_HI6Q_DESC_NUM(x) \
- (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM)
-#define BIT_GET_HI6Q_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM)
-
-/* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */
-
-#define BIT_HI7Q_FLAG BIT(14)
-
-#define BIT_SHIFT_HI7Q_DESC_MODE 12
-#define BIT_MASK_HI7Q_DESC_MODE 0x3
-#define BIT_HI7Q_DESC_MODE(x) \
- (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE)
-#define BIT_GET_HI7Q_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE)
-
-#define BIT_SHIFT_HI7Q_DESC_NUM 0
-#define BIT_MASK_HI7Q_DESC_NUM 0xfff
-#define BIT_HI7Q_DESC_NUM(x) \
- (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM)
-#define BIT_GET_HI7Q_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_HI7Q_HW_IDX BIT(29)
-#define BIT_CLR_HI6Q_HW_IDX BIT(28)
-#define BIT_CLR_HI5Q_HW_IDX BIT(27)
-#define BIT_CLR_HI4Q_HW_IDX BIT(26)
-#define BIT_CLR_HI3Q_HW_IDX BIT(25)
-#define BIT_CLR_HI2Q_HW_IDX BIT(24)
-#define BIT_CLR_HI1Q_HW_IDX BIT(23)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_HI0Q_HW_IDX BIT(22)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_BKQ_HW_IDX BIT(21)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_BEQ_HW_IDX BIT(20)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_VIQ_HW_IDX BIT(19)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_VOQ_HW_IDX BIT(18)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_MGQ_HW_IDX BIT(17)
-
-/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */
-
-#define BIT_SHIFT_TSFT2_HCI 16
-#define BIT_MASK_TSFT2_HCI 0xffff
-#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI)
-#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI)
-
-#define BIT_CLR_RXQ_HW_IDX BIT(16)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_HI7Q_HOST_IDX BIT(13)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_HI6Q_HOST_IDX BIT(12)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_HI5Q_HOST_IDX BIT(11)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_HI4Q_HOST_IDX BIT(10)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_HI3Q_HOST_IDX BIT(9)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_HI2Q_HOST_IDX BIT(8)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_HI1Q_HOST_IDX BIT(7)
-#define BIT_CLR_HI0Q_HOST_IDX BIT(6)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_BKQ_HOST_IDX BIT(5)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_BEQ_HOST_IDX BIT(4)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_VIQ_HOST_IDX BIT(3)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_VOQ_HOST_IDX BIT(2)
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_CLR_MGQ_HOST_IDX BIT(1)
-
-/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */
-
-#define BIT_SHIFT_TSFT1_HCI 0
-#define BIT_MASK_TSFT1_HCI 0xffff
-#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI)
-#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI)
-
-#define BIT_CLR_RXQ_HOST_IDX BIT(0)
-
-/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */
-
-#define BIT_SHIFT_VOQ_HW_IDX 16
-#define BIT_MASK_VOQ_HW_IDX 0xfff
-#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX)
-#define BIT_GET_VOQ_HW_IDX(x) \
- (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX)
-
-#define BIT_SHIFT_VOQ_HOST_IDX 0
-#define BIT_MASK_VOQ_HOST_IDX 0xfff
-#define BIT_VOQ_HOST_IDX(x) \
- (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX)
-#define BIT_GET_VOQ_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX)
-
-/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */
-
-#define BIT_SHIFT_VIQ_HW_IDX 16
-#define BIT_MASK_VIQ_HW_IDX 0xfff
-#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX)
-#define BIT_GET_VIQ_HW_IDX(x) \
- (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX)
-
-#define BIT_SHIFT_VIQ_HOST_IDX 0
-#define BIT_MASK_VIQ_HOST_IDX 0xfff
-#define BIT_VIQ_HOST_IDX(x) \
- (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX)
-#define BIT_GET_VIQ_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX)
-
-/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */
-
-#define BIT_SHIFT_BEQ_HW_IDX 16
-#define BIT_MASK_BEQ_HW_IDX 0xfff
-#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX)
-#define BIT_GET_BEQ_HW_IDX(x) \
- (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX)
-
-#define BIT_SHIFT_BEQ_HOST_IDX 0
-#define BIT_MASK_BEQ_HOST_IDX 0xfff
-#define BIT_BEQ_HOST_IDX(x) \
- (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX)
-#define BIT_GET_BEQ_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX)
-
-/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */
-
-#define BIT_SHIFT_BKQ_HW_IDX 16
-#define BIT_MASK_BKQ_HW_IDX 0xfff
-#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX)
-#define BIT_GET_BKQ_HW_IDX(x) \
- (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX)
-
-#define BIT_SHIFT_BKQ_HOST_IDX 0
-#define BIT_MASK_BKQ_HOST_IDX 0xfff
-#define BIT_BKQ_HOST_IDX(x) \
- (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX)
-#define BIT_GET_BKQ_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX)
-
-/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */
-
-#define BIT_SHIFT_MGQ_HW_IDX 16
-#define BIT_MASK_MGQ_HW_IDX 0xfff
-#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX)
-#define BIT_GET_MGQ_HW_IDX(x) \
- (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX)
-
-#define BIT_SHIFT_MGQ_HOST_IDX 0
-#define BIT_MASK_MGQ_HOST_IDX 0xfff
-#define BIT_MGQ_HOST_IDX(x) \
- (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX)
-#define BIT_GET_MGQ_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX)
-
-/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */
-
-#define BIT_SHIFT_RXQ_HW_IDX 16
-#define BIT_MASK_RXQ_HW_IDX 0xfff
-#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX)
-#define BIT_GET_RXQ_HW_IDX(x) \
- (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX)
-
-#define BIT_SHIFT_RXQ_HOST_IDX 0
-#define BIT_MASK_RXQ_HOST_IDX 0xfff
-#define BIT_RXQ_HOST_IDX(x) \
- (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX)
-#define BIT_GET_RXQ_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX)
-
-/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */
-
-#define BIT_SHIFT_HI0Q_HW_IDX 16
-#define BIT_MASK_HI0Q_HW_IDX 0xfff
-#define BIT_HI0Q_HW_IDX(x) \
- (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX)
-#define BIT_GET_HI0Q_HW_IDX(x) \
- (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX)
-
-#define BIT_SHIFT_HI0Q_HOST_IDX 0
-#define BIT_MASK_HI0Q_HOST_IDX 0xfff
-#define BIT_HI0Q_HOST_IDX(x) \
- (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX)
-#define BIT_GET_HI0Q_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX)
-
-/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */
-
-#define BIT_SHIFT_HI1Q_HW_IDX 16
-#define BIT_MASK_HI1Q_HW_IDX 0xfff
-#define BIT_HI1Q_HW_IDX(x) \
- (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX)
-#define BIT_GET_HI1Q_HW_IDX(x) \
- (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX)
-
-#define BIT_SHIFT_HI1Q_HOST_IDX 0
-#define BIT_MASK_HI1Q_HOST_IDX 0xfff
-#define BIT_HI1Q_HOST_IDX(x) \
- (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX)
-#define BIT_GET_HI1Q_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX)
-
-/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */
-
-#define BIT_SHIFT_HI2Q_HW_IDX 16
-#define BIT_MASK_HI2Q_HW_IDX 0xfff
-#define BIT_HI2Q_HW_IDX(x) \
- (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX)
-#define BIT_GET_HI2Q_HW_IDX(x) \
- (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX)
-
-#define BIT_SHIFT_HI2Q_HOST_IDX 0
-#define BIT_MASK_HI2Q_HOST_IDX 0xfff
-#define BIT_HI2Q_HOST_IDX(x) \
- (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX)
-#define BIT_GET_HI2Q_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX)
-
-/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */
-
-#define BIT_SHIFT_HI3Q_HW_IDX 16
-#define BIT_MASK_HI3Q_HW_IDX 0xfff
-#define BIT_HI3Q_HW_IDX(x) \
- (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX)
-#define BIT_GET_HI3Q_HW_IDX(x) \
- (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX)
-
-#define BIT_SHIFT_HI3Q_HOST_IDX 0
-#define BIT_MASK_HI3Q_HOST_IDX 0xfff
-#define BIT_HI3Q_HOST_IDX(x) \
- (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX)
-#define BIT_GET_HI3Q_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX)
-
-/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */
-
-#define BIT_SHIFT_HI4Q_HW_IDX 16
-#define BIT_MASK_HI4Q_HW_IDX 0xfff
-#define BIT_HI4Q_HW_IDX(x) \
- (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX)
-#define BIT_GET_HI4Q_HW_IDX(x) \
- (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX)
-
-#define BIT_SHIFT_HI4Q_HOST_IDX 0
-#define BIT_MASK_HI4Q_HOST_IDX 0xfff
-#define BIT_HI4Q_HOST_IDX(x) \
- (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX)
-#define BIT_GET_HI4Q_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX)
-
-/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */
-
-#define BIT_SHIFT_HI5Q_HW_IDX 16
-#define BIT_MASK_HI5Q_HW_IDX 0xfff
-#define BIT_HI5Q_HW_IDX(x) \
- (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX)
-#define BIT_GET_HI5Q_HW_IDX(x) \
- (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX)
-
-#define BIT_SHIFT_HI5Q_HOST_IDX 0
-#define BIT_MASK_HI5Q_HOST_IDX 0xfff
-#define BIT_HI5Q_HOST_IDX(x) \
- (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX)
-#define BIT_GET_HI5Q_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX)
-
-/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */
-
-#define BIT_SHIFT_HI6Q_HW_IDX 16
-#define BIT_MASK_HI6Q_HW_IDX 0xfff
-#define BIT_HI6Q_HW_IDX(x) \
- (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX)
-#define BIT_GET_HI6Q_HW_IDX(x) \
- (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX)
-
-#define BIT_SHIFT_HI6Q_HOST_IDX 0
-#define BIT_MASK_HI6Q_HOST_IDX 0xfff
-#define BIT_HI6Q_HOST_IDX(x) \
- (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX)
-#define BIT_GET_HI6Q_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX)
-
-/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */
-
-#define BIT_SHIFT_HI7Q_HW_IDX 16
-#define BIT_MASK_HI7Q_HW_IDX 0xfff
-#define BIT_HI7Q_HW_IDX(x) \
- (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX)
-#define BIT_GET_HI7Q_HW_IDX(x) \
- (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX)
-
-#define BIT_SHIFT_HI7Q_HOST_IDX 0
-#define BIT_MASK_HI7Q_HOST_IDX 0xfff
-#define BIT_HI7Q_HOST_IDX(x) \
- (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX)
-#define BIT_GET_HI7Q_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX)
-
-/* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */
-
-#define BIT_DIS_TXDMA_PRE BIT(7)
-#define BIT_DIS_RXDMA_PRE BIT(6)
-#define BIT_TXFLAG_EXIT_L1_EN BIT(2)
-
-#define BIT_SHIFT_DBG_SEL 0
-#define BIT_MASK_DBG_SEL 0xff
-#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL)
-#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL)
-
-/* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */
-
-#define BIT_SHIFT_PCIE_HRPWM 0
-#define BIT_MASK_PCIE_HRPWM 0xff
-#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM)
-#define BIT_GET_PCIE_HRPWM(x) \
- (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM)
-
-/* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */
-
-#define BIT_SHIFT_PCIE_HCPWM 0
-#define BIT_MASK_PCIE_HCPWM 0xff
-#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM)
-#define BIT_GET_PCIE_HCPWM(x) \
- (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM)
-
-/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */
-
-#define BIT_SHIFT_HPS_CLKR_PCIE 4
-#define BIT_MASK_HPS_CLKR_PCIE 0x3
-#define BIT_HPS_CLKR_PCIE(x) \
- (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE)
-#define BIT_GET_HPS_CLKR_PCIE(x) \
- (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE)
-
-/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */
-
-#define BIT_PCIE_INT BIT(3)
-
-/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */
-
-#define BIT_EN_RXDMA_ALIGN BIT(1)
-#define BIT_EN_TXDMA_ALIGN BIT(0)
-
-/* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */
-
-#define BIT_SHIFT_PCIE_HRPWM2 0
-#define BIT_MASK_PCIE_HRPWM2 0xffff
-#define BIT_PCIE_HRPWM2(x) \
- (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2)
-#define BIT_GET_PCIE_HRPWM2(x) \
- (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2)
-
-/* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */
-
-#define BIT_SHIFT_PCIE_HCPWM2 0
-#define BIT_MASK_PCIE_HCPWM2 0xffff
-#define BIT_PCIE_HCPWM2(x) \
- (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2)
-#define BIT_GET_PCIE_HCPWM2(x) \
- (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2)
-
-/* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */
-
-#define BIT_SHIFT_DRV2FW_INFO 0
-#define BIT_MASK_DRV2FW_INFO 0xffffffffL
-#define BIT_DRV2FW_INFO(x) \
- (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO)
-#define BIT_GET_DRV2FW_INFO(x) \
- (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO)
-
-/* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */
-
-#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0
-#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL
-#define BIT_HCI_PCIE_C2H_MSG(x) \
- (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG)
-#define BIT_GET_HCI_PCIE_C2H_MSG(x) \
- (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG)
-
-/* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */
-
-#define BIT_SHIFT_DBI_WDATA 0
-#define BIT_MASK_DBI_WDATA 0xffffffffL
-#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA)
-#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA)
-
-/* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */
-
-#define BIT_SHIFT_DBI_RDATA 0
-#define BIT_MASK_DBI_RDATA 0xffffffffL
-#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA)
-#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA)
-
-/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */
-
-#define BIT_EN_STUCK_DBG BIT(26)
-#define BIT_RX_STUCK BIT(25)
-#define BIT_TX_STUCK BIT(24)
-#define BIT_DBI_RFLAG BIT(17)
-#define BIT_DBI_WFLAG BIT(16)
-
-#define BIT_SHIFT_DBI_WREN 12
-#define BIT_MASK_DBI_WREN 0xf
-#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN)
-#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN)
-
-#define BIT_SHIFT_DBI_ADDR 0
-#define BIT_MASK_DBI_ADDR 0xfff
-#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR)
-#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR)
-
-/* 2 REG_MDIO_V1 (Offset 0x03F4) */
-
-#define BIT_SHIFT_MDIO_RDATA 16
-#define BIT_MASK_MDIO_RDATA 0xffff
-#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA)
-#define BIT_GET_MDIO_RDATA(x) \
- (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA)
-
-#define BIT_SHIFT_MDIO_WDATA 0
-#define BIT_MASK_MDIO_WDATA 0xffff
-#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA)
-#define BIT_GET_MDIO_WDATA(x) \
- (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA)
-
-/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */
-
-#define BIT_EN_WATCH_DOG BIT(8)
-
-/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */
-
-#define BIT_SHIFT_MDIO_REG_ADDR_V1 0
-#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f
-#define BIT_MDIO_REG_ADDR_V1(x) \
- (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1)
-#define BIT_GET_MDIO_REG_ADDR_V1(x) \
- (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1)
-
-/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
-
-#define BIT_HOST_GEN2_SUPPORT BIT(20)
-
-#define BIT_SHIFT_TXDMA_ERR_FLAG 16
-#define BIT_MASK_TXDMA_ERR_FLAG 0xf
-#define BIT_TXDMA_ERR_FLAG(x) \
- (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG)
-#define BIT_GET_TXDMA_ERR_FLAG(x) \
- (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG)
-
-#define BIT_SHIFT_EARLY_MODE_SEL 12
-#define BIT_MASK_EARLY_MODE_SEL 0xf
-#define BIT_EARLY_MODE_SEL(x) \
- (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL)
-#define BIT_GET_EARLY_MODE_SEL(x) \
- (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL)
-
-#define BIT_EPHY_RX50_EN BIT(11)
-
-#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8
-#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7
-#define BIT_MSI_TIMEOUT_ID_V1(x) \
- (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1)
-#define BIT_GET_MSI_TIMEOUT_ID_V1(x) \
- (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1)
-
-#define BIT_RADDR_RD BIT(7)
-#define BIT_EN_MUL_TAG BIT(6)
-#define BIT_EN_EARLY_MODE BIT(5)
-#define BIT_L0S_LINK_OFF BIT(4)
-#define BIT_ACT_LINK_OFF BIT(3)
-
-/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
-
-#define BIT_EN_SLOW_MAC_TX BIT(2)
-#define BIT_EN_SLOW_MAC_RX BIT(1)
-
-/* 2 REG_Q0_INFO (Offset 0x0400) */
-
-#define BIT_SHIFT_QUEUEMACID_Q0_V1 25
-#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f
-#define BIT_QUEUEMACID_Q0_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1)
-#define BIT_GET_QUEUEMACID_Q0_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1)
-
-#define BIT_SHIFT_QUEUEAC_Q0_V1 23
-#define BIT_MASK_QUEUEAC_Q0_V1 0x3
-#define BIT_QUEUEAC_Q0_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1)
-#define BIT_GET_QUEUEAC_Q0_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1)
-
-/* 2 REG_Q0_INFO (Offset 0x0400) */
-
-#define BIT_TIDEMPTY_Q0_V1 BIT(22)
-
-/* 2 REG_Q0_INFO (Offset 0x0400) */
-
-#define BIT_SHIFT_TAIL_PKT_Q0_V2 11
-#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff
-#define BIT_TAIL_PKT_Q0_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2)
-#define BIT_GET_TAIL_PKT_Q0_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2)
-
-/* 2 REG_Q0_INFO (Offset 0x0400) */
-
-#define BIT_SHIFT_HEAD_PKT_Q0_V1 0
-#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff
-#define BIT_HEAD_PKT_Q0_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1)
-#define BIT_GET_HEAD_PKT_Q0_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1)
-
-/* 2 REG_Q1_INFO (Offset 0x0404) */
-
-#define BIT_SHIFT_QUEUEMACID_Q1_V1 25
-#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f
-#define BIT_QUEUEMACID_Q1_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1)
-#define BIT_GET_QUEUEMACID_Q1_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1)
-
-#define BIT_SHIFT_QUEUEAC_Q1_V1 23
-#define BIT_MASK_QUEUEAC_Q1_V1 0x3
-#define BIT_QUEUEAC_Q1_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1)
-#define BIT_GET_QUEUEAC_Q1_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1)
-
-/* 2 REG_Q1_INFO (Offset 0x0404) */
-
-#define BIT_TIDEMPTY_Q1_V1 BIT(22)
-
-/* 2 REG_Q1_INFO (Offset 0x0404) */
-
-#define BIT_SHIFT_TAIL_PKT_Q1_V2 11
-#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff
-#define BIT_TAIL_PKT_Q1_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2)
-#define BIT_GET_TAIL_PKT_Q1_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2)
-
-/* 2 REG_Q1_INFO (Offset 0x0404) */
-
-#define BIT_SHIFT_HEAD_PKT_Q1_V1 0
-#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff
-#define BIT_HEAD_PKT_Q1_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1)
-#define BIT_GET_HEAD_PKT_Q1_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1)
-
-/* 2 REG_Q2_INFO (Offset 0x0408) */
-
-#define BIT_SHIFT_QUEUEMACID_Q2_V1 25
-#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f
-#define BIT_QUEUEMACID_Q2_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1)
-#define BIT_GET_QUEUEMACID_Q2_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1)
-
-#define BIT_SHIFT_QUEUEAC_Q2_V1 23
-#define BIT_MASK_QUEUEAC_Q2_V1 0x3
-#define BIT_QUEUEAC_Q2_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1)
-#define BIT_GET_QUEUEAC_Q2_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1)
-
-/* 2 REG_Q2_INFO (Offset 0x0408) */
-
-#define BIT_TIDEMPTY_Q2_V1 BIT(22)
-
-/* 2 REG_Q2_INFO (Offset 0x0408) */
-
-#define BIT_SHIFT_TAIL_PKT_Q2_V2 11
-#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff
-#define BIT_TAIL_PKT_Q2_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2)
-#define BIT_GET_TAIL_PKT_Q2_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2)
-
-/* 2 REG_Q2_INFO (Offset 0x0408) */
-
-#define BIT_SHIFT_HEAD_PKT_Q2_V1 0
-#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff
-#define BIT_HEAD_PKT_Q2_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1)
-#define BIT_GET_HEAD_PKT_Q2_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1)
-
-/* 2 REG_Q3_INFO (Offset 0x040C) */
-
-#define BIT_SHIFT_QUEUEMACID_Q3_V1 25
-#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f
-#define BIT_QUEUEMACID_Q3_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1)
-#define BIT_GET_QUEUEMACID_Q3_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1)
-
-#define BIT_SHIFT_QUEUEAC_Q3_V1 23
-#define BIT_MASK_QUEUEAC_Q3_V1 0x3
-#define BIT_QUEUEAC_Q3_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1)
-#define BIT_GET_QUEUEAC_Q3_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1)
-
-/* 2 REG_Q3_INFO (Offset 0x040C) */
-
-#define BIT_TIDEMPTY_Q3_V1 BIT(22)
-
-/* 2 REG_Q3_INFO (Offset 0x040C) */
-
-#define BIT_SHIFT_TAIL_PKT_Q3_V2 11
-#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff
-#define BIT_TAIL_PKT_Q3_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2)
-#define BIT_GET_TAIL_PKT_Q3_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2)
-
-/* 2 REG_Q3_INFO (Offset 0x040C) */
-
-#define BIT_SHIFT_HEAD_PKT_Q3_V1 0
-#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff
-#define BIT_HEAD_PKT_Q3_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1)
-#define BIT_GET_HEAD_PKT_Q3_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1)
-
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
-
-#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25
-#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f
-#define BIT_QUEUEMACID_MGQ_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1)
-#define BIT_GET_QUEUEMACID_MGQ_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1)
-
-#define BIT_SHIFT_QUEUEAC_MGQ_V1 23
-#define BIT_MASK_QUEUEAC_MGQ_V1 0x3
-#define BIT_QUEUEAC_MGQ_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1)
-#define BIT_GET_QUEUEAC_MGQ_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1)
-
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
-
-#define BIT_TIDEMPTY_MGQ_V1 BIT(22)
-
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
-
-#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11
-#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff
-#define BIT_TAIL_PKT_MGQ_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2)
-#define BIT_GET_TAIL_PKT_MGQ_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2)
-
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
-
-#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0
-#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff
-#define BIT_HEAD_PKT_MGQ_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1)
-#define BIT_GET_HEAD_PKT_MGQ_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1)
-
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
-
-#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25
-#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f
-#define BIT_QUEUEMACID_HIQ_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1)
-#define BIT_GET_QUEUEMACID_HIQ_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1)
-
-#define BIT_SHIFT_QUEUEAC_HIQ_V1 23
-#define BIT_MASK_QUEUEAC_HIQ_V1 0x3
-#define BIT_QUEUEAC_HIQ_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1)
-#define BIT_GET_QUEUEAC_HIQ_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1)
-
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
-
-#define BIT_TIDEMPTY_HIQ_V1 BIT(22)
-
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
-
-#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11
-#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff
-#define BIT_TAIL_PKT_HIQ_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2)
-#define BIT_GET_TAIL_PKT_HIQ_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2)
-
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
-
-#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0
-#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff
-#define BIT_HEAD_PKT_HIQ_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1)
-#define BIT_GET_HEAD_PKT_HIQ_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1)
-
-/* 2 REG_BCNQ_INFO (Offset 0x0418) */
-
-#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0
-#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff
-#define BIT_BCNQ_HEAD_PG_V1(x) \
- (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1)
-#define BIT_GET_BCNQ_HEAD_PG_V1(x) \
- (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1)
-
-/* 2 REG_TXPKT_EMPTY (Offset 0x041A) */
-
-#define BIT_BCNQ_EMPTY BIT(11)
-#define BIT_HQQ_EMPTY BIT(10)
-#define BIT_MQQ_EMPTY BIT(9)
-#define BIT_MGQ_CPU_EMPTY BIT(8)
-#define BIT_AC7Q_EMPTY BIT(7)
-#define BIT_AC6Q_EMPTY BIT(6)
-#define BIT_AC5Q_EMPTY BIT(5)
-#define BIT_AC4Q_EMPTY BIT(4)
-#define BIT_AC3Q_EMPTY BIT(3)
-#define BIT_AC2Q_EMPTY BIT(2)
-#define BIT_AC1Q_EMPTY BIT(1)
-#define BIT_AC0Q_EMPTY BIT(0)
-
-/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
-
-#define BIT_BCN1_POLL BIT(30)
-
-/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
-
-#define BIT_CPUMGT_POLL BIT(29)
-#define BIT_BCN_POLL BIT(28)
-
-/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
-
-#define BIT_CPUMGQ_FW_NUM_V1 BIT(12)
-
-/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
-
-#define BIT_SHIFT_FW_FREE_TAIL_V1 0
-#define BIT_MASK_FW_FREE_TAIL_V1 0xfff
-#define BIT_FW_FREE_TAIL_V1(x) \
- (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1)
-#define BIT_GET_FW_FREE_TAIL_V1(x) \
- (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1)
-
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
-
-#define BIT_RTS_LIMIT_IN_OFDM BIT(23)
-#define BIT_EN_BCNQ_DL BIT(22)
-#define BIT_EN_RD_RESP_NAV_BK BIT(21)
-#define BIT_EN_WR_FREE_TAIL BIT(20)
-
-#define BIT_SHIFT_EN_QUEUE_RPT 8
-#define BIT_MASK_EN_QUEUE_RPT 0xff
-#define BIT_EN_QUEUE_RPT(x) \
- (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT)
-#define BIT_GET_EN_QUEUE_RPT(x) \
- (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT)
-
-#define BIT_EN_RTY_BK BIT(7)
-#define BIT_EN_USE_INI_RAT BIT(6)
-#define BIT_EN_RTS_NAV_BK BIT(5)
-#define BIT_DIS_SSN_CHECK BIT(4)
-#define BIT_MACID_MATCH_RTS BIT(3)
-
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
-
-#define BIT_EN_BCN_TRXRPT_V1 BIT(2)
-
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
-
-#define BIT_EN_FTMACKRPT BIT(1)
-
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
-
-#define BIT_EN_FTMRPT BIT(0)
-
-/* 2 REG_DATAFB_SEL (Offset 0x0423) */
-
-#define BIT__R_EN_RTY_BK_COD BIT(2)
-
-/* 2 REG_DATAFB_SEL (Offset 0x0423) */
-
-#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0
-#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3
-#define BIT__R_DATA_FALLBACK_SEL(x) \
- (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) \
- << BIT_SHIFT__R_DATA_FALLBACK_SEL)
-#define BIT_GET__R_DATA_FALLBACK_SEL(x) \
- (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & \
- BIT_MASK__R_DATA_FALLBACK_SEL)
-
-/* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */
-
-#define BIT_SHIFT_BCNQ_PGBNDY_V1 0
-#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff
-#define BIT_BCNQ_PGBNDY_V1(x) \
- (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1)
-#define BIT_GET_BCNQ_PGBNDY_V1(x) \
- (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1)
-
-/* 2 REG_LIFETIME_EN (Offset 0x0426) */
-
-#define BIT_BT_INT_CPU BIT(7)
-#define BIT_BT_INT_PTA BIT(6)
-
-/* 2 REG_LIFETIME_EN (Offset 0x0426) */
-
-#define BIT_EN_CTRL_RTYBIT BIT(4)
-
-/* 2 REG_LIFETIME_EN (Offset 0x0426) */
-
-#define BIT_LIFETIME_BK_EN BIT(3)
-#define BIT_LIFETIME_BE_EN BIT(2)
-#define BIT_LIFETIME_VI_EN BIT(1)
-#define BIT_LIFETIME_VO_EN BIT(0)
-
-/* 2 REG_SPEC_SIFS (Offset 0x0428) */
-
-#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8
-#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff
-#define BIT_SPEC_SIFS_OFDM_PTCL(x) \
- (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)
-#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) \
- (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL)
-
-#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0
-#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff
-#define BIT_SPEC_SIFS_CCK_PTCL(x) \
- (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)
-#define BIT_GET_SPEC_SIFS_CCK_PTCL(x) \
- (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL)
-
-/* 2 REG_RETRY_LIMIT (Offset 0x042A) */
-
-#define BIT_SHIFT_SRL 8
-#define BIT_MASK_SRL 0x3f
-#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)
-#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL)
-
-#define BIT_SHIFT_LRL 0
-#define BIT_MASK_LRL 0x3f
-#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)
-#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL)
-
-/* 2 REG_TXBF_CTRL (Offset 0x042C) */
-
-#define BIT_R_ENABLE_NDPA BIT(31)
-#define BIT_USE_NDPA_PARAMETER BIT(30)
-#define BIT_R_PROP_TXBF BIT(29)
-#define BIT_R_EN_NDPA_INT BIT(28)
-#define BIT_R_TXBF1_80M BIT(27)
-#define BIT_R_TXBF1_40M BIT(26)
-#define BIT_R_TXBF1_20M BIT(25)
-
-#define BIT_SHIFT_R_TXBF1_AID 16
-#define BIT_MASK_R_TXBF1_AID 0x1ff
-#define BIT_R_TXBF1_AID(x) \
- (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID)
-#define BIT_GET_R_TXBF1_AID(x) \
- (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID)
-
-/* 2 REG_TXBF_CTRL (Offset 0x042C) */
-
-#define BIT_DIS_NDP_BFEN BIT(15)
-
-/* 2 REG_TXBF_CTRL (Offset 0x042C) */
-
-#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14)
-
-/* 2 REG_TXBF_CTRL (Offset 0x042C) */
-
-#define BIT_R_TXBF0_80M BIT(11)
-#define BIT_R_TXBF0_40M BIT(10)
-#define BIT_R_TXBF0_20M BIT(9)
-
-#define BIT_SHIFT_R_TXBF0_AID 0
-#define BIT_MASK_R_TXBF0_AID 0x1ff
-#define BIT_R_TXBF0_AID(x) \
- (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID)
-#define BIT_GET_R_TXBF0_AID(x) \
- (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID)
-
-/* 2 REG_DARFRC (Offset 0x0430) */
-
-#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC8 0x1f
-#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8)
-#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8)
-
-#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC7 0x1f
-#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7)
-#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7)
-
-#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC6 0x1f
-#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6)
-#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6)
-
-#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC5 0x1f
-#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5)
-#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5)
-
-#define BIT_SHIFT_DARF_RC4 24
-#define BIT_MASK_DARF_RC4 0x1f
-#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4)
-#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4)
-
-#define BIT_SHIFT_DARF_RC3 16
-#define BIT_MASK_DARF_RC3 0x1f
-#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3)
-#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3)
-
-#define BIT_SHIFT_DARF_RC2 8
-#define BIT_MASK_DARF_RC2 0x1f
-#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2)
-#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2)
-
-#define BIT_SHIFT_DARF_RC1 0
-#define BIT_MASK_DARF_RC1 0x1f
-#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1)
-#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1)
-
-/* 2 REG_RARFRC (Offset 0x0438) */
-
-#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC8 0x1f
-#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8)
-#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8)
-
-#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC7 0x1f
-#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7)
-#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7)
-
-#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC6 0x1f
-#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6)
-#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6)
-
-#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC5 0x1f
-#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5)
-#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5)
-
-#define BIT_SHIFT_RARF_RC4 24
-#define BIT_MASK_RARF_RC4 0x1f
-#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4)
-#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4)
-
-#define BIT_SHIFT_RARF_RC3 16
-#define BIT_MASK_RARF_RC3 0x1f
-#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3)
-#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3)
-
-#define BIT_SHIFT_RARF_RC2 8
-#define BIT_MASK_RARF_RC2 0x1f
-#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2)
-#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2)
-
-#define BIT_SHIFT_RARF_RC1 0
-#define BIT_MASK_RARF_RC1 0x1f
-#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1)
-#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1)
-
-/* 2 REG_RRSR (Offset 0x0440) */
-
-#define BIT_SHIFT_RRSR_RSC 21
-#define BIT_MASK_RRSR_RSC 0x3
-#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC)
-#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC)
-
-#define BIT_RRSR_BW BIT(20)
-
-#define BIT_SHIFT_RRSC_BITMAP 0
-#define BIT_MASK_RRSC_BITMAP 0xfffff
-#define BIT_RRSC_BITMAP(x) \
- (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP)
-#define BIT_GET_RRSC_BITMAP(x) \
- (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP)
-
-/* 2 REG_ARFR0 (Offset 0x0444) */
-
-#define BIT_SHIFT_ARFR0_V1 0
-#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL
-#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1)
-#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1)
-
-/* 2 REG_ARFR1_V1 (Offset 0x044C) */
-
-#define BIT_SHIFT_ARFR1_V1 0
-#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL
-#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1)
-#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1)
-
-/* 2 REG_CCK_CHECK (Offset 0x0454) */
-
-#define BIT_CHECK_CCK_EN BIT(7)
-#define BIT_EN_BCN_PKT_REL BIT(6)
-#define BIT_BCN_PORT_SEL BIT(5)
-#define BIT_MOREDATA_BYPASS BIT(4)
-#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3)
-
-/* 2 REG_CCK_CHECK (Offset 0x0454) */
-
-#define BIT_R_EN_SET_MOREDATA BIT(2)
-#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1)
-#define BIT__R_MACID_RELEASE_EN BIT(0)
-
-/* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */
-
-#define BIT_SHIFT_AMPDU_MAX_TIME 0
-#define BIT_MASK_AMPDU_MAX_TIME 0xff
-#define BIT_AMPDU_MAX_TIME(x) \
- (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME)
-#define BIT_GET_AMPDU_MAX_TIME(x) \
- (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME)
-
-/* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */
-
-#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0
-#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff
-#define BIT_BCNQ1_PGBNDY_V1(x) \
- (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1)
-#define BIT_GET_BCNQ1_PGBNDY_V1(x) \
- (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1)
-
-/* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */
-
-#define BIT_SHIFT_AMPDU_MAX_LENGTH 0
-#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL
-#define BIT_AMPDU_MAX_LENGTH(x) \
- (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH)
-#define BIT_GET_AMPDU_MAX_LENGTH(x) \
- (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH)
-
-/* 2 REG_ACQ_STOP (Offset 0x045C) */
-
-#define BIT_AC7Q_STOP BIT(7)
-#define BIT_AC6Q_STOP BIT(6)
-#define BIT_AC5Q_STOP BIT(5)
-#define BIT_AC4Q_STOP BIT(4)
-#define BIT_AC3Q_STOP BIT(3)
-#define BIT_AC2Q_STOP BIT(2)
-#define BIT_AC1Q_STOP BIT(1)
-#define BIT_AC0Q_STOP BIT(0)
-
-/* 2 REG_NDPA_RATE (Offset 0x045D) */
-
-#define BIT_SHIFT_R_NDPA_RATE_V1 0
-#define BIT_MASK_R_NDPA_RATE_V1 0xff
-#define BIT_R_NDPA_RATE_V1(x) \
- (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1)
-#define BIT_GET_R_NDPA_RATE_V1(x) \
- (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1)
-
-/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
-
-#define BIT_R_EN_GNT_BT_AWAKE BIT(3)
-
-/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
-
-#define BIT_EN_EOF_V1 BIT(2)
-
-/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
-
-#define BIT_DIS_OQT_BLOCK BIT(1)
-#define BIT_SEARCH_QUEUE_EN BIT(0)
-
-/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
-
-#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5)
-
-/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
-
-#define BIT_SHIFT_BW_SIGTA 3
-#define BIT_MASK_BW_SIGTA 0x3
-#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA)
-#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA)
-
-/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
-
-#define BIT_EN_BAR_SIGTA BIT(2)
-
-/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
-
-#define BIT_SHIFT_R_NDPA_BW 0
-#define BIT_MASK_R_NDPA_BW 0x3
-#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW)
-#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW)
-
-/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */
-
-#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0
-#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f
-#define BIT_RD_RESP_PKT_TH_V1(x) \
- (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1)
-#define BIT_GET_RD_RESP_PKT_TH_V1(x) \
- (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1)
-
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
-
-#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25
-#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f
-#define BIT_QUEUEMACID_CMDQ_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1)
-#define BIT_GET_QUEUEMACID_CMDQ_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1)
-
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
-
-#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23
-#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3
-#define BIT_QUEUEAC_CMDQ_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1)
-#define BIT_GET_QUEUEAC_CMDQ_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1)
-
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
-
-#define BIT_TIDEMPTY_CMDQ_V1 BIT(22)
-
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
-
-#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11
-#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff
-#define BIT_TAIL_PKT_CMDQ_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2)
-#define BIT_GET_TAIL_PKT_CMDQ_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2)
-
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
-
-#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0
-#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff
-#define BIT_HEAD_PKT_CMDQ_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1)
-#define BIT_GET_HEAD_PKT_CMDQ_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1)
-
-/* 2 REG_Q4_INFO (Offset 0x0468) */
-
-#define BIT_SHIFT_QUEUEMACID_Q4_V1 25
-#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f
-#define BIT_QUEUEMACID_Q4_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1)
-#define BIT_GET_QUEUEMACID_Q4_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1)
-
-#define BIT_SHIFT_QUEUEAC_Q4_V1 23
-#define BIT_MASK_QUEUEAC_Q4_V1 0x3
-#define BIT_QUEUEAC_Q4_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1)
-#define BIT_GET_QUEUEAC_Q4_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1)
-
-/* 2 REG_Q4_INFO (Offset 0x0468) */
-
-#define BIT_TIDEMPTY_Q4_V1 BIT(22)
-
-/* 2 REG_Q4_INFO (Offset 0x0468) */
-
-#define BIT_SHIFT_TAIL_PKT_Q4_V2 11
-#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff
-#define BIT_TAIL_PKT_Q4_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2)
-#define BIT_GET_TAIL_PKT_Q4_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2)
-
-/* 2 REG_Q4_INFO (Offset 0x0468) */
-
-#define BIT_SHIFT_HEAD_PKT_Q4_V1 0
-#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff
-#define BIT_HEAD_PKT_Q4_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1)
-#define BIT_GET_HEAD_PKT_Q4_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1)
-
-/* 2 REG_Q5_INFO (Offset 0x046C) */
-
-#define BIT_SHIFT_QUEUEMACID_Q5_V1 25
-#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f
-#define BIT_QUEUEMACID_Q5_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1)
-#define BIT_GET_QUEUEMACID_Q5_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1)
-
-#define BIT_SHIFT_QUEUEAC_Q5_V1 23
-#define BIT_MASK_QUEUEAC_Q5_V1 0x3
-#define BIT_QUEUEAC_Q5_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1)
-#define BIT_GET_QUEUEAC_Q5_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1)
-
-/* 2 REG_Q5_INFO (Offset 0x046C) */
-
-#define BIT_TIDEMPTY_Q5_V1 BIT(22)
-
-/* 2 REG_Q5_INFO (Offset 0x046C) */
-
-#define BIT_SHIFT_TAIL_PKT_Q5_V2 11
-#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff
-#define BIT_TAIL_PKT_Q5_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2)
-#define BIT_GET_TAIL_PKT_Q5_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2)
-
-/* 2 REG_Q5_INFO (Offset 0x046C) */
-
-#define BIT_SHIFT_HEAD_PKT_Q5_V1 0
-#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff
-#define BIT_HEAD_PKT_Q5_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1)
-#define BIT_GET_HEAD_PKT_Q5_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1)
-
-/* 2 REG_Q6_INFO (Offset 0x0470) */
-
-#define BIT_SHIFT_QUEUEMACID_Q6_V1 25
-#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f
-#define BIT_QUEUEMACID_Q6_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1)
-#define BIT_GET_QUEUEMACID_Q6_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1)
-
-#define BIT_SHIFT_QUEUEAC_Q6_V1 23
-#define BIT_MASK_QUEUEAC_Q6_V1 0x3
-#define BIT_QUEUEAC_Q6_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1)
-#define BIT_GET_QUEUEAC_Q6_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1)
-
-/* 2 REG_Q6_INFO (Offset 0x0470) */
-
-#define BIT_TIDEMPTY_Q6_V1 BIT(22)
-
-/* 2 REG_Q6_INFO (Offset 0x0470) */
-
-#define BIT_SHIFT_TAIL_PKT_Q6_V2 11
-#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff
-#define BIT_TAIL_PKT_Q6_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2)
-#define BIT_GET_TAIL_PKT_Q6_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2)
-
-/* 2 REG_Q6_INFO (Offset 0x0470) */
-
-#define BIT_SHIFT_HEAD_PKT_Q6_V1 0
-#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff
-#define BIT_HEAD_PKT_Q6_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1)
-#define BIT_GET_HEAD_PKT_Q6_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1)
-
-/* 2 REG_Q7_INFO (Offset 0x0474) */
-
-#define BIT_SHIFT_QUEUEMACID_Q7_V1 25
-#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f
-#define BIT_QUEUEMACID_Q7_V1(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1)
-#define BIT_GET_QUEUEMACID_Q7_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1)
-
-#define BIT_SHIFT_QUEUEAC_Q7_V1 23
-#define BIT_MASK_QUEUEAC_Q7_V1 0x3
-#define BIT_QUEUEAC_Q7_V1(x) \
- (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1)
-#define BIT_GET_QUEUEAC_Q7_V1(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1)
-
-/* 2 REG_Q7_INFO (Offset 0x0474) */
-
-#define BIT_TIDEMPTY_Q7_V1 BIT(22)
-
-/* 2 REG_Q7_INFO (Offset 0x0474) */
-
-#define BIT_SHIFT_TAIL_PKT_Q7_V2 11
-#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff
-#define BIT_TAIL_PKT_Q7_V2(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2)
-#define BIT_GET_TAIL_PKT_Q7_V2(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2)
-
-/* 2 REG_Q7_INFO (Offset 0x0474) */
-
-#define BIT_SHIFT_HEAD_PKT_Q7_V1 0
-#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff
-#define BIT_HEAD_PKT_Q7_V1(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1)
-#define BIT_GET_HEAD_PKT_Q7_V1(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1)
-
-/* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */
-
-#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0
-#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff
-#define BIT_WMAC_LBK_BUF_HEAD_V1(x) \
- (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) \
- << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1)
-#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) \
- (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & \
- BIT_MASK_WMAC_LBK_BUF_HEAD_V1)
-
-/* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */
-
-#define BIT_SHIFT_MGQ_PGBNDY_V1 0
-#define BIT_MASK_MGQ_PGBNDY_V1 0xfff
-#define BIT_MGQ_PGBNDY_V1(x) \
- (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1)
-#define BIT_GET_MGQ_PGBNDY_V1(x) \
- (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1)
-
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
-
-#define BIT_SHIFT_TRXRPT_TIMER_TH 24
-#define BIT_MASK_TRXRPT_TIMER_TH 0xff
-#define BIT_TRXRPT_TIMER_TH(x) \
- (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH)
-#define BIT_GET_TRXRPT_TIMER_TH(x) \
- (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH)
-
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
-
-#define BIT_SHIFT_TRXRPT_LEN_TH 16
-#define BIT_MASK_TRXRPT_LEN_TH 0xff
-#define BIT_TRXRPT_LEN_TH(x) \
- (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH)
-#define BIT_GET_TRXRPT_LEN_TH(x) \
- (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH)
-
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
-
-#define BIT_SHIFT_TRXRPT_READ_PTR 8
-#define BIT_MASK_TRXRPT_READ_PTR 0xff
-#define BIT_TRXRPT_READ_PTR(x) \
- (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR)
-#define BIT_GET_TRXRPT_READ_PTR(x) \
- (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR)
-
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
-
-#define BIT_SHIFT_TRXRPT_WRITE_PTR 0
-#define BIT_MASK_TRXRPT_WRITE_PTR 0xff
-#define BIT_TRXRPT_WRITE_PTR(x) \
- (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR)
-#define BIT_GET_TRXRPT_WRITE_PTR(x) \
- (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR)
-
-/* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */
-
-#define BIT_LEAG_RTS_BW_DUP BIT(5)
-
-/* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */
-
-#define BIT_SHIFT_BASIC_CFEND_RATE 0
-#define BIT_MASK_BASIC_CFEND_RATE 0x1f
-#define BIT_BASIC_CFEND_RATE(x) \
- (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE)
-#define BIT_GET_BASIC_CFEND_RATE(x) \
- (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE)
-
-/* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */
-
-#define BIT_SHIFT_STBC_CFEND_RATE 0
-#define BIT_MASK_STBC_CFEND_RATE 0x1f
-#define BIT_STBC_CFEND_RATE(x) \
- (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE)
-#define BIT_GET_STBC_CFEND_RATE(x) \
- (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE)
-
-/* 2 REG_DATA_SC (Offset 0x0483) */
-
-#define BIT_SHIFT_TXSC_40M 4
-#define BIT_MASK_TXSC_40M 0xf
-#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
-#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M)
-
-#define BIT_SHIFT_TXSC_20M 0
-#define BIT_MASK_TXSC_20M 0xf
-#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
-#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M)
-
-/* 2 REG_MACID_SLEEP3 (Offset 0x0484) */
-
-#define BIT_SHIFT_MACID127_96_PKTSLEEP 0
-#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL
-#define BIT_MACID127_96_PKTSLEEP(x) \
- (((x) & BIT_MASK_MACID127_96_PKTSLEEP) \
- << BIT_SHIFT_MACID127_96_PKTSLEEP)
-#define BIT_GET_MACID127_96_PKTSLEEP(x) \
- (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & \
- BIT_MASK_MACID127_96_PKTSLEEP)
-
-/* 2 REG_MACID_SLEEP1 (Offset 0x0488) */
-
-#define BIT_SHIFT_MACID63_32_PKTSLEEP 0
-#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL
-#define BIT_MACID63_32_PKTSLEEP(x) \
- (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP)
-#define BIT_GET_MACID63_32_PKTSLEEP(x) \
- (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP)
-
-/* 2 REG_ARFR2_V1 (Offset 0x048C) */
-
-#define BIT_SHIFT_ARFR2_V1 0
-#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL
-#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1)
-#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1)
-
-/* 2 REG_ARFR3_V1 (Offset 0x0494) */
-
-#define BIT_SHIFT_ARFR3_V1 0
-#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL
-#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1)
-#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1)
-
-/* 2 REG_ARFR4 (Offset 0x049C) */
-
-#define BIT_SHIFT_ARFR4 0
-#define BIT_MASK_ARFR4 0xffffffffffffffffL
-#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4)
-#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4)
-
-/* 2 REG_ARFR5 (Offset 0x04A4) */
-
-#define BIT_SHIFT_ARFR5 0
-#define BIT_MASK_ARFR5 0xffffffffffffffffL
-#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5)
-#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5)
-
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
-
-#define BIT_SHIFT_MACID_MURATE_OFFSET 24
-#define BIT_MASK_MACID_MURATE_OFFSET 0xff
-#define BIT_MACID_MURATE_OFFSET(x) \
- (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET)
-#define BIT_GET_MACID_MURATE_OFFSET(x) \
- (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET)
-
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
-
-#define BIT_RPTFIFO_SIZE_OPT BIT(16)
-
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
-
-#define BIT_SHIFT_MACID_CTRL_OFFSET 8
-#define BIT_MASK_MACID_CTRL_OFFSET 0xff
-#define BIT_MACID_CTRL_OFFSET(x) \
- (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET)
-#define BIT_GET_MACID_CTRL_OFFSET(x) \
- (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET)
-
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
-
-#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0
-#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff
-#define BIT_AMPDU_TXRPT_OFFSET(x) \
- (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET)
-#define BIT_GET_AMPDU_TXRPT_OFFSET(x) \
- (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET)
-
-/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */
-
-#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31)
-#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30)
-#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29)
-#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28)
-#define BIT_PTA_WL_PRI_MASK_BK BIT(27)
-#define BIT_PTA_WL_PRI_MASK_BE BIT(26)
-#define BIT_PTA_WL_PRI_MASK_VI BIT(25)
-#define BIT_PTA_WL_PRI_MASK_VO BIT(24)
-
-/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */
-
-#define BIT_SHIFT_POWER_STAGE1 0
-#define BIT_MASK_POWER_STAGE1 0xffffff
-#define BIT_POWER_STAGE1(x) \
- (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1)
-#define BIT_GET_POWER_STAGE1(x) \
- (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1)
-
-/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */
-
-#define BIT__R_CTRL_PKT_POW_ADJ BIT(24)
-
-/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */
-
-#define BIT_SHIFT_POWER_STAGE2 0
-#define BIT_MASK_POWER_STAGE2 0xffffff
-#define BIT_POWER_STAGE2(x) \
- (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2)
-#define BIT_GET_POWER_STAGE2(x) \
- (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2)
-
-/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
-
-#define BIT_SHIFT_PAD_NUM_THRES 24
-#define BIT_MASK_PAD_NUM_THRES 0x3f
-#define BIT_PAD_NUM_THRES(x) \
- (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES)
-#define BIT_GET_PAD_NUM_THRES(x) \
- (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES)
-
-/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
-
-#define BIT_R_DMA_THIS_QUEUE_BK BIT(23)
-#define BIT_R_DMA_THIS_QUEUE_BE BIT(22)
-#define BIT_R_DMA_THIS_QUEUE_VI BIT(21)
-#define BIT_R_DMA_THIS_QUEUE_VO BIT(20)
-
-#define BIT_SHIFT_R_TOTAL_LEN_TH 8
-#define BIT_MASK_R_TOTAL_LEN_TH 0xfff
-#define BIT_R_TOTAL_LEN_TH(x) \
- (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH)
-#define BIT_GET_R_TOTAL_LEN_TH(x) \
- (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH)
-
-/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
-
-#define BIT_EN_NEW_EARLY BIT(7)
-
-/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
-
-#define BIT_PRE_TX_CMD BIT(6)
-
-#define BIT_SHIFT_NUM_SCL_EN 4
-#define BIT_MASK_NUM_SCL_EN 0x3
-#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN)
-#define BIT_GET_NUM_SCL_EN(x) \
- (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN)
-
-#define BIT_BK_EN BIT(3)
-#define BIT_BE_EN BIT(2)
-#define BIT_VI_EN BIT(1)
-#define BIT_VO_EN BIT(0)
-
-/* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */
-
-#define BIT_SHIFT_PKT_LIFTIME_BEBK 16
-#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff
-#define BIT_PKT_LIFTIME_BEBK(x) \
- (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK)
-#define BIT_GET_PKT_LIFTIME_BEBK(x) \
- (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK)
-
-#define BIT_SHIFT_PKT_LIFTIME_VOVI 0
-#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff
-#define BIT_PKT_LIFTIME_VOVI(x) \
- (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI)
-#define BIT_GET_PKT_LIFTIME_VOVI(x) \
- (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI)
-
-/* 2 REG_STBC_SETTING (Offset 0x04C4) */
-
-#define BIT_SHIFT_CDEND_TXTIME_L 4
-#define BIT_MASK_CDEND_TXTIME_L 0xf
-#define BIT_CDEND_TXTIME_L(x) \
- (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L)
-#define BIT_GET_CDEND_TXTIME_L(x) \
- (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L)
-
-#define BIT_SHIFT_NESS 2
-#define BIT_MASK_NESS 0x3
-#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS)
-#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS)
-
-#define BIT_SHIFT_STBC_CFEND 0
-#define BIT_MASK_STBC_CFEND 0x3
-#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND)
-#define BIT_GET_STBC_CFEND(x) \
- (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND)
-
-/* 2 REG_STBC_SETTING2 (Offset 0x04C5) */
-
-#define BIT_SHIFT_CDEND_TXTIME_H 0
-#define BIT_MASK_CDEND_TXTIME_H 0x1f
-#define BIT_CDEND_TXTIME_H(x) \
- (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H)
-#define BIT_GET_CDEND_TXTIME_H(x) \
- (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H)
-
-/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */
-
-#define BIT_PTA_EDCCA_EN BIT(5)
-#define BIT_PTA_WL_TX_EN BIT(4)
-
-/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */
-
-#define BIT_R_USE_DATA_BW BIT(3)
-#define BIT_TRI_PKT_INT_MODE1 BIT(2)
-#define BIT_TRI_PKT_INT_MODE0 BIT(1)
-#define BIT_ACQ_MODE_SEL BIT(0)
-
-/* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */
-
-#define BIT_EN_SINGLE_APMDU BIT(7)
-
-/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */
-
-#define BIT_SHIFT_RTS_MAX_AGG_NUM 24
-#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f
-#define BIT_RTS_MAX_AGG_NUM(x) \
- (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM)
-#define BIT_GET_RTS_MAX_AGG_NUM(x) \
- (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM)
-
-#define BIT_SHIFT_MAX_AGG_NUM 16
-#define BIT_MASK_MAX_AGG_NUM 0x3f
-#define BIT_MAX_AGG_NUM(x) \
- (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM)
-#define BIT_GET_MAX_AGG_NUM(x) \
- (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM)
-
-#define BIT_SHIFT_RTS_TXTIME_TH 8
-#define BIT_MASK_RTS_TXTIME_TH 0xff
-#define BIT_RTS_TXTIME_TH(x) \
- (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH)
-#define BIT_GET_RTS_TXTIME_TH(x) \
- (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH)
-
-#define BIT_SHIFT_RTS_LEN_TH 0
-#define BIT_MASK_RTS_LEN_TH 0xff
-#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH)
-#define BIT_GET_RTS_LEN_TH(x) \
- (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH)
-
-/* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */
-
-#define BIT_SHIFT_BAR_RTY_LMT 16
-#define BIT_MASK_BAR_RTY_LMT 0x3
-#define BIT_BAR_RTY_LMT(x) \
- (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT)
-#define BIT_GET_BAR_RTY_LMT(x) \
- (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT)
-
-#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8
-#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff
-#define BIT_BAR_PKT_TXTIME_TH(x) \
- (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH)
-#define BIT_GET_BAR_PKT_TXTIME_TH(x) \
- (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH)
-
-#define BIT_BAR_EN_V1 BIT(6)
-
-#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0
-#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f
-#define BIT_BAR_PKTNUM_TH_V1(x) \
- (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1)
-#define BIT_GET_BAR_PKTNUM_TH_V1(x) \
- (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1)
-
-/* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */
-
-#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0
-#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f
-#define BIT_RA_TRY_RATE_AGG_LMT_V1(x) \
- (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) \
- << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1)
-#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) \
- (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & \
- BIT_MASK_RA_TRY_RATE_AGG_LMT_V1)
-
-/* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */
-
-#define BIT_SHIFT_MACID95_64PKTSLEEP 0
-#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL
-#define BIT_MACID95_64PKTSLEEP(x) \
- (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP)
-#define BIT_GET_MACID95_64PKTSLEEP(x) \
- (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP)
-
-/* 2 REG_MACID_SLEEP (Offset 0x04D4) */
-
-#define BIT_SHIFT_MACID31_0_PKTSLEEP 0
-#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL
-#define BIT_MACID31_0_PKTSLEEP(x) \
- (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP)
-#define BIT_GET_MACID31_0_PKTSLEEP(x) \
- (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP)
-
-/* 2 REG_HW_SEQ0 (Offset 0x04D8) */
-
-#define BIT_SHIFT_HW_SSN_SEQ0 0
-#define BIT_MASK_HW_SSN_SEQ0 0xfff
-#define BIT_HW_SSN_SEQ0(x) \
- (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0)
-#define BIT_GET_HW_SSN_SEQ0(x) \
- (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0)
-
-/* 2 REG_HW_SEQ1 (Offset 0x04DA) */
-
-#define BIT_SHIFT_HW_SSN_SEQ1 0
-#define BIT_MASK_HW_SSN_SEQ1 0xfff
-#define BIT_HW_SSN_SEQ1(x) \
- (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1)
-#define BIT_GET_HW_SSN_SEQ1(x) \
- (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1)
-
-/* 2 REG_HW_SEQ2 (Offset 0x04DC) */
-
-#define BIT_SHIFT_HW_SSN_SEQ2 0
-#define BIT_MASK_HW_SSN_SEQ2 0xfff
-#define BIT_HW_SSN_SEQ2(x) \
- (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2)
-#define BIT_GET_HW_SSN_SEQ2(x) \
- (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2)
-
-/* 2 REG_HW_SEQ3 (Offset 0x04DE) */
-
-#define BIT_SHIFT_HW_SSN_SEQ3 0
-#define BIT_MASK_HW_SSN_SEQ3 0xfff
-#define BIT_HW_SSN_SEQ3(x) \
- (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3)
-#define BIT_GET_HW_SSN_SEQ3(x) \
- (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3)
-
-/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */
-
-#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2
-#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff
-#define BIT_PTCL_TOTAL_PG_V2(x) \
- (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2)
-#define BIT_GET_PTCL_TOTAL_PG_V2(x) \
- (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2)
-
-/* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */
-
-#define BIT_TX_NULL_1 BIT(1)
-#define BIT_TX_NULL_0 BIT(0)
-
-/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
-
-#define BIT_PTCL_RATE_TABLE_INVALID BIT(7)
-#define BIT_FTM_T2R_ERROR BIT(6)
-
-/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
-
-#define BIT_PTCL_ERR0 BIT(5)
-#define BIT_PTCL_ERR1 BIT(4)
-#define BIT_PTCL_ERR2 BIT(3)
-#define BIT_PTCL_ERR3 BIT(2)
-#define BIT_PTCL_ERR4 BIT(1)
-#define BIT_PTCL_ERR5 BIT(0)
-
-/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */
-
-#define BIT_CLI3_TX_NULL_1 BIT(7)
-#define BIT_CLI3_TX_NULL_0 BIT(6)
-#define BIT_CLI2_TX_NULL_1 BIT(5)
-#define BIT_CLI2_TX_NULL_0 BIT(4)
-#define BIT_CLI1_TX_NULL_1 BIT(3)
-#define BIT_CLI1_TX_NULL_0 BIT(2)
-#define BIT_CLI0_TX_NULL_1 BIT(1)
-
-/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */
-
-#define BIT_CLI0_TX_NULL_0 BIT(0)
-
-/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */
-
-#define BIT_VIDEO_JUST_DROP BIT(1)
-#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0)
-
-/* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */
-
-#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0
-#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff
-#define BIT_BT_POLLUTE_PKT_CNT(x) \
- (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT)
-#define BIT_GET_BT_POLLUTE_PKT_CNT(x) \
- (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT)
-
-/* 2 REG_PTCL_DBG (Offset 0x04EC) */
-
-#define BIT_SHIFT_PTCL_DBG 0
-#define BIT_MASK_PTCL_DBG 0xffffffffL
-#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG)
-#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG)
-
-/* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */
-
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31)
-
-#define BIT_SHIFT_GTAB_ID 28
-#define BIT_MASK_GTAB_ID 0x7
-#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID)
-#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID)
-
-#define BIT_SHIFT_TRI_HEAD_ADDR 16
-#define BIT_MASK_TRI_HEAD_ADDR 0xfff
-#define BIT_TRI_HEAD_ADDR(x) \
- (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR)
-#define BIT_GET_TRI_HEAD_ADDR(x) \
- (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR)
-
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15)
-
-#define BIT_SHIFT_GTAB_ID_V1 12
-#define BIT_MASK_GTAB_ID_V1 0x7
-#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1)
-#define BIT_GET_GTAB_ID_V1(x) \
- (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1)
-
-#define BIT_DROP_TH_EN BIT(8)
-
-#define BIT_SHIFT_DROP_TH 0
-#define BIT_MASK_DROP_TH 0xff
-#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH)
-#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH)
-
-/* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */
-
-#define BIT_BCN_EN_EXTHWSEQ BIT(1)
-#define BIT_BCN_EN_HWSEQ BIT(0)
-
-/* 2 REG_MOREDATA (Offset 0x04FE) */
-
-#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3)
-#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2)
-#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0)
-
-/* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */
-
-#define BIT_SHIFT_TXOPLIMIT 16
-#define BIT_MASK_TXOPLIMIT 0x7ff
-#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT)
-#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT)
-
-#define BIT_SHIFT_CW 8
-#define BIT_MASK_CW 0xff
-#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW)
-#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW)
-
-#define BIT_SHIFT_AIFS 0
-#define BIT_MASK_AIFS 0xff
-#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS)
-#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS)
-
-/* 2 REG_BCNTCFG (Offset 0x0510) */
-
-#define BIT_SHIFT_BCNCW_MAX 12
-#define BIT_MASK_BCNCW_MAX 0xf
-#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX)
-#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX)
-
-#define BIT_SHIFT_BCNCW_MIN 8
-#define BIT_MASK_BCNCW_MIN 0xf
-#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN)
-#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN)
-
-#define BIT_SHIFT_BCNIFS 0
-#define BIT_MASK_BCNIFS 0xff
-#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS)
-#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS)
-
-/* 2 REG_PIFS (Offset 0x0512) */
-
-#define BIT_SHIFT_PIFS 0
-#define BIT_MASK_PIFS 0xff
-#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS)
-#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS)
-
-/* 2 REG_RDG_PIFS (Offset 0x0513) */
-
-#define BIT_SHIFT_RDG_PIFS 0
-#define BIT_MASK_RDG_PIFS 0xff
-#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS)
-#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS)
-
-/* 2 REG_SIFS (Offset 0x0514) */
-
-#define BIT_SHIFT_SIFS_OFDM_TRX 24
-#define BIT_MASK_SIFS_OFDM_TRX 0xff
-#define BIT_SIFS_OFDM_TRX(x) \
- (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX)
-#define BIT_GET_SIFS_OFDM_TRX(x) \
- (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX)
-
-#define BIT_SHIFT_SIFS_CCK_TRX 16
-#define BIT_MASK_SIFS_CCK_TRX 0xff
-#define BIT_SIFS_CCK_TRX(x) \
- (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX)
-#define BIT_GET_SIFS_CCK_TRX(x) \
- (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX)
-
-#define BIT_SHIFT_SIFS_OFDM_CTX 8
-#define BIT_MASK_SIFS_OFDM_CTX 0xff
-#define BIT_SIFS_OFDM_CTX(x) \
- (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX)
-#define BIT_GET_SIFS_OFDM_CTX(x) \
- (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX)
-
-#define BIT_SHIFT_SIFS_CCK_CTX 0
-#define BIT_MASK_SIFS_CCK_CTX 0xff
-#define BIT_SIFS_CCK_CTX(x) \
- (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX)
-#define BIT_GET_SIFS_CCK_CTX(x) \
- (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX)
-
-/* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */
-
-#define BIT_SHIFT_TSFTR_SNC_OFFSET 0
-#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff
-#define BIT_TSFTR_SNC_OFFSET(x) \
- (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET)
-#define BIT_GET_TSFTR_SNC_OFFSET(x) \
- (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET)
-
-/* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */
-
-#define BIT_SHIFT_AGGR_BK_TIME 0
-#define BIT_MASK_AGGR_BK_TIME 0xff
-#define BIT_AGGR_BK_TIME(x) \
- (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME)
-#define BIT_GET_AGGR_BK_TIME(x) \
- (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME)
-
-/* 2 REG_SLOT (Offset 0x051B) */
-
-#define BIT_SHIFT_SLOT 0
-#define BIT_MASK_SLOT 0xff
-#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT)
-#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT)
-
-/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */
-
-#define BIT_DIS_EDCCA BIT(15)
-#define BIT_DIS_CCA BIT(14)
-#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13)
-#define BIT_SIFS_BK_EN BIT(12)
-
-#define BIT_SHIFT_TXQ_NAV_MSK 8
-#define BIT_MASK_TXQ_NAV_MSK 0xf
-#define BIT_TXQ_NAV_MSK(x) \
- (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK)
-#define BIT_GET_TXQ_NAV_MSK(x) \
- (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK)
-
-#define BIT_DIS_CW BIT(7)
-#define BIT_NAV_END_TXOP BIT(6)
-#define BIT_RDG_END_TXOP BIT(5)
-#define BIT_AC_INBCN_HOLD BIT(4)
-#define BIT_MGTQ_TXOP_EN BIT(3)
-#define BIT_MGTQ_RTSMF_EN BIT(2)
-#define BIT_HIQ_RTSMF_EN BIT(1)
-#define BIT_BCN_RTSMF_EN BIT(0)
-
-/* 2 REG_TXPAUSE (Offset 0x0522) */
-
-#define BIT_STOP_BCN_HI_MGT BIT(7)
-#define BIT_MAC_STOPBCNQ BIT(6)
-#define BIT_MAC_STOPHIQ BIT(5)
-#define BIT_MAC_STOPMGQ BIT(4)
-#define BIT_MAC_STOPBK BIT(3)
-#define BIT_MAC_STOPBE BIT(2)
-#define BIT_MAC_STOPVI BIT(1)
-#define BIT_MAC_STOPVO BIT(0)
-
-/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */
-
-#define BIT_DIS_BT_CCA BIT(7)
-
-/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */
-
-#define BIT_DIS_TXREQ_CLR_HI BIT(5)
-#define BIT_DIS_TXREQ_CLR_MGQ BIT(4)
-#define BIT_DIS_TXREQ_CLR_VO BIT(3)
-#define BIT_DIS_TXREQ_CLR_VI BIT(2)
-#define BIT_DIS_TXREQ_CLR_BE BIT(1)
-#define BIT_DIS_TXREQ_CLR_BK BIT(0)
-
-/* 2 REG_RD_CTRL (Offset 0x0524) */
-
-#define BIT_EN_CLR_TXREQ_INCCA BIT(15)
-#define BIT_DIS_TX_OVER_BCNQ BIT(14)
-
-/* 2 REG_RD_CTRL (Offset 0x0524) */
-
-#define BIT_EN_BCNERR_INCCCA BIT(13)
-
-/* 2 REG_RD_CTRL (Offset 0x0524) */
-
-#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)
-#define BIT_DIS_TXOP_CFE BIT(10)
-#define BIT_DIS_LSIG_CFE BIT(9)
-#define BIT_DIS_STBC_CFE BIT(8)
-#define BIT_BKQ_RD_INIT_EN BIT(7)
-#define BIT_BEQ_RD_INIT_EN BIT(6)
-#define BIT_VIQ_RD_INIT_EN BIT(5)
-#define BIT_VOQ_RD_INIT_EN BIT(4)
-#define BIT_BKQ_RD_RESP_EN BIT(3)
-#define BIT_BEQ_RD_RESP_EN BIT(2)
-#define BIT_VIQ_RD_RESP_EN BIT(1)
-#define BIT_VOQ_RD_RESP_EN BIT(0)
-
-/* 2 REG_MBSSID_CTRL (Offset 0x0526) */
-
-#define BIT_MBID_BCNQ7_EN BIT(7)
-#define BIT_MBID_BCNQ6_EN BIT(6)
-#define BIT_MBID_BCNQ5_EN BIT(5)
-#define BIT_MBID_BCNQ4_EN BIT(4)
-#define BIT_MBID_BCNQ3_EN BIT(3)
-#define BIT_MBID_BCNQ2_EN BIT(2)
-#define BIT_MBID_BCNQ1_EN BIT(1)
-#define BIT_MBID_BCNQ0_EN BIT(0)
-
-/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
-
-#define BIT_P2P_CTW_ALLSTASLEEP BIT(7)
-#define BIT_P2P_OFF_DISTX_EN BIT(6)
-#define BIT_PWR_MGT_EN BIT(5)
-
-/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
-
-#define BIT_P2P_NOA1_EN BIT(2)
-#define BIT_P2P_NOA0_EN BIT(1)
-
-/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
-
-#define BIT_EN_P2P_CTWND1 BIT(23)
-
-/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
-
-#define BIT_EN_BKF_CLR_TXREQ BIT(22)
-#define BIT_EN_TSFBIT32_RST_P2P BIT(21)
-#define BIT_EN_BCN_TX_BTCCA BIT(20)
-#define BIT_DIS_PKT_TX_ATIM BIT(19)
-#define BIT_DIS_BCN_DIS_CTN BIT(18)
-#define BIT_EN_NAVEND_RST_TXOP BIT(17)
-#define BIT_EN_FILTER_CCA BIT(16)
-
-#define BIT_SHIFT_CCA_FILTER_THRS 8
-#define BIT_MASK_CCA_FILTER_THRS 0xff
-#define BIT_CCA_FILTER_THRS(x) \
- (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS)
-#define BIT_GET_CCA_FILTER_THRS(x) \
- (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS)
-
-#define BIT_SHIFT_EDCCA_THRS 0
-#define BIT_MASK_EDCCA_THRS 0xff
-#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS)
-#define BIT_GET_EDCCA_THRS(x) \
- (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS)
-
-/* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */
-
-#define BIT_SPEC_POWER_STATE BIT(7)
-#define BIT_SPEC_CTWINDOW_ON BIT(6)
-#define BIT_SPEC_BEACON_AREA_ON BIT(5)
-#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3)
-#define BIT_SPEC_FORCE_DOZE1 BIT(2)
-#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1)
-#define BIT_SPEC_FORCE_DOZE0 BIT(0)
-
-/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */
-
-#define BIT_SHIFT_BK_QUEUE_THR 24
-#define BIT_MASK_BK_QUEUE_THR 0xff
-#define BIT_BK_QUEUE_THR(x) \
- (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR)
-#define BIT_GET_BK_QUEUE_THR(x) \
- (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR)
-
-#define BIT_SHIFT_BE_QUEUE_THR 16
-#define BIT_MASK_BE_QUEUE_THR 0xff
-#define BIT_BE_QUEUE_THR(x) \
- (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR)
-#define BIT_GET_BE_QUEUE_THR(x) \
- (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR)
-
-#define BIT_SHIFT_VI_QUEUE_THR 8
-#define BIT_MASK_VI_QUEUE_THR 0xff
-#define BIT_VI_QUEUE_THR(x) \
- (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR)
-#define BIT_GET_VI_QUEUE_THR(x) \
- (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR)
-
-#define BIT_SHIFT_VO_QUEUE_THR 0
-#define BIT_MASK_VO_QUEUE_THR 0xff
-#define BIT_VO_QUEUE_THR(x) \
- (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR)
-#define BIT_GET_VO_QUEUE_THR(x) \
- (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR)
-
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
-
-#define BIT_QUEUE_INCOL_EN BIT(16)
-
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
-
-#define BIT_SHIFT_BE_TRIGGER_NUM 12
-#define BIT_MASK_BE_TRIGGER_NUM 0xf
-#define BIT_BE_TRIGGER_NUM(x) \
- (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM)
-#define BIT_GET_BE_TRIGGER_NUM(x) \
- (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM)
-
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
-
-#define BIT_SHIFT_BK_TRIGGER_NUM 8
-#define BIT_MASK_BK_TRIGGER_NUM 0xf
-#define BIT_BK_TRIGGER_NUM(x) \
- (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM)
-#define BIT_GET_BK_TRIGGER_NUM(x) \
- (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM)
-
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
-
-#define BIT_SHIFT_VI_TRIGGER_NUM 4
-#define BIT_MASK_VI_TRIGGER_NUM 0xf
-#define BIT_VI_TRIGGER_NUM(x) \
- (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM)
-#define BIT_GET_VI_TRIGGER_NUM(x) \
- (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM)
-
-#define BIT_SHIFT_VO_TRIGGER_NUM 0
-#define BIT_MASK_VO_TRIGGER_NUM 0xf
-#define BIT_VO_TRIGGER_NUM(x) \
- (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM)
-#define BIT_GET_VO_TRIGGER_NUM(x) \
- (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM)
-
-/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */
-
-#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
-#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff
-#define BIT_TBTT_HOLD_TIME_AP(x) \
- (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP)
-#define BIT_GET_TBTT_HOLD_TIME_AP(x) \
- (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP)
-
-/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */
-
-#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0
-#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf
-#define BIT_TBTT_PROHIBIT_SETUP(x) \
- (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP)
-#define BIT_GET_TBTT_PROHIBIT_SETUP(x) \
- (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP)
-
-/* 2 REG_P2PPS_STATE (Offset 0x0543) */
-
-#define BIT_POWER_STATE BIT(7)
-#define BIT_CTWINDOW_ON BIT(6)
-#define BIT_BEACON_AREA_ON BIT(5)
-#define BIT_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_NOA1_OFF_PERIOD BIT(3)
-#define BIT_FORCE_DOZE1 BIT(2)
-#define BIT_NOA0_OFF_PERIOD BIT(1)
-#define BIT_FORCE_DOZE0 BIT(0)
-
-/* 2 REG_RD_NAV_NXT (Offset 0x0544) */
-
-#define BIT_SHIFT_RD_NAV_PROT_NXT 0
-#define BIT_MASK_RD_NAV_PROT_NXT 0xffff
-#define BIT_RD_NAV_PROT_NXT(x) \
- (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT)
-#define BIT_GET_RD_NAV_PROT_NXT(x) \
- (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT)
-
-/* 2 REG_NAV_PROT_LEN (Offset 0x0546) */
-
-#define BIT_SHIFT_NAV_PROT_LEN 0
-#define BIT_MASK_NAV_PROT_LEN 0xffff
-#define BIT_NAV_PROT_LEN(x) \
- (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN)
-#define BIT_GET_NAV_PROT_LEN(x) \
- (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN)
-
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
-
-#define BIT_DIS_RX_BSSID_FIT BIT(6)
-
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
-
-#define BIT_P0_EN_TXBCN_RPT BIT(5)
-
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
-
-#define BIT_DIS_TSF_UDT BIT(4)
-#define BIT_EN_BCN_FUNCTION BIT(3)
-
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
-
-#define BIT_P0_EN_RXBCN_RPT BIT(2)
-
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
-
-#define BIT_EN_P2P_CTWINDOW BIT(1)
-#define BIT_EN_P2P_BCNQ_AREA BIT(0)
-
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
-
-#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6)
-
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
-
-#define BIT_CLI0_DIS_TSF_UDT BIT(4)
-
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
-
-#define BIT_CLI0_EN_BCN_FUNCTION BIT(3)
-
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
-
-#define BIT_CLI0_EN_RXBCN_RPT BIT(2)
-
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
-
-#define BIT_CLI0_ENP2P_CTWINDOW BIT(1)
-#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0)
-
-/* 2 REG_MBID_NUM (Offset 0x0552) */
-
-#define BIT_EN_PRE_DL_BEACON BIT(3)
-
-#define BIT_SHIFT_MBID_BCN_NUM 0
-#define BIT_MASK_MBID_BCN_NUM 0x7
-#define BIT_MBID_BCN_NUM(x) \
- (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM)
-#define BIT_GET_MBID_BCN_NUM(x) \
- (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM)
-
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
-
-#define BIT_FREECNT_RST BIT(5)
-
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
-
-#define BIT_TSFTR_CLI3_RST BIT(4)
-
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
-
-#define BIT_TSFTR_CLI2_RST BIT(3)
-
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
-
-#define BIT_TSFTR_CLI1_RST BIT(2)
-
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
-
-#define BIT_TSFTR_CLI0_RST BIT(1)
-
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
-
-#define BIT_TSFTR_RST BIT(0)
-
-/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
-
-#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28
-#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7
-#define BIT_BCN_TIMER_SEL_FWRD(x) \
- (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD)
-#define BIT_GET_BCN_TIMER_SEL_FWRD(x) \
- (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD)
-
-/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
-
-#define BIT_SHIFT_BCN_SPACE_CLINT0 16
-#define BIT_MASK_BCN_SPACE_CLINT0 0xfff
-#define BIT_BCN_SPACE_CLINT0(x) \
- (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0)
-#define BIT_GET_BCN_SPACE_CLINT0(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0)
-
-/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
-
-#define BIT_SHIFT_BCN_SPACE0 0
-#define BIT_MASK_BCN_SPACE0 0xffff
-#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0)
-#define BIT_GET_BCN_SPACE0(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0)
-
-/* 2 REG_DRVERLYINT (Offset 0x0558) */
-
-#define BIT_SHIFT_DRVERLYITV 0
-#define BIT_MASK_DRVERLYITV 0xff
-#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV)
-#define BIT_GET_DRVERLYITV(x) \
- (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV)
-
-/* 2 REG_BCNDMATIM (Offset 0x0559) */
-
-#define BIT_SHIFT_BCNDMATIM 0
-#define BIT_MASK_BCNDMATIM 0xff
-#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM)
-#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM)
-
-/* 2 REG_ATIMWND (Offset 0x055A) */
-
-#define BIT_SHIFT_ATIMWND0 0
-#define BIT_MASK_ATIMWND0 0xffff
-#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0)
-#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0)
-
-/* 2 REG_USTIME_TSF (Offset 0x055C) */
-
-#define BIT_SHIFT_USTIME_TSF_V1 0
-#define BIT_MASK_USTIME_TSF_V1 0xff
-#define BIT_USTIME_TSF_V1(x) \
- (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1)
-#define BIT_GET_USTIME_TSF_V1(x) \
- (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1)
-
-/* 2 REG_BCN_MAX_ERR (Offset 0x055D) */
-
-#define BIT_SHIFT_BCN_MAX_ERR 0
-#define BIT_MASK_BCN_MAX_ERR 0xff
-#define BIT_BCN_MAX_ERR(x) \
- (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR)
-#define BIT_GET_BCN_MAX_ERR(x) \
- (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR)
-
-/* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */
-
-#define BIT_SHIFT_CCK_RXTSF_OFFSET 0
-#define BIT_MASK_CCK_RXTSF_OFFSET 0xff
-#define BIT_CCK_RXTSF_OFFSET(x) \
- (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET)
-#define BIT_GET_CCK_RXTSF_OFFSET(x) \
- (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET)
-
-/* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */
-
-#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0
-#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff
-#define BIT_OFDM_RXTSF_OFFSET(x) \
- (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET)
-#define BIT_GET_OFDM_RXTSF_OFFSET(x) \
- (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET)
-
-/* 2 REG_TSFTR (Offset 0x0560) */
-
-#define BIT_SHIFT_TSF_TIMER 0
-#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL
-#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER)
-#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER)
-
-/* 2 REG_FREERUN_CNT (Offset 0x0568) */
-
-#define BIT_SHIFT_FREERUN_CNT 0
-#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL
-#define BIT_FREERUN_CNT(x) \
- (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT)
-#define BIT_GET_FREERUN_CNT(x) \
- (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT)
-
-/* 2 REG_ATIMWND1_V1 (Offset 0x0570) */
-
-#define BIT_SHIFT_ATIMWND1_V1 0
-#define BIT_MASK_ATIMWND1_V1 0xff
-#define BIT_ATIMWND1_V1(x) \
- (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1)
-#define BIT_GET_ATIMWND1_V1(x) \
- (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1)
-
-/* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */
-
-#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0
-#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff
-#define BIT_TBTT_PROHIBIT_INFRA(x) \
- (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA)
-#define BIT_GET_TBTT_PROHIBIT_INFRA(x) \
- (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA)
-
-/* 2 REG_CTWND (Offset 0x0572) */
-
-#define BIT_SHIFT_CTWND 0
-#define BIT_MASK_CTWND 0xff
-#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND)
-#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND)
-
-/* 2 REG_BCNIVLCUNT (Offset 0x0573) */
-
-#define BIT_SHIFT_BCNIVLCUNT 0
-#define BIT_MASK_BCNIVLCUNT 0x7f
-#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT)
-#define BIT_GET_BCNIVLCUNT(x) \
- (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT)
-
-/* 2 REG_BCNDROPCTRL (Offset 0x0574) */
-
-#define BIT_BEACON_DROP_EN BIT(7)
-
-#define BIT_SHIFT_BEACON_DROP_IVL 0
-#define BIT_MASK_BEACON_DROP_IVL 0x7f
-#define BIT_BEACON_DROP_IVL(x) \
- (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL)
-#define BIT_GET_BEACON_DROP_IVL(x) \
- (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL)
-
-/* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */
-
-#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0
-#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff
-#define BIT_HGQ_TIMEOUT_PERIOD(x) \
- (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)
-#define BIT_GET_HGQ_TIMEOUT_PERIOD(x) \
- (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD)
-
-/* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */
-
-#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0
-#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff
-#define BIT_TXCMD_TIMEOUT_PERIOD(x) \
- (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) \
- << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)
-#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) \
- (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & \
- BIT_MASK_TXCMD_TIMEOUT_PERIOD)
-
-/* 2 REG_MISC_CTRL (Offset 0x0577) */
-
-#define BIT_DIS_TRX_CAL_BCN BIT(5)
-#define BIT_DIS_TX_CAL_TBTT BIT(4)
-#define BIT_EN_FREECNT BIT(3)
-#define BIT_BCN_AGGRESSION BIT(2)
-
-#define BIT_SHIFT_DIS_SECONDARY_CCA 0
-#define BIT_MASK_DIS_SECONDARY_CCA 0x3
-#define BIT_DIS_SECONDARY_CCA(x) \
- (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA)
-#define BIT_GET_DIS_SECONDARY_CCA(x) \
- (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA)
-
-/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
-
-#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6)
-#define BIT_CLI1_DIS_TSF_UDT BIT(4)
-#define BIT_CLI1_EN_BCN_FUNCTION BIT(3)
-
-/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
-
-#define BIT_CLI1_EN_RXBCN_RPT BIT(2)
-
-/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
-
-#define BIT_CLI1_ENP2P_CTWINDOW BIT(1)
-#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0)
-
-/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
-
-#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6)
-#define BIT_CLI2_DIS_TSF_UDT BIT(4)
-#define BIT_CLI2_EN_BCN_FUNCTION BIT(3)
-
-/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
-
-#define BIT_CLI2_EN_RXBCN_RPT BIT(2)
-
-/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
-
-#define BIT_CLI2_ENP2P_CTWINDOW BIT(1)
-#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0)
-
-/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
-
-#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6)
-#define BIT_CLI3_DIS_TSF_UDT BIT(4)
-#define BIT_CLI3_EN_BCN_FUNCTION BIT(3)
-
-/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
-
-#define BIT_CLI3_EN_RXBCN_RPT BIT(2)
-
-/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
-
-#define BIT_CLI3_ENP2P_CTWINDOW BIT(1)
-#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0)
-
-/* 2 REG_EXTEND_CTRL (Offset 0x057B) */
-
-#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5)
-#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4)
-
-#define BIT_SHIFT_PORT_SEL 0
-#define BIT_MASK_PORT_SEL 0x7
-#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL)
-#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL)
-
-/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */
-
-#define BIT_P2P1_SPEC_POWER_STATE BIT(7)
-#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6)
-#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5)
-#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3)
-#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2)
-#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1)
-#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0)
-
-/* 2 REG_P2PPS1_STATE (Offset 0x057D) */
-
-#define BIT_P2P1_POWER_STATE BIT(7)
-#define BIT_P2P1_CTWINDOW_ON BIT(6)
-#define BIT_P2P1_BEACON_AREA_ON BIT(5)
-#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3)
-#define BIT_P2P1_FORCE_DOZE1 BIT(2)
-#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1)
-#define BIT_P2P1_FORCE_DOZE0 BIT(0)
-
-/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */
-
-#define BIT_P2P2_SPEC_POWER_STATE BIT(7)
-#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6)
-#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5)
-#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3)
-#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2)
-#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1)
-#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0)
-
-/* 2 REG_P2PPS2_STATE (Offset 0x057F) */
-
-#define BIT_P2P2_POWER_STATE BIT(7)
-#define BIT_P2P2_CTWINDOW_ON BIT(6)
-#define BIT_P2P2_BEACON_AREA_ON BIT(5)
-#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3)
-#define BIT_P2P2_FORCE_DOZE1 BIT(2)
-#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1)
-#define BIT_P2P2_FORCE_DOZE0 BIT(0)
-
-/* 2 REG_PS_TIMER0 (Offset 0x0580) */
-
-#define BIT_SHIFT_PSTIMER0_INT 5
-#define BIT_MASK_PSTIMER0_INT 0x7ffffff
-#define BIT_PSTIMER0_INT(x) \
- (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT)
-#define BIT_GET_PSTIMER0_INT(x) \
- (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT)
-
-/* 2 REG_PS_TIMER1 (Offset 0x0584) */
-
-#define BIT_SHIFT_PSTIMER1_INT 5
-#define BIT_MASK_PSTIMER1_INT 0x7ffffff
-#define BIT_PSTIMER1_INT(x) \
- (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT)
-#define BIT_GET_PSTIMER1_INT(x) \
- (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT)
-
-/* 2 REG_PS_TIMER2 (Offset 0x0588) */
-
-#define BIT_SHIFT_PSTIMER2_INT 5
-#define BIT_MASK_PSTIMER2_INT 0x7ffffff
-#define BIT_PSTIMER2_INT(x) \
- (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT)
-#define BIT_GET_PSTIMER2_INT(x) \
- (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT)
-
-/* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */
-
-#define BIT_SHIFT_TBTT_CTN_AREA 0
-#define BIT_MASK_TBTT_CTN_AREA 0xff
-#define BIT_TBTT_CTN_AREA(x) \
- (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA)
-#define BIT_GET_TBTT_CTN_AREA(x) \
- (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA)
-
-/* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */
-
-#define BIT_SHIFT_FORCE_BCN_IFS 0
-#define BIT_MASK_FORCE_BCN_IFS 0xff
-#define BIT_FORCE_BCN_IFS(x) \
- (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS)
-#define BIT_GET_FORCE_BCN_IFS(x) \
- (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS)
-
-/* 2 REG_TXOP_MIN (Offset 0x0590) */
-
-#define BIT_SHIFT_TXOP_MIN 0
-#define BIT_MASK_TXOP_MIN 0x3fff
-#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN)
-#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN)
-
-/* 2 REG_PRE_BKF_TIME (Offset 0x0592) */
-
-#define BIT_SHIFT_PRE_BKF_TIME 0
-#define BIT_MASK_PRE_BKF_TIME 0xff
-#define BIT_PRE_BKF_TIME(x) \
- (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME)
-#define BIT_GET_PRE_BKF_TIME(x) \
- (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME)
-
-/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */
-
-#define BIT_DTIM_BYPASS BIT(2)
-#define BIT_RTS_NAV_TXOP BIT(1)
-#define BIT_NOT_CROSS_TXOP BIT(0)
-
-/* 2 REG_ATIMWND2 (Offset 0x05A0) */
-
-#define BIT_SHIFT_ATIMWND2 0
-#define BIT_MASK_ATIMWND2 0xff
-#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2)
-#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2)
-
-/* 2 REG_ATIMWND3 (Offset 0x05A1) */
-
-#define BIT_SHIFT_ATIMWND3 0
-#define BIT_MASK_ATIMWND3 0xff
-#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3)
-#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3)
-
-/* 2 REG_ATIMWND4 (Offset 0x05A2) */
-
-#define BIT_SHIFT_ATIMWND4 0
-#define BIT_MASK_ATIMWND4 0xff
-#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4)
-#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4)
-
-/* 2 REG_ATIMWND5 (Offset 0x05A3) */
-
-#define BIT_SHIFT_ATIMWND5 0
-#define BIT_MASK_ATIMWND5 0xff
-#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5)
-#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5)
-
-/* 2 REG_ATIMWND6 (Offset 0x05A4) */
-
-#define BIT_SHIFT_ATIMWND6 0
-#define BIT_MASK_ATIMWND6 0xff
-#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6)
-#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6)
-
-/* 2 REG_ATIMWND7 (Offset 0x05A5) */
-
-#define BIT_SHIFT_ATIMWND7 0
-#define BIT_MASK_ATIMWND7 0xff
-#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7)
-#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7)
-
-/* 2 REG_ATIMUGT (Offset 0x05A6) */
-
-#define BIT_SHIFT_ATIM_URGENT 0
-#define BIT_MASK_ATIM_URGENT 0xff
-#define BIT_ATIM_URGENT(x) \
- (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT)
-#define BIT_GET_ATIM_URGENT(x) \
- (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT)
-
-/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */
-
-#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7)
-#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6)
-#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5)
-#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4)
-#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3)
-#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2)
-#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1)
-#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)
-
-/* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */
-
-#define BIT_SHIFT_DTIM_COUNT_ROOT 0
-#define BIT_MASK_DTIM_COUNT_ROOT 0xff
-#define BIT_DTIM_COUNT_ROOT(x) \
- (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT)
-#define BIT_GET_DTIM_COUNT_ROOT(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT)
-
-/* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP1 0
-#define BIT_MASK_DTIM_COUNT_VAP1 0xff
-#define BIT_DTIM_COUNT_VAP1(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1)
-#define BIT_GET_DTIM_COUNT_VAP1(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1)
-
-/* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP2 0
-#define BIT_MASK_DTIM_COUNT_VAP2 0xff
-#define BIT_DTIM_COUNT_VAP2(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2)
-#define BIT_GET_DTIM_COUNT_VAP2(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2)
-
-/* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP3 0
-#define BIT_MASK_DTIM_COUNT_VAP3 0xff
-#define BIT_DTIM_COUNT_VAP3(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3)
-#define BIT_GET_DTIM_COUNT_VAP3(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3)
-
-/* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP4 0
-#define BIT_MASK_DTIM_COUNT_VAP4 0xff
-#define BIT_DTIM_COUNT_VAP4(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4)
-#define BIT_GET_DTIM_COUNT_VAP4(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4)
-
-/* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP5 0
-#define BIT_MASK_DTIM_COUNT_VAP5 0xff
-#define BIT_DTIM_COUNT_VAP5(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5)
-#define BIT_GET_DTIM_COUNT_VAP5(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5)
-
-/* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP6 0
-#define BIT_MASK_DTIM_COUNT_VAP6 0xff
-#define BIT_DTIM_COUNT_VAP6(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6)
-#define BIT_GET_DTIM_COUNT_VAP6(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6)
-
-/* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP7 0
-#define BIT_MASK_DTIM_COUNT_VAP7 0xff
-#define BIT_DTIM_COUNT_VAP7(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7)
-#define BIT_GET_DTIM_COUNT_VAP7(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7)
-
-/* 2 REG_DIS_ATIM (Offset 0x05B0) */
-
-#define BIT_DIS_ATIM_VAP7 BIT(7)
-#define BIT_DIS_ATIM_VAP6 BIT(6)
-#define BIT_DIS_ATIM_VAP5 BIT(5)
-#define BIT_DIS_ATIM_VAP4 BIT(4)
-#define BIT_DIS_ATIM_VAP3 BIT(3)
-#define BIT_DIS_ATIM_VAP2 BIT(2)
-#define BIT_DIS_ATIM_VAP1 BIT(1)
-#define BIT_DIS_ATIM_ROOT BIT(0)
-
-/* 2 REG_EARLY_128US (Offset 0x05B1) */
-
-#define BIT_SHIFT_TSFT_SEL_TIMER1 3
-#define BIT_MASK_TSFT_SEL_TIMER1 0x7
-#define BIT_TSFT_SEL_TIMER1(x) \
- (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1)
-#define BIT_GET_TSFT_SEL_TIMER1(x) \
- (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1)
-
-#define BIT_SHIFT_EARLY_128US 0
-#define BIT_MASK_EARLY_128US 0x7
-#define BIT_EARLY_128US(x) \
- (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US)
-#define BIT_GET_EARLY_128US(x) \
- (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US)
-
-/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */
-
-#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7)
-#define BIT_P2P1_OFF_DISTX_EN BIT(6)
-#define BIT_P2P1_PWR_MGT_EN BIT(5)
-#define BIT_P2P1_NOA1_EN BIT(2)
-#define BIT_P2P1_NOA0_EN BIT(1)
-
-/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */
-
-#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7)
-#define BIT_P2P2_OFF_DISTX_EN BIT(6)
-#define BIT_P2P2_PWR_MGT_EN BIT(5)
-#define BIT_P2P2_NOA1_EN BIT(2)
-#define BIT_P2P2_NOA0_EN BIT(1)
-
-/* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */
-
-#define BIT_SHIFT_SYNC_CLI_SEL 4
-#define BIT_MASK_SYNC_CLI_SEL 0x7
-#define BIT_SYNC_CLI_SEL(x) \
- (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL)
-#define BIT_GET_SYNC_CLI_SEL(x) \
- (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL)
-
-#define BIT_SHIFT_TSFT_SEL_TIMER0 0
-#define BIT_MASK_TSFT_SEL_TIMER0 0x7
-#define BIT_TSFT_SEL_TIMER0(x) \
- (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0)
-#define BIT_GET_TSFT_SEL_TIMER0(x) \
- (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0)
-
-/* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */
-
-#define BIT_SHIFT_NOA_UNIT2_SEL 8
-#define BIT_MASK_NOA_UNIT2_SEL 0x7
-#define BIT_NOA_UNIT2_SEL(x) \
- (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL)
-#define BIT_GET_NOA_UNIT2_SEL(x) \
- (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL)
-
-#define BIT_SHIFT_NOA_UNIT1_SEL 4
-#define BIT_MASK_NOA_UNIT1_SEL 0x7
-#define BIT_NOA_UNIT1_SEL(x) \
- (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL)
-#define BIT_GET_NOA_UNIT1_SEL(x) \
- (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL)
-
-#define BIT_SHIFT_NOA_UNIT0_SEL 0
-#define BIT_MASK_NOA_UNIT0_SEL 0x7
-#define BIT_NOA_UNIT0_SEL(x) \
- (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL)
-#define BIT_GET_NOA_UNIT0_SEL(x) \
- (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL)
-
-/* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */
-
-#define BIT_SHIFT_P2POFF_DIS_TXTIME 0
-#define BIT_MASK_P2POFF_DIS_TXTIME 0xff
-#define BIT_P2POFF_DIS_TXTIME(x) \
- (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME)
-#define BIT_GET_P2POFF_DIS_TXTIME(x) \
- (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME)
-
-/* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */
-
-#define BIT_SHIFT_BCN_SPACE_CLINT2 16
-#define BIT_MASK_BCN_SPACE_CLINT2 0xfff
-#define BIT_BCN_SPACE_CLINT2(x) \
- (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2)
-#define BIT_GET_BCN_SPACE_CLINT2(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2)
-
-#define BIT_SHIFT_BCN_SPACE_CLINT1 0
-#define BIT_MASK_BCN_SPACE_CLINT1 0xfff
-#define BIT_BCN_SPACE_CLINT1(x) \
- (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1)
-#define BIT_GET_BCN_SPACE_CLINT1(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1)
-
-/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */
-
-#define BIT_SHIFT_SUB_BCN_SPACE 16
-#define BIT_MASK_SUB_BCN_SPACE 0xff
-#define BIT_SUB_BCN_SPACE(x) \
- (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE)
-#define BIT_GET_SUB_BCN_SPACE(x) \
- (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE)
-
-/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */
-
-#define BIT_SHIFT_BCN_SPACE_CLINT3 0
-#define BIT_MASK_BCN_SPACE_CLINT3 0xfff
-#define BIT_BCN_SPACE_CLINT3(x) \
- (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3)
-#define BIT_GET_BCN_SPACE_CLINT3(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3)
-
-/* 2 REG_ACMHWCTRL (Offset 0x05C0) */
-
-#define BIT_BEQ_ACM_STATUS BIT(7)
-#define BIT_VIQ_ACM_STATUS BIT(6)
-#define BIT_VOQ_ACM_STATUS BIT(5)
-#define BIT_BEQ_ACM_EN BIT(3)
-#define BIT_VIQ_ACM_EN BIT(2)
-#define BIT_VOQ_ACM_EN BIT(1)
-#define BIT_ACMHWEN BIT(0)
-
-/* 2 REG_ACMRSTCTRL (Offset 0x05C1) */
-
-#define BIT_BE_ACM_RESET_USED_TIME BIT(2)
-#define BIT_VI_ACM_RESET_USED_TIME BIT(1)
-#define BIT_VO_ACM_RESET_USED_TIME BIT(0)
-
-/* 2 REG_ACMAVG (Offset 0x05C2) */
-
-#define BIT_SHIFT_AVGPERIOD 0
-#define BIT_MASK_AVGPERIOD 0xffff
-#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD)
-#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD)
-
-/* 2 REG_VO_ADMTIME (Offset 0x05C4) */
-
-#define BIT_SHIFT_VO_ADMITTED_TIME 0
-#define BIT_MASK_VO_ADMITTED_TIME 0xffff
-#define BIT_VO_ADMITTED_TIME(x) \
- (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME)
-#define BIT_GET_VO_ADMITTED_TIME(x) \
- (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME)
-
-/* 2 REG_VI_ADMTIME (Offset 0x05C6) */
-
-#define BIT_SHIFT_VI_ADMITTED_TIME 0
-#define BIT_MASK_VI_ADMITTED_TIME 0xffff
-#define BIT_VI_ADMITTED_TIME(x) \
- (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME)
-#define BIT_GET_VI_ADMITTED_TIME(x) \
- (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME)
-
-/* 2 REG_BE_ADMTIME (Offset 0x05C8) */
-
-#define BIT_SHIFT_BE_ADMITTED_TIME 0
-#define BIT_MASK_BE_ADMITTED_TIME 0xffff
-#define BIT_BE_ADMITTED_TIME(x) \
- (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME)
-#define BIT_GET_BE_ADMITTED_TIME(x) \
- (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME)
-
-/* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */
-
-#define BIT_SHIFT_RANDOM_GEN 0
-#define BIT_MASK_RANDOM_GEN 0xffffff
-#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN)
-#define BIT_GET_RANDOM_GEN(x) \
- (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN)
-
-/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */
-
-#define BIT_SHIFT_NOA_SEL 4
-#define BIT_MASK_NOA_SEL 0x7
-#define BIT_NOA_SEL(x) (((x) & BIT_MASK_NOA_SEL) << BIT_SHIFT_NOA_SEL)
-#define BIT_GET_NOA_SEL(x) (((x) >> BIT_SHIFT_NOA_SEL) & BIT_MASK_NOA_SEL)
-
-/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */
-
-#define BIT_SHIFT_TXCMD_SEG_SEL 0
-#define BIT_MASK_TXCMD_SEG_SEL 0xf
-#define BIT_TXCMD_SEG_SEL(x) \
- (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL)
-#define BIT_GET_TXCMD_SEG_SEL(x) \
- (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL)
-
-/* 2 REG_NOA_PARAM (Offset 0x05E0) */
-
-#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_COUNT 0xff
-#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT)
-#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT)
-
-#define BIT_SHIFT_NOA_START_TIME (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_START_TIME 0xffffffffL
-#define BIT_NOA_START_TIME(x) \
- (((x) & BIT_MASK_NOA_START_TIME) << BIT_SHIFT_NOA_START_TIME)
-#define BIT_GET_NOA_START_TIME(x) \
- (((x) >> BIT_SHIFT_NOA_START_TIME) & BIT_MASK_NOA_START_TIME)
-
-#define BIT_SHIFT_NOA_INTERVAL (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_INTERVAL 0xffffffffL
-#define BIT_NOA_INTERVAL(x) \
- (((x) & BIT_MASK_NOA_INTERVAL) << BIT_SHIFT_NOA_INTERVAL)
-#define BIT_GET_NOA_INTERVAL(x) \
- (((x) >> BIT_SHIFT_NOA_INTERVAL) & BIT_MASK_NOA_INTERVAL)
-
-#define BIT_SHIFT_NOA_DURATION 0
-#define BIT_MASK_NOA_DURATION 0xffffffffL
-#define BIT_NOA_DURATION(x) \
- (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION)
-#define BIT_GET_NOA_DURATION(x) \
- (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION)
-
-/* 2 REG_P2P_RST (Offset 0x05F0) */
-
-#define BIT_P2P2_PWR_RST1 BIT(5)
-#define BIT_P2P2_PWR_RST0 BIT(4)
-#define BIT_P2P1_PWR_RST1 BIT(3)
-#define BIT_P2P1_PWR_RST0 BIT(2)
-#define BIT_P2P_PWR_RST1_V1 BIT(1)
-#define BIT_P2P_PWR_RST0_V1 BIT(0)
-
-/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
-
-#define BIT_SYNC_CLI BIT(1)
-#define BIT_SCHEDULER_RST_V1 BIT(0)
-
-/* 2 REG_SCH_TXCMD (Offset 0x05F8) */
-
-#define BIT_SHIFT_SCH_TXCMD 0
-#define BIT_MASK_SCH_TXCMD 0xffffffffL
-#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD)
-#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD)
-
-/* 2 REG_WMAC_CR (Offset 0x0600) */
-
-#define BIT_IC_MACPHY_M BIT(0)
-
-/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
-
-#define BIT_FWEN BIT(7)
-
-/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
-
-#define BIT_PHYSTS_PKT_CTRL BIT(6)
-
-/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
-
-#define BIT_APPHDR_MIDSRCH_FAIL BIT(4)
-#define BIT_FWPARSING_EN BIT(3)
-
-#define BIT_SHIFT_APPEND_MHDR_LEN 0
-#define BIT_MASK_APPEND_MHDR_LEN 0x7
-#define BIT_APPEND_MHDR_LEN(x) \
- (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN)
-#define BIT_GET_APPEND_MHDR_LEN(x) \
- (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN)
-
-/* 2 REG_TCR (Offset 0x0604) */
-
-#define BIT_WMAC_EN_RTS_ADDR BIT(31)
-#define BIT_WMAC_DISABLE_CCK BIT(30)
-#define BIT_WMAC_RAW_LEN BIT(29)
-#define BIT_WMAC_NOTX_IN_RXNDP BIT(28)
-#define BIT_WMAC_EN_EOF BIT(27)
-#define BIT_WMAC_BF_SEL BIT(26)
-#define BIT_WMAC_ANTMODE_SEL BIT(25)
-
-/* 2 REG_TCR (Offset 0x0604) */
-
-#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24)
-
-/* 2 REG_TCR (Offset 0x0604) */
-
-#define BIT_WMAC_SMOOTH_VAL BIT(23)
-
-/* 2 REG_TCR (Offset 0x0604) */
-
-#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20)
-
-/* 2 REG_TCR (Offset 0x0604) */
-
-#define BIT_WMAC_TCR_EN_20MST BIT(19)
-#define BIT_WMAC_DIS_SIGTA BIT(18)
-#define BIT_WMAC_DIS_A2B0 BIT(17)
-#define BIT_WMAC_MSK_SIGBCRC BIT(16)
-
-/* 2 REG_TCR (Offset 0x0604) */
-
-#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15)
-#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14)
-#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13)
-#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12)
-#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11)
-#define BIT_ICV BIT(10)
-#define BIT_CFEND_FORMAT BIT(9)
-#define BIT_CRC BIT(8)
-#define BIT_PWRBIT_OW_EN BIT(7)
-#define BIT_PWR_ST BIT(6)
-#define BIT_WMAC_TCR_UPD_TIMIE BIT(5)
-#define BIT_WMAC_TCR_UPD_HGQMD BIT(4)
-
-/* 2 REG_TCR (Offset 0x0604) */
-
-#define BIT_VHTSIGA1_TXPS BIT(3)
-
-/* 2 REG_TCR (Offset 0x0604) */
-
-#define BIT_PAD_SEL BIT(2)
-#define BIT_DIS_GCLK BIT(1)
-
-/* 2 REG_RCR (Offset 0x0608) */
-
-#define BIT_APP_FCS BIT(31)
-#define BIT_APP_MIC BIT(30)
-#define BIT_APP_ICV BIT(29)
-#define BIT_APP_PHYSTS BIT(28)
-#define BIT_APP_BASSN BIT(27)
-
-/* 2 REG_RCR (Offset 0x0608) */
-
-#define BIT_VHT_DACK BIT(26)
-
-/* 2 REG_RCR (Offset 0x0608) */
-
-#define BIT_TCPOFLD_EN BIT(25)
-#define BIT_ENMBID BIT(24)
-#define BIT_LSIGEN BIT(23)
-#define BIT_MFBEN BIT(22)
-#define BIT_DISCHKPPDLLEN BIT(21)
-#define BIT_PKTCTL_DLEN BIT(20)
-#define BIT_TIM_PARSER_EN BIT(18)
-#define BIT_BC_MD_EN BIT(17)
-#define BIT_UC_MD_EN BIT(16)
-#define BIT_RXSK_PERPKT BIT(15)
-#define BIT_HTC_LOC_CTRL BIT(14)
-
-/* 2 REG_RCR (Offset 0x0608) */
-
-#define BIT_RPFM_CAM_ENABLE BIT(12)
-
-/* 2 REG_RCR (Offset 0x0608) */
-
-#define BIT_TA_BCN BIT(11)
-
-/* 2 REG_RCR (Offset 0x0608) */
-
-#define BIT_DISDECMYPKT BIT(10)
-#define BIT_AICV BIT(9)
-#define BIT_ACRC32 BIT(8)
-#define BIT_CBSSID_BCN BIT(7)
-#define BIT_CBSSID_DATA BIT(6)
-#define BIT_APWRMGT BIT(5)
-#define BIT_ADD3 BIT(4)
-#define BIT_AB BIT(3)
-#define BIT_AM BIT(2)
-#define BIT_APM BIT(1)
-#define BIT_AAP BIT(0)
-
-/* 2 REG_RX_PKT_LIMIT (Offset 0x060C) */
-
-#define BIT_SHIFT_RXPKTLMT 0
-#define BIT_MASK_RXPKTLMT 0x3f
-#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT)
-#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT)
-
-/* 2 REG_RX_DLK_TIME (Offset 0x060D) */
-
-#define BIT_SHIFT_RX_DLK_TIME 0
-#define BIT_MASK_RX_DLK_TIME 0xff
-#define BIT_RX_DLK_TIME(x) \
- (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME)
-#define BIT_GET_RX_DLK_TIME(x) \
- (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME)
-
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
-
-#define BIT_DATA_RPFM15EN BIT(15)
-#define BIT_DATA_RPFM14EN BIT(14)
-#define BIT_DATA_RPFM13EN BIT(13)
-#define BIT_DATA_RPFM12EN BIT(12)
-#define BIT_DATA_RPFM11EN BIT(11)
-#define BIT_DATA_RPFM10EN BIT(10)
-#define BIT_DATA_RPFM9EN BIT(9)
-#define BIT_DATA_RPFM8EN BIT(8)
-
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
-
-#define BIT_PHYSTS_PER_PKT_MODE BIT(7)
-#define BIT_DATA_RPFM7EN BIT(7)
-
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
-
-#define BIT_DATA_RPFM6EN BIT(6)
-
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
-
-#define BIT_DATA_RPFM5EN BIT(5)
-#define BIT_DATA_RPFM4EN BIT(4)
-#define BIT_DATA_RPFM3EN BIT(3)
-#define BIT_DATA_RPFM2EN BIT(2)
-#define BIT_DATA_RPFM1EN BIT(1)
-
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
-
-#define BIT_SHIFT_DRVINFO_SZ_V1 0
-#define BIT_MASK_DRVINFO_SZ_V1 0xf
-#define BIT_DRVINFO_SZ_V1(x) \
- (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1)
-#define BIT_GET_DRVINFO_SZ_V1(x) \
- (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1)
-
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
-
-#define BIT_DATA_RPFM0EN BIT(0)
-
-/* 2 REG_MACID (Offset 0x0610) */
-
-#define BIT_SHIFT_MACID 0
-#define BIT_MASK_MACID 0xffffffffffffL
-#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID)
-#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID)
-
-/* 2 REG_BSSID (Offset 0x0618) */
-
-#define BIT_SHIFT_BSSID 0
-#define BIT_MASK_BSSID 0xffffffffffffL
-#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID)
-#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID)
-
-/* 2 REG_MAR (Offset 0x0620) */
-
-#define BIT_SHIFT_MAR 0
-#define BIT_MASK_MAR 0xffffffffffffffffL
-#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR)
-#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR)
-
-/* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */
-
-#define BIT_SHIFT_MBIDCAM_RWDATA_L 0
-#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL
-#define BIT_MBIDCAM_RWDATA_L(x) \
- (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L)
-#define BIT_GET_MBIDCAM_RWDATA_L(x) \
- (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L)
-
-/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
-
-#define BIT_MBIDCAM_POLL BIT(31)
-#define BIT_MBIDCAM_WT_EN BIT(30)
-
-#define BIT_SHIFT_MBIDCAM_ADDR 24
-#define BIT_MASK_MBIDCAM_ADDR 0x1f
-#define BIT_MBIDCAM_ADDR(x) \
- (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR)
-#define BIT_GET_MBIDCAM_ADDR(x) \
- (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR)
-
-#define BIT_MBIDCAM_VALID BIT(23)
-#define BIT_LSIC_TXOP_EN BIT(17)
-
-/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
-
-#define BIT_CTS_EN BIT(16)
-
-/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
-
-#define BIT_SHIFT_MBIDCAM_RWDATA_H 0
-#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff
-#define BIT_MBIDCAM_RWDATA_H(x) \
- (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H)
-#define BIT_GET_MBIDCAM_RWDATA_H(x) \
- (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H)
-
-/* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */
-
-#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0
-#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff
-#define BIT_WMAC_TCR_TSFT_OFS(x) \
- (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS)
-#define BIT_GET_WMAC_TCR_TSFT_OFS(x) \
- (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS)
-
-/* 2 REG_UDF_THSD (Offset 0x0632) */
-
-#define BIT_SHIFT_UDF_THSD 0
-#define BIT_MASK_UDF_THSD 0xff
-#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD)
-#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD)
-
-/* 2 REG_ZLD_NUM (Offset 0x0633) */
-
-#define BIT_SHIFT_ZLD_NUM 0
-#define BIT_MASK_ZLD_NUM 0xff
-#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM)
-#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM)
-
-/* 2 REG_STMP_THSD (Offset 0x0634) */
-
-#define BIT_SHIFT_STMP_THSD 0
-#define BIT_MASK_STMP_THSD 0xff
-#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD)
-#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD)
-
-/* 2 REG_WMAC_TXTIMEOUT (Offset 0x0635) */
-
-#define BIT_SHIFT_WMAC_TXTIMEOUT 0
-#define BIT_MASK_WMAC_TXTIMEOUT 0xff
-#define BIT_WMAC_TXTIMEOUT(x) \
- (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT)
-#define BIT_GET_WMAC_TXTIMEOUT(x) \
- (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT)
-
-/* 2 REG_MCU_TEST_2_V1 (Offset 0x0636) */
-
-#define BIT_SHIFT_MCU_RSVD_2_V1 0
-#define BIT_MASK_MCU_RSVD_2_V1 0xffff
-#define BIT_MCU_RSVD_2_V1(x) \
- (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1)
-#define BIT_GET_MCU_RSVD_2_V1(x) \
- (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1)
-
-/* 2 REG_USTIME_EDCA (Offset 0x0638) */
-
-#define BIT_SHIFT_USTIME_EDCA_V1 0
-#define BIT_MASK_USTIME_EDCA_V1 0x1ff
-#define BIT_USTIME_EDCA_V1(x) \
- (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1)
-#define BIT_GET_USTIME_EDCA_V1(x) \
- (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1)
-
-/* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */
-
-#define BIT_SHIFT_SPEC_SIFS_OFDM 8
-#define BIT_MASK_SPEC_SIFS_OFDM 0xff
-#define BIT_SPEC_SIFS_OFDM(x) \
- (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM)
-#define BIT_GET_SPEC_SIFS_OFDM(x) \
- (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM)
-
-#define BIT_SHIFT_SPEC_SIFS_CCK 0
-#define BIT_MASK_SPEC_SIFS_CCK 0xff
-#define BIT_SPEC_SIFS_CCK(x) \
- (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK)
-#define BIT_GET_SPEC_SIFS_CCK(x) \
- (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK)
-
-/* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */
-
-#define BIT_SHIFT_SIFS_R2T_CCK 8
-#define BIT_MASK_SIFS_R2T_CCK 0xff
-#define BIT_SIFS_R2T_CCK(x) \
- (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK)
-#define BIT_GET_SIFS_R2T_CCK(x) \
- (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK)
-
-#define BIT_SHIFT_SIFS_T2T_CCK 0
-#define BIT_MASK_SIFS_T2T_CCK 0xff
-#define BIT_SIFS_T2T_CCK(x) \
- (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK)
-#define BIT_GET_SIFS_T2T_CCK(x) \
- (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK)
-
-/* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */
-
-#define BIT_SHIFT_SIFS_R2T_OFDM 8
-#define BIT_MASK_SIFS_R2T_OFDM 0xff
-#define BIT_SIFS_R2T_OFDM(x) \
- (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM)
-#define BIT_GET_SIFS_R2T_OFDM(x) \
- (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM)
-
-#define BIT_SHIFT_SIFS_T2T_OFDM 0
-#define BIT_MASK_SIFS_T2T_OFDM 0xff
-#define BIT_SIFS_T2T_OFDM(x) \
- (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM)
-#define BIT_GET_SIFS_T2T_OFDM(x) \
- (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM)
-
-/* 2 REG_ACKTO (Offset 0x0640) */
-
-#define BIT_SHIFT_ACKTO 0
-#define BIT_MASK_ACKTO 0xff
-#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO)
-#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO)
-
-/* 2 REG_CTS2TO (Offset 0x0641) */
-
-#define BIT_SHIFT_CTS2TO 0
-#define BIT_MASK_CTS2TO 0xff
-#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO)
-#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO)
-
-/* 2 REG_EIFS (Offset 0x0642) */
-
-#define BIT_SHIFT_EIFS 0
-#define BIT_MASK_EIFS 0xffff
-#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS)
-#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS)
-
-/* 2 REG_NAV_CTRL (Offset 0x0650) */
-
-#define BIT_SHIFT_NAV_UPPER 16
-#define BIT_MASK_NAV_UPPER 0xff
-#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER)
-#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER)
-
-#define BIT_SHIFT_RXMYRTS_NAV 8
-#define BIT_MASK_RXMYRTS_NAV 0xf
-#define BIT_RXMYRTS_NAV(x) \
- (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV)
-#define BIT_GET_RXMYRTS_NAV(x) \
- (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV)
-
-#define BIT_SHIFT_RTSRST 0
-#define BIT_MASK_RTSRST 0xff
-#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST)
-#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST)
-
-/* 2 REG_BACAMCMD (Offset 0x0654) */
-
-#define BIT_BACAM_POLL BIT(31)
-#define BIT_BACAM_RST BIT(17)
-#define BIT_BACAM_RW BIT(16)
-
-#define BIT_SHIFT_TXSBM 14
-#define BIT_MASK_TXSBM 0x3
-#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM)
-#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM)
-
-#define BIT_SHIFT_BACAM_ADDR 0
-#define BIT_MASK_BACAM_ADDR 0x3f
-#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR)
-#define BIT_GET_BACAM_ADDR(x) \
- (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR)
-
-/* 2 REG_BACAMCONTENT (Offset 0x0658) */
-
-#define BIT_SHIFT_BA_CONTENT_H (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_BA_CONTENT_H 0xffffffffL
-#define BIT_BA_CONTENT_H(x) \
- (((x) & BIT_MASK_BA_CONTENT_H) << BIT_SHIFT_BA_CONTENT_H)
-#define BIT_GET_BA_CONTENT_H(x) \
- (((x) >> BIT_SHIFT_BA_CONTENT_H) & BIT_MASK_BA_CONTENT_H)
-
-#define BIT_SHIFT_BA_CONTENT_L 0
-#define BIT_MASK_BA_CONTENT_L 0xffffffffL
-#define BIT_BA_CONTENT_L(x) \
- (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L)
-#define BIT_GET_BA_CONTENT_L(x) \
- (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L)
-
-/* 2 REG_LBDLY (Offset 0x0660) */
-
-#define BIT_SHIFT_LBDLY 0
-#define BIT_MASK_LBDLY 0x1f
-#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY)
-#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY)
-
-/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */
-
-#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2
-#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f
-#define BIT_BITMAP_SSNBK_COUNTER(x) \
- (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) \
- << BIT_SHIFT_BITMAP_SSNBK_COUNTER)
-#define BIT_GET_BITMAP_SSNBK_COUNTER(x) \
- (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & \
- BIT_MASK_BITMAP_SSNBK_COUNTER)
-
-#define BIT_BITMAP_EN BIT(1)
-
-/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */
-
-#define BIT_WMAC_BACAM_RPMEN BIT(0)
-
-/* 2 REG_TX_RX (Offset 0x0662) */
-
-#define BIT_SHIFT_RXPKT_TYPE 2
-#define BIT_MASK_RXPKT_TYPE 0x3f
-#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE)
-#define BIT_GET_RXPKT_TYPE(x) \
- (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE)
-
-#define BIT_TXACT_IND BIT(1)
-#define BIT_RXACT_IND BIT(0)
-
-/* 2 REG_WMAC_BITMAP_CTL (Offset 0x0663) */
-
-#define BIT_BITMAP_VO BIT(7)
-#define BIT_BITMAP_VI BIT(6)
-#define BIT_BITMAP_BE BIT(5)
-#define BIT_BITMAP_BK BIT(4)
-
-#define BIT_SHIFT_BITMAP_CONDITION 2
-#define BIT_MASK_BITMAP_CONDITION 0x3
-#define BIT_BITMAP_CONDITION(x) \
- (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION)
-#define BIT_GET_BITMAP_CONDITION(x) \
- (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION)
-
-#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1)
-#define BIT_BITMAP_FORCE BIT(0)
-
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
-
-#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28
-#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf
-#define BIT_RXERR_RPT_SEL_V1_3_0(x) \
- (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) \
- << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)
-#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) \
- (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & \
- BIT_MASK_RXERR_RPT_SEL_V1_3_0)
-
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
-
-#define BIT_RXERR_RPT_RST BIT(27)
-
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
-
-#define BIT_RXERR_RPT_SEL_V1_4 BIT(26)
-
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
-
-#define BIT_W1S BIT(23)
-
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
-
-#define BIT_UD_SELECT_BSSID BIT(22)
-
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
-
-#define BIT_SHIFT_UD_SUB_TYPE 18
-#define BIT_MASK_UD_SUB_TYPE 0xf
-#define BIT_UD_SUB_TYPE(x) \
- (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE)
-#define BIT_GET_UD_SUB_TYPE(x) \
- (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE)
-
-#define BIT_SHIFT_UD_TYPE 16
-#define BIT_MASK_UD_TYPE 0x3
-#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE)
-#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE)
-
-#define BIT_SHIFT_RPT_COUNTER 0
-#define BIT_MASK_RPT_COUNTER 0xffff
-#define BIT_RPT_COUNTER(x) \
- (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER)
-#define BIT_GET_RPT_COUNTER(x) \
- (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_SHIFT_ACKBA_TYPSEL (60 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBA_TYPSEL 0xf
-#define BIT_ACKBA_TYPSEL(x) \
- (((x) & BIT_MASK_ACKBA_TYPSEL) << BIT_SHIFT_ACKBA_TYPSEL)
-#define BIT_GET_ACKBA_TYPSEL(x) \
- (((x) >> BIT_SHIFT_ACKBA_TYPSEL) & BIT_MASK_ACKBA_TYPSEL)
-
-#define BIT_SHIFT_ACKBA_ACKPCHK (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBA_ACKPCHK 0xf
-#define BIT_ACKBA_ACKPCHK(x) \
- (((x) & BIT_MASK_ACKBA_ACKPCHK) << BIT_SHIFT_ACKBA_ACKPCHK)
-#define BIT_GET_ACKBA_ACKPCHK(x) \
- (((x) >> BIT_SHIFT_ACKBA_ACKPCHK) & BIT_MASK_ACKBA_ACKPCHK)
-
-#define BIT_SHIFT_ACKBAR_TYPESEL (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBAR_TYPESEL 0xff
-#define BIT_ACKBAR_TYPESEL(x) \
- (((x) & BIT_MASK_ACKBAR_TYPESEL) << BIT_SHIFT_ACKBAR_TYPESEL)
-#define BIT_GET_ACKBAR_TYPESEL(x) \
- (((x) >> BIT_SHIFT_ACKBAR_TYPESEL) & BIT_MASK_ACKBAR_TYPESEL)
-
-#define BIT_SHIFT_ACKBAR_ACKPCHK (44 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBAR_ACKPCHK 0xf
-#define BIT_ACKBAR_ACKPCHK(x) \
- (((x) & BIT_MASK_ACKBAR_ACKPCHK) << BIT_SHIFT_ACKBAR_ACKPCHK)
-#define BIT_GET_ACKBAR_ACKPCHK(x) \
- (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK) & BIT_MASK_ACKBAR_ACKPCHK)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_RXBA_IGNOREA2 BIT(42)
-#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41)
-#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39)
-#define BIT_DIS_TXBA_RXBARINFULL BIT(38)
-#define BIT_DIS_TXCFE_INFULL BIT(37)
-#define BIT_DIS_TXCTS_INFULL BIT(36)
-#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35)
-#define BIT_EN_TXACKBA_IN_TXOP BIT(34)
-#define BIT_EN_TXCTS_IN_RXNAV BIT(33)
-#define BIT_EN_TXCTS_INTXOP BIT(32)
-#define BIT_BLK_EDCA_BBSLP BIT(31)
-#define BIT_BLK_EDCA_BBSBY BIT(30)
-#define BIT_ACKTO_BLOCK_SCH_EN BIT(27)
-#define BIT_EIFS_BLOCK_SCH_EN BIT(26)
-#define BIT_PLCPCHK_RST_EIFS BIT(25)
-#define BIT_CCA_RST_EIFS BIT(24)
-#define BIT_DIS_UPD_MYRXPKTNAV BIT(23)
-#define BIT_EARLY_TXBA BIT(22)
-
-#define BIT_SHIFT_RESP_CHNBUSY 20
-#define BIT_MASK_RESP_CHNBUSY 0x3
-#define BIT_RESP_CHNBUSY(x) \
- (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY)
-#define BIT_GET_RESP_CHNBUSY(x) \
- (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY)
-
-#define BIT_RESP_DCTS_EN BIT(19)
-#define BIT_RESP_DCFE_EN BIT(18)
-#define BIT_RESP_SPLCPEN BIT(17)
-#define BIT_RESP_SGIEN BIT(16)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_RESP_LDPC_EN BIT(15)
-#define BIT_DIS_RESP_ACKINCCA BIT(14)
-#define BIT_DIS_RESP_CTSINCCA BIT(13)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10
-#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7
-#define BIT_R_WMAC_SECOND_CCA_TIMER(x) \
- (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) \
- << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER)
-#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) \
- (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & \
- BIT_MASK_R_WMAC_SECOND_CCA_TIMER)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_SHIFT_RFMOD 7
-#define BIT_MASK_RFMOD 0x3
-#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD)
-#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5
-#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3
-#define BIT_RESP_CTS_DYNBW_SEL(x) \
- (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL)
-#define BIT_GET_RESP_CTS_DYNBW_SEL(x) \
- (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_TXRESP_BY_RXANTSEL BIT(3)
-
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_SHIFT_ORIG_DCTS_CHK 0
-#define BIT_MASK_ORIG_DCTS_CHK 0x3
-#define BIT_ORIG_DCTS_CHK(x) \
- (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK)
-#define BIT_GET_ORIG_DCTS_CHK(x) \
- (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK)
-
-/* 2 REG_CAMCMD (Offset 0x0670) */
-
-#define BIT_SECCAM_POLLING BIT(31)
-#define BIT_SECCAM_CLR BIT(30)
-#define BIT_MFBCAM_CLR BIT(29)
-
-/* 2 REG_CAMCMD (Offset 0x0670) */
-
-#define BIT_SECCAM_WE BIT(16)
-
-/* 2 REG_CAMCMD (Offset 0x0670) */
-
-#define BIT_SHIFT_SECCAM_ADDR_V2 0
-#define BIT_MASK_SECCAM_ADDR_V2 0x3ff
-#define BIT_SECCAM_ADDR_V2(x) \
- (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2)
-#define BIT_GET_SECCAM_ADDR_V2(x) \
- (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2)
-
-/* 2 REG_CAMWRITE (Offset 0x0674) */
-
-#define BIT_SHIFT_CAMW_DATA 0
-#define BIT_MASK_CAMW_DATA 0xffffffffL
-#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA)
-#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA)
-
-/* 2 REG_CAMREAD (Offset 0x0678) */
-
-#define BIT_SHIFT_CAMR_DATA 0
-#define BIT_MASK_CAMR_DATA 0xffffffffL
-#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA)
-#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA)
-
-/* 2 REG_CAMDBG (Offset 0x067C) */
-
-#define BIT_SECCAM_INFO BIT(31)
-#define BIT_SEC_KEYFOUND BIT(15)
-
-#define BIT_SHIFT_CAMDBG_SEC_TYPE 12
-#define BIT_MASK_CAMDBG_SEC_TYPE 0x7
-#define BIT_CAMDBG_SEC_TYPE(x) \
- (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE)
-#define BIT_GET_CAMDBG_SEC_TYPE(x) \
- (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE)
-
-/* 2 REG_CAMDBG (Offset 0x067C) */
-
-#define BIT_CAMDBG_EXT_SECTYPE BIT(11)
-
-/* 2 REG_CAMDBG (Offset 0x067C) */
-
-#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5
-#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f
-#define BIT_CAMDBG_MIC_KEY_IDX(x) \
- (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX)
-#define BIT_GET_CAMDBG_MIC_KEY_IDX(x) \
- (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX)
-
-#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0
-#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f
-#define BIT_CAMDBG_SEC_KEY_IDX(x) \
- (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX)
-#define BIT_GET_CAMDBG_SEC_KEY_IDX(x) \
- (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX)
-
-/* 2 REG_SECCFG (Offset 0x0680) */
-
-#define BIT_DIS_GCLK_WAPI BIT(15)
-#define BIT_DIS_GCLK_AES BIT(14)
-#define BIT_DIS_GCLK_TKIP BIT(13)
-
-/* 2 REG_SECCFG (Offset 0x0680) */
-
-#define BIT_AES_SEL_QC_1 BIT(12)
-#define BIT_AES_SEL_QC_0 BIT(11)
-
-/* 2 REG_SECCFG (Offset 0x0680) */
-
-#define BIT_CHK_BMC BIT(9)
-
-/* 2 REG_SECCFG (Offset 0x0680) */
-
-#define BIT_CHK_KEYID BIT(8)
-#define BIT_RXBCUSEDK BIT(7)
-#define BIT_TXBCUSEDK BIT(6)
-#define BIT_NOSKMC BIT(5)
-#define BIT_SKBYA2 BIT(4)
-#define BIT_RXDEC BIT(3)
-#define BIT_TXENC BIT(2)
-#define BIT_RXUHUSEDK BIT(1)
-#define BIT_TXUHUSEDK BIT(0)
-
-/* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_1 0
-#define BIT_MASK_RXFILTER_CATEGORY_1 0xff
-#define BIT_RXFILTER_CATEGORY_1(x) \
- (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1)
-#define BIT_GET_RXFILTER_CATEGORY_1(x) \
- (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1)
-
-/* 2 REG_RXFILTER_ACTION_1 (Offset 0x0683) */
-
-#define BIT_SHIFT_RXFILTER_ACTION_1 0
-#define BIT_MASK_RXFILTER_ACTION_1 0xff
-#define BIT_RXFILTER_ACTION_1(x) \
- (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1)
-#define BIT_GET_RXFILTER_ACTION_1(x) \
- (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1)
-
-/* 2 REG_RXFILTER_CATEGORY_2 (Offset 0x0684) */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_2 0
-#define BIT_MASK_RXFILTER_CATEGORY_2 0xff
-#define BIT_RXFILTER_CATEGORY_2(x) \
- (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2)
-#define BIT_GET_RXFILTER_CATEGORY_2(x) \
- (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2)
-
-/* 2 REG_RXFILTER_ACTION_2 (Offset 0x0685) */
-
-#define BIT_SHIFT_RXFILTER_ACTION_2 0
-#define BIT_MASK_RXFILTER_ACTION_2 0xff
-#define BIT_RXFILTER_ACTION_2(x) \
- (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2)
-#define BIT_GET_RXFILTER_ACTION_2(x) \
- (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2)
-
-/* 2 REG_RXFILTER_CATEGORY_3 (Offset 0x0686) */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_3 0
-#define BIT_MASK_RXFILTER_CATEGORY_3 0xff
-#define BIT_RXFILTER_CATEGORY_3(x) \
- (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3)
-#define BIT_GET_RXFILTER_CATEGORY_3(x) \
- (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3)
-
-/* 2 REG_RXFILTER_ACTION_3 (Offset 0x0687) */
-
-#define BIT_SHIFT_RXFILTER_ACTION_3 0
-#define BIT_MASK_RXFILTER_ACTION_3 0xff
-#define BIT_RXFILTER_ACTION_3(x) \
- (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3)
-#define BIT_GET_RXFILTER_ACTION_3(x) \
- (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3)
-
-/* 2 REG_RXFLTMAP3 (Offset 0x0688) */
-
-#define BIT_MGTFLT15EN_FW BIT(15)
-#define BIT_MGTFLT14EN_FW BIT(14)
-#define BIT_MGTFLT13EN_FW BIT(13)
-#define BIT_MGTFLT12EN_FW BIT(12)
-#define BIT_MGTFLT11EN_FW BIT(11)
-#define BIT_MGTFLT10EN_FW BIT(10)
-#define BIT_MGTFLT9EN_FW BIT(9)
-#define BIT_MGTFLT8EN_FW BIT(8)
-#define BIT_MGTFLT7EN_FW BIT(7)
-#define BIT_MGTFLT6EN_FW BIT(6)
-#define BIT_MGTFLT5EN_FW BIT(5)
-#define BIT_MGTFLT4EN_FW BIT(4)
-#define BIT_MGTFLT3EN_FW BIT(3)
-#define BIT_MGTFLT2EN_FW BIT(2)
-#define BIT_MGTFLT1EN_FW BIT(1)
-#define BIT_MGTFLT0EN_FW BIT(0)
-
-/* 2 REG_RXFLTMAP4 (Offset 0x068A) */
-
-#define BIT_CTRLFLT15EN_FW BIT(15)
-#define BIT_CTRLFLT14EN_FW BIT(14)
-#define BIT_CTRLFLT13EN_FW BIT(13)
-#define BIT_CTRLFLT12EN_FW BIT(12)
-#define BIT_CTRLFLT11EN_FW BIT(11)
-#define BIT_CTRLFLT10EN_FW BIT(10)
-#define BIT_CTRLFLT9EN_FW BIT(9)
-#define BIT_CTRLFLT8EN_FW BIT(8)
-#define BIT_CTRLFLT7EN_FW BIT(7)
-#define BIT_CTRLFLT6EN_FW BIT(6)
-#define BIT_CTRLFLT5EN_FW BIT(5)
-#define BIT_CTRLFLT4EN_FW BIT(4)
-#define BIT_CTRLFLT3EN_FW BIT(3)
-#define BIT_CTRLFLT2EN_FW BIT(2)
-#define BIT_CTRLFLT1EN_FW BIT(1)
-#define BIT_CTRLFLT0EN_FW BIT(0)
-
-/* 2 REG_RXFLTMAP5 (Offset 0x068C) */
-
-#define BIT_DATAFLT15EN_FW BIT(15)
-#define BIT_DATAFLT14EN_FW BIT(14)
-#define BIT_DATAFLT13EN_FW BIT(13)
-#define BIT_DATAFLT12EN_FW BIT(12)
-#define BIT_DATAFLT11EN_FW BIT(11)
-#define BIT_DATAFLT10EN_FW BIT(10)
-#define BIT_DATAFLT9EN_FW BIT(9)
-#define BIT_DATAFLT8EN_FW BIT(8)
-#define BIT_DATAFLT7EN_FW BIT(7)
-#define BIT_DATAFLT6EN_FW BIT(6)
-#define BIT_DATAFLT5EN_FW BIT(5)
-#define BIT_DATAFLT4EN_FW BIT(4)
-#define BIT_DATAFLT3EN_FW BIT(3)
-#define BIT_DATAFLT2EN_FW BIT(2)
-#define BIT_DATAFLT1EN_FW BIT(1)
-#define BIT_DATAFLT0EN_FW BIT(0)
-
-/* 2 REG_RXFLTMAP6 (Offset 0x068E) */
-
-#define BIT_ACTIONFLT15EN_FW BIT(15)
-#define BIT_ACTIONFLT14EN_FW BIT(14)
-#define BIT_ACTIONFLT13EN_FW BIT(13)
-#define BIT_ACTIONFLT12EN_FW BIT(12)
-#define BIT_ACTIONFLT11EN_FW BIT(11)
-#define BIT_ACTIONFLT10EN_FW BIT(10)
-#define BIT_ACTIONFLT9EN_FW BIT(9)
-#define BIT_ACTIONFLT8EN_FW BIT(8)
-#define BIT_ACTIONFLT7EN_FW BIT(7)
-#define BIT_ACTIONFLT6EN_FW BIT(6)
-#define BIT_ACTIONFLT5EN_FW BIT(5)
-#define BIT_ACTIONFLT4EN_FW BIT(4)
-#define BIT_ACTIONFLT3EN_FW BIT(3)
-#define BIT_ACTIONFLT2EN_FW BIT(2)
-#define BIT_ACTIONFLT1EN_FW BIT(1)
-#define BIT_ACTIONFLT0EN_FW BIT(0)
-
-/* 2 REG_WOW_CTRL (Offset 0x0690) */
-
-#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6
-#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3
-#define BIT_PSF_BSSIDSEL_B2B1(x) \
- (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1)
-#define BIT_GET_PSF_BSSIDSEL_B2B1(x) \
- (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1)
-
-/* 2 REG_WOW_CTRL (Offset 0x0690) */
-
-#define BIT_WOWHCI BIT(5)
-
-/* 2 REG_WOW_CTRL (Offset 0x0690) */
-
-#define BIT_PSF_BSSIDSEL_B0 BIT(4)
-
-/* 2 REG_WOW_CTRL (Offset 0x0690) */
-
-#define BIT_UWF BIT(3)
-#define BIT_MAGIC BIT(2)
-#define BIT_WOWEN BIT(1)
-#define BIT_FORCE_WAKEUP BIT(0)
-
-/* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */
-
-#define BIT_CHK_TSF_TA BIT(2)
-#define BIT_CHK_TSF_CBSSID BIT(1)
-#define BIT_CHK_TSF_EN BIT(0)
-
-/* 2 REG_PS_RX_INFO (Offset 0x0692) */
-
-#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5
-#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7
-#define BIT_PORTSEL__PS_RX_INFO(x) \
- (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO)
-#define BIT_GET_PORTSEL__PS_RX_INFO(x) \
- (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO)
-
-/* 2 REG_PS_RX_INFO (Offset 0x0692) */
-
-#define BIT_RXCTRLIN0 BIT(4)
-#define BIT_RXMGTIN0 BIT(3)
-#define BIT_RXDATAIN2 BIT(2)
-#define BIT_RXDATAIN1 BIT(1)
-#define BIT_RXDATAIN0 BIT(0)
-
-/* 2 REG_WMMPS_UAPSD_TID (Offset 0x0693) */
-
-#define BIT_WMMPS_UAPSD_TID7 BIT(7)
-#define BIT_WMMPS_UAPSD_TID6 BIT(6)
-#define BIT_WMMPS_UAPSD_TID5 BIT(5)
-#define BIT_WMMPS_UAPSD_TID4 BIT(4)
-#define BIT_WMMPS_UAPSD_TID3 BIT(3)
-#define BIT_WMMPS_UAPSD_TID2 BIT(2)
-#define BIT_WMMPS_UAPSD_TID1 BIT(1)
-#define BIT_WMMPS_UAPSD_TID0 BIT(0)
-
-/* 2 REG_LPNAV_CTRL (Offset 0x0694) */
-
-#define BIT_LPNAV_EN BIT(31)
-
-#define BIT_SHIFT_LPNAV_EARLY 16
-#define BIT_MASK_LPNAV_EARLY 0x7fff
-#define BIT_LPNAV_EARLY(x) \
- (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY)
-#define BIT_GET_LPNAV_EARLY(x) \
- (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY)
-
-#define BIT_SHIFT_LPNAV_TH 0
-#define BIT_MASK_LPNAV_TH 0xffff
-#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH)
-#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH)
-
-/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
-
-#define BIT_WKFCAM_POLLING_V1 BIT(31)
-#define BIT_WKFCAM_CLR_V1 BIT(30)
-
-/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
-
-#define BIT_WKFCAM_WE BIT(16)
-
-/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
-
-#define BIT_SHIFT_WKFCAM_ADDR_V2 8
-#define BIT_MASK_WKFCAM_ADDR_V2 0xff
-#define BIT_WKFCAM_ADDR_V2(x) \
- (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
-#define BIT_GET_WKFCAM_ADDR_V2(x) \
- (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2)
-
-#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0
-#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff
-#define BIT_WKFCAM_CAM_NUM_V1(x) \
- (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1)
-#define BIT_GET_WKFCAM_CAM_NUM_V1(x) \
- (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1)
-
-/* 2 REG_WKFMCAM_RWD (Offset 0x069C) */
-
-#define BIT_SHIFT_WKFMCAM_RWD 0
-#define BIT_MASK_WKFMCAM_RWD 0xffffffffL
-#define BIT_WKFMCAM_RWD(x) \
- (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD)
-#define BIT_GET_WKFMCAM_RWD(x) \
- (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD)
-
-/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
-
-#define BIT_MGTFLT15EN BIT(15)
-#define BIT_MGTFLT14EN BIT(14)
-
-/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
-
-#define BIT_MGTFLT13EN BIT(13)
-#define BIT_MGTFLT12EN BIT(12)
-#define BIT_MGTFLT11EN BIT(11)
-#define BIT_MGTFLT10EN BIT(10)
-#define BIT_MGTFLT9EN BIT(9)
-#define BIT_MGTFLT8EN BIT(8)
-
-/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
-
-#define BIT_MGTFLT7EN BIT(7)
-#define BIT_MGTFLT6EN BIT(6)
-
-/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
-
-#define BIT_MGTFLT5EN BIT(5)
-#define BIT_MGTFLT4EN BIT(4)
-#define BIT_MGTFLT3EN BIT(3)
-#define BIT_MGTFLT2EN BIT(2)
-#define BIT_MGTFLT1EN BIT(1)
-#define BIT_MGTFLT0EN BIT(0)
-
-/* 2 REG_RXFLTMAP1 (Offset 0x06A2) */
-
-#define BIT_CTRLFLT15EN BIT(15)
-#define BIT_CTRLFLT14EN BIT(14)
-#define BIT_CTRLFLT13EN BIT(13)
-#define BIT_CTRLFLT12EN BIT(12)
-#define BIT_CTRLFLT11EN BIT(11)
-#define BIT_CTRLFLT10EN BIT(10)
-#define BIT_CTRLFLT9EN BIT(9)
-#define BIT_CTRLFLT8EN BIT(8)
-#define BIT_CTRLFLT7EN BIT(7)
-#define BIT_CTRLFLT6EN BIT(6)
-
-/* 2 REG_RXFLTMAP1 (Offset 0x06A2) */
-
-#define BIT_CTRLFLT5EN BIT(5)
-#define BIT_CTRLFLT4EN BIT(4)
-#define BIT_CTRLFLT3EN BIT(3)
-#define BIT_CTRLFLT2EN BIT(2)
-#define BIT_CTRLFLT1EN BIT(1)
-#define BIT_CTRLFLT0EN BIT(0)
-
-/* 2 REG_RXFLTMAP (Offset 0x06A4) */
-
-#define BIT_DATAFLT15EN BIT(15)
-#define BIT_DATAFLT14EN BIT(14)
-#define BIT_DATAFLT13EN BIT(13)
-#define BIT_DATAFLT12EN BIT(12)
-#define BIT_DATAFLT11EN BIT(11)
-#define BIT_DATAFLT10EN BIT(10)
-#define BIT_DATAFLT9EN BIT(9)
-#define BIT_DATAFLT8EN BIT(8)
-#define BIT_DATAFLT7EN BIT(7)
-#define BIT_DATAFLT6EN BIT(6)
-#define BIT_DATAFLT5EN BIT(5)
-#define BIT_DATAFLT4EN BIT(4)
-#define BIT_DATAFLT3EN BIT(3)
-#define BIT_DATAFLT2EN BIT(2)
-#define BIT_DATAFLT1EN BIT(1)
-#define BIT_DATAFLT0EN BIT(0)
-
-/* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */
-
-#define BIT_SHIFT_DTIM_CNT 24
-#define BIT_MASK_DTIM_CNT 0xff
-#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT)
-#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT)
-
-#define BIT_SHIFT_DTIM_PERIOD 16
-#define BIT_MASK_DTIM_PERIOD 0xff
-#define BIT_DTIM_PERIOD(x) \
- (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD)
-#define BIT_GET_DTIM_PERIOD(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD)
-
-#define BIT_DTIM BIT(15)
-#define BIT_TIM BIT(14)
-
-#define BIT_SHIFT_PS_AID_0 0
-#define BIT_MASK_PS_AID_0 0x7ff
-#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0)
-#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0)
-
-/* 2 REG_FLC_RPC (Offset 0x06AC) */
-
-#define BIT_SHIFT_FLC_RPC 0
-#define BIT_MASK_FLC_RPC 0xff
-#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC)
-#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC)
-
-/* 2 REG_FLC_RPCT (Offset 0x06AD) */
-
-#define BIT_SHIFT_FLC_RPCT 0
-#define BIT_MASK_FLC_RPCT 0xff
-#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT)
-#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT)
-
-/* 2 REG_FLC_PTS (Offset 0x06AE) */
-
-#define BIT_CMF BIT(2)
-#define BIT_CCF BIT(1)
-#define BIT_CDF BIT(0)
-
-/* 2 REG_FLC_TRPC (Offset 0x06AF) */
-
-#define BIT_FLC_RPCT_V1 BIT(7)
-#define BIT_MODE BIT(6)
-
-#define BIT_SHIFT_TRPCD 0
-#define BIT_MASK_TRPCD 0x3f
-#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD)
-#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD)
-
-/* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */
-
-#define BIT_SHIFT_RXBKQPKT_SEQ 20
-#define BIT_MASK_RXBKQPKT_SEQ 0xf
-#define BIT_RXBKQPKT_SEQ(x) \
- (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ)
-#define BIT_GET_RXBKQPKT_SEQ(x) \
- (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ)
-
-#define BIT_SHIFT_RXBEQPKT_SEQ 16
-#define BIT_MASK_RXBEQPKT_SEQ 0xf
-#define BIT_RXBEQPKT_SEQ(x) \
- (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ)
-#define BIT_GET_RXBEQPKT_SEQ(x) \
- (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ)
-
-#define BIT_SHIFT_RXVIQPKT_SEQ 12
-#define BIT_MASK_RXVIQPKT_SEQ 0xf
-#define BIT_RXVIQPKT_SEQ(x) \
- (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ)
-#define BIT_GET_RXVIQPKT_SEQ(x) \
- (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ)
-
-#define BIT_SHIFT_RXVOQPKT_SEQ 8
-#define BIT_MASK_RXVOQPKT_SEQ 0xf
-#define BIT_RXVOQPKT_SEQ(x) \
- (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ)
-#define BIT_GET_RXVOQPKT_SEQ(x) \
- (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ)
-
-#define BIT_RXBKQPKT_ERR BIT(7)
-#define BIT_RXBEQPKT_ERR BIT(6)
-#define BIT_RXVIQPKT_ERR BIT(5)
-#define BIT_RXVOQPKT_ERR BIT(4)
-#define BIT_RXDMA_MON_EN BIT(2)
-#define BIT_RXPKT_MON_RST BIT(1)
-#define BIT_RXPKT_MON_EN BIT(0)
-
-/* 2 REG_STATE_MON (Offset 0x06B4) */
-
-#define BIT_SHIFT_STATE_SEL 24
-#define BIT_MASK_STATE_SEL 0x1f
-#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL)
-#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL)
-
-#define BIT_SHIFT_STATE_INFO 8
-#define BIT_MASK_STATE_INFO 0xff
-#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO)
-#define BIT_GET_STATE_INFO(x) \
- (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO)
-
-#define BIT_UPD_NXT_STATE BIT(7)
-
-/* 2 REG_STATE_MON (Offset 0x06B4) */
-
-#define BIT_SHIFT_CUR_STATE 0
-#define BIT_MASK_CUR_STATE 0x7f
-#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE)
-#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE)
-
-/* 2 REG_ERROR_MON (Offset 0x06B8) */
-
-#define BIT_MACRX_ERR_1 BIT(17)
-#define BIT_MACRX_ERR_0 BIT(16)
-#define BIT_MACTX_ERR_3 BIT(3)
-#define BIT_MACTX_ERR_2 BIT(2)
-#define BIT_MACTX_ERR_1 BIT(1)
-#define BIT_MACTX_ERR_0 BIT(0)
-
-/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
-
-#define BIT_EN_TXRPTBUF_CLK BIT(31)
-
-#define BIT_SHIFT_INFO_INDEX_OFFSET 16
-#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff
-#define BIT_INFO_INDEX_OFFSET(x) \
- (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET)
-#define BIT_GET_INFO_INDEX_OFFSET(x) \
- (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET)
-
-/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
-
-#define BIT_WMAC_SRCH_FIFOFULL BIT(15)
-
-/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
-
-#define BIT_DIS_INFOSRCH BIT(14)
-#define BIT_DISABLE_B0 BIT(13)
-
-#define BIT_SHIFT_INFO_ADDR_OFFSET 0
-#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff
-#define BIT_INFO_ADDR_OFFSET(x) \
- (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET)
-#define BIT_GET_INFO_ADDR_OFFSET(x) \
- (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET)
-
-/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */
-
-#define BIT_PRI_MASK_RX_RESP BIT(126)
-#define BIT_PRI_MASK_RXOFDM BIT(125)
-#define BIT_PRI_MASK_RXCCK BIT(124)
-
-#define BIT_SHIFT_PRI_MASK_TXAC (117 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_TXAC 0x7f
-#define BIT_PRI_MASK_TXAC(x) \
- (((x) & BIT_MASK_PRI_MASK_TXAC) << BIT_SHIFT_PRI_MASK_TXAC)
-#define BIT_GET_PRI_MASK_TXAC(x) \
- (((x) >> BIT_SHIFT_PRI_MASK_TXAC) & BIT_MASK_PRI_MASK_TXAC)
-
-#define BIT_SHIFT_PRI_MASK_NAV (109 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_NAV 0xff
-#define BIT_PRI_MASK_NAV(x) \
- (((x) & BIT_MASK_PRI_MASK_NAV) << BIT_SHIFT_PRI_MASK_NAV)
-#define BIT_GET_PRI_MASK_NAV(x) \
- (((x) >> BIT_SHIFT_PRI_MASK_NAV) & BIT_MASK_PRI_MASK_NAV)
-
-#define BIT_PRI_MASK_CCK BIT(108)
-#define BIT_PRI_MASK_OFDM BIT(107)
-#define BIT_PRI_MASK_RTY BIT(106)
-
-#define BIT_SHIFT_PRI_MASK_NUM (102 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_NUM 0xf
-#define BIT_PRI_MASK_NUM(x) \
- (((x) & BIT_MASK_PRI_MASK_NUM) << BIT_SHIFT_PRI_MASK_NUM)
-#define BIT_GET_PRI_MASK_NUM(x) \
- (((x) >> BIT_SHIFT_PRI_MASK_NUM) & BIT_MASK_PRI_MASK_NUM)
-
-#define BIT_SHIFT_PRI_MASK_TYPE (98 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_TYPE 0xf
-#define BIT_PRI_MASK_TYPE(x) \
- (((x) & BIT_MASK_PRI_MASK_TYPE) << BIT_SHIFT_PRI_MASK_TYPE)
-#define BIT_GET_PRI_MASK_TYPE(x) \
- (((x) >> BIT_SHIFT_PRI_MASK_TYPE) & BIT_MASK_PRI_MASK_TYPE)
-
-#define BIT_OOB BIT(97)
-#define BIT_ANT_SEL BIT(96)
-
-#define BIT_SHIFT_BREAK_TABLE_2 (80 & CPU_OPT_WIDTH)
-#define BIT_MASK_BREAK_TABLE_2 0xffff
-#define BIT_BREAK_TABLE_2(x) \
- (((x) & BIT_MASK_BREAK_TABLE_2) << BIT_SHIFT_BREAK_TABLE_2)
-#define BIT_GET_BREAK_TABLE_2(x) \
- (((x) >> BIT_SHIFT_BREAK_TABLE_2) & BIT_MASK_BREAK_TABLE_2)
-
-#define BIT_SHIFT_BREAK_TABLE_1 (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_BREAK_TABLE_1 0xffff
-#define BIT_BREAK_TABLE_1(x) \
- (((x) & BIT_MASK_BREAK_TABLE_1) << BIT_SHIFT_BREAK_TABLE_1)
-#define BIT_GET_BREAK_TABLE_1(x) \
- (((x) >> BIT_SHIFT_BREAK_TABLE_1) & BIT_MASK_BREAK_TABLE_1)
-
-#define BIT_SHIFT_COEX_TABLE_2 (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_COEX_TABLE_2 0xffffffffL
-#define BIT_COEX_TABLE_2(x) \
- (((x) & BIT_MASK_COEX_TABLE_2) << BIT_SHIFT_COEX_TABLE_2)
-#define BIT_GET_COEX_TABLE_2(x) \
- (((x) >> BIT_SHIFT_COEX_TABLE_2) & BIT_MASK_COEX_TABLE_2)
-
-#define BIT_SHIFT_COEX_TABLE_1 0
-#define BIT_MASK_COEX_TABLE_1 0xffffffffL
-#define BIT_COEX_TABLE_1(x) \
- (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1)
-#define BIT_GET_COEX_TABLE_1(x) \
- (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1)
-
-/* 2 REG_RXCMD_0 (Offset 0x06D0) */
-
-#define BIT_RXCMD_EN BIT(31)
-
-#define BIT_SHIFT_RXCMD_INFO 0
-#define BIT_MASK_RXCMD_INFO 0x7fffffffL
-#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO)
-#define BIT_GET_RXCMD_INFO(x) \
- (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO)
-
-/* 2 REG_RXCMD_1 (Offset 0x06D4) */
-
-#define BIT_SHIFT_RXCMD_PRD 0
-#define BIT_MASK_RXCMD_PRD 0xffff
-#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD)
-#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD)
-
-/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
-
-#define BIT_SHIFT_WMAC_RESP_MFB 25
-#define BIT_MASK_WMAC_RESP_MFB 0x7f
-#define BIT_WMAC_RESP_MFB(x) \
- (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB)
-#define BIT_GET_WMAC_RESP_MFB(x) \
- (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB)
-
-#define BIT_SHIFT_WMAC_ANTINF_SEL 23
-#define BIT_MASK_WMAC_ANTINF_SEL 0x3
-#define BIT_WMAC_ANTINF_SEL(x) \
- (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL)
-#define BIT_GET_WMAC_ANTINF_SEL(x) \
- (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL)
-
-#define BIT_SHIFT_WMAC_ANTSEL_SEL 21
-#define BIT_MASK_WMAC_ANTSEL_SEL 0x3
-#define BIT_WMAC_ANTSEL_SEL(x) \
- (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL)
-#define BIT_GET_WMAC_ANTSEL_SEL(x) \
- (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL)
-
-/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
-
-#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18
-#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7
-#define BIT_R_WMAC_RESP_TXPOWER(x) \
- (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER)
-#define BIT_GET_R_WMAC_RESP_TXPOWER(x) \
- (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER)
-
-/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
-
-#define BIT_SHIFT_WMAC_RESP_TXANT 0
-#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff
-#define BIT_WMAC_RESP_TXANT(x) \
- (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT)
-#define BIT_GET_WMAC_RESP_TXANT(x) \
- (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT)
-
-/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
-
-#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31)
-
-/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
-
-#define BIT_WMAC_USE_NDPARATE BIT(30)
-
-#define BIT_SHIFT_WMAC_CSI_RATE 24
-#define BIT_MASK_WMAC_CSI_RATE 0x3f
-#define BIT_WMAC_CSI_RATE(x) \
- (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE)
-#define BIT_GET_WMAC_CSI_RATE(x) \
- (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE)
-
-#define BIT_SHIFT_WMAC_RESP_TXRATE 16
-#define BIT_MASK_WMAC_RESP_TXRATE 0xff
-#define BIT_WMAC_RESP_TXRATE(x) \
- (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE)
-#define BIT_GET_WMAC_RESP_TXRATE(x) \
- (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE)
-
-/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
-
-#define BIT_BBPSF_MPDUCHKEN BIT(5)
-
-/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
-
-#define BIT_BBPSF_MHCHKEN BIT(4)
-#define BIT_BBPSF_ERRCHKEN BIT(3)
-
-#define BIT_SHIFT_BBPSF_ERRTHR 0
-#define BIT_MASK_BBPSF_ERRTHR 0x7
-#define BIT_BBPSF_ERRTHR(x) \
- (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR)
-#define BIT_GET_BBPSF_ERRTHR(x) \
- (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR)
-
-/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */
-
-#define BIT_NOA_PARSER_EN BIT(15)
-
-/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */
-
-#define BIT_BSSID_SEL BIT(14)
-
-/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */
-
-#define BIT_SHIFT_P2P_OUI_TYPE 0
-#define BIT_MASK_P2P_OUI_TYPE 0xff
-#define BIT_P2P_OUI_TYPE(x) \
- (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE)
-#define BIT_GET_P2P_OUI_TYPE(x) \
- (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE)
-
-/* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */
-
-#define BIT_SHIFT_R_WMAC_TXCSI_AID0 (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_TXCSI_AID0 0x1ff
-#define BIT_R_WMAC_TXCSI_AID0(x) \
- (((x) & BIT_MASK_R_WMAC_TXCSI_AID0) << BIT_SHIFT_R_WMAC_TXCSI_AID0)
-#define BIT_GET_R_WMAC_TXCSI_AID0(x) \
- (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0) & BIT_MASK_R_WMAC_TXCSI_AID0)
-
-#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0
-#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R0(x) \
- (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) \
- << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) \
- (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & \
- BIT_MASK_R_WMAC_SOUNDING_RXADD_R0)
-
-/* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */
-
-#define BIT_SHIFT_R_WMAC_TXCSI_AID1 (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_TXCSI_AID1 0x1ff
-#define BIT_R_WMAC_TXCSI_AID1(x) \
- (((x) & BIT_MASK_R_WMAC_TXCSI_AID1) << BIT_SHIFT_R_WMAC_TXCSI_AID1)
-#define BIT_GET_R_WMAC_TXCSI_AID1(x) \
- (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1) & BIT_MASK_R_WMAC_TXCSI_AID1)
-
-#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0
-#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R1(x) \
- (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) \
- << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) \
- (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & \
- BIT_MASK_R_WMAC_SOUNDING_RXADD_R1)
-
-/* 2 REG_TX_CSI_RPT_PARAM_BW20 (Offset 0x06F4) */
-
-#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16
-#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff
-#define BIT_R_WMAC_BFINFO_20M_1(x) \
- (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1)
-#define BIT_GET_R_WMAC_BFINFO_20M_1(x) \
- (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1)
-
-#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0
-#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff
-#define BIT_R_WMAC_BFINFO_20M_0(x) \
- (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0)
-#define BIT_GET_R_WMAC_BFINFO_20M_0(x) \
- (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0)
-
-/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */
-
-#define BIT_SHIFT_WMAC_RESP_ANTCD 0
-#define BIT_MASK_WMAC_RESP_ANTCD 0xf
-#define BIT_WMAC_RESP_ANTCD(x) \
- (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD)
-#define BIT_GET_WMAC_RESP_ANTCD(x) \
- (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD)
-
-/* 2 REG_MACID1 (Offset 0x0700) */
-
-#define BIT_SHIFT_MACID1 0
-#define BIT_MASK_MACID1 0xffffffffffffL
-#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1)
-#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1)
-
-/* 2 REG_BSSID1 (Offset 0x0708) */
-
-#define BIT_SHIFT_BSSID1 0
-#define BIT_MASK_BSSID1 0xffffffffffffL
-#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1)
-#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1)
-
-/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */
-
-#define BIT_SHIFT_DTIM_CNT1 24
-#define BIT_MASK_DTIM_CNT1 0xff
-#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1)
-#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1)
-
-#define BIT_SHIFT_DTIM_PERIOD1 16
-#define BIT_MASK_DTIM_PERIOD1 0xff
-#define BIT_DTIM_PERIOD1(x) \
- (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1)
-#define BIT_GET_DTIM_PERIOD1(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1)
-
-#define BIT_DTIM1 BIT(15)
-#define BIT_TIM1 BIT(14)
-
-#define BIT_SHIFT_PS_AID_1 0
-#define BIT_MASK_PS_AID_1 0x7ff
-#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1)
-#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1)
-
-/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */
-
-#define BIT_TXUSER_ID1 BIT(25)
-
-#define BIT_SHIFT_AID1 16
-#define BIT_MASK_AID1 0x1ff
-#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1)
-#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1)
-
-#define BIT_TXUSER_ID0 BIT(9)
-
-#define BIT_SHIFT_AID0 0
-#define BIT_MASK_AID0 0x1ff
-#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0)
-#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0)
-
-/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
-
-#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24
-#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff
-#define BIT_NDP_RX_STANDBY_TIMER(x) \
- (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) \
- << BIT_SHIFT_NDP_RX_STANDBY_TIMER)
-#define BIT_GET_NDP_RX_STANDBY_TIMER(x) \
- (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & \
- BIT_MASK_NDP_RX_STANDBY_TIMER)
-
-#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16
-#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff
-#define BIT_CSI_RPT_OFFSET_HT(x) \
- (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT)
-#define BIT_GET_CSI_RPT_OFFSET_HT(x) \
- (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT)
-
-/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
-
-#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8
-#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff
-#define BIT_R_WMAC_VHT_CATEGORY(x) \
- (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY)
-#define BIT_GET_R_WMAC_VHT_CATEGORY(x) \
- (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY)
-
-/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
-
-#define BIT_R_WMAC_USE_NSTS BIT(7)
-#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6)
-#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5)
-#define BIT_R_WMAC_BFPARAM_SEL BIT(4)
-#define BIT_R_WMAC_CSISEQ_SEL BIT(3)
-#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2)
-#define BIT_R_WMAC_HT_NDPA_EN BIT(1)
-#define BIT_R_WMAC_VHT_NDPA_EN BIT(0)
-
-/* 2 REG_NS_ARP_CTRL (Offset 0x0720) */
-
-#define BIT_R_WMAC_NSARP_RSPEN BIT(15)
-#define BIT_R_WMAC_NSARP_RARP BIT(9)
-#define BIT_R_WMAC_NSARP_RIPV6 BIT(8)
-
-#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6
-#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3
-#define BIT_R_WMAC_NSARP_MODEN(x) \
- (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN)
-#define BIT_GET_R_WMAC_NSARP_MODEN(x) \
- (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN)
-
-#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4
-#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3
-#define BIT_R_WMAC_NSARP_RSPFTP(x) \
- (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP)
-#define BIT_GET_R_WMAC_NSARP_RSPFTP(x) \
- (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP)
-
-#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0
-#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf
-#define BIT_R_WMAC_NSARP_RSPSEC(x) \
- (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC)
-#define BIT_GET_R_WMAC_NSARP_RSPSEC(x) \
- (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC)
-
-/* 2 REG_NS_ARP_INFO (Offset 0x0724) */
-
-#define BIT_REQ_IS_MCNS BIT(23)
-#define BIT_REQ_IS_UCNS BIT(22)
-#define BIT_REQ_IS_USNS BIT(21)
-#define BIT_REQ_IS_ARP BIT(20)
-#define BIT_EXPRSP_MH_WITHQC BIT(19)
-
-#define BIT_SHIFT_EXPRSP_SECTYPE 16
-#define BIT_MASK_EXPRSP_SECTYPE 0x7
-#define BIT_EXPRSP_SECTYPE(x) \
- (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE)
-#define BIT_GET_EXPRSP_SECTYPE(x) \
- (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE)
-
-#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8
-#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff
-#define BIT_EXPRSP_CHKSM_7_TO_0(x) \
- (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0)
-#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) \
- (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0)
-
-#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0
-#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff
-#define BIT_EXPRSP_CHKSM_15_TO_8(x) \
- (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) \
- << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8)
-#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) \
- (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & \
- BIT_MASK_EXPRSP_CHKSM_15_TO_8)
-
-/* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */
-
-#define BIT_SHIFT_WMAC_ARPIP 0
-#define BIT_MASK_WMAC_ARPIP 0xffffffffL
-#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP)
-#define BIT_GET_WMAC_ARPIP(x) \
- (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP)
-
-/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */
-
-#define BIT_SHIFT_BEAMFORMING_INFO 0
-#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL
-#define BIT_BEAMFORMING_INFO(x) \
- (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO)
-#define BIT_GET_BEAMFORMING_INFO(x) \
- (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO)
-
-/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */
-
-#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4
-#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf
-#define BIT_R_WMAC_CTX_SUBTYPE(x) \
- (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)
-#define BIT_GET_R_WMAC_CTX_SUBTYPE(x) \
- (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE)
-
-#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0
-#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf
-#define BIT_R_WMAC_RTX_SUBTYPE(x) \
- (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)
-#define BIT_GET_R_WMAC_RTX_SUBTYPE(x) \
- (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE)
-
-/* 2 REG_BT_COEX_V2 (Offset 0x0762) */
-
-#define BIT_GNT_BT_POLARITY BIT(12)
-#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8)
-
-#define BIT_SHIFT_TIMER 0
-#define BIT_MASK_TIMER 0xff
-#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER)
-#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER)
-
-/* 2 REG_BT_COEX (Offset 0x0764) */
-
-#define BIT_R_GNT_BT_RFC_SW BIT(12)
-#define BIT_R_GNT_BT_RFC_SW_EN BIT(11)
-#define BIT_R_GNT_BT_BB_SW BIT(10)
-#define BIT_R_GNT_BT_BB_SW_EN BIT(9)
-#define BIT_R_BT_CNT_THREN BIT(8)
-
-#define BIT_SHIFT_R_BT_CNT_THR 0
-#define BIT_MASK_R_BT_CNT_THR 0xff
-#define BIT_R_BT_CNT_THR(x) \
- (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR)
-#define BIT_GET_R_BT_CNT_THR(x) \
- (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR)
-
-/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */
-
-#define BIT_WLRX_TER_BY_CTL BIT(43)
-#define BIT_WLRX_TER_BY_AD BIT(42)
-#define BIT_ANT_DIVERSITY_SEL BIT(41)
-#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40)
-#define BIT_WLACT_LOW_GNTWL_EN BIT(34)
-#define BIT_WLACT_HIGH_GNTBT_EN BIT(33)
-
-/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */
-
-#define BIT_NAV_UPPER_V1 BIT(32)
-
-/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */
-
-#define BIT_SHIFT_RXMYRTS_NAV_V1 8
-#define BIT_MASK_RXMYRTS_NAV_V1 0xff
-#define BIT_RXMYRTS_NAV_V1(x) \
- (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1)
-#define BIT_GET_RXMYRTS_NAV_V1(x) \
- (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1)
-
-#define BIT_SHIFT_RTSRST_V1 0
-#define BIT_MASK_RTSRST_V1 0xff
-#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1)
-#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1)
-
-/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */
-
-#define BIT_SHIFT_BT_STAT_DELAY 12
-#define BIT_MASK_BT_STAT_DELAY 0xf
-#define BIT_BT_STAT_DELAY(x) \
- (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY)
-#define BIT_GET_BT_STAT_DELAY(x) \
- (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY)
-
-#define BIT_SHIFT_BT_TRX_INIT_DETECT 8
-#define BIT_MASK_BT_TRX_INIT_DETECT 0xf
-#define BIT_BT_TRX_INIT_DETECT(x) \
- (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT)
-#define BIT_GET_BT_TRX_INIT_DETECT(x) \
- (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT)
-
-#define BIT_SHIFT_BT_PRI_DETECT_TO 4
-#define BIT_MASK_BT_PRI_DETECT_TO 0xf
-#define BIT_BT_PRI_DETECT_TO(x) \
- (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO)
-#define BIT_GET_BT_PRI_DETECT_TO(x) \
- (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO)
-
-#define BIT_R_GRANTALL_WLMASK BIT(3)
-#define BIT_STATIS_BT_EN BIT(2)
-#define BIT_WL_ACT_MASK_ENABLE BIT(1)
-#define BIT_ENHANCED_BT BIT(0)
-
-/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */
-
-#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_STATIS_BT_LO_RX 0xffff
-#define BIT_STATIS_BT_LO_RX(x) \
- (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX)
-#define BIT_GET_STATIS_BT_LO_RX(x) \
- (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX)
-
-#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_STATIS_BT_LO_TX 0xffff
-#define BIT_STATIS_BT_LO_TX(x) \
- (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX)
-#define BIT_GET_STATIS_BT_LO_TX(x) \
- (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX)
-
-/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */
-
-#define BIT_SHIFT_STATIS_BT_HI_RX 16
-#define BIT_MASK_STATIS_BT_HI_RX 0xffff
-#define BIT_STATIS_BT_HI_RX(x) \
- (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX)
-#define BIT_GET_STATIS_BT_HI_RX(x) \
- (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX)
-
-#define BIT_SHIFT_STATIS_BT_HI_TX 0
-#define BIT_MASK_STATIS_BT_HI_TX 0xffff
-#define BIT_STATIS_BT_HI_TX(x) \
- (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX)
-#define BIT_GET_STATIS_BT_HI_TX(x) \
- (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX)
-
-/* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */
-
-#define BIT_SHIFT_R_BT_CMD_RPT 16
-#define BIT_MASK_R_BT_CMD_RPT 0xffff
-#define BIT_R_BT_CMD_RPT(x) \
- (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT)
-#define BIT_GET_R_BT_CMD_RPT(x) \
- (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT)
-
-#define BIT_SHIFT_R_RPT_FROM_BT 8
-#define BIT_MASK_R_RPT_FROM_BT 0xff
-#define BIT_R_RPT_FROM_BT(x) \
- (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT)
-#define BIT_GET_R_RPT_FROM_BT(x) \
- (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT)
-
-#define BIT_SHIFT_BT_HID_ISR_SET 6
-#define BIT_MASK_BT_HID_ISR_SET 0x3
-#define BIT_BT_HID_ISR_SET(x) \
- (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET)
-#define BIT_GET_BT_HID_ISR_SET(x) \
- (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET)
-
-#define BIT_TDMA_BT_START_NOTIFY BIT(5)
-#define BIT_ENABLE_TDMA_FW_MODE BIT(4)
-#define BIT_ENABLE_PTA_TDMA_MODE BIT(3)
-#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2)
-#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1)
-#define BIT_RTK_BT_ENABLE BIT(0)
-
-/* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */
-
-#define BIT_SHIFT_BT_PROFILE 24
-#define BIT_MASK_BT_PROFILE 0xff
-#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE)
-#define BIT_GET_BT_PROFILE(x) \
- (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE)
-
-#define BIT_SHIFT_BT_POWER 16
-#define BIT_MASK_BT_POWER 0xff
-#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER)
-#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER)
-
-#define BIT_SHIFT_BT_PREDECT_STATUS 8
-#define BIT_MASK_BT_PREDECT_STATUS 0xff
-#define BIT_BT_PREDECT_STATUS(x) \
- (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS)
-#define BIT_GET_BT_PREDECT_STATUS(x) \
- (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS)
-
-#define BIT_SHIFT_BT_CMD_INFO 0
-#define BIT_MASK_BT_CMD_INFO 0xff
-#define BIT_BT_CMD_INFO(x) \
- (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO)
-#define BIT_GET_BT_CMD_INFO(x) \
- (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO)
-
-/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */
-
-#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31)
-#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30)
-#define BIT_EN_BT_STSTUS_RPT BIT(29)
-#define BIT_EN_BT_POWER BIT(28)
-#define BIT_EN_BT_CHANNEL BIT(27)
-#define BIT_EN_BT_SLOT_CHANGE BIT(26)
-#define BIT_EN_BT_PROFILE_OR_HID BIT(25)
-#define BIT_WLAN_RPT_NOTIFY BIT(24)
-
-#define BIT_SHIFT_WLAN_RPT_DATA 16
-#define BIT_MASK_WLAN_RPT_DATA 0xff
-#define BIT_WLAN_RPT_DATA(x) \
- (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA)
-#define BIT_GET_WLAN_RPT_DATA(x) \
- (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA)
-
-#define BIT_SHIFT_CMD_ID 8
-#define BIT_MASK_CMD_ID 0xff
-#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID)
-#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID)
-
-#define BIT_SHIFT_BT_DATA 0
-#define BIT_MASK_BT_DATA 0xff
-#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA)
-#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA)
-
-/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */
-
-#define BIT_SHIFT_WLAN_RPT_TO 0
-#define BIT_MASK_WLAN_RPT_TO 0xff
-#define BIT_WLAN_RPT_TO(x) \
- (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO)
-#define BIT_GET_WLAN_RPT_TO(x) \
- (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO)
-
-/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */
-
-#define BIT_SHIFT_ISOLATION_CHK 1
-#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL
-#define BIT_ISOLATION_CHK(x) \
- (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK)
-#define BIT_GET_ISOLATION_CHK(x) \
- (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK)
-
-/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */
-
-#define BIT_ISOLATION_EN BIT(0)
-
-/* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */
-
-#define BIT_BT_HID_ISR BIT(7)
-#define BIT_BT_QUERY_ISR BIT(6)
-#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5)
-#define BIT_WLAN_RPT_ISR BIT(4)
-#define BIT_BT_POWER_ISR BIT(3)
-#define BIT_BT_CHANNEL_ISR BIT(2)
-#define BIT_BT_SLOT_CHANGE_ISR BIT(1)
-#define BIT_BT_PROFILE_ISR BIT(0)
-
-/* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */
-
-#define BIT_SHIFT_BT_TIME 6
-#define BIT_MASK_BT_TIME 0x3ffffff
-#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME)
-#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME)
-
-#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0
-#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f
-#define BIT_BT_RPT_SAMPLE_RATE(x) \
- (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE)
-#define BIT_GET_BT_RPT_SAMPLE_RATE(x) \
- (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE)
-
-/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */
-
-#define BIT_SHIFT_BT_EISR_EN 16
-#define BIT_MASK_BT_EISR_EN 0xff
-#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN)
-#define BIT_GET_BT_EISR_EN(x) \
- (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN)
-
-#define BIT_BT_ACT_FALLING_ISR BIT(10)
-#define BIT_BT_ACT_RISING_ISR BIT(9)
-#define BIT_TDMA_TO_ISR BIT(8)
-
-#define BIT_SHIFT_BT_CH 0
-#define BIT_MASK_BT_CH 0xff
-#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH)
-#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH)
-
-/* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */
-
-#define BIT_OBFF_EN_V1 BIT(31)
-
-#define BIT_SHIFT_OBFF_STATE_V1 28
-#define BIT_MASK_OBFF_STATE_V1 0x3
-#define BIT_OBFF_STATE_V1(x) \
- (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1)
-#define BIT_GET_OBFF_STATE_V1(x) \
- (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1)
-
-#define BIT_OBFF_ACT_RXDMA_EN BIT(27)
-#define BIT_OBFF_BLOCK_INT_EN BIT(26)
-#define BIT_OBFF_AUTOACT_EN BIT(25)
-#define BIT_OBFF_AUTOIDLE_EN BIT(24)
-
-#define BIT_SHIFT_WAKE_MAX_PLS 20
-#define BIT_MASK_WAKE_MAX_PLS 0x7
-#define BIT_WAKE_MAX_PLS(x) \
- (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS)
-#define BIT_GET_WAKE_MAX_PLS(x) \
- (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS)
-
-#define BIT_SHIFT_WAKE_MIN_PLS 16
-#define BIT_MASK_WAKE_MIN_PLS 0x7
-#define BIT_WAKE_MIN_PLS(x) \
- (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS)
-#define BIT_GET_WAKE_MIN_PLS(x) \
- (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS)
-
-#define BIT_SHIFT_WAKE_MAX_F2F 12
-#define BIT_MASK_WAKE_MAX_F2F 0x7
-#define BIT_WAKE_MAX_F2F(x) \
- (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F)
-#define BIT_GET_WAKE_MAX_F2F(x) \
- (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F)
-
-#define BIT_SHIFT_WAKE_MIN_F2F 8
-#define BIT_MASK_WAKE_MIN_F2F 0x7
-#define BIT_WAKE_MIN_F2F(x) \
- (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F)
-#define BIT_GET_WAKE_MIN_F2F(x) \
- (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F)
-
-#define BIT_APP_CPU_ACT_V1 BIT(3)
-#define BIT_APP_OBFF_V1 BIT(2)
-#define BIT_APP_IDLE_V1 BIT(1)
-#define BIT_APP_INIT_V1 BIT(0)
-
-/* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */
-
-#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24
-#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7
-#define BIT_RX_HIGH_TIMER_IDX(x) \
- (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX)
-#define BIT_GET_RX_HIGH_TIMER_IDX(x) \
- (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX)
-
-#define BIT_SHIFT_RX_MED_TIMER_IDX 16
-#define BIT_MASK_RX_MED_TIMER_IDX 0x7
-#define BIT_RX_MED_TIMER_IDX(x) \
- (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX)
-#define BIT_GET_RX_MED_TIMER_IDX(x) \
- (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX)
-
-#define BIT_SHIFT_RX_LOW_TIMER_IDX 8
-#define BIT_MASK_RX_LOW_TIMER_IDX 0x7
-#define BIT_RX_LOW_TIMER_IDX(x) \
- (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX)
-#define BIT_GET_RX_LOW_TIMER_IDX(x) \
- (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX)
-
-#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0
-#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7
-#define BIT_OBFF_INT_TIMER_IDX(x) \
- (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX)
-#define BIT_GET_OBFF_INT_TIMER_IDX(x) \
- (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX)
-
-/* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */
-
-#define BIT_LTR_EN_V1 BIT(31)
-#define BIT_LTR_HW_EN_V1 BIT(30)
-#define BIT_LRT_ACT_CTS_EN BIT(29)
-#define BIT_LTR_ACT_RXPKT_EN BIT(28)
-#define BIT_LTR_ACT_RXDMA_EN BIT(27)
-#define BIT_LTR_IDLE_NO_SNOOP BIT(26)
-#define BIT_SPDUP_MGTPKT BIT(25)
-#define BIT_RX_AGG_EN BIT(24)
-#define BIT_APP_LTR_ACT BIT(23)
-#define BIT_APP_LTR_IDLE BIT(22)
-
-#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20
-#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3
-#define BIT_HIGH_RATE_TRIG_SEL(x) \
- (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL)
-#define BIT_GET_HIGH_RATE_TRIG_SEL(x) \
- (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL)
-
-#define BIT_SHIFT_MED_RATE_TRIG_SEL 18
-#define BIT_MASK_MED_RATE_TRIG_SEL 0x3
-#define BIT_MED_RATE_TRIG_SEL(x) \
- (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL)
-#define BIT_GET_MED_RATE_TRIG_SEL(x) \
- (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL)
-
-#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16
-#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3
-#define BIT_LOW_RATE_TRIG_SEL(x) \
- (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL)
-#define BIT_GET_LOW_RATE_TRIG_SEL(x) \
- (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL)
-
-#define BIT_SHIFT_HIGH_RATE_BD_IDX 8
-#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f
-#define BIT_HIGH_RATE_BD_IDX(x) \
- (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX)
-#define BIT_GET_HIGH_RATE_BD_IDX(x) \
- (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX)
-
-#define BIT_SHIFT_LOW_RATE_BD_IDX 0
-#define BIT_MASK_LOW_RATE_BD_IDX 0x7f
-#define BIT_LOW_RATE_BD_IDX(x) \
- (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX)
-#define BIT_GET_LOW_RATE_BD_IDX(x) \
- (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX)
-
-/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */
-
-#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24
-#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7
-#define BIT_RX_EMPTY_TIMER_IDX(x) \
- (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX)
-#define BIT_GET_RX_EMPTY_TIMER_IDX(x) \
- (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX)
-
-#define BIT_SHIFT_RX_AFULL_TH_IDX 20
-#define BIT_MASK_RX_AFULL_TH_IDX 0x7
-#define BIT_RX_AFULL_TH_IDX(x) \
- (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX)
-#define BIT_GET_RX_AFULL_TH_IDX(x) \
- (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX)
-
-#define BIT_SHIFT_RX_HIGH_TH_IDX 16
-#define BIT_MASK_RX_HIGH_TH_IDX 0x7
-#define BIT_RX_HIGH_TH_IDX(x) \
- (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX)
-#define BIT_GET_RX_HIGH_TH_IDX(x) \
- (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX)
-
-#define BIT_SHIFT_RX_MED_TH_IDX 12
-#define BIT_MASK_RX_MED_TH_IDX 0x7
-#define BIT_RX_MED_TH_IDX(x) \
- (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX)
-#define BIT_GET_RX_MED_TH_IDX(x) \
- (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX)
-
-#define BIT_SHIFT_RX_LOW_TH_IDX 8
-#define BIT_MASK_RX_LOW_TH_IDX 0x7
-#define BIT_RX_LOW_TH_IDX(x) \
- (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX)
-#define BIT_GET_RX_LOW_TH_IDX(x) \
- (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX)
-
-#define BIT_SHIFT_LTR_SPACE_IDX 4
-#define BIT_MASK_LTR_SPACE_IDX 0x3
-#define BIT_LTR_SPACE_IDX(x) \
- (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX)
-#define BIT_GET_LTR_SPACE_IDX(x) \
- (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX)
-
-#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0
-#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7
-#define BIT_LTR_IDLE_TIMER_IDX(x) \
- (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX)
-#define BIT_GET_LTR_IDLE_TIMER_IDX(x) \
- (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX)
-
-/* 2 REG_LTR_IDLE_LATENCY_V1 (Offset 0x07A8) */
-
-#define BIT_SHIFT_LTR_IDLE_L 0
-#define BIT_MASK_LTR_IDLE_L 0xffffffffL
-#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L)
-#define BIT_GET_LTR_IDLE_L(x) \
- (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L)
-
-/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */
-
-#define BIT_SHIFT_LTR_ACT_L 0
-#define BIT_MASK_LTR_ACT_L 0xffffffffL
-#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L)
-#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L)
-
-/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */
-
-#define BIT_APPEND_MACID_IN_RESP_EN BIT(50)
-#define BIT_ADDR2_MATCH_EN BIT(49)
-#define BIT_ANTTRN_EN BIT(48)
-
-#define BIT_SHIFT_TRAIN_STA_ADDR 0
-#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL
-#define BIT_TRAIN_STA_ADDR(x) \
- (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR)
-#define BIT_GET_TRAIN_STA_ADDR(x) \
- (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR)
-
-/* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */
-
-#define BIT_SHIFT_PKTCNT_BSSIDMAP 4
-#define BIT_MASK_PKTCNT_BSSIDMAP 0xf
-#define BIT_PKTCNT_BSSIDMAP(x) \
- (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP)
-#define BIT_GET_PKTCNT_BSSIDMAP(x) \
- (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP)
-
-#define BIT_PKTCNT_CNTRST BIT(1)
-#define BIT_PKTCNT_CNTEN BIT(0)
-
-/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */
-
-#define BIT_WMAC_PKTCNT_TRST BIT(9)
-#define BIT_WMAC_PKTCNT_FEN BIT(8)
-
-#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0
-#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff
-#define BIT_WMAC_PKTCNT_CFGAD(x) \
- (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD)
-#define BIT_GET_WMAC_PKTCNT_CFGAD(x) \
- (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD)
-
-/* 2 REG_IQ_DUMP (Offset 0x07C0) */
-
-#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL
-#define BIT_R_WMAC_MATCH_REF_MAC(x) \
- (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) \
- << BIT_SHIFT_R_WMAC_MATCH_REF_MAC)
-#define BIT_GET_R_WMAC_MATCH_REF_MAC(x) \
- (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & \
- BIT_MASK_R_WMAC_MATCH_REF_MAC)
-
-#define BIT_SHIFT_R_WMAC_RX_FIL_LEN (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_RX_FIL_LEN 0xffff
-#define BIT_R_WMAC_RX_FIL_LEN(x) \
- (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN) << BIT_SHIFT_R_WMAC_RX_FIL_LEN)
-#define BIT_GET_R_WMAC_RX_FIL_LEN(x) \
- (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN) & BIT_MASK_R_WMAC_RX_FIL_LEN)
-
-#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff
-#define BIT_R_WMAC_RXFIFO_FULL_TH(x) \
- (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) \
- << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH)
-#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) \
- (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & \
- BIT_MASK_R_WMAC_RXFIFO_FULL_TH)
-
-#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51)
-#define BIT_R_WMAC_NDP_RST BIT(50)
-#define BIT_R_WMAC_POWINT_EN BIT(49)
-#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48)
-#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47)
-#define BIT_R_WMAC_PFIN_TOEN BIT(46)
-#define BIT_R_WMAC_FIL_SECERR BIT(45)
-#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44)
-#define BIT_R_WMAC_FIL_FCTYPE BIT(43)
-#define BIT_R_WMAC_FIL_FCPROVER BIT(42)
-#define BIT_R_WMAC_PHYSTS_SNIF BIT(41)
-#define BIT_R_WMAC_PHYSTS_PLCP BIT(40)
-#define BIT_R_MAC_TCR_VBONF_RD BIT(39)
-#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38)
-#define BIT_R_WMAC_NDP_FILTER BIT(37)
-#define BIT_R_WMAC_RXLEN_SEL BIT(36)
-#define BIT_R_WMAC_RXLEN_SEL1 BIT(35)
-#define BIT_R_OFDM_FILTER BIT(34)
-#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33)
-
-#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL
-#define BIT_R_WMAC_MASK_LA_MAC(x) \
- (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC)
-#define BIT_GET_R_WMAC_MASK_LA_MAC(x) \
- (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC)
-
-#define BIT_R_WMAC_CHK_CCK_LEN BIT(32)
-
-/* 2 REG_IQ_DUMP (Offset 0x07C0) */
-
-#define BIT_SHIFT_R_OFDM_LEN 26
-#define BIT_MASK_R_OFDM_LEN 0x3f
-#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN)
-#define BIT_GET_R_OFDM_LEN(x) \
- (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN)
-
-#define BIT_SHIFT_DUMP_OK_ADDR 15
-#define BIT_MASK_DUMP_OK_ADDR 0x1ffff
-#define BIT_DUMP_OK_ADDR(x) \
- (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR)
-#define BIT_GET_DUMP_OK_ADDR(x) \
- (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR)
-
-#define BIT_SHIFT_R_TRIG_TIME_SEL 8
-#define BIT_MASK_R_TRIG_TIME_SEL 0x7f
-#define BIT_R_TRIG_TIME_SEL(x) \
- (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL)
-#define BIT_GET_R_TRIG_TIME_SEL(x) \
- (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL)
-
-#define BIT_SHIFT_R_MAC_TRIG_SEL 6
-#define BIT_MASK_R_MAC_TRIG_SEL 0x3
-#define BIT_R_MAC_TRIG_SEL(x) \
- (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL)
-#define BIT_GET_R_MAC_TRIG_SEL(x) \
- (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL)
-
-#define BIT_MAC_TRIG_REG BIT(5)
-
-#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3
-#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3
-#define BIT_R_LEVEL_PULSE_SEL(x) \
- (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL)
-#define BIT_GET_R_LEVEL_PULSE_SEL(x) \
- (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL)
-
-#define BIT_EN_LA_MAC BIT(2)
-#define BIT_R_EN_IQDUMP BIT(1)
-#define BIT_R_IQDATA_DUMP BIT(0)
-
-#define BIT_SHIFT_R_CCK_LEN 0
-#define BIT_MASK_R_CCK_LEN 0xffff
-#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN)
-#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN)
-
-/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */
-
-#define BIT_RXFTM_TXACK_SC BIT(6)
-#define BIT_RXFTM_TXACK_BW BIT(5)
-#define BIT_RXFTM_EN BIT(3)
-#define BIT_RXFTMREQ_BYDRV BIT(2)
-#define BIT_RXFTMREQ_EN BIT(1)
-#define BIT_FTM_EN BIT(0)
-
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-
-#define BIT_R_WMAC_MHRDDY_LATCH BIT(14)
-
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-
-#define BIT_R_WMAC_MHRDDY_CLR BIT(13)
-
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-
-#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12)
-
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-
-#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11)
-
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-
-#define BIT_R_CHK_DELIMIT_LEN BIT(10)
-#define BIT_R_REAPTER_ADDR_MATCH BIT(9)
-#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8)
-#define BIT_R_LATCH_MACHRDY BIT(7)
-#define BIT_R_WMAC_RXFIL_REND BIT(6)
-#define BIT_R_WMAC_MPDURDY_CLR BIT(5)
-#define BIT_R_WMAC_CLRRXSEC BIT(4)
-#define BIT_R_WMAC_RXFIL_RDEL BIT(3)
-#define BIT_R_WMAC_RXFIL_FCSE BIT(2)
-#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1)
-#define BIT_R_WMAC_RXFIL_MASKM BIT(0)
-
-/* 2 REG_NDP_SIG (Offset 0x07E0) */
-
-#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0
-#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff
-#define BIT_R_WMAC_TXNDP_SIGB(x) \
- (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB)
-#define BIT_GET_R_WMAC_TXNDP_SIGB(x) \
- (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB)
-
-/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */
-
-#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_MAC_DEBUG 0xffffffffL
-#define BIT_R_MAC_DEBUG(x) \
- (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG)
-#define BIT_GET_R_MAC_DEBUG(x) \
- (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG)
-
-/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */
-
-#define BIT_SHIFT_R_MAC_DBG_SHIFT 8
-#define BIT_MASK_R_MAC_DBG_SHIFT 0x7
-#define BIT_R_MAC_DBG_SHIFT(x) \
- (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT)
-#define BIT_GET_R_MAC_DBG_SHIFT(x) \
- (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT)
-
-#define BIT_SHIFT_R_MAC_DBG_SEL 0
-#define BIT_MASK_R_MAC_DBG_SEL 0x3
-#define BIT_R_MAC_DBG_SEL(x) \
- (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL)
-#define BIT_GET_R_MAC_DBG_SEL(x) \
- (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL)
-
-/* 2 REG_SYS_CFG3 (Offset 0x1000) */
-
-#define BIT_PWC_MA33V BIT(15)
-
-/* 2 REG_SYS_CFG3 (Offset 0x1000) */
-
-#define BIT_PWC_MA12V BIT(14)
-#define BIT_PWC_MD12V BIT(13)
-#define BIT_PWC_PD12V BIT(12)
-#define BIT_PWC_UD12V BIT(11)
-#define BIT_ISO_MA2MD BIT(1)
-
-/* 2 REG_SYS_CFG5 (Offset 0x1070) */
-
-#define BIT_LPS_STATUS BIT(3)
-#define BIT_HCI_TXDMA_BUSY BIT(2)
-#define BIT_HCI_TXDMA_ALLOW BIT(1)
-#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0)
-
-/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
-
-#define BIT_WDT_OPT_IOWRAPPER BIT(19)
-
-/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
-
-#define BIT_ANA_PORT_IDLE BIT(18)
-#define BIT_MAC_PORT_IDLE BIT(17)
-#define BIT_WL_PLATFORM_RST BIT(16)
-#define BIT_WL_SECURITY_CLK BIT(15)
-
-/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
-
-#define BIT_SHIFT_CPU_DMEM_CON 0
-#define BIT_MASK_CPU_DMEM_CON 0xff
-#define BIT_CPU_DMEM_CON(x) \
- (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON)
-#define BIT_GET_CPU_DMEM_CON(x) \
- (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON)
-
-/* 2 REG_BOOT_REASON (Offset 0x1088) */
-
-#define BIT_SHIFT_BOOT_REASON 0
-#define BIT_MASK_BOOT_REASON 0x7
-#define BIT_BOOT_REASON(x) \
- (((x) & BIT_MASK_BOOT_REASON) << BIT_SHIFT_BOOT_REASON)
-#define BIT_GET_BOOT_REASON(x) \
- (((x) >> BIT_SHIFT_BOOT_REASON) & BIT_MASK_BOOT_REASON)
-
-/* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */
-
-#define BIT_PAD_SHUTDW BIT(18)
-#define BIT_SYSON_NFC_PAD BIT(17)
-#define BIT_NFC_INT_PAD_CTRL BIT(16)
-#define BIT_NFC_RFDIS_PAD_CTRL BIT(15)
-#define BIT_NFC_CLK_PAD_CTRL BIT(14)
-#define BIT_NFC_DATA_PAD_CTRL BIT(13)
-#define BIT_NFC_PAD_PULL_CTRL BIT(12)
-
-#define BIT_SHIFT_NFCPAD_IO_SEL 8
-#define BIT_MASK_NFCPAD_IO_SEL 0xf
-#define BIT_NFCPAD_IO_SEL(x) \
- (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL)
-#define BIT_GET_NFCPAD_IO_SEL(x) \
- (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL)
-
-#define BIT_SHIFT_NFCPAD_OUT 4
-#define BIT_MASK_NFCPAD_OUT 0xf
-#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT)
-#define BIT_GET_NFCPAD_OUT(x) \
- (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT)
-
-#define BIT_SHIFT_NFCPAD_IN 0
-#define BIT_MASK_NFCPAD_IN 0xf
-#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN)
-#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN)
-
-/* 2 REG_HIMR2 (Offset 0x10B0) */
-
-#define BIT_BCNDMAINT_P4_MSK BIT(31)
-#define BIT_BCNDMAINT_P3_MSK BIT(30)
-#define BIT_BCNDMAINT_P2_MSK BIT(29)
-#define BIT_BCNDMAINT_P1_MSK BIT(28)
-#define BIT_ATIMEND7_MSK BIT(22)
-#define BIT_ATIMEND6_MSK BIT(21)
-#define BIT_ATIMEND5_MSK BIT(20)
-#define BIT_ATIMEND4_MSK BIT(19)
-#define BIT_ATIMEND3_MSK BIT(18)
-#define BIT_ATIMEND2_MSK BIT(17)
-#define BIT_ATIMEND1_MSK BIT(16)
-#define BIT_TXBCN7OK_MSK BIT(14)
-#define BIT_TXBCN6OK_MSK BIT(13)
-#define BIT_TXBCN5OK_MSK BIT(12)
-#define BIT_TXBCN4OK_MSK BIT(11)
-#define BIT_TXBCN3OK_MSK BIT(10)
-#define BIT_TXBCN2OK_MSK BIT(9)
-#define BIT_TXBCN1OK_MSK_V1 BIT(8)
-#define BIT_TXBCN7ERR_MSK BIT(6)
-#define BIT_TXBCN6ERR_MSK BIT(5)
-#define BIT_TXBCN5ERR_MSK BIT(4)
-#define BIT_TXBCN4ERR_MSK BIT(3)
-#define BIT_TXBCN3ERR_MSK BIT(2)
-#define BIT_TXBCN2ERR_MSK BIT(1)
-#define BIT_TXBCN1ERR_MSK_V1 BIT(0)
-
-/* 2 REG_HISR2 (Offset 0x10B4) */
-
-#define BIT_BCNDMAINT_P4 BIT(31)
-#define BIT_BCNDMAINT_P3 BIT(30)
-#define BIT_BCNDMAINT_P2 BIT(29)
-#define BIT_BCNDMAINT_P1 BIT(28)
-#define BIT_ATIMEND7 BIT(22)
-#define BIT_ATIMEND6 BIT(21)
-#define BIT_ATIMEND5 BIT(20)
-#define BIT_ATIMEND4 BIT(19)
-#define BIT_ATIMEND3 BIT(18)
-#define BIT_ATIMEND2 BIT(17)
-#define BIT_ATIMEND1 BIT(16)
-#define BIT_TXBCN7OK BIT(14)
-#define BIT_TXBCN6OK BIT(13)
-#define BIT_TXBCN5OK BIT(12)
-#define BIT_TXBCN4OK BIT(11)
-#define BIT_TXBCN3OK BIT(10)
-#define BIT_TXBCN2OK BIT(9)
-#define BIT_TXBCN1OK BIT(8)
-#define BIT_TXBCN7ERR BIT(6)
-#define BIT_TXBCN6ERR BIT(5)
-#define BIT_TXBCN5ERR BIT(4)
-#define BIT_TXBCN4ERR BIT(3)
-#define BIT_TXBCN3ERR BIT(2)
-#define BIT_TXBCN2ERR BIT(1)
-#define BIT_TXBCN1ERR BIT(0)
-
-/* 2 REG_HIMR3 (Offset 0x10B8) */
-
-#define BIT_WDT_PLATFORM_INT_MSK BIT(18)
-#define BIT_WDT_CPU_INT_MSK BIT(17)
-
-/* 2 REG_HIMR3 (Offset 0x10B8) */
-
-#define BIT_SETH2CDOK_MASK BIT(16)
-#define BIT_H2C_CMD_FULL_MASK BIT(15)
-#define BIT_PWR_INT_127_MASK BIT(14)
-#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13)
-#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12)
-#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11)
-#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10)
-#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9)
-#define BIT_PWR_INT_127_MASK_V1 BIT(8)
-#define BIT_PWR_INT_126TO96_MASK BIT(7)
-#define BIT_PWR_INT_95TO64_MASK BIT(6)
-#define BIT_PWR_INT_63TO32_MASK BIT(5)
-#define BIT_PWR_INT_31TO0_MASK BIT(4)
-#define BIT_DDMA0_LP_INT_MSK BIT(1)
-#define BIT_DDMA0_HP_INT_MSK BIT(0)
-
-/* 2 REG_HISR3 (Offset 0x10BC) */
-
-#define BIT_WDT_PLATFORM_INT BIT(18)
-#define BIT_WDT_CPU_INT BIT(17)
-
-/* 2 REG_HISR3 (Offset 0x10BC) */
-
-#define BIT_SETH2CDOK BIT(16)
-#define BIT_H2C_CMD_FULL BIT(15)
-#define BIT_PWR_INT_127 BIT(14)
-#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13)
-#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12)
-#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11)
-#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10)
-#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9)
-#define BIT_PWR_INT_127_V1 BIT(8)
-#define BIT_PWR_INT_126TO96 BIT(7)
-#define BIT_PWR_INT_95TO64 BIT(6)
-#define BIT_PWR_INT_63TO32 BIT(5)
-#define BIT_PWR_INT_31TO0 BIT(4)
-#define BIT_DDMA0_LP_INT BIT(1)
-#define BIT_DDMA0_HP_INT BIT(0)
-
-/* 2 REG_SW_MDIO (Offset 0x10C0) */
-
-#define BIT_DIS_TIMEOUT_IO BIT(24)
-
-/* 2 REG_SW_FLUSH (Offset 0x10C4) */
-
-#define BIT_FLUSH_HOLDN_EN BIT(25)
-#define BIT_FLUSH_WR_EN BIT(24)
-#define BIT_SW_FLASH_CONTROL BIT(23)
-#define BIT_SW_FLASH_WEN_E BIT(19)
-#define BIT_SW_FLASH_HOLDN_E BIT(18)
-#define BIT_SW_FLASH_SO_E BIT(17)
-#define BIT_SW_FLASH_SI_E BIT(16)
-#define BIT_SW_FLASH_SK_O BIT(13)
-#define BIT_SW_FLASH_CEN_O BIT(12)
-#define BIT_SW_FLASH_WEN_O BIT(11)
-#define BIT_SW_FLASH_HOLDN_O BIT(10)
-#define BIT_SW_FLASH_SO_O BIT(9)
-#define BIT_SW_FLASH_SI_O BIT(8)
-#define BIT_SW_FLASH_WEN_I BIT(3)
-#define BIT_SW_FLASH_HOLDN_I BIT(2)
-#define BIT_SW_FLASH_SO_I BIT(1)
-#define BIT_SW_FLASH_SI_I BIT(0)
-
-/* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */
-
-#define BIT_SHIFT_H2C_PKT_READADDR 0
-#define BIT_MASK_H2C_PKT_READADDR 0x3ffff
-#define BIT_H2C_PKT_READADDR(x) \
- (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR)
-#define BIT_GET_H2C_PKT_READADDR(x) \
- (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR)
-
-/* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */
-
-#define BIT_SHIFT_H2C_PKT_WRITEADDR 0
-#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff
-#define BIT_H2C_PKT_WRITEADDR(x) \
- (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR)
-#define BIT_GET_H2C_PKT_WRITEADDR(x) \
- (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR)
-
-/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */
-
-#define BIT_MEM_BB_SD BIT(17)
-#define BIT_MEM_BB_DS BIT(16)
-#define BIT_MEM_BT_DS BIT(10)
-#define BIT_MEM_SDIO_LS BIT(9)
-#define BIT_MEM_SDIO_DS BIT(8)
-#define BIT_MEM_USB_LS BIT(7)
-#define BIT_MEM_USB_DS BIT(6)
-#define BIT_MEM_PCI_LS BIT(5)
-#define BIT_MEM_PCI_DS BIT(4)
-#define BIT_MEM_WLMAC_LS BIT(3)
-#define BIT_MEM_WLMAC_DS BIT(2)
-#define BIT_MEM_WLMCU_LS BIT(1)
-
-/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */
-
-#define BIT_MEM_WLMCU_DS BIT(0)
-
-/* 2 REG_FW_DBG0 (Offset 0x10E0) */
-
-#define BIT_SHIFT_FW_DBG0 0
-#define BIT_MASK_FW_DBG0 0xffffffffL
-#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0)
-#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0)
-
-/* 2 REG_FW_DBG1 (Offset 0x10E4) */
-
-#define BIT_SHIFT_FW_DBG1 0
-#define BIT_MASK_FW_DBG1 0xffffffffL
-#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1)
-#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1)
-
-/* 2 REG_FW_DBG2 (Offset 0x10E8) */
-
-#define BIT_SHIFT_FW_DBG2 0
-#define BIT_MASK_FW_DBG2 0xffffffffL
-#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2)
-#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2)
-
-/* 2 REG_FW_DBG3 (Offset 0x10EC) */
-
-#define BIT_SHIFT_FW_DBG3 0
-#define BIT_MASK_FW_DBG3 0xffffffffL
-#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3)
-#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3)
-
-/* 2 REG_FW_DBG4 (Offset 0x10F0) */
-
-#define BIT_SHIFT_FW_DBG4 0
-#define BIT_MASK_FW_DBG4 0xffffffffL
-#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4)
-#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4)
-
-/* 2 REG_FW_DBG5 (Offset 0x10F4) */
-
-#define BIT_SHIFT_FW_DBG5 0
-#define BIT_MASK_FW_DBG5 0xffffffffL
-#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5)
-#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5)
-
-/* 2 REG_FW_DBG6 (Offset 0x10F8) */
-
-#define BIT_SHIFT_FW_DBG6 0
-#define BIT_MASK_FW_DBG6 0xffffffffL
-#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6)
-#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6)
-
-/* 2 REG_FW_DBG7 (Offset 0x10FC) */
-
-#define BIT_SHIFT_FW_DBG7 0
-#define BIT_MASK_FW_DBG7 0xffffffffL
-#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7)
-#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7)
-
-/* 2 REG_CR_EXT (Offset 0x1100) */
-
-#define BIT_SHIFT_PHY_REQ_DELAY 24
-#define BIT_MASK_PHY_REQ_DELAY 0xf
-#define BIT_PHY_REQ_DELAY(x) \
- (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY)
-#define BIT_GET_PHY_REQ_DELAY(x) \
- (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY)
-
-#define BIT_SPD_DOWN BIT(16)
-
-#define BIT_SHIFT_NETYPE4 4
-#define BIT_MASK_NETYPE4 0x3
-#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4)
-#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4)
-
-#define BIT_SHIFT_NETYPE3 2
-#define BIT_MASK_NETYPE3 0x3
-#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3)
-#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3)
-
-#define BIT_SHIFT_NETYPE2 0
-#define BIT_MASK_NETYPE2 0x3
-#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2)
-#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2)
-
-/* 2 REG_FWFF (Offset 0x1114) */
-
-#define BIT_SHIFT_PKTNUM_TH_V1 24
-#define BIT_MASK_PKTNUM_TH_V1 0xff
-#define BIT_PKTNUM_TH_V1(x) \
- (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1)
-#define BIT_GET_PKTNUM_TH_V1(x) \
- (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1)
-
-/* 2 REG_FWFF (Offset 0x1114) */
-
-#define BIT_SHIFT_TIMER_TH 16
-#define BIT_MASK_TIMER_TH 0xff
-#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH)
-#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH)
-
-/* 2 REG_FWFF (Offset 0x1114) */
-
-#define BIT_SHIFT_RXPKT1ENADDR 0
-#define BIT_MASK_RXPKT1ENADDR 0xffff
-#define BIT_RXPKT1ENADDR(x) \
- (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR)
-#define BIT_GET_RXPKT1ENADDR(x) \
- (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR)
-
-/* 2 REG_FE2IMR (Offset 0x1120) */
-
-#define BIT__FE4ISR__IND_MSK BIT(29)
-
-/* 2 REG_FE2IMR (Offset 0x1120) */
-
-#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28)
-#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27)
-#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26)
-#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25)
-#define BIT_FS_TXSC_VODONE_INT_EN BIT(24)
-
-/* 2 REG_FE2IMR (Offset 0x1120) */
-
-#define BIT_FS_ATIM_MB7_INT_EN BIT(23)
-#define BIT_FS_ATIM_MB6_INT_EN BIT(22)
-#define BIT_FS_ATIM_MB5_INT_EN BIT(21)
-#define BIT_FS_ATIM_MB4_INT_EN BIT(20)
-#define BIT_FS_ATIM_MB3_INT_EN BIT(19)
-#define BIT_FS_ATIM_MB2_INT_EN BIT(18)
-#define BIT_FS_ATIM_MB1_INT_EN BIT(17)
-#define BIT_FS_ATIM_MB0_INT_EN BIT(16)
-#define BIT_FS_TBTT4INT_EN BIT(11)
-#define BIT_FS_TBTT3INT_EN BIT(10)
-#define BIT_FS_TBTT2INT_EN BIT(9)
-#define BIT_FS_TBTT1INT_EN BIT(8)
-#define BIT_FS_TBTT0_MB7INT_EN BIT(7)
-#define BIT_FS_TBTT0_MB6INT_EN BIT(6)
-#define BIT_FS_TBTT0_MB5INT_EN BIT(5)
-#define BIT_FS_TBTT0_MB4INT_EN BIT(4)
-#define BIT_FS_TBTT0_MB3INT_EN BIT(3)
-#define BIT_FS_TBTT0_MB2INT_EN BIT(2)
-#define BIT_FS_TBTT0_MB1INT_EN BIT(1)
-#define BIT_FS_TBTT0_INT_EN BIT(0)
-
-/* 2 REG_FE2ISR (Offset 0x1124) */
-
-#define BIT__FE4ISR__IND_INT BIT(29)
-
-/* 2 REG_FE2ISR (Offset 0x1124) */
-
-#define BIT_FS_TXSC_DESC_DONE_INT BIT(28)
-#define BIT_FS_TXSC_BKDONE_INT BIT(27)
-#define BIT_FS_TXSC_BEDONE_INT BIT(26)
-#define BIT_FS_TXSC_VIDONE_INT BIT(25)
-#define BIT_FS_TXSC_VODONE_INT BIT(24)
-
-/* 2 REG_FE2ISR (Offset 0x1124) */
-
-#define BIT_FS_ATIM_MB7_INT BIT(23)
-#define BIT_FS_ATIM_MB6_INT BIT(22)
-#define BIT_FS_ATIM_MB5_INT BIT(21)
-#define BIT_FS_ATIM_MB4_INT BIT(20)
-#define BIT_FS_ATIM_MB3_INT BIT(19)
-#define BIT_FS_ATIM_MB2_INT BIT(18)
-#define BIT_FS_ATIM_MB1_INT BIT(17)
-#define BIT_FS_ATIM_MB0_INT BIT(16)
-#define BIT_FS_TBTT4INT BIT(11)
-#define BIT_FS_TBTT3INT BIT(10)
-#define BIT_FS_TBTT2INT BIT(9)
-#define BIT_FS_TBTT1INT BIT(8)
-#define BIT_FS_TBTT0_MB7INT BIT(7)
-#define BIT_FS_TBTT0_MB6INT BIT(6)
-#define BIT_FS_TBTT0_MB5INT BIT(5)
-#define BIT_FS_TBTT0_MB4INT BIT(4)
-#define BIT_FS_TBTT0_MB3INT BIT(3)
-#define BIT_FS_TBTT0_MB2INT BIT(2)
-#define BIT_FS_TBTT0_MB1INT BIT(1)
-#define BIT_FS_TBTT0_INT BIT(0)
-
-/* 2 REG_FE3IMR (Offset 0x1128) */
-
-#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31)
-
-/* 2 REG_FE3IMR (Offset 0x1128) */
-
-#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30)
-
-/* 2 REG_FE3IMR (Offset 0x1128) */
-
-#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29)
-
-/* 2 REG_FE3IMR (Offset 0x1128) */
-
-#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28)
-
-/* 2 REG_FE3IMR (Offset 0x1128) */
-
-#define BIT_FS_BCNDMA4_INT_EN BIT(27)
-#define BIT_FS_BCNDMA3_INT_EN BIT(26)
-#define BIT_FS_BCNDMA2_INT_EN BIT(25)
-#define BIT_FS_BCNDMA1_INT_EN BIT(24)
-#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23)
-#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22)
-#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21)
-#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20)
-#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19)
-#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18)
-#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17)
-#define BIT_FS_BCNDMA0_INT_EN BIT(16)
-#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15)
-#define BIT_FS_BCNERLY4_INT_EN BIT(11)
-#define BIT_FS_BCNERLY3_INT_EN BIT(10)
-#define BIT_FS_BCNERLY2_INT_EN BIT(9)
-#define BIT_FS_BCNERLY1_INT_EN BIT(8)
-#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7)
-#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6)
-#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5)
-#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4)
-#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3)
-#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2)
-#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1)
-#define BIT_FS_BCNERLY0_INT_EN BIT(0)
-
-/* 2 REG_FE3ISR (Offset 0x112C) */
-
-#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31)
-
-/* 2 REG_FE3ISR (Offset 0x112C) */
-
-#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30)
-
-/* 2 REG_FE3ISR (Offset 0x112C) */
-
-#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29)
-
-/* 2 REG_FE3ISR (Offset 0x112C) */
-
-#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28)
-
-/* 2 REG_FE3ISR (Offset 0x112C) */
-
-#define BIT_FS_BCNDMA4_INT BIT(27)
-#define BIT_FS_BCNDMA3_INT BIT(26)
-#define BIT_FS_BCNDMA2_INT BIT(25)
-#define BIT_FS_BCNDMA1_INT BIT(24)
-#define BIT_FS_BCNDMA0_MB7_INT BIT(23)
-#define BIT_FS_BCNDMA0_MB6_INT BIT(22)
-#define BIT_FS_BCNDMA0_MB5_INT BIT(21)
-#define BIT_FS_BCNDMA0_MB4_INT BIT(20)
-#define BIT_FS_BCNDMA0_MB3_INT BIT(19)
-#define BIT_FS_BCNDMA0_MB2_INT BIT(18)
-#define BIT_FS_BCNDMA0_MB1_INT BIT(17)
-#define BIT_FS_BCNDMA0_INT BIT(16)
-#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15)
-#define BIT_FS_BCNERLY4_INT BIT(11)
-#define BIT_FS_BCNERLY3_INT BIT(10)
-#define BIT_FS_BCNERLY2_INT BIT(9)
-#define BIT_FS_BCNERLY1_INT BIT(8)
-#define BIT_FS_BCNERLY0_MB7INT BIT(7)
-#define BIT_FS_BCNERLY0_MB6INT BIT(6)
-#define BIT_FS_BCNERLY0_MB5INT BIT(5)
-#define BIT_FS_BCNERLY0_MB4INT BIT(4)
-#define BIT_FS_BCNERLY0_MB3INT BIT(3)
-#define BIT_FS_BCNERLY0_MB2INT BIT(2)
-#define BIT_FS_BCNERLY0_MB1INT BIT(1)
-#define BIT_FS_BCNERLY0_INT BIT(0)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1)
-
-/* 2 REG_FE4IMR (Offset 0x1130) */
-
-#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI3_TXPKTIN_INT BIT(19)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI2_TXPKTIN_INT BIT(18)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI1_TXPKTIN_INT BIT(17)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI0_TXPKTIN_INT BIT(16)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI3_RX_UMD0_INT BIT(15)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI3_RX_UMD1_INT BIT(14)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI3_RX_BMD0_INT BIT(13)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI3_RX_BMD1_INT BIT(12)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI2_RX_UMD0_INT BIT(11)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI2_RX_UMD1_INT BIT(10)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI2_RX_BMD0_INT BIT(9)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI2_RX_BMD1_INT BIT(8)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI1_RX_UMD0_INT BIT(7)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI1_RX_UMD1_INT BIT(6)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI1_RX_BMD0_INT BIT(5)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI1_RX_BMD1_INT BIT(4)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI0_RX_UMD0_INT BIT(3)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI0_RX_UMD1_INT BIT(2)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI0_RX_BMD0_INT BIT(1)
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
-
-#define BIT_FS_CLI0_RX_BMD1_INT BIT(0)
-
-/* 2 REG_FT1IMR (Offset 0x1138) */
-
-#define BIT__FT2ISR__IND_MSK BIT(30)
-#define BIT_FTM_PTT_INT_EN BIT(29)
-#define BIT_RXFTMREQ_INT_EN BIT(28)
-#define BIT_RXFTM_INT_EN BIT(27)
-#define BIT_TXFTM_INT_EN BIT(26)
-
-/* 2 REG_FT1IMR (Offset 0x1138) */
-
-#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25)
-#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24)
-
-/* 2 REG_FT1IMR (Offset 0x1138) */
-
-#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23)
-#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22)
-#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21)
-#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20)
-#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19)
-#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18)
-#define BIT_FS_CTWEND2_INT_EN BIT(17)
-#define BIT_FS_CTWEND1_INT_EN BIT(16)
-#define BIT_FS_CTWEND0_INT_EN BIT(15)
-#define BIT_FS_TX_NULL1_INT_EN BIT(14)
-#define BIT_FS_TX_NULL0_INT_EN BIT(13)
-#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12)
-#define BIT_FS_P2P_RFON2_INT_EN BIT(11)
-#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10)
-#define BIT_FS_P2P_RFON1_INT_EN BIT(9)
-#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8)
-#define BIT_FS_P2P_RFON0_INT_EN BIT(7)
-#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6)
-#define BIT_FS_RX_UAPSDMD1_EN BIT(5)
-#define BIT_FS_RX_UAPSDMD0_EN BIT(4)
-#define BIT_FS_TRIGGER_PKT_EN BIT(3)
-#define BIT_FS_EOSP_INT_EN BIT(2)
-#define BIT_FS_RPWM2_INT_EN BIT(1)
-#define BIT_FS_RPWM_INT_EN BIT(0)
-
-/* 2 REG_FT1ISR (Offset 0x113C) */
-
-#define BIT__FT2ISR__IND_INT BIT(30)
-#define BIT_FTM_PTT_INT BIT(29)
-#define BIT_RXFTMREQ_INT BIT(28)
-#define BIT_RXFTM_INT BIT(27)
-#define BIT_TXFTM_INT BIT(26)
-
-/* 2 REG_FT1ISR (Offset 0x113C) */
-
-#define BIT_FS_H2C_CMD_OK_INT BIT(25)
-#define BIT_FS_H2C_CMD_FULL_INT BIT(24)
-
-/* 2 REG_FT1ISR (Offset 0x113C) */
-
-#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23)
-#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22)
-#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21)
-#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20)
-#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19)
-#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18)
-#define BIT_FS_CTWEND2_INT BIT(17)
-#define BIT_FS_CTWEND1_INT BIT(16)
-#define BIT_FS_CTWEND0_INT BIT(15)
-#define BIT_FS_TX_NULL1_INT BIT(14)
-#define BIT_FS_TX_NULL0_INT BIT(13)
-#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12)
-#define BIT_FS_P2P_RFON2_INT BIT(11)
-#define BIT_FS_P2P_RFOFF2_INT BIT(10)
-#define BIT_FS_P2P_RFON1_INT BIT(9)
-#define BIT_FS_P2P_RFOFF1_INT BIT(8)
-#define BIT_FS_P2P_RFON0_INT BIT(7)
-#define BIT_FS_P2P_RFOFF0_INT BIT(6)
-#define BIT_FS_RX_UAPSDMD1_INT BIT(5)
-#define BIT_FS_RX_UAPSDMD0_INT BIT(4)
-#define BIT_FS_TRIGGER_PKT_INT BIT(3)
-#define BIT_FS_EOSP_INT BIT(2)
-#define BIT_FS_RPWM2_INT BIT(1)
-#define BIT_FS_RPWM_INT BIT(0)
-
-/* 2 REG_SPWR0 (Offset 0x1140) */
-
-#define BIT_SHIFT_MID_31TO0 0
-#define BIT_MASK_MID_31TO0 0xffffffffL
-#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0)
-#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0)
-
-/* 2 REG_SPWR1 (Offset 0x1144) */
-
-#define BIT_SHIFT_MID_63TO32 0
-#define BIT_MASK_MID_63TO32 0xffffffffL
-#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32)
-#define BIT_GET_MID_63TO32(x) \
- (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32)
-
-/* 2 REG_SPWR2 (Offset 0x1148) */
-
-#define BIT_SHIFT_MID_95O64 0
-#define BIT_MASK_MID_95O64 0xffffffffL
-#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64)
-#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64)
-
-/* 2 REG_SPWR3 (Offset 0x114C) */
-
-#define BIT_SHIFT_MID_127TO96 0
-#define BIT_MASK_MID_127TO96 0xffffffffL
-#define BIT_MID_127TO96(x) \
- (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96)
-#define BIT_GET_MID_127TO96(x) \
- (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96)
-
-/* 2 REG_POWSEQ (Offset 0x1150) */
-
-#define BIT_SHIFT_SEQNUM_MID 16
-#define BIT_MASK_SEQNUM_MID 0xffff
-#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID)
-#define BIT_GET_SEQNUM_MID(x) \
- (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID)
-
-#define BIT_SHIFT_REF_MID 0
-#define BIT_MASK_REF_MID 0x7f
-#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID)
-#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID)
-
-/* 2 REG_TC7_CTRL_V1 (Offset 0x1158) */
-
-#define BIT_TC7INT_EN BIT(26)
-#define BIT_TC7MODE BIT(25)
-#define BIT_TC7EN BIT(24)
-
-#define BIT_SHIFT_TC7DATA 0
-#define BIT_MASK_TC7DATA 0xffffff
-#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA)
-#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA)
-
-/* 2 REG_TC8_CTRL_V1 (Offset 0x115C) */
-
-#define BIT_TC8INT_EN BIT(26)
-#define BIT_TC8MODE BIT(25)
-#define BIT_TC8EN BIT(24)
-
-#define BIT_SHIFT_TC8DATA 0
-#define BIT_MASK_TC8DATA 0xffffff
-#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA)
-#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI3_EOSP_INT_EN BIT(28)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI2_EOSP_INT_EN BIT(24)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI1_EOSP_INT_EN BIT(20)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI0_EOSP_INT_EN BIT(16)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1)
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
-
-#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI3_EOSP_INT BIT(28)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI2_EOSP_INT BIT(24)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI1_EOSP_INT BIT(20)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI0_EOSP_INT BIT(16)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI3_TX_NULL1_INT BIT(7)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI3_TX_NULL0_INT BIT(6)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI2_TX_NULL1_INT BIT(5)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI2_TX_NULL0_INT BIT(4)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI1_TX_NULL1_INT BIT(3)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI1_TX_NULL0_INT BIT(2)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI0_TX_NULL1_INT BIT(1)
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_FS_CLI0_TX_NULL0_INT BIT(0)
-
-/* 2 REG_MSG2 (Offset 0x11F0) */
-
-#define BIT_SHIFT_FW_MSG2 0
-#define BIT_MASK_FW_MSG2 0xffffffffL
-#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2)
-#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2)
-
-/* 2 REG_MSG3 (Offset 0x11F4) */
-
-#define BIT_SHIFT_FW_MSG3 0
-#define BIT_MASK_FW_MSG3 0xffffffffL
-#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3)
-#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3)
-
-/* 2 REG_MSG4 (Offset 0x11F8) */
-
-#define BIT_SHIFT_FW_MSG4 0
-#define BIT_MASK_FW_MSG4 0xffffffffL
-#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4)
-#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4)
-
-/* 2 REG_MSG5 (Offset 0x11FC) */
-
-#define BIT_SHIFT_FW_MSG5 0
-#define BIT_MASK_FW_MSG5 0xffffffffL
-#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5)
-#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5)
-
-/* 2 REG_DDMA_CH0SA (Offset 0x1200) */
-
-#define BIT_SHIFT_DDMACH0_SA 0
-#define BIT_MASK_DDMACH0_SA 0xffffffffL
-#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA)
-#define BIT_GET_DDMACH0_SA(x) \
- (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA)
-
-/* 2 REG_DDMA_CH0DA (Offset 0x1204) */
-
-#define BIT_SHIFT_DDMACH0_DA 0
-#define BIT_MASK_DDMACH0_DA 0xffffffffL
-#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA)
-#define BIT_GET_DDMACH0_DA(x) \
- (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA)
-
-/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */
-
-#define BIT_DDMACH0_OWN BIT(31)
-#define BIT_DDMACH0_CHKSUM_EN BIT(29)
-#define BIT_DDMACH0_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH0_CHKSUM_STS BIT(27)
-#define BIT_DDMACH0_DDMA_MODE BIT(26)
-#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH0_CHKSUM_CONT BIT(24)
-
-#define BIT_SHIFT_DDMACH0_DLEN 0
-#define BIT_MASK_DDMACH0_DLEN 0x3ffff
-#define BIT_DDMACH0_DLEN(x) \
- (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN)
-#define BIT_GET_DDMACH0_DLEN(x) \
- (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN)
-
-/* 2 REG_DDMA_CH1SA (Offset 0x1210) */
-
-#define BIT_SHIFT_DDMACH1_SA 0
-#define BIT_MASK_DDMACH1_SA 0xffffffffL
-#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA)
-#define BIT_GET_DDMACH1_SA(x) \
- (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA)
-
-/* 2 REG_DDMA_CH1DA (Offset 0x1214) */
-
-#define BIT_SHIFT_DDMACH1_DA 0
-#define BIT_MASK_DDMACH1_DA 0xffffffffL
-#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA)
-#define BIT_GET_DDMACH1_DA(x) \
- (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA)
-
-/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */
-
-#define BIT_DDMACH1_OWN BIT(31)
-#define BIT_DDMACH1_CHKSUM_EN BIT(29)
-#define BIT_DDMACH1_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH1_CHKSUM_STS BIT(27)
-#define BIT_DDMACH1_DDMA_MODE BIT(26)
-#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH1_CHKSUM_CONT BIT(24)
-
-#define BIT_SHIFT_DDMACH1_DLEN 0
-#define BIT_MASK_DDMACH1_DLEN 0x3ffff
-#define BIT_DDMACH1_DLEN(x) \
- (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN)
-#define BIT_GET_DDMACH1_DLEN(x) \
- (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN)
-
-/* 2 REG_DDMA_CH2SA (Offset 0x1220) */
-
-#define BIT_SHIFT_DDMACH2_SA 0
-#define BIT_MASK_DDMACH2_SA 0xffffffffL
-#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA)
-#define BIT_GET_DDMACH2_SA(x) \
- (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA)
-
-/* 2 REG_DDMA_CH2DA (Offset 0x1224) */
-
-#define BIT_SHIFT_DDMACH2_DA 0
-#define BIT_MASK_DDMACH2_DA 0xffffffffL
-#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA)
-#define BIT_GET_DDMACH2_DA(x) \
- (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA)
-
-/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */
-
-#define BIT_DDMACH2_OWN BIT(31)
-#define BIT_DDMACH2_CHKSUM_EN BIT(29)
-#define BIT_DDMACH2_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH2_CHKSUM_STS BIT(27)
-#define BIT_DDMACH2_DDMA_MODE BIT(26)
-#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH2_CHKSUM_CONT BIT(24)
-
-#define BIT_SHIFT_DDMACH2_DLEN 0
-#define BIT_MASK_DDMACH2_DLEN 0x3ffff
-#define BIT_DDMACH2_DLEN(x) \
- (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN)
-#define BIT_GET_DDMACH2_DLEN(x) \
- (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN)
-
-/* 2 REG_DDMA_CH3SA (Offset 0x1230) */
-
-#define BIT_SHIFT_DDMACH3_SA 0
-#define BIT_MASK_DDMACH3_SA 0xffffffffL
-#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA)
-#define BIT_GET_DDMACH3_SA(x) \
- (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA)
-
-/* 2 REG_DDMA_CH3DA (Offset 0x1234) */
-
-#define BIT_SHIFT_DDMACH3_DA 0
-#define BIT_MASK_DDMACH3_DA 0xffffffffL
-#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA)
-#define BIT_GET_DDMACH3_DA(x) \
- (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA)
-
-/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */
-
-#define BIT_DDMACH3_OWN BIT(31)
-#define BIT_DDMACH3_CHKSUM_EN BIT(29)
-#define BIT_DDMACH3_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH3_CHKSUM_STS BIT(27)
-#define BIT_DDMACH3_DDMA_MODE BIT(26)
-#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH3_CHKSUM_CONT BIT(24)
-
-#define BIT_SHIFT_DDMACH3_DLEN 0
-#define BIT_MASK_DDMACH3_DLEN 0x3ffff
-#define BIT_DDMACH3_DLEN(x) \
- (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN)
-#define BIT_GET_DDMACH3_DLEN(x) \
- (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN)
-
-/* 2 REG_DDMA_CH4SA (Offset 0x1240) */
-
-#define BIT_SHIFT_DDMACH4_SA 0
-#define BIT_MASK_DDMACH4_SA 0xffffffffL
-#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA)
-#define BIT_GET_DDMACH4_SA(x) \
- (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA)
-
-/* 2 REG_DDMA_CH4DA (Offset 0x1244) */
-
-#define BIT_SHIFT_DDMACH4_DA 0
-#define BIT_MASK_DDMACH4_DA 0xffffffffL
-#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA)
-#define BIT_GET_DDMACH4_DA(x) \
- (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA)
-
-/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */
-
-#define BIT_DDMACH4_OWN BIT(31)
-#define BIT_DDMACH4_CHKSUM_EN BIT(29)
-#define BIT_DDMACH4_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH4_CHKSUM_STS BIT(27)
-#define BIT_DDMACH4_DDMA_MODE BIT(26)
-#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH4_CHKSUM_CONT BIT(24)
-
-#define BIT_SHIFT_DDMACH4_DLEN 0
-#define BIT_MASK_DDMACH4_DLEN 0x3ffff
-#define BIT_DDMACH4_DLEN(x) \
- (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN)
-#define BIT_GET_DDMACH4_DLEN(x) \
- (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN)
-
-/* 2 REG_DDMA_CH5SA (Offset 0x1250) */
-
-#define BIT_SHIFT_DDMACH5_SA 0
-#define BIT_MASK_DDMACH5_SA 0xffffffffL
-#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA)
-#define BIT_GET_DDMACH5_SA(x) \
- (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA)
-
-/* 2 REG_DDMA_CH5DA (Offset 0x1254) */
-
-#define BIT_DDMACH5_OWN BIT(31)
-#define BIT_DDMACH5_CHKSUM_EN BIT(29)
-#define BIT_DDMACH5_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH5_CHKSUM_STS BIT(27)
-#define BIT_DDMACH5_DDMA_MODE BIT(26)
-#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH5_CHKSUM_CONT BIT(24)
-
-#define BIT_SHIFT_DDMACH5_DA 0
-#define BIT_MASK_DDMACH5_DA 0xffffffffL
-#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA)
-#define BIT_GET_DDMACH5_DA(x) \
- (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA)
-
-#define BIT_SHIFT_DDMACH5_DLEN 0
-#define BIT_MASK_DDMACH5_DLEN 0x3ffff
-#define BIT_DDMACH5_DLEN(x) \
- (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN)
-#define BIT_GET_DDMACH5_DLEN(x) \
- (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN)
-
-/* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */
-
-#define BIT_DDMACH5_MSK BIT(5)
-#define BIT_DDMACH4_MSK BIT(4)
-#define BIT_DDMACH3_MSK BIT(3)
-#define BIT_DDMACH2_MSK BIT(2)
-#define BIT_DDMACH1_MSK BIT(1)
-#define BIT_DDMACH0_MSK BIT(0)
-
-/* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */
-
-#define BIT_DDMACH5_BUSY BIT(5)
-#define BIT_DDMACH4_BUSY BIT(4)
-#define BIT_DDMACH3_BUSY BIT(3)
-#define BIT_DDMACH2_BUSY BIT(2)
-#define BIT_DDMACH1_BUSY BIT(1)
-#define BIT_DDMACH0_BUSY BIT(0)
-
-/* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */
-
-#define BIT_SHIFT_IDDMA0_CHKSUM 0
-#define BIT_MASK_IDDMA0_CHKSUM 0xffff
-#define BIT_IDDMA0_CHKSUM(x) \
- (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM)
-#define BIT_GET_IDDMA0_CHKSUM(x) \
- (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM)
-
-/* 2 REG_DDMA_MONITOR (Offset 0x12FC) */
-
-#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14)
-#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13)
-#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12)
-#define BIT_ECRC_EN_V1 BIT(7)
-#define BIT_MDIO_RFLAG_V1 BIT(6)
-#define BIT_CH5_ERR BIT(5)
-#define BIT_MDIO_WFLAG_V1 BIT(5)
-#define BIT_CH4_ERR BIT(4)
-#define BIT_CH3_ERR BIT(3)
-#define BIT_CH2_ERR BIT(2)
-#define BIT_CH1_ERR BIT(1)
-#define BIT_CH0_ERR BIT(0)
-
-/* 2 REG_STC_INT_CS (Offset 0x1300) */
-
-#define BIT_STC_INT_EN BIT(31)
-
-#define BIT_SHIFT_STC_INT_FLAG 16
-#define BIT_MASK_STC_INT_FLAG 0xff
-#define BIT_STC_INT_FLAG(x) \
- (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG)
-#define BIT_GET_STC_INT_FLAG(x) \
- (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG)
-
-#define BIT_SHIFT_STC_INT_IDX 8
-#define BIT_MASK_STC_INT_IDX 0x7
-#define BIT_STC_INT_IDX(x) \
- (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX)
-#define BIT_GET_STC_INT_IDX(x) \
- (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX)
-
-#define BIT_SHIFT_STC_INT_REALTIME_CS 0
-#define BIT_MASK_STC_INT_REALTIME_CS 0x3f
-#define BIT_STC_INT_REALTIME_CS(x) \
- (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS)
-#define BIT_GET_STC_INT_REALTIME_CS(x) \
- (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS)
-
-/* 2 REG_ST_INT_CFG (Offset 0x1304) */
-
-#define BIT_STC_INT_GRP_EN BIT(31)
-
-#define BIT_SHIFT_STC_INT_EXPECT_LS 8
-#define BIT_MASK_STC_INT_EXPECT_LS 0x3f
-#define BIT_STC_INT_EXPECT_LS(x) \
- (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS)
-#define BIT_GET_STC_INT_EXPECT_LS(x) \
- (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS)
-
-#define BIT_SHIFT_STC_INT_EXPECT_CS 0
-#define BIT_MASK_STC_INT_EXPECT_CS 0x3f
-#define BIT_STC_INT_EXPECT_CS(x) \
- (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS)
-#define BIT_GET_STC_INT_EXPECT_CS(x) \
- (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS)
-
-/* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */
-
-#define BIT_CMU_DLY_EN BIT(31)
-#define BIT_CMU_DLY_MODE BIT(30)
-
-#define BIT_SHIFT_CMU_DLY_PRE_DIV 0
-#define BIT_MASK_CMU_DLY_PRE_DIV 0xff
-#define BIT_CMU_DLY_PRE_DIV(x) \
- (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV)
-#define BIT_GET_CMU_DLY_PRE_DIV(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV)
-
-/* 2 REG_CMU_DLY_CFG (Offset 0x1314) */
-
-#define BIT_SHIFT_CMU_DLY_LTR_A2I 24
-#define BIT_MASK_CMU_DLY_LTR_A2I 0xff
-#define BIT_CMU_DLY_LTR_A2I(x) \
- (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I)
-#define BIT_GET_CMU_DLY_LTR_A2I(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I)
-
-#define BIT_SHIFT_CMU_DLY_LTR_I2A 16
-#define BIT_MASK_CMU_DLY_LTR_I2A 0xff
-#define BIT_CMU_DLY_LTR_I2A(x) \
- (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A)
-#define BIT_GET_CMU_DLY_LTR_I2A(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A)
-
-#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8
-#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff
-#define BIT_CMU_DLY_LTR_IDLE(x) \
- (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE)
-#define BIT_GET_CMU_DLY_LTR_IDLE(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE)
-
-#define BIT_SHIFT_CMU_DLY_LTR_ACT 0
-#define BIT_MASK_CMU_DLY_LTR_ACT 0xff
-#define BIT_CMU_DLY_LTR_ACT(x) \
- (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT)
-#define BIT_GET_CMU_DLY_LTR_ACT(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT)
-
-/* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */
-
-#define BIT_SHIFT_H2CQ_TXBD_DESA 0
-#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_H2CQ_TXBD_DESA(x) \
- (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA)
-#define BIT_GET_H2CQ_TXBD_DESA(x) \
- (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA)
-
-/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */
-
-#define BIT_PCIE_H2CQ_FLAG BIT(14)
-
-/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */
-
-#define BIT_SHIFT_H2CQ_DESC_MODE 12
-#define BIT_MASK_H2CQ_DESC_MODE 0x3
-#define BIT_H2CQ_DESC_MODE(x) \
- (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE)
-#define BIT_GET_H2CQ_DESC_MODE(x) \
- (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE)
-
-#define BIT_SHIFT_H2CQ_DESC_NUM 0
-#define BIT_MASK_H2CQ_DESC_NUM 0xfff
-#define BIT_H2CQ_DESC_NUM(x) \
- (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM)
-#define BIT_GET_H2CQ_DESC_NUM(x) \
- (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM)
-
-/* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */
-
-#define BIT_SHIFT_H2CQ_HW_IDX 16
-#define BIT_MASK_H2CQ_HW_IDX 0xfff
-#define BIT_H2CQ_HW_IDX(x) \
- (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX)
-#define BIT_GET_H2CQ_HW_IDX(x) \
- (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX)
-
-#define BIT_SHIFT_H2CQ_HOST_IDX 0
-#define BIT_MASK_H2CQ_HOST_IDX 0xfff
-#define BIT_H2CQ_HOST_IDX(x) \
- (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX)
-#define BIT_GET_H2CQ_HOST_IDX(x) \
- (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX)
-
-/* 2 REG_H2CQ_CSR (Offset 0x1330) */
-
-#define BIT_H2CQ_FULL BIT(31)
-#define BIT_CLR_H2CQ_HOST_IDX BIT(16)
-#define BIT_CLR_H2CQ_HW_IDX BIT(8)
-
-/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
-
-#define BIT_CHANGE_PCIE_SPEED BIT(18)
-
-/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
-
-#define BIT_SHIFT_GEN1_GEN2 16
-#define BIT_MASK_GEN1_GEN2 0x3
-#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2)
-#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2)
-
-/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
-
-#define BIT_SHIFT_AUTO_HANG_RELEASE 0
-#define BIT_MASK_AUTO_HANG_RELEASE 0x7
-#define BIT_AUTO_HANG_RELEASE(x) \
- (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE)
-#define BIT_GET_AUTO_HANG_RELEASE(x) \
- (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE)
-
-/* 2 REG_OLD_DEHANG (Offset 0x13F4) */
-
-#define BIT_OLD_DEHANG BIT(1)
-
-/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */
-
-#define BIT_SHIFT_AC1_PKT_INFO 16
-#define BIT_MASK_AC1_PKT_INFO 0xfff
-#define BIT_AC1_PKT_INFO(x) \
- (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO)
-#define BIT_GET_AC1_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO)
-
-#define BIT_SHIFT_AC0_PKT_INFO 0
-#define BIT_MASK_AC0_PKT_INFO 0xfff
-#define BIT_AC0_PKT_INFO(x) \
- (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO)
-#define BIT_GET_AC0_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO)
-
-/* 2 REG_Q2_Q3_INFO (Offset 0x1404) */
-
-#define BIT_SHIFT_AC3_PKT_INFO 16
-#define BIT_MASK_AC3_PKT_INFO 0xfff
-#define BIT_AC3_PKT_INFO(x) \
- (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO)
-#define BIT_GET_AC3_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO)
-
-#define BIT_SHIFT_AC2_PKT_INFO 0
-#define BIT_MASK_AC2_PKT_INFO 0xfff
-#define BIT_AC2_PKT_INFO(x) \
- (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO)
-#define BIT_GET_AC2_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO)
-
-/* 2 REG_Q4_Q5_INFO (Offset 0x1408) */
-
-#define BIT_SHIFT_AC5_PKT_INFO 16
-#define BIT_MASK_AC5_PKT_INFO 0xfff
-#define BIT_AC5_PKT_INFO(x) \
- (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO)
-#define BIT_GET_AC5_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO)
-
-#define BIT_SHIFT_AC4_PKT_INFO 0
-#define BIT_MASK_AC4_PKT_INFO 0xfff
-#define BIT_AC4_PKT_INFO(x) \
- (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO)
-#define BIT_GET_AC4_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO)
-
-/* 2 REG_Q6_Q7_INFO (Offset 0x140C) */
-
-#define BIT_SHIFT_AC7_PKT_INFO 16
-#define BIT_MASK_AC7_PKT_INFO 0xfff
-#define BIT_AC7_PKT_INFO(x) \
- (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO)
-#define BIT_GET_AC7_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO)
-
-#define BIT_SHIFT_AC6_PKT_INFO 0
-#define BIT_MASK_AC6_PKT_INFO 0xfff
-#define BIT_AC6_PKT_INFO(x) \
- (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO)
-#define BIT_GET_AC6_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO)
-
-/* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */
-
-#define BIT_SHIFT_HIQ_PKT_INFO 16
-#define BIT_MASK_HIQ_PKT_INFO 0xfff
-#define BIT_HIQ_PKT_INFO(x) \
- (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO)
-#define BIT_GET_HIQ_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO)
-
-#define BIT_SHIFT_MGQ_PKT_INFO 0
-#define BIT_MASK_MGQ_PKT_INFO 0xfff
-#define BIT_MGQ_PKT_INFO(x) \
- (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO)
-#define BIT_GET_MGQ_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO)
-
-/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
-
-#define BIT_SHIFT_CMDQ_PKT_INFO 16
-#define BIT_MASK_CMDQ_PKT_INFO 0xfff
-#define BIT_CMDQ_PKT_INFO(x) \
- (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO)
-#define BIT_GET_CMDQ_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO)
-
-/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
-
-#define BIT_SHIFT_BCNQ_PKT_INFO 0
-#define BIT_MASK_BCNQ_PKT_INFO 0xfff
-#define BIT_BCNQ_PKT_INFO(x) \
- (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO)
-#define BIT_GET_BCNQ_PKT_INFO(x) \
- (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO)
-
-/* 2 REG_USEREG_SETTING (Offset 0x1420) */
-
-#define BIT_NDPA_USEREG BIT(21)
-
-#define BIT_SHIFT_RETRY_USEREG 19
-#define BIT_MASK_RETRY_USEREG 0x3
-#define BIT_RETRY_USEREG(x) \
- (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG)
-#define BIT_GET_RETRY_USEREG(x) \
- (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG)
-
-#define BIT_SHIFT_TRYPKT_USEREG 17
-#define BIT_MASK_TRYPKT_USEREG 0x3
-#define BIT_TRYPKT_USEREG(x) \
- (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG)
-#define BIT_GET_TRYPKT_USEREG(x) \
- (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG)
-
-#define BIT_CTLPKT_USEREG BIT(16)
-
-/* 2 REG_AESIV_SETTING (Offset 0x1424) */
-
-#define BIT_SHIFT_AESIV_OFFSET 0
-#define BIT_MASK_AESIV_OFFSET 0xfff
-#define BIT_AESIV_OFFSET(x) \
- (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET)
-#define BIT_GET_AESIV_OFFSET(x) \
- (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET)
-
-/* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */
-
-#define BIT_BF0_TIMER_SET BIT(31)
-#define BIT_BF0_TIMER_CLR BIT(30)
-#define BIT_BF0_UPDATE_EN BIT(29)
-#define BIT_BF0_TIMER_EN BIT(28)
-
-#define BIT_SHIFT_BF0_PRETIME_OVER 16
-#define BIT_MASK_BF0_PRETIME_OVER 0xfff
-#define BIT_BF0_PRETIME_OVER(x) \
- (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER)
-#define BIT_GET_BF0_PRETIME_OVER(x) \
- (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER)
-
-#define BIT_SHIFT_BF0_LIFETIME 0
-#define BIT_MASK_BF0_LIFETIME 0xffff
-#define BIT_BF0_LIFETIME(x) \
- (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME)
-#define BIT_GET_BF0_LIFETIME(x) \
- (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME)
-
-/* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */
-
-#define BIT_BF1_TIMER_SET BIT(31)
-#define BIT_BF1_TIMER_CLR BIT(30)
-#define BIT_BF1_UPDATE_EN BIT(29)
-#define BIT_BF1_TIMER_EN BIT(28)
-
-#define BIT_SHIFT_BF1_PRETIME_OVER 16
-#define BIT_MASK_BF1_PRETIME_OVER 0xfff
-#define BIT_BF1_PRETIME_OVER(x) \
- (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER)
-#define BIT_GET_BF1_PRETIME_OVER(x) \
- (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER)
-
-#define BIT_SHIFT_BF1_LIFETIME 0
-#define BIT_MASK_BF1_LIFETIME 0xffff
-#define BIT_BF1_LIFETIME(x) \
- (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME)
-#define BIT_GET_BF1_LIFETIME(x) \
- (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME)
-
-/* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */
-
-#define BIT_EN_VHT_LDPC BIT(9)
-#define BIT_EN_HT_LDPC BIT(8)
-#define BIT_BF1_TIMEOUT_EN BIT(1)
-#define BIT_BF0_TIMEOUT_EN BIT(0)
-
-/* 2 REG_MACID_RELEASE0 (Offset 0x1434) */
-
-#define BIT_SHIFT_MACID31_0_RELEASE 0
-#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL
-#define BIT_MACID31_0_RELEASE(x) \
- (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE)
-#define BIT_GET_MACID31_0_RELEASE(x) \
- (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE)
-
-/* 2 REG_MACID_RELEASE1 (Offset 0x1438) */
-
-#define BIT_SHIFT_MACID63_32_RELEASE 0
-#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL
-#define BIT_MACID63_32_RELEASE(x) \
- (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE)
-#define BIT_GET_MACID63_32_RELEASE(x) \
- (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE)
-
-/* 2 REG_MACID_RELEASE2 (Offset 0x143C) */
-
-#define BIT_SHIFT_MACID95_64_RELEASE 0
-#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL
-#define BIT_MACID95_64_RELEASE(x) \
- (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE)
-#define BIT_GET_MACID95_64_RELEASE(x) \
- (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE)
-
-/* 2 REG_MACID_RELEASE3 (Offset 0x1440) */
-
-#define BIT_SHIFT_MACID127_96_RELEASE 0
-#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL
-#define BIT_MACID127_96_RELEASE(x) \
- (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE)
-#define BIT_GET_MACID127_96_RELEASE(x) \
- (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE)
-
-/* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */
-
-#define BIT_MACID_VALUE BIT(7)
-
-#define BIT_SHIFT_MACID_OFFSET 0
-#define BIT_MASK_MACID_OFFSET 0x7f
-#define BIT_MACID_OFFSET(x) \
- (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET)
-#define BIT_GET_MACID_OFFSET(x) \
- (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET)
-
-/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */
-
-#define BIT_SHIFT_VI_FAST_EDCA_TO 24
-#define BIT_MASK_VI_FAST_EDCA_TO 0xff
-#define BIT_VI_FAST_EDCA_TO(x) \
- (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO)
-#define BIT_GET_VI_FAST_EDCA_TO(x) \
- (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO)
-
-#define BIT_VI_THRESHOLD_SEL BIT(23)
-
-#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16
-#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f
-#define BIT_VI_FAST_EDCA_PKT_TH(x) \
- (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)
-#define BIT_GET_VI_FAST_EDCA_PKT_TH(x) \
- (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH)
-
-#define BIT_SHIFT_VO_FAST_EDCA_TO 8
-#define BIT_MASK_VO_FAST_EDCA_TO 0xff
-#define BIT_VO_FAST_EDCA_TO(x) \
- (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO)
-#define BIT_GET_VO_FAST_EDCA_TO(x) \
- (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO)
-
-#define BIT_VO_THRESHOLD_SEL BIT(7)
-
-#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0
-#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f
-#define BIT_VO_FAST_EDCA_PKT_TH(x) \
- (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)
-#define BIT_GET_VO_FAST_EDCA_PKT_TH(x) \
- (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH)
-
-/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */
-
-#define BIT_SHIFT_BK_FAST_EDCA_TO 24
-#define BIT_MASK_BK_FAST_EDCA_TO 0xff
-#define BIT_BK_FAST_EDCA_TO(x) \
- (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO)
-#define BIT_GET_BK_FAST_EDCA_TO(x) \
- (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO)
-
-#define BIT_BK_THRESHOLD_SEL BIT(23)
-
-#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16
-#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f
-#define BIT_BK_FAST_EDCA_PKT_TH(x) \
- (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)
-#define BIT_GET_BK_FAST_EDCA_PKT_TH(x) \
- (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH)
-
-#define BIT_SHIFT_BE_FAST_EDCA_TO 8
-#define BIT_MASK_BE_FAST_EDCA_TO 0xff
-#define BIT_BE_FAST_EDCA_TO(x) \
- (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO)
-#define BIT_GET_BE_FAST_EDCA_TO(x) \
- (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO)
-
-#define BIT_BE_THRESHOLD_SEL BIT(7)
-
-#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0
-#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f
-#define BIT_BE_FAST_EDCA_PKT_TH(x) \
- (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)
-#define BIT_GET_BE_FAST_EDCA_PKT_TH(x) \
- (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH)
-
-/* 2 REG_MACID_DROP0 (Offset 0x1450) */
-
-#define BIT_SHIFT_MACID31_0_DROP 0
-#define BIT_MASK_MACID31_0_DROP 0xffffffffL
-#define BIT_MACID31_0_DROP(x) \
- (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP)
-#define BIT_GET_MACID31_0_DROP(x) \
- (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP)
-
-/* 2 REG_MACID_DROP1 (Offset 0x1454) */
-
-#define BIT_SHIFT_MACID63_32_DROP 0
-#define BIT_MASK_MACID63_32_DROP 0xffffffffL
-#define BIT_MACID63_32_DROP(x) \
- (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP)
-#define BIT_GET_MACID63_32_DROP(x) \
- (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP)
-
-/* 2 REG_MACID_DROP2 (Offset 0x1458) */
-
-#define BIT_SHIFT_MACID95_64_DROP 0
-#define BIT_MASK_MACID95_64_DROP 0xffffffffL
-#define BIT_MACID95_64_DROP(x) \
- (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP)
-#define BIT_GET_MACID95_64_DROP(x) \
- (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP)
-
-/* 2 REG_MACID_DROP3 (Offset 0x145C) */
-
-#define BIT_SHIFT_MACID127_96_DROP 0
-#define BIT_MASK_MACID127_96_DROP 0xffffffffL
-#define BIT_MACID127_96_DROP(x) \
- (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP)
-#define BIT_GET_MACID127_96_DROP(x) \
- (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_0(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_0)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_1(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_1)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_2 (Offset 0x1468) */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_2(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_2)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_3(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_3)
-
-/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */
-
-#define BIT_R_MGG_FIFO_EN BIT(31)
-
-#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28
-#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7
-#define BIT_R_MGG_FIFO_PG_SIZE(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE)
-#define BIT_GET_R_MGG_FIFO_PG_SIZE(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE)
-
-#define BIT_SHIFT_R_MGG_FIFO_START_PG 16
-#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff
-#define BIT_R_MGG_FIFO_START_PG(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG)
-#define BIT_GET_R_MGG_FIFO_START_PG(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG)
-
-#define BIT_SHIFT_R_MGG_FIFO_SIZE 14
-#define BIT_MASK_R_MGG_FIFO_SIZE 0x3
-#define BIT_R_MGG_FIFO_SIZE(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE)
-#define BIT_GET_R_MGG_FIFO_SIZE(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE)
-
-#define BIT_R_MGG_FIFO_PAUSE BIT(13)
-
-#define BIT_SHIFT_R_MGG_FIFO_RPTR 8
-#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f
-#define BIT_R_MGG_FIFO_RPTR(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR)
-#define BIT_GET_R_MGG_FIFO_RPTR(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR)
-
-#define BIT_R_MGG_FIFO_OV BIT(7)
-#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6)
-#define BIT_R_EN_CPU_LIFETIME BIT(5)
-
-#define BIT_SHIFT_R_MGG_FIFO_WPTR 0
-#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f
-#define BIT_R_MGG_FIFO_WPTR(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR)
-#define BIT_GET_R_MGG_FIFO_WPTR(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR)
-
-/* 2 REG_MGG_FIFO_INT (Offset 0x1474) */
-
-#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16
-#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff
-#define BIT_R_MGG_FIFO_INT_FLAG(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG)
-#define BIT_GET_R_MGG_FIFO_INT_FLAG(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG)
-
-#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0
-#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff
-#define BIT_R_MGG_FIFO_INT_MASK(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK)
-#define BIT_GET_R_MGG_FIFO_INT_MASK(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK)
-
-/* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */
-
-#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16
-#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff
-#define BIT_R_MGG_FIFO_LIFETIME(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME)
-#define BIT_GET_R_MGG_FIFO_LIFETIME(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME)
-
-#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0
-#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff
-#define BIT_R_MGG_FIFO_VALID_MAP(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) \
- << BIT_SHIFT_R_MGG_FIFO_VALID_MAP)
-#define BIT_GET_R_MGG_FIFO_VALID_MAP(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & \
- BIT_MASK_R_MGG_FIFO_VALID_MAP)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f
-#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
-
-#define BIT_SHIFT_P2PON_DIS_TXTIME 0
-#define BIT_MASK_P2PON_DIS_TXTIME 0xff
-#define BIT_P2PON_DIS_TXTIME(x) \
- (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME)
-#define BIT_GET_P2PON_DIS_TXTIME(x) \
- (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME)
-
-/* 2 REG_MACID_SHCUT_OFFSET (Offset 0x1480) */
-
-#define BIT_SHIFT_MACID_SHCUT_OFFSET_V1 0
-#define BIT_MASK_MACID_SHCUT_OFFSET_V1 0xff
-#define BIT_MACID_SHCUT_OFFSET_V1(x) \
- (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1) \
- << BIT_SHIFT_MACID_SHCUT_OFFSET_V1)
-#define BIT_GET_MACID_SHCUT_OFFSET_V1(x) \
- (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1) & \
- BIT_MASK_MACID_SHCUT_OFFSET_V1)
-
-/* 2 REG_MU_TX_CTL (Offset 0x14C0) */
-
-#define BIT_R_EN_REVERS_GTAB BIT(6)
-
-#define BIT_SHIFT_R_MU_TABLE_VALID 0
-#define BIT_MASK_R_MU_TABLE_VALID 0x3f
-#define BIT_R_MU_TABLE_VALID(x) \
- (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID)
-#define BIT_GET_R_MU_TABLE_VALID(x) \
- (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID)
-
-#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0
-#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL
-#define BIT_R_MU_STA_GTAB_VALID(x) \
- (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID)
-#define BIT_GET_R_MU_STA_GTAB_VALID(x) \
- (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID)
-
-#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0
-#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL
-#define BIT_R_MU_STA_GTAB_POSITION(x) \
- (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) \
- << BIT_SHIFT_R_MU_STA_GTAB_POSITION)
-#define BIT_GET_R_MU_STA_GTAB_POSITION(x) \
- (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & \
- BIT_MASK_R_MU_STA_GTAB_POSITION)
-
-/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */
-
-#define BIT_MU_DNGCNT_RST BIT(20)
-
-#define BIT_SHIFT_MU_DBGCNT_SEL 16
-#define BIT_MASK_MU_DBGCNT_SEL 0xf
-#define BIT_MU_DBGCNT_SEL(x) \
- (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL)
-#define BIT_GET_MU_DBGCNT_SEL(x) \
- (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL)
-
-#define BIT_SHIFT_MU_DNGCNT 0
-#define BIT_MASK_MU_DNGCNT 0xffff
-#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT)
-#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT)
-
-/* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */
-
-#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0
-#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL
-#define BIT_CPUMGQ_TX_TIMER_V1(x) \
- (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)
-#define BIT_GET_CPUMGQ_TX_TIMER_V1(x) \
- (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1)
-
-/* 2 REG_PS_TIMER_A (Offset 0x1504) */
-
-#define BIT_SHIFT_PS_TIMER_A_V1 0
-#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL
-#define BIT_PS_TIMER_A_V1(x) \
- (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1)
-#define BIT_GET_PS_TIMER_A_V1(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1)
-
-/* 2 REG_PS_TIMER_B (Offset 0x1508) */
-
-#define BIT_SHIFT_PS_TIMER_B_V1 0
-#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL
-#define BIT_PS_TIMER_B_V1(x) \
- (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1)
-#define BIT_GET_PS_TIMER_B_V1(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1)
-
-/* 2 REG_PS_TIMER_C (Offset 0x150C) */
-
-#define BIT_SHIFT_PS_TIMER_C_V1 0
-#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL
-#define BIT_PS_TIMER_C_V1(x) \
- (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1)
-#define BIT_GET_PS_TIMER_C_V1(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1)
-
-/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */
-
-#define BIT_CPUMGQ_TIMER_EN BIT(31)
-#define BIT_CPUMGQ_TX_EN BIT(28)
-
-#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24
-#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7
-#define BIT_CPUMGQ_TIMER_TSF_SEL(x) \
- (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) \
- << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)
-#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) \
- (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & \
- BIT_MASK_CPUMGQ_TIMER_TSF_SEL)
-
-#define BIT_PS_TIMER_C_EN BIT(23)
-
-#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16
-#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7
-#define BIT_PS_TIMER_C_TSF_SEL(x) \
- (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL)
-#define BIT_GET_PS_TIMER_C_TSF_SEL(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL)
-
-#define BIT_PS_TIMER_B_EN BIT(15)
-
-#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8
-#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7
-#define BIT_PS_TIMER_B_TSF_SEL(x) \
- (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL)
-#define BIT_GET_PS_TIMER_B_TSF_SEL(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL)
-
-#define BIT_PS_TIMER_A_EN BIT(7)
-
-#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0
-#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7
-#define BIT_PS_TIMER_A_TSF_SEL(x) \
- (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL)
-#define BIT_GET_PS_TIMER_A_TSF_SEL(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL)
-
-/* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */
-
-#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0
-#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff
-#define BIT_CPUMGQ_TX_TIMER_EARLY(x) \
- (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) \
- << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)
-#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) \
- (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & \
- BIT_MASK_CPUMGQ_TX_TIMER_EARLY)
-
-/* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */
-
-#define BIT_SHIFT_PS_TIMER_A_EARLY 0
-#define BIT_MASK_PS_TIMER_A_EARLY 0xff
-#define BIT_PS_TIMER_A_EARLY(x) \
- (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY)
-#define BIT_GET_PS_TIMER_A_EARLY(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY)
-
-/* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */
-
-#define BIT_SHIFT_PS_TIMER_B_EARLY 0
-#define BIT_MASK_PS_TIMER_B_EARLY 0xff
-#define BIT_PS_TIMER_B_EARLY(x) \
- (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY)
-#define BIT_GET_PS_TIMER_B_EARLY(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY)
-
-/* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */
-
-#define BIT_SHIFT_PS_TIMER_C_EARLY 0
-#define BIT_MASK_PS_TIMER_C_EARLY 0xff
-#define BIT_PS_TIMER_C_EARLY(x) \
- (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY)
-#define BIT_GET_PS_TIMER_C_EARLY(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY)
-
-/* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */
-
-#define BIT_SHIFT_DTIM_CNT2 24
-#define BIT_MASK_DTIM_CNT2 0xff
-#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2)
-#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2)
-
-#define BIT_SHIFT_DTIM_PERIOD2 16
-#define BIT_MASK_DTIM_PERIOD2 0xff
-#define BIT_DTIM_PERIOD2(x) \
- (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2)
-#define BIT_GET_DTIM_PERIOD2(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2)
-
-#define BIT_DTIM2 BIT(15)
-#define BIT_TIM2 BIT(14)
-
-#define BIT_SHIFT_PS_AID_2 0
-#define BIT_MASK_PS_AID_2 0x7ff
-#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2)
-#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2)
-
-/* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */
-
-#define BIT_SHIFT_DTIM_CNT3 24
-#define BIT_MASK_DTIM_CNT3 0xff
-#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3)
-#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3)
-
-#define BIT_SHIFT_DTIM_PERIOD3 16
-#define BIT_MASK_DTIM_PERIOD3 0xff
-#define BIT_DTIM_PERIOD3(x) \
- (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3)
-#define BIT_GET_DTIM_PERIOD3(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3)
-
-#define BIT_DTIM3 BIT(15)
-#define BIT_TIM3 BIT(14)
-
-#define BIT_SHIFT_PS_AID_3 0
-#define BIT_MASK_PS_AID_3 0x7ff
-#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3)
-#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3)
-
-/* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */
-
-#define BIT_SHIFT_DTIM_CNT4 24
-#define BIT_MASK_DTIM_CNT4 0xff
-#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4)
-#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4)
-
-#define BIT_SHIFT_DTIM_PERIOD4 16
-#define BIT_MASK_DTIM_PERIOD4 0xff
-#define BIT_DTIM_PERIOD4(x) \
- (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4)
-#define BIT_GET_DTIM_PERIOD4(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4)
-
-#define BIT_DTIM4 BIT(15)
-#define BIT_TIM4 BIT(14)
-
-#define BIT_SHIFT_PS_AID_4 0
-#define BIT_MASK_PS_AID_4 0x7ff
-#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4)
-#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4)
-
-/* 2 REG_A1_ADDR_MASK (Offset 0x160C) */
-
-#define BIT_SHIFT_A1_ADDR_MASK 0
-#define BIT_MASK_A1_ADDR_MASK 0xffffffffL
-#define BIT_A1_ADDR_MASK(x) \
- (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK)
-#define BIT_GET_A1_ADDR_MASK(x) \
- (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK)
-
-/* 2 REG_MACID2 (Offset 0x1620) */
-
-#define BIT_SHIFT_MACID2 0
-#define BIT_MASK_MACID2 0xffffffffffffL
-#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2)
-#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2)
-
-/* 2 REG_BSSID2 (Offset 0x1628) */
-
-#define BIT_SHIFT_BSSID2 0
-#define BIT_MASK_BSSID2 0xffffffffffffL
-#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2)
-#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2)
-
-/* 2 REG_MACID3 (Offset 0x1630) */
-
-#define BIT_SHIFT_MACID3 0
-#define BIT_MASK_MACID3 0xffffffffffffL
-#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3)
-#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3)
-
-/* 2 REG_BSSID3 (Offset 0x1638) */
-
-#define BIT_SHIFT_BSSID3 0
-#define BIT_MASK_BSSID3 0xffffffffffffL
-#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3)
-#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3)
-
-/* 2 REG_MACID4 (Offset 0x1640) */
-
-#define BIT_SHIFT_MACID4 0
-#define BIT_MASK_MACID4 0xffffffffffffL
-#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4)
-#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4)
-
-/* 2 REG_BSSID4 (Offset 0x1648) */
-
-#define BIT_SHIFT_BSSID4 0
-#define BIT_MASK_BSSID4 0xffffffffffffL
-#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4)
-#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4)
-
-/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
-
-#define BIT_CLI3_PWRBIT_OW_EN BIT(7)
-#define BIT_CLI3_PWR_ST BIT(6)
-#define BIT_CLI2_PWRBIT_OW_EN BIT(5)
-#define BIT_CLI2_PWR_ST BIT(4)
-#define BIT_CLI1_PWRBIT_OW_EN BIT(3)
-#define BIT_CLI1_PWR_ST BIT(2)
-#define BIT_CLI0_PWRBIT_OW_EN BIT(1)
-#define BIT_CLI0_PWR_ST BIT(0)
-
-/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */
-
-#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7)
-
-/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */
-
-#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6)
-
-/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */
-
-#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4
-#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3
-#define BIT_WMAC_TXMU_ACKPOLICY(x) \
- (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY)
-#define BIT_GET_WMAC_TXMU_ACKPOLICY(x) \
- (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY)
-
-#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1
-#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7
-#define BIT_WMAC_MU_BFEE_PORT_SEL(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) \
- << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL)
-#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & \
- BIT_MASK_WMAC_MU_BFEE_PORT_SEL)
-
-#define BIT_WMAC_MU_BFEE_DIS BIT(0)
-
-/* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */
-
-#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0
-#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff
-#define BIT_WMAC_PAUSE_BB_CLR_TH(x) \
- (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) \
- << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH)
-#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) \
- (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & \
- BIT_MASK_WMAC_PAUSE_BB_CLR_TH)
-
-/* 2 REG_WMAC_MU_ARB (Offset 0x167E) */
-
-#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7)
-#define BIT_WMAC_ARB_SW_EN BIT(6)
-
-#define BIT_SHIFT_WMAC_ARB_SW_STATE 0
-#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f
-#define BIT_WMAC_ARB_SW_STATE(x) \
- (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE)
-#define BIT_GET_WMAC_ARB_SW_STATE(x) \
- (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE)
-
-/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */
-
-#define BIT_SHIFT_WMAC_MU_DBGSEL 5
-#define BIT_MASK_WMAC_MU_DBGSEL 0x3
-#define BIT_WMAC_MU_DBGSEL(x) \
- (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL)
-#define BIT_GET_WMAC_MU_DBGSEL(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL)
-
-#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0
-#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f
-#define BIT_WMAC_MU_CPRD_TIMEOUT(x) \
- (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) \
- << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT)
-#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & \
- BIT_MASK_WMAC_MU_CPRD_TIMEOUT)
-
-/* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */
-
-#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15)
-#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14)
-
-#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12
-#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3
-#define BIT_WMAC_MU_BFRPTSEG_SEL(x) \
- (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) \
- << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL)
-#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & \
- BIT_MASK_WMAC_MU_BFRPTSEG_SEL)
-
-#define BIT_SHIFT_WMAC_MU_BF_MYAID 0
-#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff
-#define BIT_WMAC_MU_BF_MYAID(x) \
- (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID)
-#define BIT_GET_WMAC_MU_BF_MYAID(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID)
-
-#define BIT_SHIFT_BFRPT_PARA 0
-#define BIT_MASK_BFRPT_PARA 0xfff
-#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA)
-#define BIT_GET_BFRPT_PARA(x) \
- (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA)
-
-/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */
-
-#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12
-#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7
-#define BIT_BIT_BFRPT_PARA_USERID_SEL(x) \
- (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) \
- << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL)
-#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) \
- (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & \
- BIT_MASK_BIT_BFRPT_PARA_USERID_SEL)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */
-
-#define BIT_STATUS_BFEE2 BIT(10)
-#define BIT_WMAC_MU_BFEE2_EN BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0
-#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff
-#define BIT_WMAC_MU_BFEE2_AID(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID)
-#define BIT_GET_WMAC_MU_BFEE2_AID(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */
-
-#define BIT_STATUS_BFEE3 BIT(10)
-#define BIT_WMAC_MU_BFEE3_EN BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0
-#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff
-#define BIT_WMAC_MU_BFEE3_AID(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID)
-#define BIT_GET_WMAC_MU_BFEE3_AID(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */
-
-#define BIT_STATUS_BFEE4 BIT(10)
-#define BIT_WMAC_MU_BFEE4_EN BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0
-#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff
-#define BIT_WMAC_MU_BFEE4_AID(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID)
-#define BIT_GET_WMAC_MU_BFEE4_AID(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */
-
-#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55)
-#define BIT_R_WMAC_RXRST_DLY BIT(54)
-#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53)
-#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52)
-#define BIT_STATUS_BFEE5 BIT(10)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */
-
-#define BIT_WMAC_MU_BFEE5_EN BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0
-#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff
-#define BIT_WMAC_MU_BFEE5_AID(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID)
-#define BIT_GET_WMAC_MU_BFEE5_AID(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6 (Offset 0x168C) */
-
-#define BIT_STATUS_BFEE6 BIT(10)
-#define BIT_WMAC_MU_BFEE6_EN BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0
-#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff
-#define BIT_WMAC_MU_BFEE6_AID(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID)
-#define BIT_GET_WMAC_MU_BFEE6_AID(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */
-
-#define BIT_BIT_STATUS_BFEE4 BIT(10)
-#define BIT_WMAC_MU_BFEE7_EN BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0
-#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff
-#define BIT_WMAC_MU_BFEE7_AID(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID)
-#define BIT_GET_WMAC_MU_BFEE7_AID(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID)
-
-/* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */
-
-#define BIT_RST_ALL_COUNTER BIT(31)
-
-#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16
-#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff
-#define BIT_ABORT_RX_VBON_COUNTER(x) \
- (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) \
- << BIT_SHIFT_ABORT_RX_VBON_COUNTER)
-#define BIT_GET_ABORT_RX_VBON_COUNTER(x) \
- (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & \
- BIT_MASK_ABORT_RX_VBON_COUNTER)
-
-#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8
-#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff
-#define BIT_ABORT_RX_RDRDY_COUNTER(x) \
- (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) \
- << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER)
-#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) \
- (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & \
- BIT_MASK_ABORT_RX_RDRDY_COUNTER)
-
-#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0
-#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff
-#define BIT_VBON_EARLY_FALLING_COUNTER(x) \
- (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) \
- << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER)
-#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) \
- (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & \
- BIT_MASK_VBON_EARLY_FALLING_COUNTER)
-
-/* 2 REG_WMAC_PLCP_MONITOR (Offset 0x1694) */
-
-#define BIT_WMAC_PLCP_TRX_SEL BIT(31)
-
-#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28
-#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7
-#define BIT_WMAC_PLCP_RDSIG_SEL(x) \
- (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL)
-#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) \
- (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL)
-
-#define BIT_SHIFT_WMAC_RATE_IDX 24
-#define BIT_MASK_WMAC_RATE_IDX 0xf
-#define BIT_WMAC_RATE_IDX(x) \
- (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX)
-#define BIT_GET_WMAC_RATE_IDX(x) \
- (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX)
-
-#define BIT_SHIFT_WMAC_PLCP_RDSIG 0
-#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff
-#define BIT_WMAC_PLCP_RDSIG(x) \
- (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG)
-#define BIT_GET_WMAC_PLCP_RDSIG(x) \
- (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG)
-
-/* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */
-
-#define BIT_WMAC_MUTX_IDX BIT(24)
-
-/* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */
-
-#define BIT_SHIFT_TA0 0
-#define BIT_MASK_TA0 0xffffffffffffL
-#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0)
-#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0)
-
-/* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */
-
-#define BIT_SHIFT_TA1 0
-#define BIT_MASK_TA1 0xffffffffffffL
-#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1)
-#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1)
-
-/* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */
-
-#define BIT_SHIFT_TA2 0
-#define BIT_MASK_TA2 0xffffffffffffL
-#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2)
-#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2)
-
-/* 2 REG_TRANSMIT_ADDRSS_3 (Offset 0x16B8) */
-
-#define BIT_SHIFT_TA3 0
-#define BIT_MASK_TA3 0xffffffffffffL
-#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3)
-#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3)
-
-/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */
-
-#define BIT_SHIFT_TA4 0
-#define BIT_MASK_TA4 0xffffffffffffL
-#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4)
-#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4)
-
-/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */
-
-#define BIT_LTECOEX_ACCESS_START_V1 BIT(31)
-#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30)
-#define BIT_LTECOEX_READY_BIT_V1 BIT(29)
-
-#define BIT_SHIFT_WRITE_BYTE_EN_V1 16
-#define BIT_MASK_WRITE_BYTE_EN_V1 0xf
-#define BIT_WRITE_BYTE_EN_V1(x) \
- (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1)
-#define BIT_GET_WRITE_BYTE_EN_V1(x) \
- (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1)
-
-#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0
-#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff
-#define BIT_LTECOEX_REG_ADDR_V1(x) \
- (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1)
-#define BIT_GET_LTECOEX_REG_ADDR_V1(x) \
- (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1)
-
-/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */
-
-#define BIT_SHIFT_LTECOEX_W_DATA_V1 0
-#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL
-#define BIT_LTECOEX_W_DATA_V1(x) \
- (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1)
-#define BIT_GET_LTECOEX_W_DATA_V1(x) \
- (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1)
-
-/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */
-
-#define BIT_SHIFT_LTECOEX_R_DATA_V1 0
-#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL
-#define BIT_LTECOEX_R_DATA_V1(x) \
- (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1)
-#define BIT_GET_LTECOEX_R_DATA_V1(x) \
- (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1)
-
-#endif /* __RTL_WLAN_BITDEF_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __INC_HALMAC_BIT_8822B_H
-#define __INC_HALMAC_BIT_8822B_H
-
-#define CPU_OPT_WIDTH 0x1F
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_SYS_ISO_CTRL_8822B */
-#define BIT_PWC_EV12V_8822B BIT(15)
-#define BIT_PWC_EV25V_8822B BIT(14)
-#define BIT_PA33V_EN_8822B BIT(13)
-#define BIT_PA12V_EN_8822B BIT(12)
-#define BIT_UA33V_EN_8822B BIT(11)
-#define BIT_UA12V_EN_8822B BIT(10)
-#define BIT_ISO_RFDIO_8822B BIT(9)
-#define BIT_ISO_EB2CORE_8822B BIT(8)
-#define BIT_ISO_DIOE_8822B BIT(7)
-#define BIT_ISO_WLPON2PP_8822B BIT(6)
-#define BIT_ISO_IP2MAC_WA2PP_8822B BIT(5)
-#define BIT_ISO_PD2CORE_8822B BIT(4)
-#define BIT_ISO_PA2PCIE_8822B BIT(3)
-#define BIT_ISO_UD2CORE_8822B BIT(2)
-#define BIT_ISO_UA2USB_8822B BIT(1)
-#define BIT_ISO_WD2PP_8822B BIT(0)
-
-/* 2 REG_SYS_FUNC_EN_8822B */
-#define BIT_FEN_MREGEN_8822B BIT(15)
-#define BIT_FEN_HWPDN_8822B BIT(14)
-#define BIT_EN_25_1_8822B BIT(13)
-#define BIT_FEN_ELDR_8822B BIT(12)
-#define BIT_FEN_DCORE_8822B BIT(11)
-#define BIT_FEN_CPUEN_8822B BIT(10)
-#define BIT_FEN_DIOE_8822B BIT(9)
-#define BIT_FEN_PCIED_8822B BIT(8)
-#define BIT_FEN_PPLL_8822B BIT(7)
-#define BIT_FEN_PCIEA_8822B BIT(6)
-#define BIT_FEN_DIO_PCIE_8822B BIT(5)
-#define BIT_FEN_USBD_8822B BIT(4)
-#define BIT_FEN_UPLL_8822B BIT(3)
-#define BIT_FEN_USBA_8822B BIT(2)
-#define BIT_FEN_BB_GLB_RSTN_8822B BIT(1)
-#define BIT_FEN_BBRSTB_8822B BIT(0)
-
-/* 2 REG_SYS_PW_CTRL_8822B */
-#define BIT_SOP_EABM_8822B BIT(31)
-#define BIT_SOP_ACKF_8822B BIT(30)
-#define BIT_SOP_ERCK_8822B BIT(29)
-#define BIT_SOP_ESWR_8822B BIT(28)
-#define BIT_SOP_PWMM_8822B BIT(27)
-#define BIT_SOP_EECK_8822B BIT(26)
-#define BIT_SOP_EXTL_8822B BIT(24)
-#define BIT_SYM_OP_RING_12M_8822B BIT(22)
-#define BIT_ROP_SWPR_8822B BIT(21)
-#define BIT_DIS_HW_LPLDM_8822B BIT(20)
-#define BIT_OPT_SWRST_WLMCU_8822B BIT(19)
-#define BIT_RDY_SYSPWR_8822B BIT(17)
-#define BIT_EN_WLON_8822B BIT(16)
-#define BIT_APDM_HPDN_8822B BIT(15)
-#define BIT_AFSM_PCIE_SUS_EN_8822B BIT(12)
-#define BIT_AFSM_WLSUS_EN_8822B BIT(11)
-#define BIT_APFM_SWLPS_8822B BIT(10)
-#define BIT_APFM_OFFMAC_8822B BIT(9)
-#define BIT_APFN_ONMAC_8822B BIT(8)
-#define BIT_CHIP_PDN_EN_8822B BIT(7)
-#define BIT_RDY_MACDIS_8822B BIT(6)
-#define BIT_RING_CLK_12M_EN_8822B BIT(4)
-#define BIT_PFM_WOWL_8822B BIT(3)
-#define BIT_PFM_LDKP_8822B BIT(2)
-#define BIT_WL_HCI_ALD_8822B BIT(1)
-#define BIT_PFM_LDALL_8822B BIT(0)
-
-/* 2 REG_SYS_CLK_CTRL_8822B */
-#define BIT_LDO_DUMMY_8822B BIT(15)
-#define BIT_CPU_CLK_EN_8822B BIT(14)
-#define BIT_SYMREG_CLK_EN_8822B BIT(13)
-#define BIT_HCI_CLK_EN_8822B BIT(12)
-#define BIT_MAC_CLK_EN_8822B BIT(11)
-#define BIT_SEC_CLK_EN_8822B BIT(10)
-#define BIT_PHY_SSC_RSTB_8822B BIT(9)
-#define BIT_EXT_32K_EN_8822B BIT(8)
-#define BIT_WL_CLK_TEST_8822B BIT(7)
-#define BIT_OP_SPS_PWM_EN_8822B BIT(6)
-#define BIT_LOADER_CLK_EN_8822B BIT(5)
-#define BIT_MACSLP_8822B BIT(4)
-#define BIT_WAKEPAD_EN_8822B BIT(3)
-#define BIT_ROMD16V_EN_8822B BIT(2)
-#define BIT_CKANA12M_EN_8822B BIT(1)
-#define BIT_CNTD16V_EN_8822B BIT(0)
-
-/* 2 REG_SYS_EEPROM_CTRL_8822B */
-
-#define BIT_SHIFT_VPDIDX_8822B 8
-#define BIT_MASK_VPDIDX_8822B 0xff
-#define BIT_VPDIDX_8822B(x) \
- (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B)
-#define BIT_GET_VPDIDX_8822B(x) \
- (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B)
-
-#define BIT_SHIFT_EEM1_0_8822B 6
-#define BIT_MASK_EEM1_0_8822B 0x3
-#define BIT_EEM1_0_8822B(x) \
- (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B)
-#define BIT_GET_EEM1_0_8822B(x) \
- (((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B)
-
-#define BIT_AUTOLOAD_SUS_8822B BIT(5)
-#define BIT_EERPOMSEL_8822B BIT(4)
-#define BIT_EECS_V1_8822B BIT(3)
-#define BIT_EESK_V1_8822B BIT(2)
-#define BIT_EEDI_V1_8822B BIT(1)
-#define BIT_EEDO_V1_8822B BIT(0)
-
-/* 2 REG_EE_VPD_8822B */
-
-#define BIT_SHIFT_VPD_DATA_8822B 0
-#define BIT_MASK_VPD_DATA_8822B 0xffffffffL
-#define BIT_VPD_DATA_8822B(x) \
- (((x) & BIT_MASK_VPD_DATA_8822B) << BIT_SHIFT_VPD_DATA_8822B)
-#define BIT_GET_VPD_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B)
-
-/* 2 REG_SYS_SWR_CTRL1_8822B */
-#define BIT_C2_L_BIT0_8822B BIT(31)
-
-#define BIT_SHIFT_C1_L_8822B 29
-#define BIT_MASK_C1_L_8822B 0x3
-#define BIT_C1_L_8822B(x) (((x) & BIT_MASK_C1_L_8822B) << BIT_SHIFT_C1_L_8822B)
-#define BIT_GET_C1_L_8822B(x) \
- (((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B)
-
-#define BIT_SHIFT_REG_FREQ_L_8822B 25
-#define BIT_MASK_REG_FREQ_L_8822B 0x7
-#define BIT_REG_FREQ_L_8822B(x) \
- (((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B)
-#define BIT_GET_REG_FREQ_L_8822B(x) \
- (((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B)
-
-#define BIT_REG_EN_DUTY_8822B BIT(24)
-
-#define BIT_SHIFT_REG_MODE_8822B 22
-#define BIT_MASK_REG_MODE_8822B 0x3
-#define BIT_REG_MODE_8822B(x) \
- (((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B)
-#define BIT_GET_REG_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B)
-
-#define BIT_REG_EN_SP_8822B BIT(21)
-#define BIT_REG_AUTO_L_8822B BIT(20)
-#define BIT_SW18_SELD_BIT0_8822B BIT(19)
-#define BIT_SW18_POWOCP_8822B BIT(18)
-
-#define BIT_SHIFT_OCP_L1_8822B 15
-#define BIT_MASK_OCP_L1_8822B 0x7
-#define BIT_OCP_L1_8822B(x) \
- (((x) & BIT_MASK_OCP_L1_8822B) << BIT_SHIFT_OCP_L1_8822B)
-#define BIT_GET_OCP_L1_8822B(x) \
- (((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B)
-
-#define BIT_SHIFT_CF_L_8822B 13
-#define BIT_MASK_CF_L_8822B 0x3
-#define BIT_CF_L_8822B(x) (((x) & BIT_MASK_CF_L_8822B) << BIT_SHIFT_CF_L_8822B)
-#define BIT_GET_CF_L_8822B(x) \
- (((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B)
-
-#define BIT_SW18_FPWM_8822B BIT(11)
-#define BIT_SW18_SWEN_8822B BIT(9)
-#define BIT_SW18_LDEN_8822B BIT(8)
-#define BIT_MAC_ID_EN_8822B BIT(7)
-#define BIT_AFE_BGEN_8822B BIT(0)
-
-/* 2 REG_SYS_SWR_CTRL2_8822B */
-#define BIT_POW_ZCD_L_8822B BIT(31)
-#define BIT_AUTOZCD_L_8822B BIT(30)
-
-#define BIT_SHIFT_REG_DELAY_8822B 28
-#define BIT_MASK_REG_DELAY_8822B 0x3
-#define BIT_REG_DELAY_8822B(x) \
- (((x) & BIT_MASK_REG_DELAY_8822B) << BIT_SHIFT_REG_DELAY_8822B)
-#define BIT_GET_REG_DELAY_8822B(x) \
- (((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B)
-
-#define BIT_SHIFT_V15ADJ_L1_V1_8822B 24
-#define BIT_MASK_V15ADJ_L1_V1_8822B 0x7
-#define BIT_V15ADJ_L1_V1_8822B(x) \
- (((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B)
-#define BIT_GET_V15ADJ_L1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B)
-
-#define BIT_SHIFT_VOL_L1_V1_8822B 20
-#define BIT_MASK_VOL_L1_V1_8822B 0xf
-#define BIT_VOL_L1_V1_8822B(x) \
- (((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B)
-#define BIT_GET_VOL_L1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B)
-
-#define BIT_SHIFT_IN_L1_V1_8822B 17
-#define BIT_MASK_IN_L1_V1_8822B 0x7
-#define BIT_IN_L1_V1_8822B(x) \
- (((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B)
-#define BIT_GET_IN_L1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B)
-
-#define BIT_SHIFT_TBOX_L1_8822B 15
-#define BIT_MASK_TBOX_L1_8822B 0x3
-#define BIT_TBOX_L1_8822B(x) \
- (((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B)
-#define BIT_GET_TBOX_L1_8822B(x) \
- (((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B)
-
-#define BIT_SW18_SEL_8822B BIT(13)
-
-/* 2 REG_NOT_VALID_8822B */
-#define BIT_SW18_SD_8822B BIT(10)
-
-#define BIT_SHIFT_R3_L_8822B 7
-#define BIT_MASK_R3_L_8822B 0x3
-#define BIT_R3_L_8822B(x) (((x) & BIT_MASK_R3_L_8822B) << BIT_SHIFT_R3_L_8822B)
-#define BIT_GET_R3_L_8822B(x) \
- (((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B)
-
-#define BIT_SHIFT_SW18_R2_8822B 5
-#define BIT_MASK_SW18_R2_8822B 0x3
-#define BIT_SW18_R2_8822B(x) \
- (((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B)
-#define BIT_GET_SW18_R2_8822B(x) \
- (((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B)
-
-#define BIT_SHIFT_SW18_R1_8822B 3
-#define BIT_MASK_SW18_R1_8822B 0x3
-#define BIT_SW18_R1_8822B(x) \
- (((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B)
-#define BIT_GET_SW18_R1_8822B(x) \
- (((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B)
-
-#define BIT_SHIFT_C3_L_C3_8822B 1
-#define BIT_MASK_C3_L_C3_8822B 0x3
-#define BIT_C3_L_C3_8822B(x) \
- (((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B)
-#define BIT_GET_C3_L_C3_8822B(x) \
- (((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B)
-
-#define BIT_C2_L_BIT1_8822B BIT(0)
-
-/* 2 REG_SYS_SWR_CTRL3_8822B */
-#define BIT_SPS18_OCP_DIS_8822B BIT(31)
-
-#define BIT_SHIFT_SPS18_OCP_TH_8822B 16
-#define BIT_MASK_SPS18_OCP_TH_8822B 0x7fff
-#define BIT_SPS18_OCP_TH_8822B(x) \
- (((x) & BIT_MASK_SPS18_OCP_TH_8822B) << BIT_SHIFT_SPS18_OCP_TH_8822B)
-#define BIT_GET_SPS18_OCP_TH_8822B(x) \
- (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B)
-
-#define BIT_SHIFT_OCP_WINDOW_8822B 0
-#define BIT_MASK_OCP_WINDOW_8822B 0xffff
-#define BIT_OCP_WINDOW_8822B(x) \
- (((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B)
-#define BIT_GET_OCP_WINDOW_8822B(x) \
- (((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B)
-
-/* 2 REG_RSV_CTRL_8822B */
-#define BIT_HREG_DBG_8822B BIT(23)
-#define BIT_WLMCUIOIF_8822B BIT(8)
-#define BIT_LOCK_ALL_EN_8822B BIT(7)
-#define BIT_R_DIS_PRST_8822B BIT(6)
-#define BIT_WLOCK_1C_B6_8822B BIT(5)
-#define BIT_WLOCK_40_8822B BIT(4)
-#define BIT_WLOCK_08_8822B BIT(3)
-#define BIT_WLOCK_04_8822B BIT(2)
-#define BIT_WLOCK_00_8822B BIT(1)
-#define BIT_WLOCK_ALL_8822B BIT(0)
-
-/* 2 REG_RF_CTRL_8822B */
-#define BIT_RF_SDMRSTB_8822B BIT(2)
-#define BIT_RF_RSTB_8822B BIT(1)
-#define BIT_RF_EN_8822B BIT(0)
-
-/* 2 REG_AFE_LDO_CTRL_8822B */
-
-#define BIT_SHIFT_LPLDH12_RSV_8822B 29
-#define BIT_MASK_LPLDH12_RSV_8822B 0x7
-#define BIT_LPLDH12_RSV_8822B(x) \
- (((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B)
-#define BIT_GET_LPLDH12_RSV_8822B(x) \
- (((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B)
-
-#define BIT_LPLDH12_SLP_8822B BIT(28)
-
-#define BIT_SHIFT_LPLDH12_VADJ_8822B 24
-#define BIT_MASK_LPLDH12_VADJ_8822B 0xf
-#define BIT_LPLDH12_VADJ_8822B(x) \
- (((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B)
-#define BIT_GET_LPLDH12_VADJ_8822B(x) \
- (((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B)
-
-#define BIT_LDH12_EN_8822B BIT(16)
-#define BIT_WLBBOFF_BIG_PWC_EN_8822B BIT(14)
-#define BIT_WLBBOFF_SMALL_PWC_EN_8822B BIT(13)
-#define BIT_WLMACOFF_BIG_PWC_EN_8822B BIT(12)
-#define BIT_WLPON_PWC_EN_8822B BIT(11)
-#define BIT_POW_REGU_P1_8822B BIT(10)
-#define BIT_LDOV12W_EN_8822B BIT(8)
-#define BIT_EX_XTAL_DRV_DIGI_8822B BIT(7)
-#define BIT_EX_XTAL_DRV_USB_8822B BIT(6)
-#define BIT_EX_XTAL_DRV_AFE_8822B BIT(5)
-#define BIT_EX_XTAL_DRV_RF2_8822B BIT(4)
-#define BIT_EX_XTAL_DRV_RF1_8822B BIT(3)
-#define BIT_POW_REGU_P0_8822B BIT(2)
-
-/* 2 REG_NOT_VALID_8822B */
-#define BIT_POW_PLL_LDO_8822B BIT(0)
-
-/* 2 REG_AFE_CTRL1_8822B */
-#define BIT_AGPIO_GPE_8822B BIT(31)
-
-#define BIT_SHIFT_XTAL_CAP_XI_8822B 25
-#define BIT_MASK_XTAL_CAP_XI_8822B 0x3f
-#define BIT_XTAL_CAP_XI_8822B(x) \
- (((x) & BIT_MASK_XTAL_CAP_XI_8822B) << BIT_SHIFT_XTAL_CAP_XI_8822B)
-#define BIT_GET_XTAL_CAP_XI_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B)
-
-#define BIT_SHIFT_XTAL_DRV_DIGI_8822B 23
-#define BIT_MASK_XTAL_DRV_DIGI_8822B 0x3
-#define BIT_XTAL_DRV_DIGI_8822B(x) \
- (((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B)
-#define BIT_GET_XTAL_DRV_DIGI_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B)
-
-#define BIT_XTAL_DRV_USB_BIT1_8822B BIT(22)
-
-#define BIT_SHIFT_MAC_CLK_SEL_8822B 20
-#define BIT_MASK_MAC_CLK_SEL_8822B 0x3
-#define BIT_MAC_CLK_SEL_8822B(x) \
- (((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B)
-#define BIT_GET_MAC_CLK_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B)
-
-#define BIT_XTAL_DRV_USB_BIT0_8822B BIT(19)
-
-#define BIT_SHIFT_XTAL_DRV_AFE_8822B 17
-#define BIT_MASK_XTAL_DRV_AFE_8822B 0x3
-#define BIT_XTAL_DRV_AFE_8822B(x) \
- (((x) & BIT_MASK_XTAL_DRV_AFE_8822B) << BIT_SHIFT_XTAL_DRV_AFE_8822B)
-#define BIT_GET_XTAL_DRV_AFE_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B)
-
-#define BIT_SHIFT_XTAL_DRV_RF2_8822B 15
-#define BIT_MASK_XTAL_DRV_RF2_8822B 0x3
-#define BIT_XTAL_DRV_RF2_8822B(x) \
- (((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B)
-#define BIT_GET_XTAL_DRV_RF2_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B)
-
-#define BIT_SHIFT_XTAL_DRV_RF1_8822B 13
-#define BIT_MASK_XTAL_DRV_RF1_8822B 0x3
-#define BIT_XTAL_DRV_RF1_8822B(x) \
- (((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B)
-#define BIT_GET_XTAL_DRV_RF1_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B)
-
-#define BIT_XTAL_DELAY_DIGI_8822B BIT(12)
-#define BIT_XTAL_DELAY_USB_8822B BIT(11)
-#define BIT_XTAL_DELAY_AFE_8822B BIT(10)
-
-#define BIT_SHIFT_XTAL_LDO_VREF_8822B 7
-#define BIT_MASK_XTAL_LDO_VREF_8822B 0x7
-#define BIT_XTAL_LDO_VREF_8822B(x) \
- (((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B)
-#define BIT_GET_XTAL_LDO_VREF_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B)
-
-#define BIT_XTAL_XQSEL_RF_8822B BIT(6)
-#define BIT_XTAL_XQSEL_8822B BIT(5)
-
-#define BIT_SHIFT_XTAL_GMN_V2_8822B 3
-#define BIT_MASK_XTAL_GMN_V2_8822B 0x3
-#define BIT_XTAL_GMN_V2_8822B(x) \
- (((x) & BIT_MASK_XTAL_GMN_V2_8822B) << BIT_SHIFT_XTAL_GMN_V2_8822B)
-#define BIT_GET_XTAL_GMN_V2_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B)
-
-#define BIT_SHIFT_XTAL_GMP_V2_8822B 1
-#define BIT_MASK_XTAL_GMP_V2_8822B 0x3
-#define BIT_XTAL_GMP_V2_8822B(x) \
- (((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B)
-#define BIT_GET_XTAL_GMP_V2_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B)
-
-#define BIT_XTAL_EN_8822B BIT(0)
-
-/* 2 REG_AFE_CTRL2_8822B */
-
-#define BIT_SHIFT_REG_C3_V4_8822B 30
-#define BIT_MASK_REG_C3_V4_8822B 0x3
-#define BIT_REG_C3_V4_8822B(x) \
- (((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B)
-#define BIT_GET_REG_C3_V4_8822B(x) \
- (((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B)
-
-#define BIT_REG_CP_BIT1_8822B BIT(29)
-
-#define BIT_SHIFT_REG_RS_V4_8822B 26
-#define BIT_MASK_REG_RS_V4_8822B 0x7
-#define BIT_REG_RS_V4_8822B(x) \
- (((x) & BIT_MASK_REG_RS_V4_8822B) << BIT_SHIFT_REG_RS_V4_8822B)
-#define BIT_GET_REG_RS_V4_8822B(x) \
- (((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B)
-
-#define BIT_SHIFT_REG__CS_8822B 24
-#define BIT_MASK_REG__CS_8822B 0x3
-#define BIT_REG__CS_8822B(x) \
- (((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B)
-#define BIT_GET_REG__CS_8822B(x) \
- (((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B)
-
-#define BIT_SHIFT_REG_CP_OFFSET_8822B 21
-#define BIT_MASK_REG_CP_OFFSET_8822B 0x7
-#define BIT_REG_CP_OFFSET_8822B(x) \
- (((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B)
-#define BIT_GET_REG_CP_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B)
-
-#define BIT_SHIFT_CP_BIAS_8822B 18
-#define BIT_MASK_CP_BIAS_8822B 0x7
-#define BIT_CP_BIAS_8822B(x) \
- (((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B)
-#define BIT_GET_CP_BIAS_8822B(x) \
- (((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B)
-
-#define BIT_REG_IDOUBLE_V2_8822B BIT(17)
-#define BIT_EN_SYN_8822B BIT(16)
-
-#define BIT_SHIFT_MCCO_8822B 14
-#define BIT_MASK_MCCO_8822B 0x3
-#define BIT_MCCO_8822B(x) (((x) & BIT_MASK_MCCO_8822B) << BIT_SHIFT_MCCO_8822B)
-#define BIT_GET_MCCO_8822B(x) \
- (((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B)
-
-#define BIT_SHIFT_REG_LDO_SEL_8822B 12
-#define BIT_MASK_REG_LDO_SEL_8822B 0x3
-#define BIT_REG_LDO_SEL_8822B(x) \
- (((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B)
-#define BIT_GET_REG_LDO_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B)
-
-#define BIT_REG_KVCO_V2_8822B BIT(10)
-#define BIT_AGPIO_GPO_8822B BIT(9)
-
-#define BIT_SHIFT_AGPIO_DRV_8822B 7
-#define BIT_MASK_AGPIO_DRV_8822B 0x3
-#define BIT_AGPIO_DRV_8822B(x) \
- (((x) & BIT_MASK_AGPIO_DRV_8822B) << BIT_SHIFT_AGPIO_DRV_8822B)
-#define BIT_GET_AGPIO_DRV_8822B(x) \
- (((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B)
-
-#define BIT_SHIFT_XTAL_CAP_XO_8822B 1
-#define BIT_MASK_XTAL_CAP_XO_8822B 0x3f
-#define BIT_XTAL_CAP_XO_8822B(x) \
- (((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B)
-#define BIT_GET_XTAL_CAP_XO_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B)
-
-#define BIT_POW_PLL_8822B BIT(0)
-
-/* 2 REG_AFE_CTRL3_8822B */
-
-#define BIT_SHIFT_PS_8822B 7
-#define BIT_MASK_PS_8822B 0x7
-#define BIT_PS_8822B(x) (((x) & BIT_MASK_PS_8822B) << BIT_SHIFT_PS_8822B)
-#define BIT_GET_PS_8822B(x) (((x) >> BIT_SHIFT_PS_8822B) & BIT_MASK_PS_8822B)
-
-#define BIT_PSEN_8822B BIT(6)
-#define BIT_DOGENB_8822B BIT(5)
-#define BIT_REG_MBIAS_8822B BIT(4)
-
-#define BIT_SHIFT_REG_R3_V4_8822B 1
-#define BIT_MASK_REG_R3_V4_8822B 0x7
-#define BIT_REG_R3_V4_8822B(x) \
- (((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B)
-#define BIT_GET_REG_R3_V4_8822B(x) \
- (((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B)
-
-#define BIT_REG_CP_BIT0_8822B BIT(0)
-
-/* 2 REG_EFUSE_CTRL_8822B */
-#define BIT_EF_FLAG_8822B BIT(31)
-
-#define BIT_SHIFT_EF_PGPD_8822B 28
-#define BIT_MASK_EF_PGPD_8822B 0x7
-#define BIT_EF_PGPD_8822B(x) \
- (((x) & BIT_MASK_EF_PGPD_8822B) << BIT_SHIFT_EF_PGPD_8822B)
-#define BIT_GET_EF_PGPD_8822B(x) \
- (((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B)
-
-#define BIT_SHIFT_EF_RDT_8822B 24
-#define BIT_MASK_EF_RDT_8822B 0xf
-#define BIT_EF_RDT_8822B(x) \
- (((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B)
-#define BIT_GET_EF_RDT_8822B(x) \
- (((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B)
-
-#define BIT_SHIFT_EF_PGTS_8822B 20
-#define BIT_MASK_EF_PGTS_8822B 0xf
-#define BIT_EF_PGTS_8822B(x) \
- (((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B)
-#define BIT_GET_EF_PGTS_8822B(x) \
- (((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B)
-
-#define BIT_EF_PDWN_8822B BIT(19)
-#define BIT_EF_ALDEN_8822B BIT(18)
-
-#define BIT_SHIFT_EF_ADDR_8822B 8
-#define BIT_MASK_EF_ADDR_8822B 0x3ff
-#define BIT_EF_ADDR_8822B(x) \
- (((x) & BIT_MASK_EF_ADDR_8822B) << BIT_SHIFT_EF_ADDR_8822B)
-#define BIT_GET_EF_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B)
-
-#define BIT_SHIFT_EF_DATA_8822B 0
-#define BIT_MASK_EF_DATA_8822B 0xff
-#define BIT_EF_DATA_8822B(x) \
- (((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B)
-#define BIT_GET_EF_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B)
-
-/* 2 REG_LDO_EFUSE_CTRL_8822B */
-#define BIT_LDOE25_EN_8822B BIT(31)
-
-#define BIT_SHIFT_LDOE25_V12ADJ_L_8822B 27
-#define BIT_MASK_LDOE25_V12ADJ_L_8822B 0xf
-#define BIT_LDOE25_V12ADJ_L_8822B(x) \
- (((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B) \
- << BIT_SHIFT_LDOE25_V12ADJ_L_8822B)
-#define BIT_GET_LDOE25_V12ADJ_L_8822B(x) \
- (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) & \
- BIT_MASK_LDOE25_V12ADJ_L_8822B)
-
-#define BIT_EF_CRES_SEL_8822B BIT(26)
-
-#define BIT_SHIFT_EF_SCAN_START_V1_8822B 16
-#define BIT_MASK_EF_SCAN_START_V1_8822B 0x3ff
-#define BIT_EF_SCAN_START_V1_8822B(x) \
- (((x) & BIT_MASK_EF_SCAN_START_V1_8822B) \
- << BIT_SHIFT_EF_SCAN_START_V1_8822B)
-#define BIT_GET_EF_SCAN_START_V1_8822B(x) \
- (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) & \
- BIT_MASK_EF_SCAN_START_V1_8822B)
-
-#define BIT_SHIFT_EF_SCAN_END_8822B 12
-#define BIT_MASK_EF_SCAN_END_8822B 0xf
-#define BIT_EF_SCAN_END_8822B(x) \
- (((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B)
-#define BIT_GET_EF_SCAN_END_8822B(x) \
- (((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B)
-
-#define BIT_EF_PD_DIS_8822B BIT(11)
-
-#define BIT_SHIFT_EF_CELL_SEL_8822B 8
-#define BIT_MASK_EF_CELL_SEL_8822B 0x3
-#define BIT_EF_CELL_SEL_8822B(x) \
- (((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B)
-#define BIT_GET_EF_CELL_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B)
-
-#define BIT_EF_TRPT_8822B BIT(7)
-
-#define BIT_SHIFT_EF_TTHD_8822B 0
-#define BIT_MASK_EF_TTHD_8822B 0x7f
-#define BIT_EF_TTHD_8822B(x) \
- (((x) & BIT_MASK_EF_TTHD_8822B) << BIT_SHIFT_EF_TTHD_8822B)
-#define BIT_GET_EF_TTHD_8822B(x) \
- (((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B)
-
-/* 2 REG_PWR_OPTION_CTRL_8822B */
-
-#define BIT_SHIFT_DBG_SEL_V1_8822B 16
-#define BIT_MASK_DBG_SEL_V1_8822B 0xff
-#define BIT_DBG_SEL_V1_8822B(x) \
- (((x) & BIT_MASK_DBG_SEL_V1_8822B) << BIT_SHIFT_DBG_SEL_V1_8822B)
-#define BIT_GET_DBG_SEL_V1_8822B(x) \
- (((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B)
-
-#define BIT_SHIFT_DBG_SEL_BYTE_8822B 14
-#define BIT_MASK_DBG_SEL_BYTE_8822B 0x3
-#define BIT_DBG_SEL_BYTE_8822B(x) \
- (((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B)
-#define BIT_GET_DBG_SEL_BYTE_8822B(x) \
- (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B)
-
-#define BIT_SHIFT_STD_L1_V1_8822B 12
-#define BIT_MASK_STD_L1_V1_8822B 0x3
-#define BIT_STD_L1_V1_8822B(x) \
- (((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B)
-#define BIT_GET_STD_L1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B)
-
-#define BIT_SYSON_DBG_PAD_E2_8822B BIT(11)
-#define BIT_SYSON_LED_PAD_E2_8822B BIT(10)
-#define BIT_SYSON_GPEE_PAD_E2_8822B BIT(9)
-#define BIT_SYSON_PCI_PAD_E2_8822B BIT(8)
-#define BIT_AUTO_SW_LDO_VOL_EN_8822B BIT(7)
-
-#define BIT_SHIFT_SYSON_SPS0WWV_WT_8822B 4
-#define BIT_MASK_SYSON_SPS0WWV_WT_8822B 0x3
-#define BIT_SYSON_SPS0WWV_WT_8822B(x) \
- (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) \
- << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B)
-#define BIT_GET_SYSON_SPS0WWV_WT_8822B(x) \
- (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) & \
- BIT_MASK_SYSON_SPS0WWV_WT_8822B)
-
-#define BIT_SHIFT_SYSON_SPS0LDO_WT_8822B 2
-#define BIT_MASK_SYSON_SPS0LDO_WT_8822B 0x3
-#define BIT_SYSON_SPS0LDO_WT_8822B(x) \
- (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) \
- << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B)
-#define BIT_GET_SYSON_SPS0LDO_WT_8822B(x) \
- (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) & \
- BIT_MASK_SYSON_SPS0LDO_WT_8822B)
-
-#define BIT_SHIFT_SYSON_RCLK_SCALE_8822B 0
-#define BIT_MASK_SYSON_RCLK_SCALE_8822B 0x3
-#define BIT_SYSON_RCLK_SCALE_8822B(x) \
- (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B) \
- << BIT_SHIFT_SYSON_RCLK_SCALE_8822B)
-#define BIT_GET_SYSON_RCLK_SCALE_8822B(x) \
- (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) & \
- BIT_MASK_SYSON_RCLK_SCALE_8822B)
-
-/* 2 REG_CAL_TIMER_8822B */
-
-#define BIT_SHIFT_MATCH_CNT_8822B 8
-#define BIT_MASK_MATCH_CNT_8822B 0xff
-#define BIT_MATCH_CNT_8822B(x) \
- (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)
-#define BIT_GET_MATCH_CNT_8822B(x) \
- (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)
-
-#define BIT_SHIFT_CAL_SCAL_8822B 0
-#define BIT_MASK_CAL_SCAL_8822B 0xff
-#define BIT_CAL_SCAL_8822B(x) \
- (((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B)
-#define BIT_GET_CAL_SCAL_8822B(x) \
- (((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B)
-
-/* 2 REG_ACLK_MON_8822B */
-
-#define BIT_SHIFT_RCLK_MON_8822B 5
-#define BIT_MASK_RCLK_MON_8822B 0x7ff
-#define BIT_RCLK_MON_8822B(x) \
- (((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B)
-#define BIT_GET_RCLK_MON_8822B(x) \
- (((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B)
-
-#define BIT_CAL_EN_8822B BIT(4)
-
-#define BIT_SHIFT_DPSTU_8822B 2
-#define BIT_MASK_DPSTU_8822B 0x3
-#define BIT_DPSTU_8822B(x) \
- (((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B)
-#define BIT_GET_DPSTU_8822B(x) \
- (((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B)
-
-#define BIT_SUS_16X_8822B BIT(1)
-
-/* 2 REG_GPIO_MUXCFG_8822B */
-#define BIT_FSPI_EN_8822B BIT(19)
-#define BIT_WL_RTS_EXT_32K_SEL_8822B BIT(18)
-#define BIT_WLGP_SPI_EN_8822B BIT(16)
-#define BIT_SIC_LBK_8822B BIT(15)
-#define BIT_ENHTP_8822B BIT(14)
-#define BIT_ENSIC_8822B BIT(12)
-#define BIT_SIC_SWRST_8822B BIT(11)
-#define BIT_PO_WIFI_PTA_PINS_8822B BIT(10)
-#define BIT_PO_BT_PTA_PINS_8822B BIT(9)
-#define BIT_ENUART_8822B BIT(8)
-
-#define BIT_SHIFT_BTMODE_8822B 6
-#define BIT_MASK_BTMODE_8822B 0x3
-#define BIT_BTMODE_8822B(x) \
- (((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B)
-#define BIT_GET_BTMODE_8822B(x) \
- (((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B)
-
-#define BIT_ENBT_8822B BIT(5)
-#define BIT_EROM_EN_8822B BIT(4)
-#define BIT_WLRFE_6_7_EN_8822B BIT(3)
-#define BIT_WLRFE_4_5_EN_8822B BIT(2)
-
-#define BIT_SHIFT_GPIOSEL_8822B 0
-#define BIT_MASK_GPIOSEL_8822B 0x3
-#define BIT_GPIOSEL_8822B(x) \
- (((x) & BIT_MASK_GPIOSEL_8822B) << BIT_SHIFT_GPIOSEL_8822B)
-#define BIT_GET_GPIOSEL_8822B(x) \
- (((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B)
-
-/* 2 REG_GPIO_PIN_CTRL_8822B */
-
-#define BIT_SHIFT_GPIO_MOD_7_TO_0_8822B 24
-#define BIT_MASK_GPIO_MOD_7_TO_0_8822B 0xff
-#define BIT_GPIO_MOD_7_TO_0_8822B(x) \
- (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) \
- << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B)
-#define BIT_GET_GPIO_MOD_7_TO_0_8822B(x) \
- (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) & \
- BIT_MASK_GPIO_MOD_7_TO_0_8822B)
-
-#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B 16
-#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B 0xff
-#define BIT_GPIO_IO_SEL_7_TO_0_8822B(x) \
- (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) \
- << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B)
-#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x) \
- (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) & \
- BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B)
-
-#define BIT_SHIFT_GPIO_OUT_7_TO_0_8822B 8
-#define BIT_MASK_GPIO_OUT_7_TO_0_8822B 0xff
-#define BIT_GPIO_OUT_7_TO_0_8822B(x) \
- (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) \
- << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B)
-#define BIT_GET_GPIO_OUT_7_TO_0_8822B(x) \
- (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) & \
- BIT_MASK_GPIO_OUT_7_TO_0_8822B)
-
-#define BIT_SHIFT_GPIO_IN_7_TO_0_8822B 0
-#define BIT_MASK_GPIO_IN_7_TO_0_8822B 0xff
-#define BIT_GPIO_IN_7_TO_0_8822B(x) \
- (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B) \
- << BIT_SHIFT_GPIO_IN_7_TO_0_8822B)
-#define BIT_GET_GPIO_IN_7_TO_0_8822B(x) \
- (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) & \
- BIT_MASK_GPIO_IN_7_TO_0_8822B)
-
-/* 2 REG_GPIO_INTM_8822B */
-
-#define BIT_SHIFT_MUXDBG_SEL_8822B 30
-#define BIT_MASK_MUXDBG_SEL_8822B 0x3
-#define BIT_MUXDBG_SEL_8822B(x) \
- (((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B)
-#define BIT_GET_MUXDBG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B)
-
-#define BIT_EXTWOL_SEL_8822B BIT(17)
-#define BIT_EXTWOL_EN_8822B BIT(16)
-#define BIT_GPIOF_INT_MD_8822B BIT(15)
-#define BIT_GPIOE_INT_MD_8822B BIT(14)
-#define BIT_GPIOD_INT_MD_8822B BIT(13)
-#define BIT_GPIOF_INT_MD_8822B BIT(15)
-#define BIT_GPIOE_INT_MD_8822B BIT(14)
-#define BIT_GPIOD_INT_MD_8822B BIT(13)
-#define BIT_GPIOC_INT_MD_8822B BIT(12)
-#define BIT_GPIOB_INT_MD_8822B BIT(11)
-#define BIT_GPIOA_INT_MD_8822B BIT(10)
-#define BIT_GPIO9_INT_MD_8822B BIT(9)
-#define BIT_GPIO8_INT_MD_8822B BIT(8)
-#define BIT_GPIO7_INT_MD_8822B BIT(7)
-#define BIT_GPIO6_INT_MD_8822B BIT(6)
-#define BIT_GPIO5_INT_MD_8822B BIT(5)
-#define BIT_GPIO4_INT_MD_8822B BIT(4)
-#define BIT_GPIO3_INT_MD_8822B BIT(3)
-#define BIT_GPIO2_INT_MD_8822B BIT(2)
-#define BIT_GPIO1_INT_MD_8822B BIT(1)
-#define BIT_GPIO0_INT_MD_8822B BIT(0)
-
-/* 2 REG_LED_CFG_8822B */
-#define BIT_GPIO3_WL_CTRL_EN_8822B BIT(27)
-#define BIT_LNAON_SEL_EN_8822B BIT(26)
-#define BIT_PAPE_SEL_EN_8822B BIT(25)
-#define BIT_DPDT_WLBT_SEL_8822B BIT(24)
-#define BIT_DPDT_SEL_EN_8822B BIT(23)
-#define BIT_GPIO13_14_WL_CTRL_EN_8822B BIT(22)
-#define BIT_GPIO13_14_WL_CTRL_EN_8822B BIT(22)
-#define BIT_LED2DIS_8822B BIT(21)
-#define BIT_LED2PL_8822B BIT(20)
-#define BIT_LED2SV_8822B BIT(19)
-
-#define BIT_SHIFT_LED2CM_8822B 16
-#define BIT_MASK_LED2CM_8822B 0x7
-#define BIT_LED2CM_8822B(x) \
- (((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B)
-#define BIT_GET_LED2CM_8822B(x) \
- (((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B)
-
-#define BIT_LED1DIS_8822B BIT(15)
-#define BIT_LED1PL_8822B BIT(12)
-#define BIT_LED1SV_8822B BIT(11)
-
-#define BIT_SHIFT_LED1CM_8822B 8
-#define BIT_MASK_LED1CM_8822B 0x7
-#define BIT_LED1CM_8822B(x) \
- (((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B)
-#define BIT_GET_LED1CM_8822B(x) \
- (((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B)
-
-#define BIT_LED0DIS_8822B BIT(7)
-
-#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B 5
-#define BIT_MASK_AFE_LDO_SWR_CHECK_8822B 0x3
-#define BIT_AFE_LDO_SWR_CHECK_8822B(x) \
- (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) \
- << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B)
-#define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x) \
- (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) & \
- BIT_MASK_AFE_LDO_SWR_CHECK_8822B)
-
-#define BIT_LED0PL_8822B BIT(4)
-#define BIT_LED0SV_8822B BIT(3)
-
-#define BIT_SHIFT_LED0CM_8822B 0
-#define BIT_MASK_LED0CM_8822B 0x7
-#define BIT_LED0CM_8822B(x) \
- (((x) & BIT_MASK_LED0CM_8822B) << BIT_SHIFT_LED0CM_8822B)
-#define BIT_GET_LED0CM_8822B(x) \
- (((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B)
-
-/* 2 REG_FSIMR_8822B */
-#define BIT_FS_PDNINT_EN_8822B BIT(31)
-#define BIT_NFC_INT_PAD_EN_8822B BIT(30)
-#define BIT_FS_SPS_OCP_INT_EN_8822B BIT(29)
-#define BIT_FS_PWMERR_INT_EN_8822B BIT(28)
-#define BIT_FS_GPIOF_INT_EN_8822B BIT(27)
-#define BIT_FS_GPIOE_INT_EN_8822B BIT(26)
-#define BIT_FS_GPIOD_INT_EN_8822B BIT(25)
-#define BIT_FS_GPIOC_INT_EN_8822B BIT(24)
-#define BIT_FS_GPIOB_INT_EN_8822B BIT(23)
-#define BIT_FS_GPIOA_INT_EN_8822B BIT(22)
-#define BIT_FS_GPIO9_INT_EN_8822B BIT(21)
-#define BIT_FS_GPIO8_INT_EN_8822B BIT(20)
-#define BIT_FS_GPIO7_INT_EN_8822B BIT(19)
-#define BIT_FS_GPIO6_INT_EN_8822B BIT(18)
-#define BIT_FS_GPIO5_INT_EN_8822B BIT(17)
-#define BIT_FS_GPIO4_INT_EN_8822B BIT(16)
-#define BIT_FS_GPIO3_INT_EN_8822B BIT(15)
-#define BIT_FS_GPIO2_INT_EN_8822B BIT(14)
-#define BIT_FS_GPIO1_INT_EN_8822B BIT(13)
-#define BIT_FS_GPIO0_INT_EN_8822B BIT(12)
-#define BIT_FS_HCI_SUS_EN_8822B BIT(11)
-#define BIT_FS_HCI_RES_EN_8822B BIT(10)
-#define BIT_FS_HCI_RESET_EN_8822B BIT(9)
-#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8822B BIT(7)
-#define BIT_ACT2RECOVERY_INT_EN_V1_8822B BIT(6)
-#define BIT_GEN1GEN2_SWITCH_8822B BIT(5)
-#define BIT_HCI_TXDMA_REQ_HIMR_8822B BIT(4)
-#define BIT_FS_32K_LEAVE_SETTING_MAK_8822B BIT(3)
-#define BIT_FS_32K_ENTER_SETTING_MAK_8822B BIT(2)
-#define BIT_FS_USB_LPMRSM_MSK_8822B BIT(1)
-#define BIT_FS_USB_LPMINT_MSK_8822B BIT(0)
-
-/* 2 REG_FSISR_8822B */
-#define BIT_FS_PDNINT_8822B BIT(31)
-#define BIT_FS_SPS_OCP_INT_8822B BIT(29)
-#define BIT_FS_PWMERR_INT_8822B BIT(28)
-#define BIT_FS_GPIOF_INT_8822B BIT(27)
-#define BIT_FS_GPIOE_INT_8822B BIT(26)
-#define BIT_FS_GPIOD_INT_8822B BIT(25)
-#define BIT_FS_GPIOC_INT_8822B BIT(24)
-#define BIT_FS_GPIOB_INT_8822B BIT(23)
-#define BIT_FS_GPIOA_INT_8822B BIT(22)
-#define BIT_FS_GPIO9_INT_8822B BIT(21)
-#define BIT_FS_GPIO8_INT_8822B BIT(20)
-#define BIT_FS_GPIO7_INT_8822B BIT(19)
-#define BIT_FS_GPIO6_INT_8822B BIT(18)
-#define BIT_FS_GPIO5_INT_8822B BIT(17)
-#define BIT_FS_GPIO4_INT_8822B BIT(16)
-#define BIT_FS_GPIO3_INT_8822B BIT(15)
-#define BIT_FS_GPIO2_INT_8822B BIT(14)
-#define BIT_FS_GPIO1_INT_8822B BIT(13)
-#define BIT_FS_GPIO0_INT_8822B BIT(12)
-#define BIT_FS_HCI_SUS_INT_8822B BIT(11)
-#define BIT_FS_HCI_RES_INT_8822B BIT(10)
-#define BIT_FS_HCI_RESET_INT_8822B BIT(9)
-#define BIT_ACT2RECOVERY_8822B BIT(6)
-#define BIT_GEN1GEN2_SWITCH_8822B BIT(5)
-#define BIT_HCI_TXDMA_REQ_HISR_8822B BIT(4)
-#define BIT_FS_32K_LEAVE_SETTING_INT_8822B BIT(3)
-#define BIT_FS_32K_ENTER_SETTING_INT_8822B BIT(2)
-#define BIT_FS_USB_LPMRSM_INT_8822B BIT(1)
-#define BIT_FS_USB_LPMINT_INT_8822B BIT(0)
-
-/* 2 REG_HSIMR_8822B */
-#define BIT_GPIOF_INT_EN_8822B BIT(31)
-#define BIT_GPIOE_INT_EN_8822B BIT(30)
-#define BIT_GPIOD_INT_EN_8822B BIT(29)
-#define BIT_GPIOC_INT_EN_8822B BIT(28)
-#define BIT_GPIOB_INT_EN_8822B BIT(27)
-#define BIT_GPIOA_INT_EN_8822B BIT(26)
-#define BIT_GPIO9_INT_EN_8822B BIT(25)
-#define BIT_GPIO8_INT_EN_8822B BIT(24)
-#define BIT_GPIO7_INT_EN_8822B BIT(23)
-#define BIT_GPIO6_INT_EN_8822B BIT(22)
-#define BIT_GPIO5_INT_EN_8822B BIT(21)
-#define BIT_GPIO4_INT_EN_8822B BIT(20)
-#define BIT_GPIO3_INT_EN_8822B BIT(19)
-#define BIT_GPIO2_INT_EN_V1_8822B BIT(16)
-#define BIT_GPIO1_INT_EN_8822B BIT(17)
-#define BIT_GPIO0_INT_EN_8822B BIT(16)
-#define BIT_PDNINT_EN_8822B BIT(7)
-#define BIT_RON_INT_EN_8822B BIT(6)
-#define BIT_SPS_OCP_INT_EN_8822B BIT(5)
-#define BIT_GPIO15_0_INT_EN_8822B BIT(0)
-
-/* 2 REG_HSISR_8822B */
-#define BIT_GPIOF_INT_8822B BIT(31)
-#define BIT_GPIOE_INT_8822B BIT(30)
-#define BIT_GPIOD_INT_8822B BIT(29)
-#define BIT_GPIOC_INT_8822B BIT(28)
-#define BIT_GPIOB_INT_8822B BIT(27)
-#define BIT_GPIOA_INT_8822B BIT(26)
-#define BIT_GPIO9_INT_8822B BIT(25)
-#define BIT_GPIO8_INT_8822B BIT(24)
-#define BIT_GPIO7_INT_8822B BIT(23)
-#define BIT_GPIO6_INT_8822B BIT(22)
-#define BIT_GPIO5_INT_8822B BIT(21)
-#define BIT_GPIO4_INT_8822B BIT(20)
-#define BIT_GPIO3_INT_8822B BIT(19)
-#define BIT_GPIO2_INT_V1_8822B BIT(16)
-#define BIT_GPIO1_INT_8822B BIT(17)
-#define BIT_GPIO0_INT_8822B BIT(16)
-#define BIT_PDNINT_8822B BIT(7)
-#define BIT_RON_INT_8822B BIT(6)
-#define BIT_SPS_OCP_INT_8822B BIT(5)
-#define BIT_GPIO15_0_INT_8822B BIT(0)
-
-/* 2 REG_GPIO_EXT_CTRL_8822B */
-
-#define BIT_SHIFT_GPIO_MOD_15_TO_8_8822B 24
-#define BIT_MASK_GPIO_MOD_15_TO_8_8822B 0xff
-#define BIT_GPIO_MOD_15_TO_8_8822B(x) \
- (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) \
- << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B)
-#define BIT_GET_GPIO_MOD_15_TO_8_8822B(x) \
- (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) & \
- BIT_MASK_GPIO_MOD_15_TO_8_8822B)
-
-#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B 16
-#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B 0xff
-#define BIT_GPIO_IO_SEL_15_TO_8_8822B(x) \
- (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) \
- << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B)
-#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x) \
- (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) & \
- BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B)
-
-#define BIT_SHIFT_GPIO_OUT_15_TO_8_8822B 8
-#define BIT_MASK_GPIO_OUT_15_TO_8_8822B 0xff
-#define BIT_GPIO_OUT_15_TO_8_8822B(x) \
- (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) \
- << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B)
-#define BIT_GET_GPIO_OUT_15_TO_8_8822B(x) \
- (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) & \
- BIT_MASK_GPIO_OUT_15_TO_8_8822B)
-
-#define BIT_SHIFT_GPIO_IN_15_TO_8_8822B 0
-#define BIT_MASK_GPIO_IN_15_TO_8_8822B 0xff
-#define BIT_GPIO_IN_15_TO_8_8822B(x) \
- (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B) \
- << BIT_SHIFT_GPIO_IN_15_TO_8_8822B)
-#define BIT_GET_GPIO_IN_15_TO_8_8822B(x) \
- (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) & \
- BIT_MASK_GPIO_IN_15_TO_8_8822B)
-
-/* 2 REG_PAD_CTRL1_8822B */
-#define BIT_PAPE_WLBT_SEL_8822B BIT(29)
-#define BIT_LNAON_WLBT_SEL_8822B BIT(28)
-#define BIT_BTGP_GPG3_FEN_8822B BIT(26)
-#define BIT_BTGP_GPG2_FEN_8822B BIT(25)
-#define BIT_BTGP_JTAG_EN_8822B BIT(24)
-#define BIT_XTAL_CLK_EXTARNAL_EN_8822B BIT(23)
-#define BIT_BTGP_UART0_EN_8822B BIT(22)
-#define BIT_BTGP_UART1_EN_8822B BIT(21)
-#define BIT_BTGP_SPI_EN_8822B BIT(20)
-#define BIT_BTGP_GPIO_E2_8822B BIT(19)
-#define BIT_BTGP_GPIO_EN_8822B BIT(18)
-
-#define BIT_SHIFT_BTGP_GPIO_SL_8822B 16
-#define BIT_MASK_BTGP_GPIO_SL_8822B 0x3
-#define BIT_BTGP_GPIO_SL_8822B(x) \
- (((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B)
-#define BIT_GET_BTGP_GPIO_SL_8822B(x) \
- (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B)
-
-#define BIT_PAD_SDIO_SR_8822B BIT(14)
-#define BIT_GPIO14_OUTPUT_PL_8822B BIT(13)
-#define BIT_HOST_WAKE_PAD_PULL_EN_8822B BIT(12)
-#define BIT_HOST_WAKE_PAD_SL_8822B BIT(11)
-#define BIT_PAD_LNAON_SR_8822B BIT(10)
-#define BIT_PAD_LNAON_E2_8822B BIT(9)
-#define BIT_SW_LNAON_G_SEL_DATA_8822B BIT(8)
-#define BIT_SW_LNAON_A_SEL_DATA_8822B BIT(7)
-#define BIT_PAD_PAPE_SR_8822B BIT(6)
-#define BIT_PAD_PAPE_E2_8822B BIT(5)
-#define BIT_SW_PAPE_G_SEL_DATA_8822B BIT(4)
-#define BIT_SW_PAPE_A_SEL_DATA_8822B BIT(3)
-#define BIT_PAD_DPDT_SR_8822B BIT(2)
-#define BIT_PAD_DPDT_PAD_E2_8822B BIT(1)
-#define BIT_SW_DPDT_SEL_DATA_8822B BIT(0)
-
-/* 2 REG_WL_BT_PWR_CTRL_8822B */
-#define BIT_ISO_BD2PP_8822B BIT(31)
-#define BIT_LDOV12B_EN_8822B BIT(30)
-#define BIT_CKEN_BTGPS_8822B BIT(29)
-#define BIT_FEN_BTGPS_8822B BIT(28)
-#define BIT_BTCPU_BOOTSEL_8822B BIT(27)
-#define BIT_SPI_SPEEDUP_8822B BIT(26)
-#define BIT_DEVWAKE_PAD_TYPE_SEL_8822B BIT(24)
-#define BIT_CLKREQ_PAD_TYPE_SEL_8822B BIT(23)
-#define BIT_ISO_BTPON2PP_8822B BIT(22)
-#define BIT_BT_HWROF_EN_8822B BIT(19)
-#define BIT_BT_FUNC_EN_8822B BIT(18)
-#define BIT_BT_HWPDN_SL_8822B BIT(17)
-#define BIT_BT_DISN_EN_8822B BIT(16)
-#define BIT_BT_PDN_PULL_EN_8822B BIT(15)
-#define BIT_WL_PDN_PULL_EN_8822B BIT(14)
-#define BIT_EXTERNAL_REQUEST_PL_8822B BIT(13)
-#define BIT_GPIO0_2_3_PULL_LOW_EN_8822B BIT(12)
-#define BIT_ISO_BA2PP_8822B BIT(11)
-#define BIT_BT_AFE_LDO_EN_8822B BIT(10)
-#define BIT_BT_AFE_PLL_EN_8822B BIT(9)
-#define BIT_BT_DIG_CLK_EN_8822B BIT(8)
-#define BIT_WL_DRV_EXIST_IDX_8822B BIT(5)
-#define BIT_DOP_EHPAD_8822B BIT(4)
-#define BIT_WL_HWROF_EN_8822B BIT(3)
-#define BIT_WL_FUNC_EN_8822B BIT(2)
-#define BIT_WL_HWPDN_SL_8822B BIT(1)
-#define BIT_WL_HWPDN_EN_8822B BIT(0)
-
-/* 2 REG_SDM_DEBUG_8822B */
-
-#define BIT_SHIFT_WLCLK_PHASE_8822B 0
-#define BIT_MASK_WLCLK_PHASE_8822B 0x1f
-#define BIT_WLCLK_PHASE_8822B(x) \
- (((x) & BIT_MASK_WLCLK_PHASE_8822B) << BIT_SHIFT_WLCLK_PHASE_8822B)
-#define BIT_GET_WLCLK_PHASE_8822B(x) \
- (((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B)
-
-/* 2 REG_SYS_SDIO_CTRL_8822B */
-#define BIT_DBG_GNT_WL_BT_8822B BIT(27)
-#define BIT_LTE_MUX_CTRL_PATH_8822B BIT(26)
-#define BIT_LTE_COEX_UART_8822B BIT(25)
-#define BIT_3W_LTE_WL_GPIO_8822B BIT(24)
-#define BIT_SDIO_INT_POLARITY_8822B BIT(19)
-#define BIT_SDIO_INT_8822B BIT(18)
-#define BIT_SDIO_OFF_EN_8822B BIT(17)
-#define BIT_SDIO_ON_EN_8822B BIT(16)
-#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8822B BIT(10)
-#define BIT_PCIE_WAIT_TIME_8822B BIT(9)
-#define BIT_MPCIE_REFCLK_XTAL_SEL_8822B BIT(8)
-
-/* 2 REG_HCI_OPT_CTRL_8822B */
-
-#define BIT_SHIFT_TSFT_SEL_8822B 29
-#define BIT_MASK_TSFT_SEL_8822B 0x7
-#define BIT_TSFT_SEL_8822B(x) \
- (((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B)
-#define BIT_GET_TSFT_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B)
-
-#define BIT_USB_HOST_PWR_OFF_EN_8822B BIT(12)
-#define BIT_SYM_LPS_BLOCK_EN_8822B BIT(11)
-#define BIT_USB_LPM_ACT_EN_8822B BIT(10)
-#define BIT_USB_LPM_NY_8822B BIT(9)
-#define BIT_USB_SUS_DIS_8822B BIT(8)
-
-#define BIT_SHIFT_SDIO_PAD_E_8822B 5
-#define BIT_MASK_SDIO_PAD_E_8822B 0x7
-#define BIT_SDIO_PAD_E_8822B(x) \
- (((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B)
-#define BIT_GET_SDIO_PAD_E_8822B(x) \
- (((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B)
-
-#define BIT_USB_LPPLL_EN_8822B BIT(4)
-#define BIT_ROP_SW15_8822B BIT(2)
-#define BIT_PCI_CKRDY_OPT_8822B BIT(1)
-#define BIT_PCI_VAUX_EN_8822B BIT(0)
-
-/* 2 REG_AFE_CTRL4_8822B */
-
-/* 2 REG_LDO_SWR_CTRL_8822B */
-#define BIT_ZCD_HW_AUTO_EN_8822B BIT(27)
-#define BIT_ZCD_REGSEL_8822B BIT(26)
-
-#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B 21
-#define BIT_MASK_AUTO_ZCD_IN_CODE_8822B 0x1f
-#define BIT_AUTO_ZCD_IN_CODE_8822B(x) \
- (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) \
- << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B)
-#define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x) \
- (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) & \
- BIT_MASK_AUTO_ZCD_IN_CODE_8822B)
-
-#define BIT_SHIFT_ZCD_CODE_IN_L_8822B 16
-#define BIT_MASK_ZCD_CODE_IN_L_8822B 0x1f
-#define BIT_ZCD_CODE_IN_L_8822B(x) \
- (((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B)
-#define BIT_GET_ZCD_CODE_IN_L_8822B(x) \
- (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B)
-
-#define BIT_SHIFT_LDO_HV5_DUMMY_8822B 14
-#define BIT_MASK_LDO_HV5_DUMMY_8822B 0x3
-#define BIT_LDO_HV5_DUMMY_8822B(x) \
- (((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B)
-#define BIT_GET_LDO_HV5_DUMMY_8822B(x) \
- (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B)
-
-#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B 12
-#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B 0x3
-#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \
- (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) \
- << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B)
-#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \
- (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) & \
- BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B)
-
-#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B 10
-#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B 0x3
-#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \
- (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) \
- << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B)
-#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \
- (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) & \
- BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B)
-
-#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B 8
-#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B 0x3
-#define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \
- (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) \
- << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B)
-#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \
- (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) & \
- BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B)
-
-#define BIT_REG_BYPASS_L_8822B BIT(7)
-#define BIT_REG_LDOF_L_8822B BIT(6)
-#define BIT_REG_TYPE_L_V1_8822B BIT(5)
-#define BIT_ARENB_L_8822B BIT(3)
-
-#define BIT_SHIFT_CFC_L_8822B 1
-#define BIT_MASK_CFC_L_8822B 0x3
-#define BIT_CFC_L_8822B(x) \
- (((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B)
-#define BIT_GET_CFC_L_8822B(x) \
- (((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B)
-
-#define BIT_REG_OCPS_L_V1_8822B BIT(0)
-
-/* 2 REG_MCUFW_CTRL_8822B */
-
-#define BIT_SHIFT_RPWM_8822B 24
-#define BIT_MASK_RPWM_8822B 0xff
-#define BIT_RPWM_8822B(x) (((x) & BIT_MASK_RPWM_8822B) << BIT_SHIFT_RPWM_8822B)
-#define BIT_GET_RPWM_8822B(x) \
- (((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B)
-
-#define BIT_ANA_PORT_EN_8822B BIT(22)
-#define BIT_MAC_PORT_EN_8822B BIT(21)
-#define BIT_BOOT_FSPI_EN_8822B BIT(20)
-#define BIT_ROM_DLEN_8822B BIT(19)
-
-#define BIT_SHIFT_ROM_PGE_8822B 16
-#define BIT_MASK_ROM_PGE_8822B 0x7
-#define BIT_ROM_PGE_8822B(x) \
- (((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B)
-#define BIT_GET_ROM_PGE_8822B(x) \
- (((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B)
-
-#define BIT_FW_INIT_RDY_8822B BIT(15)
-#define BIT_FW_DW_RDY_8822B BIT(14)
-
-#define BIT_SHIFT_CPU_CLK_SEL_8822B 12
-#define BIT_MASK_CPU_CLK_SEL_8822B 0x3
-#define BIT_CPU_CLK_SEL_8822B(x) \
- (((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B)
-#define BIT_GET_CPU_CLK_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B)
-
-#define BIT_CCLK_CHG_MASK_8822B BIT(11)
-#define BIT_EMEM__TXBUF_CHKSUM_OK_8822B BIT(10)
-#define BIT_EMEM_TXBUF_DW_RDY_8822B BIT(9)
-#define BIT_EMEM_CHKSUM_OK_8822B BIT(8)
-#define BIT_EMEM_DW_OK_8822B BIT(7)
-#define BIT_DMEM_CHKSUM_OK_8822B BIT(6)
-#define BIT_DMEM_DW_OK_8822B BIT(5)
-#define BIT_IMEM_CHKSUM_OK_8822B BIT(4)
-#define BIT_IMEM_DW_OK_8822B BIT(3)
-#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8822B BIT(2)
-#define BIT_IMEM_BOOT_LOAD_DW_OK_8822B BIT(1)
-#define BIT_MCUFWDL_EN_8822B BIT(0)
-
-/* 2 REG_MCU_TST_CFG_8822B */
-
-#define BIT_SHIFT_LBKTST_8822B 0
-#define BIT_MASK_LBKTST_8822B 0xffff
-#define BIT_LBKTST_8822B(x) \
- (((x) & BIT_MASK_LBKTST_8822B) << BIT_SHIFT_LBKTST_8822B)
-#define BIT_GET_LBKTST_8822B(x) \
- (((x) >> BIT_SHIFT_LBKTST_8822B) & BIT_MASK_LBKTST_8822B)
-
-/* 2 REG_HMEBOX_E0_E1_8822B */
-
-#define BIT_SHIFT_HOST_MSG_E1_8822B 16
-#define BIT_MASK_HOST_MSG_E1_8822B 0xffff
-#define BIT_HOST_MSG_E1_8822B(x) \
- (((x) & BIT_MASK_HOST_MSG_E1_8822B) << BIT_SHIFT_HOST_MSG_E1_8822B)
-#define BIT_GET_HOST_MSG_E1_8822B(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B)
-
-#define BIT_SHIFT_HOST_MSG_E0_8822B 0
-#define BIT_MASK_HOST_MSG_E0_8822B 0xffff
-#define BIT_HOST_MSG_E0_8822B(x) \
- (((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B)
-#define BIT_GET_HOST_MSG_E0_8822B(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B)
-
-/* 2 REG_HMEBOX_E2_E3_8822B */
-
-#define BIT_SHIFT_HOST_MSG_E3_8822B 16
-#define BIT_MASK_HOST_MSG_E3_8822B 0xffff
-#define BIT_HOST_MSG_E3_8822B(x) \
- (((x) & BIT_MASK_HOST_MSG_E3_8822B) << BIT_SHIFT_HOST_MSG_E3_8822B)
-#define BIT_GET_HOST_MSG_E3_8822B(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B)
-
-#define BIT_SHIFT_HOST_MSG_E2_8822B 0
-#define BIT_MASK_HOST_MSG_E2_8822B 0xffff
-#define BIT_HOST_MSG_E2_8822B(x) \
- (((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B)
-#define BIT_GET_HOST_MSG_E2_8822B(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B)
-
-/* 2 REG_WLLPS_CTRL_8822B */
-#define BIT_WLLPSOP_EABM_8822B BIT(31)
-#define BIT_WLLPSOP_ACKF_8822B BIT(30)
-#define BIT_WLLPSOP_DLDM_8822B BIT(29)
-#define BIT_WLLPSOP_ESWR_8822B BIT(28)
-#define BIT_WLLPSOP_PWMM_8822B BIT(27)
-#define BIT_WLLPSOP_EECK_8822B BIT(26)
-#define BIT_WLLPSOP_WLMACOFF_8822B BIT(25)
-#define BIT_WLLPSOP_EXTAL_8822B BIT(24)
-#define BIT_WL_SYNPON_VOLTSPDN_8822B BIT(23)
-#define BIT_WLLPSOP_WLBBOFF_8822B BIT(22)
-#define BIT_WLLPSOP_WLMEM_DS_8822B BIT(21)
-
-#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B 12
-#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B 0xf
-#define BIT_LPLDH12_VADJ_STEP_DN_8822B(x) \
- (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) \
- << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B)
-#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x) \
- (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) & \
- BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B)
-
-#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B 8
-#define BIT_MASK_V15ADJ_L1_STEP_DN_8822B 0x7
-#define BIT_V15ADJ_L1_STEP_DN_8822B(x) \
- (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) \
- << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B)
-#define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x) \
- (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) & \
- BIT_MASK_V15ADJ_L1_STEP_DN_8822B)
-
-#define BIT_REGU_32K_CLK_EN_8822B BIT(1)
-#define BIT_WL_LPS_EN_8822B BIT(0)
-
-/* 2 REG_AFE_CTRL5_8822B */
-#define BIT_BB_DBG_SEL_AFE_SDM_BIT0_8822B BIT(31)
-#define BIT_ORDER_SDM_8822B BIT(30)
-#define BIT_RFE_SEL_SDM_8822B BIT(29)
-
-#define BIT_SHIFT_REF_SEL_8822B 25
-#define BIT_MASK_REF_SEL_8822B 0xf
-#define BIT_REF_SEL_8822B(x) \
- (((x) & BIT_MASK_REF_SEL_8822B) << BIT_SHIFT_REF_SEL_8822B)
-#define BIT_GET_REF_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B)
-
-#define BIT_SHIFT_F0F_SDM_8822B 12
-#define BIT_MASK_F0F_SDM_8822B 0x1fff
-#define BIT_F0F_SDM_8822B(x) \
- (((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B)
-#define BIT_GET_F0F_SDM_8822B(x) \
- (((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B)
-
-#define BIT_SHIFT_F0N_SDM_8822B 9
-#define BIT_MASK_F0N_SDM_8822B 0x7
-#define BIT_F0N_SDM_8822B(x) \
- (((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B)
-#define BIT_GET_F0N_SDM_8822B(x) \
- (((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B)
-
-#define BIT_SHIFT_DIVN_SDM_8822B 3
-#define BIT_MASK_DIVN_SDM_8822B 0x3f
-#define BIT_DIVN_SDM_8822B(x) \
- (((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B)
-#define BIT_GET_DIVN_SDM_8822B(x) \
- (((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B)
-
-/* 2 REG_GPIO_DEBOUNCE_CTRL_8822B */
-#define BIT_WLGP_DBC1EN_8822B BIT(15)
-
-#define BIT_SHIFT_WLGP_DBC1_8822B 8
-#define BIT_MASK_WLGP_DBC1_8822B 0xf
-#define BIT_WLGP_DBC1_8822B(x) \
- (((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B)
-#define BIT_GET_WLGP_DBC1_8822B(x) \
- (((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B)
-
-#define BIT_WLGP_DBC0EN_8822B BIT(7)
-
-#define BIT_SHIFT_WLGP_DBC0_8822B 0
-#define BIT_MASK_WLGP_DBC0_8822B 0xf
-#define BIT_WLGP_DBC0_8822B(x) \
- (((x) & BIT_MASK_WLGP_DBC0_8822B) << BIT_SHIFT_WLGP_DBC0_8822B)
-#define BIT_GET_WLGP_DBC0_8822B(x) \
- (((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B)
-
-/* 2 REG_RPWM2_8822B */
-
-#define BIT_SHIFT_RPWM2_8822B 16
-#define BIT_MASK_RPWM2_8822B 0xffff
-#define BIT_RPWM2_8822B(x) \
- (((x) & BIT_MASK_RPWM2_8822B) << BIT_SHIFT_RPWM2_8822B)
-#define BIT_GET_RPWM2_8822B(x) \
- (((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B)
-
-/* 2 REG_SYSON_FSM_MON_8822B */
-
-#define BIT_SHIFT_FSM_MON_SEL_8822B 24
-#define BIT_MASK_FSM_MON_SEL_8822B 0x7
-#define BIT_FSM_MON_SEL_8822B(x) \
- (((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B)
-#define BIT_GET_FSM_MON_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B)
-
-#define BIT_DOP_ELDO_8822B BIT(23)
-#define BIT_FSM_MON_UPD_8822B BIT(15)
-
-#define BIT_SHIFT_FSM_PAR_8822B 0
-#define BIT_MASK_FSM_PAR_8822B 0x7fff
-#define BIT_FSM_PAR_8822B(x) \
- (((x) & BIT_MASK_FSM_PAR_8822B) << BIT_SHIFT_FSM_PAR_8822B)
-#define BIT_GET_FSM_PAR_8822B(x) \
- (((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B)
-
-/* 2 REG_AFE_CTRL6_8822B */
-
-#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0
-#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0x7
-#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \
- (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) \
- << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
-#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \
- (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) & \
- BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
-
-/* 2 REG_PMC_DBG_CTRL1_8822B */
-#define BIT_BT_INT_EN_8822B BIT(31)
-
-#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B 16
-#define BIT_MASK_RD_WR_WIFI_BT_INFO_8822B 0x7fff
-#define BIT_RD_WR_WIFI_BT_INFO_8822B(x) \
- (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) \
- << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B)
-#define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) & \
- BIT_MASK_RD_WR_WIFI_BT_INFO_8822B)
-
-#define BIT_PMC_WR_OVF_8822B BIT(8)
-
-#define BIT_SHIFT_WLPMC_ERRINT_8822B 0
-#define BIT_MASK_WLPMC_ERRINT_8822B 0xff
-#define BIT_WLPMC_ERRINT_8822B(x) \
- (((x) & BIT_MASK_WLPMC_ERRINT_8822B) << BIT_SHIFT_WLPMC_ERRINT_8822B)
-#define BIT_GET_WLPMC_ERRINT_8822B(x) \
- (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B)
-
-/* 2 REG_AFE_CTRL7_8822B */
-
-#define BIT_SHIFT_SEL_V_8822B 30
-#define BIT_MASK_SEL_V_8822B 0x3
-#define BIT_SEL_V_8822B(x) \
- (((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B)
-#define BIT_GET_SEL_V_8822B(x) \
- (((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B)
-
-#define BIT_SEL_LDO_PC_8822B BIT(29)
-
-#define BIT_SHIFT_CK_MON_SEL_8822B 26
-#define BIT_MASK_CK_MON_SEL_8822B 0x7
-#define BIT_CK_MON_SEL_8822B(x) \
- (((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B)
-#define BIT_GET_CK_MON_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B)
-
-#define BIT_CK_MON_EN_8822B BIT(25)
-#define BIT_FREF_EDGE_8822B BIT(24)
-#define BIT_CK320M_EN_8822B BIT(23)
-#define BIT_CK_5M_EN_8822B BIT(22)
-#define BIT_TESTEN_8822B BIT(21)
-
-/* 2 REG_HIMR0_8822B */
-#define BIT_TIMEOUT_INTERRUPT2_MASK_8822B BIT(31)
-#define BIT_TIMEOUT_INTERRUTP1_MASK_8822B BIT(30)
-#define BIT_PSTIMEOUT_MSK_8822B BIT(29)
-#define BIT_GTINT4_MSK_8822B BIT(28)
-#define BIT_GTINT3_MSK_8822B BIT(27)
-#define BIT_TXBCN0ERR_MSK_8822B BIT(26)
-#define BIT_TXBCN0OK_MSK_8822B BIT(25)
-#define BIT_TSF_BIT32_TOGGLE_MSK_8822B BIT(24)
-#define BIT_BCNDMAINT0_MSK_8822B BIT(20)
-#define BIT_BCNDERR0_MSK_8822B BIT(16)
-#define BIT_HSISR_IND_ON_INT_MSK_8822B BIT(15)
-#define BIT_BCNDMAINT_E_MSK_8822B BIT(14)
-#define BIT_CTWEND_MSK_8822B BIT(12)
-#define BIT_HISR1_IND_MSK_8822B BIT(11)
-#define BIT_C2HCMD_MSK_8822B BIT(10)
-#define BIT_CPWM2_MSK_8822B BIT(9)
-#define BIT_CPWM_MSK_8822B BIT(8)
-#define BIT_HIGHDOK_MSK_8822B BIT(7)
-#define BIT_MGTDOK_MSK_8822B BIT(6)
-#define BIT_BKDOK_MSK_8822B BIT(5)
-#define BIT_BEDOK_MSK_8822B BIT(4)
-#define BIT_VIDOK_MSK_8822B BIT(3)
-#define BIT_VODOK_MSK_8822B BIT(2)
-#define BIT_RDU_MSK_8822B BIT(1)
-#define BIT_RXOK_MSK_8822B BIT(0)
-
-/* 2 REG_HISR0_8822B */
-#define BIT_TIMEOUT_INTERRUPT2_8822B BIT(31)
-#define BIT_TIMEOUT_INTERRUTP1_8822B BIT(30)
-#define BIT_PSTIMEOUT_8822B BIT(29)
-#define BIT_GTINT4_8822B BIT(28)
-#define BIT_GTINT3_8822B BIT(27)
-#define BIT_TXBCN0ERR_8822B BIT(26)
-#define BIT_TXBCN0OK_8822B BIT(25)
-#define BIT_TSF_BIT32_TOGGLE_8822B BIT(24)
-#define BIT_BCNDMAINT0_8822B BIT(20)
-#define BIT_BCNDERR0_8822B BIT(16)
-#define BIT_HSISR_IND_ON_INT_8822B BIT(15)
-#define BIT_BCNDMAINT_E_8822B BIT(14)
-#define BIT_CTWEND_8822B BIT(12)
-#define BIT_HISR1_IND_INT_8822B BIT(11)
-#define BIT_C2HCMD_8822B BIT(10)
-#define BIT_CPWM2_8822B BIT(9)
-#define BIT_CPWM_8822B BIT(8)
-#define BIT_HIGHDOK_8822B BIT(7)
-#define BIT_MGTDOK_8822B BIT(6)
-#define BIT_BKDOK_8822B BIT(5)
-#define BIT_BEDOK_8822B BIT(4)
-#define BIT_VIDOK_8822B BIT(3)
-#define BIT_VODOK_8822B BIT(2)
-#define BIT_RDU_8822B BIT(1)
-#define BIT_RXOK_8822B BIT(0)
-
-/* 2 REG_HIMR1_8822B */
-#define BIT_TXFIFO_TH_INT_8822B BIT(30)
-#define BIT_BTON_STS_UPDATE_MASK_8822B BIT(29)
-#define BIT_MCU_ERR_MASK_8822B BIT(28)
-#define BIT_BCNDMAINT7__MSK_8822B BIT(27)
-#define BIT_BCNDMAINT6__MSK_8822B BIT(26)
-#define BIT_BCNDMAINT5__MSK_8822B BIT(25)
-#define BIT_BCNDMAINT4__MSK_8822B BIT(24)
-#define BIT_BCNDMAINT3_MSK_8822B BIT(23)
-#define BIT_BCNDMAINT2_MSK_8822B BIT(22)
-#define BIT_BCNDMAINT1_MSK_8822B BIT(21)
-#define BIT_BCNDERR7_MSK_8822B BIT(20)
-#define BIT_BCNDERR6_MSK_8822B BIT(19)
-#define BIT_BCNDERR5_MSK_8822B BIT(18)
-#define BIT_BCNDERR4_MSK_8822B BIT(17)
-#define BIT_BCNDERR3_MSK_8822B BIT(16)
-#define BIT_BCNDERR2_MSK_8822B BIT(15)
-#define BIT_BCNDERR1_MSK_8822B BIT(14)
-#define BIT_ATIMEND_E_MSK_8822B BIT(13)
-#define BIT_ATIMEND__MSK_8822B BIT(12)
-#define BIT_TXERR_MSK_8822B BIT(11)
-#define BIT_RXERR_MSK_8822B BIT(10)
-#define BIT_TXFOVW_MSK_8822B BIT(9)
-#define BIT_FOVW_MSK_8822B BIT(8)
-#define BIT_CPU_MGQ_TXDONE_MSK_8822B BIT(5)
-#define BIT_PS_TIMER_C_MSK_8822B BIT(4)
-#define BIT_PS_TIMER_B_MSK_8822B BIT(3)
-#define BIT_PS_TIMER_A_MSK_8822B BIT(2)
-#define BIT_CPUMGQ_TX_TIMER_MSK_8822B BIT(1)
-
-/* 2 REG_HISR1_8822B */
-#define BIT_TXFIFO_TH_INT_8822B BIT(30)
-#define BIT_BTON_STS_UPDATE_INT_8822B BIT(29)
-#define BIT_MCU_ERR_8822B BIT(28)
-#define BIT_BCNDMAINT7_8822B BIT(27)
-#define BIT_BCNDMAINT6_8822B BIT(26)
-#define BIT_BCNDMAINT5_8822B BIT(25)
-#define BIT_BCNDMAINT4_8822B BIT(24)
-#define BIT_BCNDMAINT3_8822B BIT(23)
-#define BIT_BCNDMAINT2_8822B BIT(22)
-#define BIT_BCNDMAINT1_8822B BIT(21)
-#define BIT_BCNDERR7_8822B BIT(20)
-#define BIT_BCNDERR6_8822B BIT(19)
-#define BIT_BCNDERR5_8822B BIT(18)
-#define BIT_BCNDERR4_8822B BIT(17)
-#define BIT_BCNDERR3_8822B BIT(16)
-#define BIT_BCNDERR2_8822B BIT(15)
-#define BIT_BCNDERR1_8822B BIT(14)
-#define BIT_ATIMEND_E_8822B BIT(13)
-#define BIT_ATIMEND_8822B BIT(12)
-#define BIT_TXERR_INT_8822B BIT(11)
-#define BIT_RXERR_INT_8822B BIT(10)
-#define BIT_TXFOVW_8822B BIT(9)
-#define BIT_FOVW_8822B BIT(8)
-#define BIT_CPU_MGQ_TXDONE_8822B BIT(5)
-#define BIT_PS_TIMER_C_8822B BIT(4)
-#define BIT_PS_TIMER_B_8822B BIT(3)
-#define BIT_PS_TIMER_A_8822B BIT(2)
-#define BIT_CPUMGQ_TX_TIMER_8822B BIT(1)
-
-/* 2 REG_DBG_PORT_SEL_8822B */
-
-#define BIT_SHIFT_DEBUG_ST_8822B 0
-#define BIT_MASK_DEBUG_ST_8822B 0xffffffffL
-#define BIT_DEBUG_ST_8822B(x) \
- (((x) & BIT_MASK_DEBUG_ST_8822B) << BIT_SHIFT_DEBUG_ST_8822B)
-#define BIT_GET_DEBUG_ST_8822B(x) \
- (((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B)
-
-/* 2 REG_PAD_CTRL2_8822B */
-#define BIT_USB3_USB2_TRANSITION_8822B BIT(20)
-
-#define BIT_SHIFT_USB23_SW_MODE_V1_8822B 18
-#define BIT_MASK_USB23_SW_MODE_V1_8822B 0x3
-#define BIT_USB23_SW_MODE_V1_8822B(x) \
- (((x) & BIT_MASK_USB23_SW_MODE_V1_8822B) \
- << BIT_SHIFT_USB23_SW_MODE_V1_8822B)
-#define BIT_GET_USB23_SW_MODE_V1_8822B(x) \
- (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) & \
- BIT_MASK_USB23_SW_MODE_V1_8822B)
-
-#define BIT_NO_PDN_CHIPOFF_V1_8822B BIT(17)
-#define BIT_RSM_EN_V1_8822B BIT(16)
-
-#define BIT_SHIFT_MATCH_CNT_8822B 8
-#define BIT_MASK_MATCH_CNT_8822B 0xff
-#define BIT_MATCH_CNT_8822B(x) \
- (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)
-#define BIT_GET_MATCH_CNT_8822B(x) \
- (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)
-
-#define BIT_LD_B12V_EN_8822B BIT(7)
-#define BIT_EECS_IOSEL_V1_8822B BIT(6)
-#define BIT_EECS_DATA_O_V1_8822B BIT(5)
-#define BIT_EECS_DATA_I_V1_8822B BIT(4)
-#define BIT_EESK_IOSEL_V1_8822B BIT(2)
-#define BIT_EESK_DATA_O_V1_8822B BIT(1)
-#define BIT_EESK_DATA_I_V1_8822B BIT(0)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_PMC_DBG_CTRL2_8822B */
-
-#define BIT_SHIFT_EFUSE_BURN_GNT_8822B 24
-#define BIT_MASK_EFUSE_BURN_GNT_8822B 0xff
-#define BIT_EFUSE_BURN_GNT_8822B(x) \
- (((x) & BIT_MASK_EFUSE_BURN_GNT_8822B) \
- << BIT_SHIFT_EFUSE_BURN_GNT_8822B)
-#define BIT_GET_EFUSE_BURN_GNT_8822B(x) \
- (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) & \
- BIT_MASK_EFUSE_BURN_GNT_8822B)
-
-#define BIT_STOP_WL_PMC_8822B BIT(9)
-#define BIT_STOP_SYM_PMC_8822B BIT(8)
-#define BIT_REG_RST_WLPMC_8822B BIT(5)
-#define BIT_REG_RST_PD12N_8822B BIT(4)
-#define BIT_SYSON_DIS_WLREG_WRMSK_8822B BIT(3)
-#define BIT_SYSON_DIS_PMCREG_WRMSK_8822B BIT(2)
-
-#define BIT_SHIFT_SYSON_REG_ARB_8822B 0
-#define BIT_MASK_SYSON_REG_ARB_8822B 0x3
-#define BIT_SYSON_REG_ARB_8822B(x) \
- (((x) & BIT_MASK_SYSON_REG_ARB_8822B) << BIT_SHIFT_SYSON_REG_ARB_8822B)
-#define BIT_GET_SYSON_REG_ARB_8822B(x) \
- (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B)
-
-/* 2 REG_BIST_CTRL_8822B */
-#define BIT_BIST_USB_DIS_8822B BIT(27)
-#define BIT_BIST_PCI_DIS_8822B BIT(26)
-#define BIT_BIST_BT_DIS_8822B BIT(25)
-#define BIT_BIST_WL_DIS_8822B BIT(24)
-
-#define BIT_SHIFT_BIST_RPT_SEL_8822B 16
-#define BIT_MASK_BIST_RPT_SEL_8822B 0xf
-#define BIT_BIST_RPT_SEL_8822B(x) \
- (((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B)
-#define BIT_GET_BIST_RPT_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B)
-
-#define BIT_BIST_RESUME_PS_8822B BIT(4)
-#define BIT_BIST_RESUME_8822B BIT(3)
-#define BIT_BIST_NORMAL_8822B BIT(2)
-#define BIT_BIST_RSTN_8822B BIT(1)
-#define BIT_BIST_CLK_EN_8822B BIT(0)
-
-/* 2 REG_BIST_RPT_8822B */
-
-#define BIT_SHIFT_MBIST_REPORT_8822B 0
-#define BIT_MASK_MBIST_REPORT_8822B 0xffffffffL
-#define BIT_MBIST_REPORT_8822B(x) \
- (((x) & BIT_MASK_MBIST_REPORT_8822B) << BIT_SHIFT_MBIST_REPORT_8822B)
-#define BIT_GET_MBIST_REPORT_8822B(x) \
- (((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B)
-
-/* 2 REG_MEM_CTRL_8822B */
-#define BIT_UMEM_RME_8822B BIT(31)
-
-#define BIT_SHIFT_BT_SPRAM_8822B 28
-#define BIT_MASK_BT_SPRAM_8822B 0x3
-#define BIT_BT_SPRAM_8822B(x) \
- (((x) & BIT_MASK_BT_SPRAM_8822B) << BIT_SHIFT_BT_SPRAM_8822B)
-#define BIT_GET_BT_SPRAM_8822B(x) \
- (((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B)
-
-#define BIT_SHIFT_BT_ROM_8822B 24
-#define BIT_MASK_BT_ROM_8822B 0xf
-#define BIT_BT_ROM_8822B(x) \
- (((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B)
-#define BIT_GET_BT_ROM_8822B(x) \
- (((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B)
-
-#define BIT_SHIFT_PCI_DPRAM_8822B 10
-#define BIT_MASK_PCI_DPRAM_8822B 0x3
-#define BIT_PCI_DPRAM_8822B(x) \
- (((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B)
-#define BIT_GET_PCI_DPRAM_8822B(x) \
- (((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B)
-
-#define BIT_SHIFT_PCI_SPRAM_8822B 8
-#define BIT_MASK_PCI_SPRAM_8822B 0x3
-#define BIT_PCI_SPRAM_8822B(x) \
- (((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B)
-#define BIT_GET_PCI_SPRAM_8822B(x) \
- (((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B)
-
-#define BIT_SHIFT_USB_SPRAM_8822B 6
-#define BIT_MASK_USB_SPRAM_8822B 0x3
-#define BIT_USB_SPRAM_8822B(x) \
- (((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B)
-#define BIT_GET_USB_SPRAM_8822B(x) \
- (((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B)
-
-#define BIT_SHIFT_USB_SPRF_8822B 4
-#define BIT_MASK_USB_SPRF_8822B 0x3
-#define BIT_USB_SPRF_8822B(x) \
- (((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B)
-#define BIT_GET_USB_SPRF_8822B(x) \
- (((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B)
-
-#define BIT_SHIFT_MCU_ROM_8822B 0
-#define BIT_MASK_MCU_ROM_8822B 0xf
-#define BIT_MCU_ROM_8822B(x) \
- (((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B)
-#define BIT_GET_MCU_ROM_8822B(x) \
- (((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B)
-
-/* 2 REG_AFE_CTRL8_8822B */
-#define BIT_SYN_AGPIO_8822B BIT(20)
-#define BIT_XTAL_LP_8822B BIT(4)
-#define BIT_XTAL_GM_SEP_8822B BIT(3)
-
-#define BIT_SHIFT_XTAL_SEL_TOK_8822B 0
-#define BIT_MASK_XTAL_SEL_TOK_8822B 0x7
-#define BIT_XTAL_SEL_TOK_8822B(x) \
- (((x) & BIT_MASK_XTAL_SEL_TOK_8822B) << BIT_SHIFT_XTAL_SEL_TOK_8822B)
-#define BIT_GET_XTAL_SEL_TOK_8822B(x) \
- (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B)
-
-/* 2 REG_USB_SIE_INTF_8822B */
-#define BIT_RD_SEL_8822B BIT(31)
-#define BIT_USB_SIE_INTF_WE_V1_8822B BIT(30)
-#define BIT_USB_SIE_INTF_BYIOREG_V1_8822B BIT(29)
-#define BIT_USB_SIE_SELECT_8822B BIT(28)
-
-#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B 16
-#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B 0x1ff
-#define BIT_USB_SIE_INTF_ADDR_V1_8822B(x) \
- (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) \
- << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B)
-#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x) \
- (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) & \
- BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B)
-
-#define BIT_SHIFT_USB_SIE_INTF_RD_8822B 8
-#define BIT_MASK_USB_SIE_INTF_RD_8822B 0xff
-#define BIT_USB_SIE_INTF_RD_8822B(x) \
- (((x) & BIT_MASK_USB_SIE_INTF_RD_8822B) \
- << BIT_SHIFT_USB_SIE_INTF_RD_8822B)
-#define BIT_GET_USB_SIE_INTF_RD_8822B(x) \
- (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) & \
- BIT_MASK_USB_SIE_INTF_RD_8822B)
-
-#define BIT_SHIFT_USB_SIE_INTF_WD_8822B 0
-#define BIT_MASK_USB_SIE_INTF_WD_8822B 0xff
-#define BIT_USB_SIE_INTF_WD_8822B(x) \
- (((x) & BIT_MASK_USB_SIE_INTF_WD_8822B) \
- << BIT_SHIFT_USB_SIE_INTF_WD_8822B)
-#define BIT_GET_USB_SIE_INTF_WD_8822B(x) \
- (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) & \
- BIT_MASK_USB_SIE_INTF_WD_8822B)
-
-/* 2 REG_PCIE_MIO_INTF_8822B */
-#define BIT_PCIE_MIO_BYIOREG_8822B BIT(13)
-#define BIT_PCIE_MIO_RE_8822B BIT(12)
-
-#define BIT_SHIFT_PCIE_MIO_WE_8822B 8
-#define BIT_MASK_PCIE_MIO_WE_8822B 0xf
-#define BIT_PCIE_MIO_WE_8822B(x) \
- (((x) & BIT_MASK_PCIE_MIO_WE_8822B) << BIT_SHIFT_PCIE_MIO_WE_8822B)
-#define BIT_GET_PCIE_MIO_WE_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B)
-
-#define BIT_SHIFT_PCIE_MIO_ADDR_8822B 0
-#define BIT_MASK_PCIE_MIO_ADDR_8822B 0xff
-#define BIT_PCIE_MIO_ADDR_8822B(x) \
- (((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B)
-#define BIT_GET_PCIE_MIO_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B)
-
-/* 2 REG_PCIE_MIO_INTD_8822B */
-
-#define BIT_SHIFT_PCIE_MIO_DATA_8822B 0
-#define BIT_MASK_PCIE_MIO_DATA_8822B 0xffffffffL
-#define BIT_PCIE_MIO_DATA_8822B(x) \
- (((x) & BIT_MASK_PCIE_MIO_DATA_8822B) << BIT_SHIFT_PCIE_MIO_DATA_8822B)
-#define BIT_GET_PCIE_MIO_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B)
-
-/* 2 REG_WLRF1_8822B */
-
-#define BIT_SHIFT_WLRF1_CTRL_8822B 24
-#define BIT_MASK_WLRF1_CTRL_8822B 0xff
-#define BIT_WLRF1_CTRL_8822B(x) \
- (((x) & BIT_MASK_WLRF1_CTRL_8822B) << BIT_SHIFT_WLRF1_CTRL_8822B)
-#define BIT_GET_WLRF1_CTRL_8822B(x) \
- (((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B)
-
-/* 2 REG_SYS_CFG1_8822B */
-
-#define BIT_SHIFT_TRP_ICFG_8822B 28
-#define BIT_MASK_TRP_ICFG_8822B 0xf
-#define BIT_TRP_ICFG_8822B(x) \
- (((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B)
-#define BIT_GET_TRP_ICFG_8822B(x) \
- (((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B)
-
-#define BIT_RF_TYPE_ID_8822B BIT(27)
-#define BIT_BD_HCI_SEL_8822B BIT(26)
-#define BIT_BD_PKG_SEL_8822B BIT(25)
-#define BIT_SPSLDO_SEL_8822B BIT(24)
-#define BIT_RTL_ID_8822B BIT(23)
-#define BIT_PAD_HWPD_IDN_8822B BIT(22)
-#define BIT_TESTMODE_8822B BIT(20)
-
-#define BIT_SHIFT_VENDOR_ID_8822B 16
-#define BIT_MASK_VENDOR_ID_8822B 0xf
-#define BIT_VENDOR_ID_8822B(x) \
- (((x) & BIT_MASK_VENDOR_ID_8822B) << BIT_SHIFT_VENDOR_ID_8822B)
-#define BIT_GET_VENDOR_ID_8822B(x) \
- (((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B)
-
-#define BIT_SHIFT_CHIP_VER_8822B 12
-#define BIT_MASK_CHIP_VER_8822B 0xf
-#define BIT_CHIP_VER_8822B(x) \
- (((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B)
-#define BIT_GET_CHIP_VER_8822B(x) \
- (((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B)
-
-#define BIT_BD_MAC3_8822B BIT(11)
-#define BIT_BD_MAC1_8822B BIT(10)
-#define BIT_BD_MAC2_8822B BIT(9)
-#define BIT_SIC_IDLE_8822B BIT(8)
-#define BIT_SW_OFFLOAD_EN_8822B BIT(7)
-#define BIT_OCP_SHUTDN_8822B BIT(6)
-#define BIT_V15_VLD_8822B BIT(5)
-#define BIT_PCIRSTB_8822B BIT(4)
-#define BIT_PCLK_VLD_8822B BIT(3)
-#define BIT_UCLK_VLD_8822B BIT(2)
-#define BIT_ACLK_VLD_8822B BIT(1)
-#define BIT_XCLK_VLD_8822B BIT(0)
-
-/* 2 REG_SYS_STATUS1_8822B */
-
-#define BIT_SHIFT_RF_RL_ID_8822B 28
-#define BIT_MASK_RF_RL_ID_8822B 0xf
-#define BIT_RF_RL_ID_8822B(x) \
- (((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B)
-#define BIT_GET_RF_RL_ID_8822B(x) \
- (((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B)
-
-#define BIT_HPHY_ICFG_8822B BIT(19)
-
-#define BIT_SHIFT_SEL_0XC0_8822B 16
-#define BIT_MASK_SEL_0XC0_8822B 0x3
-#define BIT_SEL_0XC0_8822B(x) \
- (((x) & BIT_MASK_SEL_0XC0_8822B) << BIT_SHIFT_SEL_0XC0_8822B)
-#define BIT_GET_SEL_0XC0_8822B(x) \
- (((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B)
-
-#define BIT_SHIFT_HCI_SEL_V3_8822B 12
-#define BIT_MASK_HCI_SEL_V3_8822B 0x7
-#define BIT_HCI_SEL_V3_8822B(x) \
- (((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B)
-#define BIT_GET_HCI_SEL_V3_8822B(x) \
- (((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B)
-
-#define BIT_USB_OPERATION_MODE_8822B BIT(10)
-#define BIT_BT_PDN_8822B BIT(9)
-#define BIT_AUTO_WLPON_8822B BIT(8)
-#define BIT_WL_MODE_8822B BIT(7)
-#define BIT_PKG_SEL_HCI_8822B BIT(6)
-
-#define BIT_SHIFT_PAD_HCI_SEL_V1_8822B 3
-#define BIT_MASK_PAD_HCI_SEL_V1_8822B 0x7
-#define BIT_PAD_HCI_SEL_V1_8822B(x) \
- (((x) & BIT_MASK_PAD_HCI_SEL_V1_8822B) \
- << BIT_SHIFT_PAD_HCI_SEL_V1_8822B)
-#define BIT_GET_PAD_HCI_SEL_V1_8822B(x) \
- (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) & \
- BIT_MASK_PAD_HCI_SEL_V1_8822B)
-
-#define BIT_SHIFT_EFS_HCI_SEL_V1_8822B 0
-#define BIT_MASK_EFS_HCI_SEL_V1_8822B 0x7
-#define BIT_EFS_HCI_SEL_V1_8822B(x) \
- (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B) \
- << BIT_SHIFT_EFS_HCI_SEL_V1_8822B)
-#define BIT_GET_EFS_HCI_SEL_V1_8822B(x) \
- (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) & \
- BIT_MASK_EFS_HCI_SEL_V1_8822B)
-
-/* 2 REG_SYS_STATUS2_8822B */
-#define BIT_SIO_ALDN_8822B BIT(19)
-#define BIT_USB_ALDN_8822B BIT(18)
-#define BIT_PCI_ALDN_8822B BIT(17)
-#define BIT_SYS_ALDN_8822B BIT(16)
-
-#define BIT_SHIFT_EPVID1_8822B 8
-#define BIT_MASK_EPVID1_8822B 0xff
-#define BIT_EPVID1_8822B(x) \
- (((x) & BIT_MASK_EPVID1_8822B) << BIT_SHIFT_EPVID1_8822B)
-#define BIT_GET_EPVID1_8822B(x) \
- (((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B)
-
-#define BIT_SHIFT_EPVID0_8822B 0
-#define BIT_MASK_EPVID0_8822B 0xff
-#define BIT_EPVID0_8822B(x) \
- (((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B)
-#define BIT_GET_EPVID0_8822B(x) \
- (((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B)
-
-/* 2 REG_SYS_CFG2_8822B */
-#define BIT_HCI_SEL_EMBEDDED_8822B BIT(8)
-
-#define BIT_SHIFT_HW_ID_8822B 0
-#define BIT_MASK_HW_ID_8822B 0xff
-#define BIT_HW_ID_8822B(x) \
- (((x) & BIT_MASK_HW_ID_8822B) << BIT_SHIFT_HW_ID_8822B)
-#define BIT_GET_HW_ID_8822B(x) \
- (((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B)
-
-/* 2 REG_SYS_CFG3_8822B */
-#define BIT_PWC_MA33V_8822B BIT(15)
-#define BIT_PWC_MA12V_8822B BIT(14)
-#define BIT_PWC_MD12V_8822B BIT(13)
-#define BIT_PWC_PD12V_8822B BIT(12)
-#define BIT_PWC_UD12V_8822B BIT(11)
-#define BIT_ISO_MA2MD_8822B BIT(1)
-#define BIT_ISO_MD2PP_8822B BIT(0)
-
-/* 2 REG_SYS_CFG4_8822B */
-
-/* 2 REG_SYS_CFG5_8822B */
-#define BIT_LPS_STATUS_8822B BIT(3)
-#define BIT_HCI_TXDMA_BUSY_8822B BIT(2)
-#define BIT_HCI_TXDMA_ALLOW_8822B BIT(1)
-#define BIT_FW_CTRL_HCI_TXDMA_EN_8822B BIT(0)
-
-/* 2 REG_CPU_DMEM_CON_8822B */
-#define BIT_WDT_OPT_IOWRAPPER_8822B BIT(19)
-#define BIT_ANA_PORT_IDLE_8822B BIT(18)
-#define BIT_MAC_PORT_IDLE_8822B BIT(17)
-#define BIT_WL_PLATFORM_RST_8822B BIT(16)
-#define BIT_WL_SECURITY_CLK_8822B BIT(15)
-
-#define BIT_SHIFT_CPU_DMEM_CON_8822B 0
-#define BIT_MASK_CPU_DMEM_CON_8822B 0xff
-#define BIT_CPU_DMEM_CON_8822B(x) \
- (((x) & BIT_MASK_CPU_DMEM_CON_8822B) << BIT_SHIFT_CPU_DMEM_CON_8822B)
-#define BIT_GET_CPU_DMEM_CON_8822B(x) \
- (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B)
-
-/* 2 REG_BOOT_REASON_8822B */
-
-#define BIT_SHIFT_BOOT_REASON_8822B 0
-#define BIT_MASK_BOOT_REASON_8822B 0x7
-#define BIT_BOOT_REASON_8822B(x) \
- (((x) & BIT_MASK_BOOT_REASON_8822B) << BIT_SHIFT_BOOT_REASON_8822B)
-#define BIT_GET_BOOT_REASON_8822B(x) \
- (((x) >> BIT_SHIFT_BOOT_REASON_8822B) & BIT_MASK_BOOT_REASON_8822B)
-
-/* 2 REG_NFCPAD_CTRL_8822B */
-#define BIT_PAD_SHUTDW_8822B BIT(18)
-#define BIT_SYSON_NFC_PAD_8822B BIT(17)
-#define BIT_NFC_INT_PAD_CTRL_8822B BIT(16)
-#define BIT_NFC_RFDIS_PAD_CTRL_8822B BIT(15)
-#define BIT_NFC_CLK_PAD_CTRL_8822B BIT(14)
-#define BIT_NFC_DATA_PAD_CTRL_8822B BIT(13)
-#define BIT_NFC_PAD_PULL_CTRL_8822B BIT(12)
-
-#define BIT_SHIFT_NFCPAD_IO_SEL_8822B 8
-#define BIT_MASK_NFCPAD_IO_SEL_8822B 0xf
-#define BIT_NFCPAD_IO_SEL_8822B(x) \
- (((x) & BIT_MASK_NFCPAD_IO_SEL_8822B) << BIT_SHIFT_NFCPAD_IO_SEL_8822B)
-#define BIT_GET_NFCPAD_IO_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B)
-
-#define BIT_SHIFT_NFCPAD_OUT_8822B 4
-#define BIT_MASK_NFCPAD_OUT_8822B 0xf
-#define BIT_NFCPAD_OUT_8822B(x) \
- (((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B)
-#define BIT_GET_NFCPAD_OUT_8822B(x) \
- (((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B)
-
-#define BIT_SHIFT_NFCPAD_IN_8822B 0
-#define BIT_MASK_NFCPAD_IN_8822B 0xf
-#define BIT_NFCPAD_IN_8822B(x) \
- (((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B)
-#define BIT_GET_NFCPAD_IN_8822B(x) \
- (((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B)
-
-/* 2 REG_HIMR2_8822B */
-#define BIT_BCNDMAINT_P4_MSK_8822B BIT(31)
-#define BIT_BCNDMAINT_P3_MSK_8822B BIT(30)
-#define BIT_BCNDMAINT_P2_MSK_8822B BIT(29)
-#define BIT_BCNDMAINT_P1_MSK_8822B BIT(28)
-#define BIT_ATIMEND7_MSK_8822B BIT(22)
-#define BIT_ATIMEND6_MSK_8822B BIT(21)
-#define BIT_ATIMEND5_MSK_8822B BIT(20)
-#define BIT_ATIMEND4_MSK_8822B BIT(19)
-#define BIT_ATIMEND3_MSK_8822B BIT(18)
-#define BIT_ATIMEND2_MSK_8822B BIT(17)
-#define BIT_ATIMEND1_MSK_8822B BIT(16)
-#define BIT_TXBCN7OK_MSK_8822B BIT(14)
-#define BIT_TXBCN6OK_MSK_8822B BIT(13)
-#define BIT_TXBCN5OK_MSK_8822B BIT(12)
-#define BIT_TXBCN4OK_MSK_8822B BIT(11)
-#define BIT_TXBCN3OK_MSK_8822B BIT(10)
-#define BIT_TXBCN2OK_MSK_8822B BIT(9)
-#define BIT_TXBCN1OK_MSK_V1_8822B BIT(8)
-#define BIT_TXBCN7ERR_MSK_8822B BIT(6)
-#define BIT_TXBCN6ERR_MSK_8822B BIT(5)
-#define BIT_TXBCN5ERR_MSK_8822B BIT(4)
-#define BIT_TXBCN4ERR_MSK_8822B BIT(3)
-#define BIT_TXBCN3ERR_MSK_8822B BIT(2)
-#define BIT_TXBCN2ERR_MSK_8822B BIT(1)
-#define BIT_TXBCN1ERR_MSK_V1_8822B BIT(0)
-
-/* 2 REG_HISR2_8822B */
-#define BIT_BCNDMAINT_P4_8822B BIT(31)
-#define BIT_BCNDMAINT_P3_8822B BIT(30)
-#define BIT_BCNDMAINT_P2_8822B BIT(29)
-#define BIT_BCNDMAINT_P1_8822B BIT(28)
-#define BIT_ATIMEND7_8822B BIT(22)
-#define BIT_ATIMEND6_8822B BIT(21)
-#define BIT_ATIMEND5_8822B BIT(20)
-#define BIT_ATIMEND4_8822B BIT(19)
-#define BIT_ATIMEND3_8822B BIT(18)
-#define BIT_ATIMEND2_8822B BIT(17)
-#define BIT_ATIMEND1_8822B BIT(16)
-#define BIT_TXBCN7OK_8822B BIT(14)
-#define BIT_TXBCN6OK_8822B BIT(13)
-#define BIT_TXBCN5OK_8822B BIT(12)
-#define BIT_TXBCN4OK_8822B BIT(11)
-#define BIT_TXBCN3OK_8822B BIT(10)
-#define BIT_TXBCN2OK_8822B BIT(9)
-#define BIT_TXBCN1OK_8822B BIT(8)
-#define BIT_TXBCN7ERR_8822B BIT(6)
-#define BIT_TXBCN6ERR_8822B BIT(5)
-#define BIT_TXBCN5ERR_8822B BIT(4)
-#define BIT_TXBCN4ERR_8822B BIT(3)
-#define BIT_TXBCN3ERR_8822B BIT(2)
-#define BIT_TXBCN2ERR_8822B BIT(1)
-#define BIT_TXBCN1ERR_8822B BIT(0)
-
-/* 2 REG_HIMR3_8822B */
-#define BIT_WDT_PLATFORM_INT_MSK_8822B BIT(18)
-#define BIT_WDT_CPU_INT_MSK_8822B BIT(17)
-#define BIT_SETH2CDOK_MASK_8822B BIT(16)
-#define BIT_H2C_CMD_FULL_MASK_8822B BIT(15)
-#define BIT_PWR_INT_127_MASK_8822B BIT(14)
-#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8822B BIT(13)
-#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8822B BIT(12)
-#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8822B BIT(11)
-#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8822B BIT(10)
-#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8822B BIT(9)
-#define BIT_PWR_INT_127_MASK_V1_8822B BIT(8)
-#define BIT_PWR_INT_126TO96_MASK_8822B BIT(7)
-#define BIT_PWR_INT_95TO64_MASK_8822B BIT(6)
-#define BIT_PWR_INT_63TO32_MASK_8822B BIT(5)
-#define BIT_PWR_INT_31TO0_MASK_8822B BIT(4)
-#define BIT_DDMA0_LP_INT_MSK_8822B BIT(1)
-#define BIT_DDMA0_HP_INT_MSK_8822B BIT(0)
-
-/* 2 REG_HISR3_8822B */
-#define BIT_WDT_PLATFORM_INT_8822B BIT(18)
-#define BIT_WDT_CPU_INT_8822B BIT(17)
-#define BIT_SETH2CDOK_8822B BIT(16)
-#define BIT_H2C_CMD_FULL_8822B BIT(15)
-#define BIT_PWR_INT_127_8822B BIT(14)
-#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822B BIT(13)
-#define BIT_TXSHORTCUT_BKUPDATEOK_8822B BIT(12)
-#define BIT_TXSHORTCUT_BEUPDATEOK_8822B BIT(11)
-#define BIT_TXSHORTCUT_VIUPDATEOK_8822B BIT(10)
-#define BIT_TXSHORTCUT_VOUPDATEOK_8822B BIT(9)
-#define BIT_PWR_INT_127_V1_8822B BIT(8)
-#define BIT_PWR_INT_126TO96_8822B BIT(7)
-#define BIT_PWR_INT_95TO64_8822B BIT(6)
-#define BIT_PWR_INT_63TO32_8822B BIT(5)
-#define BIT_PWR_INT_31TO0_8822B BIT(4)
-#define BIT_DDMA0_LP_INT_8822B BIT(1)
-#define BIT_DDMA0_HP_INT_8822B BIT(0)
-
-/* 2 REG_SW_MDIO_8822B */
-#define BIT_DIS_TIMEOUT_IO_8822B BIT(24)
-
-/* 2 REG_SW_FLUSH_8822B */
-#define BIT_FLUSH_HOLDN_EN_8822B BIT(25)
-#define BIT_FLUSH_WR_EN_8822B BIT(24)
-#define BIT_SW_FLASH_CONTROL_8822B BIT(23)
-#define BIT_SW_FLASH_WEN_E_8822B BIT(19)
-#define BIT_SW_FLASH_HOLDN_E_8822B BIT(18)
-#define BIT_SW_FLASH_SO_E_8822B BIT(17)
-#define BIT_SW_FLASH_SI_E_8822B BIT(16)
-#define BIT_SW_FLASH_SK_O_8822B BIT(13)
-#define BIT_SW_FLASH_CEN_O_8822B BIT(12)
-#define BIT_SW_FLASH_WEN_O_8822B BIT(11)
-#define BIT_SW_FLASH_HOLDN_O_8822B BIT(10)
-#define BIT_SW_FLASH_SO_O_8822B BIT(9)
-#define BIT_SW_FLASH_SI_O_8822B BIT(8)
-#define BIT_SW_FLASH_WEN_I_8822B BIT(3)
-#define BIT_SW_FLASH_HOLDN_I_8822B BIT(2)
-#define BIT_SW_FLASH_SO_I_8822B BIT(1)
-#define BIT_SW_FLASH_SI_I_8822B BIT(0)
-
-/* 2 REG_H2C_PKT_READADDR_8822B */
-
-#define BIT_SHIFT_H2C_PKT_READADDR_8822B 0
-#define BIT_MASK_H2C_PKT_READADDR_8822B 0x3ffff
-#define BIT_H2C_PKT_READADDR_8822B(x) \
- (((x) & BIT_MASK_H2C_PKT_READADDR_8822B) \
- << BIT_SHIFT_H2C_PKT_READADDR_8822B)
-#define BIT_GET_H2C_PKT_READADDR_8822B(x) \
- (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) & \
- BIT_MASK_H2C_PKT_READADDR_8822B)
-
-/* 2 REG_H2C_PKT_WRITEADDR_8822B */
-
-#define BIT_SHIFT_H2C_PKT_WRITEADDR_8822B 0
-#define BIT_MASK_H2C_PKT_WRITEADDR_8822B 0x3ffff
-#define BIT_H2C_PKT_WRITEADDR_8822B(x) \
- (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) \
- << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B)
-#define BIT_GET_H2C_PKT_WRITEADDR_8822B(x) \
- (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) & \
- BIT_MASK_H2C_PKT_WRITEADDR_8822B)
-
-/* 2 REG_MEM_PWR_CRTL_8822B */
-#define BIT_MEM_BB_SD_8822B BIT(17)
-#define BIT_MEM_BB_DS_8822B BIT(16)
-#define BIT_MEM_BT_DS_8822B BIT(10)
-#define BIT_MEM_SDIO_LS_8822B BIT(9)
-#define BIT_MEM_SDIO_DS_8822B BIT(8)
-#define BIT_MEM_USB_LS_8822B BIT(7)
-#define BIT_MEM_USB_DS_8822B BIT(6)
-#define BIT_MEM_PCI_LS_8822B BIT(5)
-#define BIT_MEM_PCI_DS_8822B BIT(4)
-#define BIT_MEM_WLMAC_LS_8822B BIT(3)
-#define BIT_MEM_WLMAC_DS_8822B BIT(2)
-#define BIT_MEM_WLMCU_LS_8822B BIT(1)
-#define BIT_MEM_WLMCU_DS_8822B BIT(0)
-
-/* 2 REG_FW_DBG0_8822B */
-
-#define BIT_SHIFT_FW_DBG0_8822B 0
-#define BIT_MASK_FW_DBG0_8822B 0xffffffffL
-#define BIT_FW_DBG0_8822B(x) \
- (((x) & BIT_MASK_FW_DBG0_8822B) << BIT_SHIFT_FW_DBG0_8822B)
-#define BIT_GET_FW_DBG0_8822B(x) \
- (((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B)
-
-/* 2 REG_FW_DBG1_8822B */
-
-#define BIT_SHIFT_FW_DBG1_8822B 0
-#define BIT_MASK_FW_DBG1_8822B 0xffffffffL
-#define BIT_FW_DBG1_8822B(x) \
- (((x) & BIT_MASK_FW_DBG1_8822B) << BIT_SHIFT_FW_DBG1_8822B)
-#define BIT_GET_FW_DBG1_8822B(x) \
- (((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B)
-
-/* 2 REG_FW_DBG2_8822B */
-
-#define BIT_SHIFT_FW_DBG2_8822B 0
-#define BIT_MASK_FW_DBG2_8822B 0xffffffffL
-#define BIT_FW_DBG2_8822B(x) \
- (((x) & BIT_MASK_FW_DBG2_8822B) << BIT_SHIFT_FW_DBG2_8822B)
-#define BIT_GET_FW_DBG2_8822B(x) \
- (((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B)
-
-/* 2 REG_FW_DBG3_8822B */
-
-#define BIT_SHIFT_FW_DBG3_8822B 0
-#define BIT_MASK_FW_DBG3_8822B 0xffffffffL
-#define BIT_FW_DBG3_8822B(x) \
- (((x) & BIT_MASK_FW_DBG3_8822B) << BIT_SHIFT_FW_DBG3_8822B)
-#define BIT_GET_FW_DBG3_8822B(x) \
- (((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B)
-
-/* 2 REG_FW_DBG4_8822B */
-
-#define BIT_SHIFT_FW_DBG4_8822B 0
-#define BIT_MASK_FW_DBG4_8822B 0xffffffffL
-#define BIT_FW_DBG4_8822B(x) \
- (((x) & BIT_MASK_FW_DBG4_8822B) << BIT_SHIFT_FW_DBG4_8822B)
-#define BIT_GET_FW_DBG4_8822B(x) \
- (((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B)
-
-/* 2 REG_FW_DBG5_8822B */
-
-#define BIT_SHIFT_FW_DBG5_8822B 0
-#define BIT_MASK_FW_DBG5_8822B 0xffffffffL
-#define BIT_FW_DBG5_8822B(x) \
- (((x) & BIT_MASK_FW_DBG5_8822B) << BIT_SHIFT_FW_DBG5_8822B)
-#define BIT_GET_FW_DBG5_8822B(x) \
- (((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B)
-
-/* 2 REG_FW_DBG6_8822B */
-
-#define BIT_SHIFT_FW_DBG6_8822B 0
-#define BIT_MASK_FW_DBG6_8822B 0xffffffffL
-#define BIT_FW_DBG6_8822B(x) \
- (((x) & BIT_MASK_FW_DBG6_8822B) << BIT_SHIFT_FW_DBG6_8822B)
-#define BIT_GET_FW_DBG6_8822B(x) \
- (((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B)
-
-/* 2 REG_FW_DBG7_8822B */
-
-#define BIT_SHIFT_FW_DBG7_8822B 0
-#define BIT_MASK_FW_DBG7_8822B 0xffffffffL
-#define BIT_FW_DBG7_8822B(x) \
- (((x) & BIT_MASK_FW_DBG7_8822B) << BIT_SHIFT_FW_DBG7_8822B)
-#define BIT_GET_FW_DBG7_8822B(x) \
- (((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_CR_8822B */
-
-#define BIT_SHIFT_LBMODE_8822B 24
-#define BIT_MASK_LBMODE_8822B 0x1f
-#define BIT_LBMODE_8822B(x) \
- (((x) & BIT_MASK_LBMODE_8822B) << BIT_SHIFT_LBMODE_8822B)
-#define BIT_GET_LBMODE_8822B(x) \
- (((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B)
-
-#define BIT_SHIFT_NETYPE1_8822B 18
-#define BIT_MASK_NETYPE1_8822B 0x3
-#define BIT_NETYPE1_8822B(x) \
- (((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B)
-#define BIT_GET_NETYPE1_8822B(x) \
- (((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B)
-
-#define BIT_SHIFT_NETYPE0_8822B 16
-#define BIT_MASK_NETYPE0_8822B 0x3
-#define BIT_NETYPE0_8822B(x) \
- (((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B)
-#define BIT_GET_NETYPE0_8822B(x) \
- (((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B)
-
-#define BIT_I2C_MAILBOX_EN_8822B BIT(12)
-#define BIT_SHCUT_EN_8822B BIT(11)
-#define BIT_32K_CAL_TMR_EN_8822B BIT(10)
-#define BIT_MAC_SEC_EN_8822B BIT(9)
-#define BIT_ENSWBCN_8822B BIT(8)
-#define BIT_MACRXEN_8822B BIT(7)
-#define BIT_MACTXEN_8822B BIT(6)
-#define BIT_SCHEDULE_EN_8822B BIT(5)
-#define BIT_PROTOCOL_EN_8822B BIT(4)
-#define BIT_RXDMA_EN_8822B BIT(3)
-#define BIT_TXDMA_EN_8822B BIT(2)
-#define BIT_HCI_RXDMA_EN_8822B BIT(1)
-#define BIT_HCI_TXDMA_EN_8822B BIT(0)
-
-/* 2 REG_PKT_BUFF_ACCESS_CTRL_8822B */
-
-#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B 0
-#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B 0xff
-#define BIT_PKT_BUFF_ACCESS_CTRL_8822B(x) \
- (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B) \
- << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B)
-#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8822B(x) \
- (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B) & \
- BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B)
-
-/* 2 REG_TSF_CLK_STATE_8822B */
-#define BIT_TSF_CLK_STABLE_8822B BIT(15)
-
-/* 2 REG_TXDMA_PQ_MAP_8822B */
-
-#define BIT_SHIFT_TXDMA_HIQ_MAP_8822B 14
-#define BIT_MASK_TXDMA_HIQ_MAP_8822B 0x3
-#define BIT_TXDMA_HIQ_MAP_8822B(x) \
- (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822B) << BIT_SHIFT_TXDMA_HIQ_MAP_8822B)
-#define BIT_GET_TXDMA_HIQ_MAP_8822B(x) \
- (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B)
-
-#define BIT_SHIFT_TXDMA_MGQ_MAP_8822B 12
-#define BIT_MASK_TXDMA_MGQ_MAP_8822B 0x3
-#define BIT_TXDMA_MGQ_MAP_8822B(x) \
- (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B)
-#define BIT_GET_TXDMA_MGQ_MAP_8822B(x) \
- (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B)
-
-#define BIT_SHIFT_TXDMA_BKQ_MAP_8822B 10
-#define BIT_MASK_TXDMA_BKQ_MAP_8822B 0x3
-#define BIT_TXDMA_BKQ_MAP_8822B(x) \
- (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B)
-#define BIT_GET_TXDMA_BKQ_MAP_8822B(x) \
- (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B)
-
-#define BIT_SHIFT_TXDMA_BEQ_MAP_8822B 8
-#define BIT_MASK_TXDMA_BEQ_MAP_8822B 0x3
-#define BIT_TXDMA_BEQ_MAP_8822B(x) \
- (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B)
-#define BIT_GET_TXDMA_BEQ_MAP_8822B(x) \
- (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B)
-
-#define BIT_SHIFT_TXDMA_VIQ_MAP_8822B 6
-#define BIT_MASK_TXDMA_VIQ_MAP_8822B 0x3
-#define BIT_TXDMA_VIQ_MAP_8822B(x) \
- (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B)
-#define BIT_GET_TXDMA_VIQ_MAP_8822B(x) \
- (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B)
-
-#define BIT_SHIFT_TXDMA_VOQ_MAP_8822B 4
-#define BIT_MASK_TXDMA_VOQ_MAP_8822B 0x3
-#define BIT_TXDMA_VOQ_MAP_8822B(x) \
- (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B)
-#define BIT_GET_TXDMA_VOQ_MAP_8822B(x) \
- (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B)
-
-#define BIT_RXDMA_AGG_EN_8822B BIT(2)
-#define BIT_RXSHFT_EN_8822B BIT(1)
-#define BIT_RXDMA_ARBBW_EN_8822B BIT(0)
-
-/* 2 REG_TRXFF_BNDY_8822B */
-
-#define BIT_SHIFT_RXFFOVFL_RSV_V2_8822B 8
-#define BIT_MASK_RXFFOVFL_RSV_V2_8822B 0xf
-#define BIT_RXFFOVFL_RSV_V2_8822B(x) \
- (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) \
- << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B)
-#define BIT_GET_RXFFOVFL_RSV_V2_8822B(x) \
- (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) & \
- BIT_MASK_RXFFOVFL_RSV_V2_8822B)
-
-#define BIT_SHIFT_TXPKTBUF_PGBNDY_8822B 0
-#define BIT_MASK_TXPKTBUF_PGBNDY_8822B 0xff
-#define BIT_TXPKTBUF_PGBNDY_8822B(x) \
- (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) \
- << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B)
-#define BIT_GET_TXPKTBUF_PGBNDY_8822B(x) \
- (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) & \
- BIT_MASK_TXPKTBUF_PGBNDY_8822B)
-
-/* 2 REG_PTA_I2C_MBOX_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_I2C_M_STATUS_8822B 8
-#define BIT_MASK_I2C_M_STATUS_8822B 0xf
-#define BIT_I2C_M_STATUS_8822B(x) \
- (((x) & BIT_MASK_I2C_M_STATUS_8822B) << BIT_SHIFT_I2C_M_STATUS_8822B)
-#define BIT_GET_I2C_M_STATUS_8822B(x) \
- (((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B)
-
-#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B 4
-#define BIT_MASK_I2C_M_BUS_GNT_FW_8822B 0x7
-#define BIT_I2C_M_BUS_GNT_FW_8822B(x) \
- (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) \
- << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B)
-#define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x) \
- (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) & \
- BIT_MASK_I2C_M_BUS_GNT_FW_8822B)
-
-#define BIT_I2C_M_GNT_FW_8822B BIT(3)
-
-#define BIT_SHIFT_I2C_M_SPEED_8822B 1
-#define BIT_MASK_I2C_M_SPEED_8822B 0x3
-#define BIT_I2C_M_SPEED_8822B(x) \
- (((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B)
-#define BIT_GET_I2C_M_SPEED_8822B(x) \
- (((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B)
-
-#define BIT_I2C_M_UNLOCK_8822B BIT(0)
-
-/* 2 REG_RXFF_BNDY_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_RXFF0_BNDY_V2_8822B 0
-#define BIT_MASK_RXFF0_BNDY_V2_8822B 0x3ffff
-#define BIT_RXFF0_BNDY_V2_8822B(x) \
- (((x) & BIT_MASK_RXFF0_BNDY_V2_8822B) << BIT_SHIFT_RXFF0_BNDY_V2_8822B)
-#define BIT_GET_RXFF0_BNDY_V2_8822B(x) \
- (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B)
-
-/* 2 REG_FE1IMR_8822B */
-#define BIT_FS_RXDMA2_DONE_INT_EN_8822B BIT(28)
-#define BIT_FS_RXDONE3_INT_EN_8822B BIT(27)
-#define BIT_FS_RXDONE2_INT_EN_8822B BIT(26)
-#define BIT_FS_RX_BCN_P4_INT_EN_8822B BIT(25)
-#define BIT_FS_RX_BCN_P3_INT_EN_8822B BIT(24)
-#define BIT_FS_RX_BCN_P2_INT_EN_8822B BIT(23)
-#define BIT_FS_RX_BCN_P1_INT_EN_8822B BIT(22)
-#define BIT_FS_RX_BCN_P0_INT_EN_8822B BIT(21)
-#define BIT_FS_RX_UMD0_INT_EN_8822B BIT(20)
-#define BIT_FS_RX_UMD1_INT_EN_8822B BIT(19)
-#define BIT_FS_RX_BMD0_INT_EN_8822B BIT(18)
-#define BIT_FS_RX_BMD1_INT_EN_8822B BIT(17)
-#define BIT_FS_RXDONE_INT_EN_8822B BIT(16)
-#define BIT_FS_WWLAN_INT_EN_8822B BIT(15)
-#define BIT_FS_SOUND_DONE_INT_EN_8822B BIT(14)
-#define BIT_FS_LP_STBY_INT_EN_8822B BIT(13)
-#define BIT_FS_TRL_MTR_INT_EN_8822B BIT(12)
-#define BIT_FS_BF1_PRETO_INT_EN_8822B BIT(11)
-#define BIT_FS_BF0_PRETO_INT_EN_8822B BIT(10)
-#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8822B BIT(9)
-#define BIT_FS_LTE_COEX_EN_8822B BIT(6)
-#define BIT_FS_WLACTOFF_INT_EN_8822B BIT(5)
-#define BIT_FS_WLACTON_INT_EN_8822B BIT(4)
-#define BIT_FS_BTCMD_INT_EN_8822B BIT(3)
-#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8822B BIT(2)
-#define BIT_FS_TRPC_TO_INT_EN_V1_8822B BIT(1)
-#define BIT_FS_RPC_O_T_INT_EN_V1_8822B BIT(0)
-
-/* 2 REG_FE1ISR_8822B */
-#define BIT_FS_RXDMA2_DONE_INT_8822B BIT(28)
-#define BIT_FS_RXDONE3_INT_8822B BIT(27)
-#define BIT_FS_RXDONE2_INT_8822B BIT(26)
-#define BIT_FS_RX_BCN_P4_INT_8822B BIT(25)
-#define BIT_FS_RX_BCN_P3_INT_8822B BIT(24)
-#define BIT_FS_RX_BCN_P2_INT_8822B BIT(23)
-#define BIT_FS_RX_BCN_P1_INT_8822B BIT(22)
-#define BIT_FS_RX_BCN_P0_INT_8822B BIT(21)
-#define BIT_FS_RX_UMD0_INT_8822B BIT(20)
-#define BIT_FS_RX_UMD1_INT_8822B BIT(19)
-#define BIT_FS_RX_BMD0_INT_8822B BIT(18)
-#define BIT_FS_RX_BMD1_INT_8822B BIT(17)
-#define BIT_FS_RXDONE_INT_8822B BIT(16)
-#define BIT_FS_WWLAN_INT_8822B BIT(15)
-#define BIT_FS_SOUND_DONE_INT_8822B BIT(14)
-#define BIT_FS_LP_STBY_INT_8822B BIT(13)
-#define BIT_FS_TRL_MTR_INT_8822B BIT(12)
-#define BIT_FS_BF1_PRETO_INT_8822B BIT(11)
-#define BIT_FS_BF0_PRETO_INT_8822B BIT(10)
-#define BIT_FS_PTCL_RELEASE_MACID_INT_8822B BIT(9)
-#define BIT_FS_LTE_COEX_INT_8822B BIT(6)
-#define BIT_FS_WLACTOFF_INT_8822B BIT(5)
-#define BIT_FS_WLACTON_INT_8822B BIT(4)
-#define BIT_FS_BCN_RX_INT_INT_8822B BIT(3)
-#define BIT_FS_MAILBOX_TO_I2C_INT_8822B BIT(2)
-#define BIT_FS_TRPC_TO_INT_8822B BIT(1)
-#define BIT_FS_RPC_O_T_INT_8822B BIT(0)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_CPWM_8822B */
-#define BIT_CPWM_TOGGLING_8822B BIT(31)
-
-#define BIT_SHIFT_CPWM_MOD_8822B 24
-#define BIT_MASK_CPWM_MOD_8822B 0x7f
-#define BIT_CPWM_MOD_8822B(x) \
- (((x) & BIT_MASK_CPWM_MOD_8822B) << BIT_SHIFT_CPWM_MOD_8822B)
-#define BIT_GET_CPWM_MOD_8822B(x) \
- (((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B)
-
-/* 2 REG_FWIMR_8822B */
-#define BIT_FS_TXBCNOK_MB7_INT_EN_8822B BIT(31)
-#define BIT_FS_TXBCNOK_MB6_INT_EN_8822B BIT(30)
-#define BIT_FS_TXBCNOK_MB5_INT_EN_8822B BIT(29)
-#define BIT_FS_TXBCNOK_MB4_INT_EN_8822B BIT(28)
-#define BIT_FS_TXBCNOK_MB3_INT_EN_8822B BIT(27)
-#define BIT_FS_TXBCNOK_MB2_INT_EN_8822B BIT(26)
-#define BIT_FS_TXBCNOK_MB1_INT_EN_8822B BIT(25)
-#define BIT_FS_TXBCNOK_MB0_INT_EN_8822B BIT(24)
-#define BIT_FS_TXBCNERR_MB7_INT_EN_8822B BIT(23)
-#define BIT_FS_TXBCNERR_MB6_INT_EN_8822B BIT(22)
-#define BIT_FS_TXBCNERR_MB5_INT_EN_8822B BIT(21)
-#define BIT_FS_TXBCNERR_MB4_INT_EN_8822B BIT(20)
-#define BIT_FS_TXBCNERR_MB3_INT_EN_8822B BIT(19)
-#define BIT_FS_TXBCNERR_MB2_INT_EN_8822B BIT(18)
-#define BIT_FS_TXBCNERR_MB1_INT_EN_8822B BIT(17)
-#define BIT_FS_TXBCNERR_MB0_INT_EN_8822B BIT(16)
-#define BIT_CPU_MGQ_TXDONE_INT_EN_8822B BIT(15)
-#define BIT_SIFS_OVERSPEC_INT_EN_8822B BIT(14)
-#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822B BIT(13)
-#define BIT_FS_MGNTQFF_TO_INT_EN_8822B BIT(12)
-#define BIT_FS_DDMA1_LP_INT_EN_8822B BIT(11)
-#define BIT_FS_DDMA1_HP_INT_EN_8822B BIT(10)
-#define BIT_FS_DDMA0_LP_INT_EN_8822B BIT(9)
-#define BIT_FS_DDMA0_HP_INT_EN_8822B BIT(8)
-#define BIT_FS_TRXRPT_INT_EN_8822B BIT(7)
-#define BIT_FS_C2H_W_READY_INT_EN_8822B BIT(6)
-#define BIT_FS_HRCV_INT_EN_8822B BIT(5)
-#define BIT_FS_H2CCMD_INT_EN_8822B BIT(4)
-#define BIT_FS_TXPKTIN_INT_EN_8822B BIT(3)
-#define BIT_FS_ERRORHDL_INT_EN_8822B BIT(2)
-#define BIT_FS_TXCCX_INT_EN_8822B BIT(1)
-#define BIT_FS_TXCLOSE_INT_EN_8822B BIT(0)
-
-/* 2 REG_FWISR_8822B */
-#define BIT_FS_TXBCNOK_MB7_INT_8822B BIT(31)
-#define BIT_FS_TXBCNOK_MB6_INT_8822B BIT(30)
-#define BIT_FS_TXBCNOK_MB5_INT_8822B BIT(29)
-#define BIT_FS_TXBCNOK_MB4_INT_8822B BIT(28)
-#define BIT_FS_TXBCNOK_MB3_INT_8822B BIT(27)
-#define BIT_FS_TXBCNOK_MB2_INT_8822B BIT(26)
-#define BIT_FS_TXBCNOK_MB1_INT_8822B BIT(25)
-#define BIT_FS_TXBCNOK_MB0_INT_8822B BIT(24)
-#define BIT_FS_TXBCNERR_MB7_INT_8822B BIT(23)
-#define BIT_FS_TXBCNERR_MB6_INT_8822B BIT(22)
-#define BIT_FS_TXBCNERR_MB5_INT_8822B BIT(21)
-#define BIT_FS_TXBCNERR_MB4_INT_8822B BIT(20)
-#define BIT_FS_TXBCNERR_MB3_INT_8822B BIT(19)
-#define BIT_FS_TXBCNERR_MB2_INT_8822B BIT(18)
-#define BIT_FS_TXBCNERR_MB1_INT_8822B BIT(17)
-#define BIT_FS_TXBCNERR_MB0_INT_8822B BIT(16)
-#define BIT_CPU_MGQ_TXDONE_INT_8822B BIT(15)
-#define BIT_SIFS_OVERSPEC_INT_8822B BIT(14)
-#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822B BIT(13)
-#define BIT_FS_MGNTQFF_TO_INT_8822B BIT(12)
-#define BIT_FS_DDMA1_LP_INT_8822B BIT(11)
-#define BIT_FS_DDMA1_HP_INT_8822B BIT(10)
-#define BIT_FS_DDMA0_LP_INT_8822B BIT(9)
-#define BIT_FS_DDMA0_HP_INT_8822B BIT(8)
-#define BIT_FS_TRXRPT_INT_8822B BIT(7)
-#define BIT_FS_C2H_W_READY_INT_8822B BIT(6)
-#define BIT_FS_HRCV_INT_8822B BIT(5)
-#define BIT_FS_H2CCMD_INT_8822B BIT(4)
-#define BIT_FS_TXPKTIN_INT_8822B BIT(3)
-#define BIT_FS_ERRORHDL_INT_8822B BIT(2)
-#define BIT_FS_TXCCX_INT_8822B BIT(1)
-#define BIT_FS_TXCLOSE_INT_8822B BIT(0)
-
-/* 2 REG_FTIMR_8822B */
-#define BIT_PS_TIMER_C_EARLY_INT_EN_8822B BIT(23)
-#define BIT_PS_TIMER_B_EARLY_INT_EN_8822B BIT(22)
-#define BIT_PS_TIMER_A_EARLY_INT_EN_8822B BIT(21)
-#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8822B BIT(20)
-#define BIT_PS_TIMER_C_INT_EN_8822B BIT(19)
-#define BIT_PS_TIMER_B_INT_EN_8822B BIT(18)
-#define BIT_PS_TIMER_A_INT_EN_8822B BIT(17)
-#define BIT_CPUMGQ_TX_TIMER_INT_EN_8822B BIT(16)
-#define BIT_FS_PS_TIMEOUT2_EN_8822B BIT(15)
-#define BIT_FS_PS_TIMEOUT1_EN_8822B BIT(14)
-#define BIT_FS_PS_TIMEOUT0_EN_8822B BIT(13)
-#define BIT_FS_GTINT8_EN_8822B BIT(8)
-#define BIT_FS_GTINT7_EN_8822B BIT(7)
-#define BIT_FS_GTINT6_EN_8822B BIT(6)
-#define BIT_FS_GTINT5_EN_8822B BIT(5)
-#define BIT_FS_GTINT4_EN_8822B BIT(4)
-#define BIT_FS_GTINT3_EN_8822B BIT(3)
-#define BIT_FS_GTINT2_EN_8822B BIT(2)
-#define BIT_FS_GTINT1_EN_8822B BIT(1)
-#define BIT_FS_GTINT0_EN_8822B BIT(0)
-
-/* 2 REG_FTISR_8822B */
-#define BIT_PS_TIMER_C_EARLY__INT_8822B BIT(23)
-#define BIT_PS_TIMER_B_EARLY__INT_8822B BIT(22)
-#define BIT_PS_TIMER_A_EARLY__INT_8822B BIT(21)
-#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8822B BIT(20)
-#define BIT_PS_TIMER_C_INT_8822B BIT(19)
-#define BIT_PS_TIMER_B_INT_8822B BIT(18)
-#define BIT_PS_TIMER_A_INT_8822B BIT(17)
-#define BIT_CPUMGQ_TX_TIMER_INT_8822B BIT(16)
-#define BIT_FS_PS_TIMEOUT2_INT_8822B BIT(15)
-#define BIT_FS_PS_TIMEOUT1_INT_8822B BIT(14)
-#define BIT_FS_PS_TIMEOUT0_INT_8822B BIT(13)
-#define BIT_FS_GTINT8_INT_8822B BIT(8)
-#define BIT_FS_GTINT7_INT_8822B BIT(7)
-#define BIT_FS_GTINT6_INT_8822B BIT(6)
-#define BIT_FS_GTINT5_INT_8822B BIT(5)
-#define BIT_FS_GTINT4_INT_8822B BIT(4)
-#define BIT_FS_GTINT3_INT_8822B BIT(3)
-#define BIT_FS_GTINT2_INT_8822B BIT(2)
-#define BIT_FS_GTINT1_INT_8822B BIT(1)
-#define BIT_FS_GTINT0_INT_8822B BIT(0)
-
-/* 2 REG_PKTBUF_DBG_CTRL_8822B */
-
-#define BIT_SHIFT_PKTBUF_WRITE_EN_8822B 24
-#define BIT_MASK_PKTBUF_WRITE_EN_8822B 0xff
-#define BIT_PKTBUF_WRITE_EN_8822B(x) \
- (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B) \
- << BIT_SHIFT_PKTBUF_WRITE_EN_8822B)
-#define BIT_GET_PKTBUF_WRITE_EN_8822B(x) \
- (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) & \
- BIT_MASK_PKTBUF_WRITE_EN_8822B)
-
-#define BIT_TXRPTBUF_DBG_8822B BIT(23)
-
-/* 2 REG_NOT_VALID_8822B */
-#define BIT_TXPKTBUF_DBG_V2_8822B BIT(20)
-#define BIT_RXPKTBUF_DBG_8822B BIT(16)
-
-#define BIT_SHIFT_PKTBUF_DBG_ADDR_8822B 0
-#define BIT_MASK_PKTBUF_DBG_ADDR_8822B 0x1fff
-#define BIT_PKTBUF_DBG_ADDR_8822B(x) \
- (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) \
- << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B)
-#define BIT_GET_PKTBUF_DBG_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) & \
- BIT_MASK_PKTBUF_DBG_ADDR_8822B)
-
-/* 2 REG_PKTBUF_DBG_DATA_L_8822B */
-
-#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B 0
-#define BIT_MASK_PKTBUF_DBG_DATA_L_8822B 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_L_8822B(x) \
- (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) \
- << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B)
-#define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x) \
- (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) & \
- BIT_MASK_PKTBUF_DBG_DATA_L_8822B)
-
-/* 2 REG_PKTBUF_DBG_DATA_H_8822B */
-
-#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B 0
-#define BIT_MASK_PKTBUF_DBG_DATA_H_8822B 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_H_8822B(x) \
- (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) \
- << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B)
-#define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x) \
- (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) & \
- BIT_MASK_PKTBUF_DBG_DATA_H_8822B)
-
-/* 2 REG_CPWM2_8822B */
-
-#define BIT_SHIFT_L0S_TO_RCVY_NUM_8822B 16
-#define BIT_MASK_L0S_TO_RCVY_NUM_8822B 0xff
-#define BIT_L0S_TO_RCVY_NUM_8822B(x) \
- (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) \
- << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B)
-#define BIT_GET_L0S_TO_RCVY_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) & \
- BIT_MASK_L0S_TO_RCVY_NUM_8822B)
-
-#define BIT_CPWM2_TOGGLING_8822B BIT(15)
-
-#define BIT_SHIFT_CPWM2_MOD_8822B 0
-#define BIT_MASK_CPWM2_MOD_8822B 0x7fff
-#define BIT_CPWM2_MOD_8822B(x) \
- (((x) & BIT_MASK_CPWM2_MOD_8822B) << BIT_SHIFT_CPWM2_MOD_8822B)
-#define BIT_GET_CPWM2_MOD_8822B(x) \
- (((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_TC0_CTRL_8822B */
-#define BIT_TC0INT_EN_8822B BIT(26)
-#define BIT_TC0MODE_8822B BIT(25)
-#define BIT_TC0EN_8822B BIT(24)
-
-#define BIT_SHIFT_TC0DATA_8822B 0
-#define BIT_MASK_TC0DATA_8822B 0xffffff
-#define BIT_TC0DATA_8822B(x) \
- (((x) & BIT_MASK_TC0DATA_8822B) << BIT_SHIFT_TC0DATA_8822B)
-#define BIT_GET_TC0DATA_8822B(x) \
- (((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B)
-
-/* 2 REG_TC1_CTRL_8822B */
-#define BIT_TC1INT_EN_8822B BIT(26)
-#define BIT_TC1MODE_8822B BIT(25)
-#define BIT_TC1EN_8822B BIT(24)
-
-#define BIT_SHIFT_TC1DATA_8822B 0
-#define BIT_MASK_TC1DATA_8822B 0xffffff
-#define BIT_TC1DATA_8822B(x) \
- (((x) & BIT_MASK_TC1DATA_8822B) << BIT_SHIFT_TC1DATA_8822B)
-#define BIT_GET_TC1DATA_8822B(x) \
- (((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B)
-
-/* 2 REG_TC2_CTRL_8822B */
-#define BIT_TC2INT_EN_8822B BIT(26)
-#define BIT_TC2MODE_8822B BIT(25)
-#define BIT_TC2EN_8822B BIT(24)
-
-#define BIT_SHIFT_TC2DATA_8822B 0
-#define BIT_MASK_TC2DATA_8822B 0xffffff
-#define BIT_TC2DATA_8822B(x) \
- (((x) & BIT_MASK_TC2DATA_8822B) << BIT_SHIFT_TC2DATA_8822B)
-#define BIT_GET_TC2DATA_8822B(x) \
- (((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B)
-
-/* 2 REG_TC3_CTRL_8822B */
-#define BIT_TC3INT_EN_8822B BIT(26)
-#define BIT_TC3MODE_8822B BIT(25)
-#define BIT_TC3EN_8822B BIT(24)
-
-#define BIT_SHIFT_TC3DATA_8822B 0
-#define BIT_MASK_TC3DATA_8822B 0xffffff
-#define BIT_TC3DATA_8822B(x) \
- (((x) & BIT_MASK_TC3DATA_8822B) << BIT_SHIFT_TC3DATA_8822B)
-#define BIT_GET_TC3DATA_8822B(x) \
- (((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B)
-
-/* 2 REG_TC4_CTRL_8822B */
-#define BIT_TC4INT_EN_8822B BIT(26)
-#define BIT_TC4MODE_8822B BIT(25)
-#define BIT_TC4EN_8822B BIT(24)
-
-#define BIT_SHIFT_TC4DATA_8822B 0
-#define BIT_MASK_TC4DATA_8822B 0xffffff
-#define BIT_TC4DATA_8822B(x) \
- (((x) & BIT_MASK_TC4DATA_8822B) << BIT_SHIFT_TC4DATA_8822B)
-#define BIT_GET_TC4DATA_8822B(x) \
- (((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B)
-
-/* 2 REG_TCUNIT_BASE_8822B */
-
-#define BIT_SHIFT_TCUNIT_BASE_8822B 0
-#define BIT_MASK_TCUNIT_BASE_8822B 0x3fff
-#define BIT_TCUNIT_BASE_8822B(x) \
- (((x) & BIT_MASK_TCUNIT_BASE_8822B) << BIT_SHIFT_TCUNIT_BASE_8822B)
-#define BIT_GET_TCUNIT_BASE_8822B(x) \
- (((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B)
-
-/* 2 REG_TC5_CTRL_8822B */
-#define BIT_TC5INT_EN_8822B BIT(26)
-#define BIT_TC5MODE_8822B BIT(25)
-#define BIT_TC5EN_8822B BIT(24)
-
-#define BIT_SHIFT_TC5DATA_8822B 0
-#define BIT_MASK_TC5DATA_8822B 0xffffff
-#define BIT_TC5DATA_8822B(x) \
- (((x) & BIT_MASK_TC5DATA_8822B) << BIT_SHIFT_TC5DATA_8822B)
-#define BIT_GET_TC5DATA_8822B(x) \
- (((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B)
-
-/* 2 REG_TC6_CTRL_8822B */
-#define BIT_TC6INT_EN_8822B BIT(26)
-#define BIT_TC6MODE_8822B BIT(25)
-#define BIT_TC6EN_8822B BIT(24)
-
-#define BIT_SHIFT_TC6DATA_8822B 0
-#define BIT_MASK_TC6DATA_8822B 0xffffff
-#define BIT_TC6DATA_8822B(x) \
- (((x) & BIT_MASK_TC6DATA_8822B) << BIT_SHIFT_TC6DATA_8822B)
-#define BIT_GET_TC6DATA_8822B(x) \
- (((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B)
-
-/* 2 REG_MBIST_FAIL_8822B */
-
-#define BIT_SHIFT_8051_MBIST_FAIL_8822B 26
-#define BIT_MASK_8051_MBIST_FAIL_8822B 0x7
-#define BIT_8051_MBIST_FAIL_8822B(x) \
- (((x) & BIT_MASK_8051_MBIST_FAIL_8822B) \
- << BIT_SHIFT_8051_MBIST_FAIL_8822B)
-#define BIT_GET_8051_MBIST_FAIL_8822B(x) \
- (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) & \
- BIT_MASK_8051_MBIST_FAIL_8822B)
-
-#define BIT_SHIFT_USB_MBIST_FAIL_8822B 24
-#define BIT_MASK_USB_MBIST_FAIL_8822B 0x3
-#define BIT_USB_MBIST_FAIL_8822B(x) \
- (((x) & BIT_MASK_USB_MBIST_FAIL_8822B) \
- << BIT_SHIFT_USB_MBIST_FAIL_8822B)
-#define BIT_GET_USB_MBIST_FAIL_8822B(x) \
- (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) & \
- BIT_MASK_USB_MBIST_FAIL_8822B)
-
-#define BIT_SHIFT_PCIE_MBIST_FAIL_8822B 16
-#define BIT_MASK_PCIE_MBIST_FAIL_8822B 0x3f
-#define BIT_PCIE_MBIST_FAIL_8822B(x) \
- (((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B) \
- << BIT_SHIFT_PCIE_MBIST_FAIL_8822B)
-#define BIT_GET_PCIE_MBIST_FAIL_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) & \
- BIT_MASK_PCIE_MBIST_FAIL_8822B)
-
-#define BIT_SHIFT_MAC_MBIST_FAIL_8822B 0
-#define BIT_MASK_MAC_MBIST_FAIL_8822B 0xfff
-#define BIT_MAC_MBIST_FAIL_8822B(x) \
- (((x) & BIT_MASK_MAC_MBIST_FAIL_8822B) \
- << BIT_SHIFT_MAC_MBIST_FAIL_8822B)
-#define BIT_GET_MAC_MBIST_FAIL_8822B(x) \
- (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) & \
- BIT_MASK_MAC_MBIST_FAIL_8822B)
-
-/* 2 REG_MBIST_START_PAUSE_8822B */
-
-#define BIT_SHIFT_8051_MBIST_START_PAUSE_8822B 26
-#define BIT_MASK_8051_MBIST_START_PAUSE_8822B 0x7
-#define BIT_8051_MBIST_START_PAUSE_8822B(x) \
- (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) \
- << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B)
-#define BIT_GET_8051_MBIST_START_PAUSE_8822B(x) \
- (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) & \
- BIT_MASK_8051_MBIST_START_PAUSE_8822B)
-
-#define BIT_SHIFT_USB_MBIST_START_PAUSE_8822B 24
-#define BIT_MASK_USB_MBIST_START_PAUSE_8822B 0x3
-#define BIT_USB_MBIST_START_PAUSE_8822B(x) \
- (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) \
- << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B)
-#define BIT_GET_USB_MBIST_START_PAUSE_8822B(x) \
- (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) & \
- BIT_MASK_USB_MBIST_START_PAUSE_8822B)
-
-#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B 16
-#define BIT_MASK_PCIE_MBIST_START_PAUSE_8822B 0x3f
-#define BIT_PCIE_MBIST_START_PAUSE_8822B(x) \
- (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) \
- << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B)
-#define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) & \
- BIT_MASK_PCIE_MBIST_START_PAUSE_8822B)
-
-#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B 0
-#define BIT_MASK_MAC_MBIST_START_PAUSE_8822B 0xfff
-#define BIT_MAC_MBIST_START_PAUSE_8822B(x) \
- (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) \
- << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B)
-#define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x) \
- (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) & \
- BIT_MASK_MAC_MBIST_START_PAUSE_8822B)
-
-/* 2 REG_MBIST_DONE_8822B */
-
-#define BIT_SHIFT_8051_MBIST_DONE_8822B 26
-#define BIT_MASK_8051_MBIST_DONE_8822B 0x7
-#define BIT_8051_MBIST_DONE_8822B(x) \
- (((x) & BIT_MASK_8051_MBIST_DONE_8822B) \
- << BIT_SHIFT_8051_MBIST_DONE_8822B)
-#define BIT_GET_8051_MBIST_DONE_8822B(x) \
- (((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) & \
- BIT_MASK_8051_MBIST_DONE_8822B)
-
-#define BIT_SHIFT_USB_MBIST_DONE_8822B 24
-#define BIT_MASK_USB_MBIST_DONE_8822B 0x3
-#define BIT_USB_MBIST_DONE_8822B(x) \
- (((x) & BIT_MASK_USB_MBIST_DONE_8822B) \
- << BIT_SHIFT_USB_MBIST_DONE_8822B)
-#define BIT_GET_USB_MBIST_DONE_8822B(x) \
- (((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) & \
- BIT_MASK_USB_MBIST_DONE_8822B)
-
-#define BIT_SHIFT_PCIE_MBIST_DONE_8822B 16
-#define BIT_MASK_PCIE_MBIST_DONE_8822B 0x3f
-#define BIT_PCIE_MBIST_DONE_8822B(x) \
- (((x) & BIT_MASK_PCIE_MBIST_DONE_8822B) \
- << BIT_SHIFT_PCIE_MBIST_DONE_8822B)
-#define BIT_GET_PCIE_MBIST_DONE_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) & \
- BIT_MASK_PCIE_MBIST_DONE_8822B)
-
-#define BIT_SHIFT_MAC_MBIST_DONE_8822B 0
-#define BIT_MASK_MAC_MBIST_DONE_8822B 0xfff
-#define BIT_MAC_MBIST_DONE_8822B(x) \
- (((x) & BIT_MASK_MAC_MBIST_DONE_8822B) \
- << BIT_SHIFT_MAC_MBIST_DONE_8822B)
-#define BIT_GET_MAC_MBIST_DONE_8822B(x) \
- (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) & \
- BIT_MASK_MAC_MBIST_DONE_8822B)
-
-/* 2 REG_MBIST_FAIL_NRML_8822B */
-
-#define BIT_SHIFT_MBIST_FAIL_NRML_8822B 0
-#define BIT_MASK_MBIST_FAIL_NRML_8822B 0xffffffffL
-#define BIT_MBIST_FAIL_NRML_8822B(x) \
- (((x) & BIT_MASK_MBIST_FAIL_NRML_8822B) \
- << BIT_SHIFT_MBIST_FAIL_NRML_8822B)
-#define BIT_GET_MBIST_FAIL_NRML_8822B(x) \
- (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) & \
- BIT_MASK_MBIST_FAIL_NRML_8822B)
-
-/* 2 REG_AES_DECRPT_DATA_8822B */
-
-#define BIT_SHIFT_IPS_CFG_ADDR_8822B 0
-#define BIT_MASK_IPS_CFG_ADDR_8822B 0xff
-#define BIT_IPS_CFG_ADDR_8822B(x) \
- (((x) & BIT_MASK_IPS_CFG_ADDR_8822B) << BIT_SHIFT_IPS_CFG_ADDR_8822B)
-#define BIT_GET_IPS_CFG_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B)
-
-/* 2 REG_AES_DECRPT_CFG_8822B */
-
-#define BIT_SHIFT_IPS_CFG_DATA_8822B 0
-#define BIT_MASK_IPS_CFG_DATA_8822B 0xffffffffL
-#define BIT_IPS_CFG_DATA_8822B(x) \
- (((x) & BIT_MASK_IPS_CFG_DATA_8822B) << BIT_SHIFT_IPS_CFG_DATA_8822B)
-#define BIT_GET_IPS_CFG_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_TMETER_8822B */
-#define BIT_TEMP_VALID_8822B BIT(31)
-
-#define BIT_SHIFT_TEMP_VALUE_8822B 24
-#define BIT_MASK_TEMP_VALUE_8822B 0x3f
-#define BIT_TEMP_VALUE_8822B(x) \
- (((x) & BIT_MASK_TEMP_VALUE_8822B) << BIT_SHIFT_TEMP_VALUE_8822B)
-#define BIT_GET_TEMP_VALUE_8822B(x) \
- (((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B)
-
-#define BIT_SHIFT_REG_TMETER_TIMER_8822B 8
-#define BIT_MASK_REG_TMETER_TIMER_8822B 0xfff
-#define BIT_REG_TMETER_TIMER_8822B(x) \
- (((x) & BIT_MASK_REG_TMETER_TIMER_8822B) \
- << BIT_SHIFT_REG_TMETER_TIMER_8822B)
-#define BIT_GET_REG_TMETER_TIMER_8822B(x) \
- (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) & \
- BIT_MASK_REG_TMETER_TIMER_8822B)
-
-#define BIT_SHIFT_REG_TEMP_DELTA_8822B 2
-#define BIT_MASK_REG_TEMP_DELTA_8822B 0x3f
-#define BIT_REG_TEMP_DELTA_8822B(x) \
- (((x) & BIT_MASK_REG_TEMP_DELTA_8822B) \
- << BIT_SHIFT_REG_TEMP_DELTA_8822B)
-#define BIT_GET_REG_TEMP_DELTA_8822B(x) \
- (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) & \
- BIT_MASK_REG_TEMP_DELTA_8822B)
-
-#define BIT_REG_TMETER_EN_8822B BIT(0)
-
-/* 2 REG_OSC_32K_CTRL_8822B */
-
-#define BIT_SHIFT_OSC_32K_CLKGEN_0_8822B 16
-#define BIT_MASK_OSC_32K_CLKGEN_0_8822B 0xffff
-#define BIT_OSC_32K_CLKGEN_0_8822B(x) \
- (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) \
- << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B)
-#define BIT_GET_OSC_32K_CLKGEN_0_8822B(x) \
- (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) & \
- BIT_MASK_OSC_32K_CLKGEN_0_8822B)
-
-#define BIT_SHIFT_OSC_32K_RES_COMP_8822B 4
-#define BIT_MASK_OSC_32K_RES_COMP_8822B 0x3
-#define BIT_OSC_32K_RES_COMP_8822B(x) \
- (((x) & BIT_MASK_OSC_32K_RES_COMP_8822B) \
- << BIT_SHIFT_OSC_32K_RES_COMP_8822B)
-#define BIT_GET_OSC_32K_RES_COMP_8822B(x) \
- (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) & \
- BIT_MASK_OSC_32K_RES_COMP_8822B)
-
-#define BIT_OSC_32K_OUT_SEL_8822B BIT(3)
-#define BIT_ISO_WL_2_OSC_32K_8822B BIT(1)
-#define BIT_POW_CKGEN_8822B BIT(0)
-
-/* 2 REG_32K_CAL_REG1_8822B */
-#define BIT_CAL_32K_REG_WR_8822B BIT(31)
-#define BIT_CAL_32K_DBG_SEL_8822B BIT(22)
-
-#define BIT_SHIFT_CAL_32K_REG_ADDR_8822B 16
-#define BIT_MASK_CAL_32K_REG_ADDR_8822B 0x3f
-#define BIT_CAL_32K_REG_ADDR_8822B(x) \
- (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822B) \
- << BIT_SHIFT_CAL_32K_REG_ADDR_8822B)
-#define BIT_GET_CAL_32K_REG_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) & \
- BIT_MASK_CAL_32K_REG_ADDR_8822B)
-
-#define BIT_SHIFT_CAL_32K_REG_DATA_8822B 0
-#define BIT_MASK_CAL_32K_REG_DATA_8822B 0xffff
-#define BIT_CAL_32K_REG_DATA_8822B(x) \
- (((x) & BIT_MASK_CAL_32K_REG_DATA_8822B) \
- << BIT_SHIFT_CAL_32K_REG_DATA_8822B)
-#define BIT_GET_CAL_32K_REG_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) & \
- BIT_MASK_CAL_32K_REG_DATA_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_C2HEVT_8822B */
-
-#define BIT_SHIFT_C2HEVT_MSG_8822B 0
-#define BIT_MASK_C2HEVT_MSG_8822B 0xffffffffffffffffffffffffffffffffL
-#define BIT_C2HEVT_MSG_8822B(x) \
- (((x) & BIT_MASK_C2HEVT_MSG_8822B) << BIT_SHIFT_C2HEVT_MSG_8822B)
-#define BIT_GET_C2HEVT_MSG_8822B(x) \
- (((x) >> BIT_SHIFT_C2HEVT_MSG_8822B) & BIT_MASK_C2HEVT_MSG_8822B)
-
-/* 2 REG_SW_DEFINED_PAGE1_8822B */
-
-#define BIT_SHIFT_SW_DEFINED_PAGE1_8822B 0
-#define BIT_MASK_SW_DEFINED_PAGE1_8822B 0xffffffffffffffffL
-#define BIT_SW_DEFINED_PAGE1_8822B(x) \
- (((x) & BIT_MASK_SW_DEFINED_PAGE1_8822B) \
- << BIT_SHIFT_SW_DEFINED_PAGE1_8822B)
-#define BIT_GET_SW_DEFINED_PAGE1_8822B(x) \
- (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) & \
- BIT_MASK_SW_DEFINED_PAGE1_8822B)
-
-/* 2 REG_MCUTST_I_8822B */
-
-#define BIT_SHIFT_MCUDMSG_I_8822B 0
-#define BIT_MASK_MCUDMSG_I_8822B 0xffffffffL
-#define BIT_MCUDMSG_I_8822B(x) \
- (((x) & BIT_MASK_MCUDMSG_I_8822B) << BIT_SHIFT_MCUDMSG_I_8822B)
-#define BIT_GET_MCUDMSG_I_8822B(x) \
- (((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B)
-
-/* 2 REG_MCUTST_II_8822B */
-
-#define BIT_SHIFT_MCUDMSG_II_8822B 0
-#define BIT_MASK_MCUDMSG_II_8822B 0xffffffffL
-#define BIT_MCUDMSG_II_8822B(x) \
- (((x) & BIT_MASK_MCUDMSG_II_8822B) << BIT_SHIFT_MCUDMSG_II_8822B)
-#define BIT_GET_MCUDMSG_II_8822B(x) \
- (((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B)
-
-/* 2 REG_FMETHR_8822B */
-#define BIT_FMSG_INT_8822B BIT(31)
-
-#define BIT_SHIFT_FW_MSG_8822B 0
-#define BIT_MASK_FW_MSG_8822B 0xffffffffL
-#define BIT_FW_MSG_8822B(x) \
- (((x) & BIT_MASK_FW_MSG_8822B) << BIT_SHIFT_FW_MSG_8822B)
-#define BIT_GET_FW_MSG_8822B(x) \
- (((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B)
-
-/* 2 REG_HMETFR_8822B */
-
-#define BIT_SHIFT_HRCV_MSG_8822B 24
-#define BIT_MASK_HRCV_MSG_8822B 0xff
-#define BIT_HRCV_MSG_8822B(x) \
- (((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B)
-#define BIT_GET_HRCV_MSG_8822B(x) \
- (((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B)
-
-#define BIT_INT_BOX3_8822B BIT(3)
-#define BIT_INT_BOX2_8822B BIT(2)
-#define BIT_INT_BOX1_8822B BIT(1)
-#define BIT_INT_BOX0_8822B BIT(0)
-
-/* 2 REG_HMEBOX0_8822B */
-
-#define BIT_SHIFT_HOST_MSG_0_8822B 0
-#define BIT_MASK_HOST_MSG_0_8822B 0xffffffffL
-#define BIT_HOST_MSG_0_8822B(x) \
- (((x) & BIT_MASK_HOST_MSG_0_8822B) << BIT_SHIFT_HOST_MSG_0_8822B)
-#define BIT_GET_HOST_MSG_0_8822B(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B)
-
-/* 2 REG_HMEBOX1_8822B */
-
-#define BIT_SHIFT_HOST_MSG_1_8822B 0
-#define BIT_MASK_HOST_MSG_1_8822B 0xffffffffL
-#define BIT_HOST_MSG_1_8822B(x) \
- (((x) & BIT_MASK_HOST_MSG_1_8822B) << BIT_SHIFT_HOST_MSG_1_8822B)
-#define BIT_GET_HOST_MSG_1_8822B(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B)
-
-/* 2 REG_HMEBOX2_8822B */
-
-#define BIT_SHIFT_HOST_MSG_2_8822B 0
-#define BIT_MASK_HOST_MSG_2_8822B 0xffffffffL
-#define BIT_HOST_MSG_2_8822B(x) \
- (((x) & BIT_MASK_HOST_MSG_2_8822B) << BIT_SHIFT_HOST_MSG_2_8822B)
-#define BIT_GET_HOST_MSG_2_8822B(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B)
-
-/* 2 REG_HMEBOX3_8822B */
-
-#define BIT_SHIFT_HOST_MSG_3_8822B 0
-#define BIT_MASK_HOST_MSG_3_8822B 0xffffffffL
-#define BIT_HOST_MSG_3_8822B(x) \
- (((x) & BIT_MASK_HOST_MSG_3_8822B) << BIT_SHIFT_HOST_MSG_3_8822B)
-#define BIT_GET_HOST_MSG_3_8822B(x) \
- (((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B)
-
-/* 2 REG_LLT_INIT_8822B */
-
-#define BIT_SHIFT_LLTE_RWM_8822B 30
-#define BIT_MASK_LLTE_RWM_8822B 0x3
-#define BIT_LLTE_RWM_8822B(x) \
- (((x) & BIT_MASK_LLTE_RWM_8822B) << BIT_SHIFT_LLTE_RWM_8822B)
-#define BIT_GET_LLTE_RWM_8822B(x) \
- (((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B)
-
-#define BIT_SHIFT_LLTINI_PDATA_V1_8822B 16
-#define BIT_MASK_LLTINI_PDATA_V1_8822B 0xfff
-#define BIT_LLTINI_PDATA_V1_8822B(x) \
- (((x) & BIT_MASK_LLTINI_PDATA_V1_8822B) \
- << BIT_SHIFT_LLTINI_PDATA_V1_8822B)
-#define BIT_GET_LLTINI_PDATA_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) & \
- BIT_MASK_LLTINI_PDATA_V1_8822B)
-
-#define BIT_SHIFT_LLTINI_HDATA_V1_8822B 0
-#define BIT_MASK_LLTINI_HDATA_V1_8822B 0xfff
-#define BIT_LLTINI_HDATA_V1_8822B(x) \
- (((x) & BIT_MASK_LLTINI_HDATA_V1_8822B) \
- << BIT_SHIFT_LLTINI_HDATA_V1_8822B)
-#define BIT_GET_LLTINI_HDATA_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) & \
- BIT_MASK_LLTINI_HDATA_V1_8822B)
-
-/* 2 REG_LLT_INIT_ADDR_8822B */
-
-#define BIT_SHIFT_LLTINI_ADDR_V1_8822B 0
-#define BIT_MASK_LLTINI_ADDR_V1_8822B 0xfff
-#define BIT_LLTINI_ADDR_V1_8822B(x) \
- (((x) & BIT_MASK_LLTINI_ADDR_V1_8822B) \
- << BIT_SHIFT_LLTINI_ADDR_V1_8822B)
-#define BIT_GET_LLTINI_ADDR_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) & \
- BIT_MASK_LLTINI_ADDR_V1_8822B)
-
-/* 2 REG_BB_ACCESS_CTRL_8822B */
-
-#define BIT_SHIFT_BB_WRITE_READ_8822B 30
-#define BIT_MASK_BB_WRITE_READ_8822B 0x3
-#define BIT_BB_WRITE_READ_8822B(x) \
- (((x) & BIT_MASK_BB_WRITE_READ_8822B) << BIT_SHIFT_BB_WRITE_READ_8822B)
-#define BIT_GET_BB_WRITE_READ_8822B(x) \
- (((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B)
-
-#define BIT_SHIFT_BB_WRITE_EN_8822B 12
-#define BIT_MASK_BB_WRITE_EN_8822B 0xf
-#define BIT_BB_WRITE_EN_8822B(x) \
- (((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B)
-#define BIT_GET_BB_WRITE_EN_8822B(x) \
- (((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B)
-
-#define BIT_SHIFT_BB_ADDR_8822B 2
-#define BIT_MASK_BB_ADDR_8822B 0x1ff
-#define BIT_BB_ADDR_8822B(x) \
- (((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B)
-#define BIT_GET_BB_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B)
-
-#define BIT_BB_ERRACC_8822B BIT(0)
-
-/* 2 REG_BB_ACCESS_DATA_8822B */
-
-#define BIT_SHIFT_BB_DATA_8822B 0
-#define BIT_MASK_BB_DATA_8822B 0xffffffffL
-#define BIT_BB_DATA_8822B(x) \
- (((x) & BIT_MASK_BB_DATA_8822B) << BIT_SHIFT_BB_DATA_8822B)
-#define BIT_GET_BB_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B)
-
-/* 2 REG_HMEBOX_E0_8822B */
-
-#define BIT_SHIFT_HMEBOX_E0_8822B 0
-#define BIT_MASK_HMEBOX_E0_8822B 0xffffffffL
-#define BIT_HMEBOX_E0_8822B(x) \
- (((x) & BIT_MASK_HMEBOX_E0_8822B) << BIT_SHIFT_HMEBOX_E0_8822B)
-#define BIT_GET_HMEBOX_E0_8822B(x) \
- (((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B)
-
-/* 2 REG_HMEBOX_E1_8822B */
-
-#define BIT_SHIFT_HMEBOX_E1_8822B 0
-#define BIT_MASK_HMEBOX_E1_8822B 0xffffffffL
-#define BIT_HMEBOX_E1_8822B(x) \
- (((x) & BIT_MASK_HMEBOX_E1_8822B) << BIT_SHIFT_HMEBOX_E1_8822B)
-#define BIT_GET_HMEBOX_E1_8822B(x) \
- (((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B)
-
-/* 2 REG_HMEBOX_E2_8822B */
-
-#define BIT_SHIFT_HMEBOX_E2_8822B 0
-#define BIT_MASK_HMEBOX_E2_8822B 0xffffffffL
-#define BIT_HMEBOX_E2_8822B(x) \
- (((x) & BIT_MASK_HMEBOX_E2_8822B) << BIT_SHIFT_HMEBOX_E2_8822B)
-#define BIT_GET_HMEBOX_E2_8822B(x) \
- (((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B)
-
-/* 2 REG_HMEBOX_E3_8822B */
-
-#define BIT_SHIFT_HMEBOX_E3_8822B 0
-#define BIT_MASK_HMEBOX_E3_8822B 0xffffffffL
-#define BIT_HMEBOX_E3_8822B(x) \
- (((x) & BIT_MASK_HMEBOX_E3_8822B) << BIT_SHIFT_HMEBOX_E3_8822B)
-#define BIT_GET_HMEBOX_E3_8822B(x) \
- (((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_CR_EXT_8822B */
-
-#define BIT_SHIFT_PHY_REQ_DELAY_8822B 24
-#define BIT_MASK_PHY_REQ_DELAY_8822B 0xf
-#define BIT_PHY_REQ_DELAY_8822B(x) \
- (((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B)
-#define BIT_GET_PHY_REQ_DELAY_8822B(x) \
- (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B)
-
-#define BIT_SPD_DOWN_8822B BIT(16)
-
-#define BIT_SHIFT_NETYPE4_8822B 4
-#define BIT_MASK_NETYPE4_8822B 0x3
-#define BIT_NETYPE4_8822B(x) \
- (((x) & BIT_MASK_NETYPE4_8822B) << BIT_SHIFT_NETYPE4_8822B)
-#define BIT_GET_NETYPE4_8822B(x) \
- (((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B)
-
-#define BIT_SHIFT_NETYPE3_8822B 2
-#define BIT_MASK_NETYPE3_8822B 0x3
-#define BIT_NETYPE3_8822B(x) \
- (((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B)
-#define BIT_GET_NETYPE3_8822B(x) \
- (((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B)
-
-#define BIT_SHIFT_NETYPE2_8822B 0
-#define BIT_MASK_NETYPE2_8822B 0x3
-#define BIT_NETYPE2_8822B(x) \
- (((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B)
-#define BIT_GET_NETYPE2_8822B(x) \
- (((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B)
-
-/* 2 REG_FWFF_8822B */
-
-#define BIT_SHIFT_PKTNUM_TH_V1_8822B 24
-#define BIT_MASK_PKTNUM_TH_V1_8822B 0xff
-#define BIT_PKTNUM_TH_V1_8822B(x) \
- (((x) & BIT_MASK_PKTNUM_TH_V1_8822B) << BIT_SHIFT_PKTNUM_TH_V1_8822B)
-#define BIT_GET_PKTNUM_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B)
-
-#define BIT_SHIFT_TIMER_TH_8822B 16
-#define BIT_MASK_TIMER_TH_8822B 0xff
-#define BIT_TIMER_TH_8822B(x) \
- (((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B)
-#define BIT_GET_TIMER_TH_8822B(x) \
- (((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B)
-
-#define BIT_SHIFT_RXPKT1ENADDR_8822B 0
-#define BIT_MASK_RXPKT1ENADDR_8822B 0xffff
-#define BIT_RXPKT1ENADDR_8822B(x) \
- (((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B)
-#define BIT_GET_RXPKT1ENADDR_8822B(x) \
- (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B)
-
-/* 2 REG_RXFF_PTR_V1_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_RXFF0_RDPTR_V2_8822B 0
-#define BIT_MASK_RXFF0_RDPTR_V2_8822B 0x3ffff
-#define BIT_RXFF0_RDPTR_V2_8822B(x) \
- (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822B) \
- << BIT_SHIFT_RXFF0_RDPTR_V2_8822B)
-#define BIT_GET_RXFF0_RDPTR_V2_8822B(x) \
- (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) & \
- BIT_MASK_RXFF0_RDPTR_V2_8822B)
-
-/* 2 REG_RXFF_WTR_V1_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_RXFF0_WTPTR_V2_8822B 0
-#define BIT_MASK_RXFF0_WTPTR_V2_8822B 0x3ffff
-#define BIT_RXFF0_WTPTR_V2_8822B(x) \
- (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822B) \
- << BIT_SHIFT_RXFF0_WTPTR_V2_8822B)
-#define BIT_GET_RXFF0_WTPTR_V2_8822B(x) \
- (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) & \
- BIT_MASK_RXFF0_WTPTR_V2_8822B)
-
-/* 2 REG_FE2IMR_8822B */
-#define BIT__FE4ISR__IND_MSK_8822B BIT(29)
-#define BIT_FS_TXSC_DESC_DONE_INT_EN_8822B BIT(28)
-#define BIT_FS_TXSC_BKDONE_INT_EN_8822B BIT(27)
-#define BIT_FS_TXSC_BEDONE_INT_EN_8822B BIT(26)
-#define BIT_FS_TXSC_VIDONE_INT_EN_8822B BIT(25)
-#define BIT_FS_TXSC_VODONE_INT_EN_8822B BIT(24)
-#define BIT_FS_ATIM_MB7_INT_EN_8822B BIT(23)
-#define BIT_FS_ATIM_MB6_INT_EN_8822B BIT(22)
-#define BIT_FS_ATIM_MB5_INT_EN_8822B BIT(21)
-#define BIT_FS_ATIM_MB4_INT_EN_8822B BIT(20)
-#define BIT_FS_ATIM_MB3_INT_EN_8822B BIT(19)
-#define BIT_FS_ATIM_MB2_INT_EN_8822B BIT(18)
-#define BIT_FS_ATIM_MB1_INT_EN_8822B BIT(17)
-#define BIT_FS_ATIM_MB0_INT_EN_8822B BIT(16)
-#define BIT_FS_TBTT4INT_EN_8822B BIT(11)
-#define BIT_FS_TBTT3INT_EN_8822B BIT(10)
-#define BIT_FS_TBTT2INT_EN_8822B BIT(9)
-#define BIT_FS_TBTT1INT_EN_8822B BIT(8)
-#define BIT_FS_TBTT0_MB7INT_EN_8822B BIT(7)
-#define BIT_FS_TBTT0_MB6INT_EN_8822B BIT(6)
-#define BIT_FS_TBTT0_MB5INT_EN_8822B BIT(5)
-#define BIT_FS_TBTT0_MB4INT_EN_8822B BIT(4)
-#define BIT_FS_TBTT0_MB3INT_EN_8822B BIT(3)
-#define BIT_FS_TBTT0_MB2INT_EN_8822B BIT(2)
-#define BIT_FS_TBTT0_MB1INT_EN_8822B BIT(1)
-#define BIT_FS_TBTT0_INT_EN_8822B BIT(0)
-
-/* 2 REG_FE2ISR_8822B */
-#define BIT__FE4ISR__IND_INT_8822B BIT(29)
-#define BIT_FS_TXSC_DESC_DONE_INT_8822B BIT(28)
-#define BIT_FS_TXSC_BKDONE_INT_8822B BIT(27)
-#define BIT_FS_TXSC_BEDONE_INT_8822B BIT(26)
-#define BIT_FS_TXSC_VIDONE_INT_8822B BIT(25)
-#define BIT_FS_TXSC_VODONE_INT_8822B BIT(24)
-#define BIT_FS_ATIM_MB7_INT_8822B BIT(23)
-#define BIT_FS_ATIM_MB6_INT_8822B BIT(22)
-#define BIT_FS_ATIM_MB5_INT_8822B BIT(21)
-#define BIT_FS_ATIM_MB4_INT_8822B BIT(20)
-#define BIT_FS_ATIM_MB3_INT_8822B BIT(19)
-#define BIT_FS_ATIM_MB2_INT_8822B BIT(18)
-#define BIT_FS_ATIM_MB1_INT_8822B BIT(17)
-#define BIT_FS_ATIM_MB0_INT_8822B BIT(16)
-#define BIT_FS_TBTT4INT_8822B BIT(11)
-#define BIT_FS_TBTT3INT_8822B BIT(10)
-#define BIT_FS_TBTT2INT_8822B BIT(9)
-#define BIT_FS_TBTT1INT_8822B BIT(8)
-#define BIT_FS_TBTT0_MB7INT_8822B BIT(7)
-#define BIT_FS_TBTT0_MB6INT_8822B BIT(6)
-#define BIT_FS_TBTT0_MB5INT_8822B BIT(5)
-#define BIT_FS_TBTT0_MB4INT_8822B BIT(4)
-#define BIT_FS_TBTT0_MB3INT_8822B BIT(3)
-#define BIT_FS_TBTT0_MB2INT_8822B BIT(2)
-#define BIT_FS_TBTT0_MB1INT_8822B BIT(1)
-#define BIT_FS_TBTT0_INT_8822B BIT(0)
-
-/* 2 REG_FE3IMR_8822B */
-#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8822B BIT(31)
-#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8822B BIT(30)
-#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8822B BIT(29)
-#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8822B BIT(28)
-#define BIT_FS_BCNDMA4_INT_EN_8822B BIT(27)
-#define BIT_FS_BCNDMA3_INT_EN_8822B BIT(26)
-#define BIT_FS_BCNDMA2_INT_EN_8822B BIT(25)
-#define BIT_FS_BCNDMA1_INT_EN_8822B BIT(24)
-#define BIT_FS_BCNDMA0_MB7_INT_EN_8822B BIT(23)
-#define BIT_FS_BCNDMA0_MB6_INT_EN_8822B BIT(22)
-#define BIT_FS_BCNDMA0_MB5_INT_EN_8822B BIT(21)
-#define BIT_FS_BCNDMA0_MB4_INT_EN_8822B BIT(20)
-#define BIT_FS_BCNDMA0_MB3_INT_EN_8822B BIT(19)
-#define BIT_FS_BCNDMA0_MB2_INT_EN_8822B BIT(18)
-#define BIT_FS_BCNDMA0_MB1_INT_EN_8822B BIT(17)
-#define BIT_FS_BCNDMA0_INT_EN_8822B BIT(16)
-#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8822B BIT(15)
-#define BIT_FS_BCNERLY4_INT_EN_8822B BIT(11)
-#define BIT_FS_BCNERLY3_INT_EN_8822B BIT(10)
-#define BIT_FS_BCNERLY2_INT_EN_8822B BIT(9)
-#define BIT_FS_BCNERLY1_INT_EN_8822B BIT(8)
-#define BIT_FS_BCNERLY0_MB7INT_EN_8822B BIT(7)
-#define BIT_FS_BCNERLY0_MB6INT_EN_8822B BIT(6)
-#define BIT_FS_BCNERLY0_MB5INT_EN_8822B BIT(5)
-#define BIT_FS_BCNERLY0_MB4INT_EN_8822B BIT(4)
-#define BIT_FS_BCNERLY0_MB3INT_EN_8822B BIT(3)
-#define BIT_FS_BCNERLY0_MB2INT_EN_8822B BIT(2)
-#define BIT_FS_BCNERLY0_MB1INT_EN_8822B BIT(1)
-#define BIT_FS_BCNERLY0_INT_EN_8822B BIT(0)
-
-/* 2 REG_FE3ISR_8822B */
-#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8822B BIT(31)
-#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8822B BIT(30)
-#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8822B BIT(29)
-#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8822B BIT(28)
-#define BIT_FS_BCNDMA4_INT_8822B BIT(27)
-#define BIT_FS_BCNDMA3_INT_8822B BIT(26)
-#define BIT_FS_BCNDMA2_INT_8822B BIT(25)
-#define BIT_FS_BCNDMA1_INT_8822B BIT(24)
-#define BIT_FS_BCNDMA0_MB7_INT_8822B BIT(23)
-#define BIT_FS_BCNDMA0_MB6_INT_8822B BIT(22)
-#define BIT_FS_BCNDMA0_MB5_INT_8822B BIT(21)
-#define BIT_FS_BCNDMA0_MB4_INT_8822B BIT(20)
-#define BIT_FS_BCNDMA0_MB3_INT_8822B BIT(19)
-#define BIT_FS_BCNDMA0_MB2_INT_8822B BIT(18)
-#define BIT_FS_BCNDMA0_MB1_INT_8822B BIT(17)
-#define BIT_FS_BCNDMA0_INT_8822B BIT(16)
-#define BIT_FS_MTI_BCNIVLEAR_INT_8822B BIT(15)
-#define BIT_FS_BCNERLY4_INT_8822B BIT(11)
-#define BIT_FS_BCNERLY3_INT_8822B BIT(10)
-#define BIT_FS_BCNERLY2_INT_8822B BIT(9)
-#define BIT_FS_BCNERLY1_INT_8822B BIT(8)
-#define BIT_FS_BCNERLY0_MB7INT_8822B BIT(7)
-#define BIT_FS_BCNERLY0_MB6INT_8822B BIT(6)
-#define BIT_FS_BCNERLY0_MB5INT_8822B BIT(5)
-#define BIT_FS_BCNERLY0_MB4INT_8822B BIT(4)
-#define BIT_FS_BCNERLY0_MB3INT_8822B BIT(3)
-#define BIT_FS_BCNERLY0_MB2INT_8822B BIT(2)
-#define BIT_FS_BCNERLY0_MB1INT_8822B BIT(1)
-#define BIT_FS_BCNERLY0_INT_8822B BIT(0)
-
-/* 2 REG_FE4IMR_8822B */
-#define BIT_FS_CLI3_TXPKTIN_INT_EN_8822B BIT(19)
-#define BIT_FS_CLI2_TXPKTIN_INT_EN_8822B BIT(18)
-#define BIT_FS_CLI1_TXPKTIN_INT_EN_8822B BIT(17)
-#define BIT_FS_CLI0_TXPKTIN_INT_EN_8822B BIT(16)
-#define BIT_FS_CLI3_RX_UMD0_INT_EN_8822B BIT(15)
-#define BIT_FS_CLI3_RX_UMD1_INT_EN_8822B BIT(14)
-#define BIT_FS_CLI3_RX_BMD0_INT_EN_8822B BIT(13)
-#define BIT_FS_CLI3_RX_BMD1_INT_EN_8822B BIT(12)
-#define BIT_FS_CLI2_RX_UMD0_INT_EN_8822B BIT(11)
-#define BIT_FS_CLI2_RX_UMD1_INT_EN_8822B BIT(10)
-#define BIT_FS_CLI2_RX_BMD0_INT_EN_8822B BIT(9)
-#define BIT_FS_CLI2_RX_BMD1_INT_EN_8822B BIT(8)
-#define BIT_FS_CLI1_RX_UMD0_INT_EN_8822B BIT(7)
-#define BIT_FS_CLI1_RX_UMD1_INT_EN_8822B BIT(6)
-#define BIT_FS_CLI1_RX_BMD0_INT_EN_8822B BIT(5)
-#define BIT_FS_CLI1_RX_BMD1_INT_EN_8822B BIT(4)
-#define BIT_FS_CLI0_RX_UMD0_INT_EN_8822B BIT(3)
-#define BIT_FS_CLI0_RX_UMD1_INT_EN_8822B BIT(2)
-#define BIT_FS_CLI0_RX_BMD0_INT_EN_8822B BIT(1)
-#define BIT_FS_CLI0_RX_BMD1_INT_EN_8822B BIT(0)
-
-/* 2 REG_FE4ISR_8822B */
-#define BIT_FS_CLI3_TXPKTIN_INT_8822B BIT(19)
-#define BIT_FS_CLI2_TXPKTIN_INT_8822B BIT(18)
-#define BIT_FS_CLI1_TXPKTIN_INT_8822B BIT(17)
-#define BIT_FS_CLI0_TXPKTIN_INT_8822B BIT(16)
-#define BIT_FS_CLI3_RX_UMD0_INT_8822B BIT(15)
-#define BIT_FS_CLI3_RX_UMD1_INT_8822B BIT(14)
-#define BIT_FS_CLI3_RX_BMD0_INT_8822B BIT(13)
-#define BIT_FS_CLI3_RX_BMD1_INT_8822B BIT(12)
-#define BIT_FS_CLI2_RX_UMD0_INT_8822B BIT(11)
-#define BIT_FS_CLI2_RX_UMD1_INT_8822B BIT(10)
-#define BIT_FS_CLI2_RX_BMD0_INT_8822B BIT(9)
-#define BIT_FS_CLI2_RX_BMD1_INT_8822B BIT(8)
-#define BIT_FS_CLI1_RX_UMD0_INT_8822B BIT(7)
-#define BIT_FS_CLI1_RX_UMD1_INT_8822B BIT(6)
-#define BIT_FS_CLI1_RX_BMD0_INT_8822B BIT(5)
-#define BIT_FS_CLI1_RX_BMD1_INT_8822B BIT(4)
-#define BIT_FS_CLI0_RX_UMD0_INT_8822B BIT(3)
-#define BIT_FS_CLI0_RX_UMD1_INT_8822B BIT(2)
-#define BIT_FS_CLI0_RX_BMD0_INT_8822B BIT(1)
-#define BIT_FS_CLI0_RX_BMD1_INT_8822B BIT(0)
-
-/* 2 REG_FT1IMR_8822B */
-#define BIT__FT2ISR__IND_MSK_8822B BIT(30)
-#define BIT_FTM_PTT_INT_EN_8822B BIT(29)
-#define BIT_RXFTMREQ_INT_EN_8822B BIT(28)
-#define BIT_RXFTM_INT_EN_8822B BIT(27)
-#define BIT_TXFTM_INT_EN_8822B BIT(26)
-#define BIT_FS_H2C_CMD_OK_INT_EN_8822B BIT(25)
-#define BIT_FS_H2C_CMD_FULL_INT_EN_8822B BIT(24)
-#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8822B BIT(23)
-#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8822B BIT(22)
-#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8822B BIT(21)
-#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8822B BIT(20)
-#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8822B BIT(19)
-#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8822B BIT(18)
-#define BIT_FS_CTWEND2_INT_EN_8822B BIT(17)
-#define BIT_FS_CTWEND1_INT_EN_8822B BIT(16)
-#define BIT_FS_CTWEND0_INT_EN_8822B BIT(15)
-#define BIT_FS_TX_NULL1_INT_EN_8822B BIT(14)
-#define BIT_FS_TX_NULL0_INT_EN_8822B BIT(13)
-#define BIT_FS_TSF_BIT32_TOGGLE_EN_8822B BIT(12)
-#define BIT_FS_P2P_RFON2_INT_EN_8822B BIT(11)
-#define BIT_FS_P2P_RFOFF2_INT_EN_8822B BIT(10)
-#define BIT_FS_P2P_RFON1_INT_EN_8822B BIT(9)
-#define BIT_FS_P2P_RFOFF1_INT_EN_8822B BIT(8)
-#define BIT_FS_P2P_RFON0_INT_EN_8822B BIT(7)
-#define BIT_FS_P2P_RFOFF0_INT_EN_8822B BIT(6)
-#define BIT_FS_RX_UAPSDMD1_EN_8822B BIT(5)
-#define BIT_FS_RX_UAPSDMD0_EN_8822B BIT(4)
-#define BIT_FS_TRIGGER_PKT_EN_8822B BIT(3)
-#define BIT_FS_EOSP_INT_EN_8822B BIT(2)
-#define BIT_FS_RPWM2_INT_EN_8822B BIT(1)
-#define BIT_FS_RPWM_INT_EN_8822B BIT(0)
-
-/* 2 REG_FT1ISR_8822B */
-#define BIT__FT2ISR__IND_INT_8822B BIT(30)
-#define BIT_FTM_PTT_INT_8822B BIT(29)
-#define BIT_RXFTMREQ_INT_8822B BIT(28)
-#define BIT_RXFTM_INT_8822B BIT(27)
-#define BIT_TXFTM_INT_8822B BIT(26)
-#define BIT_FS_H2C_CMD_OK_INT_8822B BIT(25)
-#define BIT_FS_H2C_CMD_FULL_INT_8822B BIT(24)
-#define BIT_FS_MACID_PWRCHANGE5_INT_8822B BIT(23)
-#define BIT_FS_MACID_PWRCHANGE4_INT_8822B BIT(22)
-#define BIT_FS_MACID_PWRCHANGE3_INT_8822B BIT(21)
-#define BIT_FS_MACID_PWRCHANGE2_INT_8822B BIT(20)
-#define BIT_FS_MACID_PWRCHANGE1_INT_8822B BIT(19)
-#define BIT_FS_MACID_PWRCHANGE0_INT_8822B BIT(18)
-#define BIT_FS_CTWEND2_INT_8822B BIT(17)
-#define BIT_FS_CTWEND1_INT_8822B BIT(16)
-#define BIT_FS_CTWEND0_INT_8822B BIT(15)
-#define BIT_FS_TX_NULL1_INT_8822B BIT(14)
-#define BIT_FS_TX_NULL0_INT_8822B BIT(13)
-#define BIT_FS_TSF_BIT32_TOGGLE_INT_8822B BIT(12)
-#define BIT_FS_P2P_RFON2_INT_8822B BIT(11)
-#define BIT_FS_P2P_RFOFF2_INT_8822B BIT(10)
-#define BIT_FS_P2P_RFON1_INT_8822B BIT(9)
-#define BIT_FS_P2P_RFOFF1_INT_8822B BIT(8)
-#define BIT_FS_P2P_RFON0_INT_8822B BIT(7)
-#define BIT_FS_P2P_RFOFF0_INT_8822B BIT(6)
-#define BIT_FS_RX_UAPSDMD1_INT_8822B BIT(5)
-#define BIT_FS_RX_UAPSDMD0_INT_8822B BIT(4)
-#define BIT_FS_TRIGGER_PKT_INT_8822B BIT(3)
-#define BIT_FS_EOSP_INT_8822B BIT(2)
-#define BIT_FS_RPWM2_INT_8822B BIT(1)
-#define BIT_FS_RPWM_INT_8822B BIT(0)
-
-/* 2 REG_SPWR0_8822B */
-
-#define BIT_SHIFT_MID_31TO0_8822B 0
-#define BIT_MASK_MID_31TO0_8822B 0xffffffffL
-#define BIT_MID_31TO0_8822B(x) \
- (((x) & BIT_MASK_MID_31TO0_8822B) << BIT_SHIFT_MID_31TO0_8822B)
-#define BIT_GET_MID_31TO0_8822B(x) \
- (((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B)
-
-/* 2 REG_SPWR1_8822B */
-
-#define BIT_SHIFT_MID_63TO32_8822B 0
-#define BIT_MASK_MID_63TO32_8822B 0xffffffffL
-#define BIT_MID_63TO32_8822B(x) \
- (((x) & BIT_MASK_MID_63TO32_8822B) << BIT_SHIFT_MID_63TO32_8822B)
-#define BIT_GET_MID_63TO32_8822B(x) \
- (((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B)
-
-/* 2 REG_SPWR2_8822B */
-
-#define BIT_SHIFT_MID_95O64_8822B 0
-#define BIT_MASK_MID_95O64_8822B 0xffffffffL
-#define BIT_MID_95O64_8822B(x) \
- (((x) & BIT_MASK_MID_95O64_8822B) << BIT_SHIFT_MID_95O64_8822B)
-#define BIT_GET_MID_95O64_8822B(x) \
- (((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B)
-
-/* 2 REG_SPWR3_8822B */
-
-#define BIT_SHIFT_MID_127TO96_8822B 0
-#define BIT_MASK_MID_127TO96_8822B 0xffffffffL
-#define BIT_MID_127TO96_8822B(x) \
- (((x) & BIT_MASK_MID_127TO96_8822B) << BIT_SHIFT_MID_127TO96_8822B)
-#define BIT_GET_MID_127TO96_8822B(x) \
- (((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B)
-
-/* 2 REG_POWSEQ_8822B */
-
-#define BIT_SHIFT_SEQNUM_MID_8822B 16
-#define BIT_MASK_SEQNUM_MID_8822B 0xffff
-#define BIT_SEQNUM_MID_8822B(x) \
- (((x) & BIT_MASK_SEQNUM_MID_8822B) << BIT_SHIFT_SEQNUM_MID_8822B)
-#define BIT_GET_SEQNUM_MID_8822B(x) \
- (((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B)
-
-#define BIT_SHIFT_REF_MID_8822B 0
-#define BIT_MASK_REF_MID_8822B 0x7f
-#define BIT_REF_MID_8822B(x) \
- (((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B)
-#define BIT_GET_REF_MID_8822B(x) \
- (((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B)
-
-/* 2 REG_TC7_CTRL_V1_8822B */
-#define BIT_TC7INT_EN_8822B BIT(26)
-#define BIT_TC7MODE_8822B BIT(25)
-#define BIT_TC7EN_8822B BIT(24)
-
-#define BIT_SHIFT_TC7DATA_8822B 0
-#define BIT_MASK_TC7DATA_8822B 0xffffff
-#define BIT_TC7DATA_8822B(x) \
- (((x) & BIT_MASK_TC7DATA_8822B) << BIT_SHIFT_TC7DATA_8822B)
-#define BIT_GET_TC7DATA_8822B(x) \
- (((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B)
-
-/* 2 REG_TC8_CTRL_V1_8822B */
-#define BIT_TC8INT_EN_8822B BIT(26)
-#define BIT_TC8MODE_8822B BIT(25)
-#define BIT_TC8EN_8822B BIT(24)
-
-#define BIT_SHIFT_TC8DATA_8822B 0
-#define BIT_MASK_TC8DATA_8822B 0xffffff
-#define BIT_TC8DATA_8822B(x) \
- (((x) & BIT_MASK_TC8DATA_8822B) << BIT_SHIFT_TC8DATA_8822B)
-#define BIT_GET_TC8DATA_8822B(x) \
- (((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B)
-
-/* 2 REG_FT2IMR_8822B */
-#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822B BIT(31)
-#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8822B BIT(30)
-#define BIT_FS_CLI3_TRIGGER_PKT_EN_8822B BIT(29)
-#define BIT_FS_CLI3_EOSP_INT_EN_8822B BIT(28)
-#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8822B BIT(27)
-#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8822B BIT(26)
-#define BIT_FS_CLI2_TRIGGER_PKT_EN_8822B BIT(25)
-#define BIT_FS_CLI2_EOSP_INT_EN_8822B BIT(24)
-#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8822B BIT(23)
-#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8822B BIT(22)
-#define BIT_FS_CLI1_TRIGGER_PKT_EN_8822B BIT(21)
-#define BIT_FS_CLI1_EOSP_INT_EN_8822B BIT(20)
-#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8822B BIT(19)
-#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8822B BIT(18)
-#define BIT_FS_CLI0_TRIGGER_PKT_EN_8822B BIT(17)
-#define BIT_FS_CLI0_EOSP_INT_EN_8822B BIT(16)
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8822B BIT(9)
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8822B BIT(8)
-#define BIT_FS_CLI3_TX_NULL1_INT_EN_8822B BIT(7)
-#define BIT_FS_CLI3_TX_NULL0_INT_EN_8822B BIT(6)
-#define BIT_FS_CLI2_TX_NULL1_INT_EN_8822B BIT(5)
-#define BIT_FS_CLI2_TX_NULL0_INT_EN_8822B BIT(4)
-#define BIT_FS_CLI1_TX_NULL1_INT_EN_8822B BIT(3)
-#define BIT_FS_CLI1_TX_NULL0_INT_EN_8822B BIT(2)
-#define BIT_FS_CLI0_TX_NULL1_INT_EN_8822B BIT(1)
-#define BIT_FS_CLI0_TX_NULL0_INT_EN_8822B BIT(0)
-
-/* 2 REG_FT2ISR_8822B */
-#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8822B BIT(31)
-#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8822B BIT(30)
-#define BIT_FS_CLI3_TRIGGER_PKT_INT_8822B BIT(29)
-#define BIT_FS_CLI3_EOSP_INT_8822B BIT(28)
-#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8822B BIT(27)
-#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8822B BIT(26)
-#define BIT_FS_CLI2_TRIGGER_PKT_INT_8822B BIT(25)
-#define BIT_FS_CLI2_EOSP_INT_8822B BIT(24)
-#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8822B BIT(23)
-#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8822B BIT(22)
-#define BIT_FS_CLI1_TRIGGER_PKT_INT_8822B BIT(21)
-#define BIT_FS_CLI1_EOSP_INT_8822B BIT(20)
-#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8822B BIT(19)
-#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8822B BIT(18)
-#define BIT_FS_CLI0_TRIGGER_PKT_INT_8822B BIT(17)
-#define BIT_FS_CLI0_EOSP_INT_8822B BIT(16)
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8822B BIT(9)
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8822B BIT(8)
-#define BIT_FS_CLI3_TX_NULL1_INT_8822B BIT(7)
-#define BIT_FS_CLI3_TX_NULL0_INT_8822B BIT(6)
-#define BIT_FS_CLI2_TX_NULL1_INT_8822B BIT(5)
-#define BIT_FS_CLI2_TX_NULL0_INT_8822B BIT(4)
-#define BIT_FS_CLI1_TX_NULL1_INT_8822B BIT(3)
-#define BIT_FS_CLI1_TX_NULL0_INT_8822B BIT(2)
-#define BIT_FS_CLI0_TX_NULL1_INT_8822B BIT(1)
-#define BIT_FS_CLI0_TX_NULL0_INT_8822B BIT(0)
-
-/* 2 REG_MSG2_8822B */
-
-#define BIT_SHIFT_FW_MSG2_8822B 0
-#define BIT_MASK_FW_MSG2_8822B 0xffffffffL
-#define BIT_FW_MSG2_8822B(x) \
- (((x) & BIT_MASK_FW_MSG2_8822B) << BIT_SHIFT_FW_MSG2_8822B)
-#define BIT_GET_FW_MSG2_8822B(x) \
- (((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B)
-
-/* 2 REG_MSG3_8822B */
-
-#define BIT_SHIFT_FW_MSG3_8822B 0
-#define BIT_MASK_FW_MSG3_8822B 0xffffffffL
-#define BIT_FW_MSG3_8822B(x) \
- (((x) & BIT_MASK_FW_MSG3_8822B) << BIT_SHIFT_FW_MSG3_8822B)
-#define BIT_GET_FW_MSG3_8822B(x) \
- (((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B)
-
-/* 2 REG_MSG4_8822B */
-
-#define BIT_SHIFT_FW_MSG4_8822B 0
-#define BIT_MASK_FW_MSG4_8822B 0xffffffffL
-#define BIT_FW_MSG4_8822B(x) \
- (((x) & BIT_MASK_FW_MSG4_8822B) << BIT_SHIFT_FW_MSG4_8822B)
-#define BIT_GET_FW_MSG4_8822B(x) \
- (((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B)
-
-/* 2 REG_MSG5_8822B */
-
-#define BIT_SHIFT_FW_MSG5_8822B 0
-#define BIT_MASK_FW_MSG5_8822B 0xffffffffL
-#define BIT_FW_MSG5_8822B(x) \
- (((x) & BIT_MASK_FW_MSG5_8822B) << BIT_SHIFT_FW_MSG5_8822B)
-#define BIT_GET_FW_MSG5_8822B(x) \
- (((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_FIFOPAGE_CTRL_1_8822B */
-
-#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B 16
-#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B 0xff
-#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \
- (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) \
- << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B)
-#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \
- (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) & \
- BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B)
-
-#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B 0
-#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B 0xff
-#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \
- (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) \
- << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B)
-#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \
- (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) & \
- BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B)
-
-/* 2 REG_FIFOPAGE_CTRL_2_8822B */
-#define BIT_BCN_VALID_1_V1_8822B BIT(31)
-
-#define BIT_SHIFT_BCN_HEAD_1_V1_8822B 16
-#define BIT_MASK_BCN_HEAD_1_V1_8822B 0xfff
-#define BIT_BCN_HEAD_1_V1_8822B(x) \
- (((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B)
-#define BIT_GET_BCN_HEAD_1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B)
-
-#define BIT_BCN_VALID_V1_8822B BIT(15)
-
-#define BIT_SHIFT_BCN_HEAD_V1_8822B 0
-#define BIT_MASK_BCN_HEAD_V1_8822B 0xfff
-#define BIT_BCN_HEAD_V1_8822B(x) \
- (((x) & BIT_MASK_BCN_HEAD_V1_8822B) << BIT_SHIFT_BCN_HEAD_V1_8822B)
-#define BIT_GET_BCN_HEAD_V1_8822B(x) \
- (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B)
-
-/* 2 REG_AUTO_LLT_V1_8822B */
-
-#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 24
-#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 0xff
-#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \
- (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) \
- << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
-#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \
- (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) & \
- BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
-
-#define BIT_SHIFT_LLT_FREE_PAGE_V1_8822B 8
-#define BIT_MASK_LLT_FREE_PAGE_V1_8822B 0xffff
-#define BIT_LLT_FREE_PAGE_V1_8822B(x) \
- (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) \
- << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B)
-#define BIT_GET_LLT_FREE_PAGE_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) & \
- BIT_MASK_LLT_FREE_PAGE_V1_8822B)
-
-#define BIT_SHIFT_BLK_DESC_NUM_8822B 4
-#define BIT_MASK_BLK_DESC_NUM_8822B 0xf
-#define BIT_BLK_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B)
-#define BIT_GET_BLK_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B)
-
-#define BIT_R_BCN_HEAD_SEL_8822B BIT(3)
-#define BIT_R_EN_BCN_SW_HEAD_SEL_8822B BIT(2)
-#define BIT_LLT_DBG_SEL_8822B BIT(1)
-#define BIT_AUTO_INIT_LLT_V1_8822B BIT(0)
-
-/* 2 REG_TXDMA_OFFSET_CHK_8822B */
-#define BIT_EM_CHKSUM_FIN_8822B BIT(31)
-#define BIT_EMN_PCIE_DMA_MOD_8822B BIT(30)
-#define BIT_EN_TXQUE_CLR_8822B BIT(29)
-#define BIT_EN_PCIE_FIFO_MODE_8822B BIT(28)
-
-#define BIT_SHIFT_PG_UNDER_TH_V1_8822B 16
-#define BIT_MASK_PG_UNDER_TH_V1_8822B 0xfff
-#define BIT_PG_UNDER_TH_V1_8822B(x) \
- (((x) & BIT_MASK_PG_UNDER_TH_V1_8822B) \
- << BIT_SHIFT_PG_UNDER_TH_V1_8822B)
-#define BIT_GET_PG_UNDER_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) & \
- BIT_MASK_PG_UNDER_TH_V1_8822B)
-
-#define BIT_RESTORE_H2C_ADDRESS_8822B BIT(15)
-#define BIT_SDIO_TXDESC_CHKSUM_EN_8822B BIT(13)
-#define BIT_RST_RDPTR_8822B BIT(12)
-#define BIT_RST_WRPTR_8822B BIT(11)
-#define BIT_CHK_PG_TH_EN_8822B BIT(10)
-#define BIT_DROP_DATA_EN_8822B BIT(9)
-#define BIT_CHECK_OFFSET_EN_8822B BIT(8)
-
-#define BIT_SHIFT_CHECK_OFFSET_8822B 0
-#define BIT_MASK_CHECK_OFFSET_8822B 0xff
-#define BIT_CHECK_OFFSET_8822B(x) \
- (((x) & BIT_MASK_CHECK_OFFSET_8822B) << BIT_SHIFT_CHECK_OFFSET_8822B)
-#define BIT_GET_CHECK_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B)
-
-/* 2 REG_TXDMA_STATUS_8822B */
-#define BIT_HI_OQT_UDN_8822B BIT(17)
-#define BIT_HI_OQT_OVF_8822B BIT(16)
-#define BIT_PAYLOAD_CHKSUM_ERR_8822B BIT(15)
-#define BIT_PAYLOAD_UDN_8822B BIT(14)
-#define BIT_PAYLOAD_OVF_8822B BIT(13)
-#define BIT_DSC_CHKSUM_FAIL_8822B BIT(12)
-#define BIT_UNKNOWN_QSEL_8822B BIT(11)
-#define BIT_EP_QSEL_DIFF_8822B BIT(10)
-#define BIT_TX_OFFS_UNMATCH_8822B BIT(9)
-#define BIT_TXOQT_UDN_8822B BIT(8)
-#define BIT_TXOQT_OVF_8822B BIT(7)
-#define BIT_TXDMA_SFF_UDN_8822B BIT(6)
-#define BIT_TXDMA_SFF_OVF_8822B BIT(5)
-#define BIT_LLT_NULL_PG_8822B BIT(4)
-#define BIT_PAGE_UDN_8822B BIT(3)
-#define BIT_PAGE_OVF_8822B BIT(2)
-#define BIT_TXFF_PG_UDN_8822B BIT(1)
-#define BIT_TXFF_PG_OVF_8822B BIT(0)
-
-/* 2 REG_TX_DMA_DBG_8822B */
-
-/* 2 REG_TQPNT1_8822B */
-
-#define BIT_SHIFT_HPQ_HIGH_TH_V1_8822B 16
-#define BIT_MASK_HPQ_HIGH_TH_V1_8822B 0xfff
-#define BIT_HPQ_HIGH_TH_V1_8822B(x) \
- (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) \
- << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B)
-#define BIT_GET_HPQ_HIGH_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) & \
- BIT_MASK_HPQ_HIGH_TH_V1_8822B)
-
-#define BIT_SHIFT_HPQ_LOW_TH_V1_8822B 0
-#define BIT_MASK_HPQ_LOW_TH_V1_8822B 0xfff
-#define BIT_HPQ_LOW_TH_V1_8822B(x) \
- (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B)
-#define BIT_GET_HPQ_LOW_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B)
-
-/* 2 REG_TQPNT2_8822B */
-
-#define BIT_SHIFT_NPQ_HIGH_TH_V1_8822B 16
-#define BIT_MASK_NPQ_HIGH_TH_V1_8822B 0xfff
-#define BIT_NPQ_HIGH_TH_V1_8822B(x) \
- (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) \
- << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B)
-#define BIT_GET_NPQ_HIGH_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) & \
- BIT_MASK_NPQ_HIGH_TH_V1_8822B)
-
-#define BIT_SHIFT_NPQ_LOW_TH_V1_8822B 0
-#define BIT_MASK_NPQ_LOW_TH_V1_8822B 0xfff
-#define BIT_NPQ_LOW_TH_V1_8822B(x) \
- (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B)
-#define BIT_GET_NPQ_LOW_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B)
-
-/* 2 REG_TQPNT3_8822B */
-
-#define BIT_SHIFT_LPQ_HIGH_TH_V1_8822B 16
-#define BIT_MASK_LPQ_HIGH_TH_V1_8822B 0xfff
-#define BIT_LPQ_HIGH_TH_V1_8822B(x) \
- (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) \
- << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B)
-#define BIT_GET_LPQ_HIGH_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) & \
- BIT_MASK_LPQ_HIGH_TH_V1_8822B)
-
-#define BIT_SHIFT_LPQ_LOW_TH_V1_8822B 0
-#define BIT_MASK_LPQ_LOW_TH_V1_8822B 0xfff
-#define BIT_LPQ_LOW_TH_V1_8822B(x) \
- (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B)
-#define BIT_GET_LPQ_LOW_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B)
-
-/* 2 REG_TQPNT4_8822B */
-
-#define BIT_SHIFT_EXQ_HIGH_TH_V1_8822B 16
-#define BIT_MASK_EXQ_HIGH_TH_V1_8822B 0xfff
-#define BIT_EXQ_HIGH_TH_V1_8822B(x) \
- (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) \
- << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B)
-#define BIT_GET_EXQ_HIGH_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) & \
- BIT_MASK_EXQ_HIGH_TH_V1_8822B)
-
-#define BIT_SHIFT_EXQ_LOW_TH_V1_8822B 0
-#define BIT_MASK_EXQ_LOW_TH_V1_8822B 0xfff
-#define BIT_EXQ_LOW_TH_V1_8822B(x) \
- (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B)
-#define BIT_GET_EXQ_LOW_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B)
-
-/* 2 REG_RQPN_CTRL_1_8822B */
-
-#define BIT_SHIFT_TXPKTNUM_H_8822B 16
-#define BIT_MASK_TXPKTNUM_H_8822B 0xffff
-#define BIT_TXPKTNUM_H_8822B(x) \
- (((x) & BIT_MASK_TXPKTNUM_H_8822B) << BIT_SHIFT_TXPKTNUM_H_8822B)
-#define BIT_GET_TXPKTNUM_H_8822B(x) \
- (((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B)
-
-#define BIT_SHIFT_TXPKTNUM_V2_8822B 0
-#define BIT_MASK_TXPKTNUM_V2_8822B 0xffff
-#define BIT_TXPKTNUM_V2_8822B(x) \
- (((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B)
-#define BIT_GET_TXPKTNUM_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B)
-
-/* 2 REG_RQPN_CTRL_2_8822B */
-#define BIT_LD_RQPN_8822B BIT(31)
-#define BIT_EXQ_PUBLIC_DIS_V1_8822B BIT(19)
-#define BIT_NPQ_PUBLIC_DIS_V1_8822B BIT(18)
-#define BIT_LPQ_PUBLIC_DIS_V1_8822B BIT(17)
-#define BIT_HPQ_PUBLIC_DIS_V1_8822B BIT(16)
-
-/* 2 REG_FIFOPAGE_INFO_1_8822B */
-
-#define BIT_SHIFT_HPQ_AVAL_PG_V1_8822B 16
-#define BIT_MASK_HPQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_HPQ_AVAL_PG_V1_8822B(x) \
- (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) \
- << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B)
-#define BIT_GET_HPQ_AVAL_PG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) & \
- BIT_MASK_HPQ_AVAL_PG_V1_8822B)
-
-#define BIT_SHIFT_HPQ_V1_8822B 0
-#define BIT_MASK_HPQ_V1_8822B 0xfff
-#define BIT_HPQ_V1_8822B(x) \
- (((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B)
-#define BIT_GET_HPQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B)
-
-/* 2 REG_FIFOPAGE_INFO_2_8822B */
-
-#define BIT_SHIFT_LPQ_AVAL_PG_V1_8822B 16
-#define BIT_MASK_LPQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_LPQ_AVAL_PG_V1_8822B(x) \
- (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) \
- << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B)
-#define BIT_GET_LPQ_AVAL_PG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) & \
- BIT_MASK_LPQ_AVAL_PG_V1_8822B)
-
-#define BIT_SHIFT_LPQ_V1_8822B 0
-#define BIT_MASK_LPQ_V1_8822B 0xfff
-#define BIT_LPQ_V1_8822B(x) \
- (((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B)
-#define BIT_GET_LPQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B)
-
-/* 2 REG_FIFOPAGE_INFO_3_8822B */
-
-#define BIT_SHIFT_NPQ_AVAL_PG_V1_8822B 16
-#define BIT_MASK_NPQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_NPQ_AVAL_PG_V1_8822B(x) \
- (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) \
- << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B)
-#define BIT_GET_NPQ_AVAL_PG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) & \
- BIT_MASK_NPQ_AVAL_PG_V1_8822B)
-
-#define BIT_SHIFT_NPQ_V1_8822B 0
-#define BIT_MASK_NPQ_V1_8822B 0xfff
-#define BIT_NPQ_V1_8822B(x) \
- (((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B)
-#define BIT_GET_NPQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B)
-
-/* 2 REG_FIFOPAGE_INFO_4_8822B */
-
-#define BIT_SHIFT_EXQ_AVAL_PG_V1_8822B 16
-#define BIT_MASK_EXQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_EXQ_AVAL_PG_V1_8822B(x) \
- (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) \
- << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B)
-#define BIT_GET_EXQ_AVAL_PG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) & \
- BIT_MASK_EXQ_AVAL_PG_V1_8822B)
-
-#define BIT_SHIFT_EXQ_V1_8822B 0
-#define BIT_MASK_EXQ_V1_8822B 0xfff
-#define BIT_EXQ_V1_8822B(x) \
- (((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B)
-#define BIT_GET_EXQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B)
-
-/* 2 REG_FIFOPAGE_INFO_5_8822B */
-
-#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B 16
-#define BIT_MASK_PUBQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_PUBQ_AVAL_PG_V1_8822B(x) \
- (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) \
- << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B)
-#define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) & \
- BIT_MASK_PUBQ_AVAL_PG_V1_8822B)
-
-#define BIT_SHIFT_PUBQ_V1_8822B 0
-#define BIT_MASK_PUBQ_V1_8822B 0xfff
-#define BIT_PUBQ_V1_8822B(x) \
- (((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B)
-#define BIT_GET_PUBQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B)
-
-/* 2 REG_H2C_HEAD_8822B */
-
-#define BIT_SHIFT_H2C_HEAD_8822B 0
-#define BIT_MASK_H2C_HEAD_8822B 0x3ffff
-#define BIT_H2C_HEAD_8822B(x) \
- (((x) & BIT_MASK_H2C_HEAD_8822B) << BIT_SHIFT_H2C_HEAD_8822B)
-#define BIT_GET_H2C_HEAD_8822B(x) \
- (((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B)
-
-/* 2 REG_H2C_TAIL_8822B */
-
-#define BIT_SHIFT_H2C_TAIL_8822B 0
-#define BIT_MASK_H2C_TAIL_8822B 0x3ffff
-#define BIT_H2C_TAIL_8822B(x) \
- (((x) & BIT_MASK_H2C_TAIL_8822B) << BIT_SHIFT_H2C_TAIL_8822B)
-#define BIT_GET_H2C_TAIL_8822B(x) \
- (((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B)
-
-/* 2 REG_H2C_READ_ADDR_8822B */
-
-#define BIT_SHIFT_H2C_READ_ADDR_8822B 0
-#define BIT_MASK_H2C_READ_ADDR_8822B 0x3ffff
-#define BIT_H2C_READ_ADDR_8822B(x) \
- (((x) & BIT_MASK_H2C_READ_ADDR_8822B) << BIT_SHIFT_H2C_READ_ADDR_8822B)
-#define BIT_GET_H2C_READ_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B)
-
-/* 2 REG_H2C_WR_ADDR_8822B */
-
-#define BIT_SHIFT_H2C_WR_ADDR_8822B 0
-#define BIT_MASK_H2C_WR_ADDR_8822B 0x3ffff
-#define BIT_H2C_WR_ADDR_8822B(x) \
- (((x) & BIT_MASK_H2C_WR_ADDR_8822B) << BIT_SHIFT_H2C_WR_ADDR_8822B)
-#define BIT_GET_H2C_WR_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B)
-
-/* 2 REG_H2C_INFO_8822B */
-#define BIT_H2C_SPACE_VLD_8822B BIT(3)
-#define BIT_H2C_WR_ADDR_RST_8822B BIT(2)
-
-#define BIT_SHIFT_H2C_LEN_SEL_8822B 0
-#define BIT_MASK_H2C_LEN_SEL_8822B 0x3
-#define BIT_H2C_LEN_SEL_8822B(x) \
- (((x) & BIT_MASK_H2C_LEN_SEL_8822B) << BIT_SHIFT_H2C_LEN_SEL_8822B)
-#define BIT_GET_H2C_LEN_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B)
-
-/* 2 REG_RXDMA_AGG_PG_TH_8822B */
-
-#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B 24
-#define BIT_MASK_RXDMA_AGG_OLD_MOD_8822B 0xff
-#define BIT_RXDMA_AGG_OLD_MOD_8822B(x) \
- (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8822B) \
- << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B)
-#define BIT_GET_RXDMA_AGG_OLD_MOD_8822B(x) \
- (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B) & \
- BIT_MASK_RXDMA_AGG_OLD_MOD_8822B)
-
-#define BIT_SHIFT_PKT_NUM_WOL_8822B 16
-#define BIT_MASK_PKT_NUM_WOL_8822B 0xff
-#define BIT_PKT_NUM_WOL_8822B(x) \
- (((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B)
-#define BIT_GET_PKT_NUM_WOL_8822B(x) \
- (((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B)
-
-#define BIT_SHIFT_DMA_AGG_TO_8822B 8
-#define BIT_MASK_DMA_AGG_TO_8822B 0xf
-#define BIT_DMA_AGG_TO_8822B(x) \
- (((x) & BIT_MASK_DMA_AGG_TO_8822B) << BIT_SHIFT_DMA_AGG_TO_8822B)
-#define BIT_GET_DMA_AGG_TO_8822B(x) \
- (((x) >> BIT_SHIFT_DMA_AGG_TO_8822B) & BIT_MASK_DMA_AGG_TO_8822B)
-
-#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B 0
-#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B 0xf
-#define BIT_RXDMA_AGG_PG_TH_V1_8822B(x) \
- (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B) \
- << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B)
-#define BIT_GET_RXDMA_AGG_PG_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B) & \
- BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B)
-
-/* 2 REG_RXPKT_NUM_8822B */
-
-#define BIT_SHIFT_RXPKT_NUM_8822B 24
-#define BIT_MASK_RXPKT_NUM_8822B 0xff
-#define BIT_RXPKT_NUM_8822B(x) \
- (((x) & BIT_MASK_RXPKT_NUM_8822B) << BIT_SHIFT_RXPKT_NUM_8822B)
-#define BIT_GET_RXPKT_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B)
-
-#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B 20
-#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B 0xf
-#define BIT_FW_UPD_RDPTR19_TO_16_8822B(x) \
- (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) \
- << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B)
-#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x) \
- (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) & \
- BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B)
-
-#define BIT_RXDMA_REQ_8822B BIT(19)
-#define BIT_RW_RELEASE_EN_8822B BIT(18)
-#define BIT_RXDMA_IDLE_8822B BIT(17)
-#define BIT_RXPKT_RELEASE_POLL_8822B BIT(16)
-
-#define BIT_SHIFT_FW_UPD_RDPTR_8822B 0
-#define BIT_MASK_FW_UPD_RDPTR_8822B 0xffff
-#define BIT_FW_UPD_RDPTR_8822B(x) \
- (((x) & BIT_MASK_FW_UPD_RDPTR_8822B) << BIT_SHIFT_FW_UPD_RDPTR_8822B)
-#define BIT_GET_FW_UPD_RDPTR_8822B(x) \
- (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B)
-
-/* 2 REG_RXDMA_STATUS_8822B */
-#define BIT_C2H_PKT_OVF_8822B BIT(7)
-#define BIT_AGG_CONFGI_ISSUE_8822B BIT(6)
-#define BIT_FW_POLL_ISSUE_8822B BIT(5)
-#define BIT_RX_DATA_UDN_8822B BIT(4)
-#define BIT_RX_SFF_UDN_8822B BIT(3)
-#define BIT_RX_SFF_OVF_8822B BIT(2)
-#define BIT_RXPKT_OVF_8822B BIT(0)
-
-/* 2 REG_RXDMA_DPR_8822B */
-
-#define BIT_SHIFT_RDE_DEBUG_8822B 0
-#define BIT_MASK_RDE_DEBUG_8822B 0xffffffffL
-#define BIT_RDE_DEBUG_8822B(x) \
- (((x) & BIT_MASK_RDE_DEBUG_8822B) << BIT_SHIFT_RDE_DEBUG_8822B)
-#define BIT_GET_RDE_DEBUG_8822B(x) \
- (((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B)
-
-/* 2 REG_RXDMA_MODE_8822B */
-
-#define BIT_SHIFT_PKTNUM_TH_V2_8822B 24
-#define BIT_MASK_PKTNUM_TH_V2_8822B 0x1f
-#define BIT_PKTNUM_TH_V2_8822B(x) \
- (((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B)
-#define BIT_GET_PKTNUM_TH_V2_8822B(x) \
- (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B)
-
-#define BIT_TXBA_BREAK_USBAGG_8822B BIT(23)
-
-#define BIT_SHIFT_PKTLEN_PARA_8822B 16
-#define BIT_MASK_PKTLEN_PARA_8822B 0x7
-#define BIT_PKTLEN_PARA_8822B(x) \
- (((x) & BIT_MASK_PKTLEN_PARA_8822B) << BIT_SHIFT_PKTLEN_PARA_8822B)
-#define BIT_GET_PKTLEN_PARA_8822B(x) \
- (((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_BURST_SIZE_8822B 4
-#define BIT_MASK_BURST_SIZE_8822B 0x3
-#define BIT_BURST_SIZE_8822B(x) \
- (((x) & BIT_MASK_BURST_SIZE_8822B) << BIT_SHIFT_BURST_SIZE_8822B)
-#define BIT_GET_BURST_SIZE_8822B(x) \
- (((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B)
-
-#define BIT_SHIFT_BURST_CNT_8822B 2
-#define BIT_MASK_BURST_CNT_8822B 0x3
-#define BIT_BURST_CNT_8822B(x) \
- (((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B)
-#define BIT_GET_BURST_CNT_8822B(x) \
- (((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B)
-
-#define BIT_DMA_MODE_8822B BIT(1)
-
-/* 2 REG_C2H_PKT_8822B */
-
-#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B 24
-#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B 0xf
-#define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x) \
- (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) \
- << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B)
-#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x) \
- (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) & \
- BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B)
-
-#define BIT_R_C2H_PKT_REQ_8822B BIT(16)
-
-#define BIT_SHIFT_R_C2H_STR_ADDR_8822B 0
-#define BIT_MASK_R_C2H_STR_ADDR_8822B 0xffff
-#define BIT_R_C2H_STR_ADDR_8822B(x) \
- (((x) & BIT_MASK_R_C2H_STR_ADDR_8822B) \
- << BIT_SHIFT_R_C2H_STR_ADDR_8822B)
-#define BIT_GET_R_C2H_STR_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) & \
- BIT_MASK_R_C2H_STR_ADDR_8822B)
-
-/* 2 REG_FWFF_C2H_8822B */
-
-#define BIT_SHIFT_C2H_DMA_ADDR_8822B 0
-#define BIT_MASK_C2H_DMA_ADDR_8822B 0x3ffff
-#define BIT_C2H_DMA_ADDR_8822B(x) \
- (((x) & BIT_MASK_C2H_DMA_ADDR_8822B) << BIT_SHIFT_C2H_DMA_ADDR_8822B)
-#define BIT_GET_C2H_DMA_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B)
-
-/* 2 REG_FWFF_CTRL_8822B */
-#define BIT_FWFF_DMAPKT_REQ_8822B BIT(31)
-
-#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B 16
-#define BIT_MASK_FWFF_DMA_PKT_NUM_8822B 0xff
-#define BIT_FWFF_DMA_PKT_NUM_8822B(x) \
- (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) \
- << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B)
-#define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) & \
- BIT_MASK_FWFF_DMA_PKT_NUM_8822B)
-
-#define BIT_SHIFT_FWFF_STR_ADDR_8822B 0
-#define BIT_MASK_FWFF_STR_ADDR_8822B 0xffff
-#define BIT_FWFF_STR_ADDR_8822B(x) \
- (((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B)
-#define BIT_GET_FWFF_STR_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B)
-
-/* 2 REG_FWFF_PKT_INFO_8822B */
-
-#define BIT_SHIFT_FWFF_PKT_QUEUED_8822B 16
-#define BIT_MASK_FWFF_PKT_QUEUED_8822B 0xff
-#define BIT_FWFF_PKT_QUEUED_8822B(x) \
- (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822B) \
- << BIT_SHIFT_FWFF_PKT_QUEUED_8822B)
-#define BIT_GET_FWFF_PKT_QUEUED_8822B(x) \
- (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) & \
- BIT_MASK_FWFF_PKT_QUEUED_8822B)
-
-#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B 0
-#define BIT_MASK_FWFF_PKT_STR_ADDR_8822B 0xffff
-#define BIT_FWFF_PKT_STR_ADDR_8822B(x) \
- (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) \
- << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B)
-#define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) & \
- BIT_MASK_FWFF_PKT_STR_ADDR_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_DDMA_CH0SA_8822B */
-
-#define BIT_SHIFT_DDMACH0_SA_8822B 0
-#define BIT_MASK_DDMACH0_SA_8822B 0xffffffffL
-#define BIT_DDMACH0_SA_8822B(x) \
- (((x) & BIT_MASK_DDMACH0_SA_8822B) << BIT_SHIFT_DDMACH0_SA_8822B)
-#define BIT_GET_DDMACH0_SA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B)
-
-/* 2 REG_DDMA_CH0DA_8822B */
-
-#define BIT_SHIFT_DDMACH0_DA_8822B 0
-#define BIT_MASK_DDMACH0_DA_8822B 0xffffffffL
-#define BIT_DDMACH0_DA_8822B(x) \
- (((x) & BIT_MASK_DDMACH0_DA_8822B) << BIT_SHIFT_DDMACH0_DA_8822B)
-#define BIT_GET_DDMACH0_DA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B)
-
-/* 2 REG_DDMA_CH0CTRL_8822B */
-#define BIT_DDMACH0_OWN_8822B BIT(31)
-#define BIT_DDMACH0_CHKSUM_EN_8822B BIT(29)
-#define BIT_DDMACH0_DA_W_DISABLE_8822B BIT(28)
-#define BIT_DDMACH0_CHKSUM_STS_8822B BIT(27)
-#define BIT_DDMACH0_DDMA_MODE_8822B BIT(26)
-#define BIT_DDMACH0_RESET_CHKSUM_STS_8822B BIT(25)
-#define BIT_DDMACH0_CHKSUM_CONT_8822B BIT(24)
-
-#define BIT_SHIFT_DDMACH0_DLEN_8822B 0
-#define BIT_MASK_DDMACH0_DLEN_8822B 0x3ffff
-#define BIT_DDMACH0_DLEN_8822B(x) \
- (((x) & BIT_MASK_DDMACH0_DLEN_8822B) << BIT_SHIFT_DDMACH0_DLEN_8822B)
-#define BIT_GET_DDMACH0_DLEN_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B)
-
-/* 2 REG_DDMA_CH1SA_8822B */
-
-#define BIT_SHIFT_DDMACH1_SA_8822B 0
-#define BIT_MASK_DDMACH1_SA_8822B 0xffffffffL
-#define BIT_DDMACH1_SA_8822B(x) \
- (((x) & BIT_MASK_DDMACH1_SA_8822B) << BIT_SHIFT_DDMACH1_SA_8822B)
-#define BIT_GET_DDMACH1_SA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B)
-
-/* 2 REG_DDMA_CH1DA_8822B */
-
-#define BIT_SHIFT_DDMACH1_DA_8822B 0
-#define BIT_MASK_DDMACH1_DA_8822B 0xffffffffL
-#define BIT_DDMACH1_DA_8822B(x) \
- (((x) & BIT_MASK_DDMACH1_DA_8822B) << BIT_SHIFT_DDMACH1_DA_8822B)
-#define BIT_GET_DDMACH1_DA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B)
-
-/* 2 REG_DDMA_CH1CTRL_8822B */
-#define BIT_DDMACH1_OWN_8822B BIT(31)
-#define BIT_DDMACH1_CHKSUM_EN_8822B BIT(29)
-#define BIT_DDMACH1_DA_W_DISABLE_8822B BIT(28)
-#define BIT_DDMACH1_CHKSUM_STS_8822B BIT(27)
-#define BIT_DDMACH1_DDMA_MODE_8822B BIT(26)
-#define BIT_DDMACH1_RESET_CHKSUM_STS_8822B BIT(25)
-#define BIT_DDMACH1_CHKSUM_CONT_8822B BIT(24)
-
-#define BIT_SHIFT_DDMACH1_DLEN_8822B 0
-#define BIT_MASK_DDMACH1_DLEN_8822B 0x3ffff
-#define BIT_DDMACH1_DLEN_8822B(x) \
- (((x) & BIT_MASK_DDMACH1_DLEN_8822B) << BIT_SHIFT_DDMACH1_DLEN_8822B)
-#define BIT_GET_DDMACH1_DLEN_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B)
-
-/* 2 REG_DDMA_CH2SA_8822B */
-
-#define BIT_SHIFT_DDMACH2_SA_8822B 0
-#define BIT_MASK_DDMACH2_SA_8822B 0xffffffffL
-#define BIT_DDMACH2_SA_8822B(x) \
- (((x) & BIT_MASK_DDMACH2_SA_8822B) << BIT_SHIFT_DDMACH2_SA_8822B)
-#define BIT_GET_DDMACH2_SA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B)
-
-/* 2 REG_DDMA_CH2DA_8822B */
-
-#define BIT_SHIFT_DDMACH2_DA_8822B 0
-#define BIT_MASK_DDMACH2_DA_8822B 0xffffffffL
-#define BIT_DDMACH2_DA_8822B(x) \
- (((x) & BIT_MASK_DDMACH2_DA_8822B) << BIT_SHIFT_DDMACH2_DA_8822B)
-#define BIT_GET_DDMACH2_DA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B)
-
-/* 2 REG_DDMA_CH2CTRL_8822B */
-#define BIT_DDMACH2_OWN_8822B BIT(31)
-#define BIT_DDMACH2_CHKSUM_EN_8822B BIT(29)
-#define BIT_DDMACH2_DA_W_DISABLE_8822B BIT(28)
-#define BIT_DDMACH2_CHKSUM_STS_8822B BIT(27)
-#define BIT_DDMACH2_DDMA_MODE_8822B BIT(26)
-#define BIT_DDMACH2_RESET_CHKSUM_STS_8822B BIT(25)
-#define BIT_DDMACH2_CHKSUM_CONT_8822B BIT(24)
-
-#define BIT_SHIFT_DDMACH2_DLEN_8822B 0
-#define BIT_MASK_DDMACH2_DLEN_8822B 0x3ffff
-#define BIT_DDMACH2_DLEN_8822B(x) \
- (((x) & BIT_MASK_DDMACH2_DLEN_8822B) << BIT_SHIFT_DDMACH2_DLEN_8822B)
-#define BIT_GET_DDMACH2_DLEN_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B)
-
-/* 2 REG_DDMA_CH3SA_8822B */
-
-#define BIT_SHIFT_DDMACH3_SA_8822B 0
-#define BIT_MASK_DDMACH3_SA_8822B 0xffffffffL
-#define BIT_DDMACH3_SA_8822B(x) \
- (((x) & BIT_MASK_DDMACH3_SA_8822B) << BIT_SHIFT_DDMACH3_SA_8822B)
-#define BIT_GET_DDMACH3_SA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B)
-
-/* 2 REG_DDMA_CH3DA_8822B */
-
-#define BIT_SHIFT_DDMACH3_DA_8822B 0
-#define BIT_MASK_DDMACH3_DA_8822B 0xffffffffL
-#define BIT_DDMACH3_DA_8822B(x) \
- (((x) & BIT_MASK_DDMACH3_DA_8822B) << BIT_SHIFT_DDMACH3_DA_8822B)
-#define BIT_GET_DDMACH3_DA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B)
-
-/* 2 REG_DDMA_CH3CTRL_8822B */
-#define BIT_DDMACH3_OWN_8822B BIT(31)
-#define BIT_DDMACH3_CHKSUM_EN_8822B BIT(29)
-#define BIT_DDMACH3_DA_W_DISABLE_8822B BIT(28)
-#define BIT_DDMACH3_CHKSUM_STS_8822B BIT(27)
-#define BIT_DDMACH3_DDMA_MODE_8822B BIT(26)
-#define BIT_DDMACH3_RESET_CHKSUM_STS_8822B BIT(25)
-#define BIT_DDMACH3_CHKSUM_CONT_8822B BIT(24)
-
-#define BIT_SHIFT_DDMACH3_DLEN_8822B 0
-#define BIT_MASK_DDMACH3_DLEN_8822B 0x3ffff
-#define BIT_DDMACH3_DLEN_8822B(x) \
- (((x) & BIT_MASK_DDMACH3_DLEN_8822B) << BIT_SHIFT_DDMACH3_DLEN_8822B)
-#define BIT_GET_DDMACH3_DLEN_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B)
-
-/* 2 REG_DDMA_CH4SA_8822B */
-
-#define BIT_SHIFT_DDMACH4_SA_8822B 0
-#define BIT_MASK_DDMACH4_SA_8822B 0xffffffffL
-#define BIT_DDMACH4_SA_8822B(x) \
- (((x) & BIT_MASK_DDMACH4_SA_8822B) << BIT_SHIFT_DDMACH4_SA_8822B)
-#define BIT_GET_DDMACH4_SA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B)
-
-/* 2 REG_DDMA_CH4DA_8822B */
-
-#define BIT_SHIFT_DDMACH4_DA_8822B 0
-#define BIT_MASK_DDMACH4_DA_8822B 0xffffffffL
-#define BIT_DDMACH4_DA_8822B(x) \
- (((x) & BIT_MASK_DDMACH4_DA_8822B) << BIT_SHIFT_DDMACH4_DA_8822B)
-#define BIT_GET_DDMACH4_DA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B)
-
-/* 2 REG_DDMA_CH4CTRL_8822B */
-#define BIT_DDMACH4_OWN_8822B BIT(31)
-#define BIT_DDMACH4_CHKSUM_EN_8822B BIT(29)
-#define BIT_DDMACH4_DA_W_DISABLE_8822B BIT(28)
-#define BIT_DDMACH4_CHKSUM_STS_8822B BIT(27)
-#define BIT_DDMACH4_DDMA_MODE_8822B BIT(26)
-#define BIT_DDMACH4_RESET_CHKSUM_STS_8822B BIT(25)
-#define BIT_DDMACH4_CHKSUM_CONT_8822B BIT(24)
-
-#define BIT_SHIFT_DDMACH4_DLEN_8822B 0
-#define BIT_MASK_DDMACH4_DLEN_8822B 0x3ffff
-#define BIT_DDMACH4_DLEN_8822B(x) \
- (((x) & BIT_MASK_DDMACH4_DLEN_8822B) << BIT_SHIFT_DDMACH4_DLEN_8822B)
-#define BIT_GET_DDMACH4_DLEN_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B)
-
-/* 2 REG_DDMA_CH5SA_8822B */
-
-#define BIT_SHIFT_DDMACH5_SA_8822B 0
-#define BIT_MASK_DDMACH5_SA_8822B 0xffffffffL
-#define BIT_DDMACH5_SA_8822B(x) \
- (((x) & BIT_MASK_DDMACH5_SA_8822B) << BIT_SHIFT_DDMACH5_SA_8822B)
-#define BIT_GET_DDMACH5_SA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B)
-
-/* 2 REG_DDMA_CH5DA_8822B */
-
-#define BIT_SHIFT_DDMACH5_DA_8822B 0
-#define BIT_MASK_DDMACH5_DA_8822B 0xffffffffL
-#define BIT_DDMACH5_DA_8822B(x) \
- (((x) & BIT_MASK_DDMACH5_DA_8822B) << BIT_SHIFT_DDMACH5_DA_8822B)
-#define BIT_GET_DDMACH5_DA_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B)
-
-/* 2 REG_REG_DDMA_CH5CTRL_8822B */
-#define BIT_DDMACH5_OWN_8822B BIT(31)
-#define BIT_DDMACH5_CHKSUM_EN_8822B BIT(29)
-#define BIT_DDMACH5_DA_W_DISABLE_8822B BIT(28)
-#define BIT_DDMACH5_CHKSUM_STS_8822B BIT(27)
-#define BIT_DDMACH5_DDMA_MODE_8822B BIT(26)
-#define BIT_DDMACH5_RESET_CHKSUM_STS_8822B BIT(25)
-#define BIT_DDMACH5_CHKSUM_CONT_8822B BIT(24)
-
-#define BIT_SHIFT_DDMACH5_DLEN_8822B 0
-#define BIT_MASK_DDMACH5_DLEN_8822B 0x3ffff
-#define BIT_DDMACH5_DLEN_8822B(x) \
- (((x) & BIT_MASK_DDMACH5_DLEN_8822B) << BIT_SHIFT_DDMACH5_DLEN_8822B)
-#define BIT_GET_DDMACH5_DLEN_8822B(x) \
- (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B)
-
-/* 2 REG_DDMA_INT_MSK_8822B */
-#define BIT_DDMACH5_MSK_8822B BIT(5)
-#define BIT_DDMACH4_MSK_8822B BIT(4)
-#define BIT_DDMACH3_MSK_8822B BIT(3)
-#define BIT_DDMACH2_MSK_8822B BIT(2)
-#define BIT_DDMACH1_MSK_8822B BIT(1)
-#define BIT_DDMACH0_MSK_8822B BIT(0)
-
-/* 2 REG_DDMA_CHSTATUS_8822B */
-#define BIT_DDMACH5_BUSY_8822B BIT(5)
-#define BIT_DDMACH4_BUSY_8822B BIT(4)
-#define BIT_DDMACH3_BUSY_8822B BIT(3)
-#define BIT_DDMACH2_BUSY_8822B BIT(2)
-#define BIT_DDMACH1_BUSY_8822B BIT(1)
-#define BIT_DDMACH0_BUSY_8822B BIT(0)
-
-/* 2 REG_DDMA_CHKSUM_8822B */
-
-#define BIT_SHIFT_IDDMA0_CHKSUM_8822B 0
-#define BIT_MASK_IDDMA0_CHKSUM_8822B 0xffff
-#define BIT_IDDMA0_CHKSUM_8822B(x) \
- (((x) & BIT_MASK_IDDMA0_CHKSUM_8822B) << BIT_SHIFT_IDDMA0_CHKSUM_8822B)
-#define BIT_GET_IDDMA0_CHKSUM_8822B(x) \
- (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B)
-
-/* 2 REG_DDMA_MONITOR_8822B */
-#define BIT_IDDMA0_PERMU_UNDERFLOW_8822B BIT(14)
-#define BIT_IDDMA0_FIFO_UNDERFLOW_8822B BIT(13)
-#define BIT_IDDMA0_FIFO_OVERFLOW_8822B BIT(12)
-#define BIT_CH5_ERR_8822B BIT(5)
-#define BIT_CH4_ERR_8822B BIT(4)
-#define BIT_CH3_ERR_8822B BIT(3)
-#define BIT_CH2_ERR_8822B BIT(2)
-#define BIT_CH1_ERR_8822B BIT(1)
-#define BIT_CH0_ERR_8822B BIT(0)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_PCIE_CTRL_8822B */
-#define BIT_PCIEIO_PERSTB_SEL_8822B BIT(31)
-
-#define BIT_SHIFT_PCIE_MAX_RXDMA_8822B 28
-#define BIT_MASK_PCIE_MAX_RXDMA_8822B 0x7
-#define BIT_PCIE_MAX_RXDMA_8822B(x) \
- (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B) \
- << BIT_SHIFT_PCIE_MAX_RXDMA_8822B)
-#define BIT_GET_PCIE_MAX_RXDMA_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) & \
- BIT_MASK_PCIE_MAX_RXDMA_8822B)
-
-#define BIT_MULRW_8822B BIT(27)
-
-#define BIT_SHIFT_PCIE_MAX_TXDMA_8822B 24
-#define BIT_MASK_PCIE_MAX_TXDMA_8822B 0x7
-#define BIT_PCIE_MAX_TXDMA_8822B(x) \
- (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B) \
- << BIT_SHIFT_PCIE_MAX_TXDMA_8822B)
-#define BIT_GET_PCIE_MAX_TXDMA_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) & \
- BIT_MASK_PCIE_MAX_TXDMA_8822B)
-
-#define BIT_EN_CPL_TIMEOUT_PS_8822B BIT(22)
-#define BIT_REG_TXDMA_FAIL_PS_8822B BIT(21)
-#define BIT_PCIE_RST_TRXDMA_INTF_8822B BIT(20)
-#define BIT_EN_HWENTR_L1_8822B BIT(19)
-#define BIT_EN_ADV_CLKGATE_8822B BIT(18)
-#define BIT_PCIE_EN_SWENT_L23_8822B BIT(17)
-#define BIT_PCIE_EN_HWEXT_L1_8822B BIT(16)
-#define BIT_RX_CLOSE_EN_8822B BIT(15)
-#define BIT_STOP_BCNQ_8822B BIT(14)
-#define BIT_STOP_MGQ_8822B BIT(13)
-#define BIT_STOP_VOQ_8822B BIT(12)
-#define BIT_STOP_VIQ_8822B BIT(11)
-#define BIT_STOP_BEQ_8822B BIT(10)
-#define BIT_STOP_BKQ_8822B BIT(9)
-#define BIT_STOP_RXQ_8822B BIT(8)
-#define BIT_STOP_HI7Q_8822B BIT(7)
-#define BIT_STOP_HI6Q_8822B BIT(6)
-#define BIT_STOP_HI5Q_8822B BIT(5)
-#define BIT_STOP_HI4Q_8822B BIT(4)
-#define BIT_STOP_HI3Q_8822B BIT(3)
-#define BIT_STOP_HI2Q_8822B BIT(2)
-#define BIT_STOP_HI1Q_8822B BIT(1)
-#define BIT_STOP_HI0Q_8822B BIT(0)
-
-/* 2 REG_INT_MIG_8822B */
-
-#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B 28
-#define BIT_MASK_TXTTIMER_MATCH_NUM_8822B 0xf
-#define BIT_TXTTIMER_MATCH_NUM_8822B(x) \
- (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) \
- << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B)
-#define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) & \
- BIT_MASK_TXTTIMER_MATCH_NUM_8822B)
-
-#define BIT_SHIFT_TXPKT_NUM_MATCH_8822B 24
-#define BIT_MASK_TXPKT_NUM_MATCH_8822B 0xf
-#define BIT_TXPKT_NUM_MATCH_8822B(x) \
- (((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B) \
- << BIT_SHIFT_TXPKT_NUM_MATCH_8822B)
-#define BIT_GET_TXPKT_NUM_MATCH_8822B(x) \
- (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) & \
- BIT_MASK_TXPKT_NUM_MATCH_8822B)
-
-#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B 20
-#define BIT_MASK_RXTTIMER_MATCH_NUM_8822B 0xf
-#define BIT_RXTTIMER_MATCH_NUM_8822B(x) \
- (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) \
- << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B)
-#define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) & \
- BIT_MASK_RXTTIMER_MATCH_NUM_8822B)
-
-#define BIT_SHIFT_RXPKT_NUM_MATCH_8822B 16
-#define BIT_MASK_RXPKT_NUM_MATCH_8822B 0xf
-#define BIT_RXPKT_NUM_MATCH_8822B(x) \
- (((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B) \
- << BIT_SHIFT_RXPKT_NUM_MATCH_8822B)
-#define BIT_GET_RXPKT_NUM_MATCH_8822B(x) \
- (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) & \
- BIT_MASK_RXPKT_NUM_MATCH_8822B)
-
-#define BIT_SHIFT_MIGRATE_TIMER_8822B 0
-#define BIT_MASK_MIGRATE_TIMER_8822B 0xffff
-#define BIT_MIGRATE_TIMER_8822B(x) \
- (((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B)
-#define BIT_GET_MIGRATE_TIMER_8822B(x) \
- (((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B)
-
-/* 2 REG_BCNQ_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_BCNQ_TXBD_DESA_8822B 0
-#define BIT_MASK_BCNQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_BCNQ_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822B) \
- << BIT_SHIFT_BCNQ_TXBD_DESA_8822B)
-#define BIT_GET_BCNQ_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) & \
- BIT_MASK_BCNQ_TXBD_DESA_8822B)
-
-/* 2 REG_MGQ_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_MGQ_TXBD_DESA_8822B 0
-#define BIT_MASK_MGQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_MGQ_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_MGQ_TXBD_DESA_8822B) << BIT_SHIFT_MGQ_TXBD_DESA_8822B)
-#define BIT_GET_MGQ_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B)
-
-/* 2 REG_VOQ_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_VOQ_TXBD_DESA_8822B 0
-#define BIT_MASK_VOQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_VOQ_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_VOQ_TXBD_DESA_8822B) << BIT_SHIFT_VOQ_TXBD_DESA_8822B)
-#define BIT_GET_VOQ_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B)
-
-/* 2 REG_VIQ_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_VIQ_TXBD_DESA_8822B 0
-#define BIT_MASK_VIQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_VIQ_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_VIQ_TXBD_DESA_8822B) << BIT_SHIFT_VIQ_TXBD_DESA_8822B)
-#define BIT_GET_VIQ_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B)
-
-/* 2 REG_BEQ_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_BEQ_TXBD_DESA_8822B 0
-#define BIT_MASK_BEQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_BEQ_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_BEQ_TXBD_DESA_8822B) << BIT_SHIFT_BEQ_TXBD_DESA_8822B)
-#define BIT_GET_BEQ_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B)
-
-/* 2 REG_BKQ_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_BKQ_TXBD_DESA_8822B 0
-#define BIT_MASK_BKQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_BKQ_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_BKQ_TXBD_DESA_8822B) << BIT_SHIFT_BKQ_TXBD_DESA_8822B)
-#define BIT_GET_BKQ_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B)
-
-/* 2 REG_RXQ_RXBD_DESA_8822B */
-
-#define BIT_SHIFT_RXQ_RXBD_DESA_8822B 0
-#define BIT_MASK_RXQ_RXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_RXQ_RXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_RXQ_RXBD_DESA_8822B) << BIT_SHIFT_RXQ_RXBD_DESA_8822B)
-#define BIT_GET_RXQ_RXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B)
-
-/* 2 REG_HI0Q_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_HI0Q_TXBD_DESA_8822B 0
-#define BIT_MASK_HI0Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI0Q_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822B) \
- << BIT_SHIFT_HI0Q_TXBD_DESA_8822B)
-#define BIT_GET_HI0Q_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) & \
- BIT_MASK_HI0Q_TXBD_DESA_8822B)
-
-/* 2 REG_HI1Q_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_HI1Q_TXBD_DESA_8822B 0
-#define BIT_MASK_HI1Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI1Q_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822B) \
- << BIT_SHIFT_HI1Q_TXBD_DESA_8822B)
-#define BIT_GET_HI1Q_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) & \
- BIT_MASK_HI1Q_TXBD_DESA_8822B)
-
-/* 2 REG_HI2Q_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_HI2Q_TXBD_DESA_8822B 0
-#define BIT_MASK_HI2Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI2Q_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822B) \
- << BIT_SHIFT_HI2Q_TXBD_DESA_8822B)
-#define BIT_GET_HI2Q_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) & \
- BIT_MASK_HI2Q_TXBD_DESA_8822B)
-
-/* 2 REG_HI3Q_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_HI3Q_TXBD_DESA_8822B 0
-#define BIT_MASK_HI3Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI3Q_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822B) \
- << BIT_SHIFT_HI3Q_TXBD_DESA_8822B)
-#define BIT_GET_HI3Q_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) & \
- BIT_MASK_HI3Q_TXBD_DESA_8822B)
-
-/* 2 REG_HI4Q_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_HI4Q_TXBD_DESA_8822B 0
-#define BIT_MASK_HI4Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI4Q_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822B) \
- << BIT_SHIFT_HI4Q_TXBD_DESA_8822B)
-#define BIT_GET_HI4Q_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) & \
- BIT_MASK_HI4Q_TXBD_DESA_8822B)
-
-/* 2 REG_HI5Q_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_HI5Q_TXBD_DESA_8822B 0
-#define BIT_MASK_HI5Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI5Q_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822B) \
- << BIT_SHIFT_HI5Q_TXBD_DESA_8822B)
-#define BIT_GET_HI5Q_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) & \
- BIT_MASK_HI5Q_TXBD_DESA_8822B)
-
-/* 2 REG_HI6Q_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_HI6Q_TXBD_DESA_8822B 0
-#define BIT_MASK_HI6Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI6Q_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822B) \
- << BIT_SHIFT_HI6Q_TXBD_DESA_8822B)
-#define BIT_GET_HI6Q_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) & \
- BIT_MASK_HI6Q_TXBD_DESA_8822B)
-
-/* 2 REG_HI7Q_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_HI7Q_TXBD_DESA_8822B 0
-#define BIT_MASK_HI7Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI7Q_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822B) \
- << BIT_SHIFT_HI7Q_TXBD_DESA_8822B)
-#define BIT_GET_HI7Q_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) & \
- BIT_MASK_HI7Q_TXBD_DESA_8822B)
-
-/* 2 REG_MGQ_TXBD_NUM_8822B */
-#define BIT_PCIE_MGQ_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_MGQ_DESC_MODE_8822B 12
-#define BIT_MASK_MGQ_DESC_MODE_8822B 0x3
-#define BIT_MGQ_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_MGQ_DESC_MODE_8822B) << BIT_SHIFT_MGQ_DESC_MODE_8822B)
-#define BIT_GET_MGQ_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B)
-
-#define BIT_SHIFT_MGQ_DESC_NUM_8822B 0
-#define BIT_MASK_MGQ_DESC_NUM_8822B 0xfff
-#define BIT_MGQ_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B)
-#define BIT_GET_MGQ_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B)
-
-/* 2 REG_RX_RXBD_NUM_8822B */
-#define BIT_SYS_32_64_8822B BIT(15)
-
-#define BIT_SHIFT_BCNQ_DESC_MODE_8822B 13
-#define BIT_MASK_BCNQ_DESC_MODE_8822B 0x3
-#define BIT_BCNQ_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_BCNQ_DESC_MODE_8822B) \
- << BIT_SHIFT_BCNQ_DESC_MODE_8822B)
-#define BIT_GET_BCNQ_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) & \
- BIT_MASK_BCNQ_DESC_MODE_8822B)
-
-#define BIT_PCIE_BCNQ_FLAG_8822B BIT(12)
-
-#define BIT_SHIFT_RXQ_DESC_NUM_8822B 0
-#define BIT_MASK_RXQ_DESC_NUM_8822B 0xfff
-#define BIT_RXQ_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_RXQ_DESC_NUM_8822B) << BIT_SHIFT_RXQ_DESC_NUM_8822B)
-#define BIT_GET_RXQ_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B)
-
-/* 2 REG_VOQ_TXBD_NUM_8822B */
-#define BIT_PCIE_VOQ_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_VOQ_DESC_MODE_8822B 12
-#define BIT_MASK_VOQ_DESC_MODE_8822B 0x3
-#define BIT_VOQ_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_VOQ_DESC_MODE_8822B) << BIT_SHIFT_VOQ_DESC_MODE_8822B)
-#define BIT_GET_VOQ_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B)
-
-#define BIT_SHIFT_VOQ_DESC_NUM_8822B 0
-#define BIT_MASK_VOQ_DESC_NUM_8822B 0xfff
-#define BIT_VOQ_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B)
-#define BIT_GET_VOQ_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B)
-
-/* 2 REG_VIQ_TXBD_NUM_8822B */
-#define BIT_PCIE_VIQ_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_VIQ_DESC_MODE_8822B 12
-#define BIT_MASK_VIQ_DESC_MODE_8822B 0x3
-#define BIT_VIQ_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_VIQ_DESC_MODE_8822B) << BIT_SHIFT_VIQ_DESC_MODE_8822B)
-#define BIT_GET_VIQ_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B)
-
-#define BIT_SHIFT_VIQ_DESC_NUM_8822B 0
-#define BIT_MASK_VIQ_DESC_NUM_8822B 0xfff
-#define BIT_VIQ_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B)
-#define BIT_GET_VIQ_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B)
-
-/* 2 REG_BEQ_TXBD_NUM_8822B */
-#define BIT_PCIE_BEQ_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_BEQ_DESC_MODE_8822B 12
-#define BIT_MASK_BEQ_DESC_MODE_8822B 0x3
-#define BIT_BEQ_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_BEQ_DESC_MODE_8822B) << BIT_SHIFT_BEQ_DESC_MODE_8822B)
-#define BIT_GET_BEQ_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B)
-
-#define BIT_SHIFT_BEQ_DESC_NUM_8822B 0
-#define BIT_MASK_BEQ_DESC_NUM_8822B 0xfff
-#define BIT_BEQ_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B)
-#define BIT_GET_BEQ_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B)
-
-/* 2 REG_BKQ_TXBD_NUM_8822B */
-#define BIT_PCIE_BKQ_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_BKQ_DESC_MODE_8822B 12
-#define BIT_MASK_BKQ_DESC_MODE_8822B 0x3
-#define BIT_BKQ_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_BKQ_DESC_MODE_8822B) << BIT_SHIFT_BKQ_DESC_MODE_8822B)
-#define BIT_GET_BKQ_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B)
-
-#define BIT_SHIFT_BKQ_DESC_NUM_8822B 0
-#define BIT_MASK_BKQ_DESC_NUM_8822B 0xfff
-#define BIT_BKQ_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B)
-#define BIT_GET_BKQ_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B)
-
-/* 2 REG_HI0Q_TXBD_NUM_8822B */
-#define BIT_HI0Q_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_HI0Q_DESC_MODE_8822B 12
-#define BIT_MASK_HI0Q_DESC_MODE_8822B 0x3
-#define BIT_HI0Q_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_HI0Q_DESC_MODE_8822B) \
- << BIT_SHIFT_HI0Q_DESC_MODE_8822B)
-#define BIT_GET_HI0Q_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) & \
- BIT_MASK_HI0Q_DESC_MODE_8822B)
-
-#define BIT_SHIFT_HI0Q_DESC_NUM_8822B 0
-#define BIT_MASK_HI0Q_DESC_NUM_8822B 0xfff
-#define BIT_HI0Q_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B)
-#define BIT_GET_HI0Q_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B)
-
-/* 2 REG_HI1Q_TXBD_NUM_8822B */
-#define BIT_HI1Q_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_HI1Q_DESC_MODE_8822B 12
-#define BIT_MASK_HI1Q_DESC_MODE_8822B 0x3
-#define BIT_HI1Q_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_HI1Q_DESC_MODE_8822B) \
- << BIT_SHIFT_HI1Q_DESC_MODE_8822B)
-#define BIT_GET_HI1Q_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) & \
- BIT_MASK_HI1Q_DESC_MODE_8822B)
-
-#define BIT_SHIFT_HI1Q_DESC_NUM_8822B 0
-#define BIT_MASK_HI1Q_DESC_NUM_8822B 0xfff
-#define BIT_HI1Q_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B)
-#define BIT_GET_HI1Q_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B)
-
-/* 2 REG_HI2Q_TXBD_NUM_8822B */
-#define BIT_HI2Q_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_HI2Q_DESC_MODE_8822B 12
-#define BIT_MASK_HI2Q_DESC_MODE_8822B 0x3
-#define BIT_HI2Q_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_HI2Q_DESC_MODE_8822B) \
- << BIT_SHIFT_HI2Q_DESC_MODE_8822B)
-#define BIT_GET_HI2Q_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) & \
- BIT_MASK_HI2Q_DESC_MODE_8822B)
-
-#define BIT_SHIFT_HI2Q_DESC_NUM_8822B 0
-#define BIT_MASK_HI2Q_DESC_NUM_8822B 0xfff
-#define BIT_HI2Q_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B)
-#define BIT_GET_HI2Q_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B)
-
-/* 2 REG_HI3Q_TXBD_NUM_8822B */
-#define BIT_HI3Q_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_HI3Q_DESC_MODE_8822B 12
-#define BIT_MASK_HI3Q_DESC_MODE_8822B 0x3
-#define BIT_HI3Q_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_HI3Q_DESC_MODE_8822B) \
- << BIT_SHIFT_HI3Q_DESC_MODE_8822B)
-#define BIT_GET_HI3Q_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) & \
- BIT_MASK_HI3Q_DESC_MODE_8822B)
-
-#define BIT_SHIFT_HI3Q_DESC_NUM_8822B 0
-#define BIT_MASK_HI3Q_DESC_NUM_8822B 0xfff
-#define BIT_HI3Q_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B)
-#define BIT_GET_HI3Q_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B)
-
-/* 2 REG_HI4Q_TXBD_NUM_8822B */
-#define BIT_HI4Q_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_HI4Q_DESC_MODE_8822B 12
-#define BIT_MASK_HI4Q_DESC_MODE_8822B 0x3
-#define BIT_HI4Q_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_HI4Q_DESC_MODE_8822B) \
- << BIT_SHIFT_HI4Q_DESC_MODE_8822B)
-#define BIT_GET_HI4Q_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) & \
- BIT_MASK_HI4Q_DESC_MODE_8822B)
-
-#define BIT_SHIFT_HI4Q_DESC_NUM_8822B 0
-#define BIT_MASK_HI4Q_DESC_NUM_8822B 0xfff
-#define BIT_HI4Q_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B)
-#define BIT_GET_HI4Q_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B)
-
-/* 2 REG_HI5Q_TXBD_NUM_8822B */
-#define BIT_HI5Q_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_HI5Q_DESC_MODE_8822B 12
-#define BIT_MASK_HI5Q_DESC_MODE_8822B 0x3
-#define BIT_HI5Q_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_HI5Q_DESC_MODE_8822B) \
- << BIT_SHIFT_HI5Q_DESC_MODE_8822B)
-#define BIT_GET_HI5Q_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) & \
- BIT_MASK_HI5Q_DESC_MODE_8822B)
-
-#define BIT_SHIFT_HI5Q_DESC_NUM_8822B 0
-#define BIT_MASK_HI5Q_DESC_NUM_8822B 0xfff
-#define BIT_HI5Q_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B)
-#define BIT_GET_HI5Q_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B)
-
-/* 2 REG_HI6Q_TXBD_NUM_8822B */
-#define BIT_HI6Q_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_HI6Q_DESC_MODE_8822B 12
-#define BIT_MASK_HI6Q_DESC_MODE_8822B 0x3
-#define BIT_HI6Q_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_HI6Q_DESC_MODE_8822B) \
- << BIT_SHIFT_HI6Q_DESC_MODE_8822B)
-#define BIT_GET_HI6Q_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) & \
- BIT_MASK_HI6Q_DESC_MODE_8822B)
-
-#define BIT_SHIFT_HI6Q_DESC_NUM_8822B 0
-#define BIT_MASK_HI6Q_DESC_NUM_8822B 0xfff
-#define BIT_HI6Q_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B)
-#define BIT_GET_HI6Q_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B)
-
-/* 2 REG_HI7Q_TXBD_NUM_8822B */
-#define BIT_HI7Q_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_HI7Q_DESC_MODE_8822B 12
-#define BIT_MASK_HI7Q_DESC_MODE_8822B 0x3
-#define BIT_HI7Q_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_HI7Q_DESC_MODE_8822B) \
- << BIT_SHIFT_HI7Q_DESC_MODE_8822B)
-#define BIT_GET_HI7Q_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) & \
- BIT_MASK_HI7Q_DESC_MODE_8822B)
-
-#define BIT_SHIFT_HI7Q_DESC_NUM_8822B 0
-#define BIT_MASK_HI7Q_DESC_NUM_8822B 0xfff
-#define BIT_HI7Q_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B)
-#define BIT_GET_HI7Q_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B)
-
-/* 2 REG_TSFTIMER_HCI_8822B */
-
-#define BIT_SHIFT_TSFT2_HCI_8822B 16
-#define BIT_MASK_TSFT2_HCI_8822B 0xffff
-#define BIT_TSFT2_HCI_8822B(x) \
- (((x) & BIT_MASK_TSFT2_HCI_8822B) << BIT_SHIFT_TSFT2_HCI_8822B)
-#define BIT_GET_TSFT2_HCI_8822B(x) \
- (((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B)
-
-#define BIT_SHIFT_TSFT1_HCI_8822B 0
-#define BIT_MASK_TSFT1_HCI_8822B 0xffff
-#define BIT_TSFT1_HCI_8822B(x) \
- (((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B)
-#define BIT_GET_TSFT1_HCI_8822B(x) \
- (((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B)
-
-/* 2 REG_BD_RWPTR_CLR_8822B */
-#define BIT_CLR_HI7Q_HW_IDX_8822B BIT(29)
-#define BIT_CLR_HI6Q_HW_IDX_8822B BIT(28)
-#define BIT_CLR_HI5Q_HW_IDX_8822B BIT(27)
-#define BIT_CLR_HI4Q_HW_IDX_8822B BIT(26)
-#define BIT_CLR_HI3Q_HW_IDX_8822B BIT(25)
-#define BIT_CLR_HI2Q_HW_IDX_8822B BIT(24)
-#define BIT_CLR_HI1Q_HW_IDX_8822B BIT(23)
-#define BIT_CLR_HI0Q_HW_IDX_8822B BIT(22)
-#define BIT_CLR_BKQ_HW_IDX_8822B BIT(21)
-#define BIT_CLR_BEQ_HW_IDX_8822B BIT(20)
-#define BIT_CLR_VIQ_HW_IDX_8822B BIT(19)
-#define BIT_CLR_VOQ_HW_IDX_8822B BIT(18)
-#define BIT_CLR_MGQ_HW_IDX_8822B BIT(17)
-#define BIT_CLR_RXQ_HW_IDX_8822B BIT(16)
-#define BIT_CLR_HI7Q_HOST_IDX_8822B BIT(13)
-#define BIT_CLR_HI6Q_HOST_IDX_8822B BIT(12)
-#define BIT_CLR_HI5Q_HOST_IDX_8822B BIT(11)
-#define BIT_CLR_HI4Q_HOST_IDX_8822B BIT(10)
-#define BIT_CLR_HI3Q_HOST_IDX_8822B BIT(9)
-#define BIT_CLR_HI2Q_HOST_IDX_8822B BIT(8)
-#define BIT_CLR_HI1Q_HOST_IDX_8822B BIT(7)
-#define BIT_CLR_HI0Q_HOST_IDX_8822B BIT(6)
-#define BIT_CLR_BKQ_HOST_IDX_8822B BIT(5)
-#define BIT_CLR_BEQ_HOST_IDX_8822B BIT(4)
-#define BIT_CLR_VIQ_HOST_IDX_8822B BIT(3)
-#define BIT_CLR_VOQ_HOST_IDX_8822B BIT(2)
-#define BIT_CLR_MGQ_HOST_IDX_8822B BIT(1)
-#define BIT_CLR_RXQ_HOST_IDX_8822B BIT(0)
-
-/* 2 REG_VOQ_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_VOQ_HW_IDX_8822B 16
-#define BIT_MASK_VOQ_HW_IDX_8822B 0xfff
-#define BIT_VOQ_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_VOQ_HW_IDX_8822B) << BIT_SHIFT_VOQ_HW_IDX_8822B)
-#define BIT_GET_VOQ_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B)
-
-#define BIT_SHIFT_VOQ_HOST_IDX_8822B 0
-#define BIT_MASK_VOQ_HOST_IDX_8822B 0xfff
-#define BIT_VOQ_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B)
-#define BIT_GET_VOQ_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B)
-
-/* 2 REG_VIQ_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_VIQ_HW_IDX_8822B 16
-#define BIT_MASK_VIQ_HW_IDX_8822B 0xfff
-#define BIT_VIQ_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_VIQ_HW_IDX_8822B) << BIT_SHIFT_VIQ_HW_IDX_8822B)
-#define BIT_GET_VIQ_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B)
-
-#define BIT_SHIFT_VIQ_HOST_IDX_8822B 0
-#define BIT_MASK_VIQ_HOST_IDX_8822B 0xfff
-#define BIT_VIQ_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B)
-#define BIT_GET_VIQ_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B)
-
-/* 2 REG_BEQ_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_BEQ_HW_IDX_8822B 16
-#define BIT_MASK_BEQ_HW_IDX_8822B 0xfff
-#define BIT_BEQ_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_BEQ_HW_IDX_8822B) << BIT_SHIFT_BEQ_HW_IDX_8822B)
-#define BIT_GET_BEQ_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B)
-
-#define BIT_SHIFT_BEQ_HOST_IDX_8822B 0
-#define BIT_MASK_BEQ_HOST_IDX_8822B 0xfff
-#define BIT_BEQ_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B)
-#define BIT_GET_BEQ_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B)
-
-/* 2 REG_BKQ_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_BKQ_HW_IDX_8822B 16
-#define BIT_MASK_BKQ_HW_IDX_8822B 0xfff
-#define BIT_BKQ_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_BKQ_HW_IDX_8822B) << BIT_SHIFT_BKQ_HW_IDX_8822B)
-#define BIT_GET_BKQ_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B)
-
-#define BIT_SHIFT_BKQ_HOST_IDX_8822B 0
-#define BIT_MASK_BKQ_HOST_IDX_8822B 0xfff
-#define BIT_BKQ_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B)
-#define BIT_GET_BKQ_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B)
-
-/* 2 REG_MGQ_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_MGQ_HW_IDX_8822B 16
-#define BIT_MASK_MGQ_HW_IDX_8822B 0xfff
-#define BIT_MGQ_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_MGQ_HW_IDX_8822B) << BIT_SHIFT_MGQ_HW_IDX_8822B)
-#define BIT_GET_MGQ_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B)
-
-#define BIT_SHIFT_MGQ_HOST_IDX_8822B 0
-#define BIT_MASK_MGQ_HOST_IDX_8822B 0xfff
-#define BIT_MGQ_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B)
-#define BIT_GET_MGQ_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B)
-
-/* 2 REG_RXQ_RXBD_IDX_8822B */
-
-#define BIT_SHIFT_RXQ_HW_IDX_8822B 16
-#define BIT_MASK_RXQ_HW_IDX_8822B 0xfff
-#define BIT_RXQ_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_RXQ_HW_IDX_8822B) << BIT_SHIFT_RXQ_HW_IDX_8822B)
-#define BIT_GET_RXQ_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B)
-
-#define BIT_SHIFT_RXQ_HOST_IDX_8822B 0
-#define BIT_MASK_RXQ_HOST_IDX_8822B 0xfff
-#define BIT_RXQ_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B)
-#define BIT_GET_RXQ_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B)
-
-/* 2 REG_HI0Q_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_HI0Q_HW_IDX_8822B 16
-#define BIT_MASK_HI0Q_HW_IDX_8822B 0xfff
-#define BIT_HI0Q_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_HI0Q_HW_IDX_8822B) << BIT_SHIFT_HI0Q_HW_IDX_8822B)
-#define BIT_GET_HI0Q_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B)
-
-#define BIT_SHIFT_HI0Q_HOST_IDX_8822B 0
-#define BIT_MASK_HI0Q_HOST_IDX_8822B 0xfff
-#define BIT_HI0Q_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B)
-#define BIT_GET_HI0Q_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B)
-
-/* 2 REG_HI1Q_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_HI1Q_HW_IDX_8822B 16
-#define BIT_MASK_HI1Q_HW_IDX_8822B 0xfff
-#define BIT_HI1Q_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_HI1Q_HW_IDX_8822B) << BIT_SHIFT_HI1Q_HW_IDX_8822B)
-#define BIT_GET_HI1Q_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B)
-
-#define BIT_SHIFT_HI1Q_HOST_IDX_8822B 0
-#define BIT_MASK_HI1Q_HOST_IDX_8822B 0xfff
-#define BIT_HI1Q_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B)
-#define BIT_GET_HI1Q_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B)
-
-/* 2 REG_HI2Q_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_HI2Q_HW_IDX_8822B 16
-#define BIT_MASK_HI2Q_HW_IDX_8822B 0xfff
-#define BIT_HI2Q_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_HI2Q_HW_IDX_8822B) << BIT_SHIFT_HI2Q_HW_IDX_8822B)
-#define BIT_GET_HI2Q_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B)
-
-#define BIT_SHIFT_HI2Q_HOST_IDX_8822B 0
-#define BIT_MASK_HI2Q_HOST_IDX_8822B 0xfff
-#define BIT_HI2Q_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B)
-#define BIT_GET_HI2Q_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B)
-
-/* 2 REG_HI3Q_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_HI3Q_HW_IDX_8822B 16
-#define BIT_MASK_HI3Q_HW_IDX_8822B 0xfff
-#define BIT_HI3Q_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_HI3Q_HW_IDX_8822B) << BIT_SHIFT_HI3Q_HW_IDX_8822B)
-#define BIT_GET_HI3Q_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B)
-
-#define BIT_SHIFT_HI3Q_HOST_IDX_8822B 0
-#define BIT_MASK_HI3Q_HOST_IDX_8822B 0xfff
-#define BIT_HI3Q_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B)
-#define BIT_GET_HI3Q_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B)
-
-/* 2 REG_HI4Q_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_HI4Q_HW_IDX_8822B 16
-#define BIT_MASK_HI4Q_HW_IDX_8822B 0xfff
-#define BIT_HI4Q_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_HI4Q_HW_IDX_8822B) << BIT_SHIFT_HI4Q_HW_IDX_8822B)
-#define BIT_GET_HI4Q_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B)
-
-#define BIT_SHIFT_HI4Q_HOST_IDX_8822B 0
-#define BIT_MASK_HI4Q_HOST_IDX_8822B 0xfff
-#define BIT_HI4Q_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B)
-#define BIT_GET_HI4Q_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B)
-
-/* 2 REG_HI5Q_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_HI5Q_HW_IDX_8822B 16
-#define BIT_MASK_HI5Q_HW_IDX_8822B 0xfff
-#define BIT_HI5Q_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_HI5Q_HW_IDX_8822B) << BIT_SHIFT_HI5Q_HW_IDX_8822B)
-#define BIT_GET_HI5Q_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B)
-
-#define BIT_SHIFT_HI5Q_HOST_IDX_8822B 0
-#define BIT_MASK_HI5Q_HOST_IDX_8822B 0xfff
-#define BIT_HI5Q_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B)
-#define BIT_GET_HI5Q_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B)
-
-/* 2 REG_HI6Q_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_HI6Q_HW_IDX_8822B 16
-#define BIT_MASK_HI6Q_HW_IDX_8822B 0xfff
-#define BIT_HI6Q_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_HI6Q_HW_IDX_8822B) << BIT_SHIFT_HI6Q_HW_IDX_8822B)
-#define BIT_GET_HI6Q_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B)
-
-#define BIT_SHIFT_HI6Q_HOST_IDX_8822B 0
-#define BIT_MASK_HI6Q_HOST_IDX_8822B 0xfff
-#define BIT_HI6Q_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B)
-#define BIT_GET_HI6Q_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B)
-
-/* 2 REG_HI7Q_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_HI7Q_HW_IDX_8822B 16
-#define BIT_MASK_HI7Q_HW_IDX_8822B 0xfff
-#define BIT_HI7Q_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_HI7Q_HW_IDX_8822B) << BIT_SHIFT_HI7Q_HW_IDX_8822B)
-#define BIT_GET_HI7Q_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B)
-
-#define BIT_SHIFT_HI7Q_HOST_IDX_8822B 0
-#define BIT_MASK_HI7Q_HOST_IDX_8822B 0xfff
-#define BIT_HI7Q_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B)
-#define BIT_GET_HI7Q_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B)
-
-/* 2 REG_DBG_SEL_V1_8822B */
-
-#define BIT_SHIFT_DBG_SEL_8822B 0
-#define BIT_MASK_DBG_SEL_8822B 0xff
-#define BIT_DBG_SEL_8822B(x) \
- (((x) & BIT_MASK_DBG_SEL_8822B) << BIT_SHIFT_DBG_SEL_8822B)
-#define BIT_GET_DBG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B)
-
-/* 2 REG_PCIE_HRPWM1_V1_8822B */
-
-#define BIT_SHIFT_PCIE_HRPWM_8822B 0
-#define BIT_MASK_PCIE_HRPWM_8822B 0xff
-#define BIT_PCIE_HRPWM_8822B(x) \
- (((x) & BIT_MASK_PCIE_HRPWM_8822B) << BIT_SHIFT_PCIE_HRPWM_8822B)
-#define BIT_GET_PCIE_HRPWM_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B)
-
-/* 2 REG_PCIE_HCPWM1_V1_8822B */
-
-#define BIT_SHIFT_PCIE_HCPWM_8822B 0
-#define BIT_MASK_PCIE_HCPWM_8822B 0xff
-#define BIT_PCIE_HCPWM_8822B(x) \
- (((x) & BIT_MASK_PCIE_HCPWM_8822B) << BIT_SHIFT_PCIE_HCPWM_8822B)
-#define BIT_GET_PCIE_HCPWM_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B)
-
-/* 2 REG_PCIE_CTRL2_8822B */
-#define BIT_DIS_TXDMA_PRE_8822B BIT(7)
-#define BIT_DIS_RXDMA_PRE_8822B BIT(6)
-
-#define BIT_SHIFT_HPS_CLKR_PCIE_8822B 4
-#define BIT_MASK_HPS_CLKR_PCIE_8822B 0x3
-#define BIT_HPS_CLKR_PCIE_8822B(x) \
- (((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B)
-#define BIT_GET_HPS_CLKR_PCIE_8822B(x) \
- (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B)
-
-#define BIT_PCIE_INT_8822B BIT(3)
-#define BIT_TXFLAG_EXIT_L1_EN_8822B BIT(2)
-#define BIT_EN_RXDMA_ALIGN_8822B BIT(1)
-#define BIT_EN_TXDMA_ALIGN_8822B BIT(0)
-
-/* 2 REG_PCIE_HRPWM2_V1_8822B */
-
-#define BIT_SHIFT_PCIE_HRPWM2_8822B 0
-#define BIT_MASK_PCIE_HRPWM2_8822B 0xffff
-#define BIT_PCIE_HRPWM2_8822B(x) \
- (((x) & BIT_MASK_PCIE_HRPWM2_8822B) << BIT_SHIFT_PCIE_HRPWM2_8822B)
-#define BIT_GET_PCIE_HRPWM2_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B)
-
-/* 2 REG_PCIE_HCPWM2_V1_8822B */
-
-#define BIT_SHIFT_PCIE_HCPWM2_8822B 0
-#define BIT_MASK_PCIE_HCPWM2_8822B 0xffff
-#define BIT_PCIE_HCPWM2_8822B(x) \
- (((x) & BIT_MASK_PCIE_HCPWM2_8822B) << BIT_SHIFT_PCIE_HCPWM2_8822B)
-#define BIT_GET_PCIE_HCPWM2_8822B(x) \
- (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B)
-
-/* 2 REG_PCIE_H2C_MSG_V1_8822B */
-
-#define BIT_SHIFT_DRV2FW_INFO_8822B 0
-#define BIT_MASK_DRV2FW_INFO_8822B 0xffffffffL
-#define BIT_DRV2FW_INFO_8822B(x) \
- (((x) & BIT_MASK_DRV2FW_INFO_8822B) << BIT_SHIFT_DRV2FW_INFO_8822B)
-#define BIT_GET_DRV2FW_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B)
-
-/* 2 REG_PCIE_C2H_MSG_V1_8822B */
-
-#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B 0
-#define BIT_MASK_HCI_PCIE_C2H_MSG_8822B 0xffffffffL
-#define BIT_HCI_PCIE_C2H_MSG_8822B(x) \
- (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) \
- << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B)
-#define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x) \
- (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) & \
- BIT_MASK_HCI_PCIE_C2H_MSG_8822B)
-
-/* 2 REG_DBI_WDATA_V1_8822B */
-
-#define BIT_SHIFT_DBI_WDATA_8822B 0
-#define BIT_MASK_DBI_WDATA_8822B 0xffffffffL
-#define BIT_DBI_WDATA_8822B(x) \
- (((x) & BIT_MASK_DBI_WDATA_8822B) << BIT_SHIFT_DBI_WDATA_8822B)
-#define BIT_GET_DBI_WDATA_8822B(x) \
- (((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B)
-
-/* 2 REG_DBI_RDATA_V1_8822B */
-
-#define BIT_SHIFT_DBI_RDATA_8822B 0
-#define BIT_MASK_DBI_RDATA_8822B 0xffffffffL
-#define BIT_DBI_RDATA_8822B(x) \
- (((x) & BIT_MASK_DBI_RDATA_8822B) << BIT_SHIFT_DBI_RDATA_8822B)
-#define BIT_GET_DBI_RDATA_8822B(x) \
- (((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B)
-
-/* 2 REG_DBI_FLAG_V1_8822B */
-#define BIT_EN_STUCK_DBG_8822B BIT(26)
-#define BIT_RX_STUCK_8822B BIT(25)
-#define BIT_TX_STUCK_8822B BIT(24)
-#define BIT_DBI_RFLAG_8822B BIT(17)
-#define BIT_DBI_WFLAG_8822B BIT(16)
-
-#define BIT_SHIFT_DBI_WREN_8822B 12
-#define BIT_MASK_DBI_WREN_8822B 0xf
-#define BIT_DBI_WREN_8822B(x) \
- (((x) & BIT_MASK_DBI_WREN_8822B) << BIT_SHIFT_DBI_WREN_8822B)
-#define BIT_GET_DBI_WREN_8822B(x) \
- (((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B)
-
-#define BIT_SHIFT_DBI_ADDR_8822B 0
-#define BIT_MASK_DBI_ADDR_8822B 0xfff
-#define BIT_DBI_ADDR_8822B(x) \
- (((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B)
-#define BIT_GET_DBI_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B)
-
-/* 2 REG_MDIO_V1_8822B */
-
-#define BIT_SHIFT_MDIO_RDATA_8822B 16
-#define BIT_MASK_MDIO_RDATA_8822B 0xffff
-#define BIT_MDIO_RDATA_8822B(x) \
- (((x) & BIT_MASK_MDIO_RDATA_8822B) << BIT_SHIFT_MDIO_RDATA_8822B)
-#define BIT_GET_MDIO_RDATA_8822B(x) \
- (((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B)
-
-#define BIT_SHIFT_MDIO_WDATA_8822B 0
-#define BIT_MASK_MDIO_WDATA_8822B 0xffff
-#define BIT_MDIO_WDATA_8822B(x) \
- (((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B)
-#define BIT_GET_MDIO_WDATA_8822B(x) \
- (((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B)
-
-/* 2 REG_PCIE_MIX_CFG_8822B */
-
-#define BIT_SHIFT_MDIO_PHY_ADDR_8822B 24
-#define BIT_MASK_MDIO_PHY_ADDR_8822B 0x1f
-#define BIT_MDIO_PHY_ADDR_8822B(x) \
- (((x) & BIT_MASK_MDIO_PHY_ADDR_8822B) << BIT_SHIFT_MDIO_PHY_ADDR_8822B)
-#define BIT_GET_MDIO_PHY_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B)
-
-#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B 10
-#define BIT_MASK_WATCH_DOG_RECORD_V1_8822B 0x3fff
-#define BIT_WATCH_DOG_RECORD_V1_8822B(x) \
- (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) \
- << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B)
-#define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x) \
- (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) & \
- BIT_MASK_WATCH_DOG_RECORD_V1_8822B)
-
-#define BIT_R_IO_TIMEOUT_FLAG_V1_8822B BIT(9)
-#define BIT_EN_WATCH_DOG_8822B BIT(8)
-#define BIT_ECRC_EN_V1_8822B BIT(7)
-#define BIT_MDIO_RFLAG_V1_8822B BIT(6)
-#define BIT_MDIO_WFLAG_V1_8822B BIT(5)
-
-#define BIT_SHIFT_MDIO_REG_ADDR_V1_8822B 0
-#define BIT_MASK_MDIO_REG_ADDR_V1_8822B 0x1f
-#define BIT_MDIO_REG_ADDR_V1_8822B(x) \
- (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) \
- << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B)
-#define BIT_GET_MDIO_REG_ADDR_V1_8822B(x) \
- (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) & \
- BIT_MASK_MDIO_REG_ADDR_V1_8822B)
-
-/* 2 REG_HCI_MIX_CFG_8822B */
-#define BIT_HOST_GEN2_SUPPORT_8822B BIT(20)
-
-#define BIT_SHIFT_TXDMA_ERR_FLAG_8822B 16
-#define BIT_MASK_TXDMA_ERR_FLAG_8822B 0xf
-#define BIT_TXDMA_ERR_FLAG_8822B(x) \
- (((x) & BIT_MASK_TXDMA_ERR_FLAG_8822B) \
- << BIT_SHIFT_TXDMA_ERR_FLAG_8822B)
-#define BIT_GET_TXDMA_ERR_FLAG_8822B(x) \
- (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) & \
- BIT_MASK_TXDMA_ERR_FLAG_8822B)
-
-#define BIT_SHIFT_EARLY_MODE_SEL_8822B 12
-#define BIT_MASK_EARLY_MODE_SEL_8822B 0xf
-#define BIT_EARLY_MODE_SEL_8822B(x) \
- (((x) & BIT_MASK_EARLY_MODE_SEL_8822B) \
- << BIT_SHIFT_EARLY_MODE_SEL_8822B)
-#define BIT_GET_EARLY_MODE_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) & \
- BIT_MASK_EARLY_MODE_SEL_8822B)
-
-#define BIT_EPHY_RX50_EN_8822B BIT(11)
-
-#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B 8
-#define BIT_MASK_MSI_TIMEOUT_ID_V1_8822B 0x7
-#define BIT_MSI_TIMEOUT_ID_V1_8822B(x) \
- (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) \
- << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B)
-#define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x) \
- (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) & \
- BIT_MASK_MSI_TIMEOUT_ID_V1_8822B)
-
-#define BIT_RADDR_RD_8822B BIT(7)
-#define BIT_EN_MUL_TAG_8822B BIT(6)
-#define BIT_EN_EARLY_MODE_8822B BIT(5)
-#define BIT_L0S_LINK_OFF_8822B BIT(4)
-#define BIT_ACT_LINK_OFF_8822B BIT(3)
-#define BIT_EN_SLOW_MAC_TX_8822B BIT(2)
-#define BIT_EN_SLOW_MAC_RX_8822B BIT(1)
-
-/* 2 REG_STC_INT_CS_8822B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */
-#define BIT_STC_INT_EN_8822B BIT(31)
-
-#define BIT_SHIFT_STC_INT_FLAG_8822B 16
-#define BIT_MASK_STC_INT_FLAG_8822B 0xff
-#define BIT_STC_INT_FLAG_8822B(x) \
- (((x) & BIT_MASK_STC_INT_FLAG_8822B) << BIT_SHIFT_STC_INT_FLAG_8822B)
-#define BIT_GET_STC_INT_FLAG_8822B(x) \
- (((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B)
-
-#define BIT_SHIFT_STC_INT_IDX_8822B 8
-#define BIT_MASK_STC_INT_IDX_8822B 0x7
-#define BIT_STC_INT_IDX_8822B(x) \
- (((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B)
-#define BIT_GET_STC_INT_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B)
-
-#define BIT_SHIFT_STC_INT_REALTIME_CS_8822B 0
-#define BIT_MASK_STC_INT_REALTIME_CS_8822B 0x3f
-#define BIT_STC_INT_REALTIME_CS_8822B(x) \
- (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B) \
- << BIT_SHIFT_STC_INT_REALTIME_CS_8822B)
-#define BIT_GET_STC_INT_REALTIME_CS_8822B(x) \
- (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) & \
- BIT_MASK_STC_INT_REALTIME_CS_8822B)
-
-/* 2 REG_ST_INT_CFG_8822B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */
-#define BIT_STC_INT_GRP_EN_8822B BIT(31)
-
-#define BIT_SHIFT_STC_INT_EXPECT_LS_8822B 8
-#define BIT_MASK_STC_INT_EXPECT_LS_8822B 0x3f
-#define BIT_STC_INT_EXPECT_LS_8822B(x) \
- (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822B) \
- << BIT_SHIFT_STC_INT_EXPECT_LS_8822B)
-#define BIT_GET_STC_INT_EXPECT_LS_8822B(x) \
- (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) & \
- BIT_MASK_STC_INT_EXPECT_LS_8822B)
-
-#define BIT_SHIFT_STC_INT_EXPECT_CS_8822B 0
-#define BIT_MASK_STC_INT_EXPECT_CS_8822B 0x3f
-#define BIT_STC_INT_EXPECT_CS_8822B(x) \
- (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B) \
- << BIT_SHIFT_STC_INT_EXPECT_CS_8822B)
-#define BIT_GET_STC_INT_EXPECT_CS_8822B(x) \
- (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) & \
- BIT_MASK_STC_INT_EXPECT_CS_8822B)
-
-/* 2 REG_CMU_DLY_CTRL_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */
-#define BIT_CMU_DLY_EN_8822B BIT(31)
-#define BIT_CMU_DLY_MODE_8822B BIT(30)
-
-#define BIT_SHIFT_CMU_DLY_PRE_DIV_8822B 0
-#define BIT_MASK_CMU_DLY_PRE_DIV_8822B 0xff
-#define BIT_CMU_DLY_PRE_DIV_8822B(x) \
- (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) \
- << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B)
-#define BIT_GET_CMU_DLY_PRE_DIV_8822B(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) & \
- BIT_MASK_CMU_DLY_PRE_DIV_8822B)
-
-/* 2 REG_CMU_DLY_CFG_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */
-
-#define BIT_SHIFT_CMU_DLY_LTR_A2I_8822B 24
-#define BIT_MASK_CMU_DLY_LTR_A2I_8822B 0xff
-#define BIT_CMU_DLY_LTR_A2I_8822B(x) \
- (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) \
- << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B)
-#define BIT_GET_CMU_DLY_LTR_A2I_8822B(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) & \
- BIT_MASK_CMU_DLY_LTR_A2I_8822B)
-
-#define BIT_SHIFT_CMU_DLY_LTR_I2A_8822B 16
-#define BIT_MASK_CMU_DLY_LTR_I2A_8822B 0xff
-#define BIT_CMU_DLY_LTR_I2A_8822B(x) \
- (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) \
- << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B)
-#define BIT_GET_CMU_DLY_LTR_I2A_8822B(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) & \
- BIT_MASK_CMU_DLY_LTR_I2A_8822B)
-
-#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B 8
-#define BIT_MASK_CMU_DLY_LTR_IDLE_8822B 0xff
-#define BIT_CMU_DLY_LTR_IDLE_8822B(x) \
- (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) \
- << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B)
-#define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) & \
- BIT_MASK_CMU_DLY_LTR_IDLE_8822B)
-
-#define BIT_SHIFT_CMU_DLY_LTR_ACT_8822B 0
-#define BIT_MASK_CMU_DLY_LTR_ACT_8822B 0xff
-#define BIT_CMU_DLY_LTR_ACT_8822B(x) \
- (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) \
- << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B)
-#define BIT_GET_CMU_DLY_LTR_ACT_8822B(x) \
- (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) & \
- BIT_MASK_CMU_DLY_LTR_ACT_8822B)
-
-/* 2 REG_H2CQ_TXBD_DESA_8822B */
-
-#define BIT_SHIFT_H2CQ_TXBD_DESA_8822B 0
-#define BIT_MASK_H2CQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_H2CQ_TXBD_DESA_8822B(x) \
- (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822B) \
- << BIT_SHIFT_H2CQ_TXBD_DESA_8822B)
-#define BIT_GET_H2CQ_TXBD_DESA_8822B(x) \
- (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) & \
- BIT_MASK_H2CQ_TXBD_DESA_8822B)
-
-/* 2 REG_H2CQ_TXBD_NUM_8822B */
-#define BIT_PCIE_H2CQ_FLAG_8822B BIT(14)
-
-#define BIT_SHIFT_H2CQ_DESC_MODE_8822B 12
-#define BIT_MASK_H2CQ_DESC_MODE_8822B 0x3
-#define BIT_H2CQ_DESC_MODE_8822B(x) \
- (((x) & BIT_MASK_H2CQ_DESC_MODE_8822B) \
- << BIT_SHIFT_H2CQ_DESC_MODE_8822B)
-#define BIT_GET_H2CQ_DESC_MODE_8822B(x) \
- (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) & \
- BIT_MASK_H2CQ_DESC_MODE_8822B)
-
-#define BIT_SHIFT_H2CQ_DESC_NUM_8822B 0
-#define BIT_MASK_H2CQ_DESC_NUM_8822B 0xfff
-#define BIT_H2CQ_DESC_NUM_8822B(x) \
- (((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B)
-#define BIT_GET_H2CQ_DESC_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B)
-
-/* 2 REG_H2CQ_TXBD_IDX_8822B */
-
-#define BIT_SHIFT_H2CQ_HW_IDX_8822B 16
-#define BIT_MASK_H2CQ_HW_IDX_8822B 0xfff
-#define BIT_H2CQ_HW_IDX_8822B(x) \
- (((x) & BIT_MASK_H2CQ_HW_IDX_8822B) << BIT_SHIFT_H2CQ_HW_IDX_8822B)
-#define BIT_GET_H2CQ_HW_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B)
-
-#define BIT_SHIFT_H2CQ_HOST_IDX_8822B 0
-#define BIT_MASK_H2CQ_HOST_IDX_8822B 0xfff
-#define BIT_H2CQ_HOST_IDX_8822B(x) \
- (((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B)
-#define BIT_GET_H2CQ_HOST_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B)
-
-/* 2 REG_H2CQ_CSR_8822B[31:0] (H2CQ CONTROL AND STATUS) */
-#define BIT_H2CQ_FULL_8822B BIT(31)
-#define BIT_CLR_H2CQ_HOST_IDX_8822B BIT(16)
-#define BIT_CLR_H2CQ_HW_IDX_8822B BIT(8)
-
-/* 2 REG_CHANGE_PCIE_SPEED_8822B */
-#define BIT_CHANGE_PCIE_SPEED_8822B BIT(18)
-
-#define BIT_SHIFT_GEN1_GEN2_8822B 16
-#define BIT_MASK_GEN1_GEN2_8822B 0x3
-#define BIT_GEN1_GEN2_8822B(x) \
- (((x) & BIT_MASK_GEN1_GEN2_8822B) << BIT_SHIFT_GEN1_GEN2_8822B)
-#define BIT_GET_GEN1_GEN2_8822B(x) \
- (((x) >> BIT_SHIFT_GEN1_GEN2_8822B) & BIT_MASK_GEN1_GEN2_8822B)
-
-#define BIT_SHIFT_AUTO_HANG_RELEASE_8822B 0
-#define BIT_MASK_AUTO_HANG_RELEASE_8822B 0x7
-#define BIT_AUTO_HANG_RELEASE_8822B(x) \
- (((x) & BIT_MASK_AUTO_HANG_RELEASE_8822B) \
- << BIT_SHIFT_AUTO_HANG_RELEASE_8822B)
-#define BIT_GET_AUTO_HANG_RELEASE_8822B(x) \
- (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE_8822B) & \
- BIT_MASK_AUTO_HANG_RELEASE_8822B)
-
-/* 2 REG_OLD_DEHANG_8822B */
-#define BIT_OLD_DEHANG_8822B BIT(1)
-
-/* 2 REG_Q0_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_Q0_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_Q0_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q0_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q0_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) & \
- BIT_MASK_QUEUEMACID_Q0_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_Q0_V1_8822B 23
-#define BIT_MASK_QUEUEAC_Q0_V1_8822B 0x3
-#define BIT_QUEUEAC_Q0_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B)
-#define BIT_GET_QUEUEAC_Q0_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B)
-
-#define BIT_TIDEMPTY_Q0_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_Q0_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_Q0_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q0_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q0_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) & \
- BIT_MASK_TAIL_PKT_Q0_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_Q0_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_Q0_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q0_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q0_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) & \
- BIT_MASK_HEAD_PKT_Q0_V1_8822B)
-
-/* 2 REG_Q1_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_Q1_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_Q1_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q1_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) & \
- BIT_MASK_QUEUEMACID_Q1_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_Q1_V1_8822B 23
-#define BIT_MASK_QUEUEAC_Q1_V1_8822B 0x3
-#define BIT_QUEUEAC_Q1_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B)
-#define BIT_GET_QUEUEAC_Q1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B)
-
-#define BIT_TIDEMPTY_Q1_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_Q1_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_Q1_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q1_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q1_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) & \
- BIT_MASK_TAIL_PKT_Q1_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_Q1_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_Q1_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q1_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) & \
- BIT_MASK_HEAD_PKT_Q1_V1_8822B)
-
-/* 2 REG_Q2_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_Q2_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_Q2_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q2_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q2_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) & \
- BIT_MASK_QUEUEMACID_Q2_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_Q2_V1_8822B 23
-#define BIT_MASK_QUEUEAC_Q2_V1_8822B 0x3
-#define BIT_QUEUEAC_Q2_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B)
-#define BIT_GET_QUEUEAC_Q2_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B)
-
-#define BIT_TIDEMPTY_Q2_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_Q2_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_Q2_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q2_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q2_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) & \
- BIT_MASK_TAIL_PKT_Q2_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_Q2_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_Q2_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q2_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q2_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) & \
- BIT_MASK_HEAD_PKT_Q2_V1_8822B)
-
-/* 2 REG_Q3_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_Q3_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_Q3_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q3_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q3_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) & \
- BIT_MASK_QUEUEMACID_Q3_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_Q3_V1_8822B 23
-#define BIT_MASK_QUEUEAC_Q3_V1_8822B 0x3
-#define BIT_QUEUEAC_Q3_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B)
-#define BIT_GET_QUEUEAC_Q3_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B)
-
-#define BIT_TIDEMPTY_Q3_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_Q3_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_Q3_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q3_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q3_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) & \
- BIT_MASK_TAIL_PKT_Q3_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_Q3_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_Q3_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q3_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q3_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) & \
- BIT_MASK_HEAD_PKT_Q3_V1_8822B)
-
-/* 2 REG_MGQ_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_MGQ_V1_8822B 0x7f
-#define BIT_QUEUEMACID_MGQ_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B)
-#define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) & \
- BIT_MASK_QUEUEMACID_MGQ_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_MGQ_V1_8822B 23
-#define BIT_MASK_QUEUEAC_MGQ_V1_8822B 0x3
-#define BIT_QUEUEAC_MGQ_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) \
- << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B)
-#define BIT_GET_QUEUEAC_MGQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) & \
- BIT_MASK_QUEUEAC_MGQ_V1_8822B)
-
-#define BIT_TIDEMPTY_MGQ_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_MGQ_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_MGQ_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B)
-#define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) & \
- BIT_MASK_TAIL_PKT_MGQ_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_MGQ_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_MGQ_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B)
-#define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) & \
- BIT_MASK_HEAD_PKT_MGQ_V1_8822B)
-
-/* 2 REG_HIQ_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_HIQ_V1_8822B 0x7f
-#define BIT_QUEUEMACID_HIQ_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B)
-#define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) & \
- BIT_MASK_QUEUEMACID_HIQ_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_HIQ_V1_8822B 23
-#define BIT_MASK_QUEUEAC_HIQ_V1_8822B 0x3
-#define BIT_QUEUEAC_HIQ_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) \
- << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B)
-#define BIT_GET_QUEUEAC_HIQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) & \
- BIT_MASK_QUEUEAC_HIQ_V1_8822B)
-
-#define BIT_TIDEMPTY_HIQ_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_HIQ_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_HIQ_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B)
-#define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) & \
- BIT_MASK_TAIL_PKT_HIQ_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_HIQ_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_HIQ_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B)
-#define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) & \
- BIT_MASK_HEAD_PKT_HIQ_V1_8822B)
-
-/* 2 REG_BCNQ_INFO_8822B */
-
-#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B 0
-#define BIT_MASK_BCNQ_HEAD_PG_V1_8822B 0xfff
-#define BIT_BCNQ_HEAD_PG_V1_8822B(x) \
- (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) \
- << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B)
-#define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) & \
- BIT_MASK_BCNQ_HEAD_PG_V1_8822B)
-
-/* 2 REG_TXPKT_EMPTY_8822B */
-#define BIT_BCNQ_EMPTY_8822B BIT(11)
-#define BIT_HQQ_EMPTY_8822B BIT(10)
-#define BIT_MQQ_EMPTY_8822B BIT(9)
-#define BIT_MGQ_CPU_EMPTY_8822B BIT(8)
-#define BIT_AC7Q_EMPTY_8822B BIT(7)
-#define BIT_AC6Q_EMPTY_8822B BIT(6)
-#define BIT_AC5Q_EMPTY_8822B BIT(5)
-#define BIT_AC4Q_EMPTY_8822B BIT(4)
-#define BIT_AC3Q_EMPTY_8822B BIT(3)
-#define BIT_AC2Q_EMPTY_8822B BIT(2)
-#define BIT_AC1Q_EMPTY_8822B BIT(1)
-#define BIT_AC0Q_EMPTY_8822B BIT(0)
-
-/* 2 REG_CPU_MGQ_INFO_8822B */
-#define BIT_BCN1_POLL_8822B BIT(30)
-#define BIT_CPUMGT_POLL_8822B BIT(29)
-#define BIT_BCN_POLL_8822B BIT(28)
-#define BIT_CPUMGQ_FW_NUM_V1_8822B BIT(12)
-
-#define BIT_SHIFT_FW_FREE_TAIL_V1_8822B 0
-#define BIT_MASK_FW_FREE_TAIL_V1_8822B 0xfff
-#define BIT_FW_FREE_TAIL_V1_8822B(x) \
- (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822B) \
- << BIT_SHIFT_FW_FREE_TAIL_V1_8822B)
-#define BIT_GET_FW_FREE_TAIL_V1_8822B(x) \
- (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) & \
- BIT_MASK_FW_FREE_TAIL_V1_8822B)
-
-/* 2 REG_FWHW_TXQ_CTRL_8822B */
-#define BIT_RTS_LIMIT_IN_OFDM_8822B BIT(23)
-#define BIT_EN_BCNQ_DL_8822B BIT(22)
-#define BIT_EN_RD_RESP_NAV_BK_8822B BIT(21)
-#define BIT_EN_WR_FREE_TAIL_8822B BIT(20)
-
-#define BIT_SHIFT_EN_QUEUE_RPT_8822B 8
-#define BIT_MASK_EN_QUEUE_RPT_8822B 0xff
-#define BIT_EN_QUEUE_RPT_8822B(x) \
- (((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B)
-#define BIT_GET_EN_QUEUE_RPT_8822B(x) \
- (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B)
-
-#define BIT_EN_RTY_BK_8822B BIT(7)
-#define BIT_EN_USE_INI_RAT_8822B BIT(6)
-#define BIT_EN_RTS_NAV_BK_8822B BIT(5)
-#define BIT_DIS_SSN_CHECK_8822B BIT(4)
-#define BIT_MACID_MATCH_RTS_8822B BIT(3)
-#define BIT_EN_BCN_TRXRPT_V1_8822B BIT(2)
-#define BIT_EN_FTMACKRPT_8822B BIT(1)
-#define BIT_EN_FTMRPT_8822B BIT(0)
-
-/* 2 REG_DATAFB_SEL_8822B */
-#define BIT__R_EN_RTY_BK_COD_8822B BIT(2)
-
-#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B 0
-#define BIT_MASK__R_DATA_FALLBACK_SEL_8822B 0x3
-#define BIT__R_DATA_FALLBACK_SEL_8822B(x) \
- (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) \
- << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B)
-#define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x) \
- (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) & \
- BIT_MASK__R_DATA_FALLBACK_SEL_8822B)
-
-/* 2 REG_BCNQ_BDNY_V1_8822B */
-
-#define BIT_SHIFT_BCNQ_PGBNDY_V1_8822B 0
-#define BIT_MASK_BCNQ_PGBNDY_V1_8822B 0xfff
-#define BIT_BCNQ_PGBNDY_V1_8822B(x) \
- (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) \
- << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B)
-#define BIT_GET_BCNQ_PGBNDY_V1_8822B(x) \
- (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) & \
- BIT_MASK_BCNQ_PGBNDY_V1_8822B)
-
-/* 2 REG_LIFETIME_EN_8822B */
-#define BIT_BT_INT_CPU_8822B BIT(7)
-#define BIT_BT_INT_PTA_8822B BIT(6)
-#define BIT_EN_CTRL_RTYBIT_8822B BIT(4)
-#define BIT_LIFETIME_BK_EN_8822B BIT(3)
-#define BIT_LIFETIME_BE_EN_8822B BIT(2)
-#define BIT_LIFETIME_VI_EN_8822B BIT(1)
-#define BIT_LIFETIME_VO_EN_8822B BIT(0)
-
-/* 2 REG_SPEC_SIFS_8822B */
-
-#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B 8
-#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B 0xff
-#define BIT_SPEC_SIFS_OFDM_PTCL_8822B(x) \
- (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) \
- << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B)
-#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x) \
- (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) & \
- BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B)
-
-#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B 0
-#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B 0xff
-#define BIT_SPEC_SIFS_CCK_PTCL_8822B(x) \
- (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) \
- << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B)
-#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x) \
- (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) & \
- BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B)
-
-/* 2 REG_RETRY_LIMIT_8822B */
-
-#define BIT_SHIFT_SRL_8822B 8
-#define BIT_MASK_SRL_8822B 0x3f
-#define BIT_SRL_8822B(x) (((x) & BIT_MASK_SRL_8822B) << BIT_SHIFT_SRL_8822B)
-#define BIT_GET_SRL_8822B(x) (((x) >> BIT_SHIFT_SRL_8822B) & BIT_MASK_SRL_8822B)
-
-#define BIT_SHIFT_LRL_8822B 0
-#define BIT_MASK_LRL_8822B 0x3f
-#define BIT_LRL_8822B(x) (((x) & BIT_MASK_LRL_8822B) << BIT_SHIFT_LRL_8822B)
-#define BIT_GET_LRL_8822B(x) (((x) >> BIT_SHIFT_LRL_8822B) & BIT_MASK_LRL_8822B)
-
-/* 2 REG_TXBF_CTRL_8822B */
-#define BIT_R_ENABLE_NDPA_8822B BIT(31)
-#define BIT_USE_NDPA_PARAMETER_8822B BIT(30)
-#define BIT_R_PROP_TXBF_8822B BIT(29)
-#define BIT_R_EN_NDPA_INT_8822B BIT(28)
-#define BIT_R_TXBF1_80M_8822B BIT(27)
-#define BIT_R_TXBF1_40M_8822B BIT(26)
-#define BIT_R_TXBF1_20M_8822B BIT(25)
-
-#define BIT_SHIFT_R_TXBF1_AID_8822B 16
-#define BIT_MASK_R_TXBF1_AID_8822B 0x1ff
-#define BIT_R_TXBF1_AID_8822B(x) \
- (((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B)
-#define BIT_GET_R_TXBF1_AID_8822B(x) \
- (((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B)
-
-#define BIT_DIS_NDP_BFEN_8822B BIT(15)
-#define BIT_R_TXBCN_NOBLOCK_NDP_8822B BIT(14)
-#define BIT_R_TXBF0_80M_8822B BIT(11)
-#define BIT_R_TXBF0_40M_8822B BIT(10)
-#define BIT_R_TXBF0_20M_8822B BIT(9)
-
-#define BIT_SHIFT_R_TXBF0_AID_8822B 0
-#define BIT_MASK_R_TXBF0_AID_8822B 0x1ff
-#define BIT_R_TXBF0_AID_8822B(x) \
- (((x) & BIT_MASK_R_TXBF0_AID_8822B) << BIT_SHIFT_R_TXBF0_AID_8822B)
-#define BIT_GET_R_TXBF0_AID_8822B(x) \
- (((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B)
-
-/* 2 REG_DARFRC_8822B */
-
-#define BIT_SHIFT_DARF_RC8_8822B (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC8_8822B 0x1f
-#define BIT_DARF_RC8_8822B(x) \
- (((x) & BIT_MASK_DARF_RC8_8822B) << BIT_SHIFT_DARF_RC8_8822B)
-#define BIT_GET_DARF_RC8_8822B(x) \
- (((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B)
-
-#define BIT_SHIFT_DARF_RC7_8822B (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC7_8822B 0x1f
-#define BIT_DARF_RC7_8822B(x) \
- (((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B)
-#define BIT_GET_DARF_RC7_8822B(x) \
- (((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B)
-
-#define BIT_SHIFT_DARF_RC6_8822B (40 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC6_8822B 0x1f
-#define BIT_DARF_RC6_8822B(x) \
- (((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B)
-#define BIT_GET_DARF_RC6_8822B(x) \
- (((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B)
-
-#define BIT_SHIFT_DARF_RC5_8822B (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC5_8822B 0x1f
-#define BIT_DARF_RC5_8822B(x) \
- (((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B)
-#define BIT_GET_DARF_RC5_8822B(x) \
- (((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B)
-
-#define BIT_SHIFT_DARF_RC4_8822B 24
-#define BIT_MASK_DARF_RC4_8822B 0x1f
-#define BIT_DARF_RC4_8822B(x) \
- (((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B)
-#define BIT_GET_DARF_RC4_8822B(x) \
- (((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B)
-
-#define BIT_SHIFT_DARF_RC3_8822B 16
-#define BIT_MASK_DARF_RC3_8822B 0x1f
-#define BIT_DARF_RC3_8822B(x) \
- (((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B)
-#define BIT_GET_DARF_RC3_8822B(x) \
- (((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B)
-
-#define BIT_SHIFT_DARF_RC2_8822B 8
-#define BIT_MASK_DARF_RC2_8822B 0x1f
-#define BIT_DARF_RC2_8822B(x) \
- (((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B)
-#define BIT_GET_DARF_RC2_8822B(x) \
- (((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B)
-
-#define BIT_SHIFT_DARF_RC1_8822B 0
-#define BIT_MASK_DARF_RC1_8822B 0x1f
-#define BIT_DARF_RC1_8822B(x) \
- (((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B)
-#define BIT_GET_DARF_RC1_8822B(x) \
- (((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B)
-
-/* 2 REG_RARFRC_8822B */
-
-#define BIT_SHIFT_RARF_RC8_8822B (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC8_8822B 0x1f
-#define BIT_RARF_RC8_8822B(x) \
- (((x) & BIT_MASK_RARF_RC8_8822B) << BIT_SHIFT_RARF_RC8_8822B)
-#define BIT_GET_RARF_RC8_8822B(x) \
- (((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B)
-
-#define BIT_SHIFT_RARF_RC7_8822B (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC7_8822B 0x1f
-#define BIT_RARF_RC7_8822B(x) \
- (((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B)
-#define BIT_GET_RARF_RC7_8822B(x) \
- (((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B)
-
-#define BIT_SHIFT_RARF_RC6_8822B (40 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC6_8822B 0x1f
-#define BIT_RARF_RC6_8822B(x) \
- (((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B)
-#define BIT_GET_RARF_RC6_8822B(x) \
- (((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B)
-
-#define BIT_SHIFT_RARF_RC5_8822B (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC5_8822B 0x1f
-#define BIT_RARF_RC5_8822B(x) \
- (((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B)
-#define BIT_GET_RARF_RC5_8822B(x) \
- (((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B)
-
-#define BIT_SHIFT_RARF_RC4_8822B 24
-#define BIT_MASK_RARF_RC4_8822B 0x1f
-#define BIT_RARF_RC4_8822B(x) \
- (((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B)
-#define BIT_GET_RARF_RC4_8822B(x) \
- (((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B)
-
-#define BIT_SHIFT_RARF_RC3_8822B 16
-#define BIT_MASK_RARF_RC3_8822B 0x1f
-#define BIT_RARF_RC3_8822B(x) \
- (((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B)
-#define BIT_GET_RARF_RC3_8822B(x) \
- (((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B)
-
-#define BIT_SHIFT_RARF_RC2_8822B 8
-#define BIT_MASK_RARF_RC2_8822B 0x1f
-#define BIT_RARF_RC2_8822B(x) \
- (((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B)
-#define BIT_GET_RARF_RC2_8822B(x) \
- (((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B)
-
-#define BIT_SHIFT_RARF_RC1_8822B 0
-#define BIT_MASK_RARF_RC1_8822B 0x1f
-#define BIT_RARF_RC1_8822B(x) \
- (((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B)
-#define BIT_GET_RARF_RC1_8822B(x) \
- (((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B)
-
-/* 2 REG_RRSR_8822B */
-
-#define BIT_SHIFT_RRSR_RSC_8822B 21
-#define BIT_MASK_RRSR_RSC_8822B 0x3
-#define BIT_RRSR_RSC_8822B(x) \
- (((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B)
-#define BIT_GET_RRSR_RSC_8822B(x) \
- (((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B)
-
-#define BIT_RRSR_BW_8822B BIT(20)
-
-#define BIT_SHIFT_RRSC_BITMAP_8822B 0
-#define BIT_MASK_RRSC_BITMAP_8822B 0xfffff
-#define BIT_RRSC_BITMAP_8822B(x) \
- (((x) & BIT_MASK_RRSC_BITMAP_8822B) << BIT_SHIFT_RRSC_BITMAP_8822B)
-#define BIT_GET_RRSC_BITMAP_8822B(x) \
- (((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B)
-
-/* 2 REG_ARFR0_8822B */
-
-#define BIT_SHIFT_ARFR0_V1_8822B 0
-#define BIT_MASK_ARFR0_V1_8822B 0xffffffffffffffffL
-#define BIT_ARFR0_V1_8822B(x) \
- (((x) & BIT_MASK_ARFR0_V1_8822B) << BIT_SHIFT_ARFR0_V1_8822B)
-#define BIT_GET_ARFR0_V1_8822B(x) \
- (((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B)
-
-/* 2 REG_ARFR1_V1_8822B */
-
-#define BIT_SHIFT_ARFR1_V1_8822B 0
-#define BIT_MASK_ARFR1_V1_8822B 0xffffffffffffffffL
-#define BIT_ARFR1_V1_8822B(x) \
- (((x) & BIT_MASK_ARFR1_V1_8822B) << BIT_SHIFT_ARFR1_V1_8822B)
-#define BIT_GET_ARFR1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B)
-
-/* 2 REG_CCK_CHECK_8822B */
-#define BIT_CHECK_CCK_EN_8822B BIT(7)
-#define BIT_EN_BCN_PKT_REL_8822B BIT(6)
-#define BIT_BCN_PORT_SEL_8822B BIT(5)
-#define BIT_MOREDATA_BYPASS_8822B BIT(4)
-#define BIT_EN_CLR_CMD_REL_BCN_PKT_8822B BIT(3)
-#define BIT_R_EN_SET_MOREDATA_8822B BIT(2)
-#define BIT__R_DIS_CLEAR_MACID_RELEASE_8822B BIT(1)
-#define BIT__R_MACID_RELEASE_EN_8822B BIT(0)
-
-/* 2 REG_AMPDU_MAX_TIME_V1_8822B */
-
-#define BIT_SHIFT_AMPDU_MAX_TIME_8822B 0
-#define BIT_MASK_AMPDU_MAX_TIME_8822B 0xff
-#define BIT_AMPDU_MAX_TIME_8822B(x) \
- (((x) & BIT_MASK_AMPDU_MAX_TIME_8822B) \
- << BIT_SHIFT_AMPDU_MAX_TIME_8822B)
-#define BIT_GET_AMPDU_MAX_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) & \
- BIT_MASK_AMPDU_MAX_TIME_8822B)
-
-/* 2 REG_BCNQ1_BDNY_V1_8822B */
-
-#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B 0
-#define BIT_MASK_BCNQ1_PGBNDY_V1_8822B 0xfff
-#define BIT_BCNQ1_PGBNDY_V1_8822B(x) \
- (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) \
- << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B)
-#define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x) \
- (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) & \
- BIT_MASK_BCNQ1_PGBNDY_V1_8822B)
-
-/* 2 REG_AMPDU_MAX_LENGTH_8822B */
-
-#define BIT_SHIFT_AMPDU_MAX_LENGTH_8822B 0
-#define BIT_MASK_AMPDU_MAX_LENGTH_8822B 0xffffffffL
-#define BIT_AMPDU_MAX_LENGTH_8822B(x) \
- (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) \
- << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B)
-#define BIT_GET_AMPDU_MAX_LENGTH_8822B(x) \
- (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) & \
- BIT_MASK_AMPDU_MAX_LENGTH_8822B)
-
-/* 2 REG_ACQ_STOP_8822B */
-#define BIT_AC7Q_STOP_8822B BIT(7)
-#define BIT_AC6Q_STOP_8822B BIT(6)
-#define BIT_AC5Q_STOP_8822B BIT(5)
-#define BIT_AC4Q_STOP_8822B BIT(4)
-#define BIT_AC3Q_STOP_8822B BIT(3)
-#define BIT_AC2Q_STOP_8822B BIT(2)
-#define BIT_AC1Q_STOP_8822B BIT(1)
-#define BIT_AC0Q_STOP_8822B BIT(0)
-
-/* 2 REG_NDPA_RATE_8822B */
-
-#define BIT_SHIFT_R_NDPA_RATE_V1_8822B 0
-#define BIT_MASK_R_NDPA_RATE_V1_8822B 0xff
-#define BIT_R_NDPA_RATE_V1_8822B(x) \
- (((x) & BIT_MASK_R_NDPA_RATE_V1_8822B) \
- << BIT_SHIFT_R_NDPA_RATE_V1_8822B)
-#define BIT_GET_R_NDPA_RATE_V1_8822B(x) \
- (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) & \
- BIT_MASK_R_NDPA_RATE_V1_8822B)
-
-/* 2 REG_TX_HANG_CTRL_8822B */
-#define BIT_R_EN_GNT_BT_AWAKE_8822B BIT(3)
-#define BIT_EN_EOF_V1_8822B BIT(2)
-#define BIT_DIS_OQT_BLOCK_8822B BIT(1)
-#define BIT_SEARCH_QUEUE_EN_8822B BIT(0)
-
-/* 2 REG_NDPA_OPT_CTRL_8822B */
-#define BIT_R_DIS_MACID_RELEASE_RTY_8822B BIT(5)
-
-#define BIT_SHIFT_BW_SIGTA_8822B 3
-#define BIT_MASK_BW_SIGTA_8822B 0x3
-#define BIT_BW_SIGTA_8822B(x) \
- (((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B)
-#define BIT_GET_BW_SIGTA_8822B(x) \
- (((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B)
-
-#define BIT_EN_BAR_SIGTA_8822B BIT(2)
-
-#define BIT_SHIFT_R_NDPA_BW_8822B 0
-#define BIT_MASK_R_NDPA_BW_8822B 0x3
-#define BIT_R_NDPA_BW_8822B(x) \
- (((x) & BIT_MASK_R_NDPA_BW_8822B) << BIT_SHIFT_R_NDPA_BW_8822B)
-#define BIT_GET_R_NDPA_BW_8822B(x) \
- (((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B)
-
-/* 2 REG_RD_RESP_PKT_TH_8822B */
-
-#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B 0
-#define BIT_MASK_RD_RESP_PKT_TH_V1_8822B 0x3f
-#define BIT_RD_RESP_PKT_TH_V1_8822B(x) \
- (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) \
- << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B)
-#define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) & \
- BIT_MASK_RD_RESP_PKT_TH_V1_8822B)
-
-/* 2 REG_CMDQ_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_CMDQ_V1_8822B 0x7f
-#define BIT_QUEUEMACID_CMDQ_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B)
-#define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) & \
- BIT_MASK_QUEUEMACID_CMDQ_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B 23
-#define BIT_MASK_QUEUEAC_CMDQ_V1_8822B 0x3
-#define BIT_QUEUEAC_CMDQ_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) \
- << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B)
-#define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) & \
- BIT_MASK_QUEUEAC_CMDQ_V1_8822B)
-
-#define BIT_TIDEMPTY_CMDQ_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_CMDQ_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_CMDQ_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B)
-#define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) & \
- BIT_MASK_TAIL_PKT_CMDQ_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_CMDQ_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_CMDQ_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B)
-#define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) & \
- BIT_MASK_HEAD_PKT_CMDQ_V1_8822B)
-
-/* 2 REG_Q4_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_Q4_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_Q4_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q4_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q4_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) & \
- BIT_MASK_QUEUEMACID_Q4_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_Q4_V1_8822B 23
-#define BIT_MASK_QUEUEAC_Q4_V1_8822B 0x3
-#define BIT_QUEUEAC_Q4_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B)
-#define BIT_GET_QUEUEAC_Q4_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B)
-
-#define BIT_TIDEMPTY_Q4_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_Q4_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q4_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q4_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) & \
- BIT_MASK_TAIL_PKT_Q4_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_Q4_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_Q4_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q4_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q4_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) & \
- BIT_MASK_HEAD_PKT_Q4_V1_8822B)
-
-/* 2 REG_Q5_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_Q5_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_Q5_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q5_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q5_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) & \
- BIT_MASK_QUEUEMACID_Q5_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_Q5_V1_8822B 23
-#define BIT_MASK_QUEUEAC_Q5_V1_8822B 0x3
-#define BIT_QUEUEAC_Q5_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B)
-#define BIT_GET_QUEUEAC_Q5_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B)
-
-#define BIT_TIDEMPTY_Q5_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_Q5_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_Q5_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q5_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q5_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) & \
- BIT_MASK_TAIL_PKT_Q5_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_Q5_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_Q5_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q5_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q5_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) & \
- BIT_MASK_HEAD_PKT_Q5_V1_8822B)
-
-/* 2 REG_Q6_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_Q6_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_Q6_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q6_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q6_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) & \
- BIT_MASK_QUEUEMACID_Q6_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_Q6_V1_8822B 23
-#define BIT_MASK_QUEUEAC_Q6_V1_8822B 0x3
-#define BIT_QUEUEAC_Q6_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B)
-#define BIT_GET_QUEUEAC_Q6_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B)
-
-#define BIT_TIDEMPTY_Q6_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_Q6_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_Q6_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q6_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q6_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) & \
- BIT_MASK_TAIL_PKT_Q6_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_Q6_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_Q6_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q6_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q6_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) & \
- BIT_MASK_HEAD_PKT_Q6_V1_8822B)
-
-/* 2 REG_Q7_INFO_8822B */
-
-#define BIT_SHIFT_QUEUEMACID_Q7_V1_8822B 25
-#define BIT_MASK_QUEUEMACID_Q7_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q7_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) \
- << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q7_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) & \
- BIT_MASK_QUEUEMACID_Q7_V1_8822B)
-
-#define BIT_SHIFT_QUEUEAC_Q7_V1_8822B 23
-#define BIT_MASK_QUEUEAC_Q7_V1_8822B 0x3
-#define BIT_QUEUEAC_Q7_V1_8822B(x) \
- (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B)
-#define BIT_GET_QUEUEAC_Q7_V1_8822B(x) \
- (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B)
-
-#define BIT_TIDEMPTY_Q7_V1_8822B BIT(22)
-
-#define BIT_SHIFT_TAIL_PKT_Q7_V2_8822B 11
-#define BIT_MASK_TAIL_PKT_Q7_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q7_V2_8822B(x) \
- (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) \
- << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q7_V2_8822B(x) \
- (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) & \
- BIT_MASK_TAIL_PKT_Q7_V2_8822B)
-
-#define BIT_SHIFT_HEAD_PKT_Q7_V1_8822B 0
-#define BIT_MASK_HEAD_PKT_Q7_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q7_V1_8822B(x) \
- (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) \
- << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q7_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) & \
- BIT_MASK_HEAD_PKT_Q7_V1_8822B)
-
-/* 2 REG_WMAC_LBK_BUF_HD_V1_8822B */
-
-#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B 0
-#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B 0xfff
-#define BIT_WMAC_LBK_BUF_HEAD_V1_8822B(x) \
- (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) \
- << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B)
-#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) & \
- BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B)
-
-/* 2 REG_MGQ_BDNY_V1_8822B */
-
-#define BIT_SHIFT_MGQ_PGBNDY_V1_8822B 0
-#define BIT_MASK_MGQ_PGBNDY_V1_8822B 0xfff
-#define BIT_MGQ_PGBNDY_V1_8822B(x) \
- (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822B) << BIT_SHIFT_MGQ_PGBNDY_V1_8822B)
-#define BIT_GET_MGQ_PGBNDY_V1_8822B(x) \
- (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B)
-
-/* 2 REG_TXRPT_CTRL_8822B */
-
-#define BIT_SHIFT_TRXRPT_TIMER_TH_8822B 24
-#define BIT_MASK_TRXRPT_TIMER_TH_8822B 0xff
-#define BIT_TRXRPT_TIMER_TH_8822B(x) \
- (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822B) \
- << BIT_SHIFT_TRXRPT_TIMER_TH_8822B)
-#define BIT_GET_TRXRPT_TIMER_TH_8822B(x) \
- (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) & \
- BIT_MASK_TRXRPT_TIMER_TH_8822B)
-
-#define BIT_SHIFT_TRXRPT_LEN_TH_8822B 16
-#define BIT_MASK_TRXRPT_LEN_TH_8822B 0xff
-#define BIT_TRXRPT_LEN_TH_8822B(x) \
- (((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B)
-#define BIT_GET_TRXRPT_LEN_TH_8822B(x) \
- (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B)
-
-#define BIT_SHIFT_TRXRPT_READ_PTR_8822B 8
-#define BIT_MASK_TRXRPT_READ_PTR_8822B 0xff
-#define BIT_TRXRPT_READ_PTR_8822B(x) \
- (((x) & BIT_MASK_TRXRPT_READ_PTR_8822B) \
- << BIT_SHIFT_TRXRPT_READ_PTR_8822B)
-#define BIT_GET_TRXRPT_READ_PTR_8822B(x) \
- (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) & \
- BIT_MASK_TRXRPT_READ_PTR_8822B)
-
-#define BIT_SHIFT_TRXRPT_WRITE_PTR_8822B 0
-#define BIT_MASK_TRXRPT_WRITE_PTR_8822B 0xff
-#define BIT_TRXRPT_WRITE_PTR_8822B(x) \
- (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) \
- << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B)
-#define BIT_GET_TRXRPT_WRITE_PTR_8822B(x) \
- (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) & \
- BIT_MASK_TRXRPT_WRITE_PTR_8822B)
-
-/* 2 REG_INIRTS_RATE_SEL_8822B */
-#define BIT_LEAG_RTS_BW_DUP_8822B BIT(5)
-
-/* 2 REG_BASIC_CFEND_RATE_8822B */
-
-#define BIT_SHIFT_BASIC_CFEND_RATE_8822B 0
-#define BIT_MASK_BASIC_CFEND_RATE_8822B 0x1f
-#define BIT_BASIC_CFEND_RATE_8822B(x) \
- (((x) & BIT_MASK_BASIC_CFEND_RATE_8822B) \
- << BIT_SHIFT_BASIC_CFEND_RATE_8822B)
-#define BIT_GET_BASIC_CFEND_RATE_8822B(x) \
- (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) & \
- BIT_MASK_BASIC_CFEND_RATE_8822B)
-
-/* 2 REG_STBC_CFEND_RATE_8822B */
-
-#define BIT_SHIFT_STBC_CFEND_RATE_8822B 0
-#define BIT_MASK_STBC_CFEND_RATE_8822B 0x1f
-#define BIT_STBC_CFEND_RATE_8822B(x) \
- (((x) & BIT_MASK_STBC_CFEND_RATE_8822B) \
- << BIT_SHIFT_STBC_CFEND_RATE_8822B)
-#define BIT_GET_STBC_CFEND_RATE_8822B(x) \
- (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) & \
- BIT_MASK_STBC_CFEND_RATE_8822B)
-
-/* 2 REG_DATA_SC_8822B */
-
-#define BIT_SHIFT_TXSC_40M_8822B 4
-#define BIT_MASK_TXSC_40M_8822B 0xf
-#define BIT_TXSC_40M_8822B(x) \
- (((x) & BIT_MASK_TXSC_40M_8822B) << BIT_SHIFT_TXSC_40M_8822B)
-#define BIT_GET_TXSC_40M_8822B(x) \
- (((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B)
-
-#define BIT_SHIFT_TXSC_20M_8822B 0
-#define BIT_MASK_TXSC_20M_8822B 0xf
-#define BIT_TXSC_20M_8822B(x) \
- (((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B)
-#define BIT_GET_TXSC_20M_8822B(x) \
- (((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B)
-
-/* 2 REG_MACID_SLEEP3_8822B */
-
-#define BIT_SHIFT_MACID127_96_PKTSLEEP_8822B 0
-#define BIT_MASK_MACID127_96_PKTSLEEP_8822B 0xffffffffL
-#define BIT_MACID127_96_PKTSLEEP_8822B(x) \
- (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) \
- << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B)
-#define BIT_GET_MACID127_96_PKTSLEEP_8822B(x) \
- (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) & \
- BIT_MASK_MACID127_96_PKTSLEEP_8822B)
-
-/* 2 REG_MACID_SLEEP1_8822B */
-
-#define BIT_SHIFT_MACID63_32_PKTSLEEP_8822B 0
-#define BIT_MASK_MACID63_32_PKTSLEEP_8822B 0xffffffffL
-#define BIT_MACID63_32_PKTSLEEP_8822B(x) \
- (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) \
- << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B)
-#define BIT_GET_MACID63_32_PKTSLEEP_8822B(x) \
- (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) & \
- BIT_MASK_MACID63_32_PKTSLEEP_8822B)
-
-/* 2 REG_ARFR2_V1_8822B */
-
-#define BIT_SHIFT_ARFR2_V1_8822B 0
-#define BIT_MASK_ARFR2_V1_8822B 0xffffffffffffffffL
-#define BIT_ARFR2_V1_8822B(x) \
- (((x) & BIT_MASK_ARFR2_V1_8822B) << BIT_SHIFT_ARFR2_V1_8822B)
-#define BIT_GET_ARFR2_V1_8822B(x) \
- (((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B)
-
-/* 2 REG_ARFR3_V1_8822B */
-
-#define BIT_SHIFT_ARFR3_V1_8822B 0
-#define BIT_MASK_ARFR3_V1_8822B 0xffffffffffffffffL
-#define BIT_ARFR3_V1_8822B(x) \
- (((x) & BIT_MASK_ARFR3_V1_8822B) << BIT_SHIFT_ARFR3_V1_8822B)
-#define BIT_GET_ARFR3_V1_8822B(x) \
- (((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B)
-
-/* 2 REG_ARFR4_8822B */
-
-#define BIT_SHIFT_ARFR4_8822B 0
-#define BIT_MASK_ARFR4_8822B 0xffffffffffffffffL
-#define BIT_ARFR4_8822B(x) \
- (((x) & BIT_MASK_ARFR4_8822B) << BIT_SHIFT_ARFR4_8822B)
-#define BIT_GET_ARFR4_8822B(x) \
- (((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B)
-
-/* 2 REG_ARFR5_8822B */
-
-#define BIT_SHIFT_ARFR5_8822B 0
-#define BIT_MASK_ARFR5_8822B 0xffffffffffffffffL
-#define BIT_ARFR5_8822B(x) \
- (((x) & BIT_MASK_ARFR5_8822B) << BIT_SHIFT_ARFR5_8822B)
-#define BIT_GET_ARFR5_8822B(x) \
- (((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B)
-
-/* 2 REG_TXRPT_START_OFFSET_8822B */
-
-#define BIT_SHIFT_MACID_MURATE_OFFSET_8822B 24
-#define BIT_MASK_MACID_MURATE_OFFSET_8822B 0xff
-#define BIT_MACID_MURATE_OFFSET_8822B(x) \
- (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B) \
- << BIT_SHIFT_MACID_MURATE_OFFSET_8822B)
-#define BIT_GET_MACID_MURATE_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) & \
- BIT_MASK_MACID_MURATE_OFFSET_8822B)
-
-#define BIT_RPTFIFO_SIZE_OPT_8822B BIT(16)
-
-#define BIT_SHIFT_MACID_CTRL_OFFSET_8822B 8
-#define BIT_MASK_MACID_CTRL_OFFSET_8822B 0xff
-#define BIT_MACID_CTRL_OFFSET_8822B(x) \
- (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822B) \
- << BIT_SHIFT_MACID_CTRL_OFFSET_8822B)
-#define BIT_GET_MACID_CTRL_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) & \
- BIT_MASK_MACID_CTRL_OFFSET_8822B)
-
-#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B 0
-#define BIT_MASK_AMPDU_TXRPT_OFFSET_8822B 0xff
-#define BIT_AMPDU_TXRPT_OFFSET_8822B(x) \
- (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) \
- << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B)
-#define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) & \
- BIT_MASK_AMPDU_TXRPT_OFFSET_8822B)
-
-/* 2 REG_POWER_STAGE1_8822B */
-#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822B BIT(31)
-#define BIT_PTA_WL_PRI_MASK_BCNQ_8822B BIT(30)
-#define BIT_PTA_WL_PRI_MASK_HIQ_8822B BIT(29)
-#define BIT_PTA_WL_PRI_MASK_MGQ_8822B BIT(28)
-#define BIT_PTA_WL_PRI_MASK_BK_8822B BIT(27)
-#define BIT_PTA_WL_PRI_MASK_BE_8822B BIT(26)
-#define BIT_PTA_WL_PRI_MASK_VI_8822B BIT(25)
-#define BIT_PTA_WL_PRI_MASK_VO_8822B BIT(24)
-
-#define BIT_SHIFT_POWER_STAGE1_8822B 0
-#define BIT_MASK_POWER_STAGE1_8822B 0xffffff
-#define BIT_POWER_STAGE1_8822B(x) \
- (((x) & BIT_MASK_POWER_STAGE1_8822B) << BIT_SHIFT_POWER_STAGE1_8822B)
-#define BIT_GET_POWER_STAGE1_8822B(x) \
- (((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B)
-
-/* 2 REG_POWER_STAGE2_8822B */
-#define BIT__R_CTRL_PKT_POW_ADJ_8822B BIT(24)
-
-#define BIT_SHIFT_POWER_STAGE2_8822B 0
-#define BIT_MASK_POWER_STAGE2_8822B 0xffffff
-#define BIT_POWER_STAGE2_8822B(x) \
- (((x) & BIT_MASK_POWER_STAGE2_8822B) << BIT_SHIFT_POWER_STAGE2_8822B)
-#define BIT_GET_POWER_STAGE2_8822B(x) \
- (((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B)
-
-/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822B */
-
-#define BIT_SHIFT_PAD_NUM_THRES_8822B 24
-#define BIT_MASK_PAD_NUM_THRES_8822B 0x3f
-#define BIT_PAD_NUM_THRES_8822B(x) \
- (((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B)
-#define BIT_GET_PAD_NUM_THRES_8822B(x) \
- (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B)
-
-#define BIT_R_DMA_THIS_QUEUE_BK_8822B BIT(23)
-#define BIT_R_DMA_THIS_QUEUE_BE_8822B BIT(22)
-#define BIT_R_DMA_THIS_QUEUE_VI_8822B BIT(21)
-#define BIT_R_DMA_THIS_QUEUE_VO_8822B BIT(20)
-
-#define BIT_SHIFT_R_TOTAL_LEN_TH_8822B 8
-#define BIT_MASK_R_TOTAL_LEN_TH_8822B 0xfff
-#define BIT_R_TOTAL_LEN_TH_8822B(x) \
- (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B) \
- << BIT_SHIFT_R_TOTAL_LEN_TH_8822B)
-#define BIT_GET_R_TOTAL_LEN_TH_8822B(x) \
- (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) & \
- BIT_MASK_R_TOTAL_LEN_TH_8822B)
-
-#define BIT_EN_NEW_EARLY_8822B BIT(7)
-#define BIT_PRE_TX_CMD_8822B BIT(6)
-
-#define BIT_SHIFT_NUM_SCL_EN_8822B 4
-#define BIT_MASK_NUM_SCL_EN_8822B 0x3
-#define BIT_NUM_SCL_EN_8822B(x) \
- (((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B)
-#define BIT_GET_NUM_SCL_EN_8822B(x) \
- (((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B)
-
-#define BIT_BK_EN_8822B BIT(3)
-#define BIT_BE_EN_8822B BIT(2)
-#define BIT_VI_EN_8822B BIT(1)
-#define BIT_VO_EN_8822B BIT(0)
-
-/* 2 REG_PKT_LIFE_TIME_8822B */
-
-#define BIT_SHIFT_PKT_LIFTIME_BEBK_8822B 16
-#define BIT_MASK_PKT_LIFTIME_BEBK_8822B 0xffff
-#define BIT_PKT_LIFTIME_BEBK_8822B(x) \
- (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) \
- << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B)
-#define BIT_GET_PKT_LIFTIME_BEBK_8822B(x) \
- (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) & \
- BIT_MASK_PKT_LIFTIME_BEBK_8822B)
-
-#define BIT_SHIFT_PKT_LIFTIME_VOVI_8822B 0
-#define BIT_MASK_PKT_LIFTIME_VOVI_8822B 0xffff
-#define BIT_PKT_LIFTIME_VOVI_8822B(x) \
- (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) \
- << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B)
-#define BIT_GET_PKT_LIFTIME_VOVI_8822B(x) \
- (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) & \
- BIT_MASK_PKT_LIFTIME_VOVI_8822B)
-
-/* 2 REG_STBC_SETTING_8822B */
-
-#define BIT_SHIFT_CDEND_TXTIME_L_8822B 4
-#define BIT_MASK_CDEND_TXTIME_L_8822B 0xf
-#define BIT_CDEND_TXTIME_L_8822B(x) \
- (((x) & BIT_MASK_CDEND_TXTIME_L_8822B) \
- << BIT_SHIFT_CDEND_TXTIME_L_8822B)
-#define BIT_GET_CDEND_TXTIME_L_8822B(x) \
- (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) & \
- BIT_MASK_CDEND_TXTIME_L_8822B)
-
-#define BIT_SHIFT_NESS_8822B 2
-#define BIT_MASK_NESS_8822B 0x3
-#define BIT_NESS_8822B(x) (((x) & BIT_MASK_NESS_8822B) << BIT_SHIFT_NESS_8822B)
-#define BIT_GET_NESS_8822B(x) \
- (((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B)
-
-#define BIT_SHIFT_STBC_CFEND_8822B 0
-#define BIT_MASK_STBC_CFEND_8822B 0x3
-#define BIT_STBC_CFEND_8822B(x) \
- (((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B)
-#define BIT_GET_STBC_CFEND_8822B(x) \
- (((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B)
-
-/* 2 REG_STBC_SETTING2_8822B */
-
-#define BIT_SHIFT_CDEND_TXTIME_H_8822B 0
-#define BIT_MASK_CDEND_TXTIME_H_8822B 0x1f
-#define BIT_CDEND_TXTIME_H_8822B(x) \
- (((x) & BIT_MASK_CDEND_TXTIME_H_8822B) \
- << BIT_SHIFT_CDEND_TXTIME_H_8822B)
-#define BIT_GET_CDEND_TXTIME_H_8822B(x) \
- (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) & \
- BIT_MASK_CDEND_TXTIME_H_8822B)
-
-/* 2 REG_QUEUE_CTRL_8822B */
-#define BIT_PTA_EDCCA_EN_8822B BIT(5)
-#define BIT_PTA_WL_TX_EN_8822B BIT(4)
-#define BIT_R_USE_DATA_BW_8822B BIT(3)
-#define BIT_TRI_PKT_INT_MODE1_8822B BIT(2)
-#define BIT_TRI_PKT_INT_MODE0_8822B BIT(1)
-#define BIT_ACQ_MODE_SEL_8822B BIT(0)
-
-/* 2 REG_SINGLE_AMPDU_CTRL_8822B */
-#define BIT_EN_SINGLE_APMDU_8822B BIT(7)
-
-/* 2 REG_PROT_MODE_CTRL_8822B */
-
-#define BIT_SHIFT_RTS_MAX_AGG_NUM_8822B 24
-#define BIT_MASK_RTS_MAX_AGG_NUM_8822B 0x3f
-#define BIT_RTS_MAX_AGG_NUM_8822B(x) \
- (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) \
- << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B)
-#define BIT_GET_RTS_MAX_AGG_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) & \
- BIT_MASK_RTS_MAX_AGG_NUM_8822B)
-
-#define BIT_SHIFT_MAX_AGG_NUM_8822B 16
-#define BIT_MASK_MAX_AGG_NUM_8822B 0x3f
-#define BIT_MAX_AGG_NUM_8822B(x) \
- (((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B)
-#define BIT_GET_MAX_AGG_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B)
-
-#define BIT_SHIFT_RTS_TXTIME_TH_8822B 8
-#define BIT_MASK_RTS_TXTIME_TH_8822B 0xff
-#define BIT_RTS_TXTIME_TH_8822B(x) \
- (((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B)
-#define BIT_GET_RTS_TXTIME_TH_8822B(x) \
- (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B)
-
-#define BIT_SHIFT_RTS_LEN_TH_8822B 0
-#define BIT_MASK_RTS_LEN_TH_8822B 0xff
-#define BIT_RTS_LEN_TH_8822B(x) \
- (((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B)
-#define BIT_GET_RTS_LEN_TH_8822B(x) \
- (((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B)
-
-/* 2 REG_BAR_MODE_CTRL_8822B */
-
-#define BIT_SHIFT_BAR_RTY_LMT_8822B 16
-#define BIT_MASK_BAR_RTY_LMT_8822B 0x3
-#define BIT_BAR_RTY_LMT_8822B(x) \
- (((x) & BIT_MASK_BAR_RTY_LMT_8822B) << BIT_SHIFT_BAR_RTY_LMT_8822B)
-#define BIT_GET_BAR_RTY_LMT_8822B(x) \
- (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B)
-
-#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B 8
-#define BIT_MASK_BAR_PKT_TXTIME_TH_8822B 0xff
-#define BIT_BAR_PKT_TXTIME_TH_8822B(x) \
- (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) \
- << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B)
-#define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x) \
- (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) & \
- BIT_MASK_BAR_PKT_TXTIME_TH_8822B)
-
-#define BIT_BAR_EN_V1_8822B BIT(6)
-
-#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B 0
-#define BIT_MASK_BAR_PKTNUM_TH_V1_8822B 0x3f
-#define BIT_BAR_PKTNUM_TH_V1_8822B(x) \
- (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) \
- << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B)
-#define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x) \
- (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) & \
- BIT_MASK_BAR_PKTNUM_TH_V1_8822B)
-
-/* 2 REG_RA_TRY_RATE_AGG_LMT_8822B */
-
-#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B 0
-#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B 0x3f
-#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \
- (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) \
- << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B)
-#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \
- (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) & \
- BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B)
-
-/* 2 REG_MACID_SLEEP2_8822B */
-
-#define BIT_SHIFT_MACID95_64PKTSLEEP_8822B 0
-#define BIT_MASK_MACID95_64PKTSLEEP_8822B 0xffffffffL
-#define BIT_MACID95_64PKTSLEEP_8822B(x) \
- (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822B) \
- << BIT_SHIFT_MACID95_64PKTSLEEP_8822B)
-#define BIT_GET_MACID95_64PKTSLEEP_8822B(x) \
- (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) & \
- BIT_MASK_MACID95_64PKTSLEEP_8822B)
-
-/* 2 REG_MACID_SLEEP_8822B */
-
-#define BIT_SHIFT_MACID31_0_PKTSLEEP_8822B 0
-#define BIT_MASK_MACID31_0_PKTSLEEP_8822B 0xffffffffL
-#define BIT_MACID31_0_PKTSLEEP_8822B(x) \
- (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) \
- << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B)
-#define BIT_GET_MACID31_0_PKTSLEEP_8822B(x) \
- (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) & \
- BIT_MASK_MACID31_0_PKTSLEEP_8822B)
-
-/* 2 REG_HW_SEQ0_8822B */
-
-#define BIT_SHIFT_HW_SSN_SEQ0_8822B 0
-#define BIT_MASK_HW_SSN_SEQ0_8822B 0xfff
-#define BIT_HW_SSN_SEQ0_8822B(x) \
- (((x) & BIT_MASK_HW_SSN_SEQ0_8822B) << BIT_SHIFT_HW_SSN_SEQ0_8822B)
-#define BIT_GET_HW_SSN_SEQ0_8822B(x) \
- (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B)
-
-/* 2 REG_HW_SEQ1_8822B */
-
-#define BIT_SHIFT_HW_SSN_SEQ1_8822B 0
-#define BIT_MASK_HW_SSN_SEQ1_8822B 0xfff
-#define BIT_HW_SSN_SEQ1_8822B(x) \
- (((x) & BIT_MASK_HW_SSN_SEQ1_8822B) << BIT_SHIFT_HW_SSN_SEQ1_8822B)
-#define BIT_GET_HW_SSN_SEQ1_8822B(x) \
- (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B)
-
-/* 2 REG_HW_SEQ2_8822B */
-
-#define BIT_SHIFT_HW_SSN_SEQ2_8822B 0
-#define BIT_MASK_HW_SSN_SEQ2_8822B 0xfff
-#define BIT_HW_SSN_SEQ2_8822B(x) \
- (((x) & BIT_MASK_HW_SSN_SEQ2_8822B) << BIT_SHIFT_HW_SSN_SEQ2_8822B)
-#define BIT_GET_HW_SSN_SEQ2_8822B(x) \
- (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B)
-
-/* 2 REG_HW_SEQ3_8822B */
-
-#define BIT_SHIFT_HW_SSN_SEQ3_8822B 0
-#define BIT_MASK_HW_SSN_SEQ3_8822B 0xfff
-#define BIT_HW_SSN_SEQ3_8822B(x) \
- (((x) & BIT_MASK_HW_SSN_SEQ3_8822B) << BIT_SHIFT_HW_SSN_SEQ3_8822B)
-#define BIT_GET_HW_SSN_SEQ3_8822B(x) \
- (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B)
-
-/* 2 REG_NULL_PKT_STATUS_V1_8822B */
-
-#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B 2
-#define BIT_MASK_PTCL_TOTAL_PG_V2_8822B 0x3fff
-#define BIT_PTCL_TOTAL_PG_V2_8822B(x) \
- (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) \
- << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B)
-#define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x) \
- (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) & \
- BIT_MASK_PTCL_TOTAL_PG_V2_8822B)
-
-#define BIT_TX_NULL_1_8822B BIT(1)
-#define BIT_TX_NULL_0_8822B BIT(0)
-
-/* 2 REG_PTCL_ERR_STATUS_8822B */
-#define BIT_PTCL_RATE_TABLE_INVALID_8822B BIT(7)
-#define BIT_FTM_T2R_ERROR_8822B BIT(6)
-#define BIT_PTCL_ERR0_8822B BIT(5)
-#define BIT_PTCL_ERR1_8822B BIT(4)
-#define BIT_PTCL_ERR2_8822B BIT(3)
-#define BIT_PTCL_ERR3_8822B BIT(2)
-#define BIT_PTCL_ERR4_8822B BIT(1)
-#define BIT_PTCL_ERR5_8822B BIT(0)
-
-/* 2 REG_NULL_PKT_STATUS_EXTEND_8822B */
-#define BIT_CLI3_TX_NULL_1_8822B BIT(7)
-#define BIT_CLI3_TX_NULL_0_8822B BIT(6)
-#define BIT_CLI2_TX_NULL_1_8822B BIT(5)
-#define BIT_CLI2_TX_NULL_0_8822B BIT(4)
-#define BIT_CLI1_TX_NULL_1_8822B BIT(3)
-#define BIT_CLI1_TX_NULL_0_8822B BIT(2)
-#define BIT_CLI0_TX_NULL_1_8822B BIT(1)
-#define BIT_CLI0_TX_NULL_0_8822B BIT(0)
-
-/* 2 REG_VIDEO_ENHANCEMENT_FUN_8822B */
-#define BIT_VIDEO_JUST_DROP_8822B BIT(1)
-#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8822B BIT(0)
-
-/* 2 REG_BT_POLLUTE_PKT_CNT_8822B */
-
-#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B 0
-#define BIT_MASK_BT_POLLUTE_PKT_CNT_8822B 0xffff
-#define BIT_BT_POLLUTE_PKT_CNT_8822B(x) \
- (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) \
- << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B)
-#define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x) \
- (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) & \
- BIT_MASK_BT_POLLUTE_PKT_CNT_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_PTCL_DBG_8822B */
-
-#define BIT_SHIFT_PTCL_DBG_8822B 0
-#define BIT_MASK_PTCL_DBG_8822B 0xffffffffL
-#define BIT_PTCL_DBG_8822B(x) \
- (((x) & BIT_MASK_PTCL_DBG_8822B) << BIT_SHIFT_PTCL_DBG_8822B)
-#define BIT_GET_PTCL_DBG_8822B(x) \
- (((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_CPUMGQ_TIMER_CTRL2_8822B */
-
-#define BIT_SHIFT_TRI_HEAD_ADDR_8822B 16
-#define BIT_MASK_TRI_HEAD_ADDR_8822B 0xfff
-#define BIT_TRI_HEAD_ADDR_8822B(x) \
- (((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B)
-#define BIT_GET_TRI_HEAD_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B)
-
-#define BIT_DROP_TH_EN_8822B BIT(8)
-
-#define BIT_SHIFT_DROP_TH_8822B 0
-#define BIT_MASK_DROP_TH_8822B 0xff
-#define BIT_DROP_TH_8822B(x) \
- (((x) & BIT_MASK_DROP_TH_8822B) << BIT_SHIFT_DROP_TH_8822B)
-#define BIT_GET_DROP_TH_8822B(x) \
- (((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_DUMMY_PAGE4_V1_8822B */
-#define BIT_BCN_EN_EXTHWSEQ_8822B BIT(1)
-#define BIT_BCN_EN_HWSEQ_8822B BIT(0)
-
-/* 2 REG_MOREDATA_8822B */
-#define BIT_MOREDATA_CTRL2_EN_V1_8822B BIT(3)
-#define BIT_MOREDATA_CTRL1_EN_V1_8822B BIT(2)
-#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8822B BIT(0)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_Q0_Q1_INFO_8822B */
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
-
-#define BIT_SHIFT_GTAB_ID_8822B 28
-#define BIT_MASK_GTAB_ID_8822B 0x7
-#define BIT_GTAB_ID_8822B(x) \
- (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
-#define BIT_GET_GTAB_ID_8822B(x) \
- (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
-
-#define BIT_SHIFT_AC1_PKT_INFO_8822B 16
-#define BIT_MASK_AC1_PKT_INFO_8822B 0xfff
-#define BIT_AC1_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B)
-#define BIT_GET_AC1_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B)
-
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
-
-#define BIT_SHIFT_GTAB_ID_V1_8822B 12
-#define BIT_MASK_GTAB_ID_V1_8822B 0x7
-#define BIT_GTAB_ID_V1_8822B(x) \
- (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
-#define BIT_GET_GTAB_ID_V1_8822B(x) \
- (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
-
-#define BIT_SHIFT_AC0_PKT_INFO_8822B 0
-#define BIT_MASK_AC0_PKT_INFO_8822B 0xfff
-#define BIT_AC0_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B)
-#define BIT_GET_AC0_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B)
-
-/* 2 REG_Q2_Q3_INFO_8822B */
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
-
-#define BIT_SHIFT_GTAB_ID_8822B 28
-#define BIT_MASK_GTAB_ID_8822B 0x7
-#define BIT_GTAB_ID_8822B(x) \
- (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
-#define BIT_GET_GTAB_ID_8822B(x) \
- (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
-
-#define BIT_SHIFT_AC3_PKT_INFO_8822B 16
-#define BIT_MASK_AC3_PKT_INFO_8822B 0xfff
-#define BIT_AC3_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B)
-#define BIT_GET_AC3_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B)
-
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
-
-#define BIT_SHIFT_GTAB_ID_V1_8822B 12
-#define BIT_MASK_GTAB_ID_V1_8822B 0x7
-#define BIT_GTAB_ID_V1_8822B(x) \
- (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
-#define BIT_GET_GTAB_ID_V1_8822B(x) \
- (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
-
-#define BIT_SHIFT_AC2_PKT_INFO_8822B 0
-#define BIT_MASK_AC2_PKT_INFO_8822B 0xfff
-#define BIT_AC2_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B)
-#define BIT_GET_AC2_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B)
-
-/* 2 REG_Q4_Q5_INFO_8822B */
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
-
-#define BIT_SHIFT_GTAB_ID_8822B 28
-#define BIT_MASK_GTAB_ID_8822B 0x7
-#define BIT_GTAB_ID_8822B(x) \
- (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
-#define BIT_GET_GTAB_ID_8822B(x) \
- (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
-
-#define BIT_SHIFT_AC5_PKT_INFO_8822B 16
-#define BIT_MASK_AC5_PKT_INFO_8822B 0xfff
-#define BIT_AC5_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B)
-#define BIT_GET_AC5_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B)
-
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
-
-#define BIT_SHIFT_GTAB_ID_V1_8822B 12
-#define BIT_MASK_GTAB_ID_V1_8822B 0x7
-#define BIT_GTAB_ID_V1_8822B(x) \
- (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
-#define BIT_GET_GTAB_ID_V1_8822B(x) \
- (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
-
-#define BIT_SHIFT_AC4_PKT_INFO_8822B 0
-#define BIT_MASK_AC4_PKT_INFO_8822B 0xfff
-#define BIT_AC4_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B)
-#define BIT_GET_AC4_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B)
-
-/* 2 REG_Q6_Q7_INFO_8822B */
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
-
-#define BIT_SHIFT_GTAB_ID_8822B 28
-#define BIT_MASK_GTAB_ID_8822B 0x7
-#define BIT_GTAB_ID_8822B(x) \
- (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
-#define BIT_GET_GTAB_ID_8822B(x) \
- (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
-
-#define BIT_SHIFT_AC7_PKT_INFO_8822B 16
-#define BIT_MASK_AC7_PKT_INFO_8822B 0xfff
-#define BIT_AC7_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B)
-#define BIT_GET_AC7_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B)
-
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
-
-#define BIT_SHIFT_GTAB_ID_V1_8822B 12
-#define BIT_MASK_GTAB_ID_V1_8822B 0x7
-#define BIT_GTAB_ID_V1_8822B(x) \
- (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
-#define BIT_GET_GTAB_ID_V1_8822B(x) \
- (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
-
-#define BIT_SHIFT_AC6_PKT_INFO_8822B 0
-#define BIT_MASK_AC6_PKT_INFO_8822B 0xfff
-#define BIT_AC6_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B)
-#define BIT_GET_AC6_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B)
-
-/* 2 REG_MGQ_HIQ_INFO_8822B */
-
-#define BIT_SHIFT_HIQ_PKT_INFO_8822B 16
-#define BIT_MASK_HIQ_PKT_INFO_8822B 0xfff
-#define BIT_HIQ_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_HIQ_PKT_INFO_8822B) << BIT_SHIFT_HIQ_PKT_INFO_8822B)
-#define BIT_GET_HIQ_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B)
-
-#define BIT_SHIFT_MGQ_PKT_INFO_8822B 0
-#define BIT_MASK_MGQ_PKT_INFO_8822B 0xfff
-#define BIT_MGQ_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B)
-#define BIT_GET_MGQ_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B)
-
-/* 2 REG_CMDQ_BCNQ_INFO_8822B */
-
-#define BIT_SHIFT_CMDQ_PKT_INFO_8822B 16
-#define BIT_MASK_CMDQ_PKT_INFO_8822B 0xfff
-#define BIT_CMDQ_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_CMDQ_PKT_INFO_8822B) << BIT_SHIFT_CMDQ_PKT_INFO_8822B)
-#define BIT_GET_CMDQ_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B)
-
-#define BIT_SHIFT_BCNQ_PKT_INFO_8822B 0
-#define BIT_MASK_BCNQ_PKT_INFO_8822B 0xfff
-#define BIT_BCNQ_PKT_INFO_8822B(x) \
- (((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B)
-#define BIT_GET_BCNQ_PKT_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B)
-
-/* 2 REG_USEREG_SETTING_8822B */
-#define BIT_NDPA_USEREG_8822B BIT(21)
-
-#define BIT_SHIFT_RETRY_USEREG_8822B 19
-#define BIT_MASK_RETRY_USEREG_8822B 0x3
-#define BIT_RETRY_USEREG_8822B(x) \
- (((x) & BIT_MASK_RETRY_USEREG_8822B) << BIT_SHIFT_RETRY_USEREG_8822B)
-#define BIT_GET_RETRY_USEREG_8822B(x) \
- (((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B)
-
-#define BIT_SHIFT_TRYPKT_USEREG_8822B 17
-#define BIT_MASK_TRYPKT_USEREG_8822B 0x3
-#define BIT_TRYPKT_USEREG_8822B(x) \
- (((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B)
-#define BIT_GET_TRYPKT_USEREG_8822B(x) \
- (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B)
-
-#define BIT_CTLPKT_USEREG_8822B BIT(16)
-
-/* 2 REG_AESIV_SETTING_8822B */
-
-#define BIT_SHIFT_AESIV_OFFSET_8822B 0
-#define BIT_MASK_AESIV_OFFSET_8822B 0xfff
-#define BIT_AESIV_OFFSET_8822B(x) \
- (((x) & BIT_MASK_AESIV_OFFSET_8822B) << BIT_SHIFT_AESIV_OFFSET_8822B)
-#define BIT_GET_AESIV_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B)
-
-/* 2 REG_BF0_TIME_SETTING_8822B */
-#define BIT_BF0_TIMER_SET_8822B BIT(31)
-#define BIT_BF0_TIMER_CLR_8822B BIT(30)
-#define BIT_BF0_UPDATE_EN_8822B BIT(29)
-#define BIT_BF0_TIMER_EN_8822B BIT(28)
-
-#define BIT_SHIFT_BF0_PRETIME_OVER_8822B 16
-#define BIT_MASK_BF0_PRETIME_OVER_8822B 0xfff
-#define BIT_BF0_PRETIME_OVER_8822B(x) \
- (((x) & BIT_MASK_BF0_PRETIME_OVER_8822B) \
- << BIT_SHIFT_BF0_PRETIME_OVER_8822B)
-#define BIT_GET_BF0_PRETIME_OVER_8822B(x) \
- (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) & \
- BIT_MASK_BF0_PRETIME_OVER_8822B)
-
-#define BIT_SHIFT_BF0_LIFETIME_8822B 0
-#define BIT_MASK_BF0_LIFETIME_8822B 0xffff
-#define BIT_BF0_LIFETIME_8822B(x) \
- (((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B)
-#define BIT_GET_BF0_LIFETIME_8822B(x) \
- (((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B)
-
-/* 2 REG_BF1_TIME_SETTING_8822B */
-#define BIT_BF1_TIMER_SET_8822B BIT(31)
-#define BIT_BF1_TIMER_CLR_8822B BIT(30)
-#define BIT_BF1_UPDATE_EN_8822B BIT(29)
-#define BIT_BF1_TIMER_EN_8822B BIT(28)
-
-#define BIT_SHIFT_BF1_PRETIME_OVER_8822B 16
-#define BIT_MASK_BF1_PRETIME_OVER_8822B 0xfff
-#define BIT_BF1_PRETIME_OVER_8822B(x) \
- (((x) & BIT_MASK_BF1_PRETIME_OVER_8822B) \
- << BIT_SHIFT_BF1_PRETIME_OVER_8822B)
-#define BIT_GET_BF1_PRETIME_OVER_8822B(x) \
- (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) & \
- BIT_MASK_BF1_PRETIME_OVER_8822B)
-
-#define BIT_SHIFT_BF1_LIFETIME_8822B 0
-#define BIT_MASK_BF1_LIFETIME_8822B 0xffff
-#define BIT_BF1_LIFETIME_8822B(x) \
- (((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B)
-#define BIT_GET_BF1_LIFETIME_8822B(x) \
- (((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B)
-
-/* 2 REG_BF_TIMEOUT_EN_8822B */
-#define BIT_EN_VHT_LDPC_8822B BIT(9)
-#define BIT_EN_HT_LDPC_8822B BIT(8)
-#define BIT_BF1_TIMEOUT_EN_8822B BIT(1)
-#define BIT_BF0_TIMEOUT_EN_8822B BIT(0)
-
-/* 2 REG_MACID_RELEASE0_8822B */
-
-#define BIT_SHIFT_MACID31_0_RELEASE_8822B 0
-#define BIT_MASK_MACID31_0_RELEASE_8822B 0xffffffffL
-#define BIT_MACID31_0_RELEASE_8822B(x) \
- (((x) & BIT_MASK_MACID31_0_RELEASE_8822B) \
- << BIT_SHIFT_MACID31_0_RELEASE_8822B)
-#define BIT_GET_MACID31_0_RELEASE_8822B(x) \
- (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) & \
- BIT_MASK_MACID31_0_RELEASE_8822B)
-
-/* 2 REG_MACID_RELEASE1_8822B */
-
-#define BIT_SHIFT_MACID63_32_RELEASE_8822B 0
-#define BIT_MASK_MACID63_32_RELEASE_8822B 0xffffffffL
-#define BIT_MACID63_32_RELEASE_8822B(x) \
- (((x) & BIT_MASK_MACID63_32_RELEASE_8822B) \
- << BIT_SHIFT_MACID63_32_RELEASE_8822B)
-#define BIT_GET_MACID63_32_RELEASE_8822B(x) \
- (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) & \
- BIT_MASK_MACID63_32_RELEASE_8822B)
-
-/* 2 REG_MACID_RELEASE2_8822B */
-
-#define BIT_SHIFT_MACID95_64_RELEASE_8822B 0
-#define BIT_MASK_MACID95_64_RELEASE_8822B 0xffffffffL
-#define BIT_MACID95_64_RELEASE_8822B(x) \
- (((x) & BIT_MASK_MACID95_64_RELEASE_8822B) \
- << BIT_SHIFT_MACID95_64_RELEASE_8822B)
-#define BIT_GET_MACID95_64_RELEASE_8822B(x) \
- (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) & \
- BIT_MASK_MACID95_64_RELEASE_8822B)
-
-/* 2 REG_MACID_RELEASE3_8822B */
-
-#define BIT_SHIFT_MACID127_96_RELEASE_8822B 0
-#define BIT_MASK_MACID127_96_RELEASE_8822B 0xffffffffL
-#define BIT_MACID127_96_RELEASE_8822B(x) \
- (((x) & BIT_MASK_MACID127_96_RELEASE_8822B) \
- << BIT_SHIFT_MACID127_96_RELEASE_8822B)
-#define BIT_GET_MACID127_96_RELEASE_8822B(x) \
- (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) & \
- BIT_MASK_MACID127_96_RELEASE_8822B)
-
-/* 2 REG_MACID_RELEASE_SETTING_8822B */
-#define BIT_MACID_VALUE_8822B BIT(7)
-
-#define BIT_SHIFT_MACID_OFFSET_8822B 0
-#define BIT_MASK_MACID_OFFSET_8822B 0x7f
-#define BIT_MACID_OFFSET_8822B(x) \
- (((x) & BIT_MASK_MACID_OFFSET_8822B) << BIT_SHIFT_MACID_OFFSET_8822B)
-#define BIT_GET_MACID_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B)
-
-/* 2 REG_FAST_EDCA_VOVI_SETTING_8822B */
-
-#define BIT_SHIFT_VI_FAST_EDCA_TO_8822B 24
-#define BIT_MASK_VI_FAST_EDCA_TO_8822B 0xff
-#define BIT_VI_FAST_EDCA_TO_8822B(x) \
- (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B) \
- << BIT_SHIFT_VI_FAST_EDCA_TO_8822B)
-#define BIT_GET_VI_FAST_EDCA_TO_8822B(x) \
- (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) & \
- BIT_MASK_VI_FAST_EDCA_TO_8822B)
-
-#define BIT_VI_THRESHOLD_SEL_8822B BIT(23)
-
-#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B 16
-#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B 0x7f
-#define BIT_VI_FAST_EDCA_PKT_TH_8822B(x) \
- (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) \
- << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B)
-#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x) \
- (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) & \
- BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B)
-
-#define BIT_SHIFT_VO_FAST_EDCA_TO_8822B 8
-#define BIT_MASK_VO_FAST_EDCA_TO_8822B 0xff
-#define BIT_VO_FAST_EDCA_TO_8822B(x) \
- (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B) \
- << BIT_SHIFT_VO_FAST_EDCA_TO_8822B)
-#define BIT_GET_VO_FAST_EDCA_TO_8822B(x) \
- (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) & \
- BIT_MASK_VO_FAST_EDCA_TO_8822B)
-
-#define BIT_VO_THRESHOLD_SEL_8822B BIT(7)
-
-#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B 0
-#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B 0x7f
-#define BIT_VO_FAST_EDCA_PKT_TH_8822B(x) \
- (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) \
- << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B)
-#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x) \
- (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) & \
- BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B)
-
-/* 2 REG_FAST_EDCA_BEBK_SETTING_8822B */
-
-#define BIT_SHIFT_BK_FAST_EDCA_TO_8822B 24
-#define BIT_MASK_BK_FAST_EDCA_TO_8822B 0xff
-#define BIT_BK_FAST_EDCA_TO_8822B(x) \
- (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B) \
- << BIT_SHIFT_BK_FAST_EDCA_TO_8822B)
-#define BIT_GET_BK_FAST_EDCA_TO_8822B(x) \
- (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) & \
- BIT_MASK_BK_FAST_EDCA_TO_8822B)
-
-#define BIT_BK_THRESHOLD_SEL_8822B BIT(23)
-
-#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B 16
-#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B 0x7f
-#define BIT_BK_FAST_EDCA_PKT_TH_8822B(x) \
- (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) \
- << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B)
-#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x) \
- (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) & \
- BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B)
-
-#define BIT_SHIFT_BE_FAST_EDCA_TO_8822B 8
-#define BIT_MASK_BE_FAST_EDCA_TO_8822B 0xff
-#define BIT_BE_FAST_EDCA_TO_8822B(x) \
- (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B) \
- << BIT_SHIFT_BE_FAST_EDCA_TO_8822B)
-#define BIT_GET_BE_FAST_EDCA_TO_8822B(x) \
- (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) & \
- BIT_MASK_BE_FAST_EDCA_TO_8822B)
-
-#define BIT_BE_THRESHOLD_SEL_8822B BIT(7)
-
-#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B 0
-#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B 0x7f
-#define BIT_BE_FAST_EDCA_PKT_TH_8822B(x) \
- (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) \
- << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B)
-#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x) \
- (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) & \
- BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B)
-
-/* 2 REG_MACID_DROP0_8822B */
-
-#define BIT_SHIFT_MACID31_0_DROP_8822B 0
-#define BIT_MASK_MACID31_0_DROP_8822B 0xffffffffL
-#define BIT_MACID31_0_DROP_8822B(x) \
- (((x) & BIT_MASK_MACID31_0_DROP_8822B) \
- << BIT_SHIFT_MACID31_0_DROP_8822B)
-#define BIT_GET_MACID31_0_DROP_8822B(x) \
- (((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) & \
- BIT_MASK_MACID31_0_DROP_8822B)
-
-/* 2 REG_MACID_DROP1_8822B */
-
-#define BIT_SHIFT_MACID63_32_DROP_8822B 0
-#define BIT_MASK_MACID63_32_DROP_8822B 0xffffffffL
-#define BIT_MACID63_32_DROP_8822B(x) \
- (((x) & BIT_MASK_MACID63_32_DROP_8822B) \
- << BIT_SHIFT_MACID63_32_DROP_8822B)
-#define BIT_GET_MACID63_32_DROP_8822B(x) \
- (((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) & \
- BIT_MASK_MACID63_32_DROP_8822B)
-
-/* 2 REG_MACID_DROP2_8822B */
-
-#define BIT_SHIFT_MACID95_64_DROP_8822B 0
-#define BIT_MASK_MACID95_64_DROP_8822B 0xffffffffL
-#define BIT_MACID95_64_DROP_8822B(x) \
- (((x) & BIT_MASK_MACID95_64_DROP_8822B) \
- << BIT_SHIFT_MACID95_64_DROP_8822B)
-#define BIT_GET_MACID95_64_DROP_8822B(x) \
- (((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) & \
- BIT_MASK_MACID95_64_DROP_8822B)
-
-/* 2 REG_MACID_DROP3_8822B */
-
-#define BIT_SHIFT_MACID127_96_DROP_8822B 0
-#define BIT_MASK_MACID127_96_DROP_8822B 0xffffffffL
-#define BIT_MACID127_96_DROP_8822B(x) \
- (((x) & BIT_MASK_MACID127_96_DROP_8822B) \
- << BIT_SHIFT_MACID127_96_DROP_8822B)
-#define BIT_GET_MACID127_96_DROP_8822B(x) \
- (((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) & \
- BIT_MASK_MACID127_96_DROP_8822B)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822B */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_0_8822B(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822B */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_1_8822B(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822B */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_2_8822B(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822B */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_3_8822B(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B)
-
-/* 2 REG_MGG_FIFO_CRTL_8822B */
-#define BIT_R_MGG_FIFO_EN_8822B BIT(31)
-
-#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B 28
-#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B 0x7
-#define BIT_R_MGG_FIFO_PG_SIZE_8822B(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) \
- << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B)
-#define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) & \
- BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B)
-
-#define BIT_SHIFT_R_MGG_FIFO_START_PG_8822B 16
-#define BIT_MASK_R_MGG_FIFO_START_PG_8822B 0xfff
-#define BIT_R_MGG_FIFO_START_PG_8822B(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) \
- << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B)
-#define BIT_GET_R_MGG_FIFO_START_PG_8822B(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) & \
- BIT_MASK_R_MGG_FIFO_START_PG_8822B)
-
-#define BIT_SHIFT_R_MGG_FIFO_SIZE_8822B 14
-#define BIT_MASK_R_MGG_FIFO_SIZE_8822B 0x3
-#define BIT_R_MGG_FIFO_SIZE_8822B(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) \
- << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B)
-#define BIT_GET_R_MGG_FIFO_SIZE_8822B(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) & \
- BIT_MASK_R_MGG_FIFO_SIZE_8822B)
-
-#define BIT_R_MGG_FIFO_PAUSE_8822B BIT(13)
-
-#define BIT_SHIFT_R_MGG_FIFO_RPTR_8822B 8
-#define BIT_MASK_R_MGG_FIFO_RPTR_8822B 0x1f
-#define BIT_R_MGG_FIFO_RPTR_8822B(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) \
- << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B)
-#define BIT_GET_R_MGG_FIFO_RPTR_8822B(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) & \
- BIT_MASK_R_MGG_FIFO_RPTR_8822B)
-
-#define BIT_R_MGG_FIFO_OV_8822B BIT(7)
-#define BIT_R_MGG_FIFO_WPTR_ERROR_8822B BIT(6)
-#define BIT_R_EN_CPU_LIFETIME_8822B BIT(5)
-
-#define BIT_SHIFT_R_MGG_FIFO_WPTR_8822B 0
-#define BIT_MASK_R_MGG_FIFO_WPTR_8822B 0x1f
-#define BIT_R_MGG_FIFO_WPTR_8822B(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) \
- << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B)
-#define BIT_GET_R_MGG_FIFO_WPTR_8822B(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) & \
- BIT_MASK_R_MGG_FIFO_WPTR_8822B)
-
-/* 2 REG_MGG_FIFO_INT_8822B */
-
-#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B 16
-#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B 0xffff
-#define BIT_R_MGG_FIFO_INT_FLAG_8822B(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) \
- << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B)
-#define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) & \
- BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B)
-
-#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B 0
-#define BIT_MASK_R_MGG_FIFO_INT_MASK_8822B 0xffff
-#define BIT_R_MGG_FIFO_INT_MASK_8822B(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) \
- << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B)
-#define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) & \
- BIT_MASK_R_MGG_FIFO_INT_MASK_8822B)
-
-/* 2 REG_MGG_FIFO_LIFETIME_8822B */
-
-#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B 16
-#define BIT_MASK_R_MGG_FIFO_LIFETIME_8822B 0xffff
-#define BIT_R_MGG_FIFO_LIFETIME_8822B(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) \
- << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B)
-#define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) & \
- BIT_MASK_R_MGG_FIFO_LIFETIME_8822B)
-
-#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B 0
-#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B 0xffff
-#define BIT_R_MGG_FIFO_VALID_MAP_8822B(x) \
- (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) \
- << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B)
-#define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x) \
- (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) & \
- BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B)
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x7f
-#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \
- (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) \
- << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) & \
- BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
-
-/* 2 REG_MACID_SHCUT_OFFSET_8822B */
-
-#define BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B 0
-#define BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B 0xff
-#define BIT_MACID_SHCUT_OFFSET_V1_8822B(x) \
- (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B) \
- << BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B)
-#define BIT_GET_MACID_SHCUT_OFFSET_V1_8822B(x) \
- (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B) & \
- BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B)
-
-/* 2 REG_MU_TX_CTL_8822B */
-#define BIT_R_EN_REVERS_GTAB_8822B BIT(6)
-
-#define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0
-#define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f
-#define BIT_R_MU_TABLE_VALID_8822B(x) \
- (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) \
- << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
-#define BIT_GET_R_MU_TABLE_VALID_8822B(x) \
- (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & \
- BIT_MASK_R_MU_TABLE_VALID_8822B)
-
-/* 2 REG_MU_STA_GID_VLD_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
-#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
-#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \
- (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \
- << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
-#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \
- (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \
- BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
-
-#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
-#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
-#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \
- (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \
- << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
-#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \
- (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \
- BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
-
-/* 2 REG_MU_STA_USER_POS_INFO_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
-#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
-#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \
- (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \
- << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
-#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \
- (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \
- BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
-
-#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
-#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
-#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \
- (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \
- << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
-#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \
- (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \
- BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
-
-/* 2 REG_MU_TRX_DBG_CNT_8822B */
-#define BIT_MU_DNGCNT_RST_8822B BIT(20)
-
-#define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16
-#define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf
-#define BIT_MU_DBGCNT_SEL_8822B(x) \
- (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
-#define BIT_GET_MU_DBGCNT_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B)
-
-#define BIT_SHIFT_MU_DNGCNT_8822B 0
-#define BIT_MASK_MU_DNGCNT_8822B 0xffff
-#define BIT_MU_DNGCNT_8822B(x) \
- (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B)
-#define BIT_GET_MU_DNGCNT_8822B(x) \
- (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_EDCA_VO_PARAM_8822B */
-
-#define BIT_SHIFT_TXOPLIMIT_8822B 16
-#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
-#define BIT_TXOPLIMIT_8822B(x) \
- (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
-#define BIT_GET_TXOPLIMIT_8822B(x) \
- (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
-
-#define BIT_SHIFT_CW_8822B 8
-#define BIT_MASK_CW_8822B 0xff
-#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
-#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
-
-#define BIT_SHIFT_AIFS_8822B 0
-#define BIT_MASK_AIFS_8822B 0xff
-#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
-#define BIT_GET_AIFS_8822B(x) \
- (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
-
-/* 2 REG_EDCA_VI_PARAM_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_TXOPLIMIT_8822B 16
-#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
-#define BIT_TXOPLIMIT_8822B(x) \
- (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
-#define BIT_GET_TXOPLIMIT_8822B(x) \
- (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
-
-#define BIT_SHIFT_CW_8822B 8
-#define BIT_MASK_CW_8822B 0xff
-#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
-#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
-
-#define BIT_SHIFT_AIFS_8822B 0
-#define BIT_MASK_AIFS_8822B 0xff
-#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
-#define BIT_GET_AIFS_8822B(x) \
- (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
-
-/* 2 REG_EDCA_BE_PARAM_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_TXOPLIMIT_8822B 16
-#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
-#define BIT_TXOPLIMIT_8822B(x) \
- (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
-#define BIT_GET_TXOPLIMIT_8822B(x) \
- (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
-
-#define BIT_SHIFT_CW_8822B 8
-#define BIT_MASK_CW_8822B 0xff
-#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
-#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
-
-#define BIT_SHIFT_AIFS_8822B 0
-#define BIT_MASK_AIFS_8822B 0xff
-#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
-#define BIT_GET_AIFS_8822B(x) \
- (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
-
-/* 2 REG_EDCA_BK_PARAM_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_TXOPLIMIT_8822B 16
-#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
-#define BIT_TXOPLIMIT_8822B(x) \
- (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
-#define BIT_GET_TXOPLIMIT_8822B(x) \
- (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
-
-#define BIT_SHIFT_CW_8822B 8
-#define BIT_MASK_CW_8822B 0xff
-#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
-#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
-
-#define BIT_SHIFT_AIFS_8822B 0
-#define BIT_MASK_AIFS_8822B 0xff
-#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
-#define BIT_GET_AIFS_8822B(x) \
- (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
-
-/* 2 REG_BCNTCFG_8822B */
-
-#define BIT_SHIFT_BCNCW_MAX_8822B 12
-#define BIT_MASK_BCNCW_MAX_8822B 0xf
-#define BIT_BCNCW_MAX_8822B(x) \
- (((x) & BIT_MASK_BCNCW_MAX_8822B) << BIT_SHIFT_BCNCW_MAX_8822B)
-#define BIT_GET_BCNCW_MAX_8822B(x) \
- (((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B)
-
-#define BIT_SHIFT_BCNCW_MIN_8822B 8
-#define BIT_MASK_BCNCW_MIN_8822B 0xf
-#define BIT_BCNCW_MIN_8822B(x) \
- (((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B)
-#define BIT_GET_BCNCW_MIN_8822B(x) \
- (((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B)
-
-#define BIT_SHIFT_BCNIFS_8822B 0
-#define BIT_MASK_BCNIFS_8822B 0xff
-#define BIT_BCNIFS_8822B(x) \
- (((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B)
-#define BIT_GET_BCNIFS_8822B(x) \
- (((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B)
-
-/* 2 REG_PIFS_8822B */
-
-#define BIT_SHIFT_PIFS_8822B 0
-#define BIT_MASK_PIFS_8822B 0xff
-#define BIT_PIFS_8822B(x) (((x) & BIT_MASK_PIFS_8822B) << BIT_SHIFT_PIFS_8822B)
-#define BIT_GET_PIFS_8822B(x) \
- (((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B)
-
-/* 2 REG_RDG_PIFS_8822B */
-
-#define BIT_SHIFT_RDG_PIFS_8822B 0
-#define BIT_MASK_RDG_PIFS_8822B 0xff
-#define BIT_RDG_PIFS_8822B(x) \
- (((x) & BIT_MASK_RDG_PIFS_8822B) << BIT_SHIFT_RDG_PIFS_8822B)
-#define BIT_GET_RDG_PIFS_8822B(x) \
- (((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B)
-
-/* 2 REG_SIFS_8822B */
-
-#define BIT_SHIFT_SIFS_OFDM_TRX_8822B 24
-#define BIT_MASK_SIFS_OFDM_TRX_8822B 0xff
-#define BIT_SIFS_OFDM_TRX_8822B(x) \
- (((x) & BIT_MASK_SIFS_OFDM_TRX_8822B) << BIT_SHIFT_SIFS_OFDM_TRX_8822B)
-#define BIT_GET_SIFS_OFDM_TRX_8822B(x) \
- (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B)
-
-#define BIT_SHIFT_SIFS_CCK_TRX_8822B 16
-#define BIT_MASK_SIFS_CCK_TRX_8822B 0xff
-#define BIT_SIFS_CCK_TRX_8822B(x) \
- (((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B)
-#define BIT_GET_SIFS_CCK_TRX_8822B(x) \
- (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B)
-
-#define BIT_SHIFT_SIFS_OFDM_CTX_8822B 8
-#define BIT_MASK_SIFS_OFDM_CTX_8822B 0xff
-#define BIT_SIFS_OFDM_CTX_8822B(x) \
- (((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B)
-#define BIT_GET_SIFS_OFDM_CTX_8822B(x) \
- (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B)
-
-#define BIT_SHIFT_SIFS_CCK_CTX_8822B 0
-#define BIT_MASK_SIFS_CCK_CTX_8822B 0xff
-#define BIT_SIFS_CCK_CTX_8822B(x) \
- (((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B)
-#define BIT_GET_SIFS_CCK_CTX_8822B(x) \
- (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B)
-
-/* 2 REG_TSFTR_SYN_OFFSET_8822B */
-
-#define BIT_SHIFT_TSFTR_SNC_OFFSET_8822B 0
-#define BIT_MASK_TSFTR_SNC_OFFSET_8822B 0xffff
-#define BIT_TSFTR_SNC_OFFSET_8822B(x) \
- (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) \
- << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B)
-#define BIT_GET_TSFTR_SNC_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) & \
- BIT_MASK_TSFTR_SNC_OFFSET_8822B)
-
-/* 2 REG_AGGR_BREAK_TIME_8822B */
-
-#define BIT_SHIFT_AGGR_BK_TIME_8822B 0
-#define BIT_MASK_AGGR_BK_TIME_8822B 0xff
-#define BIT_AGGR_BK_TIME_8822B(x) \
- (((x) & BIT_MASK_AGGR_BK_TIME_8822B) << BIT_SHIFT_AGGR_BK_TIME_8822B)
-#define BIT_GET_AGGR_BK_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B)
-
-/* 2 REG_SLOT_8822B */
-
-#define BIT_SHIFT_SLOT_8822B 0
-#define BIT_MASK_SLOT_8822B 0xff
-#define BIT_SLOT_8822B(x) (((x) & BIT_MASK_SLOT_8822B) << BIT_SHIFT_SLOT_8822B)
-#define BIT_GET_SLOT_8822B(x) \
- (((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B)
-
-/* 2 REG_TX_PTCL_CTRL_8822B */
-#define BIT_DIS_EDCCA_8822B BIT(15)
-#define BIT_DIS_CCA_8822B BIT(14)
-#define BIT_LSIG_TXOP_TXCMD_NAV_8822B BIT(13)
-#define BIT_SIFS_BK_EN_8822B BIT(12)
-
-#define BIT_SHIFT_TXQ_NAV_MSK_8822B 8
-#define BIT_MASK_TXQ_NAV_MSK_8822B 0xf
-#define BIT_TXQ_NAV_MSK_8822B(x) \
- (((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B)
-#define BIT_GET_TXQ_NAV_MSK_8822B(x) \
- (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B)
-
-#define BIT_DIS_CW_8822B BIT(7)
-#define BIT_NAV_END_TXOP_8822B BIT(6)
-#define BIT_RDG_END_TXOP_8822B BIT(5)
-#define BIT_AC_INBCN_HOLD_8822B BIT(4)
-#define BIT_MGTQ_TXOP_EN_8822B BIT(3)
-#define BIT_MGTQ_RTSMF_EN_8822B BIT(2)
-#define BIT_HIQ_RTSMF_EN_8822B BIT(1)
-#define BIT_BCN_RTSMF_EN_8822B BIT(0)
-
-/* 2 REG_TXPAUSE_8822B */
-#define BIT_STOP_BCN_HI_MGT_8822B BIT(7)
-#define BIT_MAC_STOPBCNQ_8822B BIT(6)
-#define BIT_MAC_STOPHIQ_8822B BIT(5)
-#define BIT_MAC_STOPMGQ_8822B BIT(4)
-#define BIT_MAC_STOPBK_8822B BIT(3)
-#define BIT_MAC_STOPBE_8822B BIT(2)
-#define BIT_MAC_STOPVI_8822B BIT(1)
-#define BIT_MAC_STOPVO_8822B BIT(0)
-
-/* 2 REG_DIS_TXREQ_CLR_8822B */
-#define BIT_DIS_BT_CCA_8822B BIT(7)
-#define BIT_DIS_TXREQ_CLR_HI_8822B BIT(5)
-#define BIT_DIS_TXREQ_CLR_MGQ_8822B BIT(4)
-#define BIT_DIS_TXREQ_CLR_VO_8822B BIT(3)
-#define BIT_DIS_TXREQ_CLR_VI_8822B BIT(2)
-#define BIT_DIS_TXREQ_CLR_BE_8822B BIT(1)
-#define BIT_DIS_TXREQ_CLR_BK_8822B BIT(0)
-
-/* 2 REG_RD_CTRL_8822B */
-#define BIT_EN_CLR_TXREQ_INCCA_8822B BIT(15)
-#define BIT_DIS_TX_OVER_BCNQ_8822B BIT(14)
-#define BIT_EN_BCNERR_INCCCA_8822B BIT(13)
-#define BIT_EDCCA_MSK_CNTDOWN_EN_8822B BIT(11)
-#define BIT_DIS_TXOP_CFE_8822B BIT(10)
-#define BIT_DIS_LSIG_CFE_8822B BIT(9)
-#define BIT_DIS_STBC_CFE_8822B BIT(8)
-#define BIT_BKQ_RD_INIT_EN_8822B BIT(7)
-#define BIT_BEQ_RD_INIT_EN_8822B BIT(6)
-#define BIT_VIQ_RD_INIT_EN_8822B BIT(5)
-#define BIT_VOQ_RD_INIT_EN_8822B BIT(4)
-#define BIT_BKQ_RD_RESP_EN_8822B BIT(3)
-#define BIT_BEQ_RD_RESP_EN_8822B BIT(2)
-#define BIT_VIQ_RD_RESP_EN_8822B BIT(1)
-#define BIT_VOQ_RD_RESP_EN_8822B BIT(0)
-
-/* 2 REG_MBSSID_CTRL_8822B */
-#define BIT_MBID_BCNQ7_EN_8822B BIT(7)
-#define BIT_MBID_BCNQ6_EN_8822B BIT(6)
-#define BIT_MBID_BCNQ5_EN_8822B BIT(5)
-#define BIT_MBID_BCNQ4_EN_8822B BIT(4)
-#define BIT_MBID_BCNQ3_EN_8822B BIT(3)
-#define BIT_MBID_BCNQ2_EN_8822B BIT(2)
-#define BIT_MBID_BCNQ1_EN_8822B BIT(1)
-#define BIT_MBID_BCNQ0_EN_8822B BIT(0)
-
-/* 2 REG_P2PPS_CTRL_8822B */
-#define BIT_P2P_CTW_ALLSTASLEEP_8822B BIT(7)
-#define BIT_P2P_OFF_DISTX_EN_8822B BIT(6)
-#define BIT_PWR_MGT_EN_8822B BIT(5)
-#define BIT_P2P_NOA1_EN_8822B BIT(2)
-#define BIT_P2P_NOA0_EN_8822B BIT(1)
-
-/* 2 REG_PKT_LIFETIME_CTRL_8822B */
-#define BIT_EN_P2P_CTWND1_8822B BIT(23)
-#define BIT_EN_BKF_CLR_TXREQ_8822B BIT(22)
-#define BIT_EN_TSFBIT32_RST_P2P_8822B BIT(21)
-#define BIT_EN_BCN_TX_BTCCA_8822B BIT(20)
-#define BIT_DIS_PKT_TX_ATIM_8822B BIT(19)
-#define BIT_DIS_BCN_DIS_CTN_8822B BIT(18)
-#define BIT_EN_NAVEND_RST_TXOP_8822B BIT(17)
-#define BIT_EN_FILTER_CCA_8822B BIT(16)
-
-#define BIT_SHIFT_CCA_FILTER_THRS_8822B 8
-#define BIT_MASK_CCA_FILTER_THRS_8822B 0xff
-#define BIT_CCA_FILTER_THRS_8822B(x) \
- (((x) & BIT_MASK_CCA_FILTER_THRS_8822B) \
- << BIT_SHIFT_CCA_FILTER_THRS_8822B)
-#define BIT_GET_CCA_FILTER_THRS_8822B(x) \
- (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) & \
- BIT_MASK_CCA_FILTER_THRS_8822B)
-
-#define BIT_SHIFT_EDCCA_THRS_8822B 0
-#define BIT_MASK_EDCCA_THRS_8822B 0xff
-#define BIT_EDCCA_THRS_8822B(x) \
- (((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B)
-#define BIT_GET_EDCCA_THRS_8822B(x) \
- (((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B)
-
-/* 2 REG_P2PPS_SPEC_STATE_8822B */
-#define BIT_SPEC_POWER_STATE_8822B BIT(7)
-#define BIT_SPEC_CTWINDOW_ON_8822B BIT(6)
-#define BIT_SPEC_BEACON_AREA_ON_8822B BIT(5)
-#define BIT_SPEC_CTWIN_EARLY_DISTX_8822B BIT(4)
-#define BIT_SPEC_NOA1_OFF_PERIOD_8822B BIT(3)
-#define BIT_SPEC_FORCE_DOZE1_8822B BIT(2)
-#define BIT_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)
-#define BIT_SPEC_FORCE_DOZE0_8822B BIT(0)
-
-/* 2 REG_BAR_TX_CTRL_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_P2PON_DIS_TXTIME_8822B 0
-#define BIT_MASK_P2PON_DIS_TXTIME_8822B 0xff
-#define BIT_P2PON_DIS_TXTIME_8822B(x) \
- (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822B) \
- << BIT_SHIFT_P2PON_DIS_TXTIME_8822B)
-#define BIT_GET_P2PON_DIS_TXTIME_8822B(x) \
- (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) & \
- BIT_MASK_P2PON_DIS_TXTIME_8822B)
-
-/* 2 REG_QUEUE_INCOL_THR_8822B */
-
-#define BIT_SHIFT_BK_QUEUE_THR_8822B 24
-#define BIT_MASK_BK_QUEUE_THR_8822B 0xff
-#define BIT_BK_QUEUE_THR_8822B(x) \
- (((x) & BIT_MASK_BK_QUEUE_THR_8822B) << BIT_SHIFT_BK_QUEUE_THR_8822B)
-#define BIT_GET_BK_QUEUE_THR_8822B(x) \
- (((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B)
-
-#define BIT_SHIFT_BE_QUEUE_THR_8822B 16
-#define BIT_MASK_BE_QUEUE_THR_8822B 0xff
-#define BIT_BE_QUEUE_THR_8822B(x) \
- (((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B)
-#define BIT_GET_BE_QUEUE_THR_8822B(x) \
- (((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B)
-
-#define BIT_SHIFT_VI_QUEUE_THR_8822B 8
-#define BIT_MASK_VI_QUEUE_THR_8822B 0xff
-#define BIT_VI_QUEUE_THR_8822B(x) \
- (((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B)
-#define BIT_GET_VI_QUEUE_THR_8822B(x) \
- (((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B)
-
-#define BIT_SHIFT_VO_QUEUE_THR_8822B 0
-#define BIT_MASK_VO_QUEUE_THR_8822B 0xff
-#define BIT_VO_QUEUE_THR_8822B(x) \
- (((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B)
-#define BIT_GET_VO_QUEUE_THR_8822B(x) \
- (((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B)
-
-/* 2 REG_QUEUE_INCOL_EN_8822B */
-#define BIT_QUEUE_INCOL_EN_8822B BIT(16)
-
-#define BIT_SHIFT_BE_TRIGGER_NUM_8822B 12
-#define BIT_MASK_BE_TRIGGER_NUM_8822B 0xf
-#define BIT_BE_TRIGGER_NUM_8822B(x) \
- (((x) & BIT_MASK_BE_TRIGGER_NUM_8822B) \
- << BIT_SHIFT_BE_TRIGGER_NUM_8822B)
-#define BIT_GET_BE_TRIGGER_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) & \
- BIT_MASK_BE_TRIGGER_NUM_8822B)
-
-#define BIT_SHIFT_BK_TRIGGER_NUM_8822B 8
-#define BIT_MASK_BK_TRIGGER_NUM_8822B 0xf
-#define BIT_BK_TRIGGER_NUM_8822B(x) \
- (((x) & BIT_MASK_BK_TRIGGER_NUM_8822B) \
- << BIT_SHIFT_BK_TRIGGER_NUM_8822B)
-#define BIT_GET_BK_TRIGGER_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) & \
- BIT_MASK_BK_TRIGGER_NUM_8822B)
-
-#define BIT_SHIFT_VI_TRIGGER_NUM_8822B 4
-#define BIT_MASK_VI_TRIGGER_NUM_8822B 0xf
-#define BIT_VI_TRIGGER_NUM_8822B(x) \
- (((x) & BIT_MASK_VI_TRIGGER_NUM_8822B) \
- << BIT_SHIFT_VI_TRIGGER_NUM_8822B)
-#define BIT_GET_VI_TRIGGER_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) & \
- BIT_MASK_VI_TRIGGER_NUM_8822B)
-
-#define BIT_SHIFT_VO_TRIGGER_NUM_8822B 0
-#define BIT_MASK_VO_TRIGGER_NUM_8822B 0xf
-#define BIT_VO_TRIGGER_NUM_8822B(x) \
- (((x) & BIT_MASK_VO_TRIGGER_NUM_8822B) \
- << BIT_SHIFT_VO_TRIGGER_NUM_8822B)
-#define BIT_GET_VO_TRIGGER_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) & \
- BIT_MASK_VO_TRIGGER_NUM_8822B)
-
-/* 2 REG_TBTT_PROHIBIT_8822B */
-
-#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B 8
-#define BIT_MASK_TBTT_HOLD_TIME_AP_8822B 0xfff
-#define BIT_TBTT_HOLD_TIME_AP_8822B(x) \
- (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) \
- << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B)
-#define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x) \
- (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) & \
- BIT_MASK_TBTT_HOLD_TIME_AP_8822B)
-
-#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B 0
-#define BIT_MASK_TBTT_PROHIBIT_SETUP_8822B 0xf
-#define BIT_TBTT_PROHIBIT_SETUP_8822B(x) \
- (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) \
- << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B)
-#define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x) \
- (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) & \
- BIT_MASK_TBTT_PROHIBIT_SETUP_8822B)
-
-/* 2 REG_P2PPS_STATE_8822B */
-#define BIT_POWER_STATE_8822B BIT(7)
-#define BIT_CTWINDOW_ON_8822B BIT(6)
-#define BIT_BEACON_AREA_ON_8822B BIT(5)
-#define BIT_CTWIN_EARLY_DISTX_8822B BIT(4)
-#define BIT_NOA1_OFF_PERIOD_8822B BIT(3)
-#define BIT_FORCE_DOZE1_8822B BIT(2)
-#define BIT_NOA0_OFF_PERIOD_8822B BIT(1)
-#define BIT_FORCE_DOZE0_8822B BIT(0)
-
-/* 2 REG_RD_NAV_NXT_8822B */
-
-#define BIT_SHIFT_RD_NAV_PROT_NXT_8822B 0
-#define BIT_MASK_RD_NAV_PROT_NXT_8822B 0xffff
-#define BIT_RD_NAV_PROT_NXT_8822B(x) \
- (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822B) \
- << BIT_SHIFT_RD_NAV_PROT_NXT_8822B)
-#define BIT_GET_RD_NAV_PROT_NXT_8822B(x) \
- (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) & \
- BIT_MASK_RD_NAV_PROT_NXT_8822B)
-
-/* 2 REG_NAV_PROT_LEN_8822B */
-
-#define BIT_SHIFT_NAV_PROT_LEN_8822B 0
-#define BIT_MASK_NAV_PROT_LEN_8822B 0xffff
-#define BIT_NAV_PROT_LEN_8822B(x) \
- (((x) & BIT_MASK_NAV_PROT_LEN_8822B) << BIT_SHIFT_NAV_PROT_LEN_8822B)
-#define BIT_GET_NAV_PROT_LEN_8822B(x) \
- (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B)
-
-/* 2 REG_BCN_CTRL_8822B */
-#define BIT_DIS_RX_BSSID_FIT_8822B BIT(6)
-#define BIT_P0_EN_TXBCN_RPT_8822B BIT(5)
-#define BIT_DIS_TSF_UDT_8822B BIT(4)
-#define BIT_EN_BCN_FUNCTION_8822B BIT(3)
-#define BIT_P0_EN_RXBCN_RPT_8822B BIT(2)
-#define BIT_EN_P2P_CTWINDOW_8822B BIT(1)
-#define BIT_EN_P2P_BCNQ_AREA_8822B BIT(0)
-
-/* 2 REG_BCN_CTRL_CLINT0_8822B */
-#define BIT_CLI0_DIS_RX_BSSID_FIT_8822B BIT(6)
-#define BIT_CLI0_DIS_TSF_UDT_8822B BIT(4)
-#define BIT_CLI0_EN_BCN_FUNCTION_8822B BIT(3)
-#define BIT_CLI0_EN_RXBCN_RPT_8822B BIT(2)
-#define BIT_CLI0_ENP2P_CTWINDOW_8822B BIT(1)
-#define BIT_CLI0_ENP2P_BCNQ_AREA_8822B BIT(0)
-
-/* 2 REG_MBID_NUM_8822B */
-#define BIT_EN_PRE_DL_BEACON_8822B BIT(3)
-
-#define BIT_SHIFT_MBID_BCN_NUM_8822B 0
-#define BIT_MASK_MBID_BCN_NUM_8822B 0x7
-#define BIT_MBID_BCN_NUM_8822B(x) \
- (((x) & BIT_MASK_MBID_BCN_NUM_8822B) << BIT_SHIFT_MBID_BCN_NUM_8822B)
-#define BIT_GET_MBID_BCN_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B)
-
-/* 2 REG_DUAL_TSF_RST_8822B */
-#define BIT_FREECNT_RST_8822B BIT(5)
-#define BIT_TSFTR_CLI3_RST_8822B BIT(4)
-#define BIT_TSFTR_CLI2_RST_8822B BIT(3)
-#define BIT_TSFTR_CLI1_RST_8822B BIT(2)
-#define BIT_TSFTR_CLI0_RST_8822B BIT(1)
-#define BIT_TSFTR_RST_8822B BIT(0)
-
-/* 2 REG_MBSSID_BCN_SPACE_8822B */
-
-#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B 28
-#define BIT_MASK_BCN_TIMER_SEL_FWRD_8822B 0x7
-#define BIT_BCN_TIMER_SEL_FWRD_8822B(x) \
- (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) \
- << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B)
-#define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x) \
- (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) & \
- BIT_MASK_BCN_TIMER_SEL_FWRD_8822B)
-
-#define BIT_SHIFT_BCN_SPACE_CLINT0_8822B 16
-#define BIT_MASK_BCN_SPACE_CLINT0_8822B 0xfff
-#define BIT_BCN_SPACE_CLINT0_8822B(x) \
- (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B) \
- << BIT_SHIFT_BCN_SPACE_CLINT0_8822B)
-#define BIT_GET_BCN_SPACE_CLINT0_8822B(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) & \
- BIT_MASK_BCN_SPACE_CLINT0_8822B)
-
-#define BIT_SHIFT_BCN_SPACE0_8822B 0
-#define BIT_MASK_BCN_SPACE0_8822B 0xffff
-#define BIT_BCN_SPACE0_8822B(x) \
- (((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B)
-#define BIT_GET_BCN_SPACE0_8822B(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B)
-
-/* 2 REG_DRVERLYINT_8822B */
-
-#define BIT_SHIFT_DRVERLYITV_8822B 0
-#define BIT_MASK_DRVERLYITV_8822B 0xff
-#define BIT_DRVERLYITV_8822B(x) \
- (((x) & BIT_MASK_DRVERLYITV_8822B) << BIT_SHIFT_DRVERLYITV_8822B)
-#define BIT_GET_DRVERLYITV_8822B(x) \
- (((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B)
-
-/* 2 REG_BCNDMATIM_8822B */
-
-#define BIT_SHIFT_BCNDMATIM_8822B 0
-#define BIT_MASK_BCNDMATIM_8822B 0xff
-#define BIT_BCNDMATIM_8822B(x) \
- (((x) & BIT_MASK_BCNDMATIM_8822B) << BIT_SHIFT_BCNDMATIM_8822B)
-#define BIT_GET_BCNDMATIM_8822B(x) \
- (((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B)
-
-/* 2 REG_ATIMWND_8822B */
-
-#define BIT_SHIFT_ATIMWND0_8822B 0
-#define BIT_MASK_ATIMWND0_8822B 0xffff
-#define BIT_ATIMWND0_8822B(x) \
- (((x) & BIT_MASK_ATIMWND0_8822B) << BIT_SHIFT_ATIMWND0_8822B)
-#define BIT_GET_ATIMWND0_8822B(x) \
- (((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B)
-
-/* 2 REG_USTIME_TSF_8822B */
-
-#define BIT_SHIFT_USTIME_TSF_V1_8822B 0
-#define BIT_MASK_USTIME_TSF_V1_8822B 0xff
-#define BIT_USTIME_TSF_V1_8822B(x) \
- (((x) & BIT_MASK_USTIME_TSF_V1_8822B) << BIT_SHIFT_USTIME_TSF_V1_8822B)
-#define BIT_GET_USTIME_TSF_V1_8822B(x) \
- (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B)
-
-/* 2 REG_BCN_MAX_ERR_8822B */
-
-#define BIT_SHIFT_BCN_MAX_ERR_8822B 0
-#define BIT_MASK_BCN_MAX_ERR_8822B 0xff
-#define BIT_BCN_MAX_ERR_8822B(x) \
- (((x) & BIT_MASK_BCN_MAX_ERR_8822B) << BIT_SHIFT_BCN_MAX_ERR_8822B)
-#define BIT_GET_BCN_MAX_ERR_8822B(x) \
- (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B)
-
-/* 2 REG_RXTSF_OFFSET_CCK_8822B */
-
-#define BIT_SHIFT_CCK_RXTSF_OFFSET_8822B 0
-#define BIT_MASK_CCK_RXTSF_OFFSET_8822B 0xff
-#define BIT_CCK_RXTSF_OFFSET_8822B(x) \
- (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) \
- << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B)
-#define BIT_GET_CCK_RXTSF_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) & \
- BIT_MASK_CCK_RXTSF_OFFSET_8822B)
-
-/* 2 REG_RXTSF_OFFSET_OFDM_8822B */
-
-#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B 0
-#define BIT_MASK_OFDM_RXTSF_OFFSET_8822B 0xff
-#define BIT_OFDM_RXTSF_OFFSET_8822B(x) \
- (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) \
- << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B)
-#define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) & \
- BIT_MASK_OFDM_RXTSF_OFFSET_8822B)
-
-/* 2 REG_TSFTR_8822B */
-
-#define BIT_SHIFT_TSF_TIMER_8822B 0
-#define BIT_MASK_TSF_TIMER_8822B 0xffffffffffffffffL
-#define BIT_TSF_TIMER_8822B(x) \
- (((x) & BIT_MASK_TSF_TIMER_8822B) << BIT_SHIFT_TSF_TIMER_8822B)
-#define BIT_GET_TSF_TIMER_8822B(x) \
- (((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B)
-
-/* 2 REG_FREERUN_CNT_8822B */
-
-#define BIT_SHIFT_FREERUN_CNT_8822B 0
-#define BIT_MASK_FREERUN_CNT_8822B 0xffffffffffffffffL
-#define BIT_FREERUN_CNT_8822B(x) \
- (((x) & BIT_MASK_FREERUN_CNT_8822B) << BIT_SHIFT_FREERUN_CNT_8822B)
-#define BIT_GET_FREERUN_CNT_8822B(x) \
- (((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B)
-
-/* 2 REG_ATIMWND1_V1_8822B */
-
-#define BIT_SHIFT_ATIMWND1_V1_8822B 0
-#define BIT_MASK_ATIMWND1_V1_8822B 0xff
-#define BIT_ATIMWND1_V1_8822B(x) \
- (((x) & BIT_MASK_ATIMWND1_V1_8822B) << BIT_SHIFT_ATIMWND1_V1_8822B)
-#define BIT_GET_ATIMWND1_V1_8822B(x) \
- (((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B)
-
-/* 2 REG_TBTT_PROHIBIT_INFRA_8822B */
-
-#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B 0
-#define BIT_MASK_TBTT_PROHIBIT_INFRA_8822B 0xff
-#define BIT_TBTT_PROHIBIT_INFRA_8822B(x) \
- (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) \
- << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B)
-#define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x) \
- (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) & \
- BIT_MASK_TBTT_PROHIBIT_INFRA_8822B)
-
-/* 2 REG_CTWND_8822B */
-
-#define BIT_SHIFT_CTWND_8822B 0
-#define BIT_MASK_CTWND_8822B 0xff
-#define BIT_CTWND_8822B(x) \
- (((x) & BIT_MASK_CTWND_8822B) << BIT_SHIFT_CTWND_8822B)
-#define BIT_GET_CTWND_8822B(x) \
- (((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B)
-
-/* 2 REG_BCNIVLCUNT_8822B */
-
-#define BIT_SHIFT_BCNIVLCUNT_8822B 0
-#define BIT_MASK_BCNIVLCUNT_8822B 0x7f
-#define BIT_BCNIVLCUNT_8822B(x) \
- (((x) & BIT_MASK_BCNIVLCUNT_8822B) << BIT_SHIFT_BCNIVLCUNT_8822B)
-#define BIT_GET_BCNIVLCUNT_8822B(x) \
- (((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B)
-
-/* 2 REG_BCNDROPCTRL_8822B */
-#define BIT_BEACON_DROP_EN_8822B BIT(7)
-
-#define BIT_SHIFT_BEACON_DROP_IVL_8822B 0
-#define BIT_MASK_BEACON_DROP_IVL_8822B 0x7f
-#define BIT_BEACON_DROP_IVL_8822B(x) \
- (((x) & BIT_MASK_BEACON_DROP_IVL_8822B) \
- << BIT_SHIFT_BEACON_DROP_IVL_8822B)
-#define BIT_GET_BEACON_DROP_IVL_8822B(x) \
- (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) & \
- BIT_MASK_BEACON_DROP_IVL_8822B)
-
-/* 2 REG_HGQ_TIMEOUT_PERIOD_8822B */
-
-#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B 0
-#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B 0xff
-#define BIT_HGQ_TIMEOUT_PERIOD_8822B(x) \
- (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) \
- << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B)
-#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x) \
- (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) & \
- BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B)
-
-/* 2 REG_TXCMD_TIMEOUT_PERIOD_8822B */
-
-#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B 0
-#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B 0xff
-#define BIT_TXCMD_TIMEOUT_PERIOD_8822B(x) \
- (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) \
- << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B)
-#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x) \
- (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) & \
- BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B)
-
-/* 2 REG_MISC_CTRL_8822B */
-#define BIT_DIS_TRX_CAL_BCN_8822B BIT(5)
-#define BIT_DIS_TX_CAL_TBTT_8822B BIT(4)
-#define BIT_EN_FREECNT_8822B BIT(3)
-#define BIT_BCN_AGGRESSION_8822B BIT(2)
-
-#define BIT_SHIFT_DIS_SECONDARY_CCA_8822B 0
-#define BIT_MASK_DIS_SECONDARY_CCA_8822B 0x3
-#define BIT_DIS_SECONDARY_CCA_8822B(x) \
- (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822B) \
- << BIT_SHIFT_DIS_SECONDARY_CCA_8822B)
-#define BIT_GET_DIS_SECONDARY_CCA_8822B(x) \
- (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) & \
- BIT_MASK_DIS_SECONDARY_CCA_8822B)
-
-/* 2 REG_BCN_CTRL_CLINT1_8822B */
-#define BIT_CLI1_DIS_RX_BSSID_FIT_8822B BIT(6)
-#define BIT_CLI1_DIS_TSF_UDT_8822B BIT(4)
-#define BIT_CLI1_EN_BCN_FUNCTION_8822B BIT(3)
-#define BIT_CLI1_EN_RXBCN_RPT_8822B BIT(2)
-#define BIT_CLI1_ENP2P_CTWINDOW_8822B BIT(1)
-#define BIT_CLI1_ENP2P_BCNQ_AREA_8822B BIT(0)
-
-/* 2 REG_BCN_CTRL_CLINT2_8822B */
-#define BIT_CLI2_DIS_RX_BSSID_FIT_8822B BIT(6)
-#define BIT_CLI2_DIS_TSF_UDT_8822B BIT(4)
-#define BIT_CLI2_EN_BCN_FUNCTION_8822B BIT(3)
-#define BIT_CLI2_EN_RXBCN_RPT_8822B BIT(2)
-#define BIT_CLI2_ENP2P_CTWINDOW_8822B BIT(1)
-#define BIT_CLI2_ENP2P_BCNQ_AREA_8822B BIT(0)
-
-/* 2 REG_BCN_CTRL_CLINT3_8822B */
-#define BIT_CLI3_DIS_RX_BSSID_FIT_8822B BIT(6)
-#define BIT_CLI3_DIS_TSF_UDT_8822B BIT(4)
-#define BIT_CLI3_EN_BCN_FUNCTION_8822B BIT(3)
-#define BIT_CLI3_EN_RXBCN_RPT_8822B BIT(2)
-#define BIT_CLI3_ENP2P_CTWINDOW_8822B BIT(1)
-#define BIT_CLI3_ENP2P_BCNQ_AREA_8822B BIT(0)
-
-/* 2 REG_EXTEND_CTRL_8822B */
-#define BIT_EN_TSFBIT32_RST_P2P2_8822B BIT(5)
-#define BIT_EN_TSFBIT32_RST_P2P1_8822B BIT(4)
-
-#define BIT_SHIFT_PORT_SEL_8822B 0
-#define BIT_MASK_PORT_SEL_8822B 0x7
-#define BIT_PORT_SEL_8822B(x) \
- (((x) & BIT_MASK_PORT_SEL_8822B) << BIT_SHIFT_PORT_SEL_8822B)
-#define BIT_GET_PORT_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B)
-
-/* 2 REG_P2PPS1_SPEC_STATE_8822B */
-#define BIT_P2P1_SPEC_POWER_STATE_8822B BIT(7)
-#define BIT_P2P1_SPEC_CTWINDOW_ON_8822B BIT(6)
-#define BIT_P2P1_SPEC_BCN_AREA_ON_8822B BIT(5)
-#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8822B BIT(4)
-#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8822B BIT(3)
-#define BIT_P2P1_SPEC_FORCE_DOZE1_8822B BIT(2)
-#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)
-#define BIT_P2P1_SPEC_FORCE_DOZE0_8822B BIT(0)
-
-/* 2 REG_P2PPS1_STATE_8822B */
-#define BIT_P2P1_POWER_STATE_8822B BIT(7)
-#define BIT_P2P1_CTWINDOW_ON_8822B BIT(6)
-#define BIT_P2P1_BEACON_AREA_ON_8822B BIT(5)
-#define BIT_P2P1_CTWIN_EARLY_DISTX_8822B BIT(4)
-#define BIT_P2P1_NOA1_OFF_PERIOD_8822B BIT(3)
-#define BIT_P2P1_FORCE_DOZE1_8822B BIT(2)
-#define BIT_P2P1_NOA0_OFF_PERIOD_8822B BIT(1)
-#define BIT_P2P1_FORCE_DOZE0_8822B BIT(0)
-
-/* 2 REG_P2PPS2_SPEC_STATE_8822B */
-#define BIT_P2P2_SPEC_POWER_STATE_8822B BIT(7)
-#define BIT_P2P2_SPEC_CTWINDOW_ON_8822B BIT(6)
-#define BIT_P2P2_SPEC_BCN_AREA_ON_8822B BIT(5)
-#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8822B BIT(4)
-#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8822B BIT(3)
-#define BIT_P2P2_SPEC_FORCE_DOZE1_8822B BIT(2)
-#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)
-#define BIT_P2P2_SPEC_FORCE_DOZE0_8822B BIT(0)
-
-/* 2 REG_P2PPS2_STATE_8822B */
-#define BIT_P2P2_POWER_STATE_8822B BIT(7)
-#define BIT_P2P2_CTWINDOW_ON_8822B BIT(6)
-#define BIT_P2P2_BEACON_AREA_ON_8822B BIT(5)
-#define BIT_P2P2_CTWIN_EARLY_DISTX_8822B BIT(4)
-#define BIT_P2P2_NOA1_OFF_PERIOD_8822B BIT(3)
-#define BIT_P2P2_FORCE_DOZE1_8822B BIT(2)
-#define BIT_P2P2_NOA0_OFF_PERIOD_8822B BIT(1)
-#define BIT_P2P2_FORCE_DOZE0_8822B BIT(0)
-
-/* 2 REG_PS_TIMER0_8822B */
-
-#define BIT_SHIFT_PSTIMER0_INT_8822B 5
-#define BIT_MASK_PSTIMER0_INT_8822B 0x7ffffff
-#define BIT_PSTIMER0_INT_8822B(x) \
- (((x) & BIT_MASK_PSTIMER0_INT_8822B) << BIT_SHIFT_PSTIMER0_INT_8822B)
-#define BIT_GET_PSTIMER0_INT_8822B(x) \
- (((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B)
-
-/* 2 REG_PS_TIMER1_8822B */
-
-#define BIT_SHIFT_PSTIMER1_INT_8822B 5
-#define BIT_MASK_PSTIMER1_INT_8822B 0x7ffffff
-#define BIT_PSTIMER1_INT_8822B(x) \
- (((x) & BIT_MASK_PSTIMER1_INT_8822B) << BIT_SHIFT_PSTIMER1_INT_8822B)
-#define BIT_GET_PSTIMER1_INT_8822B(x) \
- (((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B)
-
-/* 2 REG_PS_TIMER2_8822B */
-
-#define BIT_SHIFT_PSTIMER2_INT_8822B 5
-#define BIT_MASK_PSTIMER2_INT_8822B 0x7ffffff
-#define BIT_PSTIMER2_INT_8822B(x) \
- (((x) & BIT_MASK_PSTIMER2_INT_8822B) << BIT_SHIFT_PSTIMER2_INT_8822B)
-#define BIT_GET_PSTIMER2_INT_8822B(x) \
- (((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B)
-
-/* 2 REG_TBTT_CTN_AREA_8822B */
-
-#define BIT_SHIFT_TBTT_CTN_AREA_8822B 0
-#define BIT_MASK_TBTT_CTN_AREA_8822B 0xff
-#define BIT_TBTT_CTN_AREA_8822B(x) \
- (((x) & BIT_MASK_TBTT_CTN_AREA_8822B) << BIT_SHIFT_TBTT_CTN_AREA_8822B)
-#define BIT_GET_TBTT_CTN_AREA_8822B(x) \
- (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B)
-
-/* 2 REG_FORCE_BCN_IFS_8822B */
-
-#define BIT_SHIFT_FORCE_BCN_IFS_8822B 0
-#define BIT_MASK_FORCE_BCN_IFS_8822B 0xff
-#define BIT_FORCE_BCN_IFS_8822B(x) \
- (((x) & BIT_MASK_FORCE_BCN_IFS_8822B) << BIT_SHIFT_FORCE_BCN_IFS_8822B)
-#define BIT_GET_FORCE_BCN_IFS_8822B(x) \
- (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B)
-
-/* 2 REG_TXOP_MIN_8822B */
-
-#define BIT_SHIFT_TXOP_MIN_8822B 0
-#define BIT_MASK_TXOP_MIN_8822B 0x3fff
-#define BIT_TXOP_MIN_8822B(x) \
- (((x) & BIT_MASK_TXOP_MIN_8822B) << BIT_SHIFT_TXOP_MIN_8822B)
-#define BIT_GET_TXOP_MIN_8822B(x) \
- (((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B)
-
-/* 2 REG_PRE_BKF_TIME_8822B */
-
-#define BIT_SHIFT_PRE_BKF_TIME_8822B 0
-#define BIT_MASK_PRE_BKF_TIME_8822B 0xff
-#define BIT_PRE_BKF_TIME_8822B(x) \
- (((x) & BIT_MASK_PRE_BKF_TIME_8822B) << BIT_SHIFT_PRE_BKF_TIME_8822B)
-#define BIT_GET_PRE_BKF_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B)
-
-/* 2 REG_CROSS_TXOP_CTRL_8822B */
-#define BIT_DTIM_BYPASS_8822B BIT(2)
-#define BIT_RTS_NAV_TXOP_8822B BIT(1)
-#define BIT_NOT_CROSS_TXOP_8822B BIT(0)
-
-/* 2 REG_ATIMWND2_8822B */
-
-#define BIT_SHIFT_ATIMWND2_8822B 0
-#define BIT_MASK_ATIMWND2_8822B 0xff
-#define BIT_ATIMWND2_8822B(x) \
- (((x) & BIT_MASK_ATIMWND2_8822B) << BIT_SHIFT_ATIMWND2_8822B)
-#define BIT_GET_ATIMWND2_8822B(x) \
- (((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B)
-
-/* 2 REG_ATIMWND3_8822B */
-
-#define BIT_SHIFT_ATIMWND3_8822B 0
-#define BIT_MASK_ATIMWND3_8822B 0xff
-#define BIT_ATIMWND3_8822B(x) \
- (((x) & BIT_MASK_ATIMWND3_8822B) << BIT_SHIFT_ATIMWND3_8822B)
-#define BIT_GET_ATIMWND3_8822B(x) \
- (((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B)
-
-/* 2 REG_ATIMWND4_8822B */
-
-#define BIT_SHIFT_ATIMWND4_8822B 0
-#define BIT_MASK_ATIMWND4_8822B 0xff
-#define BIT_ATIMWND4_8822B(x) \
- (((x) & BIT_MASK_ATIMWND4_8822B) << BIT_SHIFT_ATIMWND4_8822B)
-#define BIT_GET_ATIMWND4_8822B(x) \
- (((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B)
-
-/* 2 REG_ATIMWND5_8822B */
-
-#define BIT_SHIFT_ATIMWND5_8822B 0
-#define BIT_MASK_ATIMWND5_8822B 0xff
-#define BIT_ATIMWND5_8822B(x) \
- (((x) & BIT_MASK_ATIMWND5_8822B) << BIT_SHIFT_ATIMWND5_8822B)
-#define BIT_GET_ATIMWND5_8822B(x) \
- (((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B)
-
-/* 2 REG_ATIMWND6_8822B */
-
-#define BIT_SHIFT_ATIMWND6_8822B 0
-#define BIT_MASK_ATIMWND6_8822B 0xff
-#define BIT_ATIMWND6_8822B(x) \
- (((x) & BIT_MASK_ATIMWND6_8822B) << BIT_SHIFT_ATIMWND6_8822B)
-#define BIT_GET_ATIMWND6_8822B(x) \
- (((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B)
-
-/* 2 REG_ATIMWND7_8822B */
-
-#define BIT_SHIFT_ATIMWND7_8822B 0
-#define BIT_MASK_ATIMWND7_8822B 0xff
-#define BIT_ATIMWND7_8822B(x) \
- (((x) & BIT_MASK_ATIMWND7_8822B) << BIT_SHIFT_ATIMWND7_8822B)
-#define BIT_GET_ATIMWND7_8822B(x) \
- (((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B)
-
-/* 2 REG_ATIMUGT_8822B */
-
-#define BIT_SHIFT_ATIM_URGENT_8822B 0
-#define BIT_MASK_ATIM_URGENT_8822B 0xff
-#define BIT_ATIM_URGENT_8822B(x) \
- (((x) & BIT_MASK_ATIM_URGENT_8822B) << BIT_SHIFT_ATIM_URGENT_8822B)
-#define BIT_GET_ATIM_URGENT_8822B(x) \
- (((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B)
-
-/* 2 REG_HIQ_NO_LMT_EN_8822B */
-#define BIT_HIQ_NO_LMT_EN_VAP7_8822B BIT(7)
-#define BIT_HIQ_NO_LMT_EN_VAP6_8822B BIT(6)
-#define BIT_HIQ_NO_LMT_EN_VAP5_8822B BIT(5)
-#define BIT_HIQ_NO_LMT_EN_VAP4_8822B BIT(4)
-#define BIT_HIQ_NO_LMT_EN_VAP3_8822B BIT(3)
-#define BIT_HIQ_NO_LMT_EN_VAP2_8822B BIT(2)
-#define BIT_HIQ_NO_LMT_EN_VAP1_8822B BIT(1)
-#define BIT_HIQ_NO_LMT_EN_ROOT_8822B BIT(0)
-
-/* 2 REG_DTIM_COUNTER_ROOT_8822B */
-
-#define BIT_SHIFT_DTIM_COUNT_ROOT_8822B 0
-#define BIT_MASK_DTIM_COUNT_ROOT_8822B 0xff
-#define BIT_DTIM_COUNT_ROOT_8822B(x) \
- (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822B) \
- << BIT_SHIFT_DTIM_COUNT_ROOT_8822B)
-#define BIT_GET_DTIM_COUNT_ROOT_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) & \
- BIT_MASK_DTIM_COUNT_ROOT_8822B)
-
-/* 2 REG_DTIM_COUNTER_VAP1_8822B */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP1_8822B 0
-#define BIT_MASK_DTIM_COUNT_VAP1_8822B 0xff
-#define BIT_DTIM_COUNT_VAP1_8822B(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822B) \
- << BIT_SHIFT_DTIM_COUNT_VAP1_8822B)
-#define BIT_GET_DTIM_COUNT_VAP1_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) & \
- BIT_MASK_DTIM_COUNT_VAP1_8822B)
-
-/* 2 REG_DTIM_COUNTER_VAP2_8822B */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP2_8822B 0
-#define BIT_MASK_DTIM_COUNT_VAP2_8822B 0xff
-#define BIT_DTIM_COUNT_VAP2_8822B(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822B) \
- << BIT_SHIFT_DTIM_COUNT_VAP2_8822B)
-#define BIT_GET_DTIM_COUNT_VAP2_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) & \
- BIT_MASK_DTIM_COUNT_VAP2_8822B)
-
-/* 2 REG_DTIM_COUNTER_VAP3_8822B */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP3_8822B 0
-#define BIT_MASK_DTIM_COUNT_VAP3_8822B 0xff
-#define BIT_DTIM_COUNT_VAP3_8822B(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822B) \
- << BIT_SHIFT_DTIM_COUNT_VAP3_8822B)
-#define BIT_GET_DTIM_COUNT_VAP3_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) & \
- BIT_MASK_DTIM_COUNT_VAP3_8822B)
-
-/* 2 REG_DTIM_COUNTER_VAP4_8822B */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP4_8822B 0
-#define BIT_MASK_DTIM_COUNT_VAP4_8822B 0xff
-#define BIT_DTIM_COUNT_VAP4_8822B(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822B) \
- << BIT_SHIFT_DTIM_COUNT_VAP4_8822B)
-#define BIT_GET_DTIM_COUNT_VAP4_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) & \
- BIT_MASK_DTIM_COUNT_VAP4_8822B)
-
-/* 2 REG_DTIM_COUNTER_VAP5_8822B */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP5_8822B 0
-#define BIT_MASK_DTIM_COUNT_VAP5_8822B 0xff
-#define BIT_DTIM_COUNT_VAP5_8822B(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822B) \
- << BIT_SHIFT_DTIM_COUNT_VAP5_8822B)
-#define BIT_GET_DTIM_COUNT_VAP5_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) & \
- BIT_MASK_DTIM_COUNT_VAP5_8822B)
-
-/* 2 REG_DTIM_COUNTER_VAP6_8822B */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP6_8822B 0
-#define BIT_MASK_DTIM_COUNT_VAP6_8822B 0xff
-#define BIT_DTIM_COUNT_VAP6_8822B(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822B) \
- << BIT_SHIFT_DTIM_COUNT_VAP6_8822B)
-#define BIT_GET_DTIM_COUNT_VAP6_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) & \
- BIT_MASK_DTIM_COUNT_VAP6_8822B)
-
-/* 2 REG_DTIM_COUNTER_VAP7_8822B */
-
-#define BIT_SHIFT_DTIM_COUNT_VAP7_8822B 0
-#define BIT_MASK_DTIM_COUNT_VAP7_8822B 0xff
-#define BIT_DTIM_COUNT_VAP7_8822B(x) \
- (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822B) \
- << BIT_SHIFT_DTIM_COUNT_VAP7_8822B)
-#define BIT_GET_DTIM_COUNT_VAP7_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) & \
- BIT_MASK_DTIM_COUNT_VAP7_8822B)
-
-/* 2 REG_DIS_ATIM_8822B */
-#define BIT_DIS_ATIM_VAP7_8822B BIT(7)
-#define BIT_DIS_ATIM_VAP6_8822B BIT(6)
-#define BIT_DIS_ATIM_VAP5_8822B BIT(5)
-#define BIT_DIS_ATIM_VAP4_8822B BIT(4)
-#define BIT_DIS_ATIM_VAP3_8822B BIT(3)
-#define BIT_DIS_ATIM_VAP2_8822B BIT(2)
-#define BIT_DIS_ATIM_VAP1_8822B BIT(1)
-#define BIT_DIS_ATIM_ROOT_8822B BIT(0)
-
-/* 2 REG_EARLY_128US_8822B */
-
-#define BIT_SHIFT_TSFT_SEL_TIMER1_8822B 3
-#define BIT_MASK_TSFT_SEL_TIMER1_8822B 0x7
-#define BIT_TSFT_SEL_TIMER1_8822B(x) \
- (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822B) \
- << BIT_SHIFT_TSFT_SEL_TIMER1_8822B)
-#define BIT_GET_TSFT_SEL_TIMER1_8822B(x) \
- (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) & \
- BIT_MASK_TSFT_SEL_TIMER1_8822B)
-
-#define BIT_SHIFT_EARLY_128US_8822B 0
-#define BIT_MASK_EARLY_128US_8822B 0x7
-#define BIT_EARLY_128US_8822B(x) \
- (((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B)
-#define BIT_GET_EARLY_128US_8822B(x) \
- (((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B)
-
-/* 2 REG_P2PPS1_CTRL_8822B */
-#define BIT_P2P1_CTW_ALLSTASLEEP_8822B BIT(7)
-#define BIT_P2P1_OFF_DISTX_EN_8822B BIT(6)
-#define BIT_P2P1_PWR_MGT_EN_8822B BIT(5)
-#define BIT_P2P1_NOA1_EN_8822B BIT(2)
-#define BIT_P2P1_NOA0_EN_8822B BIT(1)
-
-/* 2 REG_P2PPS2_CTRL_8822B */
-#define BIT_P2P2_CTW_ALLSTASLEEP_8822B BIT(7)
-#define BIT_P2P2_OFF_DISTX_EN_8822B BIT(6)
-#define BIT_P2P2_PWR_MGT_EN_8822B BIT(5)
-#define BIT_P2P2_NOA1_EN_8822B BIT(2)
-#define BIT_P2P2_NOA0_EN_8822B BIT(1)
-
-/* 2 REG_TIMER0_SRC_SEL_8822B */
-
-#define BIT_SHIFT_SYNC_CLI_SEL_8822B 4
-#define BIT_MASK_SYNC_CLI_SEL_8822B 0x7
-#define BIT_SYNC_CLI_SEL_8822B(x) \
- (((x) & BIT_MASK_SYNC_CLI_SEL_8822B) << BIT_SHIFT_SYNC_CLI_SEL_8822B)
-#define BIT_GET_SYNC_CLI_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B)
-
-#define BIT_SHIFT_TSFT_SEL_TIMER0_8822B 0
-#define BIT_MASK_TSFT_SEL_TIMER0_8822B 0x7
-#define BIT_TSFT_SEL_TIMER0_8822B(x) \
- (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B) \
- << BIT_SHIFT_TSFT_SEL_TIMER0_8822B)
-#define BIT_GET_TSFT_SEL_TIMER0_8822B(x) \
- (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) & \
- BIT_MASK_TSFT_SEL_TIMER0_8822B)
-
-/* 2 REG_NOA_UNIT_SEL_8822B */
-
-#define BIT_SHIFT_NOA_UNIT2_SEL_8822B 8
-#define BIT_MASK_NOA_UNIT2_SEL_8822B 0x7
-#define BIT_NOA_UNIT2_SEL_8822B(x) \
- (((x) & BIT_MASK_NOA_UNIT2_SEL_8822B) << BIT_SHIFT_NOA_UNIT2_SEL_8822B)
-#define BIT_GET_NOA_UNIT2_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B)
-
-#define BIT_SHIFT_NOA_UNIT1_SEL_8822B 4
-#define BIT_MASK_NOA_UNIT1_SEL_8822B 0x7
-#define BIT_NOA_UNIT1_SEL_8822B(x) \
- (((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B)
-#define BIT_GET_NOA_UNIT1_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B)
-
-#define BIT_SHIFT_NOA_UNIT0_SEL_8822B 0
-#define BIT_MASK_NOA_UNIT0_SEL_8822B 0x7
-#define BIT_NOA_UNIT0_SEL_8822B(x) \
- (((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B)
-#define BIT_GET_NOA_UNIT0_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B)
-
-/* 2 REG_P2POFF_DIS_TXTIME_8822B */
-
-#define BIT_SHIFT_P2POFF_DIS_TXTIME_8822B 0
-#define BIT_MASK_P2POFF_DIS_TXTIME_8822B 0xff
-#define BIT_P2POFF_DIS_TXTIME_8822B(x) \
- (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) \
- << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B)
-#define BIT_GET_P2POFF_DIS_TXTIME_8822B(x) \
- (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) & \
- BIT_MASK_P2POFF_DIS_TXTIME_8822B)
-
-/* 2 REG_MBSSID_BCN_SPACE2_8822B */
-
-#define BIT_SHIFT_BCN_SPACE_CLINT2_8822B 16
-#define BIT_MASK_BCN_SPACE_CLINT2_8822B 0xfff
-#define BIT_BCN_SPACE_CLINT2_8822B(x) \
- (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822B) \
- << BIT_SHIFT_BCN_SPACE_CLINT2_8822B)
-#define BIT_GET_BCN_SPACE_CLINT2_8822B(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) & \
- BIT_MASK_BCN_SPACE_CLINT2_8822B)
-
-#define BIT_SHIFT_BCN_SPACE_CLINT1_8822B 0
-#define BIT_MASK_BCN_SPACE_CLINT1_8822B 0xfff
-#define BIT_BCN_SPACE_CLINT1_8822B(x) \
- (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B) \
- << BIT_SHIFT_BCN_SPACE_CLINT1_8822B)
-#define BIT_GET_BCN_SPACE_CLINT1_8822B(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) & \
- BIT_MASK_BCN_SPACE_CLINT1_8822B)
-
-/* 2 REG_MBSSID_BCN_SPACE3_8822B */
-
-#define BIT_SHIFT_SUB_BCN_SPACE_8822B 16
-#define BIT_MASK_SUB_BCN_SPACE_8822B 0xff
-#define BIT_SUB_BCN_SPACE_8822B(x) \
- (((x) & BIT_MASK_SUB_BCN_SPACE_8822B) << BIT_SHIFT_SUB_BCN_SPACE_8822B)
-#define BIT_GET_SUB_BCN_SPACE_8822B(x) \
- (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B)
-
-#define BIT_SHIFT_BCN_SPACE_CLINT3_8822B 0
-#define BIT_MASK_BCN_SPACE_CLINT3_8822B 0xfff
-#define BIT_BCN_SPACE_CLINT3_8822B(x) \
- (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B) \
- << BIT_SHIFT_BCN_SPACE_CLINT3_8822B)
-#define BIT_GET_BCN_SPACE_CLINT3_8822B(x) \
- (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) & \
- BIT_MASK_BCN_SPACE_CLINT3_8822B)
-
-/* 2 REG_ACMHWCTRL_8822B */
-#define BIT_BEQ_ACM_STATUS_8822B BIT(7)
-#define BIT_VIQ_ACM_STATUS_8822B BIT(6)
-#define BIT_VOQ_ACM_STATUS_8822B BIT(5)
-#define BIT_BEQ_ACM_EN_8822B BIT(3)
-#define BIT_VIQ_ACM_EN_8822B BIT(2)
-#define BIT_VOQ_ACM_EN_8822B BIT(1)
-#define BIT_ACMHWEN_8822B BIT(0)
-
-/* 2 REG_ACMRSTCTRL_8822B */
-#define BIT_BE_ACM_RESET_USED_TIME_8822B BIT(2)
-#define BIT_VI_ACM_RESET_USED_TIME_8822B BIT(1)
-#define BIT_VO_ACM_RESET_USED_TIME_8822B BIT(0)
-
-/* 2 REG_ACMAVG_8822B */
-
-#define BIT_SHIFT_AVGPERIOD_8822B 0
-#define BIT_MASK_AVGPERIOD_8822B 0xffff
-#define BIT_AVGPERIOD_8822B(x) \
- (((x) & BIT_MASK_AVGPERIOD_8822B) << BIT_SHIFT_AVGPERIOD_8822B)
-#define BIT_GET_AVGPERIOD_8822B(x) \
- (((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B)
-
-/* 2 REG_VO_ADMTIME_8822B */
-
-#define BIT_SHIFT_VO_ADMITTED_TIME_8822B 0
-#define BIT_MASK_VO_ADMITTED_TIME_8822B 0xffff
-#define BIT_VO_ADMITTED_TIME_8822B(x) \
- (((x) & BIT_MASK_VO_ADMITTED_TIME_8822B) \
- << BIT_SHIFT_VO_ADMITTED_TIME_8822B)
-#define BIT_GET_VO_ADMITTED_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) & \
- BIT_MASK_VO_ADMITTED_TIME_8822B)
-
-/* 2 REG_VI_ADMTIME_8822B */
-
-#define BIT_SHIFT_VI_ADMITTED_TIME_8822B 0
-#define BIT_MASK_VI_ADMITTED_TIME_8822B 0xffff
-#define BIT_VI_ADMITTED_TIME_8822B(x) \
- (((x) & BIT_MASK_VI_ADMITTED_TIME_8822B) \
- << BIT_SHIFT_VI_ADMITTED_TIME_8822B)
-#define BIT_GET_VI_ADMITTED_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) & \
- BIT_MASK_VI_ADMITTED_TIME_8822B)
-
-/* 2 REG_BE_ADMTIME_8822B */
-
-#define BIT_SHIFT_BE_ADMITTED_TIME_8822B 0
-#define BIT_MASK_BE_ADMITTED_TIME_8822B 0xffff
-#define BIT_BE_ADMITTED_TIME_8822B(x) \
- (((x) & BIT_MASK_BE_ADMITTED_TIME_8822B) \
- << BIT_SHIFT_BE_ADMITTED_TIME_8822B)
-#define BIT_GET_BE_ADMITTED_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) & \
- BIT_MASK_BE_ADMITTED_TIME_8822B)
-
-/* 2 REG_EDCA_RANDOM_GEN_8822B */
-
-#define BIT_SHIFT_RANDOM_GEN_8822B 0
-#define BIT_MASK_RANDOM_GEN_8822B 0xffffff
-#define BIT_RANDOM_GEN_8822B(x) \
- (((x) & BIT_MASK_RANDOM_GEN_8822B) << BIT_SHIFT_RANDOM_GEN_8822B)
-#define BIT_GET_RANDOM_GEN_8822B(x) \
- (((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B)
-
-/* 2 REG_TXCMD_NOA_SEL_8822B */
-
-#define BIT_SHIFT_NOA_SEL_8822B 4
-#define BIT_MASK_NOA_SEL_8822B 0x7
-#define BIT_NOA_SEL_8822B(x) \
- (((x) & BIT_MASK_NOA_SEL_8822B) << BIT_SHIFT_NOA_SEL_8822B)
-#define BIT_GET_NOA_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_NOA_SEL_8822B) & BIT_MASK_NOA_SEL_8822B)
-
-#define BIT_SHIFT_TXCMD_SEG_SEL_8822B 0
-#define BIT_MASK_TXCMD_SEG_SEL_8822B 0xf
-#define BIT_TXCMD_SEG_SEL_8822B(x) \
- (((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B)
-#define BIT_GET_TXCMD_SEG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B)
-
-/* 2 REG_NOA_PARAM_8822B */
-
-#define BIT_SHIFT_NOA_COUNT_8822B (96 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_COUNT_8822B 0xff
-#define BIT_NOA_COUNT_8822B(x) \
- (((x) & BIT_MASK_NOA_COUNT_8822B) << BIT_SHIFT_NOA_COUNT_8822B)
-#define BIT_GET_NOA_COUNT_8822B(x) \
- (((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B)
-
-#define BIT_SHIFT_NOA_START_TIME_8822B (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_START_TIME_8822B 0xffffffffL
-#define BIT_NOA_START_TIME_8822B(x) \
- (((x) & BIT_MASK_NOA_START_TIME_8822B) \
- << BIT_SHIFT_NOA_START_TIME_8822B)
-#define BIT_GET_NOA_START_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_NOA_START_TIME_8822B) & \
- BIT_MASK_NOA_START_TIME_8822B)
-
-#define BIT_SHIFT_NOA_INTERVAL_8822B (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_INTERVAL_8822B 0xffffffffL
-#define BIT_NOA_INTERVAL_8822B(x) \
- (((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B)
-#define BIT_GET_NOA_INTERVAL_8822B(x) \
- (((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B)
-
-#define BIT_SHIFT_NOA_DURATION_8822B 0
-#define BIT_MASK_NOA_DURATION_8822B 0xffffffffL
-#define BIT_NOA_DURATION_8822B(x) \
- (((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B)
-#define BIT_GET_NOA_DURATION_8822B(x) \
- (((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B)
-
-/* 2 REG_P2P_RST_8822B */
-#define BIT_P2P2_PWR_RST1_8822B BIT(5)
-#define BIT_P2P2_PWR_RST0_8822B BIT(4)
-#define BIT_P2P1_PWR_RST1_8822B BIT(3)
-#define BIT_P2P1_PWR_RST0_8822B BIT(2)
-#define BIT_P2P_PWR_RST1_V1_8822B BIT(1)
-#define BIT_P2P_PWR_RST0_V1_8822B BIT(0)
-
-/* 2 REG_SCHEDULER_RST_8822B */
-#define BIT_SYNC_CLI_8822B BIT(1)
-#define BIT_SCHEDULER_RST_V1_8822B BIT(0)
-
-/* 2 REG_SCH_TXCMD_8822B */
-
-#define BIT_SHIFT_SCH_TXCMD_8822B 0
-#define BIT_MASK_SCH_TXCMD_8822B 0xffffffffL
-#define BIT_SCH_TXCMD_8822B(x) \
- (((x) & BIT_MASK_SCH_TXCMD_8822B) << BIT_SHIFT_SCH_TXCMD_8822B)
-#define BIT_GET_SCH_TXCMD_8822B(x) \
- (((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B)
-
-/* 2 REG_PAGE5_DUMMY_8822B */
-
-/* 2 REG_CPUMGQ_TX_TIMER_8822B */
-
-#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B 0
-#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B 0xffffffffL
-#define BIT_CPUMGQ_TX_TIMER_V1_8822B(x) \
- (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) \
- << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B)
-#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x) \
- (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) & \
- BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B)
-
-/* 2 REG_PS_TIMER_A_8822B */
-
-#define BIT_SHIFT_PS_TIMER_A_V1_8822B 0
-#define BIT_MASK_PS_TIMER_A_V1_8822B 0xffffffffL
-#define BIT_PS_TIMER_A_V1_8822B(x) \
- (((x) & BIT_MASK_PS_TIMER_A_V1_8822B) << BIT_SHIFT_PS_TIMER_A_V1_8822B)
-#define BIT_GET_PS_TIMER_A_V1_8822B(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B)
-
-/* 2 REG_PS_TIMER_B_8822B */
-
-#define BIT_SHIFT_PS_TIMER_B_V1_8822B 0
-#define BIT_MASK_PS_TIMER_B_V1_8822B 0xffffffffL
-#define BIT_PS_TIMER_B_V1_8822B(x) \
- (((x) & BIT_MASK_PS_TIMER_B_V1_8822B) << BIT_SHIFT_PS_TIMER_B_V1_8822B)
-#define BIT_GET_PS_TIMER_B_V1_8822B(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B)
-
-/* 2 REG_PS_TIMER_C_8822B */
-
-#define BIT_SHIFT_PS_TIMER_C_V1_8822B 0
-#define BIT_MASK_PS_TIMER_C_V1_8822B 0xffffffffL
-#define BIT_PS_TIMER_C_V1_8822B(x) \
- (((x) & BIT_MASK_PS_TIMER_C_V1_8822B) << BIT_SHIFT_PS_TIMER_C_V1_8822B)
-#define BIT_GET_PS_TIMER_C_V1_8822B(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B)
-
-/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B */
-#define BIT_CPUMGQ_TIMER_EN_8822B BIT(31)
-#define BIT_CPUMGQ_TX_EN_8822B BIT(28)
-
-#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B 24
-#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B 0x7
-#define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x) \
- (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) \
- << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B)
-#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) & \
- BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B)
-
-#define BIT_PS_TIMER_C_EN_8822B BIT(23)
-
-#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B 16
-#define BIT_MASK_PS_TIMER_C_TSF_SEL_8822B 0x7
-#define BIT_PS_TIMER_C_TSF_SEL_8822B(x) \
- (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) \
- << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B)
-#define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) & \
- BIT_MASK_PS_TIMER_C_TSF_SEL_8822B)
-
-#define BIT_PS_TIMER_B_EN_8822B BIT(15)
-
-#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B 8
-#define BIT_MASK_PS_TIMER_B_TSF_SEL_8822B 0x7
-#define BIT_PS_TIMER_B_TSF_SEL_8822B(x) \
- (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) \
- << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B)
-#define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) & \
- BIT_MASK_PS_TIMER_B_TSF_SEL_8822B)
-
-#define BIT_PS_TIMER_A_EN_8822B BIT(7)
-
-#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B 0
-#define BIT_MASK_PS_TIMER_A_TSF_SEL_8822B 0x7
-#define BIT_PS_TIMER_A_TSF_SEL_8822B(x) \
- (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) \
- << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B)
-#define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) & \
- BIT_MASK_PS_TIMER_A_TSF_SEL_8822B)
-
-/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822B */
-
-#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B 0
-#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B 0xff
-#define BIT_CPUMGQ_TX_TIMER_EARLY_8822B(x) \
- (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) \
- << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B)
-#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x) \
- (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) & \
- BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B)
-
-/* 2 REG_PS_TIMER_A_EARLY_8822B */
-
-#define BIT_SHIFT_PS_TIMER_A_EARLY_8822B 0
-#define BIT_MASK_PS_TIMER_A_EARLY_8822B 0xff
-#define BIT_PS_TIMER_A_EARLY_8822B(x) \
- (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822B) \
- << BIT_SHIFT_PS_TIMER_A_EARLY_8822B)
-#define BIT_GET_PS_TIMER_A_EARLY_8822B(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) & \
- BIT_MASK_PS_TIMER_A_EARLY_8822B)
-
-/* 2 REG_PS_TIMER_B_EARLY_8822B */
-
-#define BIT_SHIFT_PS_TIMER_B_EARLY_8822B 0
-#define BIT_MASK_PS_TIMER_B_EARLY_8822B 0xff
-#define BIT_PS_TIMER_B_EARLY_8822B(x) \
- (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822B) \
- << BIT_SHIFT_PS_TIMER_B_EARLY_8822B)
-#define BIT_GET_PS_TIMER_B_EARLY_8822B(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) & \
- BIT_MASK_PS_TIMER_B_EARLY_8822B)
-
-/* 2 REG_PS_TIMER_C_EARLY_8822B */
-
-#define BIT_SHIFT_PS_TIMER_C_EARLY_8822B 0
-#define BIT_MASK_PS_TIMER_C_EARLY_8822B 0xff
-#define BIT_PS_TIMER_C_EARLY_8822B(x) \
- (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822B) \
- << BIT_SHIFT_PS_TIMER_C_EARLY_8822B)
-#define BIT_GET_PS_TIMER_C_EARLY_8822B(x) \
- (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) & \
- BIT_MASK_PS_TIMER_C_EARLY_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_BWOPMODE_8822B (BW OPERATION MODE REGISTER) */
-
-/* 2 REG_WMAC_FWPKT_CR_8822B */
-#define BIT_FWEN_8822B BIT(7)
-#define BIT_PHYSTS_PKT_CTRL_8822B BIT(6)
-#define BIT_APPHDR_MIDSRCH_FAIL_8822B BIT(4)
-#define BIT_FWPARSING_EN_8822B BIT(3)
-
-#define BIT_SHIFT_APPEND_MHDR_LEN_8822B 0
-#define BIT_MASK_APPEND_MHDR_LEN_8822B 0x7
-#define BIT_APPEND_MHDR_LEN_8822B(x) \
- (((x) & BIT_MASK_APPEND_MHDR_LEN_8822B) \
- << BIT_SHIFT_APPEND_MHDR_LEN_8822B)
-#define BIT_GET_APPEND_MHDR_LEN_8822B(x) \
- (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) & \
- BIT_MASK_APPEND_MHDR_LEN_8822B)
-
-/* 2 REG_WMAC_CR_8822B (WMAC CR AND APSD CONTROL REGISTER) */
-#define BIT_IC_MACPHY_M_8822B BIT(0)
-
-/* 2 REG_TCR_8822B (TRANSMISSION CONFIGURATION REGISTER) */
-#define BIT_WMAC_EN_RTS_ADDR_8822B BIT(31)
-#define BIT_WMAC_DISABLE_CCK_8822B BIT(30)
-#define BIT_WMAC_RAW_LEN_8822B BIT(29)
-#define BIT_WMAC_NOTX_IN_RXNDP_8822B BIT(28)
-#define BIT_WMAC_EN_EOF_8822B BIT(27)
-#define BIT_WMAC_BF_SEL_8822B BIT(26)
-#define BIT_WMAC_ANTMODE_SEL_8822B BIT(25)
-#define BIT_WMAC_TCRPWRMGT_HWCTL_8822B BIT(24)
-#define BIT_WMAC_SMOOTH_VAL_8822B BIT(23)
-#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8822B BIT(20)
-#define BIT_WMAC_TCR_EN_20MST_8822B BIT(19)
-#define BIT_WMAC_DIS_SIGTA_8822B BIT(18)
-#define BIT_WMAC_DIS_A2B0_8822B BIT(17)
-#define BIT_WMAC_MSK_SIGBCRC_8822B BIT(16)
-#define BIT_WMAC_TCR_ERRSTEN_3_8822B BIT(15)
-#define BIT_WMAC_TCR_ERRSTEN_2_8822B BIT(14)
-#define BIT_WMAC_TCR_ERRSTEN_1_8822B BIT(13)
-#define BIT_WMAC_TCR_ERRSTEN_0_8822B BIT(12)
-#define BIT_WMAC_TCR_TXSK_PERPKT_8822B BIT(11)
-#define BIT_ICV_8822B BIT(10)
-#define BIT_CFEND_FORMAT_8822B BIT(9)
-#define BIT_CRC_8822B BIT(8)
-#define BIT_PWRBIT_OW_EN_8822B BIT(7)
-#define BIT_PWR_ST_8822B BIT(6)
-#define BIT_WMAC_TCR_UPD_TIMIE_8822B BIT(5)
-#define BIT_WMAC_TCR_UPD_HGQMD_8822B BIT(4)
-#define BIT_VHTSIGA1_TXPS_8822B BIT(3)
-#define BIT_PAD_SEL_8822B BIT(2)
-#define BIT_DIS_GCLK_8822B BIT(1)
-
-/* 2 REG_RCR_8822B (RECEIVE CONFIGURATION REGISTER) */
-#define BIT_APP_FCS_8822B BIT(31)
-#define BIT_APP_MIC_8822B BIT(30)
-#define BIT_APP_ICV_8822B BIT(29)
-#define BIT_APP_PHYSTS_8822B BIT(28)
-#define BIT_APP_BASSN_8822B BIT(27)
-#define BIT_VHT_DACK_8822B BIT(26)
-#define BIT_TCPOFLD_EN_8822B BIT(25)
-#define BIT_ENMBID_8822B BIT(24)
-#define BIT_LSIGEN_8822B BIT(23)
-#define BIT_MFBEN_8822B BIT(22)
-#define BIT_DISCHKPPDLLEN_8822B BIT(21)
-#define BIT_PKTCTL_DLEN_8822B BIT(20)
-#define BIT_TIM_PARSER_EN_8822B BIT(18)
-#define BIT_BC_MD_EN_8822B BIT(17)
-#define BIT_UC_MD_EN_8822B BIT(16)
-#define BIT_RXSK_PERPKT_8822B BIT(15)
-#define BIT_HTC_LOC_CTRL_8822B BIT(14)
-#define BIT_RPFM_CAM_ENABLE_8822B BIT(12)
-#define BIT_TA_BCN_8822B BIT(11)
-#define BIT_DISDECMYPKT_8822B BIT(10)
-#define BIT_AICV_8822B BIT(9)
-#define BIT_ACRC32_8822B BIT(8)
-#define BIT_CBSSID_BCN_8822B BIT(7)
-#define BIT_CBSSID_DATA_8822B BIT(6)
-#define BIT_APWRMGT_8822B BIT(5)
-#define BIT_ADD3_8822B BIT(4)
-#define BIT_AB_8822B BIT(3)
-#define BIT_AM_8822B BIT(2)
-#define BIT_APM_8822B BIT(1)
-#define BIT_AAP_8822B BIT(0)
-
-/* 2 REG_RX_DRVINFO_SZ_8822B (RX DRIVER INFO SIZE REGISTER) */
-#define BIT_PHYSTS_PER_PKT_MODE_8822B BIT(7)
-
-#define BIT_SHIFT_DRVINFO_SZ_V1_8822B 0
-#define BIT_MASK_DRVINFO_SZ_V1_8822B 0xf
-#define BIT_DRVINFO_SZ_V1_8822B(x) \
- (((x) & BIT_MASK_DRVINFO_SZ_V1_8822B) << BIT_SHIFT_DRVINFO_SZ_V1_8822B)
-#define BIT_GET_DRVINFO_SZ_V1_8822B(x) \
- (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B)
-
-/* 2 REG_RX_DLK_TIME_8822B (RX DEADLOCK TIME REGISTER) */
-
-#define BIT_SHIFT_RX_DLK_TIME_8822B 0
-#define BIT_MASK_RX_DLK_TIME_8822B 0xff
-#define BIT_RX_DLK_TIME_8822B(x) \
- (((x) & BIT_MASK_RX_DLK_TIME_8822B) << BIT_SHIFT_RX_DLK_TIME_8822B)
-#define BIT_GET_RX_DLK_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B)
-
-/* 2 REG_RX_PKT_LIMIT_8822B (RX PACKET LENGTH LIMIT REGISTER) */
-
-#define BIT_SHIFT_RXPKTLMT_8822B 0
-#define BIT_MASK_RXPKTLMT_8822B 0x3f
-#define BIT_RXPKTLMT_8822B(x) \
- (((x) & BIT_MASK_RXPKTLMT_8822B) << BIT_SHIFT_RXPKTLMT_8822B)
-#define BIT_GET_RXPKTLMT_8822B(x) \
- (((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B)
-
-/* 2 REG_MACID_8822B (MAC ID REGISTER) */
-
-#define BIT_SHIFT_MACID_8822B 0
-#define BIT_MASK_MACID_8822B 0xffffffffffffL
-#define BIT_MACID_8822B(x) \
- (((x) & BIT_MASK_MACID_8822B) << BIT_SHIFT_MACID_8822B)
-#define BIT_GET_MACID_8822B(x) \
- (((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B)
-
-/* 2 REG_BSSID_8822B (BSSID REGISTER) */
-
-#define BIT_SHIFT_BSSID_8822B 0
-#define BIT_MASK_BSSID_8822B 0xffffffffffffL
-#define BIT_BSSID_8822B(x) \
- (((x) & BIT_MASK_BSSID_8822B) << BIT_SHIFT_BSSID_8822B)
-#define BIT_GET_BSSID_8822B(x) \
- (((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B)
-
-/* 2 REG_MAR_8822B (MULTICAST ADDRESS REGISTER) */
-
-#define BIT_SHIFT_MAR_8822B 0
-#define BIT_MASK_MAR_8822B 0xffffffffffffffffL
-#define BIT_MAR_8822B(x) (((x) & BIT_MASK_MAR_8822B) << BIT_SHIFT_MAR_8822B)
-#define BIT_GET_MAR_8822B(x) (((x) >> BIT_SHIFT_MAR_8822B) & BIT_MASK_MAR_8822B)
-
-/* 2 REG_MBIDCAMCFG_1_8822B (MBSSID CAM CONFIGURATION REGISTER) */
-
-#define BIT_SHIFT_MBIDCAM_RWDATA_L_8822B 0
-#define BIT_MASK_MBIDCAM_RWDATA_L_8822B 0xffffffffL
-#define BIT_MBIDCAM_RWDATA_L_8822B(x) \
- (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) \
- << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B)
-#define BIT_GET_MBIDCAM_RWDATA_L_8822B(x) \
- (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) & \
- BIT_MASK_MBIDCAM_RWDATA_L_8822B)
-
-/* 2 REG_MBIDCAMCFG_2_8822B (MBSSID CAM CONFIGURATION REGISTER) */
-#define BIT_MBIDCAM_POLL_8822B BIT(31)
-#define BIT_MBIDCAM_WT_EN_8822B BIT(30)
-
-#define BIT_SHIFT_MBIDCAM_ADDR_8822B 24
-#define BIT_MASK_MBIDCAM_ADDR_8822B 0x1f
-#define BIT_MBIDCAM_ADDR_8822B(x) \
- (((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B)
-#define BIT_GET_MBIDCAM_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B)
-
-#define BIT_MBIDCAM_VALID_8822B BIT(23)
-#define BIT_LSIC_TXOP_EN_8822B BIT(17)
-#define BIT_CTS_EN_8822B BIT(16)
-
-#define BIT_SHIFT_MBIDCAM_RWDATA_H_8822B 0
-#define BIT_MASK_MBIDCAM_RWDATA_H_8822B 0xffff
-#define BIT_MBIDCAM_RWDATA_H_8822B(x) \
- (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) \
- << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B)
-#define BIT_GET_MBIDCAM_RWDATA_H_8822B(x) \
- (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) & \
- BIT_MASK_MBIDCAM_RWDATA_H_8822B)
-
-/* 2 REG_ZLD_NUM_8822B */
-
-#define BIT_SHIFT_ZLD_NUM_8822B 0
-#define BIT_MASK_ZLD_NUM_8822B 0xff
-#define BIT_ZLD_NUM_8822B(x) \
- (((x) & BIT_MASK_ZLD_NUM_8822B) << BIT_SHIFT_ZLD_NUM_8822B)
-#define BIT_GET_ZLD_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B)
-
-/* 2 REG_UDF_THSD_8822B */
-
-#define BIT_SHIFT_UDF_THSD_8822B 0
-#define BIT_MASK_UDF_THSD_8822B 0xff
-#define BIT_UDF_THSD_8822B(x) \
- (((x) & BIT_MASK_UDF_THSD_8822B) << BIT_SHIFT_UDF_THSD_8822B)
-#define BIT_GET_UDF_THSD_8822B(x) \
- (((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B)
-
-/* 2 REG_WMAC_TCR_TSFT_OFS_8822B */
-
-#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B 0
-#define BIT_MASK_WMAC_TCR_TSFT_OFS_8822B 0xffff
-#define BIT_WMAC_TCR_TSFT_OFS_8822B(x) \
- (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) \
- << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B)
-#define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) & \
- BIT_MASK_WMAC_TCR_TSFT_OFS_8822B)
-
-/* 2 REG_MCU_TEST_2_V1_8822B */
-
-#define BIT_SHIFT_MCU_RSVD_2_V1_8822B 0
-#define BIT_MASK_MCU_RSVD_2_V1_8822B 0xffff
-#define BIT_MCU_RSVD_2_V1_8822B(x) \
- (((x) & BIT_MASK_MCU_RSVD_2_V1_8822B) << BIT_SHIFT_MCU_RSVD_2_V1_8822B)
-#define BIT_GET_MCU_RSVD_2_V1_8822B(x) \
- (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B)
-
-/* 2 REG_WMAC_TXTIMEOUT_8822B */
-
-#define BIT_SHIFT_WMAC_TXTIMEOUT_8822B 0
-#define BIT_MASK_WMAC_TXTIMEOUT_8822B 0xff
-#define BIT_WMAC_TXTIMEOUT_8822B(x) \
- (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822B) \
- << BIT_SHIFT_WMAC_TXTIMEOUT_8822B)
-#define BIT_GET_WMAC_TXTIMEOUT_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) & \
- BIT_MASK_WMAC_TXTIMEOUT_8822B)
-
-/* 2 REG_STMP_THSD_8822B */
-
-#define BIT_SHIFT_STMP_THSD_8822B 0
-#define BIT_MASK_STMP_THSD_8822B 0xff
-#define BIT_STMP_THSD_8822B(x) \
- (((x) & BIT_MASK_STMP_THSD_8822B) << BIT_SHIFT_STMP_THSD_8822B)
-#define BIT_GET_STMP_THSD_8822B(x) \
- (((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B)
-
-/* 2 REG_MAC_SPEC_SIFS_8822B (SPECIFICATION SIFS REGISTER) */
-
-#define BIT_SHIFT_SPEC_SIFS_OFDM_8822B 8
-#define BIT_MASK_SPEC_SIFS_OFDM_8822B 0xff
-#define BIT_SPEC_SIFS_OFDM_8822B(x) \
- (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822B) \
- << BIT_SHIFT_SPEC_SIFS_OFDM_8822B)
-#define BIT_GET_SPEC_SIFS_OFDM_8822B(x) \
- (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) & \
- BIT_MASK_SPEC_SIFS_OFDM_8822B)
-
-#define BIT_SHIFT_SPEC_SIFS_CCK_8822B 0
-#define BIT_MASK_SPEC_SIFS_CCK_8822B 0xff
-#define BIT_SPEC_SIFS_CCK_8822B(x) \
- (((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B)
-#define BIT_GET_SPEC_SIFS_CCK_8822B(x) \
- (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B)
-
-/* 2 REG_USTIME_EDCA_8822B (US TIME TUNING FOR EDCA REGISTER) */
-
-#define BIT_SHIFT_USTIME_EDCA_V1_8822B 0
-#define BIT_MASK_USTIME_EDCA_V1_8822B 0x1ff
-#define BIT_USTIME_EDCA_V1_8822B(x) \
- (((x) & BIT_MASK_USTIME_EDCA_V1_8822B) \
- << BIT_SHIFT_USTIME_EDCA_V1_8822B)
-#define BIT_GET_USTIME_EDCA_V1_8822B(x) \
- (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) & \
- BIT_MASK_USTIME_EDCA_V1_8822B)
-
-/* 2 REG_RESP_SIFS_OFDM_8822B (RESPONSE SIFS FOR OFDM REGISTER) */
-
-#define BIT_SHIFT_SIFS_R2T_OFDM_8822B 8
-#define BIT_MASK_SIFS_R2T_OFDM_8822B 0xff
-#define BIT_SIFS_R2T_OFDM_8822B(x) \
- (((x) & BIT_MASK_SIFS_R2T_OFDM_8822B) << BIT_SHIFT_SIFS_R2T_OFDM_8822B)
-#define BIT_GET_SIFS_R2T_OFDM_8822B(x) \
- (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B)
-
-#define BIT_SHIFT_SIFS_T2T_OFDM_8822B 0
-#define BIT_MASK_SIFS_T2T_OFDM_8822B 0xff
-#define BIT_SIFS_T2T_OFDM_8822B(x) \
- (((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B)
-#define BIT_GET_SIFS_T2T_OFDM_8822B(x) \
- (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B)
-
-/* 2 REG_RESP_SIFS_CCK_8822B (RESPONSE SIFS FOR CCK REGISTER) */
-
-#define BIT_SHIFT_SIFS_R2T_CCK_8822B 8
-#define BIT_MASK_SIFS_R2T_CCK_8822B 0xff
-#define BIT_SIFS_R2T_CCK_8822B(x) \
- (((x) & BIT_MASK_SIFS_R2T_CCK_8822B) << BIT_SHIFT_SIFS_R2T_CCK_8822B)
-#define BIT_GET_SIFS_R2T_CCK_8822B(x) \
- (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B)
-
-#define BIT_SHIFT_SIFS_T2T_CCK_8822B 0
-#define BIT_MASK_SIFS_T2T_CCK_8822B 0xff
-#define BIT_SIFS_T2T_CCK_8822B(x) \
- (((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B)
-#define BIT_GET_SIFS_T2T_CCK_8822B(x) \
- (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B)
-
-/* 2 REG_EIFS_8822B (EIFS REGISTER) */
-
-#define BIT_SHIFT_EIFS_8822B 0
-#define BIT_MASK_EIFS_8822B 0xffff
-#define BIT_EIFS_8822B(x) (((x) & BIT_MASK_EIFS_8822B) << BIT_SHIFT_EIFS_8822B)
-#define BIT_GET_EIFS_8822B(x) \
- (((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B)
-
-/* 2 REG_CTS2TO_8822B (CTS2 TIMEOUT REGISTER) */
-
-#define BIT_SHIFT_CTS2TO_8822B 0
-#define BIT_MASK_CTS2TO_8822B 0xff
-#define BIT_CTS2TO_8822B(x) \
- (((x) & BIT_MASK_CTS2TO_8822B) << BIT_SHIFT_CTS2TO_8822B)
-#define BIT_GET_CTS2TO_8822B(x) \
- (((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B)
-
-/* 2 REG_ACKTO_8822B (ACK TIMEOUT REGISTER) */
-
-#define BIT_SHIFT_ACKTO_8822B 0
-#define BIT_MASK_ACKTO_8822B 0xff
-#define BIT_ACKTO_8822B(x) \
- (((x) & BIT_MASK_ACKTO_8822B) << BIT_SHIFT_ACKTO_8822B)
-#define BIT_GET_ACKTO_8822B(x) \
- (((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B)
-
-/* 2 REG_NAV_CTRL_8822B (NAV CONTROL REGISTER) */
-
-#define BIT_SHIFT_NAV_UPPER_8822B 16
-#define BIT_MASK_NAV_UPPER_8822B 0xff
-#define BIT_NAV_UPPER_8822B(x) \
- (((x) & BIT_MASK_NAV_UPPER_8822B) << BIT_SHIFT_NAV_UPPER_8822B)
-#define BIT_GET_NAV_UPPER_8822B(x) \
- (((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B)
-
-#define BIT_SHIFT_RXMYRTS_NAV_8822B 8
-#define BIT_MASK_RXMYRTS_NAV_8822B 0xf
-#define BIT_RXMYRTS_NAV_8822B(x) \
- (((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B)
-#define BIT_GET_RXMYRTS_NAV_8822B(x) \
- (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B)
-
-#define BIT_SHIFT_RTSRST_8822B 0
-#define BIT_MASK_RTSRST_8822B 0xff
-#define BIT_RTSRST_8822B(x) \
- (((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B)
-#define BIT_GET_RTSRST_8822B(x) \
- (((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B)
-
-/* 2 REG_BACAMCMD_8822B (BLOCK ACK CAM COMMAND REGISTER) */
-#define BIT_BACAM_POLL_8822B BIT(31)
-#define BIT_BACAM_RST_8822B BIT(17)
-#define BIT_BACAM_RW_8822B BIT(16)
-
-#define BIT_SHIFT_TXSBM_8822B 14
-#define BIT_MASK_TXSBM_8822B 0x3
-#define BIT_TXSBM_8822B(x) \
- (((x) & BIT_MASK_TXSBM_8822B) << BIT_SHIFT_TXSBM_8822B)
-#define BIT_GET_TXSBM_8822B(x) \
- (((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B)
-
-#define BIT_SHIFT_BACAM_ADDR_8822B 0
-#define BIT_MASK_BACAM_ADDR_8822B 0x3f
-#define BIT_BACAM_ADDR_8822B(x) \
- (((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B)
-#define BIT_GET_BACAM_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B)
-
-/* 2 REG_BACAMCONTENT_8822B (BLOCK ACK CAM CONTENT REGISTER) */
-
-#define BIT_SHIFT_BA_CONTENT_H_8822B (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_BA_CONTENT_H_8822B 0xffffffffL
-#define BIT_BA_CONTENT_H_8822B(x) \
- (((x) & BIT_MASK_BA_CONTENT_H_8822B) << BIT_SHIFT_BA_CONTENT_H_8822B)
-#define BIT_GET_BA_CONTENT_H_8822B(x) \
- (((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B)
-
-#define BIT_SHIFT_BA_CONTENT_L_8822B 0
-#define BIT_MASK_BA_CONTENT_L_8822B 0xffffffffL
-#define BIT_BA_CONTENT_L_8822B(x) \
- (((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B)
-#define BIT_GET_BA_CONTENT_L_8822B(x) \
- (((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B)
-
-/* 2 REG_WMAC_BITMAP_CTL_8822B */
-#define BIT_BITMAP_VO_8822B BIT(7)
-#define BIT_BITMAP_VI_8822B BIT(6)
-#define BIT_BITMAP_BE_8822B BIT(5)
-#define BIT_BITMAP_BK_8822B BIT(4)
-
-#define BIT_SHIFT_BITMAP_CONDITION_8822B 2
-#define BIT_MASK_BITMAP_CONDITION_8822B 0x3
-#define BIT_BITMAP_CONDITION_8822B(x) \
- (((x) & BIT_MASK_BITMAP_CONDITION_8822B) \
- << BIT_SHIFT_BITMAP_CONDITION_8822B)
-#define BIT_GET_BITMAP_CONDITION_8822B(x) \
- (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) & \
- BIT_MASK_BITMAP_CONDITION_8822B)
-
-#define BIT_BITMAP_SSNBK_COUNTER_CLR_8822B BIT(1)
-#define BIT_BITMAP_FORCE_8822B BIT(0)
-
-/* 2 REG_TX_RX_8822B STATUS */
-
-#define BIT_SHIFT_RXPKT_TYPE_8822B 2
-#define BIT_MASK_RXPKT_TYPE_8822B 0x3f
-#define BIT_RXPKT_TYPE_8822B(x) \
- (((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B)
-#define BIT_GET_RXPKT_TYPE_8822B(x) \
- (((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B)
-
-#define BIT_TXACT_IND_8822B BIT(1)
-#define BIT_RXACT_IND_8822B BIT(0)
-
-/* 2 REG_WMAC_BACAM_RPMEN_8822B */
-
-#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B 2
-#define BIT_MASK_BITMAP_SSNBK_COUNTER_8822B 0x3f
-#define BIT_BITMAP_SSNBK_COUNTER_8822B(x) \
- (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) \
- << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B)
-#define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x) \
- (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) & \
- BIT_MASK_BITMAP_SSNBK_COUNTER_8822B)
-
-#define BIT_BITMAP_EN_8822B BIT(1)
-#define BIT_WMAC_BACAM_RPMEN_8822B BIT(0)
-
-/* 2 REG_LBDLY_8822B (LOOPBACK DELAY REGISTER) */
-
-#define BIT_SHIFT_LBDLY_8822B 0
-#define BIT_MASK_LBDLY_8822B 0x1f
-#define BIT_LBDLY_8822B(x) \
- (((x) & BIT_MASK_LBDLY_8822B) << BIT_SHIFT_LBDLY_8822B)
-#define BIT_GET_LBDLY_8822B(x) \
- (((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B)
-
-/* 2 REG_RXERR_RPT_8822B (RX ERROR REPORT REGISTER) */
-
-#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B 28
-#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B 0xf
-#define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x) \
- (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) \
- << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B)
-#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x) \
- (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) & \
- BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B)
-
-#define BIT_RXERR_RPT_RST_8822B BIT(27)
-#define BIT_RXERR_RPT_SEL_V1_4_8822B BIT(26)
-#define BIT_W1S_8822B BIT(23)
-#define BIT_UD_SELECT_BSSID_8822B BIT(22)
-
-#define BIT_SHIFT_UD_SUB_TYPE_8822B 18
-#define BIT_MASK_UD_SUB_TYPE_8822B 0xf
-#define BIT_UD_SUB_TYPE_8822B(x) \
- (((x) & BIT_MASK_UD_SUB_TYPE_8822B) << BIT_SHIFT_UD_SUB_TYPE_8822B)
-#define BIT_GET_UD_SUB_TYPE_8822B(x) \
- (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B)
-
-#define BIT_SHIFT_UD_TYPE_8822B 16
-#define BIT_MASK_UD_TYPE_8822B 0x3
-#define BIT_UD_TYPE_8822B(x) \
- (((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B)
-#define BIT_GET_UD_TYPE_8822B(x) \
- (((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B)
-
-#define BIT_SHIFT_RPT_COUNTER_8822B 0
-#define BIT_MASK_RPT_COUNTER_8822B 0xffff
-#define BIT_RPT_COUNTER_8822B(x) \
- (((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B)
-#define BIT_GET_RPT_COUNTER_8822B(x) \
- (((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B)
-
-/* 2 REG_WMAC_TRXPTCL_CTL_8822B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */
-
-#define BIT_SHIFT_ACKBA_TYPSEL_8822B (60 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBA_TYPSEL_8822B 0xf
-#define BIT_ACKBA_TYPSEL_8822B(x) \
- (((x) & BIT_MASK_ACKBA_TYPSEL_8822B) << BIT_SHIFT_ACKBA_TYPSEL_8822B)
-#define BIT_GET_ACKBA_TYPSEL_8822B(x) \
- (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B)
-
-#define BIT_SHIFT_ACKBA_ACKPCHK_8822B (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBA_ACKPCHK_8822B 0xf
-#define BIT_ACKBA_ACKPCHK_8822B(x) \
- (((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B)
-#define BIT_GET_ACKBA_ACKPCHK_8822B(x) \
- (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B)
-
-#define BIT_SHIFT_ACKBAR_TYPESEL_8822B (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBAR_TYPESEL_8822B 0xff
-#define BIT_ACKBAR_TYPESEL_8822B(x) \
- (((x) & BIT_MASK_ACKBAR_TYPESEL_8822B) \
- << BIT_SHIFT_ACKBAR_TYPESEL_8822B)
-#define BIT_GET_ACKBAR_TYPESEL_8822B(x) \
- (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) & \
- BIT_MASK_ACKBAR_TYPESEL_8822B)
-
-#define BIT_SHIFT_ACKBAR_ACKPCHK_8822B (44 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBAR_ACKPCHK_8822B 0xf
-#define BIT_ACKBAR_ACKPCHK_8822B(x) \
- (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B) \
- << BIT_SHIFT_ACKBAR_ACKPCHK_8822B)
-#define BIT_GET_ACKBAR_ACKPCHK_8822B(x) \
- (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) & \
- BIT_MASK_ACKBAR_ACKPCHK_8822B)
-
-#define BIT_RXBA_IGNOREA2_8822B BIT(42)
-#define BIT_EN_SAVE_ALL_TXOPADDR_8822B BIT(41)
-#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8822B BIT(40)
-#define BIT_DIS_TXBA_AMPDUFCSERR_8822B BIT(39)
-#define BIT_DIS_TXBA_RXBARINFULL_8822B BIT(38)
-#define BIT_DIS_TXCFE_INFULL_8822B BIT(37)
-#define BIT_DIS_TXCTS_INFULL_8822B BIT(36)
-#define BIT_EN_TXACKBA_IN_TX_RDG_8822B BIT(35)
-#define BIT_EN_TXACKBA_IN_TXOP_8822B BIT(34)
-#define BIT_EN_TXCTS_IN_RXNAV_8822B BIT(33)
-#define BIT_EN_TXCTS_INTXOP_8822B BIT(32)
-#define BIT_BLK_EDCA_BBSLP_8822B BIT(31)
-#define BIT_BLK_EDCA_BBSBY_8822B BIT(30)
-#define BIT_ACKTO_BLOCK_SCH_EN_8822B BIT(27)
-#define BIT_EIFS_BLOCK_SCH_EN_8822B BIT(26)
-#define BIT_PLCPCHK_RST_EIFS_8822B BIT(25)
-#define BIT_CCA_RST_EIFS_8822B BIT(24)
-#define BIT_DIS_UPD_MYRXPKTNAV_8822B BIT(23)
-#define BIT_EARLY_TXBA_8822B BIT(22)
-
-#define BIT_SHIFT_RESP_CHNBUSY_8822B 20
-#define BIT_MASK_RESP_CHNBUSY_8822B 0x3
-#define BIT_RESP_CHNBUSY_8822B(x) \
- (((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B)
-#define BIT_GET_RESP_CHNBUSY_8822B(x) \
- (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B)
-
-#define BIT_RESP_DCTS_EN_8822B BIT(19)
-#define BIT_RESP_DCFE_EN_8822B BIT(18)
-#define BIT_RESP_SPLCPEN_8822B BIT(17)
-#define BIT_RESP_SGIEN_8822B BIT(16)
-#define BIT_RESP_LDPC_EN_8822B BIT(15)
-#define BIT_DIS_RESP_ACKINCCA_8822B BIT(14)
-#define BIT_DIS_RESP_CTSINCCA_8822B BIT(13)
-
-#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B 10
-#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B 0x7
-#define BIT_R_WMAC_SECOND_CCA_TIMER_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) \
- << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B)
-#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) & \
- BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B)
-
-#define BIT_SHIFT_RFMOD_8822B 7
-#define BIT_MASK_RFMOD_8822B 0x3
-#define BIT_RFMOD_8822B(x) \
- (((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B)
-#define BIT_GET_RFMOD_8822B(x) \
- (((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B)
-
-#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B 5
-#define BIT_MASK_RESP_CTS_DYNBW_SEL_8822B 0x3
-#define BIT_RESP_CTS_DYNBW_SEL_8822B(x) \
- (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) \
- << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B)
-#define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) & \
- BIT_MASK_RESP_CTS_DYNBW_SEL_8822B)
-
-#define BIT_DLY_TX_WAIT_RXANTSEL_8822B BIT(4)
-#define BIT_TXRESP_BY_RXANTSEL_8822B BIT(3)
-
-#define BIT_SHIFT_ORIG_DCTS_CHK_8822B 0
-#define BIT_MASK_ORIG_DCTS_CHK_8822B 0x3
-#define BIT_ORIG_DCTS_CHK_8822B(x) \
- (((x) & BIT_MASK_ORIG_DCTS_CHK_8822B) << BIT_SHIFT_ORIG_DCTS_CHK_8822B)
-#define BIT_GET_ORIG_DCTS_CHK_8822B(x) \
- (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B)
-
-/* 2 REG_CAMCMD_8822B (CAM COMMAND REGISTER) */
-#define BIT_SECCAM_POLLING_8822B BIT(31)
-#define BIT_SECCAM_CLR_8822B BIT(30)
-#define BIT_MFBCAM_CLR_8822B BIT(29)
-#define BIT_SECCAM_WE_8822B BIT(16)
-
-#define BIT_SHIFT_SECCAM_ADDR_V2_8822B 0
-#define BIT_MASK_SECCAM_ADDR_V2_8822B 0x3ff
-#define BIT_SECCAM_ADDR_V2_8822B(x) \
- (((x) & BIT_MASK_SECCAM_ADDR_V2_8822B) \
- << BIT_SHIFT_SECCAM_ADDR_V2_8822B)
-#define BIT_GET_SECCAM_ADDR_V2_8822B(x) \
- (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) & \
- BIT_MASK_SECCAM_ADDR_V2_8822B)
-
-/* 2 REG_CAMWRITE_8822B (CAM WRITE REGISTER) */
-
-#define BIT_SHIFT_CAMW_DATA_8822B 0
-#define BIT_MASK_CAMW_DATA_8822B 0xffffffffL
-#define BIT_CAMW_DATA_8822B(x) \
- (((x) & BIT_MASK_CAMW_DATA_8822B) << BIT_SHIFT_CAMW_DATA_8822B)
-#define BIT_GET_CAMW_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B)
-
-/* 2 REG_CAMREAD_8822B (CAM READ REGISTER) */
-
-#define BIT_SHIFT_CAMR_DATA_8822B 0
-#define BIT_MASK_CAMR_DATA_8822B 0xffffffffL
-#define BIT_CAMR_DATA_8822B(x) \
- (((x) & BIT_MASK_CAMR_DATA_8822B) << BIT_SHIFT_CAMR_DATA_8822B)
-#define BIT_GET_CAMR_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B)
-
-/* 2 REG_CAMDBG_8822B (CAM DEBUG REGISTER) */
-#define BIT_SECCAM_INFO_8822B BIT(31)
-#define BIT_SEC_KEYFOUND_8822B BIT(15)
-
-#define BIT_SHIFT_CAMDBG_SEC_TYPE_8822B 12
-#define BIT_MASK_CAMDBG_SEC_TYPE_8822B 0x7
-#define BIT_CAMDBG_SEC_TYPE_8822B(x) \
- (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) \
- << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B)
-#define BIT_GET_CAMDBG_SEC_TYPE_8822B(x) \
- (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) & \
- BIT_MASK_CAMDBG_SEC_TYPE_8822B)
-
-#define BIT_CAMDBG_EXT_SECTYPE_8822B BIT(11)
-
-#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B 5
-#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B 0x1f
-#define BIT_CAMDBG_MIC_KEY_IDX_8822B(x) \
- (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) \
- << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B)
-#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) & \
- BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B)
-
-#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B 0
-#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B 0x1f
-#define BIT_CAMDBG_SEC_KEY_IDX_8822B(x) \
- (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) \
- << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B)
-#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) & \
- BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B)
-
-/* 2 REG_RXFILTER_ACTION_1_8822B */
-
-#define BIT_SHIFT_RXFILTER_ACTION_1_8822B 0
-#define BIT_MASK_RXFILTER_ACTION_1_8822B 0xff
-#define BIT_RXFILTER_ACTION_1_8822B(x) \
- (((x) & BIT_MASK_RXFILTER_ACTION_1_8822B) \
- << BIT_SHIFT_RXFILTER_ACTION_1_8822B)
-#define BIT_GET_RXFILTER_ACTION_1_8822B(x) \
- (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) & \
- BIT_MASK_RXFILTER_ACTION_1_8822B)
-
-/* 2 REG_RXFILTER_CATEGORY_1_8822B */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_1_8822B 0
-#define BIT_MASK_RXFILTER_CATEGORY_1_8822B 0xff
-#define BIT_RXFILTER_CATEGORY_1_8822B(x) \
- (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) \
- << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B)
-#define BIT_GET_RXFILTER_CATEGORY_1_8822B(x) \
- (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) & \
- BIT_MASK_RXFILTER_CATEGORY_1_8822B)
-
-/* 2 REG_SECCFG_8822B (SECURITY CONFIGURATION REGISTER) */
-#define BIT_DIS_GCLK_WAPI_8822B BIT(15)
-#define BIT_DIS_GCLK_AES_8822B BIT(14)
-#define BIT_DIS_GCLK_TKIP_8822B BIT(13)
-#define BIT_AES_SEL_QC_1_8822B BIT(12)
-#define BIT_AES_SEL_QC_0_8822B BIT(11)
-#define BIT_CHK_BMC_8822B BIT(9)
-#define BIT_CHK_KEYID_8822B BIT(8)
-#define BIT_RXBCUSEDK_8822B BIT(7)
-#define BIT_TXBCUSEDK_8822B BIT(6)
-#define BIT_NOSKMC_8822B BIT(5)
-#define BIT_SKBYA2_8822B BIT(4)
-#define BIT_RXDEC_8822B BIT(3)
-#define BIT_TXENC_8822B BIT(2)
-#define BIT_RXUHUSEDK_8822B BIT(1)
-#define BIT_TXUHUSEDK_8822B BIT(0)
-
-/* 2 REG_RXFILTER_ACTION_3_8822B */
-
-#define BIT_SHIFT_RXFILTER_ACTION_3_8822B 0
-#define BIT_MASK_RXFILTER_ACTION_3_8822B 0xff
-#define BIT_RXFILTER_ACTION_3_8822B(x) \
- (((x) & BIT_MASK_RXFILTER_ACTION_3_8822B) \
- << BIT_SHIFT_RXFILTER_ACTION_3_8822B)
-#define BIT_GET_RXFILTER_ACTION_3_8822B(x) \
- (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) & \
- BIT_MASK_RXFILTER_ACTION_3_8822B)
-
-/* 2 REG_RXFILTER_CATEGORY_3_8822B */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_3_8822B 0
-#define BIT_MASK_RXFILTER_CATEGORY_3_8822B 0xff
-#define BIT_RXFILTER_CATEGORY_3_8822B(x) \
- (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) \
- << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B)
-#define BIT_GET_RXFILTER_CATEGORY_3_8822B(x) \
- (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) & \
- BIT_MASK_RXFILTER_CATEGORY_3_8822B)
-
-/* 2 REG_RXFILTER_ACTION_2_8822B */
-
-#define BIT_SHIFT_RXFILTER_ACTION_2_8822B 0
-#define BIT_MASK_RXFILTER_ACTION_2_8822B 0xff
-#define BIT_RXFILTER_ACTION_2_8822B(x) \
- (((x) & BIT_MASK_RXFILTER_ACTION_2_8822B) \
- << BIT_SHIFT_RXFILTER_ACTION_2_8822B)
-#define BIT_GET_RXFILTER_ACTION_2_8822B(x) \
- (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) & \
- BIT_MASK_RXFILTER_ACTION_2_8822B)
-
-/* 2 REG_RXFILTER_CATEGORY_2_8822B */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_2_8822B 0
-#define BIT_MASK_RXFILTER_CATEGORY_2_8822B 0xff
-#define BIT_RXFILTER_CATEGORY_2_8822B(x) \
- (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) \
- << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B)
-#define BIT_GET_RXFILTER_CATEGORY_2_8822B(x) \
- (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) & \
- BIT_MASK_RXFILTER_CATEGORY_2_8822B)
-
-/* 2 REG_RXFLTMAP4_8822B (RX FILTER MAP GROUP 4) */
-#define BIT_CTRLFLT15EN_FW_8822B BIT(15)
-#define BIT_CTRLFLT14EN_FW_8822B BIT(14)
-#define BIT_CTRLFLT13EN_FW_8822B BIT(13)
-#define BIT_CTRLFLT12EN_FW_8822B BIT(12)
-#define BIT_CTRLFLT11EN_FW_8822B BIT(11)
-#define BIT_CTRLFLT10EN_FW_8822B BIT(10)
-#define BIT_CTRLFLT9EN_FW_8822B BIT(9)
-#define BIT_CTRLFLT8EN_FW_8822B BIT(8)
-#define BIT_CTRLFLT7EN_FW_8822B BIT(7)
-#define BIT_CTRLFLT6EN_FW_8822B BIT(6)
-#define BIT_CTRLFLT5EN_FW_8822B BIT(5)
-#define BIT_CTRLFLT4EN_FW_8822B BIT(4)
-#define BIT_CTRLFLT3EN_FW_8822B BIT(3)
-#define BIT_CTRLFLT2EN_FW_8822B BIT(2)
-#define BIT_CTRLFLT1EN_FW_8822B BIT(1)
-#define BIT_CTRLFLT0EN_FW_8822B BIT(0)
-
-/* 2 REG_RXFLTMAP3_8822B (RX FILTER MAP GROUP 3) */
-#define BIT_MGTFLT15EN_FW_8822B BIT(15)
-#define BIT_MGTFLT14EN_FW_8822B BIT(14)
-#define BIT_MGTFLT13EN_FW_8822B BIT(13)
-#define BIT_MGTFLT12EN_FW_8822B BIT(12)
-#define BIT_MGTFLT11EN_FW_8822B BIT(11)
-#define BIT_MGTFLT10EN_FW_8822B BIT(10)
-#define BIT_MGTFLT9EN_FW_8822B BIT(9)
-#define BIT_MGTFLT8EN_FW_8822B BIT(8)
-#define BIT_MGTFLT7EN_FW_8822B BIT(7)
-#define BIT_MGTFLT6EN_FW_8822B BIT(6)
-#define BIT_MGTFLT5EN_FW_8822B BIT(5)
-#define BIT_MGTFLT4EN_FW_8822B BIT(4)
-#define BIT_MGTFLT3EN_FW_8822B BIT(3)
-#define BIT_MGTFLT2EN_FW_8822B BIT(2)
-#define BIT_MGTFLT1EN_FW_8822B BIT(1)
-#define BIT_MGTFLT0EN_FW_8822B BIT(0)
-
-/* 2 REG_RXFLTMAP6_8822B (RX FILTER MAP GROUP 3) */
-#define BIT_ACTIONFLT15EN_FW_8822B BIT(15)
-#define BIT_ACTIONFLT14EN_FW_8822B BIT(14)
-#define BIT_ACTIONFLT13EN_FW_8822B BIT(13)
-#define BIT_ACTIONFLT12EN_FW_8822B BIT(12)
-#define BIT_ACTIONFLT11EN_FW_8822B BIT(11)
-#define BIT_ACTIONFLT10EN_FW_8822B BIT(10)
-#define BIT_ACTIONFLT9EN_FW_8822B BIT(9)
-#define BIT_ACTIONFLT8EN_FW_8822B BIT(8)
-#define BIT_ACTIONFLT7EN_FW_8822B BIT(7)
-#define BIT_ACTIONFLT6EN_FW_8822B BIT(6)
-#define BIT_ACTIONFLT5EN_FW_8822B BIT(5)
-#define BIT_ACTIONFLT4EN_FW_8822B BIT(4)
-#define BIT_ACTIONFLT3EN_FW_8822B BIT(3)
-#define BIT_ACTIONFLT2EN_FW_8822B BIT(2)
-#define BIT_ACTIONFLT1EN_FW_8822B BIT(1)
-#define BIT_ACTIONFLT0EN_FW_8822B BIT(0)
-
-/* 2 REG_RXFLTMAP5_8822B (RX FILTER MAP GROUP 3) */
-#define BIT_DATAFLT15EN_FW_8822B BIT(15)
-#define BIT_DATAFLT14EN_FW_8822B BIT(14)
-#define BIT_DATAFLT13EN_FW_8822B BIT(13)
-#define BIT_DATAFLT12EN_FW_8822B BIT(12)
-#define BIT_DATAFLT11EN_FW_8822B BIT(11)
-#define BIT_DATAFLT10EN_FW_8822B BIT(10)
-#define BIT_DATAFLT9EN_FW_8822B BIT(9)
-#define BIT_DATAFLT8EN_FW_8822B BIT(8)
-#define BIT_DATAFLT7EN_FW_8822B BIT(7)
-#define BIT_DATAFLT6EN_FW_8822B BIT(6)
-#define BIT_DATAFLT5EN_FW_8822B BIT(5)
-#define BIT_DATAFLT4EN_FW_8822B BIT(4)
-#define BIT_DATAFLT3EN_FW_8822B BIT(3)
-#define BIT_DATAFLT2EN_FW_8822B BIT(2)
-#define BIT_DATAFLT1EN_FW_8822B BIT(1)
-#define BIT_DATAFLT0EN_FW_8822B BIT(0)
-
-/* 2 REG_WMMPS_UAPSD_TID_8822B (WMM POWER SAVE UAPSD TID REGISTER) */
-#define BIT_WMMPS_UAPSD_TID7_8822B BIT(7)
-#define BIT_WMMPS_UAPSD_TID6_8822B BIT(6)
-#define BIT_WMMPS_UAPSD_TID5_8822B BIT(5)
-#define BIT_WMMPS_UAPSD_TID4_8822B BIT(4)
-#define BIT_WMMPS_UAPSD_TID3_8822B BIT(3)
-#define BIT_WMMPS_UAPSD_TID2_8822B BIT(2)
-#define BIT_WMMPS_UAPSD_TID1_8822B BIT(1)
-#define BIT_WMMPS_UAPSD_TID0_8822B BIT(0)
-
-/* 2 REG_PS_RX_INFO_8822B (POWER SAVE RX INFORMATION REGISTER) */
-
-#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B 5
-#define BIT_MASK_PORTSEL__PS_RX_INFO_8822B 0x7
-#define BIT_PORTSEL__PS_RX_INFO_8822B(x) \
- (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) \
- << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B)
-#define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) & \
- BIT_MASK_PORTSEL__PS_RX_INFO_8822B)
-
-#define BIT_RXCTRLIN0_8822B BIT(4)
-#define BIT_RXMGTIN0_8822B BIT(3)
-#define BIT_RXDATAIN2_8822B BIT(2)
-#define BIT_RXDATAIN1_8822B BIT(1)
-#define BIT_RXDATAIN0_8822B BIT(0)
-
-/* 2 REG_NAN_RX_TSF_FILTER_8822B(NAN_RX_TSF_ADDRESS_FILTER) */
-#define BIT_CHK_TSF_TA_8822B BIT(2)
-#define BIT_CHK_TSF_CBSSID_8822B BIT(1)
-#define BIT_CHK_TSF_EN_8822B BIT(0)
-
-/* 2 REG_WOW_CTRL_8822B (WAKE ON WLAN CONTROL REGISTER) */
-
-#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B 6
-#define BIT_MASK_PSF_BSSIDSEL_B2B1_8822B 0x3
-#define BIT_PSF_BSSIDSEL_B2B1_8822B(x) \
- (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) \
- << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B)
-#define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x) \
- (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) & \
- BIT_MASK_PSF_BSSIDSEL_B2B1_8822B)
-
-#define BIT_WOWHCI_8822B BIT(5)
-#define BIT_PSF_BSSIDSEL_B0_8822B BIT(4)
-#define BIT_UWF_8822B BIT(3)
-#define BIT_MAGIC_8822B BIT(2)
-#define BIT_WOWEN_8822B BIT(1)
-#define BIT_FORCE_WAKEUP_8822B BIT(0)
-
-/* 2 REG_LPNAV_CTRL_8822B (LOW POWER NAV CONTROL REGISTER) */
-#define BIT_LPNAV_EN_8822B BIT(31)
-
-#define BIT_SHIFT_LPNAV_EARLY_8822B 16
-#define BIT_MASK_LPNAV_EARLY_8822B 0x7fff
-#define BIT_LPNAV_EARLY_8822B(x) \
- (((x) & BIT_MASK_LPNAV_EARLY_8822B) << BIT_SHIFT_LPNAV_EARLY_8822B)
-#define BIT_GET_LPNAV_EARLY_8822B(x) \
- (((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B)
-
-#define BIT_SHIFT_LPNAV_TH_8822B 0
-#define BIT_MASK_LPNAV_TH_8822B 0xffff
-#define BIT_LPNAV_TH_8822B(x) \
- (((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B)
-#define BIT_GET_LPNAV_TH_8822B(x) \
- (((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B)
-
-/* 2 REG_WKFMCAM_CMD_8822B (WAKEUP FRAME CAM COMMAND REGISTER) */
-#define BIT_WKFCAM_POLLING_V1_8822B BIT(31)
-#define BIT_WKFCAM_CLR_V1_8822B BIT(30)
-#define BIT_WKFCAM_WE_8822B BIT(16)
-
-#define BIT_SHIFT_WKFCAM_ADDR_V2_8822B 8
-#define BIT_MASK_WKFCAM_ADDR_V2_8822B 0xff
-#define BIT_WKFCAM_ADDR_V2_8822B(x) \
- (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822B) \
- << BIT_SHIFT_WKFCAM_ADDR_V2_8822B)
-#define BIT_GET_WKFCAM_ADDR_V2_8822B(x) \
- (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822B) & \
- BIT_MASK_WKFCAM_ADDR_V2_8822B)
-
-#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B 0
-#define BIT_MASK_WKFCAM_CAM_NUM_V1_8822B 0xff
-#define BIT_WKFCAM_CAM_NUM_V1_8822B(x) \
- (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) \
- << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B)
-#define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x) \
- (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) & \
- BIT_MASK_WKFCAM_CAM_NUM_V1_8822B)
-
-/* 2 REG_WKFMCAM_RWD_8822B (WAKEUP FRAME READ/WRITE DATA) */
-
-#define BIT_SHIFT_WKFMCAM_RWD_8822B 0
-#define BIT_MASK_WKFMCAM_RWD_8822B 0xffffffffL
-#define BIT_WKFMCAM_RWD_8822B(x) \
- (((x) & BIT_MASK_WKFMCAM_RWD_8822B) << BIT_SHIFT_WKFMCAM_RWD_8822B)
-#define BIT_GET_WKFMCAM_RWD_8822B(x) \
- (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B)
-
-/* 2 REG_RXFLTMAP1_8822B (RX FILTER MAP GROUP 1) */
-#define BIT_CTRLFLT15EN_8822B BIT(15)
-#define BIT_CTRLFLT14EN_8822B BIT(14)
-#define BIT_CTRLFLT13EN_8822B BIT(13)
-#define BIT_CTRLFLT12EN_8822B BIT(12)
-#define BIT_CTRLFLT11EN_8822B BIT(11)
-#define BIT_CTRLFLT10EN_8822B BIT(10)
-#define BIT_CTRLFLT9EN_8822B BIT(9)
-#define BIT_CTRLFLT8EN_8822B BIT(8)
-#define BIT_CTRLFLT7EN_8822B BIT(7)
-#define BIT_CTRLFLT6EN_8822B BIT(6)
-#define BIT_CTRLFLT5EN_8822B BIT(5)
-#define BIT_CTRLFLT4EN_8822B BIT(4)
-#define BIT_CTRLFLT3EN_8822B BIT(3)
-#define BIT_CTRLFLT2EN_8822B BIT(2)
-#define BIT_CTRLFLT1EN_8822B BIT(1)
-#define BIT_CTRLFLT0EN_8822B BIT(0)
-
-/* 2 REG_RXFLTMAP0_8822B (RX FILTER MAP GROUP 0) */
-#define BIT_MGTFLT15EN_8822B BIT(15)
-#define BIT_MGTFLT14EN_8822B BIT(14)
-#define BIT_MGTFLT13EN_8822B BIT(13)
-#define BIT_MGTFLT12EN_8822B BIT(12)
-#define BIT_MGTFLT11EN_8822B BIT(11)
-#define BIT_MGTFLT10EN_8822B BIT(10)
-#define BIT_MGTFLT9EN_8822B BIT(9)
-#define BIT_MGTFLT8EN_8822B BIT(8)
-#define BIT_MGTFLT7EN_8822B BIT(7)
-#define BIT_MGTFLT6EN_8822B BIT(6)
-#define BIT_MGTFLT5EN_8822B BIT(5)
-#define BIT_MGTFLT4EN_8822B BIT(4)
-#define BIT_MGTFLT3EN_8822B BIT(3)
-#define BIT_MGTFLT2EN_8822B BIT(2)
-#define BIT_MGTFLT1EN_8822B BIT(1)
-#define BIT_MGTFLT0EN_8822B BIT(0)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_RXFLTMAP_8822B (RX FILTER MAP GROUP 2) */
-#define BIT_DATAFLT15EN_8822B BIT(15)
-#define BIT_DATAFLT14EN_8822B BIT(14)
-#define BIT_DATAFLT13EN_8822B BIT(13)
-#define BIT_DATAFLT12EN_8822B BIT(12)
-#define BIT_DATAFLT11EN_8822B BIT(11)
-#define BIT_DATAFLT10EN_8822B BIT(10)
-#define BIT_DATAFLT9EN_8822B BIT(9)
-#define BIT_DATAFLT8EN_8822B BIT(8)
-#define BIT_DATAFLT7EN_8822B BIT(7)
-#define BIT_DATAFLT6EN_8822B BIT(6)
-#define BIT_DATAFLT5EN_8822B BIT(5)
-#define BIT_DATAFLT4EN_8822B BIT(4)
-#define BIT_DATAFLT3EN_8822B BIT(3)
-#define BIT_DATAFLT2EN_8822B BIT(2)
-#define BIT_DATAFLT1EN_8822B BIT(1)
-#define BIT_DATAFLT0EN_8822B BIT(0)
-
-/* 2 REG_BCN_PSR_RPT_8822B (BEACON PARSER REPORT REGISTER) */
-
-#define BIT_SHIFT_DTIM_CNT_8822B 24
-#define BIT_MASK_DTIM_CNT_8822B 0xff
-#define BIT_DTIM_CNT_8822B(x) \
- (((x) & BIT_MASK_DTIM_CNT_8822B) << BIT_SHIFT_DTIM_CNT_8822B)
-#define BIT_GET_DTIM_CNT_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B)
-
-#define BIT_SHIFT_DTIM_PERIOD_8822B 16
-#define BIT_MASK_DTIM_PERIOD_8822B 0xff
-#define BIT_DTIM_PERIOD_8822B(x) \
- (((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B)
-#define BIT_GET_DTIM_PERIOD_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B)
-
-#define BIT_DTIM_8822B BIT(15)
-#define BIT_TIM_8822B BIT(14)
-
-#define BIT_SHIFT_PS_AID_0_8822B 0
-#define BIT_MASK_PS_AID_0_8822B 0x7ff
-#define BIT_PS_AID_0_8822B(x) \
- (((x) & BIT_MASK_PS_AID_0_8822B) << BIT_SHIFT_PS_AID_0_8822B)
-#define BIT_GET_PS_AID_0_8822B(x) \
- (((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B)
-
-/* 2 REG_FLC_TRPC_8822B (TIMER OF FLC_RPC) */
-#define BIT_FLC_RPCT_V1_8822B BIT(7)
-#define BIT_MODE_8822B BIT(6)
-
-#define BIT_SHIFT_TRPCD_8822B 0
-#define BIT_MASK_TRPCD_8822B 0x3f
-#define BIT_TRPCD_8822B(x) \
- (((x) & BIT_MASK_TRPCD_8822B) << BIT_SHIFT_TRPCD_8822B)
-#define BIT_GET_TRPCD_8822B(x) \
- (((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B)
-
-/* 2 REG_FLC_PTS_8822B (PKT TYPE SELECTION OF FLC_RPC T) */
-#define BIT_CMF_8822B BIT(2)
-#define BIT_CCF_8822B BIT(1)
-#define BIT_CDF_8822B BIT(0)
-
-/* 2 REG_FLC_RPCT_8822B (FLC_RPC THRESHOLD) */
-
-#define BIT_SHIFT_FLC_RPCT_8822B 0
-#define BIT_MASK_FLC_RPCT_8822B 0xff
-#define BIT_FLC_RPCT_8822B(x) \
- (((x) & BIT_MASK_FLC_RPCT_8822B) << BIT_SHIFT_FLC_RPCT_8822B)
-#define BIT_GET_FLC_RPCT_8822B(x) \
- (((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B)
-
-/* 2 REG_FLC_RPC_8822B (FW LPS CONDITION -- RX PKT COUNTER) */
-
-#define BIT_SHIFT_FLC_RPC_8822B 0
-#define BIT_MASK_FLC_RPC_8822B 0xff
-#define BIT_FLC_RPC_8822B(x) \
- (((x) & BIT_MASK_FLC_RPC_8822B) << BIT_SHIFT_FLC_RPC_8822B)
-#define BIT_GET_FLC_RPC_8822B(x) \
- (((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B)
-
-/* 2 REG_RXPKTMON_CTRL_8822B */
-
-#define BIT_SHIFT_RXBKQPKT_SEQ_8822B 20
-#define BIT_MASK_RXBKQPKT_SEQ_8822B 0xf
-#define BIT_RXBKQPKT_SEQ_8822B(x) \
- (((x) & BIT_MASK_RXBKQPKT_SEQ_8822B) << BIT_SHIFT_RXBKQPKT_SEQ_8822B)
-#define BIT_GET_RXBKQPKT_SEQ_8822B(x) \
- (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B)
-
-#define BIT_SHIFT_RXBEQPKT_SEQ_8822B 16
-#define BIT_MASK_RXBEQPKT_SEQ_8822B 0xf
-#define BIT_RXBEQPKT_SEQ_8822B(x) \
- (((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B)
-#define BIT_GET_RXBEQPKT_SEQ_8822B(x) \
- (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B)
-
-#define BIT_SHIFT_RXVIQPKT_SEQ_8822B 12
-#define BIT_MASK_RXVIQPKT_SEQ_8822B 0xf
-#define BIT_RXVIQPKT_SEQ_8822B(x) \
- (((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B)
-#define BIT_GET_RXVIQPKT_SEQ_8822B(x) \
- (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B)
-
-#define BIT_SHIFT_RXVOQPKT_SEQ_8822B 8
-#define BIT_MASK_RXVOQPKT_SEQ_8822B 0xf
-#define BIT_RXVOQPKT_SEQ_8822B(x) \
- (((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B)
-#define BIT_GET_RXVOQPKT_SEQ_8822B(x) \
- (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B)
-
-#define BIT_RXBKQPKT_ERR_8822B BIT(7)
-#define BIT_RXBEQPKT_ERR_8822B BIT(6)
-#define BIT_RXVIQPKT_ERR_8822B BIT(5)
-#define BIT_RXVOQPKT_ERR_8822B BIT(4)
-#define BIT_RXDMA_MON_EN_8822B BIT(2)
-#define BIT_RXPKT_MON_RST_8822B BIT(1)
-#define BIT_RXPKT_MON_EN_8822B BIT(0)
-
-/* 2 REG_STATE_MON_8822B */
-
-#define BIT_SHIFT_STATE_SEL_8822B 24
-#define BIT_MASK_STATE_SEL_8822B 0x1f
-#define BIT_STATE_SEL_8822B(x) \
- (((x) & BIT_MASK_STATE_SEL_8822B) << BIT_SHIFT_STATE_SEL_8822B)
-#define BIT_GET_STATE_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B)
-
-#define BIT_SHIFT_STATE_INFO_8822B 8
-#define BIT_MASK_STATE_INFO_8822B 0xff
-#define BIT_STATE_INFO_8822B(x) \
- (((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B)
-#define BIT_GET_STATE_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B)
-
-#define BIT_UPD_NXT_STATE_8822B BIT(7)
-
-#define BIT_SHIFT_CUR_STATE_8822B 0
-#define BIT_MASK_CUR_STATE_8822B 0x7f
-#define BIT_CUR_STATE_8822B(x) \
- (((x) & BIT_MASK_CUR_STATE_8822B) << BIT_SHIFT_CUR_STATE_8822B)
-#define BIT_GET_CUR_STATE_8822B(x) \
- (((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B)
-
-/* 2 REG_ERROR_MON_8822B */
-#define BIT_MACRX_ERR_1_8822B BIT(17)
-#define BIT_MACRX_ERR_0_8822B BIT(16)
-#define BIT_MACTX_ERR_3_8822B BIT(3)
-#define BIT_MACTX_ERR_2_8822B BIT(2)
-#define BIT_MACTX_ERR_1_8822B BIT(1)
-#define BIT_MACTX_ERR_0_8822B BIT(0)
-
-/* 2 REG_SEARCH_MACID_8822B */
-#define BIT_EN_TXRPTBUF_CLK_8822B BIT(31)
-
-#define BIT_SHIFT_INFO_INDEX_OFFSET_8822B 16
-#define BIT_MASK_INFO_INDEX_OFFSET_8822B 0x1fff
-#define BIT_INFO_INDEX_OFFSET_8822B(x) \
- (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B) \
- << BIT_SHIFT_INFO_INDEX_OFFSET_8822B)
-#define BIT_GET_INFO_INDEX_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) & \
- BIT_MASK_INFO_INDEX_OFFSET_8822B)
-
-#define BIT_WMAC_SRCH_FIFOFULL_8822B BIT(15)
-#define BIT_DIS_INFOSRCH_8822B BIT(14)
-#define BIT_DISABLE_B0_8822B BIT(13)
-
-#define BIT_SHIFT_INFO_ADDR_OFFSET_8822B 0
-#define BIT_MASK_INFO_ADDR_OFFSET_8822B 0x1fff
-#define BIT_INFO_ADDR_OFFSET_8822B(x) \
- (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822B) \
- << BIT_SHIFT_INFO_ADDR_OFFSET_8822B)
-#define BIT_GET_INFO_ADDR_OFFSET_8822B(x) \
- (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) & \
- BIT_MASK_INFO_ADDR_OFFSET_8822B)
-
-/* 2 REG_BT_COEX_TABLE_8822B (BT-COEXISTENCE CONTROL REGISTER) */
-#define BIT_PRI_MASK_RX_RESP_8822B BIT(126)
-#define BIT_PRI_MASK_RXOFDM_8822B BIT(125)
-#define BIT_PRI_MASK_RXCCK_8822B BIT(124)
-
-#define BIT_SHIFT_PRI_MASK_TXAC_8822B (117 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_TXAC_8822B 0x7f
-#define BIT_PRI_MASK_TXAC_8822B(x) \
- (((x) & BIT_MASK_PRI_MASK_TXAC_8822B) << BIT_SHIFT_PRI_MASK_TXAC_8822B)
-#define BIT_GET_PRI_MASK_TXAC_8822B(x) \
- (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B)
-
-#define BIT_SHIFT_PRI_MASK_NAV_8822B (109 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_NAV_8822B 0xff
-#define BIT_PRI_MASK_NAV_8822B(x) \
- (((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B)
-#define BIT_GET_PRI_MASK_NAV_8822B(x) \
- (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B)
-
-#define BIT_PRI_MASK_CCK_8822B BIT(108)
-#define BIT_PRI_MASK_OFDM_8822B BIT(107)
-#define BIT_PRI_MASK_RTY_8822B BIT(106)
-
-#define BIT_SHIFT_PRI_MASK_NUM_8822B (102 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_NUM_8822B 0xf
-#define BIT_PRI_MASK_NUM_8822B(x) \
- (((x) & BIT_MASK_PRI_MASK_NUM_8822B) << BIT_SHIFT_PRI_MASK_NUM_8822B)
-#define BIT_GET_PRI_MASK_NUM_8822B(x) \
- (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B)
-
-#define BIT_SHIFT_PRI_MASK_TYPE_8822B (98 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_TYPE_8822B 0xf
-#define BIT_PRI_MASK_TYPE_8822B(x) \
- (((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B)
-#define BIT_GET_PRI_MASK_TYPE_8822B(x) \
- (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B)
-
-#define BIT_OOB_8822B BIT(97)
-#define BIT_ANT_SEL_8822B BIT(96)
-
-#define BIT_SHIFT_BREAK_TABLE_2_8822B (80 & CPU_OPT_WIDTH)
-#define BIT_MASK_BREAK_TABLE_2_8822B 0xffff
-#define BIT_BREAK_TABLE_2_8822B(x) \
- (((x) & BIT_MASK_BREAK_TABLE_2_8822B) << BIT_SHIFT_BREAK_TABLE_2_8822B)
-#define BIT_GET_BREAK_TABLE_2_8822B(x) \
- (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B)
-
-#define BIT_SHIFT_BREAK_TABLE_1_8822B (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_BREAK_TABLE_1_8822B 0xffff
-#define BIT_BREAK_TABLE_1_8822B(x) \
- (((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B)
-#define BIT_GET_BREAK_TABLE_1_8822B(x) \
- (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B)
-
-#define BIT_SHIFT_COEX_TABLE_2_8822B (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_COEX_TABLE_2_8822B 0xffffffffL
-#define BIT_COEX_TABLE_2_8822B(x) \
- (((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B)
-#define BIT_GET_COEX_TABLE_2_8822B(x) \
- (((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B)
-
-#define BIT_SHIFT_COEX_TABLE_1_8822B 0
-#define BIT_MASK_COEX_TABLE_1_8822B 0xffffffffL
-#define BIT_COEX_TABLE_1_8822B(x) \
- (((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B)
-#define BIT_GET_COEX_TABLE_1_8822B(x) \
- (((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B)
-
-/* 2 REG_RXCMD_0_8822B */
-#define BIT_RXCMD_EN_8822B BIT(31)
-
-#define BIT_SHIFT_RXCMD_INFO_8822B 0
-#define BIT_MASK_RXCMD_INFO_8822B 0x7fffffffL
-#define BIT_RXCMD_INFO_8822B(x) \
- (((x) & BIT_MASK_RXCMD_INFO_8822B) << BIT_SHIFT_RXCMD_INFO_8822B)
-#define BIT_GET_RXCMD_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B)
-
-/* 2 REG_RXCMD_1_8822B */
-
-#define BIT_SHIFT_RXCMD_PRD_8822B 0
-#define BIT_MASK_RXCMD_PRD_8822B 0xffff
-#define BIT_RXCMD_PRD_8822B(x) \
- (((x) & BIT_MASK_RXCMD_PRD_8822B) << BIT_SHIFT_RXCMD_PRD_8822B)
-#define BIT_GET_RXCMD_PRD_8822B(x) \
- (((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_WMAC_RESP_TXINFO_8822B (RESPONSE TXINFO REGISTER) */
-
-#define BIT_SHIFT_WMAC_RESP_MFB_8822B 25
-#define BIT_MASK_WMAC_RESP_MFB_8822B 0x7f
-#define BIT_WMAC_RESP_MFB_8822B(x) \
- (((x) & BIT_MASK_WMAC_RESP_MFB_8822B) << BIT_SHIFT_WMAC_RESP_MFB_8822B)
-#define BIT_GET_WMAC_RESP_MFB_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B)
-
-#define BIT_SHIFT_WMAC_ANTINF_SEL_8822B 23
-#define BIT_MASK_WMAC_ANTINF_SEL_8822B 0x3
-#define BIT_WMAC_ANTINF_SEL_8822B(x) \
- (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B) \
- << BIT_SHIFT_WMAC_ANTINF_SEL_8822B)
-#define BIT_GET_WMAC_ANTINF_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) & \
- BIT_MASK_WMAC_ANTINF_SEL_8822B)
-
-#define BIT_SHIFT_WMAC_ANTSEL_SEL_8822B 21
-#define BIT_MASK_WMAC_ANTSEL_SEL_8822B 0x3
-#define BIT_WMAC_ANTSEL_SEL_8822B(x) \
- (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) \
- << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B)
-#define BIT_GET_WMAC_ANTSEL_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) & \
- BIT_MASK_WMAC_ANTSEL_SEL_8822B)
-
-#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B 18
-#define BIT_MASK_R_WMAC_RESP_TXPOWER_8822B 0x7
-#define BIT_R_WMAC_RESP_TXPOWER_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) \
- << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B)
-#define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) & \
- BIT_MASK_R_WMAC_RESP_TXPOWER_8822B)
-
-#define BIT_SHIFT_WMAC_RESP_TXANT_8822B 0
-#define BIT_MASK_WMAC_RESP_TXANT_8822B 0x3ffff
-#define BIT_WMAC_RESP_TXANT_8822B(x) \
- (((x) & BIT_MASK_WMAC_RESP_TXANT_8822B) \
- << BIT_SHIFT_WMAC_RESP_TXANT_8822B)
-#define BIT_GET_WMAC_RESP_TXANT_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) & \
- BIT_MASK_WMAC_RESP_TXANT_8822B)
-
-/* 2 REG_BBPSF_CTRL_8822B */
-#define BIT_CTL_IDLE_CLR_CSI_RPT_8822B BIT(31)
-#define BIT_WMAC_USE_NDPARATE_8822B BIT(30)
-
-#define BIT_SHIFT_WMAC_CSI_RATE_8822B 24
-#define BIT_MASK_WMAC_CSI_RATE_8822B 0x3f
-#define BIT_WMAC_CSI_RATE_8822B(x) \
- (((x) & BIT_MASK_WMAC_CSI_RATE_8822B) << BIT_SHIFT_WMAC_CSI_RATE_8822B)
-#define BIT_GET_WMAC_CSI_RATE_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B)
-
-#define BIT_SHIFT_WMAC_RESP_TXRATE_8822B 16
-#define BIT_MASK_WMAC_RESP_TXRATE_8822B 0xff
-#define BIT_WMAC_RESP_TXRATE_8822B(x) \
- (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B) \
- << BIT_SHIFT_WMAC_RESP_TXRATE_8822B)
-#define BIT_GET_WMAC_RESP_TXRATE_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) & \
- BIT_MASK_WMAC_RESP_TXRATE_8822B)
-
-#define BIT_BBPSF_MPDUCHKEN_8822B BIT(5)
-#define BIT_BBPSF_MHCHKEN_8822B BIT(4)
-#define BIT_BBPSF_ERRCHKEN_8822B BIT(3)
-
-#define BIT_SHIFT_BBPSF_ERRTHR_8822B 0
-#define BIT_MASK_BBPSF_ERRTHR_8822B 0x7
-#define BIT_BBPSF_ERRTHR_8822B(x) \
- (((x) & BIT_MASK_BBPSF_ERRTHR_8822B) << BIT_SHIFT_BBPSF_ERRTHR_8822B)
-#define BIT_GET_BBPSF_ERRTHR_8822B(x) \
- (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_P2P_RX_BCN_NOA_8822B (P2P RX BEACON NOA REGISTER) */
-#define BIT_NOA_PARSER_EN_8822B BIT(15)
-#define BIT_BSSID_SEL_8822B BIT(14)
-
-#define BIT_SHIFT_P2P_OUI_TYPE_8822B 0
-#define BIT_MASK_P2P_OUI_TYPE_8822B 0xff
-#define BIT_P2P_OUI_TYPE_8822B(x) \
- (((x) & BIT_MASK_P2P_OUI_TYPE_8822B) << BIT_SHIFT_P2P_OUI_TYPE_8822B)
-#define BIT_GET_P2P_OUI_TYPE_8822B(x) \
- (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B)
-
-/* 2 REG_ASSOCIATED_BFMER0_INFO_8822B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
-
-#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_TXCSI_AID0_8822B 0x1ff
-#define BIT_R_WMAC_TXCSI_AID0_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) \
- << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B)
-#define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) & \
- BIT_MASK_R_WMAC_TXCSI_AID0_8822B)
-
-#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B 0
-#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) \
- << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) & \
- BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B)
-
-/* 2 REG_ASSOCIATED_BFMER1_INFO_8822B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
-
-#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_TXCSI_AID1_8822B 0x1ff
-#define BIT_R_WMAC_TXCSI_AID1_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) \
- << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B)
-#define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) & \
- BIT_MASK_R_WMAC_TXCSI_AID1_8822B)
-
-#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B 0
-#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) \
- << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) & \
- BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B)
-
-/* 2 REG_TX_CSI_RPT_PARAM_BW20_8822B (TX CSI REPORT PARAMETER REGISTER) */
-
-#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B 16
-#define BIT_MASK_R_WMAC_BFINFO_20M_1_8822B 0xfff
-#define BIT_R_WMAC_BFINFO_20M_1_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) \
- << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B)
-#define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) & \
- BIT_MASK_R_WMAC_BFINFO_20M_1_8822B)
-
-#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B 0
-#define BIT_MASK_R_WMAC_BFINFO_20M_0_8822B 0xfff
-#define BIT_R_WMAC_BFINFO_20M_0_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) \
- << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B)
-#define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) & \
- BIT_MASK_R_WMAC_BFINFO_20M_0_8822B)
-
-/* 2 REG_TX_CSI_RPT_PARAM_BW40_8822B (TX CSI REPORT PARAMETER_BW40 REGISTER) */
-
-#define BIT_SHIFT_WMAC_RESP_ANTCD_8822B 0
-#define BIT_MASK_WMAC_RESP_ANTCD_8822B 0xf
-#define BIT_WMAC_RESP_ANTCD_8822B(x) \
- (((x) & BIT_MASK_WMAC_RESP_ANTCD_8822B) \
- << BIT_SHIFT_WMAC_RESP_ANTCD_8822B)
-#define BIT_GET_WMAC_RESP_ANTCD_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) & \
- BIT_MASK_WMAC_RESP_ANTCD_8822B)
-
-/* 2 REG_TX_CSI_RPT_PARAM_BW80_8822B (TX CSI REPORT PARAMETER_BW80 REGISTER) */
-
-/* 2 REG_BCN_PSR_RPT2_8822B (BEACON PARSER REPORT REGISTER2) */
-
-#define BIT_SHIFT_DTIM_CNT2_8822B 24
-#define BIT_MASK_DTIM_CNT2_8822B 0xff
-#define BIT_DTIM_CNT2_8822B(x) \
- (((x) & BIT_MASK_DTIM_CNT2_8822B) << BIT_SHIFT_DTIM_CNT2_8822B)
-#define BIT_GET_DTIM_CNT2_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B)
-
-#define BIT_SHIFT_DTIM_PERIOD2_8822B 16
-#define BIT_MASK_DTIM_PERIOD2_8822B 0xff
-#define BIT_DTIM_PERIOD2_8822B(x) \
- (((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B)
-#define BIT_GET_DTIM_PERIOD2_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B)
-
-#define BIT_DTIM2_8822B BIT(15)
-#define BIT_TIM2_8822B BIT(14)
-
-#define BIT_SHIFT_PS_AID_2_8822B 0
-#define BIT_MASK_PS_AID_2_8822B 0x7ff
-#define BIT_PS_AID_2_8822B(x) \
- (((x) & BIT_MASK_PS_AID_2_8822B) << BIT_SHIFT_PS_AID_2_8822B)
-#define BIT_GET_PS_AID_2_8822B(x) \
- (((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B)
-
-/* 2 REG_BCN_PSR_RPT3_8822B (BEACON PARSER REPORT REGISTER3) */
-
-#define BIT_SHIFT_DTIM_CNT3_8822B 24
-#define BIT_MASK_DTIM_CNT3_8822B 0xff
-#define BIT_DTIM_CNT3_8822B(x) \
- (((x) & BIT_MASK_DTIM_CNT3_8822B) << BIT_SHIFT_DTIM_CNT3_8822B)
-#define BIT_GET_DTIM_CNT3_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B)
-
-#define BIT_SHIFT_DTIM_PERIOD3_8822B 16
-#define BIT_MASK_DTIM_PERIOD3_8822B 0xff
-#define BIT_DTIM_PERIOD3_8822B(x) \
- (((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B)
-#define BIT_GET_DTIM_PERIOD3_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B)
-
-#define BIT_DTIM3_8822B BIT(15)
-#define BIT_TIM3_8822B BIT(14)
-
-#define BIT_SHIFT_PS_AID_3_8822B 0
-#define BIT_MASK_PS_AID_3_8822B 0x7ff
-#define BIT_PS_AID_3_8822B(x) \
- (((x) & BIT_MASK_PS_AID_3_8822B) << BIT_SHIFT_PS_AID_3_8822B)
-#define BIT_GET_PS_AID_3_8822B(x) \
- (((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B)
-
-/* 2 REG_BCN_PSR_RPT4_8822B (BEACON PARSER REPORT REGISTER4) */
-
-#define BIT_SHIFT_DTIM_CNT4_8822B 24
-#define BIT_MASK_DTIM_CNT4_8822B 0xff
-#define BIT_DTIM_CNT4_8822B(x) \
- (((x) & BIT_MASK_DTIM_CNT4_8822B) << BIT_SHIFT_DTIM_CNT4_8822B)
-#define BIT_GET_DTIM_CNT4_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B)
-
-#define BIT_SHIFT_DTIM_PERIOD4_8822B 16
-#define BIT_MASK_DTIM_PERIOD4_8822B 0xff
-#define BIT_DTIM_PERIOD4_8822B(x) \
- (((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B)
-#define BIT_GET_DTIM_PERIOD4_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B)
-
-#define BIT_DTIM4_8822B BIT(15)
-#define BIT_TIM4_8822B BIT(14)
-
-#define BIT_SHIFT_PS_AID_4_8822B 0
-#define BIT_MASK_PS_AID_4_8822B 0x7ff
-#define BIT_PS_AID_4_8822B(x) \
- (((x) & BIT_MASK_PS_AID_4_8822B) << BIT_SHIFT_PS_AID_4_8822B)
-#define BIT_GET_PS_AID_4_8822B(x) \
- (((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B)
-
-/* 2 REG_A1_ADDR_MASK_8822B (A1 ADDR MASK REGISTER) */
-
-#define BIT_SHIFT_A1_ADDR_MASK_8822B 0
-#define BIT_MASK_A1_ADDR_MASK_8822B 0xffffffffL
-#define BIT_A1_ADDR_MASK_8822B(x) \
- (((x) & BIT_MASK_A1_ADDR_MASK_8822B) << BIT_SHIFT_A1_ADDR_MASK_8822B)
-#define BIT_GET_A1_ADDR_MASK_8822B(x) \
- (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B)
-
-/* 2 REG_MACID2_8822B (MAC ID2 REGISTER) */
-
-#define BIT_SHIFT_MACID2_8822B 0
-#define BIT_MASK_MACID2_8822B 0xffffffffffffL
-#define BIT_MACID2_8822B(x) \
- (((x) & BIT_MASK_MACID2_8822B) << BIT_SHIFT_MACID2_8822B)
-#define BIT_GET_MACID2_8822B(x) \
- (((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B)
-
-/* 2 REG_BSSID2_8822B (BSSID2 REGISTER) */
-
-#define BIT_SHIFT_BSSID2_8822B 0
-#define BIT_MASK_BSSID2_8822B 0xffffffffffffL
-#define BIT_BSSID2_8822B(x) \
- (((x) & BIT_MASK_BSSID2_8822B) << BIT_SHIFT_BSSID2_8822B)
-#define BIT_GET_BSSID2_8822B(x) \
- (((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B)
-
-/* 2 REG_MACID3_8822B (MAC ID3 REGISTER) */
-
-#define BIT_SHIFT_MACID3_8822B 0
-#define BIT_MASK_MACID3_8822B 0xffffffffffffL
-#define BIT_MACID3_8822B(x) \
- (((x) & BIT_MASK_MACID3_8822B) << BIT_SHIFT_MACID3_8822B)
-#define BIT_GET_MACID3_8822B(x) \
- (((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B)
-
-/* 2 REG_BSSID3_8822B (BSSID3 REGISTER) */
-
-#define BIT_SHIFT_BSSID3_8822B 0
-#define BIT_MASK_BSSID3_8822B 0xffffffffffffL
-#define BIT_BSSID3_8822B(x) \
- (((x) & BIT_MASK_BSSID3_8822B) << BIT_SHIFT_BSSID3_8822B)
-#define BIT_GET_BSSID3_8822B(x) \
- (((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B)
-
-/* 2 REG_MACID4_8822B (MAC ID4 REGISTER) */
-
-#define BIT_SHIFT_MACID4_8822B 0
-#define BIT_MASK_MACID4_8822B 0xffffffffffffL
-#define BIT_MACID4_8822B(x) \
- (((x) & BIT_MASK_MACID4_8822B) << BIT_SHIFT_MACID4_8822B)
-#define BIT_GET_MACID4_8822B(x) \
- (((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B)
-
-/* 2 REG_BSSID4_8822B (BSSID4 REGISTER) */
-
-#define BIT_SHIFT_BSSID4_8822B 0
-#define BIT_MASK_BSSID4_8822B 0xffffffffffffL
-#define BIT_BSSID4_8822B(x) \
- (((x) & BIT_MASK_BSSID4_8822B) << BIT_SHIFT_BSSID4_8822B)
-#define BIT_GET_BSSID4_8822B(x) \
- (((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B)
-
-/* 2 REG_NOA_REPORT_8822B */
-
-/* 2 REG_PWRBIT_SETTING_8822B */
-#define BIT_CLI3_PWRBIT_OW_EN_8822B BIT(7)
-#define BIT_CLI3_PWR_ST_8822B BIT(6)
-#define BIT_CLI2_PWRBIT_OW_EN_8822B BIT(5)
-#define BIT_CLI2_PWR_ST_8822B BIT(4)
-#define BIT_CLI1_PWRBIT_OW_EN_8822B BIT(3)
-#define BIT_CLI1_PWR_ST_8822B BIT(2)
-#define BIT_CLI0_PWRBIT_OW_EN_8822B BIT(1)
-#define BIT_CLI0_PWR_ST_8822B BIT(0)
-
-/* 2 REG_WMAC_MU_BF_OPTION_8822B */
-#define BIT_WMAC_RESP_NONSTA1_DIS_8822B BIT(7)
-#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8822B BIT(6)
-
-#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B 4
-#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B 0x3
-#define BIT_WMAC_TXMU_ACKPOLICY_8822B(x) \
- (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) \
- << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B)
-#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) & \
- BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B)
-
-#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B 1
-#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B 0x7
-#define BIT_WMAC_MU_BFEE_PORT_SEL_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) \
- << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B)
-#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) & \
- BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B)
-
-#define BIT_WMAC_MU_BFEE_DIS_8822B BIT(0)
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B 0
-#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B 0xff
-#define BIT_WMAC_PAUSE_BB_CLR_TH_8822B(x) \
- (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) \
- << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B)
-#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) & \
- BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B)
-
-/* 2 REG_WMAC_MU_ARB_8822B */
-#define BIT_WMAC_ARB_HW_ADAPT_EN_8822B BIT(7)
-#define BIT_WMAC_ARB_SW_EN_8822B BIT(6)
-
-#define BIT_SHIFT_WMAC_ARB_SW_STATE_8822B 0
-#define BIT_MASK_WMAC_ARB_SW_STATE_8822B 0x3f
-#define BIT_WMAC_ARB_SW_STATE_8822B(x) \
- (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) \
- << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B)
-#define BIT_GET_WMAC_ARB_SW_STATE_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) & \
- BIT_MASK_WMAC_ARB_SW_STATE_8822B)
-
-/* 2 REG_WMAC_MU_OPTION_8822B */
-
-#define BIT_SHIFT_WMAC_MU_DBGSEL_8822B 5
-#define BIT_MASK_WMAC_MU_DBGSEL_8822B 0x3
-#define BIT_WMAC_MU_DBGSEL_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_DBGSEL_8822B) \
- << BIT_SHIFT_WMAC_MU_DBGSEL_8822B)
-#define BIT_GET_WMAC_MU_DBGSEL_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8822B) & \
- BIT_MASK_WMAC_MU_DBGSEL_8822B)
-
-#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B 0
-#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B 0x1f
-#define BIT_WMAC_MU_CPRD_TIMEOUT_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) \
- << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B)
-#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) & \
- BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B)
-
-/* 2 REG_WMAC_MU_BF_CTL_8822B */
-#define BIT_WMAC_INVLD_BFPRT_CHK_8822B BIT(15)
-#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822B BIT(14)
-
-#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B 12
-#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B 0x3
-#define BIT_WMAC_MU_BFRPTSEG_SEL_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) \
- << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B)
-#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) & \
- BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B)
-
-#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822B 0
-#define BIT_MASK_WMAC_MU_BF_MYAID_8822B 0xfff
-#define BIT_WMAC_MU_BF_MYAID_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) \
- << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B)
-#define BIT_GET_WMAC_MU_BF_MYAID_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) & \
- BIT_MASK_WMAC_MU_BF_MYAID_8822B)
-
-/* 2 REG_WMAC_MU_BFRPT_PARA_8822B */
-
-#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B 12
-#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B 0x7
-#define BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \
- (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) \
- << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B)
-#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) & \
- BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B)
-
-#define BIT_SHIFT_BFRPT_PARA_8822B 0
-#define BIT_MASK_BFRPT_PARA_8822B 0xfff
-#define BIT_BFRPT_PARA_8822B(x) \
- (((x) & BIT_MASK_BFRPT_PARA_8822B) << BIT_SHIFT_BFRPT_PARA_8822B)
-#define BIT_GET_BFRPT_PARA_8822B(x) \
- (((x) >> BIT_SHIFT_BFRPT_PARA_8822B) & BIT_MASK_BFRPT_PARA_8822B)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B */
-#define BIT_STATUS_BFEE2_8822B BIT(10)
-#define BIT_WMAC_MU_BFEE2_EN_8822B BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B 0
-#define BIT_MASK_WMAC_MU_BFEE2_AID_8822B 0x1ff
-#define BIT_WMAC_MU_BFEE2_AID_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) \
- << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B)
-#define BIT_GET_WMAC_MU_BFEE2_AID_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) & \
- BIT_MASK_WMAC_MU_BFEE2_AID_8822B)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B */
-#define BIT_STATUS_BFEE3_8822B BIT(10)
-#define BIT_WMAC_MU_BFEE3_EN_8822B BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B 0
-#define BIT_MASK_WMAC_MU_BFEE3_AID_8822B 0x1ff
-#define BIT_WMAC_MU_BFEE3_AID_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) \
- << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B)
-#define BIT_GET_WMAC_MU_BFEE3_AID_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) & \
- BIT_MASK_WMAC_MU_BFEE3_AID_8822B)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B */
-#define BIT_STATUS_BFEE4_8822B BIT(10)
-#define BIT_WMAC_MU_BFEE4_EN_8822B BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B 0
-#define BIT_MASK_WMAC_MU_BFEE4_AID_8822B 0x1ff
-#define BIT_WMAC_MU_BFEE4_AID_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) \
- << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B)
-#define BIT_GET_WMAC_MU_BFEE4_AID_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) & \
- BIT_MASK_WMAC_MU_BFEE4_AID_8822B)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B */
-#define BIT_STATUS_BFEE5_8822B BIT(10)
-#define BIT_WMAC_MU_BFEE5_EN_8822B BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B 0
-#define BIT_MASK_WMAC_MU_BFEE5_AID_8822B 0x1ff
-#define BIT_WMAC_MU_BFEE5_AID_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) \
- << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B)
-#define BIT_GET_WMAC_MU_BFEE5_AID_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) & \
- BIT_MASK_WMAC_MU_BFEE5_AID_8822B)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B */
-#define BIT_STATUS_BFEE6_8822B BIT(10)
-#define BIT_WMAC_MU_BFEE6_EN_8822B BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B 0
-#define BIT_MASK_WMAC_MU_BFEE6_AID_8822B 0x1ff
-#define BIT_WMAC_MU_BFEE6_AID_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) \
- << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B)
-#define BIT_GET_WMAC_MU_BFEE6_AID_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) & \
- BIT_MASK_WMAC_MU_BFEE6_AID_8822B)
-
-/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B */
-#define BIT_BIT_STATUS_BFEE4_8822B BIT(10)
-#define BIT_WMAC_MU_BFEE7_EN_8822B BIT(9)
-
-#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B 0
-#define BIT_MASK_WMAC_MU_BFEE7_AID_8822B 0x1ff
-#define BIT_WMAC_MU_BFEE7_AID_8822B(x) \
- (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) \
- << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B)
-#define BIT_GET_WMAC_MU_BFEE7_AID_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) & \
- BIT_MASK_WMAC_MU_BFEE7_AID_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-#define BIT_RST_ALL_COUNTER_8822B BIT(31)
-
-#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B 16
-#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822B 0xff
-#define BIT_ABORT_RX_VBON_COUNTER_8822B(x) \
- (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) \
- << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B)
-#define BIT_GET_ABORT_RX_VBON_COUNTER_8822B(x) \
- (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) & \
- BIT_MASK_ABORT_RX_VBON_COUNTER_8822B)
-
-#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B 8
-#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B 0xff
-#define BIT_ABORT_RX_RDRDY_COUNTER_8822B(x) \
- (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) \
- << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B)
-#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822B(x) \
- (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) & \
- BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B)
-
-#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B 0
-#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B 0xff
-#define BIT_VBON_EARLY_FALLING_COUNTER_8822B(x) \
- (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) \
- << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B)
-#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822B(x) \
- (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) & \
- BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-#define BIT_WMAC_PLCP_TRX_SEL_8822B BIT(31)
-
-#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B 28
-#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B 0x7
-#define BIT_WMAC_PLCP_RDSIG_SEL_8822B(x) \
- (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) \
- << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B)
-#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) & \
- BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B)
-
-#define BIT_SHIFT_WMAC_RATE_IDX_8822B 24
-#define BIT_MASK_WMAC_RATE_IDX_8822B 0xf
-#define BIT_WMAC_RATE_IDX_8822B(x) \
- (((x) & BIT_MASK_WMAC_RATE_IDX_8822B) << BIT_SHIFT_WMAC_RATE_IDX_8822B)
-#define BIT_GET_WMAC_RATE_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822B) & BIT_MASK_WMAC_RATE_IDX_8822B)
-
-#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0
-#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff
-#define BIT_WMAC_PLCP_RDSIG_8822B(x) \
- (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) \
- << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
-#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & \
- BIT_MASK_WMAC_PLCP_RDSIG_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-#define BIT_WMAC_MUTX_IDX_8822B BIT(24)
-
-#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0
-#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff
-#define BIT_WMAC_PLCP_RDSIG_8822B(x) \
- (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) \
- << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
-#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & \
- BIT_MASK_WMAC_PLCP_RDSIG_8822B)
-
-/* 2 REG_TRANSMIT_ADDRSS_0_8822B (TA0 REGISTER) */
-
-#define BIT_SHIFT_TA0_8822B 0
-#define BIT_MASK_TA0_8822B 0xffffffffffffL
-#define BIT_TA0_8822B(x) (((x) & BIT_MASK_TA0_8822B) << BIT_SHIFT_TA0_8822B)
-#define BIT_GET_TA0_8822B(x) (((x) >> BIT_SHIFT_TA0_8822B) & BIT_MASK_TA0_8822B)
-
-/* 2 REG_TRANSMIT_ADDRSS_1_8822B (TA1 REGISTER) */
-
-#define BIT_SHIFT_TA1_8822B 0
-#define BIT_MASK_TA1_8822B 0xffffffffffffL
-#define BIT_TA1_8822B(x) (((x) & BIT_MASK_TA1_8822B) << BIT_SHIFT_TA1_8822B)
-#define BIT_GET_TA1_8822B(x) (((x) >> BIT_SHIFT_TA1_8822B) & BIT_MASK_TA1_8822B)
-
-/* 2 REG_TRANSMIT_ADDRSS_2_8822B (TA2 REGISTER) */
-
-#define BIT_SHIFT_TA2_8822B 0
-#define BIT_MASK_TA2_8822B 0xffffffffffffL
-#define BIT_TA2_8822B(x) (((x) & BIT_MASK_TA2_8822B) << BIT_SHIFT_TA2_8822B)
-#define BIT_GET_TA2_8822B(x) (((x) >> BIT_SHIFT_TA2_8822B) & BIT_MASK_TA2_8822B)
-
-/* 2 REG_TRANSMIT_ADDRSS_3_8822B (TA3 REGISTER) */
-
-#define BIT_SHIFT_TA3_8822B 0
-#define BIT_MASK_TA3_8822B 0xffffffffffffL
-#define BIT_TA3_8822B(x) (((x) & BIT_MASK_TA3_8822B) << BIT_SHIFT_TA3_8822B)
-#define BIT_GET_TA3_8822B(x) (((x) >> BIT_SHIFT_TA3_8822B) & BIT_MASK_TA3_8822B)
-
-/* 2 REG_TRANSMIT_ADDRSS_4_8822B (TA4 REGISTER) */
-
-#define BIT_SHIFT_TA4_8822B 0
-#define BIT_MASK_TA4_8822B 0xffffffffffffL
-#define BIT_TA4_8822B(x) (((x) & BIT_MASK_TA4_8822B) << BIT_SHIFT_TA4_8822B)
-#define BIT_GET_TA4_8822B(x) (((x) >> BIT_SHIFT_TA4_8822B) & BIT_MASK_TA4_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_MACID1_8822B */
-
-#define BIT_SHIFT_MACID1_8822B 0
-#define BIT_MASK_MACID1_8822B 0xffffffffffffL
-#define BIT_MACID1_8822B(x) \
- (((x) & BIT_MASK_MACID1_8822B) << BIT_SHIFT_MACID1_8822B)
-#define BIT_GET_MACID1_8822B(x) \
- (((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B)
-
-/* 2 REG_BSSID1_8822B */
-
-#define BIT_SHIFT_BSSID1_8822B 0
-#define BIT_MASK_BSSID1_8822B 0xffffffffffffL
-#define BIT_BSSID1_8822B(x) \
- (((x) & BIT_MASK_BSSID1_8822B) << BIT_SHIFT_BSSID1_8822B)
-#define BIT_GET_BSSID1_8822B(x) \
- (((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B)
-
-/* 2 REG_BCN_PSR_RPT1_8822B */
-
-#define BIT_SHIFT_DTIM_CNT1_8822B 24
-#define BIT_MASK_DTIM_CNT1_8822B 0xff
-#define BIT_DTIM_CNT1_8822B(x) \
- (((x) & BIT_MASK_DTIM_CNT1_8822B) << BIT_SHIFT_DTIM_CNT1_8822B)
-#define BIT_GET_DTIM_CNT1_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B)
-
-#define BIT_SHIFT_DTIM_PERIOD1_8822B 16
-#define BIT_MASK_DTIM_PERIOD1_8822B 0xff
-#define BIT_DTIM_PERIOD1_8822B(x) \
- (((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B)
-#define BIT_GET_DTIM_PERIOD1_8822B(x) \
- (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B)
-
-#define BIT_DTIM1_8822B BIT(15)
-#define BIT_TIM1_8822B BIT(14)
-
-#define BIT_SHIFT_PS_AID_1_8822B 0
-#define BIT_MASK_PS_AID_1_8822B 0x7ff
-#define BIT_PS_AID_1_8822B(x) \
- (((x) & BIT_MASK_PS_AID_1_8822B) << BIT_SHIFT_PS_AID_1_8822B)
-#define BIT_GET_PS_AID_1_8822B(x) \
- (((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B)
-
-/* 2 REG_ASSOCIATED_BFMEE_SEL_8822B */
-#define BIT_TXUSER_ID1_8822B BIT(25)
-
-#define BIT_SHIFT_AID1_8822B 16
-#define BIT_MASK_AID1_8822B 0x1ff
-#define BIT_AID1_8822B(x) (((x) & BIT_MASK_AID1_8822B) << BIT_SHIFT_AID1_8822B)
-#define BIT_GET_AID1_8822B(x) \
- (((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B)
-
-#define BIT_TXUSER_ID0_8822B BIT(9)
-
-#define BIT_SHIFT_AID0_8822B 0
-#define BIT_MASK_AID0_8822B 0x1ff
-#define BIT_AID0_8822B(x) (((x) & BIT_MASK_AID0_8822B) << BIT_SHIFT_AID0_8822B)
-#define BIT_GET_AID0_8822B(x) \
- (((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B)
-
-/* 2 REG_SND_PTCL_CTRL_8822B */
-
-#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B 24
-#define BIT_MASK_NDP_RX_STANDBY_TIMER_8822B 0xff
-#define BIT_NDP_RX_STANDBY_TIMER_8822B(x) \
- (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) \
- << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B)
-#define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x) \
- (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) & \
- BIT_MASK_NDP_RX_STANDBY_TIMER_8822B)
-
-#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B 16
-#define BIT_MASK_CSI_RPT_OFFSET_HT_8822B 0xff
-#define BIT_CSI_RPT_OFFSET_HT_8822B(x) \
- (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8822B) \
- << BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B)
-#define BIT_GET_CSI_RPT_OFFSET_HT_8822B(x) \
- (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B) & \
- BIT_MASK_CSI_RPT_OFFSET_HT_8822B)
-
-#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B 8
-#define BIT_MASK_R_WMAC_VHT_CATEGORY_8822B 0xff
-#define BIT_R_WMAC_VHT_CATEGORY_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8822B) \
- << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B)
-#define BIT_GET_R_WMAC_VHT_CATEGORY_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B) & \
- BIT_MASK_R_WMAC_VHT_CATEGORY_8822B)
-
-#define BIT_R_WMAC_USE_NSTS_8822B BIT(7)
-#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822B BIT(6)
-#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8822B BIT(5)
-#define BIT_R_WMAC_BFPARAM_SEL_8822B BIT(4)
-#define BIT_R_WMAC_CSISEQ_SEL_8822B BIT(3)
-#define BIT_R_WMAC_CSI_WITHHTC_EN_8822B BIT(2)
-#define BIT_R_WMAC_HT_NDPA_EN_8822B BIT(1)
-#define BIT_R_WMAC_VHT_NDPA_EN_8822B BIT(0)
-
-/* 2 REG_RX_CSI_RPT_INFO_8822B */
-
-/* 2 REG_NS_ARP_CTRL_8822B */
-#define BIT_R_WMAC_NSARP_RSPEN_8822B BIT(15)
-#define BIT_R_WMAC_NSARP_RARP_8822B BIT(9)
-#define BIT_R_WMAC_NSARP_RIPV6_8822B BIT(8)
-
-#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B 6
-#define BIT_MASK_R_WMAC_NSARP_MODEN_8822B 0x3
-#define BIT_R_WMAC_NSARP_MODEN_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) \
- << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B)
-#define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) & \
- BIT_MASK_R_WMAC_NSARP_MODEN_8822B)
-
-#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B 4
-#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B 0x3
-#define BIT_R_WMAC_NSARP_RSPFTP_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) \
- << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B)
-#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) & \
- BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B)
-
-#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B 0
-#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B 0xf
-#define BIT_R_WMAC_NSARP_RSPSEC_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) \
- << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B)
-#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) & \
- BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B)
-
-/* 2 REG_NS_ARP_INFO_8822B */
-#define BIT_REQ_IS_MCNS_8822B BIT(23)
-#define BIT_REQ_IS_UCNS_8822B BIT(22)
-#define BIT_REQ_IS_USNS_8822B BIT(21)
-#define BIT_REQ_IS_ARP_8822B BIT(20)
-#define BIT_EXPRSP_MH_WITHQC_8822B BIT(19)
-
-#define BIT_SHIFT_EXPRSP_SECTYPE_8822B 16
-#define BIT_MASK_EXPRSP_SECTYPE_8822B 0x7
-#define BIT_EXPRSP_SECTYPE_8822B(x) \
- (((x) & BIT_MASK_EXPRSP_SECTYPE_8822B) \
- << BIT_SHIFT_EXPRSP_SECTYPE_8822B)
-#define BIT_GET_EXPRSP_SECTYPE_8822B(x) \
- (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) & \
- BIT_MASK_EXPRSP_SECTYPE_8822B)
-
-#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B 8
-#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B 0xff
-#define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x) \
- (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) \
- << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B)
-#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x) \
- (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) & \
- BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B)
-
-#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B 0
-#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B 0xff
-#define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x) \
- (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) \
- << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B)
-#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x) \
- (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) & \
- BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B)
-
-/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822B */
-
-#define BIT_SHIFT_WMAC_ARPIP_8822B 0
-#define BIT_MASK_WMAC_ARPIP_8822B 0xffffffffL
-#define BIT_WMAC_ARPIP_8822B(x) \
- (((x) & BIT_MASK_WMAC_ARPIP_8822B) << BIT_SHIFT_WMAC_ARPIP_8822B)
-#define BIT_GET_WMAC_ARPIP_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B)
-
-/* 2 REG_BEAMFORMING_INFO_NSARP_8822B */
-
-#define BIT_SHIFT_BEAMFORMING_INFO_8822B 0
-#define BIT_MASK_BEAMFORMING_INFO_8822B 0xffffffffL
-#define BIT_BEAMFORMING_INFO_8822B(x) \
- (((x) & BIT_MASK_BEAMFORMING_INFO_8822B) \
- << BIT_SHIFT_BEAMFORMING_INFO_8822B)
-#define BIT_GET_BEAMFORMING_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) & \
- BIT_MASK_BEAMFORMING_INFO_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B 0
-#define BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B 0xffffffffffffffffffffffffffffffffL
-#define BIT_R_WMAC_IPV6_MYIPAD_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) \
- << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B)
-#define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) & \
- BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B)
-
-/* 2 REG_RSVD_0X740_8822B */
-
-/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B */
-
-#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B 4
-#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B 0xf
-#define BIT_R_WMAC_CTX_SUBTYPE_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) \
- << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B)
-#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) & \
- BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B)
-
-#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B 0
-#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B 0xf
-#define BIT_R_WMAC_RTX_SUBTYPE_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) \
- << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B)
-#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) & \
- BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B)
-
-/* 2 REG_WMAC_SWAES_CFG_8822B */
-
-/* 2 REG_BT_COEX_V2_8822B */
-#define BIT_GNT_BT_POLARITY_8822B BIT(12)
-#define BIT_GNT_BT_BYPASS_PRIORITY_8822B BIT(8)
-
-#define BIT_SHIFT_TIMER_8822B 0
-#define BIT_MASK_TIMER_8822B 0xff
-#define BIT_TIMER_8822B(x) \
- (((x) & BIT_MASK_TIMER_8822B) << BIT_SHIFT_TIMER_8822B)
-#define BIT_GET_TIMER_8822B(x) \
- (((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B)
-
-/* 2 REG_BT_COEX_8822B */
-#define BIT_R_GNT_BT_RFC_SW_8822B BIT(12)
-#define BIT_R_GNT_BT_RFC_SW_EN_8822B BIT(11)
-#define BIT_R_GNT_BT_BB_SW_8822B BIT(10)
-#define BIT_R_GNT_BT_BB_SW_EN_8822B BIT(9)
-#define BIT_R_BT_CNT_THREN_8822B BIT(8)
-
-#define BIT_SHIFT_R_BT_CNT_THR_8822B 0
-#define BIT_MASK_R_BT_CNT_THR_8822B 0xff
-#define BIT_R_BT_CNT_THR_8822B(x) \
- (((x) & BIT_MASK_R_BT_CNT_THR_8822B) << BIT_SHIFT_R_BT_CNT_THR_8822B)
-#define BIT_GET_R_BT_CNT_THR_8822B(x) \
- (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B)
-
-/* 2 REG_WLAN_ACT_MASK_CTRL_8822B */
-#define BIT_WLRX_TER_BY_CTL_8822B BIT(43)
-#define BIT_WLRX_TER_BY_AD_8822B BIT(42)
-#define BIT_ANT_DIVERSITY_SEL_8822B BIT(41)
-#define BIT_ANTSEL_FOR_BT_CTRL_EN_8822B BIT(40)
-#define BIT_WLACT_LOW_GNTWL_EN_8822B BIT(34)
-#define BIT_WLACT_HIGH_GNTBT_EN_8822B BIT(33)
-#define BIT_NAV_UPPER_V1_8822B BIT(32)
-
-#define BIT_SHIFT_RXMYRTS_NAV_V1_8822B 8
-#define BIT_MASK_RXMYRTS_NAV_V1_8822B 0xff
-#define BIT_RXMYRTS_NAV_V1_8822B(x) \
- (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822B) \
- << BIT_SHIFT_RXMYRTS_NAV_V1_8822B)
-#define BIT_GET_RXMYRTS_NAV_V1_8822B(x) \
- (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) & \
- BIT_MASK_RXMYRTS_NAV_V1_8822B)
-
-#define BIT_SHIFT_RTSRST_V1_8822B 0
-#define BIT_MASK_RTSRST_V1_8822B 0xff
-#define BIT_RTSRST_V1_8822B(x) \
- (((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B)
-#define BIT_GET_RTSRST_V1_8822B(x) \
- (((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B)
-
-/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822B */
-
-#define BIT_SHIFT_BT_STAT_DELAY_8822B 12
-#define BIT_MASK_BT_STAT_DELAY_8822B 0xf
-#define BIT_BT_STAT_DELAY_8822B(x) \
- (((x) & BIT_MASK_BT_STAT_DELAY_8822B) << BIT_SHIFT_BT_STAT_DELAY_8822B)
-#define BIT_GET_BT_STAT_DELAY_8822B(x) \
- (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B)
-
-#define BIT_SHIFT_BT_TRX_INIT_DETECT_8822B 8
-#define BIT_MASK_BT_TRX_INIT_DETECT_8822B 0xf
-#define BIT_BT_TRX_INIT_DETECT_8822B(x) \
- (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) \
- << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B)
-#define BIT_GET_BT_TRX_INIT_DETECT_8822B(x) \
- (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) & \
- BIT_MASK_BT_TRX_INIT_DETECT_8822B)
-
-#define BIT_SHIFT_BT_PRI_DETECT_TO_8822B 4
-#define BIT_MASK_BT_PRI_DETECT_TO_8822B 0xf
-#define BIT_BT_PRI_DETECT_TO_8822B(x) \
- (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B) \
- << BIT_SHIFT_BT_PRI_DETECT_TO_8822B)
-#define BIT_GET_BT_PRI_DETECT_TO_8822B(x) \
- (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) & \
- BIT_MASK_BT_PRI_DETECT_TO_8822B)
-
-#define BIT_R_GRANTALL_WLMASK_8822B BIT(3)
-#define BIT_STATIS_BT_EN_8822B BIT(2)
-#define BIT_WL_ACT_MASK_ENABLE_8822B BIT(1)
-#define BIT_ENHANCED_BT_8822B BIT(0)
-
-/* 2 REG_BT_ACT_STATISTICS_8822B */
-
-#define BIT_SHIFT_STATIS_BT_LO_RX_8822B (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_STATIS_BT_LO_RX_8822B 0xffff
-#define BIT_STATIS_BT_LO_RX_8822B(x) \
- (((x) & BIT_MASK_STATIS_BT_LO_RX_8822B) \
- << BIT_SHIFT_STATIS_BT_LO_RX_8822B)
-#define BIT_GET_STATIS_BT_LO_RX_8822B(x) \
- (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) & \
- BIT_MASK_STATIS_BT_LO_RX_8822B)
-
-#define BIT_SHIFT_STATIS_BT_LO_TX_8822B (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_STATIS_BT_LO_TX_8822B 0xffff
-#define BIT_STATIS_BT_LO_TX_8822B(x) \
- (((x) & BIT_MASK_STATIS_BT_LO_TX_8822B) \
- << BIT_SHIFT_STATIS_BT_LO_TX_8822B)
-#define BIT_GET_STATIS_BT_LO_TX_8822B(x) \
- (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) & \
- BIT_MASK_STATIS_BT_LO_TX_8822B)
-
-#define BIT_SHIFT_STATIS_BT_HI_RX_8822B 16
-#define BIT_MASK_STATIS_BT_HI_RX_8822B 0xffff
-#define BIT_STATIS_BT_HI_RX_8822B(x) \
- (((x) & BIT_MASK_STATIS_BT_HI_RX_8822B) \
- << BIT_SHIFT_STATIS_BT_HI_RX_8822B)
-#define BIT_GET_STATIS_BT_HI_RX_8822B(x) \
- (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) & \
- BIT_MASK_STATIS_BT_HI_RX_8822B)
-
-#define BIT_SHIFT_STATIS_BT_HI_TX_8822B 0
-#define BIT_MASK_STATIS_BT_HI_TX_8822B 0xffff
-#define BIT_STATIS_BT_HI_TX_8822B(x) \
- (((x) & BIT_MASK_STATIS_BT_HI_TX_8822B) \
- << BIT_SHIFT_STATIS_BT_HI_TX_8822B)
-#define BIT_GET_STATIS_BT_HI_TX_8822B(x) \
- (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) & \
- BIT_MASK_STATIS_BT_HI_TX_8822B)
-
-/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822B */
-
-#define BIT_SHIFT_R_BT_CMD_RPT_8822B 16
-#define BIT_MASK_R_BT_CMD_RPT_8822B 0xffff
-#define BIT_R_BT_CMD_RPT_8822B(x) \
- (((x) & BIT_MASK_R_BT_CMD_RPT_8822B) << BIT_SHIFT_R_BT_CMD_RPT_8822B)
-#define BIT_GET_R_BT_CMD_RPT_8822B(x) \
- (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B)
-
-#define BIT_SHIFT_R_RPT_FROM_BT_8822B 8
-#define BIT_MASK_R_RPT_FROM_BT_8822B 0xff
-#define BIT_R_RPT_FROM_BT_8822B(x) \
- (((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B)
-#define BIT_GET_R_RPT_FROM_BT_8822B(x) \
- (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B)
-
-#define BIT_SHIFT_BT_HID_ISR_SET_8822B 6
-#define BIT_MASK_BT_HID_ISR_SET_8822B 0x3
-#define BIT_BT_HID_ISR_SET_8822B(x) \
- (((x) & BIT_MASK_BT_HID_ISR_SET_8822B) \
- << BIT_SHIFT_BT_HID_ISR_SET_8822B)
-#define BIT_GET_BT_HID_ISR_SET_8822B(x) \
- (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) & \
- BIT_MASK_BT_HID_ISR_SET_8822B)
-
-#define BIT_TDMA_BT_START_NOTIFY_8822B BIT(5)
-#define BIT_ENABLE_TDMA_FW_MODE_8822B BIT(4)
-#define BIT_ENABLE_PTA_TDMA_MODE_8822B BIT(3)
-#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8822B BIT(2)
-#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8822B BIT(1)
-#define BIT_RTK_BT_ENABLE_8822B BIT(0)
-
-/* 2 REG_BT_STATUS_REPORT_REGISTER_8822B */
-
-#define BIT_SHIFT_BT_PROFILE_8822B 24
-#define BIT_MASK_BT_PROFILE_8822B 0xff
-#define BIT_BT_PROFILE_8822B(x) \
- (((x) & BIT_MASK_BT_PROFILE_8822B) << BIT_SHIFT_BT_PROFILE_8822B)
-#define BIT_GET_BT_PROFILE_8822B(x) \
- (((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B)
-
-#define BIT_SHIFT_BT_POWER_8822B 16
-#define BIT_MASK_BT_POWER_8822B 0xff
-#define BIT_BT_POWER_8822B(x) \
- (((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B)
-#define BIT_GET_BT_POWER_8822B(x) \
- (((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B)
-
-#define BIT_SHIFT_BT_PREDECT_STATUS_8822B 8
-#define BIT_MASK_BT_PREDECT_STATUS_8822B 0xff
-#define BIT_BT_PREDECT_STATUS_8822B(x) \
- (((x) & BIT_MASK_BT_PREDECT_STATUS_8822B) \
- << BIT_SHIFT_BT_PREDECT_STATUS_8822B)
-#define BIT_GET_BT_PREDECT_STATUS_8822B(x) \
- (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) & \
- BIT_MASK_BT_PREDECT_STATUS_8822B)
-
-#define BIT_SHIFT_BT_CMD_INFO_8822B 0
-#define BIT_MASK_BT_CMD_INFO_8822B 0xff
-#define BIT_BT_CMD_INFO_8822B(x) \
- (((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B)
-#define BIT_GET_BT_CMD_INFO_8822B(x) \
- (((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B)
-
-/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822B */
-#define BIT_EN_MAC_NULL_PKT_NOTIFY_8822B BIT(31)
-#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8822B BIT(30)
-#define BIT_EN_BT_STSTUS_RPT_8822B BIT(29)
-#define BIT_EN_BT_POWER_8822B BIT(28)
-#define BIT_EN_BT_CHANNEL_8822B BIT(27)
-#define BIT_EN_BT_SLOT_CHANGE_8822B BIT(26)
-#define BIT_EN_BT_PROFILE_OR_HID_8822B BIT(25)
-#define BIT_WLAN_RPT_NOTIFY_8822B BIT(24)
-
-#define BIT_SHIFT_WLAN_RPT_DATA_8822B 16
-#define BIT_MASK_WLAN_RPT_DATA_8822B 0xff
-#define BIT_WLAN_RPT_DATA_8822B(x) \
- (((x) & BIT_MASK_WLAN_RPT_DATA_8822B) << BIT_SHIFT_WLAN_RPT_DATA_8822B)
-#define BIT_GET_WLAN_RPT_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B)
-
-#define BIT_SHIFT_CMD_ID_8822B 8
-#define BIT_MASK_CMD_ID_8822B 0xff
-#define BIT_CMD_ID_8822B(x) \
- (((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B)
-#define BIT_GET_CMD_ID_8822B(x) \
- (((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B)
-
-#define BIT_SHIFT_BT_DATA_8822B 0
-#define BIT_MASK_BT_DATA_8822B 0xff
-#define BIT_BT_DATA_8822B(x) \
- (((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B)
-#define BIT_GET_BT_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B)
-
-/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B */
-
-#define BIT_SHIFT_WLAN_RPT_TO_8822B 0
-#define BIT_MASK_WLAN_RPT_TO_8822B 0xff
-#define BIT_WLAN_RPT_TO_8822B(x) \
- (((x) & BIT_MASK_WLAN_RPT_TO_8822B) << BIT_SHIFT_WLAN_RPT_TO_8822B)
-#define BIT_GET_WLAN_RPT_TO_8822B(x) \
- (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B)
-
-/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B */
-
-#define BIT_SHIFT_ISOLATION_CHK_8822B 1
-#define BIT_MASK_ISOLATION_CHK_8822B 0x7fffffffffffffffffffL
-#define BIT_ISOLATION_CHK_8822B(x) \
- (((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B)
-#define BIT_GET_ISOLATION_CHK_8822B(x) \
- (((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B)
-
-#define BIT_ISOLATION_EN_8822B BIT(0)
-
-/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8822B */
-#define BIT_BT_HID_ISR_8822B BIT(7)
-#define BIT_BT_QUERY_ISR_8822B BIT(6)
-#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8822B BIT(5)
-#define BIT_WLAN_RPT_ISR_8822B BIT(4)
-#define BIT_BT_POWER_ISR_8822B BIT(3)
-#define BIT_BT_CHANNEL_ISR_8822B BIT(2)
-#define BIT_BT_SLOT_CHANGE_ISR_8822B BIT(1)
-#define BIT_BT_PROFILE_ISR_8822B BIT(0)
-
-/* 2 REG_BT_TDMA_TIME_REGISTER_8822B */
-
-#define BIT_SHIFT_BT_TIME_8822B 6
-#define BIT_MASK_BT_TIME_8822B 0x3ffffff
-#define BIT_BT_TIME_8822B(x) \
- (((x) & BIT_MASK_BT_TIME_8822B) << BIT_SHIFT_BT_TIME_8822B)
-#define BIT_GET_BT_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B)
-
-#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B 0
-#define BIT_MASK_BT_RPT_SAMPLE_RATE_8822B 0x3f
-#define BIT_BT_RPT_SAMPLE_RATE_8822B(x) \
- (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) \
- << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B)
-#define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x) \
- (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) & \
- BIT_MASK_BT_RPT_SAMPLE_RATE_8822B)
-
-/* 2 REG_BT_ACT_REGISTER_8822B */
-
-#define BIT_SHIFT_BT_EISR_EN_8822B 16
-#define BIT_MASK_BT_EISR_EN_8822B 0xff
-#define BIT_BT_EISR_EN_8822B(x) \
- (((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B)
-#define BIT_GET_BT_EISR_EN_8822B(x) \
- (((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B)
-
-#define BIT_BT_ACT_FALLING_ISR_8822B BIT(10)
-#define BIT_BT_ACT_RISING_ISR_8822B BIT(9)
-#define BIT_TDMA_TO_ISR_8822B BIT(8)
-
-#define BIT_SHIFT_BT_CH_8822B 0
-#define BIT_MASK_BT_CH_8822B 0xff
-#define BIT_BT_CH_8822B(x) \
- (((x) & BIT_MASK_BT_CH_8822B) << BIT_SHIFT_BT_CH_8822B)
-#define BIT_GET_BT_CH_8822B(x) \
- (((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B)
-
-/* 2 REG_OBFF_CTRL_BASIC_8822B */
-#define BIT_OBFF_EN_V1_8822B BIT(31)
-
-#define BIT_SHIFT_OBFF_STATE_V1_8822B 28
-#define BIT_MASK_OBFF_STATE_V1_8822B 0x3
-#define BIT_OBFF_STATE_V1_8822B(x) \
- (((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B)
-#define BIT_GET_OBFF_STATE_V1_8822B(x) \
- (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B)
-
-#define BIT_OBFF_ACT_RXDMA_EN_8822B BIT(27)
-#define BIT_OBFF_BLOCK_INT_EN_8822B BIT(26)
-#define BIT_OBFF_AUTOACT_EN_8822B BIT(25)
-#define BIT_OBFF_AUTOIDLE_EN_8822B BIT(24)
-
-#define BIT_SHIFT_WAKE_MAX_PLS_8822B 20
-#define BIT_MASK_WAKE_MAX_PLS_8822B 0x7
-#define BIT_WAKE_MAX_PLS_8822B(x) \
- (((x) & BIT_MASK_WAKE_MAX_PLS_8822B) << BIT_SHIFT_WAKE_MAX_PLS_8822B)
-#define BIT_GET_WAKE_MAX_PLS_8822B(x) \
- (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B)
-
-#define BIT_SHIFT_WAKE_MIN_PLS_8822B 16
-#define BIT_MASK_WAKE_MIN_PLS_8822B 0x7
-#define BIT_WAKE_MIN_PLS_8822B(x) \
- (((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B)
-#define BIT_GET_WAKE_MIN_PLS_8822B(x) \
- (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B)
-
-#define BIT_SHIFT_WAKE_MAX_F2F_8822B 12
-#define BIT_MASK_WAKE_MAX_F2F_8822B 0x7
-#define BIT_WAKE_MAX_F2F_8822B(x) \
- (((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B)
-#define BIT_GET_WAKE_MAX_F2F_8822B(x) \
- (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B)
-
-#define BIT_SHIFT_WAKE_MIN_F2F_8822B 8
-#define BIT_MASK_WAKE_MIN_F2F_8822B 0x7
-#define BIT_WAKE_MIN_F2F_8822B(x) \
- (((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B)
-#define BIT_GET_WAKE_MIN_F2F_8822B(x) \
- (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B)
-
-#define BIT_APP_CPU_ACT_V1_8822B BIT(3)
-#define BIT_APP_OBFF_V1_8822B BIT(2)
-#define BIT_APP_IDLE_V1_8822B BIT(1)
-#define BIT_APP_INIT_V1_8822B BIT(0)
-
-/* 2 REG_OBFF_CTRL2_TIMER_8822B */
-
-#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B 24
-#define BIT_MASK_RX_HIGH_TIMER_IDX_8822B 0x7
-#define BIT_RX_HIGH_TIMER_IDX_8822B(x) \
- (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) \
- << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B)
-#define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) & \
- BIT_MASK_RX_HIGH_TIMER_IDX_8822B)
-
-#define BIT_SHIFT_RX_MED_TIMER_IDX_8822B 16
-#define BIT_MASK_RX_MED_TIMER_IDX_8822B 0x7
-#define BIT_RX_MED_TIMER_IDX_8822B(x) \
- (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B) \
- << BIT_SHIFT_RX_MED_TIMER_IDX_8822B)
-#define BIT_GET_RX_MED_TIMER_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) & \
- BIT_MASK_RX_MED_TIMER_IDX_8822B)
-
-#define BIT_SHIFT_RX_LOW_TIMER_IDX_8822B 8
-#define BIT_MASK_RX_LOW_TIMER_IDX_8822B 0x7
-#define BIT_RX_LOW_TIMER_IDX_8822B(x) \
- (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) \
- << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B)
-#define BIT_GET_RX_LOW_TIMER_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) & \
- BIT_MASK_RX_LOW_TIMER_IDX_8822B)
-
-#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B 0
-#define BIT_MASK_OBFF_INT_TIMER_IDX_8822B 0x7
-#define BIT_OBFF_INT_TIMER_IDX_8822B(x) \
- (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) \
- << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B)
-#define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) & \
- BIT_MASK_OBFF_INT_TIMER_IDX_8822B)
-
-/* 2 REG_LTR_CTRL_BASIC_8822B */
-#define BIT_LTR_EN_V1_8822B BIT(31)
-#define BIT_LTR_HW_EN_V1_8822B BIT(30)
-#define BIT_LRT_ACT_CTS_EN_8822B BIT(29)
-#define BIT_LTR_ACT_RXPKT_EN_8822B BIT(28)
-#define BIT_LTR_ACT_RXDMA_EN_8822B BIT(27)
-#define BIT_LTR_IDLE_NO_SNOOP_8822B BIT(26)
-#define BIT_SPDUP_MGTPKT_8822B BIT(25)
-#define BIT_RX_AGG_EN_8822B BIT(24)
-#define BIT_APP_LTR_ACT_8822B BIT(23)
-#define BIT_APP_LTR_IDLE_8822B BIT(22)
-
-#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B 20
-#define BIT_MASK_HIGH_RATE_TRIG_SEL_8822B 0x3
-#define BIT_HIGH_RATE_TRIG_SEL_8822B(x) \
- (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) \
- << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B)
-#define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) & \
- BIT_MASK_HIGH_RATE_TRIG_SEL_8822B)
-
-#define BIT_SHIFT_MED_RATE_TRIG_SEL_8822B 18
-#define BIT_MASK_MED_RATE_TRIG_SEL_8822B 0x3
-#define BIT_MED_RATE_TRIG_SEL_8822B(x) \
- (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) \
- << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B)
-#define BIT_GET_MED_RATE_TRIG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) & \
- BIT_MASK_MED_RATE_TRIG_SEL_8822B)
-
-#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B 16
-#define BIT_MASK_LOW_RATE_TRIG_SEL_8822B 0x3
-#define BIT_LOW_RATE_TRIG_SEL_8822B(x) \
- (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) \
- << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B)
-#define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) & \
- BIT_MASK_LOW_RATE_TRIG_SEL_8822B)
-
-#define BIT_SHIFT_HIGH_RATE_BD_IDX_8822B 8
-#define BIT_MASK_HIGH_RATE_BD_IDX_8822B 0x7f
-#define BIT_HIGH_RATE_BD_IDX_8822B(x) \
- (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) \
- << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B)
-#define BIT_GET_HIGH_RATE_BD_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) & \
- BIT_MASK_HIGH_RATE_BD_IDX_8822B)
-
-#define BIT_SHIFT_LOW_RATE_BD_IDX_8822B 0
-#define BIT_MASK_LOW_RATE_BD_IDX_8822B 0x7f
-#define BIT_LOW_RATE_BD_IDX_8822B(x) \
- (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B) \
- << BIT_SHIFT_LOW_RATE_BD_IDX_8822B)
-#define BIT_GET_LOW_RATE_BD_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) & \
- BIT_MASK_LOW_RATE_BD_IDX_8822B)
-
-/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822B */
-
-#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B 24
-#define BIT_MASK_RX_EMPTY_TIMER_IDX_8822B 0x7
-#define BIT_RX_EMPTY_TIMER_IDX_8822B(x) \
- (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) \
- << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B)
-#define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) & \
- BIT_MASK_RX_EMPTY_TIMER_IDX_8822B)
-
-#define BIT_SHIFT_RX_AFULL_TH_IDX_8822B 20
-#define BIT_MASK_RX_AFULL_TH_IDX_8822B 0x7
-#define BIT_RX_AFULL_TH_IDX_8822B(x) \
- (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B) \
- << BIT_SHIFT_RX_AFULL_TH_IDX_8822B)
-#define BIT_GET_RX_AFULL_TH_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) & \
- BIT_MASK_RX_AFULL_TH_IDX_8822B)
-
-#define BIT_SHIFT_RX_HIGH_TH_IDX_8822B 16
-#define BIT_MASK_RX_HIGH_TH_IDX_8822B 0x7
-#define BIT_RX_HIGH_TH_IDX_8822B(x) \
- (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B) \
- << BIT_SHIFT_RX_HIGH_TH_IDX_8822B)
-#define BIT_GET_RX_HIGH_TH_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) & \
- BIT_MASK_RX_HIGH_TH_IDX_8822B)
-
-#define BIT_SHIFT_RX_MED_TH_IDX_8822B 12
-#define BIT_MASK_RX_MED_TH_IDX_8822B 0x7
-#define BIT_RX_MED_TH_IDX_8822B(x) \
- (((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B)
-#define BIT_GET_RX_MED_TH_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B)
-
-#define BIT_SHIFT_RX_LOW_TH_IDX_8822B 8
-#define BIT_MASK_RX_LOW_TH_IDX_8822B 0x7
-#define BIT_RX_LOW_TH_IDX_8822B(x) \
- (((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B)
-#define BIT_GET_RX_LOW_TH_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B)
-
-#define BIT_SHIFT_LTR_SPACE_IDX_8822B 4
-#define BIT_MASK_LTR_SPACE_IDX_8822B 0x3
-#define BIT_LTR_SPACE_IDX_8822B(x) \
- (((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B)
-#define BIT_GET_LTR_SPACE_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B)
-
-#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B 0
-#define BIT_MASK_LTR_IDLE_TIMER_IDX_8822B 0x7
-#define BIT_LTR_IDLE_TIMER_IDX_8822B(x) \
- (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) \
- << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B)
-#define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x) \
- (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) & \
- BIT_MASK_LTR_IDLE_TIMER_IDX_8822B)
-
-/* 2 REG_LTR_IDLE_LATENCY_V1_8822B */
-
-#define BIT_SHIFT_LTR_IDLE_L_8822B 0
-#define BIT_MASK_LTR_IDLE_L_8822B 0xffffffffL
-#define BIT_LTR_IDLE_L_8822B(x) \
- (((x) & BIT_MASK_LTR_IDLE_L_8822B) << BIT_SHIFT_LTR_IDLE_L_8822B)
-#define BIT_GET_LTR_IDLE_L_8822B(x) \
- (((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B)
-
-/* 2 REG_LTR_ACTIVE_LATENCY_V1_8822B */
-
-#define BIT_SHIFT_LTR_ACT_L_8822B 0
-#define BIT_MASK_LTR_ACT_L_8822B 0xffffffffL
-#define BIT_LTR_ACT_L_8822B(x) \
- (((x) & BIT_MASK_LTR_ACT_L_8822B) << BIT_SHIFT_LTR_ACT_L_8822B)
-#define BIT_GET_LTR_ACT_L_8822B(x) \
- (((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B)
-
-/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B */
-#define BIT_APPEND_MACID_IN_RESP_EN_8822B BIT(50)
-#define BIT_ADDR2_MATCH_EN_8822B BIT(49)
-#define BIT_ANTTRN_EN_8822B BIT(48)
-
-#define BIT_SHIFT_TRAIN_STA_ADDR_8822B 0
-#define BIT_MASK_TRAIN_STA_ADDR_8822B 0xffffffffffffL
-#define BIT_TRAIN_STA_ADDR_8822B(x) \
- (((x) & BIT_MASK_TRAIN_STA_ADDR_8822B) \
- << BIT_SHIFT_TRAIN_STA_ADDR_8822B)
-#define BIT_GET_TRAIN_STA_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) & \
- BIT_MASK_TRAIN_STA_ADDR_8822B)
-
-/* 2 REG_RSVD_0X7B4_8822B */
-
-/* 2 REG_WMAC_PKTCNT_RWD_8822B */
-
-#define BIT_SHIFT_PKTCNT_BSSIDMAP_8822B 4
-#define BIT_MASK_PKTCNT_BSSIDMAP_8822B 0xf
-#define BIT_PKTCNT_BSSIDMAP_8822B(x) \
- (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) \
- << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B)
-#define BIT_GET_PKTCNT_BSSIDMAP_8822B(x) \
- (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) & \
- BIT_MASK_PKTCNT_BSSIDMAP_8822B)
-
-#define BIT_PKTCNT_CNTRST_8822B BIT(1)
-#define BIT_PKTCNT_CNTEN_8822B BIT(0)
-
-/* 2 REG_WMAC_PKTCNT_CTRL_8822B */
-#define BIT_WMAC_PKTCNT_TRST_8822B BIT(9)
-#define BIT_WMAC_PKTCNT_FEN_8822B BIT(8)
-
-#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B 0
-#define BIT_MASK_WMAC_PKTCNT_CFGAD_8822B 0xff
-#define BIT_WMAC_PKTCNT_CFGAD_8822B(x) \
- (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) \
- << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B)
-#define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x) \
- (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) & \
- BIT_MASK_WMAC_PKTCNT_CFGAD_8822B)
-
-/* 2 REG_IQ_DUMP_8822B */
-
-#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B 0xffffffffL
-#define BIT_R_WMAC_MATCH_REF_MAC_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) \
- << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B)
-#define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) & \
- BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B)
-
-#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_MASK_LA_MAC_8822B 0xffffffffL
-#define BIT_R_WMAC_MASK_LA_MAC_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) \
- << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B)
-#define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) & \
- BIT_MASK_R_WMAC_MASK_LA_MAC_8822B)
-
-#define BIT_SHIFT_DUMP_OK_ADDR_8822B 15
-#define BIT_MASK_DUMP_OK_ADDR_8822B 0x1ffff
-#define BIT_DUMP_OK_ADDR_8822B(x) \
- (((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B)
-#define BIT_GET_DUMP_OK_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B)
-
-#define BIT_SHIFT_R_TRIG_TIME_SEL_8822B 8
-#define BIT_MASK_R_TRIG_TIME_SEL_8822B 0x7f
-#define BIT_R_TRIG_TIME_SEL_8822B(x) \
- (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B) \
- << BIT_SHIFT_R_TRIG_TIME_SEL_8822B)
-#define BIT_GET_R_TRIG_TIME_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) & \
- BIT_MASK_R_TRIG_TIME_SEL_8822B)
-
-#define BIT_SHIFT_R_MAC_TRIG_SEL_8822B 6
-#define BIT_MASK_R_MAC_TRIG_SEL_8822B 0x3
-#define BIT_R_MAC_TRIG_SEL_8822B(x) \
- (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B) \
- << BIT_SHIFT_R_MAC_TRIG_SEL_8822B)
-#define BIT_GET_R_MAC_TRIG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) & \
- BIT_MASK_R_MAC_TRIG_SEL_8822B)
-
-#define BIT_MAC_TRIG_REG_8822B BIT(5)
-
-#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B 3
-#define BIT_MASK_R_LEVEL_PULSE_SEL_8822B 0x3
-#define BIT_R_LEVEL_PULSE_SEL_8822B(x) \
- (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) \
- << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B)
-#define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) & \
- BIT_MASK_R_LEVEL_PULSE_SEL_8822B)
-
-#define BIT_EN_LA_MAC_8822B BIT(2)
-#define BIT_R_EN_IQDUMP_8822B BIT(1)
-#define BIT_R_IQDATA_DUMP_8822B BIT(0)
-
-/* 2 REG_WMAC_FTM_CTL_8822B */
-#define BIT_RXFTM_TXACK_SC_8822B BIT(6)
-#define BIT_RXFTM_TXACK_BW_8822B BIT(5)
-#define BIT_RXFTM_EN_8822B BIT(3)
-#define BIT_RXFTMREQ_BYDRV_8822B BIT(2)
-#define BIT_RXFTMREQ_EN_8822B BIT(1)
-#define BIT_FTM_EN_8822B BIT(0)
-
-/* 2 REG_WMAC_IQ_MDPK_FUNC_8822B */
-
-/* 2 REG_WMAC_OPTION_FUNCTION_8822B */
-
-#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_RX_FIL_LEN_8822B 0xffff
-#define BIT_R_WMAC_RX_FIL_LEN_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) \
- << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B)
-#define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) & \
- BIT_MASK_R_WMAC_RX_FIL_LEN_8822B)
-
-#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B 0xff
-#define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) \
- << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B)
-#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) & \
- BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B)
-
-#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8822B BIT(55)
-#define BIT_R_WMAC_RXRST_DLY_8822B BIT(54)
-#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8822B BIT(53)
-#define BIT_R_WMAC_SRCH_TXRPT_UA1_8822B BIT(52)
-#define BIT_R_WMAC_SRCH_TXRPT_TYPE_8822B BIT(51)
-#define BIT_R_WMAC_NDP_RST_8822B BIT(50)
-#define BIT_R_WMAC_POWINT_EN_8822B BIT(49)
-#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_8822B BIT(48)
-#define BIT_R_WMAC_SRCH_TXRPT_MID_8822B BIT(47)
-#define BIT_R_WMAC_PFIN_TOEN_8822B BIT(46)
-#define BIT_R_WMAC_FIL_SECERR_8822B BIT(45)
-#define BIT_R_WMAC_FIL_CTLPKTLEN_8822B BIT(44)
-#define BIT_R_WMAC_FIL_FCTYPE_8822B BIT(43)
-#define BIT_R_WMAC_FIL_FCPROVER_8822B BIT(42)
-#define BIT_R_WMAC_PHYSTS_SNIF_8822B BIT(41)
-#define BIT_R_WMAC_PHYSTS_PLCP_8822B BIT(40)
-#define BIT_R_MAC_TCR_VBONF_RD_8822B BIT(39)
-#define BIT_R_WMAC_TCR_MPAR_NDP_8822B BIT(38)
-#define BIT_R_WMAC_NDP_FILTER_8822B BIT(37)
-#define BIT_R_WMAC_RXLEN_SEL_8822B BIT(36)
-#define BIT_R_WMAC_RXLEN_SEL1_8822B BIT(35)
-#define BIT_R_OFDM_FILTER_8822B BIT(34)
-#define BIT_R_WMAC_CHK_OFDM_LEN_8822B BIT(33)
-#define BIT_R_WMAC_CHK_CCK_LEN_8822B BIT(32)
-
-#define BIT_SHIFT_R_OFDM_LEN_8822B 26
-#define BIT_MASK_R_OFDM_LEN_8822B 0x3f
-#define BIT_R_OFDM_LEN_8822B(x) \
- (((x) & BIT_MASK_R_OFDM_LEN_8822B) << BIT_SHIFT_R_OFDM_LEN_8822B)
-#define BIT_GET_R_OFDM_LEN_8822B(x) \
- (((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B)
-
-#define BIT_SHIFT_R_CCK_LEN_8822B 0
-#define BIT_MASK_R_CCK_LEN_8822B 0xffff
-#define BIT_R_CCK_LEN_8822B(x) \
- (((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B)
-#define BIT_GET_R_CCK_LEN_8822B(x) \
- (((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B)
-
-/* 2 REG_RX_FILTER_FUNCTION_8822B */
-#define BIT_R_WMAC_MHRDDY_LATCH_8822B BIT(14)
-#define BIT_R_WMAC_MHRDDY_CLR_8822B BIT(13)
-#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8822B BIT(12)
-#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8822B BIT(11)
-#define BIT_R_CHK_DELIMIT_LEN_8822B BIT(10)
-#define BIT_R_REAPTER_ADDR_MATCH_8822B BIT(9)
-#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8822B BIT(8)
-#define BIT_R_LATCH_MACHRDY_8822B BIT(7)
-#define BIT_R_WMAC_RXFIL_REND_8822B BIT(6)
-#define BIT_R_WMAC_MPDURDY_CLR_8822B BIT(5)
-#define BIT_R_WMAC_CLRRXSEC_8822B BIT(4)
-#define BIT_R_WMAC_RXFIL_RDEL_8822B BIT(3)
-#define BIT_R_WMAC_RXFIL_FCSE_8822B BIT(2)
-#define BIT_R_WMAC_RXFIL_MESH_DEL_8822B BIT(1)
-#define BIT_R_WMAC_RXFIL_MASKM_8822B BIT(0)
-
-/* 2 REG_NDP_SIG_8822B */
-
-#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B 0
-#define BIT_MASK_R_WMAC_TXNDP_SIGB_8822B 0x1fffff
-#define BIT_R_WMAC_TXNDP_SIGB_8822B(x) \
- (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) \
- << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B)
-#define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x) \
- (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) & \
- BIT_MASK_R_WMAC_TXNDP_SIGB_8822B)
-
-/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822B */
-
-#define BIT_SHIFT_R_MAC_DEBUG_8822B (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_MAC_DEBUG_8822B 0xffffffffL
-#define BIT_R_MAC_DEBUG_8822B(x) \
- (((x) & BIT_MASK_R_MAC_DEBUG_8822B) << BIT_SHIFT_R_MAC_DEBUG_8822B)
-#define BIT_GET_R_MAC_DEBUG_8822B(x) \
- (((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B)
-
-#define BIT_SHIFT_R_MAC_DBG_SHIFT_8822B 8
-#define BIT_MASK_R_MAC_DBG_SHIFT_8822B 0x7
-#define BIT_R_MAC_DBG_SHIFT_8822B(x) \
- (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) \
- << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B)
-#define BIT_GET_R_MAC_DBG_SHIFT_8822B(x) \
- (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) & \
- BIT_MASK_R_MAC_DBG_SHIFT_8822B)
-
-#define BIT_SHIFT_R_MAC_DBG_SEL_8822B 0
-#define BIT_MASK_R_MAC_DBG_SEL_8822B 0x3
-#define BIT_R_MAC_DBG_SEL_8822B(x) \
- (((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B)
-#define BIT_GET_R_MAC_DBG_SEL_8822B(x) \
- (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B)
-
-/* 2 REG_RTS_ADDRESS_0_8822B */
-
-/* 2 REG_RTS_ADDRESS_1_8822B */
-
-/* 2 REG__RPFM_MAP1_8822B
- * (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1
- */
-#define BIT_DATA_RPFM15EN_8822B BIT(15)
-#define BIT_DATA_RPFM14EN_8822B BIT(14)
-#define BIT_DATA_RPFM13EN_8822B BIT(13)
-#define BIT_DATA_RPFM12EN_8822B BIT(12)
-#define BIT_DATA_RPFM11EN_8822B BIT(11)
-#define BIT_DATA_RPFM10EN_8822B BIT(10)
-#define BIT_DATA_RPFM9EN_8822B BIT(9)
-#define BIT_DATA_RPFM8EN_8822B BIT(8)
-#define BIT_DATA_RPFM7EN_8822B BIT(7)
-#define BIT_DATA_RPFM6EN_8822B BIT(6)
-#define BIT_DATA_RPFM5EN_8822B BIT(5)
-#define BIT_DATA_RPFM4EN_8822B BIT(4)
-#define BIT_DATA_RPFM3EN_8822B BIT(3)
-#define BIT_DATA_RPFM2EN_8822B BIT(2)
-#define BIT_DATA_RPFM1EN_8822B BIT(1)
-#define BIT_DATA_RPFM0EN_8822B BIT(0)
-
-/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B */
-#define BIT_LTECOEX_ACCESS_START_V1_8822B BIT(31)
-#define BIT_LTECOEX_WRITE_MODE_V1_8822B BIT(30)
-#define BIT_LTECOEX_READY_BIT_V1_8822B BIT(29)
-
-#define BIT_SHIFT_WRITE_BYTE_EN_V1_8822B 16
-#define BIT_MASK_WRITE_BYTE_EN_V1_8822B 0xf
-#define BIT_WRITE_BYTE_EN_V1_8822B(x) \
- (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) \
- << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B)
-#define BIT_GET_WRITE_BYTE_EN_V1_8822B(x) \
- (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) & \
- BIT_MASK_WRITE_BYTE_EN_V1_8822B)
-
-#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B 0
-#define BIT_MASK_LTECOEX_REG_ADDR_V1_8822B 0xffff
-#define BIT_LTECOEX_REG_ADDR_V1_8822B(x) \
- (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) \
- << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B)
-#define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) & \
- BIT_MASK_LTECOEX_REG_ADDR_V1_8822B)
-
-/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B */
-
-#define BIT_SHIFT_LTECOEX_W_DATA_V1_8822B 0
-#define BIT_MASK_LTECOEX_W_DATA_V1_8822B 0xffffffffL
-#define BIT_LTECOEX_W_DATA_V1_8822B(x) \
- (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) \
- << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B)
-#define BIT_GET_LTECOEX_W_DATA_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) & \
- BIT_MASK_LTECOEX_W_DATA_V1_8822B)
-
-/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B */
-
-#define BIT_SHIFT_LTECOEX_R_DATA_V1_8822B 0
-#define BIT_MASK_LTECOEX_R_DATA_V1_8822B 0xffffffffL
-#define BIT_LTECOEX_R_DATA_V1_8822B(x) \
- (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) \
- << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B)
-#define BIT_GET_LTECOEX_R_DATA_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) & \
- BIT_MASK_LTECOEX_R_DATA_V1_8822B)
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_SDIO_TX_CTRL_8822B */
-
-#define BIT_SHIFT_SDIO_INT_TIMEOUT_8822B 16
-#define BIT_MASK_SDIO_INT_TIMEOUT_8822B 0xffff
-#define BIT_SDIO_INT_TIMEOUT_8822B(x) \
- (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) \
- << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B)
-#define BIT_GET_SDIO_INT_TIMEOUT_8822B(x) \
- (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) & \
- BIT_MASK_SDIO_INT_TIMEOUT_8822B)
-
-#define BIT_IO_ERR_STATUS_8822B BIT(15)
-#define BIT_REPLY_ERRCRC_IN_DATA_8822B BIT(9)
-#define BIT_EN_CMD53_OVERLAP_8822B BIT(8)
-#define BIT_REPLY_ERR_IN_R5_8822B BIT(7)
-#define BIT_R18A_EN_8822B BIT(6)
-#define BIT_INIT_CMD_EN_8822B BIT(5)
-#define BIT_EN_RXDMA_MASK_INT_8822B BIT(2)
-#define BIT_EN_MASK_TIMER_8822B BIT(1)
-#define BIT_CMD_ERR_STOP_INT_EN_8822B BIT(0)
-
-/* 2 REG_SDIO_HIMR_8822B */
-#define BIT_SDIO_CRCERR_MSK_8822B BIT(31)
-#define BIT_SDIO_HSISR3_IND_MSK_8822B BIT(30)
-#define BIT_SDIO_HSISR2_IND_MSK_8822B BIT(29)
-#define BIT_SDIO_HEISR_IND_MSK_8822B BIT(28)
-#define BIT_SDIO_CTWEND_MSK_8822B BIT(27)
-#define BIT_SDIO_ATIMEND_E_MSK_8822B BIT(26)
-#define BIT_SDIIO_ATIMEND_MSK_8822B BIT(25)
-#define BIT_SDIO_OCPINT_MSK_8822B BIT(24)
-#define BIT_SDIO_PSTIMEOUT_MSK_8822B BIT(23)
-#define BIT_SDIO_GTINT4_MSK_8822B BIT(22)
-#define BIT_SDIO_GTINT3_MSK_8822B BIT(21)
-#define BIT_SDIO_HSISR_IND_MSK_8822B BIT(20)
-#define BIT_SDIO_CPWM2_MSK_8822B BIT(19)
-#define BIT_SDIO_CPWM1_MSK_8822B BIT(18)
-#define BIT_SDIO_C2HCMD_INT_MSK_8822B BIT(17)
-#define BIT_SDIO_BCNERLY_INT_MSK_8822B BIT(16)
-#define BIT_SDIO_TXBCNERR_MSK_8822B BIT(7)
-#define BIT_SDIO_TXBCNOK_MSK_8822B BIT(6)
-#define BIT_SDIO_RXFOVW_MSK_8822B BIT(5)
-#define BIT_SDIO_TXFOVW_MSK_8822B BIT(4)
-#define BIT_SDIO_RXERR_MSK_8822B BIT(3)
-#define BIT_SDIO_TXERR_MSK_8822B BIT(2)
-#define BIT_SDIO_AVAL_MSK_8822B BIT(1)
-#define BIT_RX_REQUEST_MSK_8822B BIT(0)
-
-/* 2 REG_SDIO_HISR_8822B */
-#define BIT_SDIO_CRCERR_8822B BIT(31)
-#define BIT_SDIO_HSISR3_IND_8822B BIT(30)
-#define BIT_SDIO_HSISR2_IND_8822B BIT(29)
-#define BIT_SDIO_HEISR_IND_8822B BIT(28)
-#define BIT_SDIO_CTWEND_8822B BIT(27)
-#define BIT_SDIO_ATIMEND_E_8822B BIT(26)
-#define BIT_SDIO_ATIMEND_8822B BIT(25)
-#define BIT_SDIO_OCPINT_8822B BIT(24)
-#define BIT_SDIO_PSTIMEOUT_8822B BIT(23)
-#define BIT_SDIO_GTINT4_8822B BIT(22)
-#define BIT_SDIO_GTINT3_8822B BIT(21)
-#define BIT_SDIO_HSISR_IND_8822B BIT(20)
-#define BIT_SDIO_CPWM2_8822B BIT(19)
-#define BIT_SDIO_CPWM1_8822B BIT(18)
-#define BIT_SDIO_C2HCMD_INT_8822B BIT(17)
-#define BIT_SDIO_BCNERLY_INT_8822B BIT(16)
-#define BIT_SDIO_TXBCNERR_8822B BIT(7)
-#define BIT_SDIO_TXBCNOK_8822B BIT(6)
-#define BIT_SDIO_RXFOVW_8822B BIT(5)
-#define BIT_SDIO_TXFOVW_8822B BIT(4)
-#define BIT_SDIO_RXERR_8822B BIT(3)
-#define BIT_SDIO_TXERR_8822B BIT(2)
-#define BIT_SDIO_AVAL_8822B BIT(1)
-#define BIT_RX_REQUEST_8822B BIT(0)
-
-/* 2 REG_SDIO_RX_REQ_LEN_8822B */
-
-#define BIT_SHIFT_RX_REQ_LEN_V1_8822B 0
-#define BIT_MASK_RX_REQ_LEN_V1_8822B 0x3ffff
-#define BIT_RX_REQ_LEN_V1_8822B(x) \
- (((x) & BIT_MASK_RX_REQ_LEN_V1_8822B) << BIT_SHIFT_RX_REQ_LEN_V1_8822B)
-#define BIT_GET_RX_REQ_LEN_V1_8822B(x) \
- (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B)
-
-/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822B */
-
-#define BIT_SHIFT_FREE_TXPG_SEQ_8822B 0
-#define BIT_MASK_FREE_TXPG_SEQ_8822B 0xff
-#define BIT_FREE_TXPG_SEQ_8822B(x) \
- (((x) & BIT_MASK_FREE_TXPG_SEQ_8822B) << BIT_SHIFT_FREE_TXPG_SEQ_8822B)
-#define BIT_GET_FREE_TXPG_SEQ_8822B(x) \
- (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B)
-
-/* 2 REG_SDIO_FREE_TXPG_8822B */
-
-#define BIT_SHIFT_MID_FREEPG_V1_8822B 16
-#define BIT_MASK_MID_FREEPG_V1_8822B 0xfff
-#define BIT_MID_FREEPG_V1_8822B(x) \
- (((x) & BIT_MASK_MID_FREEPG_V1_8822B) << BIT_SHIFT_MID_FREEPG_V1_8822B)
-#define BIT_GET_MID_FREEPG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B)
-
-#define BIT_SHIFT_HIQ_FREEPG_V1_8822B 0
-#define BIT_MASK_HIQ_FREEPG_V1_8822B 0xfff
-#define BIT_HIQ_FREEPG_V1_8822B(x) \
- (((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B)
-#define BIT_GET_HIQ_FREEPG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B)
-
-/* 2 REG_SDIO_FREE_TXPG2_8822B */
-
-#define BIT_SHIFT_PUB_FREEPG_V1_8822B 16
-#define BIT_MASK_PUB_FREEPG_V1_8822B 0xfff
-#define BIT_PUB_FREEPG_V1_8822B(x) \
- (((x) & BIT_MASK_PUB_FREEPG_V1_8822B) << BIT_SHIFT_PUB_FREEPG_V1_8822B)
-#define BIT_GET_PUB_FREEPG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B)
-
-#define BIT_SHIFT_LOW_FREEPG_V1_8822B 0
-#define BIT_MASK_LOW_FREEPG_V1_8822B 0xfff
-#define BIT_LOW_FREEPG_V1_8822B(x) \
- (((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B)
-#define BIT_GET_LOW_FREEPG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B)
-
-/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822B */
-
-#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B 24
-#define BIT_MASK_NOAC_OQT_FREEPG_V1_8822B 0xff
-#define BIT_NOAC_OQT_FREEPG_V1_8822B(x) \
- (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) \
- << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B)
-#define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) & \
- BIT_MASK_NOAC_OQT_FREEPG_V1_8822B)
-
-#define BIT_SHIFT_AC_OQT_FREEPG_V1_8822B 16
-#define BIT_MASK_AC_OQT_FREEPG_V1_8822B 0xff
-#define BIT_AC_OQT_FREEPG_V1_8822B(x) \
- (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) \
- << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B)
-#define BIT_GET_AC_OQT_FREEPG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) & \
- BIT_MASK_AC_OQT_FREEPG_V1_8822B)
-
-#define BIT_SHIFT_EXQ_FREEPG_V1_8822B 0
-#define BIT_MASK_EXQ_FREEPG_V1_8822B 0xfff
-#define BIT_EXQ_FREEPG_V1_8822B(x) \
- (((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B)
-#define BIT_GET_EXQ_FREEPG_V1_8822B(x) \
- (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B)
-
-/* 2 REG_SDIO_HTSFR_INFO_8822B */
-
-#define BIT_SHIFT_HTSFR1_8822B 16
-#define BIT_MASK_HTSFR1_8822B 0xffff
-#define BIT_HTSFR1_8822B(x) \
- (((x) & BIT_MASK_HTSFR1_8822B) << BIT_SHIFT_HTSFR1_8822B)
-#define BIT_GET_HTSFR1_8822B(x) \
- (((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B)
-
-#define BIT_SHIFT_HTSFR0_8822B 0
-#define BIT_MASK_HTSFR0_8822B 0xffff
-#define BIT_HTSFR0_8822B(x) \
- (((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B)
-#define BIT_GET_HTSFR0_8822B(x) \
- (((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B)
-
-/* 2 REG_SDIO_HCPWM1_V2_8822B */
-#define BIT_TOGGLING_8822B BIT(7)
-#define BIT_ACK_8822B BIT(6)
-#define BIT_SYS_CLK_8822B BIT(0)
-
-/* 2 REG_SDIO_HCPWM2_V2_8822B */
-
-/* 2 REG_SDIO_INDIRECT_REG_CFG_8822B */
-#define BIT_INDIRECT_REG_RDY_8822B BIT(20)
-#define BIT_INDIRECT_REG_R_8822B BIT(19)
-#define BIT_INDIRECT_REG_W_8822B BIT(18)
-
-#define BIT_SHIFT_INDIRECT_REG_SIZE_8822B 16
-#define BIT_MASK_INDIRECT_REG_SIZE_8822B 0x3
-#define BIT_INDIRECT_REG_SIZE_8822B(x) \
- (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822B) \
- << BIT_SHIFT_INDIRECT_REG_SIZE_8822B)
-#define BIT_GET_INDIRECT_REG_SIZE_8822B(x) \
- (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) & \
- BIT_MASK_INDIRECT_REG_SIZE_8822B)
-
-#define BIT_SHIFT_INDIRECT_REG_ADDR_8822B 0
-#define BIT_MASK_INDIRECT_REG_ADDR_8822B 0xffff
-#define BIT_INDIRECT_REG_ADDR_8822B(x) \
- (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B) \
- << BIT_SHIFT_INDIRECT_REG_ADDR_8822B)
-#define BIT_GET_INDIRECT_REG_ADDR_8822B(x) \
- (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) & \
- BIT_MASK_INDIRECT_REG_ADDR_8822B)
-
-/* 2 REG_SDIO_INDIRECT_REG_DATA_8822B */
-
-#define BIT_SHIFT_INDIRECT_REG_DATA_8822B 0
-#define BIT_MASK_INDIRECT_REG_DATA_8822B 0xffffffffL
-#define BIT_INDIRECT_REG_DATA_8822B(x) \
- (((x) & BIT_MASK_INDIRECT_REG_DATA_8822B) \
- << BIT_SHIFT_INDIRECT_REG_DATA_8822B)
-#define BIT_GET_INDIRECT_REG_DATA_8822B(x) \
- (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) & \
- BIT_MASK_INDIRECT_REG_DATA_8822B)
-
-/* 2 REG_SDIO_H2C_8822B */
-
-#define BIT_SHIFT_SDIO_H2C_MSG_8822B 0
-#define BIT_MASK_SDIO_H2C_MSG_8822B 0xffffffffL
-#define BIT_SDIO_H2C_MSG_8822B(x) \
- (((x) & BIT_MASK_SDIO_H2C_MSG_8822B) << BIT_SHIFT_SDIO_H2C_MSG_8822B)
-#define BIT_GET_SDIO_H2C_MSG_8822B(x) \
- (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B)
-
-/* 2 REG_SDIO_C2H_8822B */
-
-#define BIT_SHIFT_SDIO_C2H_MSG_8822B 0
-#define BIT_MASK_SDIO_C2H_MSG_8822B 0xffffffffL
-#define BIT_SDIO_C2H_MSG_8822B(x) \
- (((x) & BIT_MASK_SDIO_C2H_MSG_8822B) << BIT_SHIFT_SDIO_C2H_MSG_8822B)
-#define BIT_GET_SDIO_C2H_MSG_8822B(x) \
- (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B)
-
-/* 2 REG_SDIO_HRPWM1_8822B */
-#define BIT_TOGGLING_8822B BIT(7)
-#define BIT_ACK_8822B BIT(6)
-#define BIT_32K_PERMISSION_8822B BIT(0)
-
-/* 2 REG_SDIO_HRPWM2_8822B */
-
-/* 2 REG_SDIO_HPS_CLKR_8822B */
-
-/* 2 REG_SDIO_BUS_CTRL_8822B */
-#define BIT_PAD_CLK_XHGE_EN_8822B BIT(3)
-#define BIT_INTER_CLK_EN_8822B BIT(2)
-#define BIT_EN_RPT_TXCRC_8822B BIT(1)
-#define BIT_DIS_RXDMA_STS_8822B BIT(0)
-
-/* 2 REG_SDIO_HSUS_CTRL_8822B */
-#define BIT_INTR_CTRL_8822B BIT(4)
-#define BIT_SDIO_VOLTAGE_8822B BIT(3)
-#define BIT_BYPASS_INIT_8822B BIT(2)
-#define BIT_HCI_RESUME_RDY_8822B BIT(1)
-#define BIT_HCI_SUS_REQ_8822B BIT(0)
-
-/* 2 REG_SDIO_RESPONSE_TIMER_8822B */
-
-#define BIT_SHIFT_CMDIN_2RESP_TIMER_8822B 0
-#define BIT_MASK_CMDIN_2RESP_TIMER_8822B 0xffff
-#define BIT_CMDIN_2RESP_TIMER_8822B(x) \
- (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) \
- << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B)
-#define BIT_GET_CMDIN_2RESP_TIMER_8822B(x) \
- (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) & \
- BIT_MASK_CMDIN_2RESP_TIMER_8822B)
-
-/* 2 REG_SDIO_CMD_CRC_8822B */
-
-#define BIT_SHIFT_SDIO_CMD_CRC_V1_8822B 0
-#define BIT_MASK_SDIO_CMD_CRC_V1_8822B 0xff
-#define BIT_SDIO_CMD_CRC_V1_8822B(x) \
- (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) \
- << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B)
-#define BIT_GET_SDIO_CMD_CRC_V1_8822B(x) \
- (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) & \
- BIT_MASK_SDIO_CMD_CRC_V1_8822B)
-
-/* 2 REG_SDIO_HSISR_8822B */
-#define BIT_DRV_WLAN_INT_CLR_8822B BIT(1)
-#define BIT_DRV_WLAN_INT_8822B BIT(0)
-
-/* 2 REG_SDIO_HSIMR_8822B */
-#define BIT_HISR_MASK_8822B BIT(0)
-
-/* 2 REG_SDIO_ERR_RPT_8822B */
-#define BIT_HR_FF_OVF_8822B BIT(6)
-#define BIT_HR_FF_UDN_8822B BIT(5)
-#define BIT_TXDMA_BUSY_ERR_8822B BIT(4)
-#define BIT_TXDMA_VLD_ERR_8822B BIT(3)
-#define BIT_QSEL_UNKNOWN_ERR_8822B BIT(2)
-#define BIT_QSEL_MIS_ERR_8822B BIT(1)
-#define BIT_SDIO_OVERRD_ERR_8822B BIT(0)
-
-/* 2 REG_SDIO_CMD_ERRCNT_8822B */
-
-#define BIT_SHIFT_CMD_CRC_ERR_CNT_8822B 0
-#define BIT_MASK_CMD_CRC_ERR_CNT_8822B 0xff
-#define BIT_CMD_CRC_ERR_CNT_8822B(x) \
- (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) \
- << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B)
-#define BIT_GET_CMD_CRC_ERR_CNT_8822B(x) \
- (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) & \
- BIT_MASK_CMD_CRC_ERR_CNT_8822B)
-
-/* 2 REG_SDIO_DATA_ERRCNT_8822B */
-
-#define BIT_SHIFT_DATA_CRC_ERR_CNT_8822B 0
-#define BIT_MASK_DATA_CRC_ERR_CNT_8822B 0xff
-#define BIT_DATA_CRC_ERR_CNT_8822B(x) \
- (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) \
- << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B)
-#define BIT_GET_DATA_CRC_ERR_CNT_8822B(x) \
- (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) & \
- BIT_MASK_DATA_CRC_ERR_CNT_8822B)
-
-/* 2 REG_SDIO_CMD_ERR_CONTENT_8822B */
-
-#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B 0
-#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B 0xffffffffffL
-#define BIT_SDIO_CMD_ERR_CONTENT_8822B(x) \
- (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) \
- << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B)
-#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x) \
- (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) & \
- BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B)
-
-/* 2 REG_SDIO_CRC_ERR_IDX_8822B */
-#define BIT_D3_CRC_ERR_8822B BIT(4)
-#define BIT_D2_CRC_ERR_8822B BIT(3)
-#define BIT_D1_CRC_ERR_8822B BIT(2)
-#define BIT_D0_CRC_ERR_8822B BIT(1)
-#define BIT_CMD_CRC_ERR_8822B BIT(0)
-
-/* 2 REG_SDIO_DATA_CRC_8822B */
-
-#define BIT_SHIFT_SDIO_DATA_CRC_8822B 0
-#define BIT_MASK_SDIO_DATA_CRC_8822B 0xff
-#define BIT_SDIO_DATA_CRC_8822B(x) \
- (((x) & BIT_MASK_SDIO_DATA_CRC_8822B) << BIT_SHIFT_SDIO_DATA_CRC_8822B)
-#define BIT_GET_SDIO_DATA_CRC_8822B(x) \
- (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B)
-
-/* 2 REG_SDIO_DATA_REPLY_TIME_8822B */
-
-#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B 0
-#define BIT_MASK_SDIO_DATA_REPLY_TIME_8822B 0x7
-#define BIT_SDIO_DATA_REPLY_TIME_8822B(x) \
- (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) \
- << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B)
-#define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x) \
- (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) & \
- BIT_MASK_SDIO_DATA_REPLY_TIME_8822B)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_FW_INFO_H_
-#define _HALMAC_FW_INFO_H_
-
-#define H2C_FORMAT_VERSION 6
-
-#define H2C_ACK_HDR_CONTENT_LENGTH 8
-#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16
-#define SCAN_STATUS_RPT_CONTENT_LENGTH 4
-#define C2H_DBG_HEADER_LENGTH 4
-#define C2H_DBG_CONTENT_MAX_LENGTH 228
-
-#define C2H_DBG_CONTENT_SEQ_OFFSET 1
-
-/* Rename from FW SysHalCom_Debug_RAM.h */
-#define FW_REG_H2CPKT_DONE_SEQ 0x1C8
-#define fw_reg_wow_reason 0x1C7
-
-enum halmac_data_type {
- HALMAC_DATA_TYPE_MAC_REG = 0x00,
- HALMAC_DATA_TYPE_BB_REG = 0x01,
- HALMAC_DATA_TYPE_RADIO_A = 0x02,
- HALMAC_DATA_TYPE_RADIO_B = 0x03,
- HALMAC_DATA_TYPE_RADIO_C = 0x04,
- HALMAC_DATA_TYPE_RADIO_D = 0x05,
-
- HALMAC_DATA_TYPE_DRV_DEFINE_0 = 0x80,
- HALMAC_DATA_TYPE_DRV_DEFINE_1 = 0x81,
- HALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82,
- HALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83,
- HALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF,
-};
-
-enum halmac_packet_id {
- HALMAC_PACKET_PROBE_REQ = 0x00,
- HALMAC_PACKET_SYNC_BCN = 0x01,
- HALMAC_PACKET_DISCOVERY_BCN = 0x02,
-
- HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF,
-};
-
-/* Channel Switch Action ID */
-enum halmac_cs_action_id {
- HALMAC_CS_ACTION_NONE = 0x00,
- HALMAC_CS_ACTIVE_SCAN = 0x01,
- HALMAC_CS_NAN_NONMASTER_DW = 0x02,
- HALMAC_CS_NAN_NONMASTER_NONDW = 0x03,
- HALMAC_CS_NAN_MASTER_NONDW = 0x04,
- HALMAC_CS_NAN_MASTER_DW = 0x05,
-
- HALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF,
-};
-
-/* Channel Switch Extra Action ID */
-enum halmac_cs_extra_action_id {
- HALMAC_CS_EXTRA_ACTION_NONE = 0x00,
- HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01,
- HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02,
-
- HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF,
-};
-
-enum halmac_h2c_return_code {
- HALMAC_H2C_RETURN_SUCCESS = 0x00,
- HALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01,
- HALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02,
-
- HALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03,
-
- HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04, /* DMEM buffer full */
- HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05, /* Invalid pack id */
-
- HALMAC_H2C_RETURN_RUN_ERR_EMPTY =
- 0x06, /* No data in dedicated buffer */
- HALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07,
- HALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08,
- HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09, /* Invalid pack id */
-
- HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A, /* DMEM buffer full */
- HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B, /* Invalid packet id */
-
- HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C, /* DMEM buffer full */
- HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D, /* PHYDM API return fail */
-
- HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E, /* Invalid original H2C cmd id */
-
- HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF,
-};
-
-enum halmac_scan_report_code {
- HALMAC_SCAN_REPORT_DONE = 0x00,
- HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01, /* PHYDM API return fail */
- HALMAC_SCAN_REPORT_ERR_ID = 0x02, /* Invalid ActionID */
- HALMAC_SCAN_REPORT_ERR_TX = 0x03, /* Tx RsvdPage fail */
-
- HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF,
-};
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
-#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
-#define C2H_SUB_CMD_ID_C2H_DBG 0X00
-#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
-#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
-#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
-#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01
-#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
-#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
-#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01
-#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
-#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
-#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01
-#define C2H_SUB_CMD_ID_IQK_ACK 0X01
-#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01
-#define C2H_SUB_CMD_ID_PSD_ACK 0X01
-#define C2H_SUB_CMD_ID_PSD_DATA 0X04
-#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
-#define C2H_SUB_CMD_ID_IQK_DATA 0X06
-#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07
-#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08
-#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09
-#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A
-#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B
-#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C
-#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D
-#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E
-#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
-#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
-#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER
-#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
-#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
-#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET
-#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
-#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
-#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH
-#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
-#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING
-#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
-#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
-#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF
-#define H2C_CMD_ID_BT_COEX_ACK 0XFF
-#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
-#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF
-#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
-#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
-#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF
-#define H2C_CMD_ID_IQK_ACK 0XFF
-#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF
-#define H2C_CMD_ID_PSD_ACK 0XFF
-#define H2C_CMD_ID_CCX_RPT 0XFF
-#define C2H_HDR_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_HDR_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_HDR_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_HDR_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_HDR_GET_C2H_SUB_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
-#define C2H_HDR_SET_C2H_SUB_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
-#define C2H_HDR_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
-#define C2H_HDR_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
-#define C2H_DBG_GET_DBG_MSG(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
-#define C2H_DBG_SET_DBG_MSG(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
-#define BT_COEX_INFO_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
-#define BT_COEX_INFO_SET_DATA_START(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
-#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
-#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
-#define SCAN_STATUS_RPT_GET_H2C_SEQ(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
-#define SCAN_STATUS_RPT_SET_H2C_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
-#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
-#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
-#define H2C_ACK_HDR_GET_H2C_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define H2C_ACK_HDR_SET_H2C_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
-#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
-#define H2C_ACK_HDR_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 16)
-#define H2C_ACK_HDR_SET_H2C_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 16, __value)
-#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0XC, 0, 32)
-#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0XC, 0, 32, __value)
-#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X10, 0, 32)
-#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X10, 0, 32, __value)
-#define BT_COEX_ACK_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0XC, 0, 8)
-#define BT_COEX_ACK_SET_DATA_START(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0XC, 0, 8, __value)
-#define PSD_DATA_GET_SEGMENT_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 7)
-#define PSD_DATA_SET_SEGMENT_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 7, __value)
-#define PSD_DATA_GET_END_SEGMENT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 7, 1)
-#define PSD_DATA_SET_END_SEGMENT(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 7, 1, __value)
-#define PSD_DATA_GET_SEGMENT_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define PSD_DATA_SET_SEGMENT_SIZE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define PSD_DATA_GET_TOTAL_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
-#define PSD_DATA_SET_TOTAL_SIZE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
-#define PSD_DATA_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 0, 16)
-#define PSD_DATA_SET_H2C_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 0, 16, __value)
-#define PSD_DATA_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 16, 8)
-#define PSD_DATA_SET_DATA_START(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 16, 8, __value)
-#define EFUSE_DATA_GET_SEGMENT_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 7)
-#define EFUSE_DATA_SET_SEGMENT_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 7, __value)
-#define EFUSE_DATA_GET_END_SEGMENT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 7, 1)
-#define EFUSE_DATA_SET_END_SEGMENT(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 7, 1, __value)
-#define EFUSE_DATA_GET_SEGMENT_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define EFUSE_DATA_SET_SEGMENT_SIZE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define EFUSE_DATA_GET_TOTAL_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
-#define EFUSE_DATA_SET_TOTAL_SIZE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
-#define EFUSE_DATA_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 0, 16)
-#define EFUSE_DATA_SET_H2C_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 0, 16, __value)
-#define EFUSE_DATA_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 16, 8)
-#define EFUSE_DATA_SET_DATA_START(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 16, 8, __value)
-#define IQK_DATA_GET_SEGMENT_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 7)
-#define IQK_DATA_SET_SEGMENT_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 7, __value)
-#define IQK_DATA_GET_END_SEGMENT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 7, 1)
-#define IQK_DATA_SET_END_SEGMENT(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 7, 1, __value)
-#define IQK_DATA_GET_SEGMENT_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define IQK_DATA_SET_SEGMENT_SIZE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define IQK_DATA_GET_TOTAL_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
-#define IQK_DATA_SET_TOTAL_SIZE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
-#define IQK_DATA_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 0, 16)
-#define IQK_DATA_SET_H2C_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 0, 16, __value)
-#define IQK_DATA_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 16, 8)
-#define IQK_DATA_SET_DATA_START(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 16, 8, __value)
-#define CCX_RPT_GET_CCX_RPT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X4, 0, 129)
-#define CCX_RPT_SET_CCX_RPT(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X4, 0, 129, __value)
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
-#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
-#define CMD_ID_FW_OFFLOAD_H2C 0XFF
-#define CMD_ID_CHANNEL_SWITCH 0XFF
-#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
-#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
-#define CMD_ID_CFG_PARAMETER 0XFF
-#define CMD_ID_UPDATE_DATAPACK 0XFF
-#define CMD_ID_RUN_DATAPACK 0XFF
-#define CMD_ID_DOWNLOAD_FLASH 0XFF
-#define CMD_ID_UPDATE_PACKET 0XFF
-#define CMD_ID_GENERAL_INFO 0XFF
-#define CMD_ID_IQK 0XFF
-#define CMD_ID_POWER_TRACKING 0XFF
-#define CMD_ID_PSD 0XFF
-#define CMD_ID_P2PPS 0XFF
-#define CMD_ID_BT_COEX 0XFF
-#define CMD_ID_NAN_CTRL 0XFF
-#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
-#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
-#define CATEGORY_H2C_CMD_HEADER 0X00
-#define CATEGORY_FW_OFFLOAD_H2C 0X01
-#define CATEGORY_CHANNEL_SWITCH 0X01
-#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
-#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
-#define CATEGORY_CFG_PARAMETER 0X01
-#define CATEGORY_UPDATE_DATAPACK 0X01
-#define CATEGORY_RUN_DATAPACK 0X01
-#define CATEGORY_DOWNLOAD_FLASH 0X01
-#define CATEGORY_UPDATE_PACKET 0X01
-#define CATEGORY_GENERAL_INFO 0X01
-#define CATEGORY_IQK 0X01
-#define CATEGORY_POWER_TRACKING 0X01
-#define CATEGORY_PSD 0X01
-#define CATEGORY_P2PPS 0X01
-#define CATEGORY_BT_COEX 0X01
-#define CATEGORY_NAN_CTRL 0X01
-#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
-#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
-#define SUB_CMD_ID_CHANNEL_SWITCH 0X02
-#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
-#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
-#define SUB_CMD_ID_CFG_PARAMETER 0X08
-#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
-#define SUB_CMD_ID_RUN_DATAPACK 0X0A
-#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
-#define SUB_CMD_ID_UPDATE_PACKET 0X0C
-#define SUB_CMD_ID_GENERAL_INFO 0X0D
-#define SUB_CMD_ID_IQK 0X0E
-#define SUB_CMD_ID_POWER_TRACKING 0X0F
-#define SUB_CMD_ID_PSD 0X10
-#define SUB_CMD_ID_P2PPS 0X24
-#define SUB_CMD_ID_BT_COEX 0X60
-#define SUB_CMD_ID_NAN_CTRL 0XB2
-#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
-#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
-#define H2C_CMD_HEADER_GET_CATEGORY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 7)
-#define H2C_CMD_HEADER_SET_CATEGORY(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 7, __value)
-#define H2C_CMD_HEADER_GET_ACK(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 7, 1)
-#define H2C_CMD_HEADER_SET_ACK(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 7, 1, __value)
-#define H2C_CMD_HEADER_GET_TOTAL_LEN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 16)
-#define H2C_CMD_HEADER_SET_TOTAL_LEN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 16, __value)
-#define H2C_CMD_HEADER_GET_SEQ_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 16)
-#define H2C_CMD_HEADER_SET_SEQ_NUM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 16, __value)
-#define FW_OFFLOAD_H2C_GET_CATEGORY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 7)
-#define FW_OFFLOAD_H2C_SET_CATEGORY(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 7, __value)
-#define FW_OFFLOAD_H2C_GET_ACK(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 7, 1)
-#define FW_OFFLOAD_H2C_SET_ACK(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 7, 1, __value)
-#define FW_OFFLOAD_H2C_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define FW_OFFLOAD_H2C_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 16)
-#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 16, __value)
-#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 16)
-#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 16, __value)
-#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 16)
-#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 16, __value)
-#define CHANNEL_SWITCH_GET_SWITCH_START(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
-#define CHANNEL_SWITCH_SET_SWITCH_START(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
-#define CHANNEL_SWITCH_GET_DEST_CH_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
-#define CHANNEL_SWITCH_SET_DEST_CH_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
-#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 2, 1)
-#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 2, 1, __value)
-#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 3, 2)
-#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 3, 2, __value)
-#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
-#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
-#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
-#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
-#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 4)
-#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 4, __value)
-#define CHANNEL_SWITCH_GET_DEST_BW(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 28, 4)
-#define CHANNEL_SWITCH_SET_DEST_BW(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 28, 4, __value)
-#define CHANNEL_SWITCH_GET_DEST_CH(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
-#define CHANNEL_SWITCH_SET_DEST_CH(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
-#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 8, 8)
-#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 8, 8, __value)
-#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 8)
-#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 8, __value)
-#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 24, 8)
-#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 24, 8, __value)
-#define CHANNEL_SWITCH_GET_TSF_HIGH(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
-#define CHANNEL_SWITCH_SET_TSF_HIGH(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
-#define CHANNEL_SWITCH_GET_TSF_LOW(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 32)
-#define CHANNEL_SWITCH_SET_TSF_LOW(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 32, __value)
-#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 16)
-#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 16, __value)
-#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
-#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
-#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 4)
-#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 4, __value)
-#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 12, 4)
-#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 12, 4, __value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 32, __value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 32, __value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 32, __value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 32, __value)
-#define CFG_PARAMETER_GET_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
-#define CFG_PARAMETER_SET_NUM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
-#define CFG_PARAMETER_GET_INIT_CASE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 1)
-#define CFG_PARAMETER_SET_INIT_CASE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 1, __value)
-#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
-#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
-#define UPDATE_DATAPACK_GET_SIZE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
-#define UPDATE_DATAPACK_SET_SIZE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
-#define UPDATE_DATAPACK_GET_DATAPACK_ID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
-#define UPDATE_DATAPACK_SET_DATAPACK_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
-#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
-#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
-#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
-#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
-#define UPDATE_DATAPACK_GET_END_SEGMENT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 8, 1)
-#define UPDATE_DATAPACK_SET_END_SEGMENT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 8, 1, __value)
-#define RUN_DATAPACK_GET_DATAPACK_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
-#define RUN_DATAPACK_SET_DATAPACK_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
-#define DOWNLOAD_FLASH_GET_SPI_CMD(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
-#define DOWNLOAD_FLASH_SET_SPI_CMD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
-#define DOWNLOAD_FLASH_GET_LOCATION(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 16)
-#define DOWNLOAD_FLASH_SET_LOCATION(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 16, __value)
-#define DOWNLOAD_FLASH_GET_SIZE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 32)
-#define DOWNLOAD_FLASH_SET_SIZE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 32, __value)
-#define DOWNLOAD_FLASH_GET_START_ADDR(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
-#define DOWNLOAD_FLASH_SET_START_ADDR(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
-#define UPDATE_PACKET_GET_SIZE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
-#define UPDATE_PACKET_SET_SIZE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
-#define UPDATE_PACKET_GET_PACKET_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
-#define UPDATE_PACKET_SET_PACKET_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
-#define UPDATE_PACKET_GET_PACKET_LOC(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
-#define UPDATE_PACKET_SET_PACKET_LOC(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
-#define GENERAL_INFO_GET_REF_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
-#define GENERAL_INFO_SET_REF_TYPE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
-#define GENERAL_INFO_GET_RF_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 9)
-#define GENERAL_INFO_SET_RF_TYPE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 9, __value)
-#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
-#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
-#define IQK_GET_CLEAR(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
-#define IQK_SET_CLEAR(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
-#define IQK_GET_SEGMENT_IQK(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
-#define IQK_SET_SEGMENT_IQK(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
-#define POWER_TRACKING_GET_ENABLE_A(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
-#define POWER_TRACKING_SET_ENABLE_A(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
-#define POWER_TRACKING_GET_ENABLE_B(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
-#define POWER_TRACKING_SET_ENABLE_B(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
-#define POWER_TRACKING_GET_ENABLE_C(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 2, 1)
-#define POWER_TRACKING_SET_ENABLE_C(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 2, 1, __value)
-#define POWER_TRACKING_GET_ENABLE_D(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 3, 1)
-#define POWER_TRACKING_SET_ENABLE_D(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 3, 1, __value)
-#define POWER_TRACKING_GET_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 4, 3)
-#define POWER_TRACKING_SET_TYPE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 4, 3, __value)
-#define POWER_TRACKING_GET_BBSWING_INDEX(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
-#define POWER_TRACKING_SET_BBSWING_INDEX(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 8, 8, __value)
-#define POWER_TRACKING_GET_TSSI_VALUE_A(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_A(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 8, __value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 8, __value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X10, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 8, 8, __value)
-#define POWER_TRACKING_GET_TSSI_VALUE_B(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X10, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_B(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 16, 8, __value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 8, __value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X14, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 8, 8, __value)
-#define POWER_TRACKING_GET_TSSI_VALUE_C(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X14, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_C(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 16, 8, __value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 8, __value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 8, 8, __value)
-#define POWER_TRACKING_GET_TSSI_VALUE_D(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_D(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 16, 8, __value)
-#define PSD_GET_START_PSD(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
-#define PSD_SET_START_PSD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
-#define PSD_GET_END_PSD(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 16)
-#define PSD_SET_END_PSD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 16, __value)
-#define P2PPS_GET_OFFLOAD_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
-#define P2PPS_SET_OFFLOAD_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
-#define P2PPS_GET_ROLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
-#define P2PPS_SET_ROLE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
-#define P2PPS_GET_CTWINDOW_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 2, 1)
-#define P2PPS_SET_CTWINDOW_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 2, 1, __value)
-#define P2PPS_GET_NOA_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 3, 1)
-#define P2PPS_SET_NOA_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 3, 1, __value)
-#define P2PPS_GET_NOA_SEL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 4, 1)
-#define P2PPS_SET_NOA_SEL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 4, 1, __value)
-#define P2PPS_GET_ALLSTASLEEP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 5, 1)
-#define P2PPS_SET_ALLSTASLEEP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 5, 1, __value)
-#define P2PPS_GET_DISCOVERY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 6, 1)
-#define P2PPS_SET_DISCOVERY(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 6, 1, __value)
-#define P2PPS_GET_P2P_PORT_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
-#define P2PPS_SET_P2P_PORT_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
-#define P2PPS_GET_P2P_GROUP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
-#define P2PPS_SET_P2P_GROUP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
-#define P2PPS_GET_P2P_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
-#define P2PPS_SET_P2P_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
-#define P2PPS_GET_CTWINDOW_LENGTH(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
-#define P2PPS_SET_CTWINDOW_LENGTH(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
-#define P2PPS_GET_NOA_DURATION_PARA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
-#define P2PPS_SET_NOA_DURATION_PARA(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
-#define P2PPS_GET_NOA_INTERVAL_PARA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 32)
-#define P2PPS_SET_NOA_INTERVAL_PARA(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 32, __value)
-#define P2PPS_GET_NOA_START_TIME_PARA(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 32)
-#define P2PPS_SET_NOA_START_TIME_PARA(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 32, __value)
-#define P2PPS_GET_NOA_COUNT_PARA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 32)
-#define P2PPS_SET_NOA_COUNT_PARA(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 32, __value)
-#define BT_COEX_GET_DATA_START(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
-#define BT_COEX_SET_DATA_START(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
-#define NAN_CTRL_GET_NAN_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 2)
-#define NAN_CTRL_SET_NAN_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 2, __value)
-#define NAN_CTRL_GET_SUPPORT_BAND(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 2)
-#define NAN_CTRL_SET_SUPPORT_BAND(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 2, __value)
-#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 10, 1)
-#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 10, 1, __value)
-#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 11, 1)
-#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 11, 1, __value)
-#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
-#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
-#define NAN_CTRL_GET_CHANNEL_2G(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
-#define NAN_CTRL_SET_CHANNEL_2G(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
-#define NAN_CTRL_GET_CHANNEL_5G(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
-#define NAN_CTRL_SET_CHANNEL_5G(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
-#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
-#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
-#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
-#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
-#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 16)
-#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 16, __value)
-#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 16)
-#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 16, __value)
-#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 8)
-#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 8, __value)
-#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X10, 8, 8)
-#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 8, 8, __value)
-#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 16)
-#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 16, __value)
-#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X14, 16, 16)
-#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 16, 16, __value)
-#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 8)
-#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 8, __value)
-#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 8, 8)
-#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 8, 8, __value)
-#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 16)
-#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 16, __value)
-#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X1C, 16, 16)
-#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 16, 16, __value)
-#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
-#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
-#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
-#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
-#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 16)
-#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 16, __value)
-#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 16)
-#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 16, __value)
-#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 8)
-#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 8, __value)
-#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X10, 8, 8)
-#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 8, 8, __value)
-#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 16)
-#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 16, __value)
-#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X14, 16, 16)
-#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 16, 16, __value)
-#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 8)
-#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 8, __value)
-#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X18, 8, 8)
-#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 8, 8, __value)
-#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 16)
-#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 16, __value)
-#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X1C, 16, 16)
-#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 16, 16, __value)
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
-#define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
-#define PHY_PARAMETER_INFO_GET_LENGTH(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 0, 8)
-#define PHY_PARAMETER_INFO_SET_LENGTH(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 0, 8, __value)
-#define PHY_PARAMETER_INFO_GET_IO_CMD(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 8, 7)
-#define PHY_PARAMETER_INFO_SET_IO_CMD(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 8, 7, __value)
-#define PHY_PARAMETER_INFO_GET_MSK_EN(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 15, 1)
-#define PHY_PARAMETER_INFO_SET_MSK_EN(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 15, 1, __value)
-#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
-#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
-#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
-#define PHY_PARAMETER_INFO_GET_RF_ADDR(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_RF_ADDR(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
-#define PHY_PARAMETER_INFO_GET_IO_ADDR(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 16)
-#define PHY_PARAMETER_INFO_SET_IO_ADDR(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 16, __value)
-#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 16)
-#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 16, __value)
-#define PHY_PARAMETER_INFO_GET_RF_PATH(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 24, 8)
-#define PHY_PARAMETER_INFO_SET_RF_PATH(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 24, 8, __value)
-#define PHY_PARAMETER_INFO_GET_DATA(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X04, 0, 32)
-#define PHY_PARAMETER_INFO_SET_DATA(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X04, 0, 32, __value)
-#define PHY_PARAMETER_INFO_GET_MASK(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X08, 0, 32)
-#define PHY_PARAMETER_INFO_SET_MASK(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X08, 0, 32, __value)
-#define CHANNEL_INFO_GET_CHANNEL(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 0, 8)
-#define CHANNEL_INFO_SET_CHANNEL(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 0, 8, __value)
-#define CHANNEL_INFO_GET_PRI_CH_IDX(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 8, 4)
-#define CHANNEL_INFO_SET_PRI_CH_IDX(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 8, 4, __value)
-#define CHANNEL_INFO_GET_BANDWIDTH(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 12, 4)
-#define CHANNEL_INFO_SET_BANDWIDTH(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 12, 4, __value)
-#define CHANNEL_INFO_GET_TIMEOUT(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
-#define CHANNEL_INFO_SET_TIMEOUT(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
-#define CHANNEL_INFO_GET_ACTION_ID(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 24, 7)
-#define CHANNEL_INFO_SET_ACTION_ID(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 24, 7, __value)
-#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 31, 1)
-#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 31, 1, __value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 0, 7)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 0, 7, __value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 7, 1)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 7, 1, __value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 8, 8)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 8, 8, __value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__extra_info) \
- LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 1)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__extra_info, __value) \
- SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 1, __value)
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef HALMAC_INTF_PHY_CMD
-#define HALMAC_INTF_PHY_CMD
-
-/* Cut mask */
-enum halmac_intf_phy_cut {
- HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0),
- HALMAC_INTF_PHY_CUT_A = BIT(1),
- HALMAC_INTF_PHY_CUT_B = BIT(2),
- HALMAC_INTF_PHY_CUT_C = BIT(3),
- HALMAC_INTF_PHY_CUT_D = BIT(4),
- HALMAC_INTF_PHY_CUT_E = BIT(5),
- HALMAC_INTF_PHY_CUT_F = BIT(6),
- HALMAC_INTF_PHY_CUT_G = BIT(7),
- HALMAC_INTF_PHY_CUT_ALL = 0x7FFF,
-};
-
-/* IP selection */
-enum halmac_ip_sel {
- HALMAC_IP_SEL_INTF_PHY = 0,
- HALMAC_IP_SEL_MAC = 1,
- HALMAC_IP_SEL_PCIE_DBI = 2,
- HALMAC_IP_SEL_UNDEFINE = 0x7FFF,
-};
-
-/* Platform mask */
-enum halmac_intf_phy_platform {
- HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF,
-};
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
-#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
-#define CMD_ID_C2H 0X00
-#define CMD_ID_DBG 0X00
-#define CMD_ID_C2H_LB 0X01
-#define CMD_ID_C2H_SND_TXBF 0X02
-#define CMD_ID_C2H_CCX_RPT 0X03
-#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
-#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
-#define CMD_ID_C2H_RA_RPT 0X0C
-#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
-#define CMD_ID_C2H_RA_PARA_RPT 0X0E
-#define CMD_ID_C2H_CUR_CHANNEL 0X10
-#define CMD_ID_C2H_GPIO_WAKEUP 0X14
-#define C2H_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define DBG_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define DBG_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define DBG_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define DBG_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define DBG_GET_DBG_STR1(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
-#define DBG_SET_DBG_STR1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
-#define DBG_GET_DBG_STR2(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
-#define DBG_SET_DBG_STR2(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
-#define DBG_GET_DBG_STR3(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
-#define DBG_SET_DBG_STR3(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
-#define DBG_GET_DBG_STR4(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define DBG_SET_DBG_STR4(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define DBG_GET_DBG_STR5(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
-#define DBG_SET_DBG_STR5(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
-#define DBG_GET_DBG_STR6(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
-#define DBG_SET_DBG_STR6(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
-#define DBG_GET_DBG_STR7(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
-#define DBG_SET_DBG_STR7(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
-#define DBG_GET_DBG_STR8(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
-#define DBG_SET_DBG_STR8(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
-#define DBG_GET_DBG_STR9(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 16, 8)
-#define DBG_SET_DBG_STR9(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 16, 8, __value)
-#define DBG_GET_DBG_STR10(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 24, 8)
-#define DBG_SET_DBG_STR10(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 24, 8, __value)
-#define DBG_GET_DBG_STR11(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 0, 8)
-#define DBG_SET_DBG_STR11(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 0, 8, __value)
-#define DBG_GET_DBG_STR12(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 8, 8)
-#define DBG_SET_DBG_STR12(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 8, 8, __value)
-#define DBG_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define DBG_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define DBG_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define DBG_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_LB_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_LB_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_LB_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_LB_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_LB_GET_PAYLOAD1(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 16)
-#define C2H_LB_SET_PAYLOAD1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 16, __value)
-#define C2H_LB_GET_PAYLOAD2(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 32)
-#define C2H_LB_SET_PAYLOAD2(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 32, __value)
-#define C2H_LB_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_LB_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_LB_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_LB_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_SND_TXBF_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_SND_TXBF_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_SND_TXBF_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_SND_TXBF_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_SND_TXBF_GET_SND_RESULT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 1)
-#define C2H_SND_TXBF_SET_SND_RESULT(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 1, __value)
-#define C2H_SND_TXBF_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_SND_TXBF_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_SND_TXBF_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_SND_TXBF_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_CCX_RPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_CCX_RPT_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_CCX_RPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_CCX_RPT_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_CCX_RPT_GET_QSEL(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 5)
-#define C2H_CCX_RPT_SET_QSEL(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 5, __value)
-#define C2H_CCX_RPT_GET_BMC(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 21, 1)
-#define C2H_CCX_RPT_SET_BMC(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 21, 1, __value)
-#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 22, 1)
-#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 22, 1, __value)
-#define C2H_CCX_RPT_GET_RETRY_OVER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 23, 1)
-#define C2H_CCX_RPT_SET_RETRY_OVER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 23, 1, __value)
-#define C2H_CCX_RPT_GET_MACID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
-#define C2H_CCX_RPT_SET_MACID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
-#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 6)
-#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 6, __value)
-#define C2H_CCX_RPT_GET_QUEUE7_0(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define C2H_CCX_RPT_SET_QUEUE7_0(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define C2H_CCX_RPT_GET_QUEUE15_8(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
-#define C2H_CCX_RPT_SET_QUEUE15_8(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
-#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
-#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
-#define C2H_CCX_RPT_GET_SW_DEFINE_0(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
-#define C2H_CCX_RPT_SET_SW_DEFINE_0(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
-#define C2H_CCX_RPT_GET_SW_DEFINE_1(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 4)
-#define C2H_CCX_RPT_SET_SW_DEFINE_1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 4, __value)
-#define C2H_CCX_RPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_CCX_RPT_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_CCX_RPT_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_CCX_RPT_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X08, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 16, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X08, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 24, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X0C, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 0, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X0C, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 8, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 7)
-#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 7, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_RA_RPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_RA_RPT_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_RA_RPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_RA_RPT_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_RA_RPT_GET_RATE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
-#define C2H_RA_RPT_SET_RATE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
-#define C2H_RA_RPT_GET_MACID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
-#define C2H_RA_RPT_SET_MACID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
-#define C2H_RA_RPT_GET_USE_LDPC(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 1)
-#define C2H_RA_RPT_SET_USE_LDPC(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 1, __value)
-#define C2H_RA_RPT_GET_USE_TXBF(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 1, 1)
-#define C2H_RA_RPT_SET_USE_TXBF(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 1, 1, __value)
-#define C2H_RA_RPT_GET_COLLISION_STATE(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define C2H_RA_RPT_SET_COLLISION_STATE(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define C2H_RA_RPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_RA_RPT_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_RA_RPT_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_RA_RPT_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_SEQ(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_SPECIAL_STATISTICS_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA0(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA0(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA1(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA1(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA2(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA2(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA3(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA3(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA4(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA4(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA5(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA5(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA6(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA6(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA7(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X08, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA7(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 16, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_LEN(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_RA_PARA_RPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_RA_PARA_RPT_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_RA_PARA_RPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_RA_PARA_RPT_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_RA_PARA_RPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_RA_PARA_RPT_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_RA_PARA_RPT_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_RA_PARA_RPT_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_CUR_CHANNEL_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_CUR_CHANNEL_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_CUR_CHANNEL_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_CUR_CHANNEL_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__c2h) \
- LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
-#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
-#define C2H_CUR_CHANNEL_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_CUR_CHANNEL_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_CUR_CHANNEL_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_CUR_CHANNEL_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#define C2H_GPIO_WAKEUP_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
-#define C2H_GPIO_WAKEUP_SET_CMD_ID(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
-#define C2H_GPIO_WAKEUP_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
-#define C2H_GPIO_WAKEUP_SET_SEQ(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
-#define C2H_GPIO_WAKEUP_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
-#define C2H_GPIO_WAKEUP_SET_LEN(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
-#define C2H_GPIO_WAKEUP_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
-#define C2H_GPIO_WAKEUP_SET_TRIGGER(__c2h, __value) \
- SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_
-#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_
-#define CMD_ID_ORIGINAL_H2C 0X00
-#define CMD_ID_H2C2H_LB 0X0
-#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06
-#define CMD_ID_RSVD_PAGE 0X0
-#define CMD_ID_MEDIA_STATUS_RPT 0X01
-#define CMD_ID_KEEP_ALIVE 0X03
-#define CMD_ID_DISCONNECT_DECISION 0X04
-#define CMD_ID_AP_OFFLOAD 0X08
-#define CMD_ID_BCN_RSVDPAGE 0X09
-#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A
-#define CMD_ID_SET_PWR_MODE 0X00
-#define CMD_ID_PS_TUNING_PARA 0X01
-#define CMD_ID_PS_TUNING_PARA_II 0X02
-#define CMD_ID_PS_LPS_PARA 0X03
-#define CMD_ID_P2P_PS_OFFLOAD 0X04
-#define CMD_ID_PS_SCAN_EN 0X05
-#define CMD_ID_SAP_PS 0X06
-#define CMD_ID_INACTIVE_PS 0X07
-#define CMD_ID_MACID_CFG 0X00
-#define CMD_ID_TXBF 0X01
-#define CMD_ID_RSSI_SETTING 0X02
-#define CMD_ID_AP_REQ_TXRPT 0X03
-#define CMD_ID_INIT_RATE_COLLECTION 0X04
-#define CMD_ID_IQK_OFFLOAD 0X05
-#define CMD_ID_MACID_CFG_3SS 0X06
-#define CMD_ID_RA_PARA_ADJUST 0X07
-#define CMD_ID_WWLAN 0X00
-#define CMD_ID_REMOTE_WAKE_CTRL 0X01
-#define CMD_ID_AOAC_GLOBAL_INFO 0X02
-#define CMD_ID_AOAC_RSVD_PAGE 0X03
-#define CMD_ID_AOAC_RSVD_PAGE2 0X04
-#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05
-#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07
-#define CMD_ID_AOAC_RSVD_PAGE3 0X08
-#define CLASS_ORIGINAL_H2C 0X00
-#define CLASS_H2C2H_LB 0X07
-#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04
-#define CLASS_RSVD_PAGE 0X0
-#define CLASS_MEDIA_STATUS_RPT 0X0
-#define CLASS_KEEP_ALIVE 0X0
-#define CLASS_DISCONNECT_DECISION 0X0
-#define CLASS_AP_OFFLOAD 0X0
-#define CLASS_BCN_RSVDPAGE 0X0
-#define CLASS_PROBE_RSP_RSVDPAGE 0X0
-#define CLASS_SET_PWR_MODE 0X01
-#define CLASS_PS_TUNING_PARA 0X01
-#define CLASS_PS_TUNING_PARA_II 0X01
-#define CLASS_PS_LPS_PARA 0X01
-#define CLASS_P2P_PS_OFFLOAD 0X01
-#define CLASS_PS_SCAN_EN 0X1
-#define CLASS_SAP_PS 0X1
-#define CLASS_INACTIVE_PS 0X1
-#define CLASS_MACID_CFG 0X2
-#define CLASS_TXBF 0X2
-#define CLASS_RSSI_SETTING 0X2
-#define CLASS_AP_REQ_TXRPT 0X2
-#define CLASS_INIT_RATE_COLLECTION 0X2
-#define CLASS_IQK_OFFLOAD 0X2
-#define CLASS_MACID_CFG_3SS 0X2
-#define CLASS_RA_PARA_ADJUST 0X02
-#define CLASS_WWLAN 0X4
-#define CLASS_REMOTE_WAKE_CTRL 0X4
-#define CLASS_AOAC_GLOBAL_INFO 0X04
-#define CLASS_AOAC_RSVD_PAGE 0X04
-#define CLASS_AOAC_RSVD_PAGE2 0X04
-#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04
-#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04
-#define CLASS_AOAC_RSVD_PAGE3 0X04
-#define ORIGINAL_H2C_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define ORIGINAL_H2C_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define ORIGINAL_H2C_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define ORIGINAL_H2C_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define H2C2H_LB_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define H2C2H_LB_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define H2C2H_LB_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define H2C2H_LB_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define H2C2H_LB_GET_SEQ(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define H2C2H_LB_SET_SEQ(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define H2C2H_LB_GET_PAYLOAD1(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 16)
-#define H2C2H_LB_SET_PAYLOAD1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 16, __value)
-#define H2C2H_LB_GET_PAYLOAD2(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 32)
-#define H2C2H_LB_SET_PAYLOAD2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 32, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 17)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 17, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define RSVD_PAGE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define RSVD_PAGE_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define RSVD_PAGE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define RSVD_PAGE_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define RSVD_PAGE_GET_LOC_PROBE_RSP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define RSVD_PAGE_SET_LOC_PROBE_RSP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define RSVD_PAGE_GET_LOC_PS_POLL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define RSVD_PAGE_SET_LOC_PS_POLL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define RSVD_PAGE_GET_LOC_NULL_DATA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define RSVD_PAGE_SET_LOC_NULL_DATA(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define RSVD_PAGE_GET_LOC_QOS_NULL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define RSVD_PAGE_SET_LOC_QOS_NULL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define RSVD_PAGE_GET_LOC_CTS2SELF(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
-#define RSVD_PAGE_SET_LOC_CTS2SELF(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
-#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
-#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
-#define MEDIA_STATUS_RPT_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define MEDIA_STATUS_RPT_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define MEDIA_STATUS_RPT_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define MEDIA_STATUS_RPT_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define MEDIA_STATUS_RPT_GET_OP_MODE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define MEDIA_STATUS_RPT_SET_OP_MODE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define MEDIA_STATUS_RPT_GET_MACID_IN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define MEDIA_STATUS_RPT_SET_MACID_IN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define MEDIA_STATUS_RPT_GET_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define MEDIA_STATUS_RPT_SET_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define MEDIA_STATUS_RPT_GET_MACID_END(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define MEDIA_STATUS_RPT_SET_MACID_END(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define KEEP_ALIVE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define KEEP_ALIVE_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define KEEP_ALIVE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define KEEP_ALIVE_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define KEEP_ALIVE_GET_ENABLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define KEEP_ALIVE_SET_ENABLE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define KEEP_ALIVE_GET_PKT_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
-#define KEEP_ALIVE_SET_PKT_TYPE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
-#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define DISCONNECT_DECISION_GET_CMD_ID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define DISCONNECT_DECISION_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define DISCONNECT_DECISION_GET_CLASS(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define DISCONNECT_DECISION_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define DISCONNECT_DECISION_GET_ENABLE(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define DISCONNECT_DECISION_SET_ENABLE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
-#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
-#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
-#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
-#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define AP_OFFLOAD_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define AP_OFFLOAD_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define AP_OFFLOAD_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define AP_OFFLOAD_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define AP_OFFLOAD_GET_ON(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define AP_OFFLOAD_SET_ON(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define AP_OFFLOAD_GET_LINKED(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
-#define AP_OFFLOAD_SET_LINKED(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
-#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
-#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
-#define AP_OFFLOAD_GET_WAKE_FLAG(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
-#define AP_OFFLOAD_SET_WAKE_FLAG(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
-#define AP_OFFLOAD_GET_HIDDEN_ROOT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 1)
-#define AP_OFFLOAD_SET_HIDDEN_ROOT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 1, __value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP1(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 17, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 17, 1, __value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP2(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 18, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 18, 1, __value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP3(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 19, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP3(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 19, 1, __value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP4(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 20, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP4(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 20, 1, __value)
-#define AP_OFFLOAD_GET_DENYANY_ROOT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 1)
-#define AP_OFFLOAD_SET_DENYANY_ROOT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 1, __value)
-#define AP_OFFLOAD_GET_DENYANY_VAP1(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 25, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 25, 1, __value)
-#define AP_OFFLOAD_GET_DENYANY_VAP2(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 26, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 26, 1, __value)
-#define AP_OFFLOAD_GET_DENYANY_VAP3(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 27, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP3(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 27, 1, __value)
-#define AP_OFFLOAD_GET_DENYANY_VAP4(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 28, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP4(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 28, 1, __value)
-#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define AP_OFFLOAD_GET_LEN_IV_PAIR(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
-#define AP_OFFLOAD_SET_LEN_IV_PAIR(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
-#define AP_OFFLOAD_GET_LEN_IV_GRP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
-#define AP_OFFLOAD_SET_LEN_IV_GRP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
-#define BCN_RSVDPAGE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define BCN_RSVDPAGE_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define BCN_RSVDPAGE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define BCN_RSVDPAGE_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define BCN_RSVDPAGE_GET_LOC_ROOT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define BCN_RSVDPAGE_SET_LOC_ROOT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define BCN_RSVDPAGE_GET_LOC_VAP1(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define BCN_RSVDPAGE_GET_LOC_VAP2(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define BCN_RSVDPAGE_GET_LOC_VAP3(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP3(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define BCN_RSVDPAGE_GET_LOC_VAP4(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP4(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define PROBE_RSP_RSVDPAGE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define PROBE_RSP_RSVDPAGE_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define SET_PWR_MODE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define SET_PWR_MODE_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define SET_PWR_MODE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define SET_PWR_MODE_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define SET_PWR_MODE_GET_MODE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 7)
-#define SET_PWR_MODE_SET_MODE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 7, __value)
-#define SET_PWR_MODE_GET_CLK_REQUEST(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
-#define SET_PWR_MODE_SET_CLK_REQUEST(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
-#define SET_PWR_MODE_GET_RLBM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 4)
-#define SET_PWR_MODE_SET_RLBM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 4, __value)
-#define SET_PWR_MODE_GET_SMART_PS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 20, 4)
-#define SET_PWR_MODE_SET_SMART_PS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 20, 4, __value)
-#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 1)
-#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 1, __value)
-#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 2, 1)
-#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 2, 1, __value)
-#define SET_PWR_MODE_GET_PORT_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 5, 3)
-#define SET_PWR_MODE_SET_PORT_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 5, 3, __value)
-#define SET_PWR_MODE_GET_PWR_STATE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define SET_PWR_MODE_SET_PWR_STATE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 1)
-#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 1, __value)
-#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 17, 1)
-#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 17, 1, __value)
-#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 18, 1)
-#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 18, 1, __value)
-#define SET_PWR_MODE_GET_PROTECT_BCN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 19, 1)
-#define SET_PWR_MODE_SET_PROTECT_BCN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 19, 1, __value)
-#define SET_PWR_MODE_GET_SILENCE_PERIOD(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 20, 1)
-#define SET_PWR_MODE_SET_SILENCE_PERIOD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 20, 1, __value)
-#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 21, 1)
-#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 21, 1, __value)
-#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 22, 1)
-#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 22, 1, __value)
-#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 1)
-#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 1, __value)
-#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 25, 3)
-#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 25, 3, __value)
-#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 28, 4)
-#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 28, 4, __value)
-#define PS_TUNING_PARA_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define PS_TUNING_PARA_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define PS_TUNING_PARA_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define PS_TUNING_PARA_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 7)
-#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 7, __value)
-#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
-#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
-#define PS_TUNING_PARA_GET_PS_TIME_OUT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 4)
-#define PS_TUNING_PARA_SET_PS_TIME_OUT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 4, __value)
-#define PS_TUNING_PARA_GET_ADOPT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define PS_TUNING_PARA_SET_ADOPT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define PS_TUNING_PARA_II_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define PS_TUNING_PARA_II_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define PS_TUNING_PARA_II_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define PS_TUNING_PARA_II_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 7)
-#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 7, __value)
-#define PS_TUNING_PARA_II_GET_ADOPT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
-#define PS_TUNING_PARA_II_SET_ADOPT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
-#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define PS_LPS_PARA_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define PS_LPS_PARA_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define PS_LPS_PARA_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define PS_LPS_PARA_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define PS_LPS_PARA_GET_LPS_CONTROL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define PS_LPS_PARA_SET_LPS_CONTROL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define P2P_PS_OFFLOAD_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define P2P_PS_OFFLOAD_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define P2P_PS_OFFLOAD_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define P2P_PS_OFFLOAD_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define P2P_PS_OFFLOAD_GET_ROLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define P2P_PS_OFFLOAD_SET_ROLE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
-#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
-#define P2P_PS_OFFLOAD_GET_NOA0_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
-#define P2P_PS_OFFLOAD_SET_NOA0_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
-#define P2P_PS_OFFLOAD_GET_NOA1_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
-#define P2P_PS_OFFLOAD_SET_NOA1_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
-#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 13, 1)
-#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 13, 1, __value)
-#define P2P_PS_OFFLOAD_GET_DISCOVERY(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 14, 1)
-#define P2P_PS_OFFLOAD_SET_DISCOVERY(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 14, 1, __value)
-#define PS_SCAN_EN_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define PS_SCAN_EN_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define PS_SCAN_EN_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define PS_SCAN_EN_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define PS_SCAN_EN_GET_ENABLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define PS_SCAN_EN_SET_ENABLE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define SAP_PS_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define SAP_PS_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define SAP_PS_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define SAP_PS_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define SAP_PS_GET_ENABLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define SAP_PS_SET_ENABLE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define SAP_PS_GET_EN_PS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define SAP_PS_SET_EN_PS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define SAP_PS_GET_EN_LP_RX(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
-#define SAP_PS_SET_EN_LP_RX(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
-#define SAP_PS_GET_MANUAL_32K(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
-#define SAP_PS_SET_MANUAL_32K(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
-#define SAP_PS_GET_DURATION(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define SAP_PS_SET_DURATION(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define INACTIVE_PS_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define INACTIVE_PS_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define INACTIVE_PS_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define INACTIVE_PS_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define INACTIVE_PS_GET_ENABLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define INACTIVE_PS_SET_ENABLE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define INACTIVE_PS_GET_FREQUENCY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define INACTIVE_PS_SET_FREQUENCY(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define INACTIVE_PS_GET_DURATION(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define INACTIVE_PS_SET_DURATION(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define MACID_CFG_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define MACID_CFG_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define MACID_CFG_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define MACID_CFG_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define MACID_CFG_GET_MAC_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define MACID_CFG_SET_MAC_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define MACID_CFG_GET_RATE_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 5)
-#define MACID_CFG_SET_RATE_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 5, __value)
-#define MACID_CFG_GET_SGI(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 23, 1)
-#define MACID_CFG_SET_SGI(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 23, 1, __value)
-#define MACID_CFG_GET_BW(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 2)
-#define MACID_CFG_SET_BW(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 2, __value)
-#define MACID_CFG_GET_LDPC_CAP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 26, 1)
-#define MACID_CFG_SET_LDPC_CAP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 26, 1, __value)
-#define MACID_CFG_GET_NO_UPDATE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 27, 1)
-#define MACID_CFG_SET_NO_UPDATE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 27, 1, __value)
-#define MACID_CFG_GET_WHT_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 28, 2)
-#define MACID_CFG_SET_WHT_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 28, 2, __value)
-#define MACID_CFG_GET_DISPT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 30, 1)
-#define MACID_CFG_SET_DISPT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 30, 1, __value)
-#define MACID_CFG_GET_DISRA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 31, 1)
-#define MACID_CFG_SET_DISRA(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 31, 1, __value)
-#define MACID_CFG_GET_RATE_MASK7_0(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define MACID_CFG_SET_RATE_MASK7_0(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define MACID_CFG_GET_RATE_MASK15_8(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define MACID_CFG_SET_RATE_MASK15_8(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define MACID_CFG_GET_RATE_MASK23_16(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
-#define MACID_CFG_SET_RATE_MASK23_16(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
-#define MACID_CFG_GET_RATE_MASK31_24(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
-#define MACID_CFG_SET_RATE_MASK31_24(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
-#define TXBF_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define TXBF_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define TXBF_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define TXBF_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define TXBF_GET_NDPA0_HEAD_PAGE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define TXBF_SET_NDPA0_HEAD_PAGE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define TXBF_GET_NDPA1_HEAD_PAGE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define TXBF_SET_NDPA1_HEAD_PAGE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define TXBF_GET_PERIOD_0(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define TXBF_SET_PERIOD_0(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define RSSI_SETTING_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define RSSI_SETTING_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define RSSI_SETTING_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define RSSI_SETTING_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define RSSI_SETTING_GET_MAC_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define RSSI_SETTING_SET_MAC_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define RSSI_SETTING_GET_RSSI(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 7)
-#define RSSI_SETTING_SET_RSSI(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 7, __value)
-#define RSSI_SETTING_GET_RA_INFO(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define RSSI_SETTING_SET_RA_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define AP_REQ_TXRPT_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define AP_REQ_TXRPT_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define AP_REQ_TXRPT_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define AP_REQ_TXRPT_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define AP_REQ_TXRPT_GET_STA1_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define AP_REQ_TXRPT_SET_STA1_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define AP_REQ_TXRPT_GET_STA2_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define AP_REQ_TXRPT_SET_STA2_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 1)
-#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 1, __value)
-#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 25, 1)
-#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 25, 1, __value)
-#define INIT_RATE_COLLECTION_GET_CMD_ID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define INIT_RATE_COLLECTION_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define INIT_RATE_COLLECTION_GET_CLASS(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define INIT_RATE_COLLECTION_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define INIT_RATE_COLLECTION_GET_STA1_MACID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define INIT_RATE_COLLECTION_SET_STA1_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define INIT_RATE_COLLECTION_GET_STA2_MACID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define INIT_RATE_COLLECTION_SET_STA2_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define INIT_RATE_COLLECTION_GET_STA3_MACID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define INIT_RATE_COLLECTION_SET_STA3_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define INIT_RATE_COLLECTION_GET_STA4_MACID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define INIT_RATE_COLLECTION_SET_STA4_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define INIT_RATE_COLLECTION_GET_STA5_MACID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define INIT_RATE_COLLECTION_SET_STA5_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define INIT_RATE_COLLECTION_GET_STA6_MACID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
-#define INIT_RATE_COLLECTION_SET_STA6_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
-#define INIT_RATE_COLLECTION_GET_STA7_MACID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
-#define INIT_RATE_COLLECTION_SET_STA7_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
-#define IQK_OFFLOAD_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define IQK_OFFLOAD_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define IQK_OFFLOAD_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define IQK_OFFLOAD_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define IQK_OFFLOAD_GET_CHANNEL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define IQK_OFFLOAD_SET_CHANNEL(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define IQK_OFFLOAD_GET_BWBAND(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define IQK_OFFLOAD_SET_BWBAND(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define IQK_OFFLOAD_GET_EXTPALNA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define IQK_OFFLOAD_SET_EXTPALNA(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define MACID_CFG_3SS_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define MACID_CFG_3SS_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define MACID_CFG_3SS_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define MACID_CFG_3SS_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define MACID_CFG_3SS_GET_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define MACID_CFG_3SS_SET_MACID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define RA_PARA_ADJUST_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define RA_PARA_ADJUST_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define RA_PARA_ADJUST_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define RA_PARA_ADJUST_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define RA_PARA_ADJUST_GET_MAC_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define RA_PARA_ADJUST_SET_MAC_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define RA_PARA_ADJUST_GET_RATE_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define RA_PARA_ADJUST_SET_RATE_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
-#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
-#define WWLAN_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define WWLAN_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define WWLAN_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define WWLAN_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define WWLAN_GET_FUNC_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define WWLAN_SET_FUNC_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define WWLAN_GET_PATTERM_MAT_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define WWLAN_SET_PATTERM_MAT_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define WWLAN_GET_MAGIC_PKT_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
-#define WWLAN_SET_MAGIC_PKT_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
-#define WWLAN_GET_UNICAST_WAKEUP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
-#define WWLAN_SET_UNICAST_WAKEUP_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
-#define WWLAN_GET_ALL_PKT_DROP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
-#define WWLAN_SET_ALL_PKT_DROP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
-#define WWLAN_GET_GPIO_ACTIVE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 13, 1)
-#define WWLAN_SET_GPIO_ACTIVE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 13, 1, __value)
-#define WWLAN_GET_REKEY_WAKEUP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 14, 1)
-#define WWLAN_SET_REKEY_WAKEUP_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 14, 1, __value)
-#define WWLAN_GET_DEAUTH_WAKEUP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
-#define WWLAN_SET_DEAUTH_WAKEUP_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
-#define WWLAN_GET_GPIO_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 7)
-#define WWLAN_SET_GPIO_NUM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 7, __value)
-#define WWLAN_GET_DATAPIN_WAKEUP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 23, 1)
-#define WWLAN_SET_DATAPIN_WAKEUP_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 23, 1, __value)
-#define WWLAN_GET_GPIO_DURATION(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define WWLAN_SET_GPIO_DURATION(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define WWLAN_GET_GPIO_PLUS_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 1)
-#define WWLAN_SET_GPIO_PLUS_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 1, __value)
-#define WWLAN_GET_GPIO_PULSE_COUNT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 1, 7)
-#define WWLAN_SET_GPIO_PULSE_COUNT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 1, 7, __value)
-#define WWLAN_GET_DISABLE_UPHY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 1)
-#define WWLAN_SET_DISABLE_UPHY(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 1, __value)
-#define WWLAN_GET_HST2DEV_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 9, 1)
-#define WWLAN_SET_HST2DEV_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 9, 1, __value)
-#define WWLAN_GET_GPIO_DURATION_MS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 10, 1)
-#define WWLAN_SET_GPIO_DURATION_MS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 10, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define REMOTE_WAKE_CTRL_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define REMOTE_WAKE_CTRL_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define REMOTE_WAKE_CTRL_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
-#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_ARP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
-#define REMOTE_WAKE_CTRL_SET_ARP_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_NDP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
-#define REMOTE_WAKE_CTRL_SET_NDP_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_GTK_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
-#define REMOTE_WAKE_CTRL_SET_GTK_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
-#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 13, 1)
-#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 13, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 14, 1)
-#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 14, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
-#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 1)
-#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 17, 1)
-#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 17, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 18, 1)
-#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 18, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 1)
-#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 28, 1)
-#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 28, 1, __value)
-#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 29, 1)
-#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 29, 1, __value)
-#define AOAC_GLOBAL_INFO_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define AOAC_GLOBAL_INFO_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define AOAC_GLOBAL_INFO_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define AOAC_GLOBAL_INFO_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define AOAC_RSVD_PAGE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define AOAC_RSVD_PAGE_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define AOAC_RSVD_PAGE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define AOAC_RSVD_PAGE_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
-#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
-#define AOAC_RSVD_PAGE2_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define AOAC_RSVD_PAGE2_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define AOAC_RSVD_PAGE2_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define AOAC_RSVD_PAGE2_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
-#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
-#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
-#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
-#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
-#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
-#define AOAC_RSVD_PAGE3_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
-#define AOAC_RSVD_PAGE3_SET_CMD_ID(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
-#define AOAC_RSVD_PAGE3_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
-#define AOAC_RSVD_PAGE3_SET_CLASS(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
-#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
-#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
-#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__h2c) \
- LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
-#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__h2c, __value) \
- SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef HALMAC_POWER_SEQUENCE_CMD
-#define HALMAC_POWER_SEQUENCE_CMD
-
-#include "halmac_2_platform.h"
-#include "halmac_type.h"
-
-#define HALMAC_POLLING_READY_TIMEOUT_COUNT 20000
-
-/* The value of cmd : 4 bits */
-
-/* offset : the read register offset
- * msk : the mask of the read value
- * value : N/A, left by 0
- * Note : dirver shall implement this function by read & msk
- */
-#define HALMAC_PWR_CMD_READ 0x00
-/*
- * offset: the read register offset
- * msk: the mask of the write bits
- * value: write value
- * Note: driver shall implement this cmd by read & msk after write
- */
-#define HALMAC_PWR_CMD_WRITE 0x01
-/* offset: the read register offset
- * msk: the mask of the polled value
- * value: the value to be polled, masked by the msd field.
- * Note: driver shall implement this cmd by
- * do{
- * if( (Read(offset) & msk) == (value & msk) )
- * break;
- * } while(not timeout);
- */
-#define HALMAC_PWR_CMD_POLLING 0x02
-/* offset: the value to delay
- * msk: N/A
- * value: the unit of delay, 0: us, 1: ms
- */
-#define HALMAC_PWR_CMD_DELAY 0x03
-/* offset: N/A
- * msk: N/A
- * value: N/A
- */
-#define HALMAC_PWR_CMD_END 0x04
-
-/* The value of base : 4 bits */
-
-/* define the base address of each block */
-#define HALMAC_PWR_BASEADDR_MAC 0x00
-#define HALMAC_PWR_BASEADDR_USB 0x01
-#define HALMAC_PWR_BASEADDR_PCIE 0x02
-#define HALMAC_PWR_BASEADDR_SDIO 0x03
-
-/* The value of interface_msk : 4 bits */
-#define HALMAC_PWR_INTF_SDIO_MSK BIT(0)
-#define HALMAC_PWR_INTF_USB_MSK BIT(1)
-#define HALMAC_PWR_INTF_PCI_MSK BIT(2)
-#define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-
-/* The value of fab_msk : 4 bits */
-#define HALMAC_PWR_FAB_TSMC_MSK BIT(0)
-#define HALMAC_PWR_FAB_UMC_MSK BIT(1)
-#define HALMAC_PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-
-/* The value of cut_msk : 8 bits */
-#define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0)
-#define HALMAC_PWR_CUT_A_MSK BIT(1)
-#define HALMAC_PWR_CUT_B_MSK BIT(2)
-#define HALMAC_PWR_CUT_C_MSK BIT(3)
-#define HALMAC_PWR_CUT_D_MSK BIT(4)
-#define HALMAC_PWR_CUT_E_MSK BIT(5)
-#define HALMAC_PWR_CUT_F_MSK BIT(6)
-#define HALMAC_PWR_CUT_G_MSK BIT(7)
-#define HALMAC_PWR_CUT_ALL_MSK 0xFF
-
-enum halmac_pwrseq_cmd_delay_unit_ {
- HALMAC_PWRSEQ_DELAY_US,
- HALMAC_PWRSEQ_DELAY_MS,
-};
-
-/*Don't care endian issue, because element of pwer seq vector is fixed address*/
-struct halmac_wl_pwr_cfg_ {
- u16 offset;
- u8 cut_msk;
- u8 fab_msk : 4;
- u8 interface_msk : 4;
- u8 base : 4;
- u8 cmd : 4;
- u8 msk;
- u8 value;
-};
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __HALMAC_COM_REG_H__
-#define __HALMAC_COM_REG_H__
-/*-------------------------Modification Log-----------------------------------
- * For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524
- * The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A
- * 8812A and 8188E is not included in page0 register
- *
- * For other pages, it is based on MAC_Register.doc SVN502
- * Most IC is the same with 8812A
- *-------------------------Modification Log-----------------------------------
- */
-
-/*--------------------------Include File--------------------------------------*/
-/*--------------------------Include File--------------------------------------*/
-
-#define REG_SYS_ISO_CTRL 0x0000
-
-#define REG_SDIO_TX_CTRL 0x10250000
-
-#define REG_SYS_FUNC_EN 0x0002
-#define REG_SYS_PW_CTRL 0x0004
-#define REG_SYS_CLK_CTRL 0x0008
-#define REG_SYS_EEPROM_CTRL 0x000A
-#define REG_EE_VPD 0x000C
-#define REG_SYS_SWR_CTRL1 0x0010
-#define REG_SYS_SWR_CTRL2 0x0014
-
-#define REG_SDIO_HIMR 0x10250014
-
-#define REG_SYS_SWR_CTRL3 0x0018
-
-#define REG_SDIO_HISR 0x10250018
-
-#define REG_RSV_CTRL 0x001C
-
-#define REG_SDIO_RX_REQ_LEN 0x1025001C
-
-#define REG_RF_CTRL 0x001F
-
-#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F
-
-#define REG_AFE_LDO_CTRL 0x0020
-
-#define REG_SDIO_FREE_TXPG 0x10250020
-
-#define REG_AFE_CTRL1 0x0024
-
-#define REG_SDIO_FREE_TXPG2 0x10250024
-
-#define REG_AFE_CTRL2 0x0028
-
-#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028
-
-#define REG_AFE_CTRL3 0x002C
-#define REG_EFUSE_CTRL 0x0030
-
-#define REG_SDIO_HTSFR_INFO 0x10250030
-
-#define REG_LDO_EFUSE_CTRL 0x0034
-#define REG_PWR_OPTION_CTRL 0x0038
-
-#define REG_SDIO_HCPWM1_V2 0x10250038
-#define REG_SDIO_HCPWM2_V2 0x1025003A
-
-#define REG_CAL_TIMER 0x003C
-#define REG_ACLK_MON 0x003E
-#define REG_GPIO_MUXCFG 0x0040
-
-#define REG_SDIO_INDIRECT_REG_CFG 0x10250040
-
-#define REG_GPIO_PIN_CTRL 0x0044
-
-#define REG_SDIO_INDIRECT_REG_DATA 0x10250044
-
-#define REG_GPIO_INTM 0x0048
-#define REG_LED_CFG 0x004C
-#define REG_FSIMR 0x0050
-#define REG_FSISR 0x0054
-#define REG_HSIMR 0x0058
-#define REG_HSISR 0x005C
-#define REG_GPIO_EXT_CTRL 0x0060
-
-#define REG_SDIO_H2C 0x10250060
-
-#define REG_PAD_CTRL1 0x0064
-
-#define REG_SDIO_C2H 0x10250064
-
-#define REG_WL_BT_PWR_CTRL 0x0068
-
-#define REG_SDM_DEBUG 0x006C
-
-#define REG_SYS_SDIO_CTRL 0x0070
-
-#define REG_HCI_OPT_CTRL 0x0074
-
-#define REG_AFE_CTRL4 0x0078
-
-#define REG_LDO_SWR_CTRL 0x007C
-
-#define REG_MCUFW_CTRL 0x0080
-
-#define REG_SDIO_HRPWM1 0x10250080
-#define REG_SDIO_HRPWM2 0x10250082
-
-#define REG_MCU_TST_CFG 0x0084
-
-#define REG_SDIO_HPS_CLKR 0x10250084
-#define REG_SDIO_BUS_CTRL 0x10250085
-
-#define REG_SDIO_HSUS_CTRL 0x10250086
-
-#define REG_HMEBOX_E0_E1 0x0088
-
-#define REG_SDIO_RESPONSE_TIMER 0x10250088
-
-#define REG_SDIO_CMD_CRC 0x1025008A
-
-#define REG_HMEBOX_E2_E3 0x008C
-#define REG_WLLPS_CTRL 0x0090
-
-#define REG_SDIO_HSISR 0x10250090
-#define REG_SDIO_HSIMR 0x10250091
-
-#define REG_AFE_CTRL5 0x0094
-
-#define REG_GPIO_DEBOUNCE_CTRL 0x0098
-#define REG_RPWM2 0x009C
-#define REG_SYSON_FSM_MON 0x00A0
-
-#define REG_AFE_CTRL6 0x00A4
-
-#define REG_PMC_DBG_CTRL1 0x00A8
-
-#define REG_AFE_CTRL7 0x00AC
-
-#define REG_HIMR0 0x00B0
-#define REG_HISR0 0x00B4
-#define REG_HIMR1 0x00B8
-#define REG_HISR1 0x00BC
-#define REG_DBG_PORT_SEL 0x00C0
-
-#define REG_SDIO_ERR_RPT 0x102500C0
-#define REG_SDIO_CMD_ERRCNT 0x102500C1
-#define REG_SDIO_DATA_ERRCNT 0x102500C2
-
-#define REG_PAD_CTRL2 0x00C4
-
-#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4
-
-#define REG_SDIO_CRC_ERR_IDX 0x102500C9
-#define REG_SDIO_DATA_CRC 0x102500CA
-#define REG_SDIO_DATA_REPLY_TIME 0x102500CB
-
-#define REG_PMC_DBG_CTRL2 0x00CC
-#define REG_BIST_CTRL 0x00D0
-#define REG_BIST_RPT 0x00D4
-#define REG_MEM_CTRL 0x00D8
-
-#define REG_AFE_CTRL8 0x00DC
-
-#define REG_USB_SIE_INTF 0x00E0
-#define REG_PCIE_MIO_INTF 0x00E4
-#define REG_PCIE_MIO_INTD 0x00E8
-
-#define REG_WLRF1 0x00EC
-
-#define REG_SYS_CFG1 0x00F0
-#define REG_SYS_STATUS1 0x00F4
-#define REG_SYS_STATUS2 0x00F8
-#define REG_SYS_CFG2 0x00FC
-#define REG_CR 0x0100
-
-#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
-
-#define REG_TSF_CLK_STATE 0x0108
-#define REG_TXDMA_PQ_MAP 0x010C
-#define REG_TRXFF_BNDY 0x0114
-
-#define REG_PTA_I2C_MBOX 0x0118
-
-#define REG_RXFF_BNDY 0x011C
-
-#define REG_FE1IMR 0x0120
-
-#define REG_FE1ISR 0x0124
-
-#define REG_CPWM 0x012C
-#define REG_FWIMR 0x0130
-#define REG_FWISR 0x0134
-#define REG_FTIMR 0x0138
-#define REG_FTISR 0x013C
-#define REG_PKTBUF_DBG_CTRL 0x0140
-#define REG_PKTBUF_DBG_DATA_L 0x0144
-#define REG_PKTBUF_DBG_DATA_H 0x0148
-#define REG_CPWM2 0x014C
-#define REG_TC0_CTRL 0x0150
-#define REG_TC1_CTRL 0x0154
-#define REG_TC2_CTRL 0x0158
-#define REG_TC3_CTRL 0x015C
-#define REG_TC4_CTRL 0x0160
-#define REG_TCUNIT_BASE 0x0164
-#define REG_TC5_CTRL 0x0168
-#define REG_TC6_CTRL 0x016C
-#define REG_MBIST_FAIL 0x0170
-#define REG_MBIST_START_PAUSE 0x0174
-#define REG_MBIST_DONE 0x0178
-
-#define REG_MBIST_FAIL_NRML 0x017C
-
-#define REG_AES_DECRPT_DATA 0x0180
-#define REG_AES_DECRPT_CFG 0x0184
-
-#define REG_TMETER 0x0190
-#define REG_OSC_32K_CTRL 0x0194
-#define REG_32K_CAL_REG1 0x0198
-#define REG_C2HEVT 0x01A0
-
-#define REG_C2HEVT_1 0x01A4
-#define REG_C2HEVT_2 0x01A8
-#define REG_C2HEVT_3 0x01AC
-
-#define REG_SW_DEFINED_PAGE1 0x01B8
-
-#define REG_MCUTST_I 0x01C0
-#define REG_MCUTST_II 0x01C4
-#define REG_FMETHR 0x01C8
-#define REG_HMETFR 0x01CC
-#define REG_HMEBOX0 0x01D0
-#define REG_HMEBOX1 0x01D4
-#define REG_HMEBOX2 0x01D8
-#define REG_HMEBOX3 0x01DC
-#define REG_LLT_INIT 0x01E0
-
-#define REG_LLT_INIT_ADDR 0x01E4
-
-#define REG_BB_ACCESS_CTRL 0x01E8
-#define REG_BB_ACCESS_DATA 0x01EC
-#define REG_HMEBOX_E0 0x01F0
-#define REG_HMEBOX_E1 0x01F4
-#define REG_HMEBOX_E2 0x01F8
-#define REG_HMEBOX_E3 0x01FC
-
-#define REG_FIFOPAGE_CTRL_1 0x0200
-
-#define REG_FIFOPAGE_CTRL_2 0x0204
-
-#define REG_AUTO_LLT_V1 0x0208
-
-#define REG_TXDMA_OFFSET_CHK 0x020C
-#define REG_TXDMA_STATUS 0x0210
-
-#define REG_TX_DMA_DBG 0x0214
-
-#define REG_TQPNT1 0x0218
-#define REG_TQPNT2 0x021C
-
-#define REG_TQPNT3 0x0220
-
-#define REG_TQPNT4 0x0224
-
-#define REG_RQPN_CTRL_1 0x0228
-#define REG_RQPN_CTRL_2 0x022C
-#define REG_FIFOPAGE_INFO_1 0x0230
-#define REG_FIFOPAGE_INFO_2 0x0234
-#define REG_FIFOPAGE_INFO_3 0x0238
-#define REG_FIFOPAGE_INFO_4 0x023C
-#define REG_FIFOPAGE_INFO_5 0x0240
-
-#define REG_H2C_HEAD 0x0244
-#define REG_H2C_TAIL 0x0248
-#define REG_H2C_READ_ADDR 0x024C
-#define REG_H2C_WR_ADDR 0x0250
-#define REG_H2C_INFO 0x0254
-
-#define REG_RXDMA_AGG_PG_TH 0x0280
-#define REG_RXPKT_NUM 0x0284
-#define REG_RXDMA_STATUS 0x0288
-#define REG_RXDMA_DPR 0x028C
-#define REG_RXDMA_MODE 0x0290
-#define REG_C2H_PKT 0x0294
-
-#define REG_FWFF_C2H 0x0298
-#define REG_FWFF_CTRL 0x029C
-#define REG_FWFF_PKT_INFO 0x02A0
-
-#define REG_PCIE_CTRL 0x0300
-
-#define REG_INT_MIG 0x0304
-#define REG_BCNQ_TXBD_DESA 0x0308
-#define REG_MGQ_TXBD_DESA 0x0310
-#define REG_VOQ_TXBD_DESA 0x0318
-#define REG_VIQ_TXBD_DESA 0x0320
-#define REG_BEQ_TXBD_DESA 0x0328
-#define REG_BKQ_TXBD_DESA 0x0330
-#define REG_RXQ_RXBD_DESA 0x0338
-#define REG_HI0Q_TXBD_DESA 0x0340
-#define REG_HI1Q_TXBD_DESA 0x0348
-#define REG_HI2Q_TXBD_DESA 0x0350
-#define REG_HI3Q_TXBD_DESA 0x0358
-#define REG_HI4Q_TXBD_DESA 0x0360
-#define REG_HI5Q_TXBD_DESA 0x0368
-#define REG_HI6Q_TXBD_DESA 0x0370
-#define REG_HI7Q_TXBD_DESA 0x0378
-#define REG_MGQ_TXBD_NUM 0x0380
-#define REG_RX_RXBD_NUM 0x0382
-#define REG_VOQ_TXBD_NUM 0x0384
-#define REG_VIQ_TXBD_NUM 0x0386
-#define REG_BEQ_TXBD_NUM 0x0388
-#define REG_BKQ_TXBD_NUM 0x038A
-#define REG_HI0Q_TXBD_NUM 0x038C
-#define REG_HI1Q_TXBD_NUM 0x038E
-#define REG_HI2Q_TXBD_NUM 0x0390
-#define REG_HI3Q_TXBD_NUM 0x0392
-#define REG_HI4Q_TXBD_NUM 0x0394
-#define REG_HI5Q_TXBD_NUM 0x0396
-#define REG_HI6Q_TXBD_NUM 0x0398
-#define REG_HI7Q_TXBD_NUM 0x039A
-#define REG_TSFTIMER_HCI 0x039C
-#define REG_BD_RWPTR_CLR 0x039C
-#define REG_VOQ_TXBD_IDX 0x03A0
-#define REG_VIQ_TXBD_IDX 0x03A4
-#define REG_BEQ_TXBD_IDX 0x03A8
-#define REG_BKQ_TXBD_IDX 0x03AC
-#define REG_MGQ_TXBD_IDX 0x03B0
-#define REG_RXQ_RXBD_IDX 0x03B4
-#define REG_HI0Q_TXBD_IDX 0x03B8
-#define REG_HI1Q_TXBD_IDX 0x03BC
-#define REG_HI2Q_TXBD_IDX 0x03C0
-#define REG_HI3Q_TXBD_IDX 0x03C4
-#define REG_HI4Q_TXBD_IDX 0x03C8
-#define REG_HI5Q_TXBD_IDX 0x03CC
-#define REG_HI6Q_TXBD_IDX 0x03D0
-#define REG_HI7Q_TXBD_IDX 0x03D4
-
-#define REG_DBG_SEL_V1 0x03D8
-
-#define REG_PCIE_HRPWM1_V1 0x03D9
-
-#define REG_PCIE_HCPWM1_V1 0x03DA
-
-#define REG_PCIE_CTRL2 0x03DB
-
-#define REG_PCIE_HRPWM2_V1 0x03DC
-
-#define REG_PCIE_HCPWM2_V1 0x03DE
-
-#define REG_PCIE_H2C_MSG_V1 0x03E0
-
-#define REG_PCIE_C2H_MSG_V1 0x03E4
-
-#define REG_DBI_WDATA_V1 0x03E8
-
-#define REG_DBI_RDATA_V1 0x03EC
-
-#define REG_DBI_FLAG_V1 0x03F0
-
-#define REG_MDIO_V1 0x03F4
-
-#define REG_PCIE_MIX_CFG 0x03F8
-
-#define REG_HCI_MIX_CFG 0x03FC
-
-#define REG_Q0_INFO 0x0400
-#define REG_Q1_INFO 0x0404
-#define REG_Q2_INFO 0x0408
-#define REG_Q3_INFO 0x040C
-#define REG_MGQ_INFO 0x0410
-#define REG_HIQ_INFO 0x0414
-#define REG_BCNQ_INFO 0x0418
-#define REG_TXPKT_EMPTY 0x041A
-#define REG_CPU_MGQ_INFO 0x041C
-#define REG_FWHW_TXQ_CTRL 0x0420
-
-#define REG_DATAFB_SEL 0x0423
-
-#define REG_BCNQ_BDNY_V1 0x0424
-
-#define REG_LIFETIME_EN 0x0426
-
-#define REG_SPEC_SIFS 0x0428
-#define REG_RETRY_LIMIT 0x042A
-#define REG_TXBF_CTRL 0x042C
-#define REG_DARFRC 0x0430
-#define REG_RARFRC 0x0438
-#define REG_RRSR 0x0440
-#define REG_ARFR0 0x0444
-#define REG_ARFR1_V1 0x044C
-#define REG_CCK_CHECK 0x0454
-
-#define REG_AMPDU_MAX_TIME_V1 0x0455
-
-#define REG_BCNQ1_BDNY_V1 0x0456
-
-#define REG_AMPDU_MAX_LENGTH 0x0458
-#define REG_ACQ_STOP 0x045C
-
-#define REG_NDPA_RATE 0x045D
-
-#define REG_TX_HANG_CTRL 0x045E
-#define REG_NDPA_OPT_CTRL 0x045F
-
-#define REG_RD_RESP_PKT_TH 0x0463
-#define REG_CMDQ_INFO 0x0464
-#define REG_Q4_INFO 0x0468
-#define REG_Q5_INFO 0x046C
-#define REG_Q6_INFO 0x0470
-#define REG_Q7_INFO 0x0474
-
-#define REG_WMAC_LBK_BUF_HD_V1 0x0478
-#define REG_MGQ_BDNY_V1 0x047A
-
-#define REG_TXRPT_CTRL 0x047C
-#define REG_INIRTS_RATE_SEL 0x0480
-#define REG_BASIC_CFEND_RATE 0x0481
-#define REG_STBC_CFEND_RATE 0x0482
-#define REG_DATA_SC 0x0483
-#define REG_MACID_SLEEP3 0x0484
-#define REG_MACID_SLEEP1 0x0488
-#define REG_ARFR2_V1 0x048C
-#define REG_ARFR3_V1 0x0494
-#define REG_ARFR4 0x049C
-#define REG_ARFR5 0x04A4
-#define REG_TXRPT_START_OFFSET 0x04AC
-
-#define REG_POWER_STAGE1 0x04B4
-
-#define REG_POWER_STAGE2 0x04B8
-
-#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
-#define REG_PKT_LIFE_TIME 0x04C0
-#define REG_STBC_SETTING 0x04C4
-#define REG_STBC_SETTING2 0x04C5
-#define REG_QUEUE_CTRL 0x04C6
-#define REG_SINGLE_AMPDU_CTRL 0x04C7
-#define REG_PROT_MODE_CTRL 0x04C8
-#define REG_BAR_MODE_CTRL 0x04CC
-#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
-#define REG_MACID_SLEEP2 0x04D0
-#define REG_MACID_SLEEP 0x04D4
-
-#define REG_HW_SEQ0 0x04D8
-#define REG_HW_SEQ1 0x04DA
-#define REG_HW_SEQ2 0x04DC
-#define REG_HW_SEQ3 0x04DE
-
-#define REG_NULL_PKT_STATUS_V1 0x04E0
-
-#define REG_PTCL_ERR_STATUS 0x04E2
-
-#define REG_NULL_PKT_STATUS_EXTEND 0x04E3
-
-#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4
-
-#define REG_BT_POLLUTE_PKT_CNT 0x04E8
-#define REG_PTCL_DBG 0x04EC
-
-#define REG_CPUMGQ_TIMER_CTRL2 0x04F4
-
-#define REG_DUMMY_PAGE4_V1 0x04FC
-#define REG_MOREDATA 0x04FE
-
-#define REG_EDCA_VO_PARAM 0x0500
-#define REG_EDCA_VI_PARAM 0x0504
-#define REG_EDCA_BE_PARAM 0x0508
-#define REG_EDCA_BK_PARAM 0x050C
-#define REG_BCNTCFG 0x0510
-#define REG_PIFS 0x0512
-#define REG_RDG_PIFS 0x0513
-#define REG_SIFS 0x0514
-#define REG_TSFTR_SYN_OFFSET 0x0518
-#define REG_AGGR_BREAK_TIME 0x051A
-#define REG_SLOT 0x051B
-#define REG_TX_PTCL_CTRL 0x0520
-#define REG_TXPAUSE 0x0522
-#define REG_DIS_TXREQ_CLR 0x0523
-#define REG_RD_CTRL 0x0524
-#define REG_MBSSID_CTRL 0x0526
-#define REG_P2PPS_CTRL 0x0527
-#define REG_PKT_LIFETIME_CTRL 0x0528
-#define REG_P2PPS_SPEC_STATE 0x052B
-
-#define REG_BAR_TX_CTRL 0x0530
-
-#define REG_QUEUE_INCOL_THR 0x0538
-#define REG_QUEUE_INCOL_EN 0x053C
-
-#define REG_TBTT_PROHIBIT 0x0540
-#define REG_P2PPS_STATE 0x0543
-#define REG_RD_NAV_NXT 0x0544
-#define REG_NAV_PROT_LEN 0x0546
-
-#define REG_BCN_CTRL 0x0550
-
-#define REG_BCN_CTRL_CLINT0 0x0551
-
-#define REG_MBID_NUM 0x0552
-#define REG_DUAL_TSF_RST 0x0553
-#define REG_MBSSID_BCN_SPACE 0x0554
-#define REG_DRVERLYINT 0x0558
-#define REG_BCNDMATIM 0x0559
-#define REG_ATIMWND 0x055A
-#define REG_USTIME_TSF 0x055C
-#define REG_BCN_MAX_ERR 0x055D
-#define REG_RXTSF_OFFSET_CCK 0x055E
-#define REG_RXTSF_OFFSET_OFDM 0x055F
-#define REG_TSFTR 0x0560
-
-#define REG_FREERUN_CNT 0x0568
-
-#define REG_ATIMWND1_V1 0x0570
-
-#define REG_TBTT_PROHIBIT_INFRA 0x0571
-
-#define REG_CTWND 0x0572
-#define REG_BCNIVLCUNT 0x0573
-#define REG_BCNDROPCTRL 0x0574
-#define REG_HGQ_TIMEOUT_PERIOD 0x0575
-
-#define REG_TXCMD_TIMEOUT_PERIOD 0x0576
-#define REG_MISC_CTRL 0x0577
-#define REG_BCN_CTRL_CLINT1 0x0578
-#define REG_BCN_CTRL_CLINT2 0x0579
-#define REG_BCN_CTRL_CLINT3 0x057A
-
-#define REG_EXTEND_CTRL 0x057B
-
-#define REG_P2PPS1_SPEC_STATE 0x057C
-#define REG_P2PPS1_STATE 0x057D
-#define REG_P2PPS2_SPEC_STATE 0x057E
-#define REG_P2PPS2_STATE 0x057F
-
-#define REG_PS_TIMER0 0x0580
-
-#define REG_PS_TIMER1 0x0584
-
-#define REG_PS_TIMER2 0x0588
-
-#define REG_TBTT_CTN_AREA 0x058C
-#define REG_FORCE_BCN_IFS 0x058E
-#define REG_TXOP_MIN 0x0590
-#define REG_PRE_BKF_TIME 0x0592
-#define REG_CROSS_TXOP_CTRL 0x0593
-
-#define REG_ATIMWND2 0x05A0
-#define REG_ATIMWND3 0x05A1
-#define REG_ATIMWND4 0x05A2
-#define REG_ATIMWND5 0x05A3
-#define REG_ATIMWND6 0x05A4
-#define REG_ATIMWND7 0x05A5
-#define REG_ATIMUGT 0x05A6
-#define REG_HIQ_NO_LMT_EN 0x05A7
-#define REG_DTIM_COUNTER_ROOT 0x05A8
-#define REG_DTIM_COUNTER_VAP1 0x05A9
-#define REG_DTIM_COUNTER_VAP2 0x05AA
-#define REG_DTIM_COUNTER_VAP3 0x05AB
-#define REG_DTIM_COUNTER_VAP4 0x05AC
-#define REG_DTIM_COUNTER_VAP5 0x05AD
-#define REG_DTIM_COUNTER_VAP6 0x05AE
-#define REG_DTIM_COUNTER_VAP7 0x05AF
-#define REG_DIS_ATIM 0x05B0
-
-#define REG_EARLY_128US 0x05B1
-#define REG_P2PPS1_CTRL 0x05B2
-#define REG_P2PPS2_CTRL 0x05B3
-#define REG_TIMER0_SRC_SEL 0x05B4
-#define REG_NOA_UNIT_SEL 0x05B5
-#define REG_P2POFF_DIS_TXTIME 0x05B7
-#define REG_MBSSID_BCN_SPACE2 0x05B8
-#define REG_MBSSID_BCN_SPACE3 0x05BC
-
-#define REG_ACMHWCTRL 0x05C0
-#define REG_ACMRSTCTRL 0x05C1
-#define REG_ACMAVG 0x05C2
-#define REG_VO_ADMTIME 0x05C4
-#define REG_VI_ADMTIME 0x05C6
-#define REG_BE_ADMTIME 0x05C8
-#define REG_EDCA_RANDOM_GEN 0x05CC
-#define REG_TXCMD_NOA_SEL 0x05CF
-#define REG_NOA_PARAM 0x05E0
-
-#define REG_P2P_RST 0x05F0
-#define REG_SCHEDULER_RST 0x05F1
-
-#define REG_SCH_TXCMD 0x05F8
-#define REG_PAGE5_DUMMY 0x05FC
-#define REG_WMAC_CR 0x0600
-
-#define REG_WMAC_FWPKT_CR 0x0601
-
-#define REG_BWOPMODE 0x0603
-
-#define REG_TCR 0x0604
-#define REG_RCR 0x0608
-#define REG_RX_PKT_LIMIT 0x060C
-#define REG_RX_DLK_TIME 0x060D
-#define REG_RX_DRVINFO_SZ 0x060F
-#define REG_MACID 0x0610
-#define REG_BSSID 0x0618
-#define REG_MAR 0x0620
-#define REG_MBIDCAMCFG_1 0x0628
-#define REG_MBIDCAMCFG_2 0x062C
-
-#define REG_WMAC_TCR_TSFT_OFS 0x0630
-#define REG_UDF_THSD 0x0632
-#define REG_ZLD_NUM 0x0633
-
-#define REG_STMP_THSD 0x0634
-#define REG_WMAC_TXTIMEOUT 0x0635
-#define REG_MCU_TEST_2_V1 0x0636
-
-#define REG_USTIME_EDCA 0x0638
-
-#define REG_MAC_SPEC_SIFS 0x063A
-#define REG_RESP_SIFS_CCK 0x063C
-#define REG_RESP_SIFS_OFDM 0x063E
-#define REG_ACKTO 0x0640
-#define REG_CTS2TO 0x0641
-#define REG_EIFS 0x0642
-
-#define REG_NAV_CTRL 0x0650
-#define REG_BACAMCMD 0x0654
-#define REG_BACAMCONTENT 0x0658
-#define REG_LBDLY 0x0660
-
-#define REG_WMAC_BACAM_RPMEN 0x0661
-
-#define REG_TX_RX 0x0662
-
-#define REG_WMAC_BITMAP_CTL 0x0663
-
-#define REG_RXERR_RPT 0x0664
-#define REG_WMAC_TRXPTCL_CTL 0x0668
-#define REG_CAMCMD 0x0670
-#define REG_CAMWRITE 0x0674
-#define REG_CAMREAD 0x0678
-#define REG_CAMDBG 0x067C
-#define REG_SECCFG 0x0680
-
-#define REG_RXFILTER_CATEGORY_1 0x0682
-#define REG_RXFILTER_ACTION_1 0x0683
-#define REG_RXFILTER_CATEGORY_2 0x0684
-#define REG_RXFILTER_ACTION_2 0x0685
-#define REG_RXFILTER_CATEGORY_3 0x0686
-#define REG_RXFILTER_ACTION_3 0x0687
-#define REG_RXFLTMAP3 0x0688
-#define REG_RXFLTMAP4 0x068A
-#define REG_RXFLTMAP5 0x068C
-#define REG_RXFLTMAP6 0x068E
-
-#define REG_WOW_CTRL 0x0690
-
-#define REG_NAN_RX_TSF_FILTER 0x0691
-
-#define REG_PS_RX_INFO 0x0692
-#define REG_WMMPS_UAPSD_TID 0x0693
-#define REG_LPNAV_CTRL 0x0694
-
-#define REG_WKFMCAM_CMD 0x0698
-#define REG_WKFMCAM_RWD 0x069C
-
-#define REG_RXFLTMAP0 0x06A0
-#define REG_RXFLTMAP1 0x06A2
-#define REG_RXFLTMAP 0x06A4
-#define REG_BCN_PSR_RPT 0x06A8
-
-#define REG_FLC_RPC 0x06AC
-#define REG_FLC_RPCT 0x06AD
-#define REG_FLC_PTS 0x06AE
-#define REG_FLC_TRPC 0x06AF
-
-#define REG_RXPKTMON_CTRL 0x06B0
-
-#define REG_STATE_MON 0x06B4
-
-#define REG_ERROR_MON 0x06B8
-#define REG_SEARCH_MACID 0x06BC
-
-#define REG_BT_COEX_TABLE 0x06C0
-
-#define REG_RXCMD_0 0x06D0
-#define REG_RXCMD_1 0x06D4
-
-#define REG_WMAC_RESP_TXINFO 0x06D8
-
-#define REG_BBPSF_CTRL 0x06DC
-
-#define REG_P2P_RX_BCN_NOA 0x06E0
-#define REG_ASSOCIATED_BFMER0_INFO 0x06E4
-#define REG_ASSOCIATED_BFMER1_INFO 0x06EC
-#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4
-#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8
-#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC
-#define REG_MACID1 0x0700
-
-#define REG_BSSID1 0x0708
-
-#define REG_BCN_PSR_RPT1 0x0710
-#define REG_ASSOCIATED_BFMEE_SEL 0x0714
-#define REG_SND_PTCL_CTRL 0x0718
-#define REG_RX_CSI_RPT_INFO 0x071C
-#define REG_NS_ARP_CTRL 0x0720
-#define REG_NS_ARP_INFO 0x0724
-
-#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728
-
-#define REG_BEAMFORMING_INFO_NSARP 0x072C
-
-#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750
-
-#define REG_WMAC_SWAES_CFG 0x0760
-
-#define REG_BT_COEX_V2 0x0762
-
-#define REG_BT_COEX 0x0764
-
-#define REG_WLAN_ACT_MASK_CTRL 0x0768
-
-#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E
-
-#define REG_BT_ACT_STATISTICS 0x0770
-
-#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778
-
-#define REG_BT_STATUS_REPORT_REGISTER 0x077C
-
-#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780
-
-#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784
-
-#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785
-
-#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F
-
-#define REG_BT_TDMA_TIME_REGISTER 0x0790
-
-#define REG_BT_ACT_REGISTER 0x0794
-
-#define REG_OBFF_CTRL_BASIC 0x0798
-
-#define REG_OBFF_CTRL2_TIMER 0x079C
-
-#define REG_LTR_CTRL_BASIC 0x07A0
-
-#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4
-
-#define REG_LTR_IDLE_LATENCY_V1 0x07A8
-#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC
-
-#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0
-
-#define REG_WMAC_PKTCNT_RWD 0x07B8
-#define REG_WMAC_PKTCNT_CTRL 0x07BC
-
-#define REG_IQ_DUMP 0x07C0
-
-#define REG_WMAC_FTM_CTL 0x07CC
-
-#define REG_WMAC_IQ_MDPK_FUNC 0x07CE
-
-#define REG_WMAC_OPTION_FUNCTION 0x07D0
-
-#define REG_RX_FILTER_FUNCTION 0x07DA
-
-#define REG_NDP_SIG 0x07E0
-#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4
-
-#define REG_RTS_ADDRESS_0 0x07F0
-
-#define REG_RTS_ADDRESS_1 0x07F8
-
-#define REG__RPFM_MAP1 0x07FE
-
-#define REG_SYS_CFG3 0x1000
-#define REG_SYS_CFG4 0x1034
-
-#define REG_SYS_CFG5 0x1070
-
-#define REG_CPU_DMEM_CON 0x1080
-
-#define REG_BOOT_REASON 0x1088
-#define REG_NFCPAD_CTRL 0x10A8
-
-#define REG_HIMR2 0x10B0
-#define REG_HISR2 0x10B4
-#define REG_HIMR3 0x10B8
-#define REG_HISR3 0x10BC
-#define REG_SW_MDIO 0x10C0
-#define REG_SW_FLUSH 0x10C4
-
-#define REG_H2C_PKT_READADDR 0x10D0
-#define REG_H2C_PKT_WRITEADDR 0x10D4
-
-#define REG_MEM_PWR_CRTL 0x10D8
-
-#define REG_FW_DBG0 0x10E0
-#define REG_FW_DBG1 0x10E4
-#define REG_FW_DBG2 0x10E8
-#define REG_FW_DBG3 0x10EC
-#define REG_FW_DBG4 0x10F0
-#define REG_FW_DBG5 0x10F4
-#define REG_FW_DBG6 0x10F8
-#define REG_FW_DBG7 0x10FC
-#define REG_CR_EXT 0x1100
-#define REG_FWFF 0x1114
-
-#define REG_RXFF_PTR_V1 0x1118
-#define REG_RXFF_WTR_V1 0x111C
-
-#define REG_FE2IMR 0x1120
-#define REG_FE2ISR 0x1124
-#define REG_FE3IMR 0x1128
-#define REG_FE3ISR 0x112C
-#define REG_FE4IMR 0x1130
-#define REG_FE4ISR 0x1134
-#define REG_FT1IMR 0x1138
-#define REG_FT1ISR 0x113C
-#define REG_SPWR0 0x1140
-#define REG_SPWR1 0x1144
-#define REG_SPWR2 0x1148
-#define REG_SPWR3 0x114C
-#define REG_POWSEQ 0x1150
-
-#define REG_TC7_CTRL_V1 0x1158
-#define REG_TC8_CTRL_V1 0x115C
-
-#define REG_FT2IMR 0x11E0
-#define REG_FT2ISR 0x11E4
-
-#define REG_MSG2 0x11F0
-#define REG_MSG3 0x11F4
-#define REG_MSG4 0x11F8
-#define REG_MSG5 0x11FC
-#define REG_DDMA_CH0SA 0x1200
-#define REG_DDMA_CH0DA 0x1204
-#define REG_DDMA_CH0CTRL 0x1208
-#define REG_DDMA_CH1SA 0x1210
-#define REG_DDMA_CH1DA 0x1214
-#define REG_DDMA_CH1CTRL 0x1218
-#define REG_DDMA_CH2SA 0x1220
-#define REG_DDMA_CH2DA 0x1224
-#define REG_DDMA_CH2CTRL 0x1228
-#define REG_DDMA_CH3SA 0x1230
-#define REG_DDMA_CH3DA 0x1234
-#define REG_DDMA_CH3CTRL 0x1238
-#define REG_DDMA_CH4SA 0x1240
-#define REG_DDMA_CH4DA 0x1244
-#define REG_DDMA_CH4CTRL 0x1248
-#define REG_DDMA_CH5SA 0x1250
-#define REG_DDMA_CH5DA 0x1254
-
-#define REG_REG_DDMA_CH5CTRL 0x1258
-
-#define REG_DDMA_INT_MSK 0x12E0
-#define REG_DDMA_CHSTATUS 0x12E8
-#define REG_DDMA_CHKSUM 0x12F0
-#define REG_DDMA_MONITOR 0x12FC
-
-#define REG_STC_INT_CS 0x1300
-#define REG_ST_INT_CFG 0x1304
-#define REG_CMU_DLY_CTRL 0x1310
-#define REG_CMU_DLY_CFG 0x1314
-#define REG_H2CQ_TXBD_DESA 0x1320
-#define REG_H2CQ_TXBD_NUM 0x1328
-#define REG_H2CQ_TXBD_IDX 0x132C
-#define REG_H2CQ_CSR 0x1330
-
-#define REG_CHANGE_PCIE_SPEED 0x1350
-
-#define REG_OLD_DEHANG 0x13F4
-
-#define REG_Q0_Q1_INFO 0x1400
-#define REG_Q2_Q3_INFO 0x1404
-#define REG_Q4_Q5_INFO 0x1408
-#define REG_Q6_Q7_INFO 0x140C
-#define REG_MGQ_HIQ_INFO 0x1410
-#define REG_CMDQ_BCNQ_INFO 0x1414
-#define REG_USEREG_SETTING 0x1420
-#define REG_AESIV_SETTING 0x1424
-#define REG_BF0_TIME_SETTING 0x1428
-#define REG_BF1_TIME_SETTING 0x142C
-#define REG_BF_TIMEOUT_EN 0x1430
-#define REG_MACID_RELEASE0 0x1434
-#define REG_MACID_RELEASE1 0x1438
-#define REG_MACID_RELEASE2 0x143C
-#define REG_MACID_RELEASE3 0x1440
-#define REG_MACID_RELEASE_SETTING 0x1444
-#define REG_FAST_EDCA_VOVI_SETTING 0x1448
-#define REG_FAST_EDCA_BEBK_SETTING 0x144C
-#define REG_MACID_DROP0 0x1450
-#define REG_MACID_DROP1 0x1454
-#define REG_MACID_DROP2 0x1458
-#define REG_MACID_DROP3 0x145C
-
-#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460
-#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464
-#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468
-#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C
-#define REG_MGG_FIFO_CRTL 0x1470
-#define REG_MGG_FIFO_INT 0x1474
-#define REG_MGG_FIFO_LIFETIME 0x1478
-#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C
-
-#define REG_MACID_SHCUT_OFFSET 0x1480
-
-#define REG_MU_TX_CTL 0x14C0
-#define REG_MU_STA_GID_VLD 0x14C4
-#define REG_MU_STA_USER_POS_INFO 0x14C8
-#define REG_MU_TRX_DBG_CNT 0x14D0
-
-#define REG_CPUMGQ_TX_TIMER 0x1500
-#define REG_PS_TIMER_A 0x1504
-#define REG_PS_TIMER_B 0x1508
-#define REG_PS_TIMER_C 0x150C
-#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510
-#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514
-#define REG_PS_TIMER_A_EARLY 0x1515
-#define REG_PS_TIMER_B_EARLY 0x1516
-#define REG_PS_TIMER_C_EARLY 0x1517
-
-#define REG_BCN_PSR_RPT2 0x1600
-#define REG_BCN_PSR_RPT3 0x1604
-#define REG_BCN_PSR_RPT4 0x1608
-#define REG_A1_ADDR_MASK 0x160C
-#define REG_MACID2 0x1620
-#define REG_BSSID2 0x1628
-#define REG_MACID3 0x1630
-#define REG_BSSID3 0x1638
-#define REG_MACID4 0x1640
-#define REG_BSSID4 0x1648
-
-#define REG_NOA_REPORT 0x1650
-#define REG_PWRBIT_SETTING 0x1660
-#define REG_WMAC_MU_BF_OPTION 0x167C
-
-#define REG_WMAC_MU_ARB 0x167E
-#define REG_WMAC_MU_OPTION 0x167F
-#define REG_WMAC_MU_BF_CTL 0x1680
-
-#define REG_WMAC_MU_BFRPT_PARA 0x1682
-
-#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684
-#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686
-#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688
-#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A
-#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C
-#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E
-
-#define REG_TRANSMIT_ADDRSS_0 0x16A0
-#define REG_TRANSMIT_ADDRSS_1 0x16A8
-#define REG_TRANSMIT_ADDRSS_2 0x16B0
-#define REG_TRANSMIT_ADDRSS_3 0x16B8
-#define REG_TRANSMIT_ADDRSS_4 0x16C0
-
-#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
-#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
-#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
-
-/* ----------------------------------------------------- */
-/* */
-/* 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress */
-/* */
-/* ----------------------------------------------------- */
-#define REG_RXPKTBUF_STARTADDR 0xFB00
-#define REG_TXPKTBUF_STARTADDR 0xFC00
-
-/* ----------------------------------------------------- */
-/* */
-/* 0xFD00h ~ 0xFDFFh 8051 CPU Local REG */
-/* */
-/* ----------------------------------------------------- */
-#define REG_SYS_CTRL 0xFD00
-#define REG_PONSTS_RPT1 0xFD01
-#define REG_PONSTS_RPT2 0xFD02
-#define REG_PONSTS_RPT3 0xFD03
-#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */
-#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */
-#define REG_8051ERRFLAG 0xFD08
-#define REG_8051ERRFLAG_MASK 0xFD09
-#define REG_TXADDRH 0xFD10 /* Tx Packet High address */
-#define REG_RXADDRH 0xFD11 /* Rx Packet High address */
-#define REG_TXADDRH_EXT 0xFD12 /* 0xFD12[0] : for 8051 access txpktbuf
- * high64k as external register
- */
-
-#define REG_U3_STATE 0xFD48 /* (Read only)
- * [7:4] : usb3 changed last state.
- * [3:0] : usb3 state
- */
-
-/* for MAILBOX */
-#define REG_OUTDATA0 0xFD50
-#define REG_OUTDATA1 0xFD54
-#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady,
- * bit[1] : OutEmptyIntEn
- */
-
-#define REG_INDATA0 0xFD60
-#define REG_INDATA1 0xFD64
-#define REG_INRDY 0xFD68 /* bit[0] : InReady,
- * bit[1] : InRdyIntEn
- */
-
-/* MCU ERROR debug REG */
-#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */
-#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */
-#define REG_MCUERR_ACC 0xFD92
-#define REG_MCUERR_B 0xFD93
-#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */
-#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */
-#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */
-#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */
-#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */
-#define REG_VERA_SIM 0xFD9F
-/* 0xFD99~0xFD9F are reserved.. */
-
-/* ----------------------------------------------------- */
-/* */
-/* 0xFE00h ~ 0xFEFFh USB Configuration */
-/* */
-/* ----------------------------------------------------- */
-
-/* RTS5101 USB Register Definition */
-#define REG_USB_SETUP_DEC_INT 0xFE00
-#define REG_USB_DMACTL 0xFE01
-#define REG_USB_IRQSTAT0 0xFE02
-#define REG_USB_IRQSTAT1 0xFE03
-#define REG_USB_IRQEN0 0xFE04
-#define REG_USB_IRQEN1 0xFE05
-#define REG_USB_AUTOPTRL 0xFE06
-#define REG_USB_AUTOPTRH 0xFE07
-#define REG_USB_AUTODAT 0xFE08
-
-#define REG_USB_SCRATCH0 0xFE09
-#define REG_USB_SCRATCH1 0xFE0A
-#define REG_USB_SEEPROM 0xFE0B
-#define REG_USB_GPIO0 0xFE0C
-#define REG_USB_GPIO0DIR 0xFE0D
-#define REG_USB_CLKSEL 0xFE0E
-#define REG_USB_BOOTCTL 0xFE0F
-
-#define REG_USB_USBCTL 0xFE10
-#define REG_USB_USBSTAT 0xFE11
-#define REG_USB_DEVADDR 0xFE12
-#define REG_USB_USBTEST 0xFE13
-#define REG_USB_FNUM0 0xFE14
-#define REG_USB_FNUM1 0xFE15
-
-#define REG_USB_EP_IDX 0xFE20
-#define REG_USB_EP_CFG 0xFE21
-#define REG_USB_EP_CTL 0xFE22
-#define REG_USB_EP_STAT 0xFE23
-#define REG_USB_EP_IRQ 0xFE24
-#define REG_USB_EP_IRQEN 0xFE25
-#define REG_USB_EP_MAXPKT0 0xFE26
-#define REG_USB_EP_MAXPKT1 0xFE27
-#define REG_USB_EP_DAT 0xFE28
-#define REG_USB_EP_BC0 0xFE29
-#define REG_USB_EP_BC1 0xFE2A
-#define REG_USB_EP_TC0 0xFE2B
-#define REG_USB_EP_TC1 0xFE2C
-#define REG_USB_EP_TC2 0xFE2D
-#define REG_USB_EP_CTL2 0xFE2E
-
-#define REG_USB_INFO 0xFE17
-#define REG_USB_SPECIAL_OPTION 0xFE55
-#define REG_USB_DMA_AGG_TO 0xFE5B
-#define REG_USB_AGG_TO 0xFE5C
-#define REG_USB_AGG_TH 0xFE5D
-
-#define REG_USB_VID 0xFE60
-#define REG_USB_PID 0xFE62
-#define REG_USB_OPT 0xFE64
-#define REG_USB_CONFIG 0xFE65 /* RX EP setting.
- * 0xFE65 Bit[3:0] : RXQ,
- * Bit[7:4] : INTQ
- */
- /* TX EP setting.
- * 0xFE66 Bit[3:0] : TXQ0,
- * Bit[7:4] : TXQ1,
- * 0xFE67 Bit[3:0] : TXQ2
- */
-#define REG_USB_PHY_PARA1 0xFE68 /* Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]),
- * Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0])
- */
-#define REG_USB_PHY_PARA2 0xFE69 /* Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]),
- * Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]),
- * Bit[1]: SE0_LVL (USB PHY 0xE5[7]),
- * Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1])
- */
-#define REG_USB_PHY_PARA3 0xFE6A /* Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]),
- * Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]),
- * Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]),
- * Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]),
- * Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1])
- */
-#define REG_USB_PHY_PARA4 0xFE6B /* (USB PHY 0xE7[7:0]) */
-#define REG_USB_OPT2 0xFE6C
-#define REG_USB_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */
-#define REG_USB_MANUFACTURE_SETTING 0xFE80 /* 0xFE80~0xFE90 Max: 32 bytes*/
-#define REG_USB_PRODUCT_STRING 0xFEA0 /* 0xFEA0~0xFECF Max: 48 bytes*/
-#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 /* 0xFED0~0xFEDF Max: 12 bytes*/
-
-#define REG_USB_ALTERNATE_SETTING 0xFE4F
-#define REG_USB_INT_BINTERVAL 0xFE6E
-#define REG_USB_GPS_EP_CONFIG 0xFE6D
-
-#endif /* __HALMAC_COM_REG_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __INC_HALMAC_REG_8822B_H
-#define __INC_HALMAC_REG_8822B_H
-
-#define REG_SYS_ISO_CTRL_8822B 0x0000
-#define REG_SYS_FUNC_EN_8822B 0x0002
-#define REG_SYS_PW_CTRL_8822B 0x0004
-#define REG_SYS_CLK_CTRL_8822B 0x0008
-#define REG_SYS_EEPROM_CTRL_8822B 0x000A
-#define REG_EE_VPD_8822B 0x000C
-#define REG_SYS_SWR_CTRL1_8822B 0x0010
-#define REG_SYS_SWR_CTRL2_8822B 0x0014
-#define REG_SYS_SWR_CTRL3_8822B 0x0018
-#define REG_RSV_CTRL_8822B 0x001C
-#define REG_RF_CTRL_8822B 0x001F
-#define REG_AFE_LDO_CTRL_8822B 0x0020
-#define REG_AFE_CTRL1_8822B 0x0024
-#define REG_AFE_CTRL2_8822B 0x0028
-#define REG_AFE_CTRL3_8822B 0x002C
-#define REG_EFUSE_CTRL_8822B 0x0030
-#define REG_LDO_EFUSE_CTRL_8822B 0x0034
-#define REG_PWR_OPTION_CTRL_8822B 0x0038
-#define REG_CAL_TIMER_8822B 0x003C
-#define REG_ACLK_MON_8822B 0x003E
-#define REG_GPIO_MUXCFG_8822B 0x0040
-#define REG_GPIO_PIN_CTRL_8822B 0x0044
-#define REG_GPIO_INTM_8822B 0x0048
-#define REG_LED_CFG_8822B 0x004C
-#define REG_FSIMR_8822B 0x0050
-#define REG_FSISR_8822B 0x0054
-#define REG_HSIMR_8822B 0x0058
-#define REG_HSISR_8822B 0x005C
-#define REG_GPIO_EXT_CTRL_8822B 0x0060
-#define REG_PAD_CTRL1_8822B 0x0064
-#define REG_WL_BT_PWR_CTRL_8822B 0x0068
-#define REG_SDM_DEBUG_8822B 0x006C
-#define REG_SYS_SDIO_CTRL_8822B 0x0070
-#define REG_HCI_OPT_CTRL_8822B 0x0074
-#define REG_AFE_CTRL4_8822B 0x0078
-#define REG_LDO_SWR_CTRL_8822B 0x007C
-#define REG_MCUFW_CTRL_8822B 0x0080
-#define REG_MCU_TST_CFG_8822B 0x0084
-#define REG_HMEBOX_E0_E1_8822B 0x0088
-#define REG_HMEBOX_E2_E3_8822B 0x008C
-#define REG_WLLPS_CTRL_8822B 0x0090
-#define REG_AFE_CTRL5_8822B 0x0094
-#define REG_GPIO_DEBOUNCE_CTRL_8822B 0x0098
-#define REG_RPWM2_8822B 0x009C
-#define REG_SYSON_FSM_MON_8822B 0x00A0
-#define REG_AFE_CTRL6_8822B 0x00A4
-#define REG_PMC_DBG_CTRL1_8822B 0x00A8
-#define REG_AFE_CTRL7_8822B 0x00AC
-#define REG_HIMR0_8822B 0x00B0
-#define REG_HISR0_8822B 0x00B4
-#define REG_HIMR1_8822B 0x00B8
-#define REG_HISR1_8822B 0x00BC
-#define REG_DBG_PORT_SEL_8822B 0x00C0
-#define REG_PAD_CTRL2_8822B 0x00C4
-#define REG_PMC_DBG_CTRL2_8822B 0x00CC
-#define REG_BIST_CTRL_8822B 0x00D0
-#define REG_BIST_RPT_8822B 0x00D4
-#define REG_MEM_CTRL_8822B 0x00D8
-#define REG_AFE_CTRL8_8822B 0x00DC
-#define REG_USB_SIE_INTF_8822B 0x00E0
-#define REG_PCIE_MIO_INTF_8822B 0x00E4
-#define REG_PCIE_MIO_INTD_8822B 0x00E8
-#define REG_WLRF1_8822B 0x00EC
-#define REG_SYS_CFG1_8822B 0x00F0
-#define REG_SYS_STATUS1_8822B 0x00F4
-#define REG_SYS_STATUS2_8822B 0x00F8
-#define REG_SYS_CFG2_8822B 0x00FC
-#define REG_SYS_CFG3_8822B 0x1000
-#define REG_SYS_CFG4_8822B 0x1034
-#define REG_SYS_CFG5_8822B 0x1070
-#define REG_CPU_DMEM_CON_8822B 0x1080
-#define REG_BOOT_REASON_8822B 0x1088
-#define REG_NFCPAD_CTRL_8822B 0x10A8
-#define REG_HIMR2_8822B 0x10B0
-#define REG_HISR2_8822B 0x10B4
-#define REG_HIMR3_8822B 0x10B8
-#define REG_HISR3_8822B 0x10BC
-#define REG_SW_MDIO_8822B 0x10C0
-#define REG_SW_FLUSH_8822B 0x10C4
-#define REG_H2C_PKT_READADDR_8822B 0x10D0
-#define REG_H2C_PKT_WRITEADDR_8822B 0x10D4
-#define REG_MEM_PWR_CRTL_8822B 0x10D8
-#define REG_FW_DBG0_8822B 0x10E0
-#define REG_FW_DBG1_8822B 0x10E4
-#define REG_FW_DBG2_8822B 0x10E8
-#define REG_FW_DBG3_8822B 0x10EC
-#define REG_FW_DBG4_8822B 0x10F0
-#define REG_FW_DBG5_8822B 0x10F4
-#define REG_FW_DBG6_8822B 0x10F8
-#define REG_FW_DBG7_8822B 0x10FC
-#define REG_CR_8822B 0x0100
-#define REG_PKT_BUFF_ACCESS_CTRL_8822B 0x0106
-#define REG_TSF_CLK_STATE_8822B 0x0108
-#define REG_TXDMA_PQ_MAP_8822B 0x010C
-#define REG_TRXFF_BNDY_8822B 0x0114
-#define REG_PTA_I2C_MBOX_8822B 0x0118
-#define REG_RXFF_BNDY_8822B 0x011C
-#define REG_FE1IMR_8822B 0x0120
-#define REG_FE1ISR_8822B 0x0124
-#define REG_CPWM_8822B 0x012C
-#define REG_FWIMR_8822B 0x0130
-#define REG_FWISR_8822B 0x0134
-#define REG_FTIMR_8822B 0x0138
-#define REG_FTISR_8822B 0x013C
-#define REG_PKTBUF_DBG_CTRL_8822B 0x0140
-#define REG_PKTBUF_DBG_DATA_L_8822B 0x0144
-#define REG_PKTBUF_DBG_DATA_H_8822B 0x0148
-#define REG_CPWM2_8822B 0x014C
-#define REG_TC0_CTRL_8822B 0x0150
-#define REG_TC1_CTRL_8822B 0x0154
-#define REG_TC2_CTRL_8822B 0x0158
-#define REG_TC3_CTRL_8822B 0x015C
-#define REG_TC4_CTRL_8822B 0x0160
-#define REG_TCUNIT_BASE_8822B 0x0164
-#define REG_TC5_CTRL_8822B 0x0168
-#define REG_TC6_CTRL_8822B 0x016C
-#define REG_MBIST_FAIL_8822B 0x0170
-#define REG_MBIST_START_PAUSE_8822B 0x0174
-#define REG_MBIST_DONE_8822B 0x0178
-#define REG_MBIST_FAIL_NRML_8822B 0x017C
-#define REG_AES_DECRPT_DATA_8822B 0x0180
-#define REG_AES_DECRPT_CFG_8822B 0x0184
-#define REG_TMETER_8822B 0x0190
-#define REG_OSC_32K_CTRL_8822B 0x0194
-#define REG_32K_CAL_REG1_8822B 0x0198
-#define REG_C2HEVT_8822B 0x01A0
-#define REG_SW_DEFINED_PAGE1_8822B 0x01B8
-#define REG_MCUTST_I_8822B 0x01C0
-#define REG_MCUTST_II_8822B 0x01C4
-#define REG_FMETHR_8822B 0x01C8
-#define REG_HMETFR_8822B 0x01CC
-#define REG_HMEBOX0_8822B 0x01D0
-#define REG_HMEBOX1_8822B 0x01D4
-#define REG_HMEBOX2_8822B 0x01D8
-#define REG_HMEBOX3_8822B 0x01DC
-#define REG_LLT_INIT_8822B 0x01E0
-#define REG_LLT_INIT_ADDR_8822B 0x01E4
-#define REG_BB_ACCESS_CTRL_8822B 0x01E8
-#define REG_BB_ACCESS_DATA_8822B 0x01EC
-#define REG_HMEBOX_E0_8822B 0x01F0
-#define REG_HMEBOX_E1_8822B 0x01F4
-#define REG_HMEBOX_E2_8822B 0x01F8
-#define REG_HMEBOX_E3_8822B 0x01FC
-#define REG_CR_EXT_8822B 0x1100
-#define REG_FWFF_8822B 0x1114
-#define REG_RXFF_PTR_V1_8822B 0x1118
-#define REG_RXFF_WTR_V1_8822B 0x111C
-#define REG_FE2IMR_8822B 0x1120
-#define REG_FE2ISR_8822B 0x1124
-#define REG_FE3IMR_8822B 0x1128
-#define REG_FE3ISR_8822B 0x112C
-#define REG_FE4IMR_8822B 0x1130
-#define REG_FE4ISR_8822B 0x1134
-#define REG_FT1IMR_8822B 0x1138
-#define REG_FT1ISR_8822B 0x113C
-#define REG_SPWR0_8822B 0x1140
-#define REG_SPWR1_8822B 0x1144
-#define REG_SPWR2_8822B 0x1148
-#define REG_SPWR3_8822B 0x114C
-#define REG_POWSEQ_8822B 0x1150
-#define REG_TC7_CTRL_V1_8822B 0x1158
-#define REG_TC8_CTRL_V1_8822B 0x115C
-#define REG_FT2IMR_8822B 0x11E0
-#define REG_FT2ISR_8822B 0x11E4
-#define REG_MSG2_8822B 0x11F0
-#define REG_MSG3_8822B 0x11F4
-#define REG_MSG4_8822B 0x11F8
-#define REG_MSG5_8822B 0x11FC
-#define REG_FIFOPAGE_CTRL_1_8822B 0x0200
-#define REG_FIFOPAGE_CTRL_2_8822B 0x0204
-#define REG_AUTO_LLT_V1_8822B 0x0208
-#define REG_TXDMA_OFFSET_CHK_8822B 0x020C
-#define REG_TXDMA_STATUS_8822B 0x0210
-#define REG_TX_DMA_DBG_8822B 0x0214
-#define REG_TQPNT1_8822B 0x0218
-#define REG_TQPNT2_8822B 0x021C
-#define REG_TQPNT3_8822B 0x0220
-#define REG_TQPNT4_8822B 0x0224
-#define REG_RQPN_CTRL_1_8822B 0x0228
-#define REG_RQPN_CTRL_2_8822B 0x022C
-#define REG_FIFOPAGE_INFO_1_8822B 0x0230
-#define REG_FIFOPAGE_INFO_2_8822B 0x0234
-#define REG_FIFOPAGE_INFO_3_8822B 0x0238
-#define REG_FIFOPAGE_INFO_4_8822B 0x023C
-#define REG_FIFOPAGE_INFO_5_8822B 0x0240
-#define REG_H2C_HEAD_8822B 0x0244
-#define REG_H2C_TAIL_8822B 0x0248
-#define REG_H2C_READ_ADDR_8822B 0x024C
-#define REG_H2C_WR_ADDR_8822B 0x0250
-#define REG_H2C_INFO_8822B 0x0254
-#define REG_RXDMA_AGG_PG_TH_8822B 0x0280
-#define REG_RXPKT_NUM_8822B 0x0284
-#define REG_RXDMA_STATUS_8822B 0x0288
-#define REG_RXDMA_DPR_8822B 0x028C
-#define REG_RXDMA_MODE_8822B 0x0290
-#define REG_C2H_PKT_8822B 0x0294
-#define REG_FWFF_C2H_8822B 0x0298
-#define REG_FWFF_CTRL_8822B 0x029C
-#define REG_FWFF_PKT_INFO_8822B 0x02A0
-#define REG_DDMA_CH0SA_8822B 0x1200
-#define REG_DDMA_CH0DA_8822B 0x1204
-#define REG_DDMA_CH0CTRL_8822B 0x1208
-#define REG_DDMA_CH1SA_8822B 0x1210
-#define REG_DDMA_CH1DA_8822B 0x1214
-#define REG_DDMA_CH1CTRL_8822B 0x1218
-#define REG_DDMA_CH2SA_8822B 0x1220
-#define REG_DDMA_CH2DA_8822B 0x1224
-#define REG_DDMA_CH2CTRL_8822B 0x1228
-#define REG_DDMA_CH3SA_8822B 0x1230
-#define REG_DDMA_CH3DA_8822B 0x1234
-#define REG_DDMA_CH3CTRL_8822B 0x1238
-#define REG_DDMA_CH4SA_8822B 0x1240
-#define REG_DDMA_CH4DA_8822B 0x1244
-#define REG_DDMA_CH4CTRL_8822B 0x1248
-#define REG_DDMA_CH5SA_8822B 0x1250
-#define REG_DDMA_CH5DA_8822B 0x1254
-#define REG_REG_DDMA_CH5CTRL_8822B 0x1258
-#define REG_DDMA_INT_MSK_8822B 0x12E0
-#define REG_DDMA_CHSTATUS_8822B 0x12E8
-#define REG_DDMA_CHKSUM_8822B 0x12F0
-#define REG_DDMA_MONITOR_8822B 0x12FC
-#define REG_PCIE_CTRL_8822B 0x0300
-#define REG_INT_MIG_8822B 0x0304
-#define REG_BCNQ_TXBD_DESA_8822B 0x0308
-#define REG_MGQ_TXBD_DESA_8822B 0x0310
-#define REG_VOQ_TXBD_DESA_8822B 0x0318
-#define REG_VIQ_TXBD_DESA_8822B 0x0320
-#define REG_BEQ_TXBD_DESA_8822B 0x0328
-#define REG_BKQ_TXBD_DESA_8822B 0x0330
-#define REG_RXQ_RXBD_DESA_8822B 0x0338
-#define REG_HI0Q_TXBD_DESA_8822B 0x0340
-#define REG_HI1Q_TXBD_DESA_8822B 0x0348
-#define REG_HI2Q_TXBD_DESA_8822B 0x0350
-#define REG_HI3Q_TXBD_DESA_8822B 0x0358
-#define REG_HI4Q_TXBD_DESA_8822B 0x0360
-#define REG_HI5Q_TXBD_DESA_8822B 0x0368
-#define REG_HI6Q_TXBD_DESA_8822B 0x0370
-#define REG_HI7Q_TXBD_DESA_8822B 0x0378
-#define REG_MGQ_TXBD_NUM_8822B 0x0380
-#define REG_RX_RXBD_NUM_8822B 0x0382
-#define REG_VOQ_TXBD_NUM_8822B 0x0384
-#define REG_VIQ_TXBD_NUM_8822B 0x0386
-#define REG_BEQ_TXBD_NUM_8822B 0x0388
-#define REG_BKQ_TXBD_NUM_8822B 0x038A
-#define REG_HI0Q_TXBD_NUM_8822B 0x038C
-#define REG_HI1Q_TXBD_NUM_8822B 0x038E
-#define REG_HI2Q_TXBD_NUM_8822B 0x0390
-#define REG_HI3Q_TXBD_NUM_8822B 0x0392
-#define REG_HI4Q_TXBD_NUM_8822B 0x0394
-#define REG_HI5Q_TXBD_NUM_8822B 0x0396
-#define REG_HI6Q_TXBD_NUM_8822B 0x0398
-#define REG_HI7Q_TXBD_NUM_8822B 0x039A
-#define REG_TSFTIMER_HCI_8822B 0x039C
-#define REG_BD_RWPTR_CLR_8822B 0x039C
-#define REG_VOQ_TXBD_IDX_8822B 0x03A0
-#define REG_VIQ_TXBD_IDX_8822B 0x03A4
-#define REG_BEQ_TXBD_IDX_8822B 0x03A8
-#define REG_BKQ_TXBD_IDX_8822B 0x03AC
-#define REG_MGQ_TXBD_IDX_8822B 0x03B0
-#define REG_RXQ_RXBD_IDX_8822B 0x03B4
-#define REG_HI0Q_TXBD_IDX_8822B 0x03B8
-#define REG_HI1Q_TXBD_IDX_8822B 0x03BC
-#define REG_HI2Q_TXBD_IDX_8822B 0x03C0
-#define REG_HI3Q_TXBD_IDX_8822B 0x03C4
-#define REG_HI4Q_TXBD_IDX_8822B 0x03C8
-#define REG_HI5Q_TXBD_IDX_8822B 0x03CC
-#define REG_HI6Q_TXBD_IDX_8822B 0x03D0
-#define REG_HI7Q_TXBD_IDX_8822B 0x03D4
-#define REG_DBG_SEL_V1_8822B 0x03D8
-#define REG_PCIE_HRPWM1_V1_8822B 0x03D9
-#define REG_PCIE_HCPWM1_V1_8822B 0x03DA
-#define REG_PCIE_CTRL2_8822B 0x03DB
-#define REG_PCIE_HRPWM2_V1_8822B 0x03DC
-#define REG_PCIE_HCPWM2_V1_8822B 0x03DE
-#define REG_PCIE_H2C_MSG_V1_8822B 0x03E0
-#define REG_PCIE_C2H_MSG_V1_8822B 0x03E4
-#define REG_DBI_WDATA_V1_8822B 0x03E8
-#define REG_DBI_RDATA_V1_8822B 0x03EC
-#define REG_DBI_FLAG_V1_8822B 0x03F0
-#define REG_MDIO_V1_8822B 0x03F4
-#define REG_PCIE_MIX_CFG_8822B 0x03F8
-#define REG_HCI_MIX_CFG_8822B 0x03FC
-#define REG_STC_INT_CS_8822B 0x1300
-#define REG_ST_INT_CFG_8822B 0x1304
-#define REG_CMU_DLY_CTRL_8822B 0x1310
-#define REG_CMU_DLY_CFG_8822B 0x1314
-#define REG_H2CQ_TXBD_DESA_8822B 0x1320
-#define REG_H2CQ_TXBD_NUM_8822B 0x1328
-#define REG_H2CQ_TXBD_IDX_8822B 0x132C
-#define REG_H2CQ_CSR_8822B 0x1330
-#define REG_CHANGE_PCIE_SPEED_8822B 0x1350
-#define REG_OLD_DEHANG_8822B 0x13F4
-#define REG_Q0_INFO_8822B 0x0400
-#define REG_Q1_INFO_8822B 0x0404
-#define REG_Q2_INFO_8822B 0x0408
-#define REG_Q3_INFO_8822B 0x040C
-#define REG_MGQ_INFO_8822B 0x0410
-#define REG_HIQ_INFO_8822B 0x0414
-#define REG_BCNQ_INFO_8822B 0x0418
-#define REG_TXPKT_EMPTY_8822B 0x041A
-#define REG_CPU_MGQ_INFO_8822B 0x041C
-#define REG_FWHW_TXQ_CTRL_8822B 0x0420
-#define REG_DATAFB_SEL_8822B 0x0423
-#define REG_BCNQ_BDNY_V1_8822B 0x0424
-#define REG_LIFETIME_EN_8822B 0x0426
-#define REG_SPEC_SIFS_8822B 0x0428
-#define REG_RETRY_LIMIT_8822B 0x042A
-#define REG_TXBF_CTRL_8822B 0x042C
-#define REG_DARFRC_8822B 0x0430
-#define REG_RARFRC_8822B 0x0438
-#define REG_RRSR_8822B 0x0440
-#define REG_ARFR0_8822B 0x0444
-#define REG_ARFR1_V1_8822B 0x044C
-#define REG_CCK_CHECK_8822B 0x0454
-#define REG_AMPDU_MAX_TIME_V1_8822B 0x0455
-#define REG_BCNQ1_BDNY_V1_8822B 0x0456
-#define REG_AMPDU_MAX_LENGTH_8822B 0x0458
-#define REG_ACQ_STOP_8822B 0x045C
-#define REG_NDPA_RATE_8822B 0x045D
-#define REG_TX_HANG_CTRL_8822B 0x045E
-#define REG_NDPA_OPT_CTRL_8822B 0x045F
-#define REG_RD_RESP_PKT_TH_8822B 0x0463
-#define REG_CMDQ_INFO_8822B 0x0464
-#define REG_Q4_INFO_8822B 0x0468
-#define REG_Q5_INFO_8822B 0x046C
-#define REG_Q6_INFO_8822B 0x0470
-#define REG_Q7_INFO_8822B 0x0474
-#define REG_WMAC_LBK_BUF_HD_V1_8822B 0x0478
-#define REG_MGQ_BDNY_V1_8822B 0x047A
-#define REG_TXRPT_CTRL_8822B 0x047C
-#define REG_INIRTS_RATE_SEL_8822B 0x0480
-#define REG_BASIC_CFEND_RATE_8822B 0x0481
-#define REG_STBC_CFEND_RATE_8822B 0x0482
-#define REG_DATA_SC_8822B 0x0483
-#define REG_MACID_SLEEP3_8822B 0x0484
-#define REG_MACID_SLEEP1_8822B 0x0488
-#define REG_ARFR2_V1_8822B 0x048C
-#define REG_ARFR3_V1_8822B 0x0494
-#define REG_ARFR4_8822B 0x049C
-#define REG_ARFR5_8822B 0x04A4
-#define REG_TXRPT_START_OFFSET_8822B 0x04AC
-#define REG_POWER_STAGE1_8822B 0x04B4
-#define REG_POWER_STAGE2_8822B 0x04B8
-#define REG_SW_AMPDU_BURST_MODE_CTRL_8822B 0x04BC
-#define REG_PKT_LIFE_TIME_8822B 0x04C0
-#define REG_STBC_SETTING_8822B 0x04C4
-#define REG_STBC_SETTING2_8822B 0x04C5
-#define REG_QUEUE_CTRL_8822B 0x04C6
-#define REG_SINGLE_AMPDU_CTRL_8822B 0x04C7
-#define REG_PROT_MODE_CTRL_8822B 0x04C8
-#define REG_BAR_MODE_CTRL_8822B 0x04CC
-#define REG_RA_TRY_RATE_AGG_LMT_8822B 0x04CF
-#define REG_MACID_SLEEP2_8822B 0x04D0
-#define REG_MACID_SLEEP_8822B 0x04D4
-#define REG_HW_SEQ0_8822B 0x04D8
-#define REG_HW_SEQ1_8822B 0x04DA
-#define REG_HW_SEQ2_8822B 0x04DC
-#define REG_HW_SEQ3_8822B 0x04DE
-#define REG_NULL_PKT_STATUS_V1_8822B 0x04E0
-#define REG_PTCL_ERR_STATUS_8822B 0x04E2
-#define REG_NULL_PKT_STATUS_EXTEND_8822B 0x04E3
-#define REG_VIDEO_ENHANCEMENT_FUN_8822B 0x04E4
-#define REG_BT_POLLUTE_PKT_CNT_8822B 0x04E8
-#define REG_PTCL_DBG_8822B 0x04EC
-#define REG_CPUMGQ_TIMER_CTRL2_8822B 0x04F4
-#define REG_DUMMY_PAGE4_V1_8822B 0x04FC
-#define REG_MOREDATA_8822B 0x04FE
-#define REG_Q0_Q1_INFO_8822B 0x1400
-#define REG_Q2_Q3_INFO_8822B 0x1404
-#define REG_Q4_Q5_INFO_8822B 0x1408
-#define REG_Q6_Q7_INFO_8822B 0x140C
-#define REG_MGQ_HIQ_INFO_8822B 0x1410
-#define REG_CMDQ_BCNQ_INFO_8822B 0x1414
-#define REG_USEREG_SETTING_8822B 0x1420
-#define REG_AESIV_SETTING_8822B 0x1424
-#define REG_BF0_TIME_SETTING_8822B 0x1428
-#define REG_BF1_TIME_SETTING_8822B 0x142C
-#define REG_BF_TIMEOUT_EN_8822B 0x1430
-#define REG_MACID_RELEASE0_8822B 0x1434
-#define REG_MACID_RELEASE1_8822B 0x1438
-#define REG_MACID_RELEASE2_8822B 0x143C
-#define REG_MACID_RELEASE3_8822B 0x1440
-#define REG_MACID_RELEASE_SETTING_8822B 0x1444
-#define REG_FAST_EDCA_VOVI_SETTING_8822B 0x1448
-#define REG_FAST_EDCA_BEBK_SETTING_8822B 0x144C
-#define REG_MACID_DROP0_8822B 0x1450
-#define REG_MACID_DROP1_8822B 0x1454
-#define REG_MACID_DROP2_8822B 0x1458
-#define REG_MACID_DROP3_8822B 0x145C
-#define REG_R_MACID_RELEASE_SUCCESS_0_8822B 0x1460
-#define REG_R_MACID_RELEASE_SUCCESS_1_8822B 0x1464
-#define REG_R_MACID_RELEASE_SUCCESS_2_8822B 0x1468
-#define REG_R_MACID_RELEASE_SUCCESS_3_8822B 0x146C
-#define REG_MGG_FIFO_CRTL_8822B 0x1470
-#define REG_MGG_FIFO_INT_8822B 0x1474
-#define REG_MGG_FIFO_LIFETIME_8822B 0x1478
-#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C
-#define REG_MACID_SHCUT_OFFSET_8822B 0x1480
-#define REG_MU_TX_CTL_8822B 0x14C0
-#define REG_MU_STA_GID_VLD_8822B 0x14C4
-#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8
-#define REG_MU_TRX_DBG_CNT_8822B 0x14D0
-#define REG_EDCA_VO_PARAM_8822B 0x0500
-#define REG_EDCA_VI_PARAM_8822B 0x0504
-#define REG_EDCA_BE_PARAM_8822B 0x0508
-#define REG_EDCA_BK_PARAM_8822B 0x050C
-#define REG_BCNTCFG_8822B 0x0510
-#define REG_PIFS_8822B 0x0512
-#define REG_RDG_PIFS_8822B 0x0513
-#define REG_SIFS_8822B 0x0514
-#define REG_TSFTR_SYN_OFFSET_8822B 0x0518
-#define REG_AGGR_BREAK_TIME_8822B 0x051A
-#define REG_SLOT_8822B 0x051B
-#define REG_TX_PTCL_CTRL_8822B 0x0520
-#define REG_TXPAUSE_8822B 0x0522
-#define REG_DIS_TXREQ_CLR_8822B 0x0523
-#define REG_RD_CTRL_8822B 0x0524
-#define REG_MBSSID_CTRL_8822B 0x0526
-#define REG_P2PPS_CTRL_8822B 0x0527
-#define REG_PKT_LIFETIME_CTRL_8822B 0x0528
-#define REG_P2PPS_SPEC_STATE_8822B 0x052B
-#define REG_BAR_TX_CTRL_8822B 0x0530
-#define REG_QUEUE_INCOL_THR_8822B 0x0538
-#define REG_QUEUE_INCOL_EN_8822B 0x053C
-#define REG_TBTT_PROHIBIT_8822B 0x0540
-#define REG_P2PPS_STATE_8822B 0x0543
-#define REG_RD_NAV_NXT_8822B 0x0544
-#define REG_NAV_PROT_LEN_8822B 0x0546
-#define REG_BCN_CTRL_8822B 0x0550
-#define REG_BCN_CTRL_CLINT0_8822B 0x0551
-#define REG_MBID_NUM_8822B 0x0552
-#define REG_DUAL_TSF_RST_8822B 0x0553
-#define REG_MBSSID_BCN_SPACE_8822B 0x0554
-#define REG_DRVERLYINT_8822B 0x0558
-#define REG_BCNDMATIM_8822B 0x0559
-#define REG_ATIMWND_8822B 0x055A
-#define REG_USTIME_TSF_8822B 0x055C
-#define REG_BCN_MAX_ERR_8822B 0x055D
-#define REG_RXTSF_OFFSET_CCK_8822B 0x055E
-#define REG_RXTSF_OFFSET_OFDM_8822B 0x055F
-#define REG_TSFTR_8822B 0x0560
-#define REG_FREERUN_CNT_8822B 0x0568
-#define REG_ATIMWND1_V1_8822B 0x0570
-#define REG_TBTT_PROHIBIT_INFRA_8822B 0x0571
-#define REG_CTWND_8822B 0x0572
-#define REG_BCNIVLCUNT_8822B 0x0573
-#define REG_BCNDROPCTRL_8822B 0x0574
-#define REG_HGQ_TIMEOUT_PERIOD_8822B 0x0575
-#define REG_TXCMD_TIMEOUT_PERIOD_8822B 0x0576
-#define REG_MISC_CTRL_8822B 0x0577
-#define REG_BCN_CTRL_CLINT1_8822B 0x0578
-#define REG_BCN_CTRL_CLINT2_8822B 0x0579
-#define REG_BCN_CTRL_CLINT3_8822B 0x057A
-#define REG_EXTEND_CTRL_8822B 0x057B
-#define REG_P2PPS1_SPEC_STATE_8822B 0x057C
-#define REG_P2PPS1_STATE_8822B 0x057D
-#define REG_P2PPS2_SPEC_STATE_8822B 0x057E
-#define REG_P2PPS2_STATE_8822B 0x057F
-#define REG_PS_TIMER0_8822B 0x0580
-#define REG_PS_TIMER1_8822B 0x0584
-#define REG_PS_TIMER2_8822B 0x0588
-#define REG_TBTT_CTN_AREA_8822B 0x058C
-#define REG_FORCE_BCN_IFS_8822B 0x058E
-#define REG_TXOP_MIN_8822B 0x0590
-#define REG_PRE_BKF_TIME_8822B 0x0592
-#define REG_CROSS_TXOP_CTRL_8822B 0x0593
-#define REG_ATIMWND2_8822B 0x05A0
-#define REG_ATIMWND3_8822B 0x05A1
-#define REG_ATIMWND4_8822B 0x05A2
-#define REG_ATIMWND5_8822B 0x05A3
-#define REG_ATIMWND6_8822B 0x05A4
-#define REG_ATIMWND7_8822B 0x05A5
-#define REG_ATIMUGT_8822B 0x05A6
-#define REG_HIQ_NO_LMT_EN_8822B 0x05A7
-#define REG_DTIM_COUNTER_ROOT_8822B 0x05A8
-#define REG_DTIM_COUNTER_VAP1_8822B 0x05A9
-#define REG_DTIM_COUNTER_VAP2_8822B 0x05AA
-#define REG_DTIM_COUNTER_VAP3_8822B 0x05AB
-#define REG_DTIM_COUNTER_VAP4_8822B 0x05AC
-#define REG_DTIM_COUNTER_VAP5_8822B 0x05AD
-#define REG_DTIM_COUNTER_VAP6_8822B 0x05AE
-#define REG_DTIM_COUNTER_VAP7_8822B 0x05AF
-#define REG_DIS_ATIM_8822B 0x05B0
-#define REG_EARLY_128US_8822B 0x05B1
-#define REG_P2PPS1_CTRL_8822B 0x05B2
-#define REG_P2PPS2_CTRL_8822B 0x05B3
-#define REG_TIMER0_SRC_SEL_8822B 0x05B4
-#define REG_NOA_UNIT_SEL_8822B 0x05B5
-#define REG_P2POFF_DIS_TXTIME_8822B 0x05B7
-#define REG_MBSSID_BCN_SPACE2_8822B 0x05B8
-#define REG_MBSSID_BCN_SPACE3_8822B 0x05BC
-#define REG_ACMHWCTRL_8822B 0x05C0
-#define REG_ACMRSTCTRL_8822B 0x05C1
-#define REG_ACMAVG_8822B 0x05C2
-#define REG_VO_ADMTIME_8822B 0x05C4
-#define REG_VI_ADMTIME_8822B 0x05C6
-#define REG_BE_ADMTIME_8822B 0x05C8
-#define REG_EDCA_RANDOM_GEN_8822B 0x05CC
-#define REG_TXCMD_NOA_SEL_8822B 0x05CF
-#define REG_NOA_PARAM_8822B 0x05E0
-#define REG_P2P_RST_8822B 0x05F0
-#define REG_SCHEDULER_RST_8822B 0x05F1
-#define REG_SCH_TXCMD_8822B 0x05F8
-#define REG_PAGE5_DUMMY_8822B 0x05FC
-#define REG_CPUMGQ_TX_TIMER_8822B 0x1500
-#define REG_PS_TIMER_A_8822B 0x1504
-#define REG_PS_TIMER_B_8822B 0x1508
-#define REG_PS_TIMER_C_8822B 0x150C
-#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B 0x1510
-#define REG_CPUMGQ_TX_TIMER_EARLY_8822B 0x1514
-#define REG_PS_TIMER_A_EARLY_8822B 0x1515
-#define REG_PS_TIMER_B_EARLY_8822B 0x1516
-#define REG_PS_TIMER_C_EARLY_8822B 0x1517
-#define REG_WMAC_CR_8822B 0x0600
-#define REG_WMAC_FWPKT_CR_8822B 0x0601
-#define REG_BWOPMODE_8822B 0x0603
-#define REG_TCR_8822B 0x0604
-#define REG_RCR_8822B 0x0608
-#define REG_RX_PKT_LIMIT_8822B 0x060C
-#define REG_RX_DLK_TIME_8822B 0x060D
-#define REG_RX_DRVINFO_SZ_8822B 0x060F
-#define REG_MACID_8822B 0x0610
-#define REG_BSSID_8822B 0x0618
-#define REG_MAR_8822B 0x0620
-#define REG_MBIDCAMCFG_1_8822B 0x0628
-#define REG_MBIDCAMCFG_2_8822B 0x062C
-#define REG_WMAC_TCR_TSFT_OFS_8822B 0x0630
-#define REG_UDF_THSD_8822B 0x0632
-#define REG_ZLD_NUM_8822B 0x0633
-#define REG_STMP_THSD_8822B 0x0634
-#define REG_WMAC_TXTIMEOUT_8822B 0x0635
-#define REG_MCU_TEST_2_V1_8822B 0x0636
-#define REG_USTIME_EDCA_8822B 0x0638
-#define REG_MAC_SPEC_SIFS_8822B 0x063A
-#define REG_RESP_SIFS_CCK_8822B 0x063C
-#define REG_RESP_SIFS_OFDM_8822B 0x063E
-#define REG_ACKTO_8822B 0x0640
-#define REG_CTS2TO_8822B 0x0641
-#define REG_EIFS_8822B 0x0642
-#define REG_NAV_CTRL_8822B 0x0650
-#define REG_BACAMCMD_8822B 0x0654
-#define REG_BACAMCONTENT_8822B 0x0658
-#define REG_LBDLY_8822B 0x0660
-#define REG_WMAC_BACAM_RPMEN_8822B 0x0661
-#define REG_TX_RX_8822B 0x0662
-#define REG_WMAC_BITMAP_CTL_8822B 0x0663
-#define REG_RXERR_RPT_8822B 0x0664
-#define REG_WMAC_TRXPTCL_CTL_8822B 0x0668
-#define REG_CAMCMD_8822B 0x0670
-#define REG_CAMWRITE_8822B 0x0674
-#define REG_CAMREAD_8822B 0x0678
-#define REG_CAMDBG_8822B 0x067C
-#define REG_SECCFG_8822B 0x0680
-#define REG_RXFILTER_CATEGORY_1_8822B 0x0682
-#define REG_RXFILTER_ACTION_1_8822B 0x0683
-#define REG_RXFILTER_CATEGORY_2_8822B 0x0684
-#define REG_RXFILTER_ACTION_2_8822B 0x0685
-#define REG_RXFILTER_CATEGORY_3_8822B 0x0686
-#define REG_RXFILTER_ACTION_3_8822B 0x0687
-#define REG_RXFLTMAP3_8822B 0x0688
-#define REG_RXFLTMAP4_8822B 0x068A
-#define REG_RXFLTMAP5_8822B 0x068C
-#define REG_RXFLTMAP6_8822B 0x068E
-#define REG_WOW_CTRL_8822B 0x0690
-#define REG_NAN_RX_TSF_FILTER_8822B 0x0691
-#define REG_PS_RX_INFO_8822B 0x0692
-#define REG_WMMPS_UAPSD_TID_8822B 0x0693
-#define REG_LPNAV_CTRL_8822B 0x0694
-#define REG_WKFMCAM_CMD_8822B 0x0698
-#define REG_WKFMCAM_RWD_8822B 0x069C
-#define REG_RXFLTMAP0_8822B 0x06A0
-#define REG_RXFLTMAP1_8822B 0x06A2
-#define REG_RXFLTMAP_8822B 0x06A4
-#define REG_BCN_PSR_RPT_8822B 0x06A8
-#define REG_FLC_RPC_8822B 0x06AC
-#define REG_FLC_RPCT_8822B 0x06AD
-#define REG_FLC_PTS_8822B 0x06AE
-#define REG_FLC_TRPC_8822B 0x06AF
-#define REG_RXPKTMON_CTRL_8822B 0x06B0
-#define REG_STATE_MON_8822B 0x06B4
-#define REG_ERROR_MON_8822B 0x06B8
-#define REG_SEARCH_MACID_8822B 0x06BC
-#define REG_BT_COEX_TABLE_8822B 0x06C0
-#define REG_RXCMD_0_8822B 0x06D0
-#define REG_RXCMD_1_8822B 0x06D4
-#define REG_WMAC_RESP_TXINFO_8822B 0x06D8
-#define REG_BBPSF_CTRL_8822B 0x06DC
-#define REG_P2P_RX_BCN_NOA_8822B 0x06E0
-#define REG_ASSOCIATED_BFMER0_INFO_8822B 0x06E4
-#define REG_ASSOCIATED_BFMER1_INFO_8822B 0x06EC
-#define REG_TX_CSI_RPT_PARAM_BW20_8822B 0x06F4
-#define REG_TX_CSI_RPT_PARAM_BW40_8822B 0x06F8
-#define REG_TX_CSI_RPT_PARAM_BW80_8822B 0x06FC
-#define REG_BCN_PSR_RPT2_8822B 0x1600
-#define REG_BCN_PSR_RPT3_8822B 0x1604
-#define REG_BCN_PSR_RPT4_8822B 0x1608
-#define REG_A1_ADDR_MASK_8822B 0x160C
-#define REG_MACID2_8822B 0x1620
-#define REG_BSSID2_8822B 0x1628
-#define REG_MACID3_8822B 0x1630
-#define REG_BSSID3_8822B 0x1638
-#define REG_MACID4_8822B 0x1640
-#define REG_BSSID4_8822B 0x1648
-#define REG_NOA_REPORT_8822B 0x1650
-#define REG_PWRBIT_SETTING_8822B 0x1660
-#define REG_WMAC_MU_BF_OPTION_8822B 0x167C
-#define REG_WMAC_MU_ARB_8822B 0x167E
-#define REG_WMAC_MU_OPTION_8822B 0x167F
-#define REG_WMAC_MU_BF_CTL_8822B 0x1680
-#define REG_WMAC_MU_BFRPT_PARA_8822B 0x1682
-#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B 0x1684
-#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B 0x1686
-#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B 0x1688
-#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B 0x168A
-#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B 0x168C
-#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B 0x168E
-#define REG_TRANSMIT_ADDRSS_0_8822B 0x16A0
-#define REG_TRANSMIT_ADDRSS_1_8822B 0x16A8
-#define REG_TRANSMIT_ADDRSS_2_8822B 0x16B0
-#define REG_TRANSMIT_ADDRSS_3_8822B 0x16B8
-#define REG_TRANSMIT_ADDRSS_4_8822B 0x16C0
-#define REG_MACID1_8822B 0x0700
-#define REG_BSSID1_8822B 0x0708
-#define REG_BCN_PSR_RPT1_8822B 0x0710
-#define REG_ASSOCIATED_BFMEE_SEL_8822B 0x0714
-#define REG_SND_PTCL_CTRL_8822B 0x0718
-#define REG_RX_CSI_RPT_INFO_8822B 0x071C
-#define REG_NS_ARP_CTRL_8822B 0x0720
-#define REG_NS_ARP_INFO_8822B 0x0724
-#define REG_BEAMFORMING_INFO_NSARP_V1_8822B 0x0728
-#define REG_BEAMFORMING_INFO_NSARP_8822B 0x072C
-#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B 0x0750
-#define REG_WMAC_SWAES_CFG_8822B 0x0760
-#define REG_BT_COEX_V2_8822B 0x0762
-#define REG_BT_COEX_8822B 0x0764
-#define REG_WLAN_ACT_MASK_CTRL_8822B 0x0768
-#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822B 0x076E
-#define REG_BT_ACT_STATISTICS_8822B 0x0770
-#define REG_BT_STATISTICS_CONTROL_REGISTER_8822B 0x0778
-#define REG_BT_STATUS_REPORT_REGISTER_8822B 0x077C
-#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822B 0x0780
-#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B 0x0784
-#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B 0x0785
-#define REG_BT_INTERRUPT_STATUS_REGISTER_8822B 0x078F
-#define REG_BT_TDMA_TIME_REGISTER_8822B 0x0790
-#define REG_BT_ACT_REGISTER_8822B 0x0794
-#define REG_OBFF_CTRL_BASIC_8822B 0x0798
-#define REG_OBFF_CTRL2_TIMER_8822B 0x079C
-#define REG_LTR_CTRL_BASIC_8822B 0x07A0
-#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822B 0x07A4
-#define REG_LTR_IDLE_LATENCY_V1_8822B 0x07A8
-#define REG_LTR_ACTIVE_LATENCY_V1_8822B 0x07AC
-#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B 0x07B0
-#define REG_WMAC_PKTCNT_RWD_8822B 0x07B8
-#define REG_WMAC_PKTCNT_CTRL_8822B 0x07BC
-#define REG_IQ_DUMP_8822B 0x07C0
-#define REG_WMAC_FTM_CTL_8822B 0x07CC
-#define REG_WMAC_IQ_MDPK_FUNC_8822B 0x07CE
-#define REG_WMAC_OPTION_FUNCTION_8822B 0x07D0
-#define REG_RX_FILTER_FUNCTION_8822B 0x07DA
-#define REG_NDP_SIG_8822B 0x07E0
-#define REG_TXCMD_INFO_FOR_RSP_PKT_8822B 0x07E4
-#define REG_RTS_ADDRESS_0_8822B 0x07F0
-#define REG_RTS_ADDRESS_1_8822B 0x07F8
-#define REG__RPFM_MAP1_8822B 0x07FE
-#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B 0x1700
-#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B 0x1704
-#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B 0x1708
-#define REG_SDIO_TX_CTRL_8822B 0x10250000
-#define REG_SDIO_HIMR_8822B 0x10250014
-#define REG_SDIO_HISR_8822B 0x10250018
-#define REG_SDIO_RX_REQ_LEN_8822B 0x1025001C
-#define REG_SDIO_FREE_TXPG_SEQ_V1_8822B 0x1025001F
-#define REG_SDIO_FREE_TXPG_8822B 0x10250020
-#define REG_SDIO_FREE_TXPG2_8822B 0x10250024
-#define REG_SDIO_OQT_FREE_TXPG_V1_8822B 0x10250028
-#define REG_SDIO_HTSFR_INFO_8822B 0x10250030
-#define REG_SDIO_HCPWM1_V2_8822B 0x10250038
-#define REG_SDIO_HCPWM2_V2_8822B 0x1025003A
-#define REG_SDIO_INDIRECT_REG_CFG_8822B 0x10250040
-#define REG_SDIO_INDIRECT_REG_DATA_8822B 0x10250044
-#define REG_SDIO_H2C_8822B 0x10250060
-#define REG_SDIO_C2H_8822B 0x10250064
-#define REG_SDIO_HRPWM1_8822B 0x10250080
-#define REG_SDIO_HRPWM2_8822B 0x10250082
-#define REG_SDIO_HPS_CLKR_8822B 0x10250084
-#define REG_SDIO_BUS_CTRL_8822B 0x10250085
-#define REG_SDIO_HSUS_CTRL_8822B 0x10250086
-#define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088
-#define REG_SDIO_CMD_CRC_8822B 0x1025008A
-#define REG_SDIO_HSISR_8822B 0x10250090
-#define REG_SDIO_HSIMR_8822B 0x10250091
-#define REG_SDIO_ERR_RPT_8822B 0x102500C0
-#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C1
-#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C2
-#define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4
-#define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9
-#define REG_SDIO_DATA_CRC_8822B 0x102500CA
-#define REG_SDIO_DATA_REPLY_TIME_8822B 0x102500CB
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_RX_BD_CHIP_H_
-#define _HALMAC_RX_BD_CHIP_H_
-
-/*TXBD_DW0*/
-
-#define GET_RX_BD_RXFAIL_8822B(__rx_bd) GET_RX_BD_RXFAIL(__rx_bd)
-#define GET_RX_BD_TOTALRXPKTSIZE_8822B(__rx_bd) \
- GET_RX_BD_TOTALRXPKTSIZE(__rx_bd)
-#define GET_RX_BD_RXTAG_8822B(__rx_bd) GET_RX_BD_RXTAG(__rx_bd)
-#define GET_RX_BD_FS_8822B(__rx_bd) GET_RX_BD_FS(__rx_bd)
-#define GET_RX_BD_LS_8822B(__rx_bd) GET_RX_BD_LS(__rx_bd)
-#define GET_RX_BD_RXBUFFSIZE_8822B(__rx_bd) GET_RX_BD_RXBUFFSIZE(__rx_bd)
-
-/*TXBD_DW1*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_LOW_8822B(__rx_bd) \
- GET_RX_BD_PHYSICAL_ADDR_LOW(__rx_bd)
-
-/*TXBD_DW2*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8822B(__rx_bd) \
- GET_RX_BD_PHYSICAL_ADDR_HIGH(__rx_bd)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_RX_BD_NIC_H_
-#define _HALMAC_RX_BD_NIC_H_
-
-/*TXBD_DW0*/
-
-#define GET_RX_BD_RXFAIL(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 31, 1)
-#define GET_RX_BD_TOTALRXPKTSIZE(__rx_bd) \
- LE_BITS_TO_4BYTE(__rx_bd + 0x00, 16, 13)
-#define GET_RX_BD_RXTAG(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 16, 13)
-#define GET_RX_BD_FS(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 15, 1)
-#define GET_RX_BD_LS(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 14, 1)
-#define GET_RX_BD_RXBUFFSIZE(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 0, 14)
-
-/*TXBD_DW1*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_LOW(__rx_bd) \
- LE_BITS_TO_4BYTE(__rx_bd + 0x04, 0, 32)
-
-/*TXBD_DW2*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__rx_bd) \
- LE_BITS_TO_4BYTE(__rx_bd + 0x08, 0, 32)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_RX_DESC_CHIP_H_
-#define _HALMAC_RX_DESC_CHIP_H_
-
-/*RXDESC_WORD0*/
-
-#define GET_RX_DESC_EOR_8822B(__rx_desc) GET_RX_DESC_EOR(__rx_desc)
-#define GET_RX_DESC_PHYPKTIDC_8822B(__rx_desc) GET_RX_DESC_PHYPKTIDC(__rx_desc)
-#define GET_RX_DESC_SWDEC_8822B(__rx_desc) GET_RX_DESC_SWDEC(__rx_desc)
-#define GET_RX_DESC_PHYST_8822B(__rx_desc) GET_RX_DESC_PHYST(__rx_desc)
-#define GET_RX_DESC_SHIFT_8822B(__rx_desc) GET_RX_DESC_SHIFT(__rx_desc)
-#define GET_RX_DESC_QOS_8822B(__rx_desc) GET_RX_DESC_QOS(__rx_desc)
-#define GET_RX_DESC_SECURITY_8822B(__rx_desc) GET_RX_DESC_SECURITY(__rx_desc)
-#define GET_RX_DESC_DRV_INFO_SIZE_8822B(__rx_desc) \
- GET_RX_DESC_DRV_INFO_SIZE(__rx_desc)
-#define GET_RX_DESC_ICV_ERR_8822B(__rx_desc) GET_RX_DESC_ICV_ERR(__rx_desc)
-#define GET_RX_DESC_CRC32_8822B(__rx_desc) GET_RX_DESC_CRC32(__rx_desc)
-#define GET_RX_DESC_PKT_LEN_8822B(__rx_desc) GET_RX_DESC_PKT_LEN(__rx_desc)
-
-/*RXDESC_WORD1*/
-
-#define GET_RX_DESC_BC_8822B(__rx_desc) GET_RX_DESC_BC(__rx_desc)
-#define GET_RX_DESC_MC_8822B(__rx_desc) GET_RX_DESC_MC(__rx_desc)
-#define GET_RX_DESC_TY_PE_8822B(__rx_desc) GET_RX_DESC_TY_PE(__rx_desc)
-#define GET_RX_DESC_MF_8822B(__rx_desc) GET_RX_DESC_MF(__rx_desc)
-#define GET_RX_DESC_MD_8822B(__rx_desc) GET_RX_DESC_MD(__rx_desc)
-#define GET_RX_DESC_PWR_8822B(__rx_desc) GET_RX_DESC_PWR(__rx_desc)
-#define GET_RX_DESC_PAM_8822B(__rx_desc) GET_RX_DESC_PAM(__rx_desc)
-#define GET_RX_DESC_CHK_VLD_8822B(__rx_desc) GET_RX_DESC_CHK_VLD(__rx_desc)
-#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(__rx_desc) \
- GET_RX_DESC_RX_IS_TCP_UDP(__rx_desc)
-#define GET_RX_DESC_RX_IPV_8822B(__rx_desc) GET_RX_DESC_RX_IPV(__rx_desc)
-#define GET_RX_DESC_CHKERR_8822B(__rx_desc) GET_RX_DESC_CHKERR(__rx_desc)
-#define GET_RX_DESC_PAGGR_8822B(__rx_desc) GET_RX_DESC_PAGGR(__rx_desc)
-#define GET_RX_DESC_RXID_MATCH_8822B(__rx_desc) \
- GET_RX_DESC_RXID_MATCH(__rx_desc)
-#define GET_RX_DESC_AMSDU_8822B(__rx_desc) GET_RX_DESC_AMSDU(__rx_desc)
-#define GET_RX_DESC_MACID_VLD_8822B(__rx_desc) GET_RX_DESC_MACID_VLD(__rx_desc)
-#define GET_RX_DESC_TID_8822B(__rx_desc) GET_RX_DESC_TID(__rx_desc)
-#define GET_RX_DESC_EXT_SECTYPE_8822B(__rx_desc) \
- GET_RX_DESC_EXT_SECTYPE(__rx_desc)
-#define GET_RX_DESC_MACID_8822B(__rx_desc) GET_RX_DESC_MACID(__rx_desc)
-
-/*RXDESC_WORD2*/
-
-#define GET_RX_DESC_FCS_OK_8822B(__rx_desc) GET_RX_DESC_FCS_OK(__rx_desc)
-#define GET_RX_DESC_PPDU_CNT_8822B(__rx_desc) GET_RX_DESC_PPDU_CNT(__rx_desc)
-#define GET_RX_DESC_C2H_8822B(__rx_desc) GET_RX_DESC_C2H(__rx_desc)
-#define GET_RX_DESC_HWRSVD_8822B(__rx_desc) GET_RX_DESC_HWRSVD(__rx_desc)
-#define GET_RX_DESC_WLANHD_IV_LEN_8822B(__rx_desc) \
- GET_RX_DESC_WLANHD_IV_LEN(__rx_desc)
-#define GET_RX_DESC_RX_IS_QOS_8822B(__rx_desc) GET_RX_DESC_RX_IS_QOS(__rx_desc)
-#define GET_RX_DESC_FRAG_8822B(__rx_desc) GET_RX_DESC_FRAG(__rx_desc)
-#define GET_RX_DESC_SEQ_8822B(__rx_desc) GET_RX_DESC_SEQ(__rx_desc)
-
-/*RXDESC_WORD3*/
-
-#define GET_RX_DESC_MAGIC_WAKE_8822B(__rx_desc) \
- GET_RX_DESC_MAGIC_WAKE(__rx_desc)
-#define GET_RX_DESC_UNICAST_WAKE_8822B(__rx_desc) \
- GET_RX_DESC_UNICAST_WAKE(__rx_desc)
-#define GET_RX_DESC_PATTERN_MATCH_8822B(__rx_desc) \
- GET_RX_DESC_PATTERN_MATCH(__rx_desc)
-#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(__rx_desc) \
- GET_RX_DESC_RXPAYLOAD_MATCH(__rx_desc)
-#define GET_RX_DESC_RXPAYLOAD_ID_8822B(__rx_desc) \
- GET_RX_DESC_RXPAYLOAD_ID(__rx_desc)
-#define GET_RX_DESC_DMA_AGG_NUM_8822B(__rx_desc) \
- GET_RX_DESC_DMA_AGG_NUM(__rx_desc)
-#define GET_RX_DESC_BSSID_FIT_1_0_8822B(__rx_desc) \
- GET_RX_DESC_BSSID_FIT_1_0(__rx_desc)
-#define GET_RX_DESC_EOSP_8822B(__rx_desc) GET_RX_DESC_EOSP(__rx_desc)
-#define GET_RX_DESC_HTC_8822B(__rx_desc) GET_RX_DESC_HTC(__rx_desc)
-#define GET_RX_DESC_BSSID_FIT_4_2_8822B(__rx_desc) \
- GET_RX_DESC_BSSID_FIT_4_2(__rx_desc)
-#define GET_RX_DESC_RX_RATE_8822B(__rx_desc) GET_RX_DESC_RX_RATE(__rx_desc)
-
-/*RXDESC_WORD4*/
-
-#define GET_RX_DESC_A1_FIT_8822B(__rx_desc) GET_RX_DESC_A1_FIT(__rx_desc)
-#define GET_RX_DESC_MACID_RPT_BUFF_8822B(__rx_desc) \
- GET_RX_DESC_MACID_RPT_BUFF(__rx_desc)
-#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(__rx_desc) \
- GET_RX_DESC_RX_PRE_NDP_VLD(__rx_desc)
-#define GET_RX_DESC_RX_SCRAMBLER_8822B(__rx_desc) \
- GET_RX_DESC_RX_SCRAMBLER(__rx_desc)
-#define GET_RX_DESC_RX_EOF_8822B(__rx_desc) GET_RX_DESC_RX_EOF(__rx_desc)
-#define GET_RX_DESC_PATTERN_IDX_8822B(__rx_desc) \
- GET_RX_DESC_PATTERN_IDX(__rx_desc)
-
-/*RXDESC_WORD5*/
-
-#define GET_RX_DESC_TSFL_8822B(__rx_desc) GET_RX_DESC_TSFL(__rx_desc)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_RX_DESC_NIC_H_
-#define _HALMAC_RX_DESC_NIC_H_
-
-/*RXDESC_WORD0*/
-
-#define GET_RX_DESC_EOR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 30, 1)
-#define GET_RX_DESC_PHYPKTIDC(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x00, 28, 1)
-#define GET_RX_DESC_SWDEC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 27, 1)
-#define GET_RX_DESC_PHYST(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 26, 1)
-#define GET_RX_DESC_SHIFT(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 24, 2)
-#define GET_RX_DESC_QOS(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 23, 1)
-#define GET_RX_DESC_SECURITY(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x00, 20, 3)
-#define GET_RX_DESC_DRV_INFO_SIZE(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x00, 16, 4)
-#define GET_RX_DESC_ICV_ERR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 15, 1)
-#define GET_RX_DESC_CRC32(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 14, 1)
-#define GET_RX_DESC_PKT_LEN(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 0, 14)
-
-/*RXDESC_WORD1*/
-
-#define GET_RX_DESC_BC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 31, 1)
-#define GET_RX_DESC_MC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 30, 1)
-#define GET_RX_DESC_TY_PE(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 28, 2)
-#define GET_RX_DESC_MF(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 27, 1)
-#define GET_RX_DESC_MD(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 26, 1)
-#define GET_RX_DESC_PWR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 25, 1)
-#define GET_RX_DESC_PAM(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 24, 1)
-#define GET_RX_DESC_CHK_VLD(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 23, 1)
-#define GET_RX_DESC_RX_IS_TCP_UDP(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x04, 22, 1)
-#define GET_RX_DESC_RX_IPV(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 21, 1)
-#define GET_RX_DESC_CHKERR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 20, 1)
-#define GET_RX_DESC_PAGGR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 15, 1)
-#define GET_RX_DESC_RXID_MATCH(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x04, 14, 1)
-#define GET_RX_DESC_AMSDU(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 13, 1)
-#define GET_RX_DESC_MACID_VLD(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x04, 12, 1)
-#define GET_RX_DESC_TID(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 8, 4)
-
-#define GET_RX_DESC_EXT_SECTYPE(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x04, 7, 1)
-
-#define GET_RX_DESC_MACID(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 0, 7)
-
-/*RXDESC_WORD2*/
-
-#define GET_RX_DESC_FCS_OK(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 31, 1)
-
-#define GET_RX_DESC_PPDU_CNT(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x08, 29, 2)
-
-#define GET_RX_DESC_C2H(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 28, 1)
-#define GET_RX_DESC_HWRSVD(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 24, 4)
-#define GET_RX_DESC_WLANHD_IV_LEN(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x08, 18, 6)
-#define GET_RX_DESC_RX_IS_QOS(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x08, 16, 1)
-#define GET_RX_DESC_FRAG(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 12, 4)
-#define GET_RX_DESC_SEQ(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 0, 12)
-
-/*RXDESC_WORD3*/
-
-#define GET_RX_DESC_MAGIC_WAKE(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 31, 1)
-#define GET_RX_DESC_UNICAST_WAKE(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 30, 1)
-#define GET_RX_DESC_PATTERN_MATCH(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 29, 1)
-
-#define GET_RX_DESC_RXPAYLOAD_MATCH(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 28, 1)
-#define GET_RX_DESC_RXPAYLOAD_ID(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 24, 4)
-
-#define GET_RX_DESC_DMA_AGG_NUM(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 16, 8)
-#define GET_RX_DESC_BSSID_FIT_1_0(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 12, 2)
-#define GET_RX_DESC_EOSP(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 11, 1)
-#define GET_RX_DESC_HTC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 10, 1)
-
-#define GET_RX_DESC_BSSID_FIT_4_2(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 7, 3)
-
-#define GET_RX_DESC_RX_RATE(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 0, 7)
-
-/*RXDESC_WORD4*/
-
-#define GET_RX_DESC_A1_FIT(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x10, 24, 5)
-
-#define GET_RX_DESC_MACID_RPT_BUFF(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x10, 17, 7)
-#define GET_RX_DESC_RX_PRE_NDP_VLD(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x10, 16, 1)
-#define GET_RX_DESC_RX_SCRAMBLER(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x10, 9, 7)
-#define GET_RX_DESC_RX_EOF(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x10, 8, 1)
-
-#define GET_RX_DESC_PATTERN_IDX(__rx_desc) \
- LE_BITS_TO_4BYTE(__rx_desc + 0x10, 0, 8)
-
-/*RXDESC_WORD5*/
-
-#define GET_RX_DESC_TSFL(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x14, 0, 32)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __HALMAC_SDIO_REG_H__
-#define __HALMAC_SDIO_REG_H__
-
-/* SDIO CMD address mapping */
-
-#define HALMAC_SDIO_4BYTE_LEN_MASK 0x1FFF
-#define HALMAC_SDIO_LOCAL_MSK 0x0FFF
-#define HALMAC_WLAN_MAC_REG_MSK 0xFFFF
-#define HALMAC_WLAN_IOREG_MSK 0xFFFF
-
-/* Sdio address for SDIO Local Reg, TRX FIFO, MAC Reg */
-enum halmac_sdio_cmd_addr {
- HALMAC_SDIO_CMD_ADDR_SDIO_REG = 0,
- HALMAC_SDIO_CMD_ADDR_MAC_REG = 8,
- HALMAC_SDIO_CMD_ADDR_TXFF_HIGH = 4,
- HALMAC_SDIO_CMD_ADDR_TXFF_LOW = 6,
- HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL = 5,
- HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA = 7,
- HALMAC_SDIO_CMD_ADDR_RXFF = 7,
-};
-
-/* IO Bus domain address mapping */
-#define SDIO_LOCAL_OFFSET 0x10250000
-#define WLAN_IOREG_OFFSET 0x10260000
-#define FW_FIFO_OFFSET 0x10270000
-#define TX_HIQ_OFFSET 0x10310000
-#define TX_MIQ_OFFSET 0x10320000
-#define TX_LOQ_OFFSET 0x10330000
-#define TX_EXQ_OFFSET 0x10350000
-#define RX_RXOFF_OFFSET 0x10340000
-
-/* Get TX WLAN FIFO information in CMD53 addr */
-#define GET_WLAN_TXFF_DEVICE_ID(__cmd53_addr) \
- LE_BITS_TO_4BYTE((u32 *)__cmd53_addr, 13, 4)
-#define GET_WLAN_TXFF_PKT_SIZE(__cmd53_addr) \
- (LE_BITS_TO_4BYTE((u32 *)__cmd53_addr, 0, 13) << 2)
-
-#endif /* __HALMAC_SDIO_REG_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_TX_BD_CHIP_H_
-#define _HALMAC_TX_BD_CHIP_H_
-
-/*TXBD_DW0*/
-
-#define SET_TX_BD_OWN_8822B(__tx_bd, __value) SET_TX_BD_OWN(__tx_bd, __value)
-#define GET_TX_BD_OWN_8822B(__tx_bd) GET_TX_BD_OWN(__tx_bd)
-#define SET_TX_BD_PSB_8822B(__tx_bd, __value) SET_TX_BD_PSB(__tx_bd, __value)
-#define GET_TX_BD_PSB_8822B(__tx_bd) GET_TX_BD_PSB(__tx_bd)
-#define SET_TX_BD_TX_BUFF_SIZE0_8822B(__tx_bd, __value) \
- SET_TX_BD_TX_BUFF_SIZE0(__tx_bd, __value)
-#define GET_TX_BD_TX_BUFF_SIZE0_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE0(__tx_bd)
-
-/*TXBD_DW1*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__tx_bd, __value) \
- SET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd, __value)
-#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__tx_bd) \
- GET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd)
-
-/*TXBD_DW2*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__tx_bd, __value) \
- SET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd, __value)
-#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__tx_bd) \
- GET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd)
-
-/*TXBD_DW4*/
-
-#define SET_TX_BD_A1_8822B(__tx_bd, __value) SET_TX_BD_A1(__tx_bd, __value)
-#define GET_TX_BD_A1_8822B(__tx_bd) GET_TX_BD_A1(__tx_bd)
-#define SET_TX_BD_TX_BUFF_SIZE1_8822B(__tx_bd, __value) \
- SET_TX_BD_TX_BUFF_SIZE1(__tx_bd, __value)
-#define GET_TX_BD_TX_BUFF_SIZE1_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE1(__tx_bd)
-
-/*TXBD_DW5*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__tx_bd, __value) \
- SET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd, __value)
-#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__tx_bd) \
- GET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd)
-
-/*TXBD_DW6*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__tx_bd, __value) \
- SET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd, __value)
-#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__tx_bd) \
- GET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd)
-
-/*TXBD_DW8*/
-
-#define SET_TX_BD_A2_8822B(__tx_bd, __value) SET_TX_BD_A2(__tx_bd, __value)
-#define GET_TX_BD_A2_8822B(__tx_bd) GET_TX_BD_A2(__tx_bd)
-#define SET_TX_BD_TX_BUFF_SIZE2_8822B(__tx_bd, __value) \
- SET_TX_BD_TX_BUFF_SIZE2(__tx_bd, __value)
-#define GET_TX_BD_TX_BUFF_SIZE2_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE2(__tx_bd)
-
-/*TXBD_DW9*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__tx_bd, __value) \
- SET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd, __value)
-#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__tx_bd) \
- GET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd)
-
-/*TXBD_DW10*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__tx_bd, __value) \
- SET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd, __value)
-#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__tx_bd) \
- GET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd)
-
-/*TXBD_DW12*/
-
-#define SET_TX_BD_A3_8822B(__tx_bd, __value) SET_TX_BD_A3(__tx_bd, __value)
-#define GET_TX_BD_A3_8822B(__tx_bd) GET_TX_BD_A3(__tx_bd)
-#define SET_TX_BD_TX_BUFF_SIZE3_8822B(__tx_bd, __value) \
- SET_TX_BD_TX_BUFF_SIZE3(__tx_bd, __value)
-#define GET_TX_BD_TX_BUFF_SIZE3_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE3(__tx_bd)
-
-/*TXBD_DW13*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__tx_bd, __value) \
- SET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd, __value)
-#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__tx_bd) \
- GET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd)
-
-/*TXBD_DW14*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__tx_bd, __value) \
- SET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd, __value)
-#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__tx_bd) \
- GET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_TX_BD_NIC_H_
-#define _HALMAC_TX_BD_NIC_H_
-
-/*TXBD_DW0*/
-
-#define SET_TX_BD_OWN(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x00, 31, 1, __value)
-#define GET_TX_BD_OWN(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x00, 31, 1)
-#define SET_TX_BD_PSB(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x00, 16, 8, __value)
-#define GET_TX_BD_PSB(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x00, 16, 8)
-#define SET_TX_BD_TX_BUFF_SIZE0(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x00, 0, 16, __value)
-#define GET_TX_BD_TX_BUFF_SIZE0(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x00, 0, 16)
-
-/*TXBD_DW1*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x04, 0, 32, __value)
-#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd) \
- LE_BITS_TO_4BYTE(__tx_bd + 0x04, 0, 32)
-
-/*TXBD_DW2*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x08, 0, 32, __value)
-#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd) \
- LE_BITS_TO_4BYTE(__tx_bd + 0x08, 0, 32)
-
-/*TXBD_DW4*/
-
-#define SET_TX_BD_A1(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x10, 31, 1, __value)
-#define GET_TX_BD_A1(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x10, 31, 1)
-#define SET_TX_BD_TX_BUFF_SIZE1(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x10, 0, 16, __value)
-#define GET_TX_BD_TX_BUFF_SIZE1(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x10, 0, 16)
-
-/*TXBD_DW5*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x14, 0, 32, __value)
-#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd) \
- LE_BITS_TO_4BYTE(__tx_bd + 0x14, 0, 32)
-
-/*TXBD_DW6*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x18, 0, 32, __value)
-#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd) \
- LE_BITS_TO_4BYTE(__tx_bd + 0x18, 0, 32)
-
-/*TXBD_DW8*/
-
-#define SET_TX_BD_A2(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x20, 31, 1, __value)
-#define GET_TX_BD_A2(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x20, 31, 1)
-#define SET_TX_BD_TX_BUFF_SIZE2(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x20, 0, 16, __value)
-#define GET_TX_BD_TX_BUFF_SIZE2(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x20, 0, 16)
-
-/*TXBD_DW9*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x24, 0, 32, __value)
-#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd) \
- LE_BITS_TO_4BYTE(__tx_bd + 0x24, 0, 32)
-
-/*TXBD_DW10*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x28, 0, 32, __value)
-#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd) \
- LE_BITS_TO_4BYTE(__tx_bd + 0x28, 0, 32)
-
-/*TXBD_DW12*/
-
-#define SET_TX_BD_A3(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x30, 31, 1, __value)
-#define GET_TX_BD_A3(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x30, 31, 1)
-#define SET_TX_BD_TX_BUFF_SIZE3(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x30, 0, 16, __value)
-#define GET_TX_BD_TX_BUFF_SIZE3(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x30, 0, 16)
-
-/*TXBD_DW13*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x34, 0, 32, __value)
-#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd) \
- LE_BITS_TO_4BYTE(__tx_bd + 0x34, 0, 32)
-
-/*TXBD_DW14*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_bd + 0x38, 0, 32, __value)
-#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd) \
- LE_BITS_TO_4BYTE(__tx_bd + 0x38, 0, 32)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_TX_DESC_CHIP_H_
-#define _HALMAC_TX_DESC_CHIP_H_
-
-/*TXDESC_WORD0*/
-
-#define SET_TX_DESC_DISQSELSEQ_8822B(__tx_desc, __value) \
- SET_TX_DESC_DISQSELSEQ(__tx_desc, __value)
-#define GET_TX_DESC_DISQSELSEQ_8822B(__tx_desc) \
- GET_TX_DESC_DISQSELSEQ(__tx_desc)
-#define SET_TX_DESC_GF_8822B(__tx_desc, __value) \
- SET_TX_DESC_GF(__tx_desc, __value)
-#define GET_TX_DESC_GF_8822B(__tx_desc) GET_TX_DESC_GF(__tx_desc)
-#define SET_TX_DESC_NO_ACM_8822B(__tx_desc, __value) \
- SET_TX_DESC_NO_ACM(__tx_desc, __value)
-#define GET_TX_DESC_NO_ACM_8822B(__tx_desc) GET_TX_DESC_NO_ACM(__tx_desc)
-#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__tx_desc, __value) \
- SET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc, __value)
-#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__tx_desc) \
- GET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc)
-#define SET_TX_DESC_AMSDU_PAD_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_AMSDU_PAD_EN(__tx_desc, __value)
-#define GET_TX_DESC_AMSDU_PAD_EN_8822B(__tx_desc) \
- GET_TX_DESC_AMSDU_PAD_EN(__tx_desc)
-#define SET_TX_DESC_LS_8822B(__tx_desc, __value) \
- SET_TX_DESC_LS(__tx_desc, __value)
-#define GET_TX_DESC_LS_8822B(__tx_desc) GET_TX_DESC_LS(__tx_desc)
-#define SET_TX_DESC_HTC_8822B(__tx_desc, __value) \
- SET_TX_DESC_HTC(__tx_desc, __value)
-#define GET_TX_DESC_HTC_8822B(__tx_desc) GET_TX_DESC_HTC(__tx_desc)
-#define SET_TX_DESC_BMC_8822B(__tx_desc, __value) \
- SET_TX_DESC_BMC(__tx_desc, __value)
-#define GET_TX_DESC_BMC_8822B(__tx_desc) GET_TX_DESC_BMC(__tx_desc)
-#define SET_TX_DESC_OFFSET_8822B(__tx_desc, __value) \
- SET_TX_DESC_OFFSET(__tx_desc, __value)
-#define GET_TX_DESC_OFFSET_8822B(__tx_desc) GET_TX_DESC_OFFSET(__tx_desc)
-#define SET_TX_DESC_TXPKTSIZE_8822B(__tx_desc, __value) \
- SET_TX_DESC_TXPKTSIZE(__tx_desc, __value)
-#define GET_TX_DESC_TXPKTSIZE_8822B(__tx_desc) GET_TX_DESC_TXPKTSIZE(__tx_desc)
-
-/*TXDESC_WORD1*/
-
-#define SET_TX_DESC_MOREDATA_8822B(__tx_desc, __value) \
- SET_TX_DESC_MOREDATA(__tx_desc, __value)
-#define GET_TX_DESC_MOREDATA_8822B(__tx_desc) GET_TX_DESC_MOREDATA(__tx_desc)
-#define SET_TX_DESC_PKT_OFFSET_8822B(__tx_desc, __value) \
- SET_TX_DESC_PKT_OFFSET(__tx_desc, __value)
-#define GET_TX_DESC_PKT_OFFSET_8822B(__tx_desc) \
- GET_TX_DESC_PKT_OFFSET(__tx_desc)
-#define SET_TX_DESC_SEC_TYPE_8822B(__tx_desc, __value) \
- SET_TX_DESC_SEC_TYPE(__tx_desc, __value)
-#define GET_TX_DESC_SEC_TYPE_8822B(__tx_desc) GET_TX_DESC_SEC_TYPE(__tx_desc)
-#define SET_TX_DESC_EN_DESC_ID_8822B(__tx_desc, __value) \
- SET_TX_DESC_EN_DESC_ID(__tx_desc, __value)
-#define GET_TX_DESC_EN_DESC_ID_8822B(__tx_desc) \
- GET_TX_DESC_EN_DESC_ID(__tx_desc)
-#define SET_TX_DESC_RATE_ID_8822B(__tx_desc, __value) \
- SET_TX_DESC_RATE_ID(__tx_desc, __value)
-#define GET_TX_DESC_RATE_ID_8822B(__tx_desc) GET_TX_DESC_RATE_ID(__tx_desc)
-#define SET_TX_DESC_PIFS_8822B(__tx_desc, __value) \
- SET_TX_DESC_PIFS(__tx_desc, __value)
-#define GET_TX_DESC_PIFS_8822B(__tx_desc) GET_TX_DESC_PIFS(__tx_desc)
-#define SET_TX_DESC_LSIG_TXOP_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_LSIG_TXOP_EN(__tx_desc, __value)
-#define GET_TX_DESC_LSIG_TXOP_EN_8822B(__tx_desc) \
- GET_TX_DESC_LSIG_TXOP_EN(__tx_desc)
-#define SET_TX_DESC_RD_NAV_EXT_8822B(__tx_desc, __value) \
- SET_TX_DESC_RD_NAV_EXT(__tx_desc, __value)
-#define GET_TX_DESC_RD_NAV_EXT_8822B(__tx_desc) \
- GET_TX_DESC_RD_NAV_EXT(__tx_desc)
-#define SET_TX_DESC_QSEL_8822B(__tx_desc, __value) \
- SET_TX_DESC_QSEL(__tx_desc, __value)
-#define GET_TX_DESC_QSEL_8822B(__tx_desc) GET_TX_DESC_QSEL(__tx_desc)
-#define SET_TX_DESC_MACID_8822B(__tx_desc, __value) \
- SET_TX_DESC_MACID(__tx_desc, __value)
-#define GET_TX_DESC_MACID_8822B(__tx_desc) GET_TX_DESC_MACID(__tx_desc)
-
-/*TXDESC_WORD2*/
-
-#define SET_TX_DESC_HW_AES_IV_8822B(__tx_desc, __value) \
- SET_TX_DESC_HW_AES_IV(__tx_desc, __value)
-#define GET_TX_DESC_HW_AES_IV_8822B(__tx_desc) GET_TX_DESC_HW_AES_IV(__tx_desc)
-#define SET_TX_DESC_FTM_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_FTM_EN(__tx_desc, __value)
-#define GET_TX_DESC_FTM_EN_8822B(__tx_desc) GET_TX_DESC_FTM_EN(__tx_desc)
-#define SET_TX_DESC_G_ID_8822B(__tx_desc, __value) \
- SET_TX_DESC_G_ID(__tx_desc, __value)
-#define GET_TX_DESC_G_ID_8822B(__tx_desc) GET_TX_DESC_G_ID(__tx_desc)
-#define SET_TX_DESC_BT_NULL_8822B(__tx_desc, __value) \
- SET_TX_DESC_BT_NULL(__tx_desc, __value)
-#define GET_TX_DESC_BT_NULL_8822B(__tx_desc) GET_TX_DESC_BT_NULL(__tx_desc)
-#define SET_TX_DESC_AMPDU_DENSITY_8822B(__tx_desc, __value) \
- SET_TX_DESC_AMPDU_DENSITY(__tx_desc, __value)
-#define GET_TX_DESC_AMPDU_DENSITY_8822B(__tx_desc) \
- GET_TX_DESC_AMPDU_DENSITY(__tx_desc)
-#define SET_TX_DESC_SPE_RPT_8822B(__tx_desc, __value) \
- SET_TX_DESC_SPE_RPT(__tx_desc, __value)
-#define GET_TX_DESC_SPE_RPT_8822B(__tx_desc) GET_TX_DESC_SPE_RPT(__tx_desc)
-#define SET_TX_DESC_RAW_8822B(__tx_desc, __value) \
- SET_TX_DESC_RAW(__tx_desc, __value)
-#define GET_TX_DESC_RAW_8822B(__tx_desc) GET_TX_DESC_RAW(__tx_desc)
-#define SET_TX_DESC_MOREFRAG_8822B(__tx_desc, __value) \
- SET_TX_DESC_MOREFRAG(__tx_desc, __value)
-#define GET_TX_DESC_MOREFRAG_8822B(__tx_desc) GET_TX_DESC_MOREFRAG(__tx_desc)
-#define SET_TX_DESC_BK_8822B(__tx_desc, __value) \
- SET_TX_DESC_BK(__tx_desc, __value)
-#define GET_TX_DESC_BK_8822B(__tx_desc) GET_TX_DESC_BK(__tx_desc)
-#define SET_TX_DESC_NULL_1_8822B(__tx_desc, __value) \
- SET_TX_DESC_NULL_1(__tx_desc, __value)
-#define GET_TX_DESC_NULL_1_8822B(__tx_desc) GET_TX_DESC_NULL_1(__tx_desc)
-#define SET_TX_DESC_NULL_0_8822B(__tx_desc, __value) \
- SET_TX_DESC_NULL_0(__tx_desc, __value)
-#define GET_TX_DESC_NULL_0_8822B(__tx_desc) GET_TX_DESC_NULL_0(__tx_desc)
-#define SET_TX_DESC_RDG_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_RDG_EN(__tx_desc, __value)
-#define GET_TX_DESC_RDG_EN_8822B(__tx_desc) GET_TX_DESC_RDG_EN(__tx_desc)
-#define SET_TX_DESC_AGG_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_AGG_EN(__tx_desc, __value)
-#define GET_TX_DESC_AGG_EN_8822B(__tx_desc) GET_TX_DESC_AGG_EN(__tx_desc)
-#define SET_TX_DESC_CCA_RTS_8822B(__tx_desc, __value) \
- SET_TX_DESC_CCA_RTS(__tx_desc, __value)
-#define GET_TX_DESC_CCA_RTS_8822B(__tx_desc) GET_TX_DESC_CCA_RTS(__tx_desc)
-#define SET_TX_DESC_TRI_FRAME_8822B(__tx_desc, __value) \
- SET_TX_DESC_TRI_FRAME(__tx_desc, __value)
-#define GET_TX_DESC_TRI_FRAME_8822B(__tx_desc) GET_TX_DESC_TRI_FRAME(__tx_desc)
-#define SET_TX_DESC_P_AID_8822B(__tx_desc, __value) \
- SET_TX_DESC_P_AID(__tx_desc, __value)
-#define GET_TX_DESC_P_AID_8822B(__tx_desc) GET_TX_DESC_P_AID(__tx_desc)
-
-/*TXDESC_WORD3*/
-
-#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(__tx_desc, __value) \
- SET_TX_DESC_AMPDU_MAX_TIME(__tx_desc, __value)
-#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(__tx_desc) \
- GET_TX_DESC_AMPDU_MAX_TIME(__tx_desc)
-#define SET_TX_DESC_NDPA_8822B(__tx_desc, __value) \
- SET_TX_DESC_NDPA(__tx_desc, __value)
-#define GET_TX_DESC_NDPA_8822B(__tx_desc) GET_TX_DESC_NDPA(__tx_desc)
-#define SET_TX_DESC_MAX_AGG_NUM_8822B(__tx_desc, __value) \
- SET_TX_DESC_MAX_AGG_NUM(__tx_desc, __value)
-#define GET_TX_DESC_MAX_AGG_NUM_8822B(__tx_desc) \
- GET_TX_DESC_MAX_AGG_NUM(__tx_desc)
-#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_USE_MAX_TIME_EN(__tx_desc, __value)
-#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(__tx_desc) \
- GET_TX_DESC_USE_MAX_TIME_EN(__tx_desc)
-#define SET_TX_DESC_NAVUSEHDR_8822B(__tx_desc, __value) \
- SET_TX_DESC_NAVUSEHDR(__tx_desc, __value)
-#define GET_TX_DESC_NAVUSEHDR_8822B(__tx_desc) GET_TX_DESC_NAVUSEHDR(__tx_desc)
-#define SET_TX_DESC_CHK_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_CHK_EN(__tx_desc, __value)
-#define GET_TX_DESC_CHK_EN_8822B(__tx_desc) GET_TX_DESC_CHK_EN(__tx_desc)
-#define SET_TX_DESC_HW_RTS_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_HW_RTS_EN(__tx_desc, __value)
-#define GET_TX_DESC_HW_RTS_EN_8822B(__tx_desc) GET_TX_DESC_HW_RTS_EN(__tx_desc)
-#define SET_TX_DESC_RTSEN_8822B(__tx_desc, __value) \
- SET_TX_DESC_RTSEN(__tx_desc, __value)
-#define GET_TX_DESC_RTSEN_8822B(__tx_desc) GET_TX_DESC_RTSEN(__tx_desc)
-#define SET_TX_DESC_CTS2SELF_8822B(__tx_desc, __value) \
- SET_TX_DESC_CTS2SELF(__tx_desc, __value)
-#define GET_TX_DESC_CTS2SELF_8822B(__tx_desc) GET_TX_DESC_CTS2SELF(__tx_desc)
-#define SET_TX_DESC_DISDATAFB_8822B(__tx_desc, __value) \
- SET_TX_DESC_DISDATAFB(__tx_desc, __value)
-#define GET_TX_DESC_DISDATAFB_8822B(__tx_desc) GET_TX_DESC_DISDATAFB(__tx_desc)
-#define SET_TX_DESC_DISRTSFB_8822B(__tx_desc, __value) \
- SET_TX_DESC_DISRTSFB(__tx_desc, __value)
-#define GET_TX_DESC_DISRTSFB_8822B(__tx_desc) GET_TX_DESC_DISRTSFB(__tx_desc)
-#define SET_TX_DESC_USE_RATE_8822B(__tx_desc, __value) \
- SET_TX_DESC_USE_RATE(__tx_desc, __value)
-#define GET_TX_DESC_USE_RATE_8822B(__tx_desc) GET_TX_DESC_USE_RATE(__tx_desc)
-#define SET_TX_DESC_HW_SSN_SEL_8822B(__tx_desc, __value) \
- SET_TX_DESC_HW_SSN_SEL(__tx_desc, __value)
-#define GET_TX_DESC_HW_SSN_SEL_8822B(__tx_desc) \
- GET_TX_DESC_HW_SSN_SEL(__tx_desc)
-#define SET_TX_DESC_WHEADER_LEN_8822B(__tx_desc, __value) \
- SET_TX_DESC_WHEADER_LEN(__tx_desc, __value)
-#define GET_TX_DESC_WHEADER_LEN_8822B(__tx_desc) \
- GET_TX_DESC_WHEADER_LEN(__tx_desc)
-
-/*TXDESC_WORD4*/
-
-#define SET_TX_DESC_PCTS_MASK_IDX_8822B(__tx_desc, __value) \
- SET_TX_DESC_PCTS_MASK_IDX(__tx_desc, __value)
-#define GET_TX_DESC_PCTS_MASK_IDX_8822B(__tx_desc) \
- GET_TX_DESC_PCTS_MASK_IDX(__tx_desc)
-#define SET_TX_DESC_PCTS_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_PCTS_EN(__tx_desc, __value)
-#define GET_TX_DESC_PCTS_EN_8822B(__tx_desc) GET_TX_DESC_PCTS_EN(__tx_desc)
-#define SET_TX_DESC_RTSRATE_8822B(__tx_desc, __value) \
- SET_TX_DESC_RTSRATE(__tx_desc, __value)
-#define GET_TX_DESC_RTSRATE_8822B(__tx_desc) GET_TX_DESC_RTSRATE(__tx_desc)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__tx_desc, __value) \
- SET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc, __value)
-#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__tx_desc) \
- GET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc)
-#define SET_TX_DESC_RTY_LMT_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_RTY_LMT_EN(__tx_desc, __value)
-#define GET_TX_DESC_RTY_LMT_EN_8822B(__tx_desc) \
- GET_TX_DESC_RTY_LMT_EN(__tx_desc)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__tx_desc, __value) \
- SET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc, __value)
-#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__tx_desc) \
- GET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__tx_desc, __value) \
- SET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc, __value)
-#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__tx_desc) \
- GET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc)
-#define SET_TX_DESC_TRY_RATE_8822B(__tx_desc, __value) \
- SET_TX_DESC_TRY_RATE(__tx_desc, __value)
-#define GET_TX_DESC_TRY_RATE_8822B(__tx_desc) GET_TX_DESC_TRY_RATE(__tx_desc)
-#define SET_TX_DESC_DATARATE_8822B(__tx_desc, __value) \
- SET_TX_DESC_DATARATE(__tx_desc, __value)
-#define GET_TX_DESC_DATARATE_8822B(__tx_desc) GET_TX_DESC_DATARATE(__tx_desc)
-
-/*TXDESC_WORD5*/
-
-#define SET_TX_DESC_POLLUTED_8822B(__tx_desc, __value) \
- SET_TX_DESC_POLLUTED(__tx_desc, __value)
-#define GET_TX_DESC_POLLUTED_8822B(__tx_desc) GET_TX_DESC_POLLUTED(__tx_desc)
-#define SET_TX_DESC_TXPWR_OFSET_8822B(__tx_desc, __value) \
- SET_TX_DESC_TXPWR_OFSET(__tx_desc, __value)
-#define GET_TX_DESC_TXPWR_OFSET_8822B(__tx_desc) \
- GET_TX_DESC_TXPWR_OFSET(__tx_desc)
-#define SET_TX_DESC_TX_ANT_8822B(__tx_desc, __value) \
- SET_TX_DESC_TX_ANT(__tx_desc, __value)
-#define GET_TX_DESC_TX_ANT_8822B(__tx_desc) GET_TX_DESC_TX_ANT(__tx_desc)
-#define SET_TX_DESC_PORT_ID_8822B(__tx_desc, __value) \
- SET_TX_DESC_PORT_ID(__tx_desc, __value)
-#define GET_TX_DESC_PORT_ID_8822B(__tx_desc) GET_TX_DESC_PORT_ID(__tx_desc)
-#define SET_TX_DESC_MULTIPLE_PORT_8822B(__tx_desc, __value) \
- SET_TX_DESC_MULTIPLE_PORT(__tx_desc, __value)
-#define GET_TX_DESC_MULTIPLE_PORT_8822B(__tx_desc) \
- GET_TX_DESC_MULTIPLE_PORT(__tx_desc)
-#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc, __value)
-#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__tx_desc) \
- GET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc)
-#define SET_TX_DESC_RTS_SC_8822B(__tx_desc, __value) \
- SET_TX_DESC_RTS_SC(__tx_desc, __value)
-#define GET_TX_DESC_RTS_SC_8822B(__tx_desc) GET_TX_DESC_RTS_SC(__tx_desc)
-#define SET_TX_DESC_RTS_SHORT_8822B(__tx_desc, __value) \
- SET_TX_DESC_RTS_SHORT(__tx_desc, __value)
-#define GET_TX_DESC_RTS_SHORT_8822B(__tx_desc) GET_TX_DESC_RTS_SHORT(__tx_desc)
-#define SET_TX_DESC_VCS_STBC_8822B(__tx_desc, __value) \
- SET_TX_DESC_VCS_STBC(__tx_desc, __value)
-#define GET_TX_DESC_VCS_STBC_8822B(__tx_desc) GET_TX_DESC_VCS_STBC(__tx_desc)
-#define SET_TX_DESC_DATA_STBC_8822B(__tx_desc, __value) \
- SET_TX_DESC_DATA_STBC(__tx_desc, __value)
-#define GET_TX_DESC_DATA_STBC_8822B(__tx_desc) GET_TX_DESC_DATA_STBC(__tx_desc)
-#define SET_TX_DESC_DATA_LDPC_8822B(__tx_desc, __value) \
- SET_TX_DESC_DATA_LDPC(__tx_desc, __value)
-#define GET_TX_DESC_DATA_LDPC_8822B(__tx_desc) GET_TX_DESC_DATA_LDPC(__tx_desc)
-#define SET_TX_DESC_DATA_BW_8822B(__tx_desc, __value) \
- SET_TX_DESC_DATA_BW(__tx_desc, __value)
-#define GET_TX_DESC_DATA_BW_8822B(__tx_desc) GET_TX_DESC_DATA_BW(__tx_desc)
-#define SET_TX_DESC_DATA_SHORT_8822B(__tx_desc, __value) \
- SET_TX_DESC_DATA_SHORT(__tx_desc, __value)
-#define GET_TX_DESC_DATA_SHORT_8822B(__tx_desc) \
- GET_TX_DESC_DATA_SHORT(__tx_desc)
-#define SET_TX_DESC_DATA_SC_8822B(__tx_desc, __value) \
- SET_TX_DESC_DATA_SC(__tx_desc, __value)
-#define GET_TX_DESC_DATA_SC_8822B(__tx_desc) GET_TX_DESC_DATA_SC(__tx_desc)
-
-/*TXDESC_WORD6*/
-
-#define SET_TX_DESC_ANTSEL_D_8822B(__tx_desc, __value) \
- SET_TX_DESC_ANTSEL_D(__tx_desc, __value)
-#define GET_TX_DESC_ANTSEL_D_8822B(__tx_desc) GET_TX_DESC_ANTSEL_D(__tx_desc)
-#define SET_TX_DESC_ANT_MAPD_8822B(__tx_desc, __value) \
- SET_TX_DESC_ANT_MAPD(__tx_desc, __value)
-#define GET_TX_DESC_ANT_MAPD_8822B(__tx_desc) GET_TX_DESC_ANT_MAPD(__tx_desc)
-#define SET_TX_DESC_ANT_MAPC_8822B(__tx_desc, __value) \
- SET_TX_DESC_ANT_MAPC(__tx_desc, __value)
-#define GET_TX_DESC_ANT_MAPC_8822B(__tx_desc) GET_TX_DESC_ANT_MAPC(__tx_desc)
-#define SET_TX_DESC_ANT_MAPB_8822B(__tx_desc, __value) \
- SET_TX_DESC_ANT_MAPB(__tx_desc, __value)
-#define GET_TX_DESC_ANT_MAPB_8822B(__tx_desc) GET_TX_DESC_ANT_MAPB(__tx_desc)
-#define SET_TX_DESC_ANT_MAPA_8822B(__tx_desc, __value) \
- SET_TX_DESC_ANT_MAPA(__tx_desc, __value)
-#define GET_TX_DESC_ANT_MAPA_8822B(__tx_desc) GET_TX_DESC_ANT_MAPA(__tx_desc)
-#define SET_TX_DESC_ANTSEL_C_8822B(__tx_desc, __value) \
- SET_TX_DESC_ANTSEL_C(__tx_desc, __value)
-#define GET_TX_DESC_ANTSEL_C_8822B(__tx_desc) GET_TX_DESC_ANTSEL_C(__tx_desc)
-#define SET_TX_DESC_ANTSEL_B_8822B(__tx_desc, __value) \
- SET_TX_DESC_ANTSEL_B(__tx_desc, __value)
-#define GET_TX_DESC_ANTSEL_B_8822B(__tx_desc) GET_TX_DESC_ANTSEL_B(__tx_desc)
-#define SET_TX_DESC_ANTSEL_A_8822B(__tx_desc, __value) \
- SET_TX_DESC_ANTSEL_A(__tx_desc, __value)
-#define GET_TX_DESC_ANTSEL_A_8822B(__tx_desc) GET_TX_DESC_ANTSEL_A(__tx_desc)
-#define SET_TX_DESC_MBSSID_8822B(__tx_desc, __value) \
- SET_TX_DESC_MBSSID(__tx_desc, __value)
-#define GET_TX_DESC_MBSSID_8822B(__tx_desc) GET_TX_DESC_MBSSID(__tx_desc)
-#define SET_TX_DESC_SW_DEFINE_8822B(__tx_desc, __value) \
- SET_TX_DESC_SW_DEFINE(__tx_desc, __value)
-#define GET_TX_DESC_SW_DEFINE_8822B(__tx_desc) GET_TX_DESC_SW_DEFINE(__tx_desc)
-
-/*TXDESC_WORD7*/
-
-#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(__tx_desc, __value) \
- SET_TX_DESC_DMA_TXAGG_NUM(__tx_desc, __value)
-#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(__tx_desc) \
- GET_TX_DESC_DMA_TXAGG_NUM(__tx_desc)
-#define SET_TX_DESC_FINAL_DATA_RATE_8822B(__tx_desc, __value) \
- SET_TX_DESC_FINAL_DATA_RATE(__tx_desc, __value)
-#define GET_TX_DESC_FINAL_DATA_RATE_8822B(__tx_desc) \
- GET_TX_DESC_FINAL_DATA_RATE(__tx_desc)
-#define SET_TX_DESC_NTX_MAP_8822B(__tx_desc, __value) \
- SET_TX_DESC_NTX_MAP(__tx_desc, __value)
-#define GET_TX_DESC_NTX_MAP_8822B(__tx_desc) GET_TX_DESC_NTX_MAP(__tx_desc)
-#define SET_TX_DESC_TX_BUFF_SIZE_8822B(__tx_desc, __value) \
- SET_TX_DESC_TX_BUFF_SIZE(__tx_desc, __value)
-#define GET_TX_DESC_TX_BUFF_SIZE_8822B(__tx_desc) \
- GET_TX_DESC_TX_BUFF_SIZE(__tx_desc)
-#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(__tx_desc, __value) \
- SET_TX_DESC_TXDESC_CHECKSUM(__tx_desc, __value)
-#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(__tx_desc) \
- GET_TX_DESC_TXDESC_CHECKSUM(__tx_desc)
-#define SET_TX_DESC_TIMESTAMP_8822B(__tx_desc, __value) \
- SET_TX_DESC_TIMESTAMP(__tx_desc, __value)
-#define GET_TX_DESC_TIMESTAMP_8822B(__tx_desc) GET_TX_DESC_TIMESTAMP(__tx_desc)
-
-/*TXDESC_WORD8*/
-
-#define SET_TX_DESC_TXWIFI_CP_8822B(__tx_desc, __value) \
- SET_TX_DESC_TXWIFI_CP(__tx_desc, __value)
-#define GET_TX_DESC_TXWIFI_CP_8822B(__tx_desc) GET_TX_DESC_TXWIFI_CP(__tx_desc)
-#define SET_TX_DESC_MAC_CP_8822B(__tx_desc, __value) \
- SET_TX_DESC_MAC_CP(__tx_desc, __value)
-#define GET_TX_DESC_MAC_CP_8822B(__tx_desc) GET_TX_DESC_MAC_CP(__tx_desc)
-#define SET_TX_DESC_STW_PKTRE_DIS_8822B(__tx_desc, __value) \
- SET_TX_DESC_STW_PKTRE_DIS(__tx_desc, __value)
-#define GET_TX_DESC_STW_PKTRE_DIS_8822B(__tx_desc) \
- GET_TX_DESC_STW_PKTRE_DIS(__tx_desc)
-#define SET_TX_DESC_STW_RB_DIS_8822B(__tx_desc, __value) \
- SET_TX_DESC_STW_RB_DIS(__tx_desc, __value)
-#define GET_TX_DESC_STW_RB_DIS_8822B(__tx_desc) \
- GET_TX_DESC_STW_RB_DIS(__tx_desc)
-#define SET_TX_DESC_STW_RATE_DIS_8822B(__tx_desc, __value) \
- SET_TX_DESC_STW_RATE_DIS(__tx_desc, __value)
-#define GET_TX_DESC_STW_RATE_DIS_8822B(__tx_desc) \
- GET_TX_DESC_STW_RATE_DIS(__tx_desc)
-#define SET_TX_DESC_STW_ANT_DIS_8822B(__tx_desc, __value) \
- SET_TX_DESC_STW_ANT_DIS(__tx_desc, __value)
-#define GET_TX_DESC_STW_ANT_DIS_8822B(__tx_desc) \
- GET_TX_DESC_STW_ANT_DIS(__tx_desc)
-#define SET_TX_DESC_STW_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_STW_EN(__tx_desc, __value)
-#define GET_TX_DESC_STW_EN_8822B(__tx_desc) GET_TX_DESC_STW_EN(__tx_desc)
-#define SET_TX_DESC_SMH_EN_8822B(__tx_desc, __value) \
- SET_TX_DESC_SMH_EN(__tx_desc, __value)
-#define GET_TX_DESC_SMH_EN_8822B(__tx_desc) GET_TX_DESC_SMH_EN(__tx_desc)
-#define SET_TX_DESC_TAILPAGE_L_8822B(__tx_desc, __value) \
- SET_TX_DESC_TAILPAGE_L(__tx_desc, __value)
-#define GET_TX_DESC_TAILPAGE_L_8822B(__tx_desc) \
- GET_TX_DESC_TAILPAGE_L(__tx_desc)
-#define SET_TX_DESC_SDIO_DMASEQ_8822B(__tx_desc, __value) \
- SET_TX_DESC_SDIO_DMASEQ(__tx_desc, __value)
-#define GET_TX_DESC_SDIO_DMASEQ_8822B(__tx_desc) \
- GET_TX_DESC_SDIO_DMASEQ(__tx_desc)
-#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(__tx_desc, __value) \
- SET_TX_DESC_NEXTHEADPAGE_L(__tx_desc, __value)
-#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(__tx_desc) \
- GET_TX_DESC_NEXTHEADPAGE_L(__tx_desc)
-#define SET_TX_DESC_EN_HWSEQ_8822B(__tx_desc, __value) \
- SET_TX_DESC_EN_HWSEQ(__tx_desc, __value)
-#define GET_TX_DESC_EN_HWSEQ_8822B(__tx_desc) GET_TX_DESC_EN_HWSEQ(__tx_desc)
-#define SET_TX_DESC_EN_HWEXSEQ_8822B(__tx_desc, __value) \
- SET_TX_DESC_EN_HWEXSEQ(__tx_desc, __value)
-#define GET_TX_DESC_EN_HWEXSEQ_8822B(__tx_desc) \
- GET_TX_DESC_EN_HWEXSEQ(__tx_desc)
-#define SET_TX_DESC_DATA_RC_8822B(__tx_desc, __value) \
- SET_TX_DESC_DATA_RC(__tx_desc, __value)
-#define GET_TX_DESC_DATA_RC_8822B(__tx_desc) GET_TX_DESC_DATA_RC(__tx_desc)
-#define SET_TX_DESC_BAR_RTY_TH_8822B(__tx_desc, __value) \
- SET_TX_DESC_BAR_RTY_TH(__tx_desc, __value)
-#define GET_TX_DESC_BAR_RTY_TH_8822B(__tx_desc) \
- GET_TX_DESC_BAR_RTY_TH(__tx_desc)
-#define SET_TX_DESC_RTS_RC_8822B(__tx_desc, __value) \
- SET_TX_DESC_RTS_RC(__tx_desc, __value)
-#define GET_TX_DESC_RTS_RC_8822B(__tx_desc) GET_TX_DESC_RTS_RC(__tx_desc)
-
-/*TXDESC_WORD9*/
-
-#define SET_TX_DESC_TAILPAGE_H_8822B(__tx_desc, __value) \
- SET_TX_DESC_TAILPAGE_H(__tx_desc, __value)
-#define GET_TX_DESC_TAILPAGE_H_8822B(__tx_desc) \
- GET_TX_DESC_TAILPAGE_H(__tx_desc)
-#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(__tx_desc, __value) \
- SET_TX_DESC_NEXTHEADPAGE_H(__tx_desc, __value)
-#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(__tx_desc) \
- GET_TX_DESC_NEXTHEADPAGE_H(__tx_desc)
-#define SET_TX_DESC_SW_SEQ_8822B(__tx_desc, __value) \
- SET_TX_DESC_SW_SEQ(__tx_desc, __value)
-#define GET_TX_DESC_SW_SEQ_8822B(__tx_desc) GET_TX_DESC_SW_SEQ(__tx_desc)
-#define SET_TX_DESC_TXBF_PATH_8822B(__tx_desc, __value) \
- SET_TX_DESC_TXBF_PATH(__tx_desc, __value)
-#define GET_TX_DESC_TXBF_PATH_8822B(__tx_desc) GET_TX_DESC_TXBF_PATH(__tx_desc)
-#define SET_TX_DESC_PADDING_LEN_8822B(__tx_desc, __value) \
- SET_TX_DESC_PADDING_LEN(__tx_desc, __value)
-#define GET_TX_DESC_PADDING_LEN_8822B(__tx_desc) \
- GET_TX_DESC_PADDING_LEN(__tx_desc)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__tx_desc, __value) \
- SET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc, __value)
-#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__tx_desc) \
- GET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc)
-
-/*WORD10*/
-
-#define SET_TX_DESC_MU_DATARATE_8822B(__tx_desc, __value) \
- SET_TX_DESC_MU_DATARATE(__tx_desc, __value)
-#define GET_TX_DESC_MU_DATARATE_8822B(__tx_desc) \
- GET_TX_DESC_MU_DATARATE(__tx_desc)
-#define SET_TX_DESC_MU_RC_8822B(__tx_desc, __value) \
- SET_TX_DESC_MU_RC(__tx_desc, __value)
-#define GET_TX_DESC_MU_RC_8822B(__tx_desc) GET_TX_DESC_MU_RC(__tx_desc)
-#define SET_TX_DESC_SND_PKT_SEL_8822B(__tx_desc, __value) \
- SET_TX_DESC_SND_PKT_SEL(__tx_desc, __value)
-#define GET_TX_DESC_SND_PKT_SEL_8822B(__tx_desc) \
- GET_TX_DESC_SND_PKT_SEL(__tx_desc)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_TX_DESC_NIC_H_
-#define _HALMAC_TX_DESC_NIC_H_
-
-/*TXDESC_WORD0*/
-
-#define SET_TX_DESC_DISQSELSEQ(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 31, 1, __value)
-#define GET_TX_DESC_DISQSELSEQ(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x00, 31, 1)
-
-#define SET_TX_DESC_GF(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 30, 1, __value)
-#define GET_TX_DESC_GF(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 30, 1)
-#define SET_TX_DESC_NO_ACM(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 29, 1, __value)
-#define GET_TX_DESC_NO_ACM(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 29, 1)
-
-#define SET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 28, 1, __value)
-#define GET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x00, 28, 1)
-
-#define SET_TX_DESC_AMSDU_PAD_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 27, 1, __value)
-#define GET_TX_DESC_AMSDU_PAD_EN(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x00, 27, 1)
-
-#define SET_TX_DESC_LS(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 26, 1, __value)
-#define GET_TX_DESC_LS(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 26, 1)
-#define SET_TX_DESC_HTC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 25, 1, __value)
-#define GET_TX_DESC_HTC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 25, 1)
-#define SET_TX_DESC_BMC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 24, 1, __value)
-#define GET_TX_DESC_BMC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 24, 1)
-#define SET_TX_DESC_OFFSET(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 16, 8, __value)
-#define GET_TX_DESC_OFFSET(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 16, 8)
-#define SET_TX_DESC_TXPKTSIZE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 0, 16, __value)
-#define GET_TX_DESC_TXPKTSIZE(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x00, 0, 16)
-
-/*TXDESC_WORD1*/
-
-#define SET_TX_DESC_MOREDATA(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 29, 1, __value)
-#define GET_TX_DESC_MOREDATA(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x04, 29, 1)
-#define SET_TX_DESC_PKT_OFFSET(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 24, 5, __value)
-#define GET_TX_DESC_PKT_OFFSET(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x04, 24, 5)
-#define SET_TX_DESC_SEC_TYPE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 22, 2, __value)
-#define GET_TX_DESC_SEC_TYPE(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x04, 22, 2)
-#define SET_TX_DESC_EN_DESC_ID(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 21, 1, __value)
-#define GET_TX_DESC_EN_DESC_ID(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x04, 21, 1)
-#define SET_TX_DESC_RATE_ID(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 16, 5, __value)
-#define GET_TX_DESC_RATE_ID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 16, 5)
-#define SET_TX_DESC_PIFS(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 15, 1, __value)
-#define GET_TX_DESC_PIFS(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 15, 1)
-#define SET_TX_DESC_LSIG_TXOP_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 14, 1, __value)
-#define GET_TX_DESC_LSIG_TXOP_EN(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x04, 14, 1)
-#define SET_TX_DESC_RD_NAV_EXT(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 13, 1, __value)
-#define GET_TX_DESC_RD_NAV_EXT(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x04, 13, 1)
-#define SET_TX_DESC_QSEL(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 8, 5, __value)
-#define GET_TX_DESC_QSEL(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 8, 5)
-#define SET_TX_DESC_MACID(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 0, 7, __value)
-#define GET_TX_DESC_MACID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 0, 7)
-
-/*TXDESC_WORD2*/
-
-#define SET_TX_DESC_HW_AES_IV(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 31, 1, __value)
-#define GET_TX_DESC_HW_AES_IV(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x08, 31, 1)
-
-#define SET_TX_DESC_FTM_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 30, 1, __value)
-#define GET_TX_DESC_FTM_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 30, 1)
-
-#define SET_TX_DESC_G_ID(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 24, 6, __value)
-#define GET_TX_DESC_G_ID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 24, 6)
-#define SET_TX_DESC_BT_NULL(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 23, 1, __value)
-#define GET_TX_DESC_BT_NULL(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 23, 1)
-#define SET_TX_DESC_AMPDU_DENSITY(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 20, 3, __value)
-#define GET_TX_DESC_AMPDU_DENSITY(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x08, 20, 3)
-#ifdef SET_TX_DESC_SPE_RPT
-#undef SET_TX_DESC_SPE_RPT
-#endif
-#define SET_TX_DESC_SPE_RPT(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 19, 1, __value)
-#define GET_TX_DESC_SPE_RPT(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 19, 1)
-#define SET_TX_DESC_RAW(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 18, 1, __value)
-#define GET_TX_DESC_RAW(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 18, 1)
-#define SET_TX_DESC_MOREFRAG(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 17, 1, __value)
-#define GET_TX_DESC_MOREFRAG(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x08, 17, 1)
-#define SET_TX_DESC_BK(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 16, 1, __value)
-#define GET_TX_DESC_BK(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 16, 1)
-#define SET_TX_DESC_NULL_1(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 15, 1, __value)
-#define GET_TX_DESC_NULL_1(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 15, 1)
-#define SET_TX_DESC_NULL_0(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 14, 1, __value)
-#define GET_TX_DESC_NULL_0(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 14, 1)
-#define SET_TX_DESC_RDG_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 13, 1, __value)
-#define GET_TX_DESC_RDG_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 13, 1)
-#define SET_TX_DESC_AGG_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 12, 1, __value)
-#define GET_TX_DESC_AGG_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 12, 1)
-#define SET_TX_DESC_CCA_RTS(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 10, 2, __value)
-#define GET_TX_DESC_CCA_RTS(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 10, 2)
-
-#define SET_TX_DESC_TRI_FRAME(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 9, 1, __value)
-#define GET_TX_DESC_TRI_FRAME(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x08, 9, 1)
-
-#define SET_TX_DESC_P_AID(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 0, 9, __value)
-#define GET_TX_DESC_P_AID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 0, 9)
-
-/*TXDESC_WORD3*/
-
-#define SET_TX_DESC_AMPDU_MAX_TIME(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 24, 8, __value)
-#define GET_TX_DESC_AMPDU_MAX_TIME(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 24, 8)
-#define SET_TX_DESC_NDPA(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 22, 2, __value)
-#define GET_TX_DESC_NDPA(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 22, 2)
-#define SET_TX_DESC_MAX_AGG_NUM(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 17, 5, __value)
-#define GET_TX_DESC_MAX_AGG_NUM(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 17, 5)
-#define SET_TX_DESC_USE_MAX_TIME_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 16, 1, __value)
-#define GET_TX_DESC_USE_MAX_TIME_EN(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 16, 1)
-#define SET_TX_DESC_NAVUSEHDR(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 15, 1, __value)
-#define GET_TX_DESC_NAVUSEHDR(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 15, 1)
-
-#define SET_TX_DESC_CHK_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 14, 1, __value)
-#define GET_TX_DESC_CHK_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 14, 1)
-
-#define SET_TX_DESC_HW_RTS_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 13, 1, __value)
-#define GET_TX_DESC_HW_RTS_EN(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 13, 1)
-#define SET_TX_DESC_RTSEN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 12, 1, __value)
-#define GET_TX_DESC_RTSEN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 12, 1)
-#define SET_TX_DESC_CTS2SELF(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 11, 1, __value)
-#define GET_TX_DESC_CTS2SELF(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 11, 1)
-#define SET_TX_DESC_DISDATAFB(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 10, 1, __value)
-#define GET_TX_DESC_DISDATAFB(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 10, 1)
-#define SET_TX_DESC_DISRTSFB(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 9, 1, __value)
-#define GET_TX_DESC_DISRTSFB(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 9, 1)
-#define SET_TX_DESC_USE_RATE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 8, 1, __value)
-#define GET_TX_DESC_USE_RATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 8, 1)
-#define SET_TX_DESC_HW_SSN_SEL(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 6, 2, __value)
-#define GET_TX_DESC_HW_SSN_SEL(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 6, 2)
-
-#define SET_TX_DESC_WHEADER_LEN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 0, 5, __value)
-#define GET_TX_DESC_WHEADER_LEN(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 0, 5)
-
-/*TXDESC_WORD4*/
-
-#define SET_TX_DESC_PCTS_MASK_IDX(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 30, 2, __value)
-#define GET_TX_DESC_PCTS_MASK_IDX(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x10, 30, 2)
-#define SET_TX_DESC_PCTS_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 29, 1, __value)
-#define GET_TX_DESC_PCTS_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 29, 1)
-#define SET_TX_DESC_RTSRATE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 24, 5, __value)
-#define GET_TX_DESC_RTSRATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 24, 5)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 18, 6, __value)
-#define GET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x10, 18, 6)
-#define SET_TX_DESC_RTY_LMT_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 17, 1, __value)
-#define GET_TX_DESC_RTY_LMT_EN(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x10, 17, 1)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 13, 4, __value)
-#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x10, 13, 4)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 8, 5, __value)
-#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x10, 8, 5)
-#define SET_TX_DESC_TRY_RATE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 7, 1, __value)
-#define GET_TX_DESC_TRY_RATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 7, 1)
-#define SET_TX_DESC_DATARATE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 0, 7, __value)
-#define GET_TX_DESC_DATARATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 0, 7)
-
-/*TXDESC_WORD5*/
-
-#define SET_TX_DESC_POLLUTED(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 31, 1, __value)
-#define GET_TX_DESC_POLLUTED(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x14, 31, 1)
-
-#define SET_TX_DESC_TXPWR_OFSET(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 28, 3, __value)
-#define GET_TX_DESC_TXPWR_OFSET(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x14, 28, 3)
-#define SET_TX_DESC_TX_ANT(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 24, 4, __value)
-#define GET_TX_DESC_TX_ANT(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 24, 4)
-#define SET_TX_DESC_PORT_ID(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 21, 3, __value)
-#define GET_TX_DESC_PORT_ID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 21, 3)
-
-#define SET_TX_DESC_MULTIPLE_PORT(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 18, 3, __value)
-#define GET_TX_DESC_MULTIPLE_PORT(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x14, 18, 3)
-
-#define SET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 17, 1, __value)
-#define GET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x14, 17, 1)
-
-#define SET_TX_DESC_RTS_SC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 13, 4, __value)
-#define GET_TX_DESC_RTS_SC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 13, 4)
-#define SET_TX_DESC_RTS_SHORT(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 12, 1, __value)
-#define GET_TX_DESC_RTS_SHORT(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x14, 12, 1)
-
-#define SET_TX_DESC_VCS_STBC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 10, 2, __value)
-#define GET_TX_DESC_VCS_STBC(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x14, 10, 2)
-
-#define SET_TX_DESC_DATA_STBC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 8, 2, __value)
-#define GET_TX_DESC_DATA_STBC(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x14, 8, 2)
-
-#define SET_TX_DESC_DATA_LDPC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 7, 1, __value)
-#define GET_TX_DESC_DATA_LDPC(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x14, 7, 1)
-
-#define SET_TX_DESC_DATA_BW(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 5, 2, __value)
-#define GET_TX_DESC_DATA_BW(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 5, 2)
-#define SET_TX_DESC_DATA_SHORT(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 4, 1, __value)
-#define GET_TX_DESC_DATA_SHORT(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x14, 4, 1)
-#define SET_TX_DESC_DATA_SC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 0, 4, __value)
-#define GET_TX_DESC_DATA_SC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 0, 4)
-
-/*TXDESC_WORD6*/
-
-#define SET_TX_DESC_ANTSEL_D(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 30, 2, __value)
-#define GET_TX_DESC_ANTSEL_D(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x18, 30, 2)
-#define SET_TX_DESC_ANT_MAPD(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 28, 2, __value)
-#define GET_TX_DESC_ANT_MAPD(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x18, 28, 2)
-#define SET_TX_DESC_ANT_MAPC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 26, 2, __value)
-#define GET_TX_DESC_ANT_MAPC(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x18, 26, 2)
-#define SET_TX_DESC_ANT_MAPB(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 24, 2, __value)
-#define GET_TX_DESC_ANT_MAPB(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x18, 24, 2)
-#define SET_TX_DESC_ANT_MAPA(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 22, 2, __value)
-#define GET_TX_DESC_ANT_MAPA(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x18, 22, 2)
-#define SET_TX_DESC_ANTSEL_C(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 20, 2, __value)
-#define GET_TX_DESC_ANTSEL_C(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x18, 20, 2)
-#define SET_TX_DESC_ANTSEL_B(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 18, 2, __value)
-#define GET_TX_DESC_ANTSEL_B(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x18, 18, 2)
-
-#define SET_TX_DESC_ANTSEL_A(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 16, 2, __value)
-#define GET_TX_DESC_ANTSEL_A(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x18, 16, 2)
-#define SET_TX_DESC_MBSSID(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 12, 4, __value)
-#define GET_TX_DESC_MBSSID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x18, 12, 4)
-#ifdef SET_TX_DESC_SW_DEFINE
-#undef SET_TX_DESC_SW_DEFINE
-#endif
-#define SET_TX_DESC_SW_DEFINE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 0, 12, __value)
-#define GET_TX_DESC_SW_DEFINE(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x18, 0, 12)
-
-/*TXDESC_WORD7*/
-
-#define SET_TX_DESC_DMA_TXAGG_NUM(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 24, 8, __value)
-#define GET_TX_DESC_DMA_TXAGG_NUM(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 24, 8)
-
-#define SET_TX_DESC_FINAL_DATA_RATE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 24, 8, __value)
-#define GET_TX_DESC_FINAL_DATA_RATE(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 24, 8)
-#define SET_TX_DESC_NTX_MAP(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 20, 4, __value)
-#define GET_TX_DESC_NTX_MAP(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 20, 4)
-
-#define SET_TX_DESC_TX_BUFF_SIZE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 0, 16, __value)
-#define GET_TX_DESC_TX_BUFF_SIZE(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 0, 16)
-#define SET_TX_DESC_TXDESC_CHECKSUM(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 0, 16, __value)
-#define GET_TX_DESC_TXDESC_CHECKSUM(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 0, 16)
-#define SET_TX_DESC_TIMESTAMP(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 0, 16, __value)
-#define GET_TX_DESC_TIMESTAMP(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 0, 16)
-
-/*TXDESC_WORD8*/
-
-#define SET_TX_DESC_TXWIFI_CP(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 31, 1, __value)
-#define GET_TX_DESC_TXWIFI_CP(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 31, 1)
-#define SET_TX_DESC_MAC_CP(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 30, 1, __value)
-#define GET_TX_DESC_MAC_CP(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 30, 1)
-#define SET_TX_DESC_STW_PKTRE_DIS(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 29, 1, __value)
-#define GET_TX_DESC_STW_PKTRE_DIS(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 29, 1)
-#define SET_TX_DESC_STW_RB_DIS(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 28, 1, __value)
-#define GET_TX_DESC_STW_RB_DIS(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 28, 1)
-#define SET_TX_DESC_STW_RATE_DIS(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 27, 1, __value)
-#define GET_TX_DESC_STW_RATE_DIS(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 27, 1)
-#define SET_TX_DESC_STW_ANT_DIS(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 26, 1, __value)
-#define GET_TX_DESC_STW_ANT_DIS(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 26, 1)
-#define SET_TX_DESC_STW_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 25, 1, __value)
-#define GET_TX_DESC_STW_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 25, 1)
-#define SET_TX_DESC_SMH_EN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 24, 1, __value)
-#define GET_TX_DESC_SMH_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 24, 1)
-
-#define SET_TX_DESC_TAILPAGE_L(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 24, 8, __value)
-#define GET_TX_DESC_TAILPAGE_L(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 24, 8)
-
-#define SET_TX_DESC_SDIO_DMASEQ(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 16, 8, __value)
-#define GET_TX_DESC_SDIO_DMASEQ(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 16, 8)
-
-#define SET_TX_DESC_NEXTHEADPAGE_L(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 16, 8, __value)
-#define GET_TX_DESC_NEXTHEADPAGE_L(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 16, 8)
-#define SET_TX_DESC_EN_HWSEQ(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 15, 1, __value)
-#define GET_TX_DESC_EN_HWSEQ(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 15, 1)
-
-#define SET_TX_DESC_EN_HWEXSEQ(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 14, 1, __value)
-#define GET_TX_DESC_EN_HWEXSEQ(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 14, 1)
-
-#define SET_TX_DESC_DATA_RC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 8, 6, __value)
-#define GET_TX_DESC_DATA_RC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 8, 6)
-#define SET_TX_DESC_BAR_RTY_TH(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 6, 2, __value)
-#define GET_TX_DESC_BAR_RTY_TH(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x20, 6, 2)
-#define SET_TX_DESC_RTS_RC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 0, 6, __value)
-#define GET_TX_DESC_RTS_RC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 0, 6)
-
-/*TXDESC_WORD9*/
-
-#define SET_TX_DESC_TAILPAGE_H(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 28, 4, __value)
-#define GET_TX_DESC_TAILPAGE_H(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x24, 28, 4)
-#define SET_TX_DESC_NEXTHEADPAGE_H(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 24, 4, __value)
-#define GET_TX_DESC_NEXTHEADPAGE_H(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x24, 24, 4)
-
-#define SET_TX_DESC_SW_SEQ(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 12, 12, __value)
-#define GET_TX_DESC_SW_SEQ(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x24, 12, 12)
-#define SET_TX_DESC_TXBF_PATH(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 11, 1, __value)
-#define GET_TX_DESC_TXBF_PATH(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x24, 11, 1)
-#define SET_TX_DESC_PADDING_LEN(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 0, 11, __value)
-#define GET_TX_DESC_PADDING_LEN(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x24, 0, 11)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 0, 8, __value)
-#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x24, 0, 8)
-
-/*WORD10*/
-
-#define SET_TX_DESC_MU_DATARATE(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x28, 8, 8, __value)
-#define GET_TX_DESC_MU_DATARATE(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x28, 8, 8)
-#define SET_TX_DESC_MU_RC(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x28, 4, 4, __value)
-#define GET_TX_DESC_MU_RC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x28, 4, 4)
-#define SET_TX_DESC_SND_PKT_SEL(__tx_desc, __value) \
- SET_BITS_TO_LE_4BYTE(__tx_desc + 0x28, 0, 2, __value)
-#define GET_TX_DESC_SND_PKT_SEL(__tx_desc) \
- LE_BITS_TO_4BYTE(__tx_desc + 0x28, 0, 2)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _HALMAC_TYPE_H_
-#define _HALMAC_TYPE_H_
-
-#include "halmac_2_platform.h"
-#include "halmac_fw_info.h"
-#include "halmac_intf_phy_cmd.h"
-
-#define HALMAC_SCAN_CH_NUM_MAX 28
-#define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */
-#define HALMAC_PHY_PARAMETER_SIZE 12
-#define HALMAC_PHY_PARAMETER_MAX_NUM 128
-#define HALMAC_MAX_SSID_LEN 32
-#define HALMAC_SUPPORT_NLO_NUM 16
-#define HALMAC_SUPPORT_PROBE_REQ_NUM 8
-#define HALMC_DDMA_POLLING_COUNT 1000
-#define API_ARRAY_SIZE 32
-
-/* platform api */
-#define PLATFORM_SDIO_CMD52_READ \
- halmac_adapter->halmac_platform_api->SDIO_CMD52_READ
-#define PLATFORM_SDIO_CMD53_READ_8 \
- halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_8
-#define PLATFORM_SDIO_CMD53_READ_16 \
- halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_16
-#define PLATFORM_SDIO_CMD53_READ_32 \
- halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_32
-#define PLATFORM_SDIO_CMD53_READ_N \
- halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_N
-#define PLATFORM_SDIO_CMD52_WRITE \
- halmac_adapter->halmac_platform_api->SDIO_CMD52_WRITE
-#define PLATFORM_SDIO_CMD53_WRITE_8 \
- halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_8
-#define PLATFORM_SDIO_CMD53_WRITE_16 \
- halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_16
-#define PLATFORM_SDIO_CMD53_WRITE_32 \
- halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_32
-
-#define PLATFORM_REG_READ_8 halmac_adapter->halmac_platform_api->REG_READ_8
-#define PLATFORM_REG_READ_16 halmac_adapter->halmac_platform_api->REG_READ_16
-#define PLATFORM_REG_READ_32 halmac_adapter->halmac_platform_api->REG_READ_32
-#define PLATFORM_REG_WRITE_8 halmac_adapter->halmac_platform_api->REG_WRITE_8
-#define PLATFORM_REG_WRITE_16 halmac_adapter->halmac_platform_api->REG_WRITE_16
-#define PLATFORM_REG_WRITE_32 halmac_adapter->halmac_platform_api->REG_WRITE_32
-
-#define PLATFORM_SEND_RSVD_PAGE \
- halmac_adapter->halmac_platform_api->SEND_RSVD_PAGE
-#define PLATFORM_SEND_H2C_PKT halmac_adapter->halmac_platform_api->SEND_H2C_PKT
-
-#define PLATFORM_EVENT_INDICATION \
- halmac_adapter->halmac_platform_api->EVENT_INDICATION
-
-#define HALMAC_RT_TRACE(drv_adapter, comp, level, fmt, ...) \
- RT_TRACE(drv_adapter, COMP_HALMAC, level, fmt, ##__VA_ARGS__)
-
-#define HALMAC_REG_READ_8 halmac_api->halmac_reg_read_8
-#define HALMAC_REG_READ_16 halmac_api->halmac_reg_read_16
-#define HALMAC_REG_READ_32 halmac_api->halmac_reg_read_32
-#define HALMAC_REG_WRITE_8 halmac_api->halmac_reg_write_8
-#define HALMAC_REG_WRITE_16 halmac_api->halmac_reg_write_16
-#define HALMAC_REG_WRITE_32 halmac_api->halmac_reg_write_32
-#define HALMAC_REG_SDIO_CMD53_READ_N halmac_api->halmac_reg_sdio_cmd53_read_n
-
-/* Swap Little-endian <-> Big-endia*/
-
-/*1->Little endian 0->Big endian*/
-#if HALMAC_SYSTEM_ENDIAN
-#else
-#endif
-
-#define HALMAC_ALIGN(x, a) HALMAC_ALIGN_MASK(x, (a) - 1)
-#define HALMAC_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
-
-/* HALMAC API return status*/
-enum halmac_ret_status {
- HALMAC_RET_SUCCESS = 0x00,
- HALMAC_RET_SUCCESS_ENQUEUE = 0x01,
- HALMAC_RET_PLATFORM_API_NULL = 0x02,
- HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,
- HALMAC_RET_MALLOC_FAIL = 0x04,
- HALMAC_RET_ADAPTER_INVALID = 0x05,
- HALMAC_RET_ITF_INCORRECT = 0x06,
- HALMAC_RET_DLFW_FAIL = 0x07,
- HALMAC_RET_PORT_NOT_SUPPORT = 0x08,
- HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09,
- HALMAC_RET_INIT_LLT_FAIL = 0x0A,
- HALMAC_RET_POWER_STATE_INVALID = 0x0B,
- HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,
- HALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D,
- HALMAC_RET_EFUSE_R_FAIL = 0x0E,
- HALMAC_RET_EFUSE_W_FAIL = 0x0F,
- HALMAC_RET_H2C_SW_RES_FAIL = 0x10,
- HALMAC_RET_SEND_H2C_FAIL = 0x11,
- HALMAC_RET_PARA_NOT_SUPPORT = 0x12,
- HALMAC_RET_PLATFORM_API_INCORRECT = 0x13,
- HALMAC_RET_ENDIAN_ERR = 0x14,
- HALMAC_RET_FW_SIZE_ERR = 0x15,
- HALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16,
- HALMAC_RET_FAIL = 0x17,
- HALMAC_RET_CHANGE_PS_FAIL = 0x18,
- HALMAC_RET_CFG_PARA_FAIL = 0x19,
- HALMAC_RET_UPDATE_PROBE_FAIL = 0x1A,
- HALMAC_RET_SCAN_FAIL = 0x1B,
- HALMAC_RET_STOP_SCAN_FAIL = 0x1C,
- HALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D,
- HALMAC_RET_POWER_ON_FAIL = 0x1E,
- HALMAC_RET_POWER_OFF_FAIL = 0x1F,
- HALMAC_RET_RX_AGG_MODE_FAIL = 0x20,
- HALMAC_RET_DATA_BUF_NULL = 0x21,
- HALMAC_RET_DATA_SIZE_INCORRECT = 0x22,
- HALMAC_RET_QSEL_INCORRECT = 0x23,
- HALMAC_RET_DMA_MAP_INCORRECT = 0x24,
- HALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25,
- HALMAC_RET_DDMA_FAIL = 0x26,
- HALMAC_RET_FW_CHECKSUM_FAIL = 0x27,
- HALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28,
- HALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29,
- HALMAC_RET_WRITE_DATA_FAIL = 0x2A,
- HALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B,
- HALMAC_RET_NULL_POINTER = 0x2C,
- HALMAC_RET_PROBE_NOT_FOUND = 0x2D,
- HALMAC_RET_FW_NO_MEMORY = 0x2E,
- HALMAC_RET_H2C_STATUS_ERR = 0x2F,
- HALMAC_RET_GET_H2C_SPACE_ERR = 0x30,
- HALMAC_RET_H2C_SPACE_FULL = 0x31,
- HALMAC_RET_DATAPACK_NO_FOUND = 0x32,
- HALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33,
- HALMAC_RET_TX_DMA_ERR = 0x34,
- HALMAC_RET_RX_DMA_ERR = 0x35,
- HALMAC_RET_CHIP_NOT_SUPPORT = 0x36,
- HALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37,
- HALMAC_RET_CH_SW_SEQ_WRONG = 0x38,
- HALMAC_RET_CH_SW_NO_BUF = 0x39,
- HALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A,
- HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B,
- HALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C,
- HALMAC_RET_GEN_INFO_NOT_SENT = 0x3D,
- HALMAC_RET_STATE_INCORRECT = 0x3E,
- HALMAC_RET_H2C_BUSY = 0x3F,
- HALMAC_RET_INVALID_FEATURE_ID = 0x40,
- HALMAC_RET_BUFFER_TOO_SMALL = 0x41,
- HALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42,
- HALMAC_RET_BUSY_STATE = 0x43,
- HALMAC_RET_ERROR_STATE = 0x44,
- HALMAC_RET_API_INVALID = 0x45,
- HALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46,
- HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47,
- HALMAC_RET_EEPROM_PARSING_FAIL = 0x48,
- HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,
- HALMAC_RET_WRONG_ARGUMENT = 0x4A,
- HALMAC_RET_NOT_SUPPORT = 0x4B,
- HALMAC_RET_C2H_NOT_HANDLED = 0x4C,
- HALMAC_RET_PARA_SENDING = 0x4D,
- HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,
- HALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F,
- HALMAC_RET_SWITCH_CASE_ERROR = 0x50,
- HALMAC_RET_EFUSE_BANK_INCORRECT = 0x51,
- HALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52,
- HALMAC_RET_USB_MODE_UNCHANGE = 0x53,
- HALMAC_RET_NO_DLFW = 0x54,
- HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,
- HALMAC_RET_BIP_NO_SUPPORT = 0x56,
- HALMAC_RET_ENTRY_INDEX_ERROR = 0x57,
- HALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58,
- HALMAC_RET_DRV_DL_ERR = 0x59,
- HALMAC_RET_OQT_NOT_ENOUGH = 0x5A,
- HALMAC_RET_PWR_UNCHANGE = 0x5B,
- HALMAC_RET_FW_NO_SUPPORT = 0x60,
- HALMAC_RET_TXFIFO_NO_EMPTY = 0x61,
-};
-
-enum halmac_mac_clock_hw_def {
- HALMAC_MAC_CLOCK_HW_DEF_80M = 0,
- HALMAC_MAC_CLOCK_HW_DEF_40M = 1,
- HALMAC_MAC_CLOCK_HW_DEF_20M = 2,
-};
-
-/* Rx aggregation parameters */
-enum halmac_normal_rxagg_th_to {
- HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF,
- HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01,
-};
-
-enum halmac_loopback_rxagg_th_to {
- HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF,
- HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01,
-};
-
-/* Chip ID*/
-enum halmac_chip_id {
- HALMAC_CHIP_ID_8822B = 0,
- HALMAC_CHIP_ID_8821C = 1,
- HALMAC_CHIP_ID_8814B = 2,
- HALMAC_CHIP_ID_8197F = 3,
- HALMAC_CHIP_ID_UNDEFINE = 0x7F,
-};
-
-enum halmac_chip_id_hw_def {
- HALMAC_CHIP_ID_HW_DEF_8723A = 0x01,
- HALMAC_CHIP_ID_HW_DEF_8188E = 0x02,
- HALMAC_CHIP_ID_HW_DEF_8881A = 0x03,
- HALMAC_CHIP_ID_HW_DEF_8812A = 0x04,
- HALMAC_CHIP_ID_HW_DEF_8821A = 0x05,
- HALMAC_CHIP_ID_HW_DEF_8723B = 0x06,
- HALMAC_CHIP_ID_HW_DEF_8192E = 0x07,
- HALMAC_CHIP_ID_HW_DEF_8814A = 0x08,
- HALMAC_CHIP_ID_HW_DEF_8821C = 0x09,
- HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A,
- HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B,
- HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C,
- HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D,
- HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E,
- HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F,
- HALMAC_CHIP_ID_HW_DEF_8814B = 0x10,
- HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
- HALMAC_CHIP_ID_HW_DEF_PS = 0xEA,
-};
-
-/* Chip Version*/
-enum halmac_chip_ver {
- HALMAC_CHIP_VER_A_CUT = 0x00,
- HALMAC_CHIP_VER_B_CUT = 0x01,
- HALMAC_CHIP_VER_C_CUT = 0x02,
- HALMAC_CHIP_VER_D_CUT = 0x03,
- HALMAC_CHIP_VER_E_CUT = 0x04,
- HALMAC_CHIP_VER_F_CUT = 0x05,
- HALMAC_CHIP_VER_TEST = 0xFF,
- HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
-};
-
-/* Network type select */
-enum halmac_network_type_select {
- HALMAC_NETWORK_NO_LINK = 0,
- HALMAC_NETWORK_ADHOC = 1,
- HALMAC_NETWORK_INFRASTRUCTURE = 2,
- HALMAC_NETWORK_AP = 3,
- HALMAC_NETWORK_UNDEFINE = 0x7F,
-};
-
-/* Transfer mode select */
-enum halmac_trnsfer_mode_select {
- HALMAC_TRNSFER_NORMAL = 0x0,
- HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,
- HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,
- HALMAC_TRNSFER_UNDEFINE = 0x7F,
-};
-
-/* Queue select */
-enum halmac_dma_mapping {
- HALMAC_DMA_MAPPING_EXTRA = 0,
- HALMAC_DMA_MAPPING_LOW = 1,
- HALMAC_DMA_MAPPING_NORMAL = 2,
- HALMAC_DMA_MAPPING_HIGH = 3,
- HALMAC_DMA_MAPPING_UNDEFINE = 0x7F,
-};
-
-#define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH
-#define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL
-#define HALMAC_MAP2_LQ HALMAC_DMA_MAPPING_LOW
-#define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA
-#define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE
-
-/* TXDESC queue select TID */
-enum halmac_txdesc_queue_tid {
- HALMAC_TXDESC_QSEL_TID0 = 0,
- HALMAC_TXDESC_QSEL_TID1 = 1,
- HALMAC_TXDESC_QSEL_TID2 = 2,
- HALMAC_TXDESC_QSEL_TID3 = 3,
- HALMAC_TXDESC_QSEL_TID4 = 4,
- HALMAC_TXDESC_QSEL_TID5 = 5,
- HALMAC_TXDESC_QSEL_TID6 = 6,
- HALMAC_TXDESC_QSEL_TID7 = 7,
- HALMAC_TXDESC_QSEL_TID8 = 8,
- HALMAC_TXDESC_QSEL_TID9 = 9,
- HALMAC_TXDESC_QSEL_TIDA = 10,
- HALMAC_TXDESC_QSEL_TIDB = 11,
- HALMAC_TXDESC_QSEL_TIDC = 12,
- HALMAC_TXDESC_QSEL_TIDD = 13,
- HALMAC_TXDESC_QSEL_TIDE = 14,
- HALMAC_TXDESC_QSEL_TIDF = 15,
-
- HALMAC_TXDESC_QSEL_BEACON = 0x10,
- HALMAC_TXDESC_QSEL_HIGH = 0x11,
- HALMAC_TXDESC_QSEL_MGT = 0x12,
- HALMAC_TXDESC_QSEL_H2C_CMD = 0x13,
-
- HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,
-};
-
-enum halmac_ptcl_queue {
- HALMAC_PTCL_QUEUE_VO = 0x0,
- HALMAC_PTCL_QUEUE_VI = 0x1,
- HALMAC_PTCL_QUEUE_BE = 0x2,
- HALMAC_PTCL_QUEUE_BK = 0x3,
- HALMAC_PTCL_QUEUE_MG = 0x4,
- HALMAC_PTCL_QUEUE_HI = 0x5,
- HALMAC_PTCL_QUEUE_NUM = 0x6,
- HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F,
-};
-
-enum halmac_queue_select {
- HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6,
- HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4,
- HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0,
- HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1,
- HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
- HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
- HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
- HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
- HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON,
- HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH,
- HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT,
- HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
- HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F,
-};
-
-/* USB burst size */
-enum halmac_usb_burst_size {
- HALMAC_USB_BURST_SIZE_3_0 = 0x0,
- HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1,
- HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2,
- HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3,
- HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F,
-};
-
-/* HAL API function parameters*/
-enum halmac_interface {
- HALMAC_INTERFACE_PCIE = 0x0,
- HALMAC_INTERFACE_USB = 0x1,
- HALMAC_INTERFACE_SDIO = 0x2,
- HALMAC_INTERFACE_AXI = 0x3,
- HALMAC_INTERFACE_UNDEFINE = 0x7F,
-};
-
-enum halmac_rx_agg_mode {
- HALMAC_RX_AGG_MODE_NONE = 0x0,
- HALMAC_RX_AGG_MODE_DMA = 0x1,
- HALMAC_RX_AGG_MODE_USB = 0x2,
- HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,
-};
-
-struct halmac_rxagg_th {
- u8 drv_define;
- u8 timeout;
- u8 size;
-};
-
-struct halmac_rxagg_cfg {
- enum halmac_rx_agg_mode mode;
- struct halmac_rxagg_th threshold;
-};
-
-enum halmac_mac_power {
- HALMAC_MAC_POWER_OFF = 0x0,
- HALMAC_MAC_POWER_ON = 0x1,
- HALMAC_MAC_POWER_UNDEFINE = 0x7F,
-};
-
-enum halmac_ps_state {
- HALMAC_PS_STATE_ACT = 0x0,
- HALMAC_PS_STATE_LPS = 0x1,
- HALMAC_PS_STATE_IPS = 0x2,
- HALMAC_PS_STATE_UNDEFINE = 0x7F,
-};
-
-enum halmac_trx_mode {
- HALMAC_TRX_MODE_NORMAL = 0x0,
- HALMAC_TRX_MODE_TRXSHARE = 0x1,
- HALMAC_TRX_MODE_WMM = 0x2,
- HALMAC_TRX_MODE_P2P = 0x3,
- HALMAC_TRX_MODE_LOOPBACK = 0x4,
- HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,
- HALMAC_TRX_MODE_MAX = 0x6,
- HALMAC_TRX_MODE_WMM_LINUX = 0x7E,
- HALMAC_TRX_MODE_UNDEFINE = 0x7F,
-};
-
-enum halmac_wireless_mode {
- HALMAC_WIRELESS_MODE_B = 0x0,
- HALMAC_WIRELESS_MODE_G = 0x1,
- HALMAC_WIRELESS_MODE_N = 0x2,
- HALMAC_WIRELESS_MODE_AC = 0x3,
- HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,
-};
-
-enum halmac_bw {
- HALMAC_BW_20 = 0x00,
- HALMAC_BW_40 = 0x01,
- HALMAC_BW_80 = 0x02,
- HALMAC_BW_160 = 0x03,
- HALMAC_BW_5 = 0x04,
- HALMAC_BW_10 = 0x05,
- HALMAC_BW_MAX = 0x06,
- HALMAC_BW_UNDEFINE = 0x7F,
-};
-
-enum halmac_efuse_read_cfg {
- HALMAC_EFUSE_R_AUTO = 0x00,
- HALMAC_EFUSE_R_DRV = 0x01,
- HALMAC_EFUSE_R_FW = 0x02,
- HALMAC_EFUSE_R_UNDEFINE = 0x7F,
-};
-
-enum halmac_dlfw_mem {
- HALMAC_DLFW_MEM_EMEM = 0x00,
- HALMAC_DLFW_MEM_UNDEFINE = 0x7F,
-};
-
-struct halmac_tx_desc {
- u32 dword0;
- u32 dword1;
- u32 dword2;
- u32 dword3;
- u32 dword4;
- u32 dword5;
- u32 dword6;
- u32 dword7;
- u32 dword8;
- u32 dword9;
- u32 dword10;
- u32 dword11;
-};
-
-struct halmac_rx_desc {
- u32 dword0;
- u32 dword1;
- u32 dword2;
- u32 dword3;
- u32 dword4;
- u32 dword5;
-};
-
-struct halmac_fwlps_option {
- u8 mode;
- u8 clk_request;
- u8 rlbm;
- u8 smart_ps;
- u8 awake_interval;
- u8 all_queue_uapsd;
- u8 pwr_state;
- u8 low_pwr_rx_beacon;
- u8 ant_auto_switch;
- u8 ps_allow_bt_high_priority;
- u8 protect_bcn;
- u8 silence_period;
- u8 fast_bt_connect;
- u8 two_antenna_en;
- u8 adopt_user_setting;
- u8 drv_bcn_early_shift;
- bool enter_32K;
-};
-
-struct halmac_fwips_option {
- u8 adopt_user_setting;
-};
-
-struct halmac_wowlan_option {
- u8 adopt_user_setting;
-};
-
-struct halmac_bcn_ie_info {
- u8 func_en;
- u8 size_th;
- u8 timeout;
- u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
-};
-
-enum halmac_reg_type {
- HALMAC_REG_TYPE_MAC = 0x0,
- HALMAC_REG_TYPE_BB = 0x1,
- HALMAC_REG_TYPE_RF = 0x2,
- HALMAC_REG_TYPE_UNDEFINE = 0x7F,
-};
-
-enum halmac_parameter_cmd {
- /* HALMAC_PARAMETER_CMD_LLT = 0x1, */
- /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */
- /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */
- HALMAC_PARAMETER_CMD_MAC_W8 = 0x4,
- HALMAC_PARAMETER_CMD_MAC_W16 = 0x5,
- HALMAC_PARAMETER_CMD_MAC_W32 = 0x6,
- HALMAC_PARAMETER_CMD_RF_W = 0x7,
- HALMAC_PARAMETER_CMD_BB_W8 = 0x8,
- HALMAC_PARAMETER_CMD_BB_W16 = 0x9,
- HALMAC_PARAMETER_CMD_BB_W32 = 0XA,
- HALMAC_PARAMETER_CMD_DELAY_US = 0X10,
- HALMAC_PARAMETER_CMD_DELAY_MS = 0X11,
- HALMAC_PARAMETER_CMD_END = 0XFF,
-};
-
-union halmac_parameter_content {
- struct _MAC_REG_W {
- u32 value;
- u32 msk;
- u16 offset;
- u8 msk_en;
- } MAC_REG_W;
- struct _BB_REG_W {
- u32 value;
- u32 msk;
- u16 offset;
- u8 msk_en;
- } BB_REG_W;
- struct _RF_REG_W {
- u32 value;
- u32 msk;
- u8 offset;
- u8 msk_en;
- u8 rf_path;
- } RF_REG_W;
- struct _DELAY_TIME {
- u32 rsvd1;
- u32 rsvd2;
- u16 delay_time;
- u8 rsvd3;
- } DELAY_TIME;
-};
-
-struct halmac_phy_parameter_info {
- enum halmac_parameter_cmd cmd_id;
- union halmac_parameter_content content;
-};
-
-struct halmac_h2c_info {
- u16 h2c_seq_num; /* H2C sequence number */
- u8 in_use; /* 0 : empty 1 : used */
- enum halmac_h2c_return_code status;
-};
-
-struct halmac_pg_efuse_info {
- u8 *efuse_map;
- u32 efuse_map_size;
- u8 *efuse_mask;
- u32 efuse_mask_size;
-};
-
-struct halmac_txagg_buff_info {
- u8 *tx_agg_buf;
- u8 *curr_pkt_buf;
- u32 avai_buf_size;
- u32 total_pkt_size;
- u8 agg_num;
-};
-
-struct halmac_config_para_info {
- u32 para_buf_size; /* Parameter buffer size */
- u8 *cfg_para_buf; /* Buffer for config parameter */
- u8 *para_buf_w; /* Write pointer of the parameter buffer */
- u32 para_num; /* Parameter numbers in parameter buffer */
- u32 avai_para_buf_size; /* Free size of parameter buffer */
- u32 offset_accumulation;
- u32 value_accumulation;
- enum halmac_data_type data_type; /*DataType which is passed to FW*/
- u8 datapack_segment; /*DataPack Segment, from segment0...*/
- bool full_fifo_mode; /* Used full tx fifo to save cfg parameter */
-};
-
-struct halmac_hw_config_info {
- u32 efuse_size; /* Record efuse size */
- u32 eeprom_size; /* Record eeprom size */
- u32 bt_efuse_size; /* Record BT efuse size */
- u32 tx_fifo_size; /* Record tx fifo size */
- u32 rx_fifo_size; /* Record rx fifo size */
- u8 txdesc_size; /* Record tx desc size */
- u8 rxdesc_size; /* Record rx desc size */
- u32 page_size; /* Record page size */
- u16 tx_align_size;
- u8 page_size_2_power;
- u8 cam_entry_num; /* Record CAM entry number */
-};
-
-struct halmac_sdio_free_space {
- u16 high_queue_number; /* Free space of HIQ */
- u16 normal_queue_number; /* Free space of MIDQ */
- u16 low_queue_number; /* Free space of LOWQ */
- u16 public_queue_number; /* Free space of PUBQ */
- u16 extra_queue_number; /* Free space of EXBQ */
- u8 ac_oqt_number;
- u8 non_ac_oqt_number;
- u8 ac_empty;
-};
-
-enum hal_fifo_sel {
- HAL_FIFO_SEL_TX,
- HAL_FIFO_SEL_RX,
- HAL_FIFO_SEL_RSVD_PAGE,
- HAL_FIFO_SEL_REPORT,
- HAL_FIFO_SEL_LLT,
-};
-
-enum halmac_drv_info {
- HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */
- HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */
- HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info appended */
- HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended */
- HALMAC_DRV_INFO_UNDEFINE,
-};
-
-struct halmac_bt_coex_cmd {
- u8 element_id;
- u8 op_code;
- u8 op_code_ver;
- u8 req_num;
- u8 data0;
- u8 data1;
- u8 data2;
- u8 data3;
- u8 data4;
-};
-
-enum halmac_pri_ch_idx {
- HALMAC_CH_IDX_UNDEFINE = 0,
- HALMAC_CH_IDX_1 = 1,
- HALMAC_CH_IDX_2 = 2,
- HALMAC_CH_IDX_3 = 3,
- HALMAC_CH_IDX_4 = 4,
- HALMAC_CH_IDX_MAX = 5,
-};
-
-struct halmac_ch_info {
- enum halmac_cs_action_id action_id;
- enum halmac_bw bw;
- enum halmac_pri_ch_idx pri_ch_idx;
- u8 channel;
- u8 timeout;
- u8 extra_info;
-};
-
-struct halmac_ch_extra_info {
- u8 extra_info;
- enum halmac_cs_extra_action_id extra_action_id;
- u8 extra_info_size;
- u8 *extra_info_data;
-};
-
-enum halmac_cs_periodic_option {
- HALMAC_CS_PERIODIC_NONE,
- HALMAC_CS_PERIODIC_NORMAL,
- HALMAC_CS_PERIODIC_2_PHASE,
- HALMAC_CS_PERIODIC_SEAMLESS,
-};
-
-struct halmac_ch_switch_option {
- enum halmac_bw dest_bw;
- enum halmac_cs_periodic_option periodic_option;
- enum halmac_pri_ch_idx dest_pri_ch_idx;
- /* u32 tsf_high; */
- u32 tsf_low;
- bool switch_en;
- u8 dest_ch_en;
- u8 absolute_time_en;
- u8 dest_ch;
- u8 normal_period;
- u8 normal_cycle;
- u8 phase_2_period;
-};
-
-struct halmac_fw_version {
- u16 version;
- u8 sub_version;
- u8 sub_index;
- u16 h2c_version;
-};
-
-enum halmac_rf_type {
- HALMAC_RF_1T2R = 0,
- HALMAC_RF_2T4R = 1,
- HALMAC_RF_2T2R = 2,
- HALMAC_RF_2T3R = 3,
- HALMAC_RF_1T1R = 4,
- HALMAC_RF_2T2R_GREEN = 5,
- HALMAC_RF_3T3R = 6,
- HALMAC_RF_3T4R = 7,
- HALMAC_RF_4T4R = 8,
- HALMAC_RF_MAX_TYPE = 0xF,
-};
-
-struct halmac_general_info {
- u8 rfe_type;
- enum halmac_rf_type rf_type;
-};
-
-struct halmac_pwr_tracking_para {
- u8 enable;
- u8 tx_pwr_index;
- u8 pwr_tracking_offset_value;
- u8 tssi_value;
-};
-
-struct halmac_pwr_tracking_option {
- u8 type;
- u8 bbswing_index;
- struct halmac_pwr_tracking_para
- pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */
-};
-
-struct halmac_nlo_cfg {
- u8 num_of_ssid;
- u8 num_of_hidden_ap;
- u8 rsvd[2];
- u32 pattern_check;
- u32 rsvd1;
- u32 rsvd2;
- u8 ssid_len[HALMAC_SUPPORT_NLO_NUM];
- u8 chiper_type[HALMAC_SUPPORT_NLO_NUM];
- u8 rsvd3[HALMAC_SUPPORT_NLO_NUM];
- u8 loc_probe_req[HALMAC_SUPPORT_PROBE_REQ_NUM];
- u8 rsvd4[56];
- u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN];
-};
-
-enum halmac_data_rate {
- HALMAC_CCK1,
- HALMAC_CCK2,
- HALMAC_CCK5_5,
- HALMAC_CCK11,
- HALMAC_OFDM6,
- HALMAC_OFDM9,
- HALMAC_OFDM12,
- HALMAC_OFDM18,
- HALMAC_OFDM24,
- HALMAC_OFDM36,
- HALMAC_OFDM48,
- HALMAC_OFDM54,
- HALMAC_MCS0,
- HALMAC_MCS1,
- HALMAC_MCS2,
- HALMAC_MCS3,
- HALMAC_MCS4,
- HALMAC_MCS5,
- HALMAC_MCS6,
- HALMAC_MCS7,
- HALMAC_MCS8,
- HALMAC_MCS9,
- HALMAC_MCS10,
- HALMAC_MCS11,
- HALMAC_MCS12,
- HALMAC_MCS13,
- HALMAC_MCS14,
- HALMAC_MCS15,
- HALMAC_MCS16,
- HALMAC_MCS17,
- HALMAC_MCS18,
- HALMAC_MCS19,
- HALMAC_MCS20,
- HALMAC_MCS21,
- HALMAC_MCS22,
- HALMAC_MCS23,
- HALMAC_MCS24,
- HALMAC_MCS25,
- HALMAC_MCS26,
- HALMAC_MCS27,
- HALMAC_MCS28,
- HALMAC_MCS29,
- HALMAC_MCS30,
- HALMAC_MCS31,
- HALMAC_VHT_NSS1_MCS0,
- HALMAC_VHT_NSS1_MCS1,
- HALMAC_VHT_NSS1_MCS2,
- HALMAC_VHT_NSS1_MCS3,
- HALMAC_VHT_NSS1_MCS4,
- HALMAC_VHT_NSS1_MCS5,
- HALMAC_VHT_NSS1_MCS6,
- HALMAC_VHT_NSS1_MCS7,
- HALMAC_VHT_NSS1_MCS8,
- HALMAC_VHT_NSS1_MCS9,
- HALMAC_VHT_NSS2_MCS0,
- HALMAC_VHT_NSS2_MCS1,
- HALMAC_VHT_NSS2_MCS2,
- HALMAC_VHT_NSS2_MCS3,
- HALMAC_VHT_NSS2_MCS4,
- HALMAC_VHT_NSS2_MCS5,
- HALMAC_VHT_NSS2_MCS6,
- HALMAC_VHT_NSS2_MCS7,
- HALMAC_VHT_NSS2_MCS8,
- HALMAC_VHT_NSS2_MCS9,
- HALMAC_VHT_NSS3_MCS0,
- HALMAC_VHT_NSS3_MCS1,
- HALMAC_VHT_NSS3_MCS2,
- HALMAC_VHT_NSS3_MCS3,
- HALMAC_VHT_NSS3_MCS4,
- HALMAC_VHT_NSS3_MCS5,
- HALMAC_VHT_NSS3_MCS6,
- HALMAC_VHT_NSS3_MCS7,
- HALMAC_VHT_NSS3_MCS8,
- HALMAC_VHT_NSS3_MCS9,
- HALMAC_VHT_NSS4_MCS0,
- HALMAC_VHT_NSS4_MCS1,
- HALMAC_VHT_NSS4_MCS2,
- HALMAC_VHT_NSS4_MCS3,
- HALMAC_VHT_NSS4_MCS4,
- HALMAC_VHT_NSS4_MCS5,
- HALMAC_VHT_NSS4_MCS6,
- HALMAC_VHT_NSS4_MCS7,
- HALMAC_VHT_NSS4_MCS8,
- HALMAC_VHT_NSS4_MCS9
-};
-
-enum halmac_rf_path {
- HALMAC_RF_PATH_A,
- HALMAC_RF_PATH_B,
- HALMAC_RF_PATH_C,
- HALMAC_RF_PATH_D
-};
-
-enum halmac_snd_pkt_sel {
- HALMAC_UNI_NDPA,
- HALMAC_BMC_NDPA,
- HALMAC_NON_FINAL_BFRPRPOLL,
- HALMAC_FINAL_BFRPTPOLL,
-};
-
-enum hal_security_type {
- HAL_SECURITY_TYPE_NONE = 0,
- HAL_SECURITY_TYPE_WEP40 = 1,
- HAL_SECURITY_TYPE_WEP104 = 2,
- HAL_SECURITY_TYPE_TKIP = 3,
- HAL_SECURITY_TYPE_AES128 = 4,
- HAL_SECURITY_TYPE_WAPI = 5,
- HAL_SECURITY_TYPE_AES256 = 6,
- HAL_SECURITY_TYPE_GCMP128 = 7,
- HAL_SECURITY_TYPE_GCMP256 = 8,
- HAL_SECURITY_TYPE_GCMSMS4 = 9,
- HAL_SECURITY_TYPE_BIP = 10,
- HAL_SECURITY_TYPE_UNDEFINE = 0x7F,
-};
-
-enum hal_intf_phy {
- HAL_INTF_PHY_USB2 = 0,
- HAL_INTF_PHY_USB3 = 1,
- HAL_INTF_PHY_PCIE_GEN1 = 2,
- HAL_INTF_PHY_PCIE_GEN2 = 3,
- HAL_INTF_PHY_UNDEFINE = 0x7F,
-};
-
-enum halmac_dbg_msg_info {
- HALMAC_DBG_ERR,
- HALMAC_DBG_WARN,
- HALMAC_DBG_TRACE,
-};
-
-enum halmac_dbg_msg_type {
- HALMAC_MSG_INIT,
- HALMAC_MSG_EFUSE,
- HALMAC_MSG_FW,
- HALMAC_MSG_H2C,
- HALMAC_MSG_PWR,
- HALMAC_MSG_SND,
- HALMAC_MSG_COMMON,
- HALMAC_MSG_DBI,
- HALMAC_MSG_MDIO,
- HALMAC_MSG_USB
-};
-
-enum halmac_cmd_process_status {
- HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
- HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
- HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
- HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
- HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
- HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
-};
-
-enum halmac_feature_id {
- HALMAC_FEATURE_CFG_PARA, /* Support */
- HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */
- HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */
- HALMAC_FEATURE_UPDATE_PACKET, /* Support */
- HALMAC_FEATURE_UPDATE_DATAPACK,
- HALMAC_FEATURE_RUN_DATAPACK,
- HALMAC_FEATURE_CHANNEL_SWITCH, /* Support */
- HALMAC_FEATURE_IQK, /* Support */
- HALMAC_FEATURE_POWER_TRACKING, /* Support */
- HALMAC_FEATURE_PSD, /* Support */
- HALMAC_FEATURE_ALL, /* Support, only for reset */
-};
-
-enum halmac_drv_rsvd_pg_num {
- HALMAC_RSVD_PG_NUM16, /* 2K */
- HALMAC_RSVD_PG_NUM24, /* 3K */
- HALMAC_RSVD_PG_NUM32, /* 4K */
-};
-
-enum halmac_pcie_cfg {
- HALMAC_PCIE_GEN1,
- HALMAC_PCIE_GEN2,
- HALMAC_PCIE_CFG_UNDEFINE,
-};
-
-enum halmac_portid {
- HALMAC_PORTID0 = 0,
- HALMAC_PORTID1 = 1,
- HALMAC_PORTID2 = 2,
- HALMAC_PORTID3 = 3,
- HALMAC_PORTID4 = 4,
- HALMAC_PORTIDMAX
-};
-
-struct halmac_p2pps {
- /*DW0*/
- u8 offload_en : 1;
- u8 role : 1;
- u8 ctwindow_en : 1;
- u8 noa_en : 1;
- u8 noa_sel : 1;
- u8 all_sta_sleep : 1;
- u8 discovery : 1;
- u8 rsvd2 : 1;
- u8 p2p_port_id;
- u8 p2p_group;
- u8 p2p_macid;
-
- /*DW1*/
- u8 ctwindow_length;
- u8 rsvd3;
- u8 rsvd4;
- u8 rsvd5;
-
- /*DW2*/
- u32 noa_duration_para;
-
- /*DW3*/
- u32 noa_interval_para;
-
- /*DW4*/
- u32 noa_start_time_para;
-
- /*DW5*/
- u32 noa_count_para;
-};
-
-/* Platform API setting */
-struct halmac_platform_api {
- /* R/W register */
- u8 (*SDIO_CMD52_READ)(void *driver_adapter, u32 offset);
- u8 (*SDIO_CMD53_READ_8)(void *driver_adapter, u32 offset);
- u16 (*SDIO_CMD53_READ_16)(void *driver_adapter, u32 offset);
- u32 (*SDIO_CMD53_READ_32)(void *driver_adapter, u32 offset);
- u8 (*SDIO_CMD53_READ_N)(void *driver_adapter, u32 offset, u32 size,
- u8 *data);
- void (*SDIO_CMD52_WRITE)(void *driver_adapter, u32 offset, u8 value);
- void (*SDIO_CMD53_WRITE_8)(void *driver_adapter, u32 offset, u8 value);
- void (*SDIO_CMD53_WRITE_16)(void *driver_adapter, u32 offset,
- u16 value);
- void (*SDIO_CMD53_WRITE_32)(void *driver_adapter, u32 offset,
- u32 value);
- u8 (*REG_READ_8)(void *driver_adapter, u32 offset);
- u16 (*REG_READ_16)(void *driver_adapter, u32 offset);
- u32 (*REG_READ_32)(void *driver_adapter, u32 offset);
- void (*REG_WRITE_8)(void *driver_adapter, u32 offset, u8 value);
- void (*REG_WRITE_16)(void *driver_adapter, u32 offset, u16 value);
- void (*REG_WRITE_32)(void *driver_adapter, u32 offset, u32 value);
-
- /* send buf to reserved page, the tx_desc is not included in buf,
- * driver need to fill tx_desc with qsel = bcn
- */
- bool (*SEND_RSVD_PAGE)(void *driver_adapter, u8 *buf, u32 size);
- /* send buf to h2c queue, the tx_desc is not included in buf,
- * driver need to fill tx_desc with qsel = h2c
- */
- bool (*SEND_H2C_PKT)(void *driver_adapter, u8 *buf, u32 size);
-
- bool (*EVENT_INDICATION)(void *driver_adapter,
- enum halmac_feature_id feature_id,
- enum halmac_cmd_process_status process_status,
- u8 *buf, u32 size);
-};
-
-/*1->Little endian 0->Big endian*/
-#if HALMAC_SYSTEM_ENDIAN
-
-#else
-
-#endif
-
-/* User can not use members in address_l_h, use address[6] is mandatory */
-union halmac_wlan_addr {
- u8 address[6]; /* WLAN address (MACID, BSSID, Brodcast ID).
- * address[0] is lowest, address[5] is highest
- */
- struct {
- union {
- u32 address_low;
- __le32 le_address_low;
- u8 address_low_b[4];
- };
- union {
- u16 address_high;
- __le16 le_address_high;
- u8 address_high_b[2];
- };
- } address_l_h;
-};
-
-enum halmac_snd_role {
- HAL_BFER = 0,
- HAL_BFEE = 1,
-};
-
-enum halmac_csi_seg_len {
- HAL_CSI_SEG_4K = 0,
- HAL_CSI_SEG_8K = 1,
- HAL_CSI_SEG_11K = 2,
-};
-
-struct halmac_cfg_mumimo_para {
- enum halmac_snd_role role;
- bool sounding_sts[6];
- u16 grouping_bitmap;
- bool mu_tx_en;
- u32 given_gid_tab[2];
- u32 given_user_pos[4];
-};
-
-struct halmac_su_bfer_init_para {
- u8 userid;
- u16 paid;
- u16 csi_para;
- union halmac_wlan_addr bfer_address;
-};
-
-struct halmac_mu_bfee_init_para {
- u8 userid;
- u16 paid;
- u32 user_position_l;
- u32 user_position_h;
-};
-
-struct halmac_mu_bfer_init_para {
- u16 paid;
- u16 csi_para;
- u16 my_aid;
- enum halmac_csi_seg_len csi_length_sel;
- union halmac_wlan_addr bfer_address;
-};
-
-struct halmac_snd_info {
- u16 paid;
- u8 userid;
- enum halmac_data_rate ndpa_rate;
- u16 csi_para;
- u16 my_aid;
- enum halmac_data_rate csi_rate;
- enum halmac_csi_seg_len csi_length_sel;
- enum halmac_snd_role role;
- union halmac_wlan_addr bfer_address;
- enum halmac_bw bw;
- u8 txbf_en;
- struct halmac_su_bfer_init_para *su_bfer_init;
- struct halmac_mu_bfer_init_para *mu_bfer_init;
- struct halmac_mu_bfee_init_para *mu_bfee_init;
-};
-
-struct halmac_cs_info {
- u8 *ch_info_buf;
- u8 *ch_info_buf_w;
- u8 extra_info_en;
- u32 buf_size; /* buffer size */
- u32 avai_buf_size; /* buffer size */
- u32 total_size;
- u32 accu_timeout;
- u32 ch_num;
-};
-
-struct halmac_restore_info {
- u32 mac_register;
- u32 value;
- u8 length;
-};
-
-struct halmac_event_trigger {
- u32 physical_efuse_map : 1;
- u32 logical_efuse_map : 1;
- u32 rsvd1 : 28;
-};
-
-struct halmac_h2c_header_info {
- u16 sub_cmd_id;
- u16 content_size;
- bool ack;
-};
-
-enum halmac_dlfw_state {
- HALMAC_DLFW_NONE = 0,
- HALMAC_DLFW_DONE = 1,
- HALMAC_GEN_INFO_SENT = 2,
- HALMAC_DLFW_UNDEFINED = 0x7F,
-};
-
-enum halmac_efuse_cmd_construct_state {
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0,
- HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1,
- HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2,
- HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3,
- HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F,
-};
-
-enum halmac_cfg_para_cmd_construct_state {
- HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F,
-};
-
-enum halmac_scan_cmd_construct_state {
- HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0,
- HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1,
- HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2,
- HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3,
- HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4,
- HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F,
-};
-
-enum halmac_api_state {
- HALMAC_API_STATE_INIT = 0,
- HALMAC_API_STATE_HALT = 1,
- HALMAC_API_STATE_UNDEFINED = 0x7F,
-};
-
-struct halmac_efuse_state_set {
- enum halmac_efuse_cmd_construct_state efuse_cmd_construct_state;
- enum halmac_cmd_process_status process_status;
- u8 fw_return_code;
- u16 seq_num;
-};
-
-struct halmac_cfg_para_state_set {
- enum halmac_cfg_para_cmd_construct_state cfg_para_cmd_construct_state;
- enum halmac_cmd_process_status process_status;
- u8 fw_return_code;
- u16 seq_num;
-};
-
-struct halmac_scan_state_set {
- enum halmac_scan_cmd_construct_state scan_cmd_construct_state;
- enum halmac_cmd_process_status process_status;
- u8 fw_return_code;
- u16 seq_num;
-};
-
-struct halmac_update_packet_state_set {
- enum halmac_cmd_process_status process_status;
- u8 fw_return_code;
- u16 seq_num;
-};
-
-struct halmac_iqk_state_set {
- enum halmac_cmd_process_status process_status;
- u8 fw_return_code;
- u16 seq_num;
-};
-
-struct halmac_power_tracking_state_set {
- enum halmac_cmd_process_status process_status;
- u8 fw_return_code;
- u16 seq_num;
-};
-
-struct halmac_psd_state_set {
- enum halmac_cmd_process_status process_status;
- u16 data_size;
- u16 segment_size;
- u8 *data;
- u8 fw_return_code;
- u16 seq_num;
-};
-
-struct halmac_state {
- struct halmac_efuse_state_set
- efuse_state_set; /* State machine + cmd process status */
- struct halmac_cfg_para_state_set
- cfg_para_state_set; /* State machine + cmd process status */
- struct halmac_scan_state_set
- scan_state_set; /* State machine + cmd process status */
- struct halmac_update_packet_state_set
- update_packet_set; /* cmd process status */
- struct halmac_iqk_state_set iqk_set; /* cmd process status */
- struct halmac_power_tracking_state_set
- power_tracking_set; /* cmd process status */
- struct halmac_psd_state_set psd_set; /* cmd process status */
- enum halmac_api_state api_state; /* Halmac api state */
- enum halmac_mac_power mac_power; /* 0 : power off, 1 : power on*/
- enum halmac_ps_state ps_state; /* power saving state */
- enum halmac_dlfw_state dlfw_state; /* download FW state */
-};
-
-struct halmac_ver {
- u8 major_ver;
- u8 prototype_ver;
- u8 minor_ver;
-};
-
-enum halmac_api_id {
- /*stuff, need to be the 1st*/
- HALMAC_API_STUFF = 0x0,
- /*stuff, need to be the 1st*/
- HALMAC_API_MAC_POWER_SWITCH = 0x1,
- HALMAC_API_DOWNLOAD_FIRMWARE = 0x2,
- HALMAC_API_CFG_MAC_ADDR = 0x3,
- HALMAC_API_CFG_BSSID = 0x4,
- HALMAC_API_CFG_MULTICAST_ADDR = 0x5,
- HALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6,
- HALMAC_API_INIT_SYSTEM_CFG = 0x7,
- HALMAC_API_INIT_TRX_CFG = 0x8,
- HALMAC_API_CFG_RX_AGGREGATION = 0x9,
- HALMAC_API_INIT_PROTOCOL_CFG = 0xA,
- HALMAC_API_INIT_EDCA_CFG = 0xB,
- HALMAC_API_CFG_OPERATION_MODE = 0xC,
- HALMAC_API_CFG_CH_BW = 0xD,
- HALMAC_API_CFG_BW = 0xE,
- HALMAC_API_INIT_WMAC_CFG = 0xF,
- HALMAC_API_INIT_MAC_CFG = 0x10,
- HALMAC_API_INIT_SDIO_CFG = 0x11,
- HALMAC_API_INIT_USB_CFG = 0x12,
- HALMAC_API_INIT_PCIE_CFG = 0x13,
- HALMAC_API_INIT_INTERFACE_CFG = 0x14,
- HALMAC_API_DEINIT_SDIO_CFG = 0x15,
- HALMAC_API_DEINIT_USB_CFG = 0x16,
- HALMAC_API_DEINIT_PCIE_CFG = 0x17,
- HALMAC_API_DEINIT_INTERFACE_CFG = 0x18,
- HALMAC_API_GET_EFUSE_SIZE = 0x19,
- HALMAC_API_DUMP_EFUSE_MAP = 0x1A,
- HALMAC_API_WRITE_EFUSE = 0x1B,
- HALMAC_API_READ_EFUSE = 0x1C,
- HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,
- HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,
- HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,
- HALMAC_API_READ_LOGICAL_EFUSE = 0x20,
- HALMAC_API_PG_EFUSE_BY_MAP = 0x21,
- HALMAC_API_GET_C2H_INFO = 0x22,
- HALMAC_API_CFG_FWLPS_OPTION = 0x23,
- HALMAC_API_CFG_FWIPS_OPTION = 0x24,
- HALMAC_API_ENTER_WOWLAN = 0x25,
- HALMAC_API_LEAVE_WOWLAN = 0x26,
- HALMAC_API_ENTER_PS = 0x27,
- HALMAC_API_LEAVE_PS = 0x28,
- HALMAC_API_H2C_LB = 0x29,
- HALMAC_API_DEBUG = 0x2A,
- HALMAC_API_CFG_PARAMETER = 0x2B,
- HALMAC_API_UPDATE_PACKET = 0x2C,
- HALMAC_API_BCN_IE_FILTER = 0x2D,
- HALMAC_API_REG_READ_8 = 0x2E,
- HALMAC_API_REG_WRITE_8 = 0x2F,
- HALMAC_API_REG_READ_16 = 0x30,
- HALMAC_API_REG_WRITE_16 = 0x31,
- HALMAC_API_REG_READ_32 = 0x32,
- HALMAC_API_REG_WRITE_32 = 0x33,
- HALMAC_API_TX_ALLOWED_SDIO = 0x34,
- HALMAC_API_SET_BULKOUT_NUM = 0x35,
- HALMAC_API_GET_SDIO_TX_ADDR = 0x36,
- HALMAC_API_GET_USB_BULKOUT_ID = 0x37,
- HALMAC_API_TIMER_2S = 0x38,
- HALMAC_API_FILL_TXDESC_CHECKSUM = 0x39,
- HALMAC_API_SEND_ORIGINAL_H2C = 0x3A,
- HALMAC_API_UPDATE_DATAPACK = 0x3B,
- HALMAC_API_RUN_DATAPACK = 0x3C,
- HALMAC_API_CFG_DRV_INFO = 0x3D,
- HALMAC_API_SEND_BT_COEX = 0x3E,
- HALMAC_API_VERIFY_PLATFORM_API = 0x3F,
- HALMAC_API_GET_FIFO_SIZE = 0x40,
- HALMAC_API_DUMP_FIFO = 0x41,
- HALMAC_API_CFG_TXBF = 0x42,
- HALMAC_API_CFG_MUMIMO = 0x43,
- HALMAC_API_CFG_SOUNDING = 0x44,
- HALMAC_API_DEL_SOUNDING = 0x45,
- HALMAC_API_SU_BFER_ENTRY_INIT = 0x46,
- HALMAC_API_SU_BFEE_ENTRY_INIT = 0x47,
- HALMAC_API_MU_BFER_ENTRY_INIT = 0x48,
- HALMAC_API_MU_BFEE_ENTRY_INIT = 0x49,
- HALMAC_API_SU_BFER_ENTRY_DEL = 0x4A,
- HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,
- HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,
- HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,
-
- HALMAC_API_ADD_CH_INFO = 0x4E,
- HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,
- HALMAC_API_CTRL_CH_SWITCH = 0x50,
- HALMAC_API_CLEAR_CH_INFO = 0x51,
-
- HALMAC_API_SEND_GENERAL_INFO = 0x52,
- HALMAC_API_START_IQK = 0x53,
- HALMAC_API_CTRL_PWR_TRACKING = 0x54,
- HALMAC_API_PSD = 0x55,
- HALMAC_API_CFG_TX_AGG_ALIGN = 0x56,
-
- HALMAC_API_QUERY_STATE = 0x57,
- HALMAC_API_RESET_FEATURE = 0x58,
- HALMAC_API_CHECK_FW_STATUS = 0x59,
- HALMAC_API_DUMP_FW_DMEM = 0x5A,
- HALMAC_API_CFG_MAX_DL_SIZE = 0x5B,
-
- HALMAC_API_INIT_OBJ = 0x5C,
- HALMAC_API_DEINIT_OBJ = 0x5D,
- HALMAC_API_CFG_LA_MODE = 0x5E,
- HALMAC_API_GET_HW_VALUE = 0x5F,
- HALMAC_API_SET_HW_VALUE = 0x60,
- HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,
- HALMAC_API_SWITCH_EFUSE_BANK = 0x62,
- HALMAC_API_WRITE_EFUSE_BT = 0x63,
- HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,
- HALMAC_API_DL_DRV_RSVD_PG = 0x65,
- HALMAC_API_PCIE_SWITCH = 0x66,
- HALMAC_API_PHY_CFG = 0x67,
- HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68,
- HALMAC_API_CFG_CSI_RATE = 0x69,
- HALMAC_API_MAX
-};
-
-struct halmac_api_record {
- enum halmac_api_id api_array[API_ARRAY_SIZE];
- u8 array_wptr;
-};
-
-enum halmac_la_mode {
- HALMAC_LA_MODE_DISABLE = 0,
- HALMAC_LA_MODE_PARTIAL = 1,
- HALMAC_LA_MODE_FULL = 2,
- HALMAC_LA_MODE_UNDEFINE = 0x7F,
-};
-
-enum halmac_rx_fifo_expanding_mode {
- HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0,
- HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1,
- HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2,
- HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3,
- HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F,
-};
-
-enum halmac_sdio_cmd53_4byte_mode {
- HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0,
- HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1,
- HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2,
- HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3,
- HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F,
-};
-
-enum halmac_usb_mode {
- HALMAC_USB_MODE_U2 = 1,
- HALMAC_USB_MODE_U3 = 2,
-};
-
-enum halmac_hw_id {
- /* Get HW value */
- HALMAC_HW_RQPN_MAPPING = 0x00,
- HALMAC_HW_EFUSE_SIZE = 0x01,
- HALMAC_HW_EEPROM_SIZE = 0x02,
- HALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03,
- HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04,
- HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05,
- HALMAC_HW_TXFIFO_SIZE = 0x06,
- HALMAC_HW_RSVD_PG_BNDY = 0x07,
- HALMAC_HW_CAM_ENTRY_NUM = 0x08,
- HALMAC_HW_IC_VERSION = 0x09,
- HALMAC_HW_PAGE_SIZE = 0x0A,
- HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0B,
- HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0C,
- HALMAC_HW_DRV_INFO_SIZE = 0x0D,
- HALMAC_HW_TXFF_ALLOCATION = 0x0E,
- HALMAC_HW_RSVD_EFUSE_SIZE = 0x0F,
- HALMAC_HW_FW_HDR_SIZE = 0x10,
- HALMAC_HW_TX_DESC_SIZE = 0x11,
- HALMAC_HW_RX_DESC_SIZE = 0x12,
- HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x13,
- /* Set HW value */
- HALMAC_HW_USB_MODE = 0x60,
- HALMAC_HW_SEQ_EN = 0x61,
- HALMAC_HW_BANDWIDTH = 0x62,
- HALMAC_HW_CHANNEL = 0x63,
- HALMAC_HW_PRI_CHANNEL_IDX = 0x64,
- HALMAC_HW_EN_BB_RF = 0x65,
- HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66,
- HALMAC_HW_AMPDU_CONFIG = 0x67,
-
- HALMAC_HW_ID_UNDEFINE = 0x7F,
-};
-
-enum halmac_efuse_bank {
- HALMAC_EFUSE_BANK_WIFI = 0,
- HALMAC_EFUSE_BANK_BT = 1,
- HALMAC_EFUSE_BANK_BT_1 = 2,
- HALMAC_EFUSE_BANK_BT_2 = 3,
- HALMAC_EFUSE_BANK_MAX,
- HALMAC_EFUSE_BANK_UNDEFINE = 0X7F,
-};
-
-struct halmac_txff_allocation {
- u16 tx_fifo_pg_num;
- u16 rsvd_pg_num;
- u16 rsvd_drv_pg_num;
- u16 ac_q_pg_num;
- u16 high_queue_pg_num;
- u16 low_queue_pg_num;
- u16 normal_queue_pg_num;
- u16 extra_queue_pg_num;
- u16 pub_queue_pg_num;
- u16 rsvd_pg_bndy;
- u16 rsvd_drv_pg_bndy;
- u16 rsvd_h2c_extra_info_pg_bndy;
- u16 rsvd_h2c_queue_pg_bndy;
- u16 rsvd_cpu_instr_pg_bndy;
- u16 rsvd_fw_txbuff_pg_bndy;
- enum halmac_la_mode la_mode;
- enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode;
-};
-
-struct halmac_rqpn_map {
- enum halmac_dma_mapping dma_map_vo;
- enum halmac_dma_mapping dma_map_vi;
- enum halmac_dma_mapping dma_map_be;
- enum halmac_dma_mapping dma_map_bk;
- enum halmac_dma_mapping dma_map_mg;
- enum halmac_dma_mapping dma_map_hi;
-};
-
-struct halmac_security_setting {
- u8 tx_encryption;
- u8 rx_decryption;
- u8 bip_enable;
-};
-
-struct halmac_cam_entry_info {
- enum hal_security_type security_type;
- u32 key[4];
- u32 key_ext[4];
- u8 mac_address[6];
- u8 unicast;
- u8 key_id;
- u8 valid;
-};
-
-struct halmac_cam_entry_format {
- u16 key_id : 2;
- u16 type : 3;
- u16 mic : 1;
- u16 grp : 1;
- u16 spp_mode : 1;
- u16 rpt_md : 1;
- u16 ext_sectype : 1;
- u16 mgnt : 1;
- u16 rsvd1 : 4;
- u16 valid : 1;
- u8 mac_address[6];
- u32 key[4];
- u32 rsvd[2];
-};
-
-struct halmac_tx_page_threshold_info {
- u32 threshold;
- enum halmac_dma_mapping dma_queue_sel;
-};
-
-struct halmac_ampdu_config {
- u8 max_agg_num;
-};
-
-struct halmac_port_cfg {
- u8 port0_sync_tsf;
- u8 port1_sync_tsf;
-};
-
-struct halmac_rqpn_ {
- enum halmac_trx_mode mode;
- enum halmac_dma_mapping dma_map_vo;
- enum halmac_dma_mapping dma_map_vi;
- enum halmac_dma_mapping dma_map_be;
- enum halmac_dma_mapping dma_map_bk;
- enum halmac_dma_mapping dma_map_mg;
- enum halmac_dma_mapping dma_map_hi;
-};
-
-struct halmac_pg_num_ {
- enum halmac_trx_mode mode;
- u16 hq_num;
- u16 nq_num;
- u16 lq_num;
- u16 exq_num;
- u16 gap_num; /*used for loopback mode*/
-};
-
-struct halmac_intf_phy_para_ {
- u16 offset;
- u16 value;
- u16 ip_sel;
- u16 cut;
- u16 plaform;
-};
-
-struct halmac_iqk_para_ {
- u8 clear;
- u8 segment_iqk;
-};
-
-/* Hal mac adapter */
-struct halmac_adapter {
- /* Dma mapping of protocol queues */
- enum halmac_dma_mapping halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM];
- /* low power state option */
- struct halmac_fwlps_option fwlps_option;
- /* mac address information, suppot 2 ports */
- union halmac_wlan_addr hal_mac_addr[HALMAC_PORTIDMAX];
- /* bss address information, suppot 2 ports */
- union halmac_wlan_addr hal_bss_addr[HALMAC_PORTIDMAX];
- /* Protect h2c_packet_seq packet*/
- spinlock_t h2c_seq_lock;
- /* Protect Efuse map memory of halmac_adapter */
- spinlock_t efuse_lock;
- struct halmac_config_para_info config_para_info;
- struct halmac_cs_info ch_sw_info;
- struct halmac_event_trigger event_trigger;
- /* HW related information */
- struct halmac_hw_config_info hw_config_info;
- struct halmac_sdio_free_space sdio_free_space;
- struct halmac_snd_info snd_info;
- /* Backup HalAdapter address */
- void *hal_adapter_backup;
- /* Driver or FW adapter address. Do not write this memory*/
- void *driver_adapter;
- u8 *hal_efuse_map;
- /* Record function pointer of halmac api */
- void *halmac_api;
- /* Record function pointer of platform api */
- struct halmac_platform_api *halmac_platform_api;
- /* Record efuse used memory */
- u32 efuse_end;
- u32 h2c_buf_free_space;
- u32 h2c_buff_size;
- u32 max_download_size;
- /* Chip ID, 8822B, 8821C... */
- enum halmac_chip_id chip_id;
- /* A cut, B cut... */
- enum halmac_chip_ver chip_version;
- struct halmac_fw_version fw_version;
- struct halmac_state halmac_state;
- /* Interface information, get from driver */
- enum halmac_interface halmac_interface;
- /* Noraml, WMM, P2P, LoopBack... */
- enum halmac_trx_mode trx_mode;
- struct halmac_txff_allocation txff_allocation;
- u8 h2c_packet_seq; /* current h2c packet sequence number */
- u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */
- bool hal_efuse_map_valid;
- u8 efuse_segment_size;
- u8 rpwm_record; /* record rpwm value */
- bool low_clk; /*LPS 32K or IPS 32K*/
- u8 halmac_bulkout_num; /* USB bulkout num */
- struct halmac_api_record api_record; /* API record */
- bool gen_info_valid;
- struct halmac_general_info general_info;
- u8 drv_info_size;
- enum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte;
-};
-
-/* Function pointer of Hal mac API */
-struct halmac_api {
- enum halmac_ret_status (*halmac_mac_power_switch)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_mac_power halmac_power);
- enum halmac_ret_status (*halmac_download_firmware)(
- struct halmac_adapter *halmac_adapter, u8 *hamacl_fw,
- u32 halmac_fw_size);
- enum halmac_ret_status (*halmac_free_download_firmware)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_dlfw_mem dlfw_mem, u8 *hamacl_fw,
- u32 halmac_fw_size);
- enum halmac_ret_status (*halmac_get_fw_version)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_fw_version *fw_version);
- enum halmac_ret_status (*halmac_cfg_mac_addr)(
- struct halmac_adapter *halmac_adapter, u8 halmac_port,
- union halmac_wlan_addr *hal_address);
- enum halmac_ret_status (*halmac_cfg_bssid)(
- struct halmac_adapter *halmac_adapter, u8 halmac_port,
- union halmac_wlan_addr *hal_address);
- enum halmac_ret_status (*halmac_cfg_multicast_addr)(
- struct halmac_adapter *halmac_adapter,
- union halmac_wlan_addr *hal_address);
- enum halmac_ret_status (*halmac_pre_init_system_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_init_system_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_init_trx_cfg)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode mode);
- enum halmac_ret_status (*halmac_init_h2c)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_cfg_rx_aggregation)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
- enum halmac_ret_status (*halmac_init_protocol_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_init_edca_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_cfg_operation_mode)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_wireless_mode wireless_mode);
- enum halmac_ret_status (*halmac_cfg_ch_bw)(
- struct halmac_adapter *halmac_adapter, u8 channel,
- enum halmac_pri_ch_idx pri_ch_idx, enum halmac_bw bw);
- enum halmac_ret_status (*halmac_cfg_bw)(
- struct halmac_adapter *halmac_adapter, enum halmac_bw bw);
- enum halmac_ret_status (*halmac_init_wmac_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_init_mac_cfg)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_trx_mode mode);
- enum halmac_ret_status (*halmac_init_sdio_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_init_usb_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_init_pcie_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_init_interface_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_deinit_sdio_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_deinit_usb_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_deinit_pcie_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_deinit_interface_cfg)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_get_efuse_size)(
- struct halmac_adapter *halmac_adapter, u32 *halmac_size);
- enum halmac_ret_status (*halmac_get_efuse_available_size)(
- struct halmac_adapter *halmac_adapter, u32 *halmac_size);
- enum halmac_ret_status (*halmac_dump_efuse_map)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_read_cfg cfg);
- enum halmac_ret_status (*halmac_dump_efuse_map_bt)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_bank halmac_efues_bank, u32 bt_efuse_map_size,
- u8 *bt_efuse_map);
- enum halmac_ret_status (*halmac_write_efuse)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset,
- u8 halmac_value);
- enum halmac_ret_status (*halmac_read_efuse)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset,
- u8 *value);
- enum halmac_ret_status (*halmac_switch_efuse_bank)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_bank halmac_efues_bank);
- enum halmac_ret_status (*halmac_write_efuse_bt)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset,
- u8 halmac_value, enum halmac_efuse_bank halmac_efues_bank);
- enum halmac_ret_status (*halmac_get_logical_efuse_size)(
- struct halmac_adapter *halmac_adapter, u32 *halmac_size);
- enum halmac_ret_status (*halmac_dump_logical_efuse_map)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_efuse_read_cfg cfg);
- enum halmac_ret_status (*halmac_write_logical_efuse)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset,
- u8 halmac_value);
- enum halmac_ret_status (*halmac_read_logical_efuse)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset,
- u8 *value);
- enum halmac_ret_status (*halmac_pg_efuse_by_map)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_pg_efuse_info *pg_efuse_info,
- enum halmac_efuse_read_cfg cfg);
- enum halmac_ret_status (*halmac_get_c2h_info)(
- struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
- u32 halmac_size);
- enum halmac_ret_status (*halmac_cfg_fwlps_option)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_fwlps_option *lps_option);
- enum halmac_ret_status (*halmac_cfg_fwips_option)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_fwips_option *ips_option);
- enum halmac_ret_status (*halmac_enter_wowlan)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_wowlan_option *wowlan_option);
- enum halmac_ret_status (*halmac_leave_wowlan)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_enter_ps)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_ps_state ps_state);
- enum halmac_ret_status (*halmac_leave_ps)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_h2c_lb)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_debug)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_cfg_parameter)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_phy_parameter_info *para_info, u8 full_fifo);
- enum halmac_ret_status (*halmac_update_packet)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_packet_id pkt_id, u8 *pkt, u32 pkt_size);
- enum halmac_ret_status (*halmac_bcn_ie_filter)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_bcn_ie_info *bcn_ie_info);
- u8 (*halmac_reg_read_8)(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
- enum halmac_ret_status (*halmac_reg_write_8)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset,
- u8 halmac_data);
- u16 (*halmac_reg_read_16)(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
- enum halmac_ret_status (*halmac_reg_write_16)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset,
- u16 halmac_data);
- u32 (*halmac_reg_read_32)(struct halmac_adapter *halmac_adapter,
- u32 halmac_offset);
- u32 (*halmac_reg_read_indirect_32)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset);
- u8 (*halmac_reg_sdio_cmd53_read_n)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset,
- u32 halmac_size, u8 *halmac_data);
- enum halmac_ret_status (*halmac_reg_write_32)(
- struct halmac_adapter *halmac_adapter, u32 halmac_offset,
- u32 halmac_data);
- enum halmac_ret_status (*halmac_tx_allowed_sdio)(
- struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
- u32 halmac_size);
- enum halmac_ret_status (*halmac_set_bulkout_num)(
- struct halmac_adapter *halmac_adapter, u8 bulkout_num);
- enum halmac_ret_status (*halmac_get_sdio_tx_addr)(
- struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
- u32 halmac_size, u32 *pcmd53_addr);
- enum halmac_ret_status (*halmac_get_usb_bulkout_id)(
- struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
- u32 halmac_size, u8 *bulkout_id);
- enum halmac_ret_status (*halmac_timer_2s)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_fill_txdesc_checksum)(
- struct halmac_adapter *halmac_adapter, u8 *cur_desc);
- enum halmac_ret_status (*halmac_update_datapack)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_data_type halmac_data_type,
- struct halmac_phy_parameter_info *para_info);
- enum halmac_ret_status (*halmac_run_datapack)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_data_type halmac_data_type);
- enum halmac_ret_status (*halmac_cfg_drv_info)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_drv_info halmac_drv_info);
- enum halmac_ret_status (*halmac_send_bt_coex)(
- struct halmac_adapter *halmac_adapter, u8 *bt_buf, u32 bt_size,
- u8 ack);
- enum halmac_ret_status (*halmac_verify_platform_api)(
- struct halmac_adapter *halmac_adapte);
- u32 (*halmac_get_fifo_size)(struct halmac_adapter *halmac_adapter,
- enum hal_fifo_sel halmac_fifo_sel);
- enum halmac_ret_status (*halmac_dump_fifo)(
- struct halmac_adapter *halmac_adapter,
- enum hal_fifo_sel halmac_fifo_sel, u32 halmac_start_addr,
- u32 halmac_fifo_dump_size, u8 *fifo_map);
- enum halmac_ret_status (*halmac_cfg_txbf)(
- struct halmac_adapter *halmac_adapter, u8 userid,
- enum halmac_bw bw, u8 txbf_en);
- enum halmac_ret_status (*halmac_cfg_mumimo)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_cfg_mumimo_para *cfgmu);
- enum halmac_ret_status (*halmac_cfg_sounding)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_snd_role role, enum halmac_data_rate datarate);
- enum halmac_ret_status (*halmac_del_sounding)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_snd_role role);
- enum halmac_ret_status (*halmac_su_bfer_entry_init)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_su_bfer_init_para *su_bfer_init);
- enum halmac_ret_status (*halmac_su_bfee_entry_init)(
- struct halmac_adapter *halmac_adapter, u8 userid, u16 paid);
- enum halmac_ret_status (*halmac_mu_bfer_entry_init)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_mu_bfer_init_para *mu_bfer_init);
- enum halmac_ret_status (*halmac_mu_bfee_entry_init)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_mu_bfee_init_para *mu_bfee_init);
- enum halmac_ret_status (*halmac_su_bfer_entry_del)(
- struct halmac_adapter *halmac_adapter, u8 userid);
- enum halmac_ret_status (*halmac_su_bfee_entry_del)(
- struct halmac_adapter *halmac_adapter, u8 userid);
- enum halmac_ret_status (*halmac_mu_bfer_entry_del)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_mu_bfee_entry_del)(
- struct halmac_adapter *halmac_adapter, u8 userid);
- enum halmac_ret_status (*halmac_add_ch_info)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_ch_info *ch_info);
- enum halmac_ret_status (*halmac_add_extra_ch_info)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_ch_extra_info *ch_extra_info);
- enum halmac_ret_status (*halmac_ctrl_ch_switch)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_ch_switch_option *cs_option);
- enum halmac_ret_status (*halmac_p2pps)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_p2pps *p2p_ps);
- enum halmac_ret_status (*halmac_clear_ch_info)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_send_general_info)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_general_info *pg_general_info);
- enum halmac_ret_status (*halmac_start_iqk)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_iqk_para_ *iqk_para);
- enum halmac_ret_status (*halmac_ctrl_pwr_tracking)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_pwr_tracking_option *pwr_tracking_opt);
- enum halmac_ret_status (*halmac_psd)(
- struct halmac_adapter *halmac_adapter, u16 start_psd,
- u16 end_psd);
- enum halmac_ret_status (*halmac_cfg_tx_agg_align)(
- struct halmac_adapter *halmac_adapter, u8 enable,
- u16 align_size);
- enum halmac_ret_status (*halmac_query_status)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_feature_id feature_id,
- enum halmac_cmd_process_status *process_status, u8 *data,
- u32 *size);
- enum halmac_ret_status (*halmac_reset_feature)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_feature_id feature_id);
- enum halmac_ret_status (*halmac_check_fw_status)(
- struct halmac_adapter *halmac_adapter, bool *fw_status);
- enum halmac_ret_status (*halmac_dump_fw_dmem)(
- struct halmac_adapter *halmac_adapter, u8 *dmem, u32 *size);
- enum halmac_ret_status (*halmac_cfg_max_dl_size)(
- struct halmac_adapter *halmac_adapter, u32 size);
- enum halmac_ret_status (*halmac_cfg_la_mode)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_la_mode la_mode);
- enum halmac_ret_status (*halmac_cfg_rx_fifo_expanding_mode)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode);
- enum halmac_ret_status (*halmac_config_security)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_security_setting *sec_setting);
- u8 (*halmac_get_used_cam_entry_num)(
- struct halmac_adapter *halmac_adapter,
- enum hal_security_type sec_type);
- enum halmac_ret_status (*halmac_write_cam)(
- struct halmac_adapter *halmac_adapter, u32 entry_index,
- struct halmac_cam_entry_info *cam_entry_info);
- enum halmac_ret_status (*halmac_read_cam_entry)(
- struct halmac_adapter *halmac_adapter, u32 entry_index,
- struct halmac_cam_entry_format *content);
- enum halmac_ret_status (*halmac_clear_cam_entry)(
- struct halmac_adapter *halmac_adapter, u32 entry_index);
- enum halmac_ret_status (*halmac_get_hw_value)(
- struct halmac_adapter *halmac_adapter, enum halmac_hw_id hw_id,
- void *pvalue);
- enum halmac_ret_status (*halmac_set_hw_value)(
- struct halmac_adapter *halmac_adapter, enum halmac_hw_id hw_id,
- void *pvalue);
- enum halmac_ret_status (*halmac_cfg_drv_rsvd_pg_num)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_drv_rsvd_pg_num pg_num);
- enum halmac_ret_status (*halmac_get_chip_version)(
- struct halmac_adapter *halmac_adapter,
- struct halmac_ver *version);
- enum halmac_ret_status (*halmac_chk_txdesc)(
- struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
- u32 halmac_size);
- enum halmac_ret_status (*halmac_dl_drv_rsvd_page)(
- struct halmac_adapter *halmac_adapter, u8 pg_offset,
- u8 *hal_buf, u32 size);
- enum halmac_ret_status (*halmac_pcie_switch)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_pcie_cfg pcie_cfg);
- enum halmac_ret_status (*halmac_phy_cfg)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_intf_phy_platform platform);
- enum halmac_ret_status (*halmac_cfg_csi_rate)(
- struct halmac_adapter *halmac_adapter, u8 rssi, u8 current_rate,
- u8 fixrate_en, u8 *new_rate);
- enum halmac_ret_status (*halmac_sdio_cmd53_4byte)(
- struct halmac_adapter *halmac_adapter,
- enum halmac_sdio_cmd53_4byte_mode cmd53_4byte_mode);
- enum halmac_ret_status (*halmac_interface_integration_tuning)(
- struct halmac_adapter *halmac_adapter);
- enum halmac_ret_status (*halmac_txfifo_is_empty)(
- struct halmac_adapter *halmac_adapter, u32 chk_num);
-};
-
-#define HALMAC_GET_API(phalmac_adapter) \
- ((struct halmac_api *)phalmac_adapter->halmac_api)
-
-static inline enum halmac_ret_status
-halmac_adapter_validate(struct halmac_adapter *halmac_adapter)
-{
- if ((!halmac_adapter) ||
- (halmac_adapter->hal_adapter_backup != halmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- return HALMAC_RET_SUCCESS;
-}
-
-static inline enum halmac_ret_status
-halmac_api_validate(struct halmac_adapter *halmac_adapter)
-{
- if (halmac_adapter->halmac_state.api_state != HALMAC_API_STATE_INIT)
- return HALMAC_RET_API_INVALID;
-
- return HALMAC_RET_SUCCESS;
-}
-
-static inline enum halmac_ret_status
-halmac_fw_validate(struct halmac_adapter *halmac_adapter)
-{
- if (halmac_adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE &&
- halmac_adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT)
- return HALMAC_RET_NO_DLFW;
-
- return HALMAC_RET_SUCCESS;
-}
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __HALMAC_USB_REG_H__
-#define __HALMAC_USB_REG_H__
-
-#endif /* __HALMAC_USB_REG_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "halmac_api.h"
-#include "rtl_halmac.h"
-#include <linux/module.h>
-#include <linux/vmalloc.h>
-
-#define DEFAULT_INDICATOR_TIMELMT msecs_to_jiffies(1000) /* ms */
-#define FIRMWARE_MAX_SIZE HALMAC_FW_SIZE_MAX_88XX
-
-static struct rtl_halmac_ops rtl_halmac_operation = {
- .halmac_init_adapter = rtl_halmac_init_adapter,
- .halmac_deinit_adapter = rtl_halmac_deinit_adapter,
- .halmac_init_hal = rtl_halmac_init_hal,
- .halmac_deinit_hal = rtl_halmac_deinit_hal,
- .halmac_poweron = rtl_halmac_poweron,
- .halmac_poweroff = rtl_halmac_poweroff,
-
- .halmac_phy_power_switch = rtl_halmac_phy_power_switch,
- .halmac_set_mac_address = rtl_halmac_set_mac_address,
- .halmac_set_bssid = rtl_halmac_set_bssid,
-
- .halmac_get_physical_efuse_size = rtl_halmac_get_physical_efuse_size,
- .halmac_read_physical_efuse_map = rtl_halmac_read_physical_efuse_map,
- .halmac_get_logical_efuse_size = rtl_halmac_get_logical_efuse_size,
- .halmac_read_logical_efuse_map = rtl_halmac_read_logical_efuse_map,
-
- .halmac_set_bandwidth = rtl_halmac_set_bandwidth,
-
- .halmac_c2h_handle = rtl_halmac_c2h_handle,
-
- .halmac_chk_txdesc = rtl_halmac_chk_txdesc,
-};
-
-struct rtl_halmac_ops *rtl_halmac_get_ops_pointer(void)
-{
- return &rtl_halmac_operation;
-}
-EXPORT_SYMBOL(rtl_halmac_get_ops_pointer);
-
-/*
- * Driver API for HALMAC operations
- */
-
-static u8 _halmac_reg_read_8(void *p, u32 offset)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
-
- return rtl_read_byte(rtlpriv, offset);
-}
-
-static u16 _halmac_reg_read_16(void *p, u32 offset)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
-
- return rtl_read_word(rtlpriv, offset);
-}
-
-static u32 _halmac_reg_read_32(void *p, u32 offset)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
-
- return rtl_read_dword(rtlpriv, offset);
-}
-
-static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
-
- rtl_write_byte(rtlpriv, offset, val);
-}
-
-static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
-
- rtl_write_word(rtlpriv, offset, val);
-}
-
-static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
-
- rtl_write_dword(rtlpriv, offset, val);
-}
-
-static bool _halmac_write_data_rsvd_page(void *p, u8 *buf, u32 size)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
-
- if (rtlpriv->cfg->ops->halmac_cb_write_data_rsvd_page &&
- rtlpriv->cfg->ops->halmac_cb_write_data_rsvd_page(rtlpriv, buf,
- size))
- return true;
-
- return false;
-}
-
-static bool _halmac_write_data_h2c(void *p, u8 *buf, u32 size)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
-
- if (rtlpriv->cfg->ops->halmac_cb_write_data_h2c &&
- rtlpriv->cfg->ops->halmac_cb_write_data_h2c(rtlpriv, buf, size))
- return true;
-
- return false;
-}
-
-static const char *const RTL_HALMAC_FEATURE_NAME[] = {
- "HALMAC_FEATURE_CFG_PARA",
- "HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE",
- "HALMAC_FEATURE_DUMP_LOGICAL_EFUSE",
- "HALMAC_FEATURE_UPDATE_PACKET",
- "HALMAC_FEATURE_UPDATE_DATAPACK",
- "HALMAC_FEATURE_RUN_DATAPACK",
- "HALMAC_FEATURE_CHANNEL_SWITCH",
- "HALMAC_FEATURE_IQK",
- "HALMAC_FEATURE_POWER_TRACKING",
- "HALMAC_FEATURE_PSD",
- "HALMAC_FEATURE_ALL"};
-
-static inline bool is_valid_id_status(struct rtl_priv *rtlpriv,
- enum halmac_feature_id id,
- enum halmac_cmd_process_status status)
-{
- switch (id) {
- case HALMAC_FEATURE_CFG_PARA:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- break;
- case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- if (status != HALMAC_CMD_PROCESS_DONE) {
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
- "%s: <WARN> id(%d) unspecified status(%d)!\n",
- __func__, id, status);
- }
- break;
- case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- if (status != HALMAC_CMD_PROCESS_DONE) {
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
- "%s: <WARN> id(%d) unspecified status(%d)!\n",
- __func__, id, status);
- }
- break;
- case HALMAC_FEATURE_UPDATE_PACKET:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- break;
- case HALMAC_FEATURE_UPDATE_DATAPACK:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- break;
- case HALMAC_FEATURE_RUN_DATAPACK:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- break;
- case HALMAC_FEATURE_CHANNEL_SWITCH:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- break;
- case HALMAC_FEATURE_IQK:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- break;
- case HALMAC_FEATURE_POWER_TRACKING:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- break;
- case HALMAC_FEATURE_PSD:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- break;
- case HALMAC_FEATURE_ALL:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
- RTL_HALMAC_FEATURE_NAME[id]);
- break;
- default:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
- "%s: unknown feature id(%d)\n", __func__, id);
- return false;
- }
-
- return true;
-}
-
-static int init_halmac_event_with_waittime(struct rtl_priv *rtlpriv,
- enum halmac_feature_id id, u8 *buf,
- u32 size, u32 time)
-{
- struct completion *comp;
-
- if (!rtlpriv->halmac.indicator[id].comp) {
- comp = kzalloc(sizeof(*comp), GFP_KERNEL);
- if (!comp)
- return -ENOMEM;
- } else {
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
- "%s: <WARN> id(%d) sctx is not NULL!!\n", __func__,
- id);
- comp = rtlpriv->halmac.indicator[id].comp;
- rtlpriv->halmac.indicator[id].comp = NULL;
- }
-
- init_completion(comp);
- rtlpriv->halmac.indicator[id].wait_ms = time;
-
- rtlpriv->halmac.indicator[id].buffer = buf;
- rtlpriv->halmac.indicator[id].buf_size = size;
- rtlpriv->halmac.indicator[id].ret_size = 0;
- rtlpriv->halmac.indicator[id].status = 0;
- /* fill sctx at least to sure other variables are all ready! */
- rtlpriv->halmac.indicator[id].comp = comp;
-
- return 0;
-}
-
-static inline int init_halmac_event(struct rtl_priv *rtlpriv,
- enum halmac_feature_id id, u8 *buf,
- u32 size)
-{
- return init_halmac_event_with_waittime(rtlpriv, id, buf, size,
- DEFAULT_INDICATOR_TIMELMT);
-}
-
-static void free_halmac_event(struct rtl_priv *rtlpriv,
- enum halmac_feature_id id)
-{
- struct completion *comp;
-
- if (!rtlpriv->halmac.indicator[id].comp)
- return;
-
- comp = rtlpriv->halmac.indicator[id].comp;
- rtlpriv->halmac.indicator[id].comp = NULL;
- kfree(comp);
-}
-
-static int wait_halmac_event(struct rtl_priv *rtlpriv,
- enum halmac_feature_id id)
-{
- struct completion *comp;
- int ret;
-
- comp = rtlpriv->halmac.indicator[id].comp;
- if (!comp)
- return -1;
-
- ret = wait_for_completion_timeout(
- comp, rtlpriv->halmac.indicator[id].wait_ms);
- free_halmac_event(rtlpriv, id);
- if (ret > 0)
- return 0;
-
- return -1;
-}
-
-/*
- * Return:
- * Always return true, HALMAC don't care the return value.
- */
-static bool
-_halmac_event_indication(void *p, enum halmac_feature_id feature_id,
- enum halmac_cmd_process_status process_status, u8 *buf,
- u32 size)
-{
- struct rtl_priv *rtlpriv;
- struct rtl_halmac_indicator *tbl, *indicator;
- struct completion *comp;
- u32 cpsz;
- bool ret;
-
- rtlpriv = (struct rtl_priv *)p;
- tbl = rtlpriv->halmac.indicator;
-
- ret = is_valid_id_status(rtlpriv, feature_id, process_status);
- if (!ret)
- goto exit;
-
- indicator = &tbl[feature_id];
- indicator->status = process_status;
- indicator->ret_size = size;
- if (!indicator->comp) {
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
- "%s: No feature id(%d) waiting!!\n", __func__,
- feature_id);
- goto exit;
- }
- comp = indicator->comp;
-
- if (process_status == HALMAC_CMD_PROCESS_ERROR) {
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
- "%s: Something wrong id(%d)!!\n", __func__,
- feature_id);
- complete(comp); /* may provide error code */
- goto exit;
- }
-
- if (size > indicator->buf_size) {
- RT_TRACE(
- rtlpriv, COMP_HALMAC, DBG_LOUD,
- "%s: <WARN> id(%d) buffer is not enough(%d<%d), data will be truncated!\n",
- __func__, feature_id, indicator->buf_size, size);
- cpsz = indicator->buf_size;
- } else {
- cpsz = size;
- }
-
- if (cpsz && indicator->buffer)
- memcpy(indicator->buffer, buf, cpsz);
-
- complete(comp);
-
-exit:
- return true;
-}
-
-static struct halmac_platform_api rtl_halmac_platform_api = {
- /* R/W register */
- .REG_READ_8 = _halmac_reg_read_8,
- .REG_READ_16 = _halmac_reg_read_16,
- .REG_READ_32 = _halmac_reg_read_32,
- .REG_WRITE_8 = _halmac_reg_write_8,
- .REG_WRITE_16 = _halmac_reg_write_16,
- .REG_WRITE_32 = _halmac_reg_write_32,
-
- /* Write data */
- /* impletement in HAL-IC level */
- .SEND_RSVD_PAGE = _halmac_write_data_rsvd_page,
- .SEND_H2C_PKT = _halmac_write_data_h2c,
-
- .EVENT_INDICATION = _halmac_event_indication,
-};
-
-static int init_priv(struct rtl_halmac *halmac)
-{
- struct rtl_halmac_indicator *indicator;
- u32 count, size;
-
- halmac->send_general_info = 0;
-
- count = HALMAC_FEATURE_ALL + 1;
- size = sizeof(*indicator) * count;
- indicator = kzalloc(size, GFP_KERNEL);
- if (!indicator)
- return -ENOMEM;
- halmac->indicator = indicator;
-
- return 0;
-}
-
-static void deinit_priv(struct rtl_halmac *halmac)
-{
- struct rtl_halmac_indicator *indicator;
-
- indicator = halmac->indicator;
- halmac->indicator = NULL;
- kfree(indicator);
-}
-
-int rtl_halmac_init_adapter(struct rtl_priv *rtlpriv)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- enum halmac_interface intf;
- enum halmac_ret_status status;
- int err = 0;
- struct halmac_platform_api *pf_api = &rtl_halmac_platform_api;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- if (halmac) {
- err = 0;
- goto out;
- }
-
- err = init_priv(&rtlpriv->halmac);
- if (err)
- goto out;
-
- intf = HALMAC_INTERFACE_PCIE;
- status = halmac_init_adapter(rtlpriv, pf_api, intf, &halmac, &api);
- if (status != HALMAC_RET_SUCCESS) {
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
- "%s: halmac_init_adapter fail!(status=%d)\n", __func__,
- status);
- err = -1;
- goto out;
- }
-
- rtlpriv->halmac.internal = halmac;
-
-out:
- if (err)
- rtl_halmac_deinit_adapter(rtlpriv);
-
- return err;
-}
-
-int rtl_halmac_deinit_adapter(struct rtl_priv *rtlpriv)
-{
- struct halmac_adapter *halmac;
- enum halmac_ret_status status;
- int err = 0;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- if (!halmac) {
- err = 0;
- goto out;
- }
-
- deinit_priv(&rtlpriv->halmac);
-
- halmac_halt_api(halmac);
-
- status = halmac_deinit_adapter(halmac);
- rtlpriv->halmac.internal = NULL;
- if (status != HALMAC_RET_SUCCESS) {
- err = -1;
- goto out;
- }
-
-out:
- return err;
-}
-
-int rtl_halmac_poweron(struct rtl_priv *rtlpriv)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- int err = -1;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- if (!halmac)
- goto out;
-
- api = HALMAC_GET_API(halmac);
-
- status = api->halmac_pre_init_system_cfg(halmac);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- status = api->halmac_init_system_cfg(halmac);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- err = 0;
-out:
- return err;
-}
-
-int rtl_halmac_poweroff(struct rtl_priv *rtlpriv)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- int err = -1;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- if (!halmac)
- goto out;
-
- api = HALMAC_GET_API(halmac);
-
- status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- err = 0;
-out:
- return err;
-}
-
-/*
- * Note:
- * When this function return, the register REG_RCR may be changed.
- */
-int rtl_halmac_config_rx_info(struct rtl_priv *rtlpriv,
- enum halmac_drv_info info)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- int err = -1;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(halmac);
-
- status = api->halmac_cfg_drv_info(halmac, info);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- err = 0;
-out:
- return err;
-}
-
-static enum halmac_ret_status init_mac_flow(struct rtl_priv *rtlpriv)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- u8 wifi_test = 0;
- int err;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(halmac);
-
- if (wifi_test)
- status = api->halmac_init_mac_cfg(halmac, HALMAC_TRX_MODE_WMM);
- else
- status = api->halmac_init_mac_cfg(halmac,
- HALMAC_TRX_MODE_NORMAL);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- err = rtl_halmac_rx_agg_switch(rtlpriv, true);
- if (err)
- goto out;
-
- if (rtlpriv->cfg->maps[RTL_RC_VHT_RATE_1SS_MCS7])
- status = api->halmac_cfg_operation_mode(
- halmac, HALMAC_WIRELESS_MODE_AC);
- else if (rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS7])
- status = api->halmac_cfg_operation_mode(halmac,
- HALMAC_WIRELESS_MODE_N);
- else if (rtlpriv->cfg->maps[RTL_RC_OFDM_RATE6M])
- status = api->halmac_cfg_operation_mode(halmac,
- HALMAC_WIRELESS_MODE_G);
- else
- status = api->halmac_cfg_operation_mode(halmac,
- HALMAC_WIRELESS_MODE_B);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
-out:
- return status;
-}
-
-static inline enum halmac_rf_type _rf_type_drv2halmac(enum rf_type rf_drv)
-{
- enum halmac_rf_type rf_mac;
-
- switch (rf_drv) {
- case RF_1T2R:
- rf_mac = HALMAC_RF_1T2R;
- break;
- case RF_2T2R:
- rf_mac = HALMAC_RF_2T2R;
- break;
- case RF_1T1R:
- rf_mac = HALMAC_RF_1T1R;
- break;
- case RF_2T2R_GREEN:
- rf_mac = HALMAC_RF_2T2R_GREEN;
- break;
- default:
- rf_mac = (enum halmac_rf_type)rf_drv;
- break;
- }
-
- return rf_mac;
-}
-
-static int _send_general_info(struct rtl_priv *rtlpriv)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- struct halmac_general_info info;
- enum halmac_ret_status status;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- if (!halmac)
- return -1;
- api = HALMAC_GET_API(halmac);
-
- memset(&info, 0, sizeof(info));
- info.rfe_type = rtlpriv->rtlhal.rfe_type;
- info.rf_type = _rf_type_drv2halmac(rtlpriv->phy.rf_type);
-
- status = api->halmac_send_general_info(halmac, &info);
- switch (status) {
- case HALMAC_RET_SUCCESS:
- break;
- case HALMAC_RET_NO_DLFW:
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_WARNING,
- "%s: halmac_send_general_info() fail because fw not dl!\n",
- __func__);
- /* fall through */
- default:
- return -1;
- }
-
- return 0;
-}
-
-/*
- * Notices:
- * Make sure
- * 1. rtl_hal_get_hwreg(HW_VAR_RF_TYPE)
- * 2. HAL_DATA_TYPE.rfe_type
- * already ready for use before calling this function.
- */
-static int _halmac_init_hal(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- bool ok;
- bool fw_ok = false;
- int err, err_ret = -1;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- if (!halmac)
- goto out;
- api = HALMAC_GET_API(halmac);
-
- /* StatePowerOff */
-
- /* SKIP: halmac_init_adapter (Already done before) */
-
- /* halmac_pre_Init_system_cfg */
- /* halmac_mac_power_switch(on) */
- /* halmac_Init_system_cfg */
- err = rtl_halmac_poweron(rtlpriv);
- if (err)
- goto out;
-
- /* StatePowerOn */
-
- /* DownloadFW */
- rtlpriv->halmac.send_general_info = 0;
- if (fw && fwsize) {
- err = rtl_halmac_dlfw(rtlpriv, fw, fwsize);
- if (err)
- goto out;
- fw_ok = true;
- }
-
- /* InitMACFlow */
- status = init_mac_flow(rtlpriv);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- /* halmac_send_general_info */
- if (fw_ok) {
- rtlpriv->halmac.send_general_info = 0;
- err = _send_general_info(rtlpriv);
- if (err)
- goto out;
- } else {
- rtlpriv->halmac.send_general_info = 1;
- }
-
- /* Init Phy parameter-MAC */
- if (rtlpriv->cfg->ops->halmac_cb_init_mac_register)
- ok = rtlpriv->cfg->ops->halmac_cb_init_mac_register(rtlpriv);
- else
- ok = false;
-
- if (!ok)
- goto out;
-
- /* StateMacInitialized */
-
- /* halmac_cfg_drv_info */
- err = rtl_halmac_config_rx_info(rtlpriv, HALMAC_DRV_INFO_PHY_STATUS);
- if (err)
- goto out;
-
- /* halmac_set_hw_value(HALMAC_HW_EN_BB_RF) */
- /* Init BB, RF */
- if (rtlpriv->cfg->ops->halmac_cb_init_bb_rf_register)
- ok = rtlpriv->cfg->ops->halmac_cb_init_bb_rf_register(rtlpriv);
- else
- ok = false;
-
- if (!ok)
- goto out;
-
- status = api->halmac_init_interface_cfg(halmac);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- /* SKIP: halmac_verify_platform_api */
- /* SKIP: halmac_h2c_lb */
-
- /* StateRxIdle */
-
- err_ret = 0;
-out:
- return err_ret;
-}
-
-int rtl_halmac_init_hal(struct rtl_priv *rtlpriv)
-{
- if (!rtlpriv->rtlhal.pfirmware || rtlpriv->rtlhal.fwsize == 0)
- return -1;
-
- return _halmac_init_hal(rtlpriv, rtlpriv->rtlhal.pfirmware,
- rtlpriv->rtlhal.fwsize);
-}
-
-int rtl_halmac_deinit_hal(struct rtl_priv *rtlpriv)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- int err = -1;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- if (!halmac)
- goto out;
- api = HALMAC_GET_API(halmac);
-
- status = api->halmac_deinit_interface_cfg(halmac);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- /* rtw_hal_power_off(adapter); */
- status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- err = 0;
-out:
- return err;
-}
-
-int rtl_halmac_self_verify(struct rtl_priv *rtlpriv)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- int err = -1;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- status = api->halmac_verify_platform_api(mac);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- status = api->halmac_h2c_lb(mac);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- err = 0;
-out:
- return err;
-}
-
-int rtl_halmac_dlfw(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- struct halmac_fw_version fw_version;
- int err = 0;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- if ((!fw) || (!fwsize))
- return -1;
-
- /* 1. Driver Stop Tx */
- /* ToDo */
-
- /* 2. Driver Check Tx FIFO is empty */
- /* ToDo */
-
- /* 3. Config MAX download size */
- api->halmac_cfg_max_dl_size(mac, 0x1000);
-
- /* 4. Download Firmware */
- mac->h2c_packet_seq = 0;
- status = api->halmac_download_firmware(mac, fw, fwsize);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- status = api->halmac_get_fw_version(mac, &fw_version);
- if (status == HALMAC_RET_SUCCESS) {
- rtlpriv->rtlhal.fw_version = fw_version.version;
- rtlpriv->rtlhal.fw_subversion =
- (fw_version.sub_version << 8) | (fw_version.sub_index);
-
- RT_TRACE(
- rtlpriv, COMP_HALMAC, DBG_DMESG,
- "halmac report firmware version %04X.%04X\n",
- rtlpriv->rtlhal.fw_version,
- rtlpriv->rtlhal.fw_subversion);
- }
-
- if (rtlpriv->halmac.send_general_info) {
- rtlpriv->halmac.send_general_info = 0;
- err = _send_general_info(rtlpriv);
- }
-
- /* 5. Driver resume TX if needed */
- /* ToDo */
-
- /* 6. Reset driver variables if needed */
- /*hal->LastHMEBoxNum = 0;*/
-
- return err;
-}
-
-/*
- * Description:
- * Power on/off BB/RF domain.
- *
- * Parameters:
- * enable true/false for power on/off
- *
- * Return:
- * 0 Success
- * others Fail
- */
-int rtl_halmac_phy_power_switch(struct rtl_priv *rtlpriv, u8 enable)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- enum halmac_ret_status status;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- if (!halmac)
- return -1;
- api = HALMAC_GET_API(halmac);
-
- status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &enable);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- return 0;
-}
-
-static bool _is_fw_read_cmd_down(struct rtl_priv *rtlpriv, u8 msgbox_num)
-{
- bool read_down = false;
- int retry_cnts = 100;
- u8 valid;
-
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
- "%s, reg_1cc(%x), msg_box(%d)...\n", __func__,
- rtl_read_byte(rtlpriv, REG_HMETFR), msgbox_num);
-
- do {
- valid = rtl_read_byte(rtlpriv, REG_HMETFR) & BIT(msgbox_num);
- if (valid == 0)
- read_down = true;
- else
- mdelay(1);
- } while ((!read_down) && (retry_cnts--));
-
- return read_down;
-}
-
-int rtl_halmac_send_h2c(struct rtl_priv *rtlpriv, u8 *h2c)
-{
- u8 h2c_box_num = 0;
- u32 msgbox_addr = 0;
- u32 msgbox_ex_addr = 0;
- __le32 h2c_cmd = 0;
- __le32 h2c_cmd_ex = 0;
- s32 ret = -1;
- unsigned long flag = 0;
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
-
- if (!h2c) {
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: pbuf is NULL\n",
- __func__);
- return ret;
- }
-
- spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
-
- /* pay attention to if race condition happened in H2C cmd setting */
- h2c_box_num = rtlhal->last_hmeboxnum;
-
- if (!_is_fw_read_cmd_down(rtlpriv, h2c_box_num)) {
- RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
- " fw read cmd failed...\n");
- goto exit;
- }
-
- /* Write Ext command(byte 4 -7) */
- msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
- memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE);
- rtl_write_dword(rtlpriv, msgbox_ex_addr, le32_to_cpu(h2c_cmd_ex));
-
- /* Write command (byte 0 -3 ) */
- msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE);
- memcpy((u8 *)(&h2c_cmd), h2c, 4);
- rtl_write_dword(rtlpriv, msgbox_addr, le32_to_cpu(h2c_cmd));
-
- /* update last msg box number */
- rtlhal->last_hmeboxnum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
- ret = 0;
-
-exit:
- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
- return ret;
-}
-
-int rtl_halmac_c2h_handle(struct rtl_priv *rtlpriv, u8 *c2h, u32 size)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- status = api->halmac_get_c2h_info(mac, c2h, size);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- return 0;
-}
-
-int rtl_halmac_get_physical_efuse_size(struct rtl_priv *rtlpriv, u32 *size)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- u32 val;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- status = api->halmac_get_efuse_size(mac, &val);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- *size = val;
- return 0;
-}
-
-int rtl_halmac_read_physical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
- u32 size)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- enum halmac_feature_id id;
- int ret;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
- id = HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE;
-
- ret = init_halmac_event(rtlpriv, id, map, size);
- if (ret)
- return -1;
-
- status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_DRV);
- if (status != HALMAC_RET_SUCCESS) {
- free_halmac_event(rtlpriv, id);
- return -1;
- }
-
- ret = wait_halmac_event(rtlpriv, id);
- if (ret)
- return -1;
-
- return 0;
-}
-
-int rtl_halmac_read_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
- u32 cnt, u8 *data)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- u8 v;
- u32 i;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- for (i = 0; i < cnt; i++) {
- status = api->halmac_read_efuse(mac, offset + i, &v);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
- data[i] = v;
- }
-
- return 0;
-}
-
-int rtl_halmac_write_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
- u32 cnt, u8 *data)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- u32 i;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- for (i = 0; i < cnt; i++) {
- status = api->halmac_write_efuse(mac, offset + i, data[i]);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
- }
-
- return 0;
-}
-
-int rtl_halmac_get_logical_efuse_size(struct rtl_priv *rtlpriv, u32 *size)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- u32 val;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- status = api->halmac_get_logical_efuse_size(mac, &val);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- *size = val;
- return 0;
-}
-
-int rtl_halmac_read_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
- u32 size)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- enum halmac_feature_id id;
- int ret;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
- id = HALMAC_FEATURE_DUMP_LOGICAL_EFUSE;
-
- ret = init_halmac_event(rtlpriv, id, map, size);
- if (ret)
- return -1;
-
- status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_AUTO);
- if (status != HALMAC_RET_SUCCESS) {
- free_halmac_event(rtlpriv, id);
- return -1;
- }
-
- ret = wait_halmac_event(rtlpriv, id);
- if (ret)
- return -1;
-
- return 0;
-}
-
-int rtl_halmac_write_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
- u32 size, u8 *maskmap, u32 masksize)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- struct halmac_pg_efuse_info pginfo;
- enum halmac_ret_status status;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- pginfo.efuse_map = map;
- pginfo.efuse_map_size = size;
- pginfo.efuse_mask = maskmap;
- pginfo.efuse_mask_size = masksize;
-
- status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- return 0;
-}
-
-int rtl_halmac_read_logical_efuse(struct rtl_priv *rtlpriv, u32 offset, u32 cnt,
- u8 *data)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- u8 v;
- u32 i;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- for (i = 0; i < cnt; i++) {
- status = api->halmac_read_logical_efuse(mac, offset + i, &v);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
- data[i] = v;
- }
-
- return 0;
-}
-
-int rtl_halmac_write_logical_efuse(struct rtl_priv *rtlpriv, u32 offset,
- u32 cnt, u8 *data)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- u32 i;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- for (i = 0; i < cnt; i++) {
- status = api->halmac_write_logical_efuse(mac, offset + i,
- data[i]);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
- }
-
- return 0;
-}
-
-int rtl_halmac_set_mac_address(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- u8 port;
- union halmac_wlan_addr hwa;
- enum halmac_ret_status status;
- int err = -1;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(halmac);
-
- port = hwport;
- memset(&hwa, 0, sizeof(hwa));
- memcpy(hwa.address, addr, 6);
-
- status = api->halmac_cfg_mac_addr(halmac, port, &hwa);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- err = 0;
-out:
- return err;
-}
-
-int rtl_halmac_set_bssid(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- u8 port;
- union halmac_wlan_addr hwa;
- enum halmac_ret_status status;
- int err = -1;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(halmac);
- port = hwport;
-
- memset(&hwa, 0, sizeof(union halmac_wlan_addr));
- memcpy(hwa.address, addr, 6);
- status = api->halmac_cfg_bssid(halmac, port, &hwa);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- err = 0;
-out:
- return err;
-}
-
-int rtl_halmac_set_bandwidth(struct rtl_priv *rtlpriv, u8 channel,
- u8 pri_ch_idx, u8 bw)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- return 0;
-}
-
-int rtl_halmac_get_hw_value(struct rtl_priv *rtlpriv, enum halmac_hw_id hw_id,
- void *pvalue)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- status = api->halmac_get_hw_value(mac, hw_id, pvalue);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- return 0;
-}
-
-int rtl_halmac_dump_fifo(struct rtl_priv *rtlpriv,
- enum hal_fifo_sel halmac_fifo_sel)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
- u8 *pfifo_map = NULL;
- u32 fifo_size = 0;
- s8 ret = 0;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel);
- if (fifo_size)
- pfifo_map = vmalloc(fifo_size);
- if (!pfifo_map)
- return -1;
-
- status = api->halmac_dump_fifo(mac, halmac_fifo_sel, 0, fifo_size,
- pfifo_map);
-
- if (status != HALMAC_RET_SUCCESS) {
- ret = -1;
- goto _exit;
- }
-
-_exit:
- if (pfifo_map)
- vfree(pfifo_map);
- return ret;
-}
-
-int rtl_halmac_rx_agg_switch(struct rtl_priv *rtlpriv, bool enable)
-{
- struct halmac_adapter *halmac;
- struct halmac_api *api;
- struct halmac_rxagg_cfg rxaggcfg;
- enum halmac_ret_status status;
- int err = -1;
-
- halmac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(halmac);
- memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg));
-
- if (enable) {
- /* enable RX agg. */
- /* PCIE do nothing */
- } else {
- /* disable RX agg. */
- rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
- }
-
- status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
-
- err = 0;
-out:
- return err;
-}
-
-int rtl_halmac_get_wow_reason(struct rtl_priv *rtlpriv, u8 *reason)
-{
- u8 val8;
- int err = -1;
-
- val8 = rtl_read_byte(rtlpriv, 0x1C7);
- if (val8 == 0xEA)
- goto out;
-
- *reason = val8;
- err = 0;
-out:
- return err;
-}
-
-/*
- * Description:
- * Get RX driver info size. RX driver info is a small memory space between
- * scriptor and RX payload.
- *
- * +-------------------------+
- * | RX descriptor |
- * | usually 24 bytes |
- * +-------------------------+
- * | RX driver info |
- * | depends on driver cfg |
- * +-------------------------+
- * | RX paylad |
- * | |
- * +-------------------------+
- *
- * Parameter:
- * d pointer to struct dvobj_priv of driver
- * sz rx driver info size in bytes.
- *
- * Rteurn:
- * 0 Success
- * other Fail
- */
-int rtl_halmac_get_drv_info_sz(struct rtl_priv *rtlpriv, u8 *sz)
-{
- /* enum halmac_ret_status status; */
- u8 dw = 6; /* max number */
-
- *sz = dw * 8;
- return 0;
-}
-
-int rtl_halmac_get_rsvd_drv_pg_bndy(struct rtl_priv *rtlpriv, u16 *drv_pg)
-{
- enum halmac_ret_status status;
- struct halmac_adapter *halmac = rtlpriv_to_halmac(rtlpriv);
- struct halmac_api *api = HALMAC_GET_API(halmac);
-
- status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY,
- drv_pg);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- return 0;
-}
-
-int rtl_halmac_chk_txdesc(struct rtl_priv *rtlpriv, u8 *txdesc, u32 size)
-{
- struct halmac_adapter *mac;
- struct halmac_api *api;
- enum halmac_ret_status status;
-
- mac = rtlpriv_to_halmac(rtlpriv);
- api = HALMAC_GET_API(mac);
-
- status = api->halmac_chk_txdesc(mac, txdesc, size);
-
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-
- return 0;
-}
-
-MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
-MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef _RTL_HALMAC_H_
-#define _RTL_HALMAC_H_
-
-#include "halmac_api.h"
-
-#define rtlpriv_to_halmac(priv) \
- ((struct halmac_adapter *)((priv)->halmac.internal))
-
-/* for H2C cmd */
-#define MAX_H2C_BOX_NUMS 4
-#define MESSAGE_BOX_SIZE 4
-#define EX_MESSAGE_BOX_SIZE 4
-
-/* HALMAC API for Driver(HAL) */
-int rtl_halmac_init_adapter(struct rtl_priv *rtlpriv);
-int rtl_halmac_deinit_adapter(struct rtl_priv *rtlpriv);
-int rtl_halmac_poweron(struct rtl_priv *rtlpriv);
-int rtl_halmac_poweroff(struct rtl_priv *rtlpriv);
-int rtl_halmac_init_hal(struct rtl_priv *rtlpriv);
-int rtl_halmac_init_hal_fw(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize);
-int rtl_halmac_init_hal_fw_file(struct rtl_priv *rtlpriv, u8 *fwpath);
-int rtl_halmac_deinit_hal(struct rtl_priv *rtlpriv);
-int rtl_halmac_self_verify(struct rtl_priv *rtlpriv);
-int rtl_halmac_dlfw(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize);
-int rtl_halmac_dlfw_from_file(struct rtl_priv *rtlpriv, u8 *fwpath);
-int rtl_halmac_phy_power_switch(struct rtl_priv *rtlpriv, u8 enable);
-int rtl_halmac_send_h2c(struct rtl_priv *rtlpriv, u8 *h2c);
-int rtl_halmac_c2h_handle(struct rtl_priv *rtlpriv, u8 *c2h, u32 size);
-
-int rtl_halmac_get_physical_efuse_size(struct rtl_priv *rtlpriv, u32 *size);
-int rtl_halmac_read_physical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
- u32 size);
-int rtl_halmac_read_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
- u32 cnt, u8 *data);
-int rtl_halmac_write_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
- u32 cnt, u8 *data);
-int rtl_halmac_get_logical_efuse_size(struct rtl_priv *rtlpriv, u32 *size);
-int rtl_halmac_read_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
- u32 size);
-int rtl_halmac_write_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
- u32 size, u8 *maskmap, u32 masksize);
-int rtl_halmac_read_logical_efuse(struct rtl_priv *rtlpriv, u32 offset, u32 cnt,
- u8 *data);
-int rtl_halmac_write_logical_efuse(struct rtl_priv *rtlpriv, u32 offset,
- u32 cnt, u8 *data);
-
-int rtl_halmac_config_rx_info(struct rtl_priv *rtlpriv, enum halmac_drv_info);
-int rtl_halmac_set_mac_address(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr);
-int rtl_halmac_set_bssid(struct rtl_priv *d, u8 hwport, u8 *addr);
-
-int rtl_halmac_set_bandwidth(struct rtl_priv *rtlpriv, u8 channel,
- u8 pri_ch_idx, u8 bw);
-int rtl_halmac_rx_agg_switch(struct rtl_priv *rtlpriv, bool enable);
-int rtl_halmac_get_hw_value(struct rtl_priv *d, enum halmac_hw_id hw_id,
- void *pvalue);
-int rtl_halmac_dump_fifo(struct rtl_priv *rtlpriv,
- enum hal_fifo_sel halmac_fifo_sel);
-
-int rtl_halmac_get_wow_reason(struct rtl_priv *rtlpriv, u8 *reason);
-int rtl_halmac_get_drv_info_sz(struct rtl_priv *d, u8 *sz);
-
-int rtl_halmac_get_rsvd_drv_pg_bndy(struct rtl_priv *dvobj, u16 *drv_pg);
-int rtl_halmac_download_rsvd_page(struct rtl_priv *dvobj, u8 pg_offset,
- u8 *pbuf, u32 size);
-
-int rtl_halmac_chk_txdesc(struct rtl_priv *rtlpriv, u8 *txdesc, u32 size);
-
-struct rtl_halmac_ops *rtl_halmac_get_ops_pointer(void);
-
-#endif /* _RTL_HALMAC_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "wifi.h"
-#include "core.h"
-#include "pci.h"
-#include "base.h"
-#include "ps.h"
-#include "efuse.h"
-#include <linux/interrupt.h>
-#include <linux/export.h>
-#include <linux/module.h>
-
-MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
-MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
-MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
-
-static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
- INTEL_VENDOR_ID,
- ATI_VENDOR_ID,
- AMD_VENDOR_ID,
- SIS_VENDOR_ID
-};
-
-static const u8 ac_to_hwq[] = {
- VO_QUEUE,
- VI_QUEUE,
- BE_QUEUE,
- BK_QUEUE
-};
-
-static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
- struct sk_buff *skb)
-{
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- __le16 fc = rtl_get_fc(skb);
- u8 queue_index = skb_get_queue_mapping(skb);
- struct ieee80211_hdr *hdr;
-
- if (unlikely(ieee80211_is_beacon(fc)))
- return BEACON_QUEUE;
- if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
- return MGNT_QUEUE;
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
- if (ieee80211_is_nullfunc(fc))
- return HIGH_QUEUE;
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
- hdr = rtl_get_hdr(skb);
-
- if (is_multicast_ether_addr(hdr->addr1) ||
- is_broadcast_ether_addr(hdr->addr1))
- return HIGH_QUEUE;
- }
-
- return ac_to_hwq[queue_index];
-}
-
-/* Update PCI dependent default settings*/
-static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
- u8 init_aspm;
-
- ppsc->reg_rfps_level = 0;
- ppsc->support_aspm = false;
-
- /*Update PCI ASPM setting */
- ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
- switch (rtlpci->const_pci_aspm) {
- case 0:
- /*No ASPM */
- break;
-
- case 1:
- /*ASPM dynamically enabled/disable. */
- ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
- break;
-
- case 2:
- /*ASPM with Clock Req dynamically enabled/disable. */
- ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
- RT_RF_OFF_LEVL_CLK_REQ);
- break;
-
- case 3:
- /* Always enable ASPM and Clock Req
- * from initialization to halt.
- */
- ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
- ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
- RT_RF_OFF_LEVL_CLK_REQ);
- break;
-
- case 4:
- /* Always enable ASPM without Clock Req
- * from initialization to halt.
- */
- ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
- RT_RF_OFF_LEVL_CLK_REQ);
- ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
- break;
- }
-
- ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
-
- /*Update Radio OFF setting */
- switch (rtlpci->const_hwsw_rfoff_d3) {
- case 1:
- if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
- ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
- break;
-
- case 2:
- if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
- ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
- ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
- break;
-
- case 3:
- ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
- break;
- }
-
- /*Set HW definition to determine if it supports ASPM. */
- switch (rtlpci->const_support_pciaspm) {
- case 0:{
- /*Not support ASPM. */
- bool support_aspm = false;
-
- ppsc->support_aspm = support_aspm;
- break;
- }
- case 1:{
- /*Support ASPM. */
- bool support_aspm = true;
- bool support_backdoor = true;
-
- ppsc->support_aspm = support_aspm;
-
- /*if (priv->oem_id == RT_CID_TOSHIBA &&
- * !priv->ndis_adapter.amd_l1_patch)
- * support_backdoor = false;
- */
-
- ppsc->support_backdoor = support_backdoor;
-
- break;
- }
- case 2:
- /*ASPM value set by chipset. */
- if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
- bool support_aspm = true;
-
- ppsc->support_aspm = support_aspm;
- }
- break;
- default:
- pr_err("switch case %#x not processed\n",
- rtlpci->const_support_pciaspm);
- break;
- }
-
- /* toshiba aspm issue, toshiba will set aspm selfly
- * so we should not set aspm in driver
- */
- pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
- if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
- init_aspm == 0x43)
- ppsc->support_aspm = false;
-}
-
-static bool _rtl_pci_platform_switch_device_pci_aspm(
- struct ieee80211_hw *hw,
- u8 value)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
-
- if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
- value |= 0x40;
-
- pci_write_config_byte(rtlpci->pdev, 0x80, value);
-
- return false;
-}
-
-/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
-static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
-
- pci_write_config_byte(rtlpci->pdev, 0x81, value);
-
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
- udelay(100);
-}
-
-/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
-static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
- u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
- /*Retrieve original configuration settings. */
- u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
- u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.pcibridge_linkctrlreg;
- u16 aspmlevel = 0;
- u8 tmp_u1b = 0;
-
- if (!ppsc->support_aspm)
- return;
-
- if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
- RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
- "PCI(Bridge) UNKNOWN\n");
-
- return;
- }
-
- if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
- RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
- _rtl_pci_switch_clk_req(hw, 0x0);
- }
-
- /*for promising device will in L0 state after an I/O. */
- pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
-
- /*Set corresponding value. */
- aspmlevel |= BIT(0) | BIT(1);
- linkctrl_reg &= ~aspmlevel;
- pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
-
- _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
- udelay(50);
-
- /*4 Disable Pci Bridge ASPM */
- pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
- pcibridge_linkctrlreg);
-
- udelay(50);
-}
-
-/*
- *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
- *power saving We should follow the sequence to enable
- *RTL8192SE first then enable Pci Bridge ASPM
- *or the system will show bluescreen.
- */
-static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
- u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
- u16 aspmlevel;
- u8 u_pcibridge_aspmsetting;
- u8 u_device_aspmsetting;
-
- if (!ppsc->support_aspm)
- return;
-
- if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
- RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
- "PCI(Bridge) UNKNOWN\n");
- return;
- }
-
- /*4 Enable Pci Bridge ASPM */
-
- u_pcibridge_aspmsetting =
- pcipriv->ndis_adapter.pcibridge_linkctrlreg |
- rtlpci->const_hostpci_aspm_setting;
-
- if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
- u_pcibridge_aspmsetting &= ~BIT(0);
-
- pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
- u_pcibridge_aspmsetting);
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "PlatformEnableASPM(): Write reg[%x] = %x\n",
- (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
- u_pcibridge_aspmsetting);
-
- udelay(50);
-
- /*Get ASPM level (with/without Clock Req) */
- aspmlevel = rtlpci->const_devicepci_aspm_setting;
- u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
-
- /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
- /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
-
- u_device_aspmsetting |= aspmlevel;
-
- _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
-
- if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
- _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
- RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
- RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
- }
- udelay(100);
-}
-
-static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- bool status = false;
- u8 offset_e0;
- unsigned int offset_e4;
-
- pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
-
- pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
-
- if (offset_e0 == 0xA0) {
- pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
- if (offset_e4 & BIT(23))
- status = true;
- }
-
- return status;
-}
-
-static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
- struct rtl_priv **buddy_priv)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- bool find_buddy_priv = false;
- struct rtl_priv *tpriv;
- struct rtl_pci_priv *tpcipriv = NULL;
-
- if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
- list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
- list) {
- tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "pcipriv->ndis_adapter.funcnumber %x\n",
- pcipriv->ndis_adapter.funcnumber);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "tpcipriv->ndis_adapter.funcnumber %x\n",
- tpcipriv->ndis_adapter.funcnumber);
-
- if ((pcipriv->ndis_adapter.busnumber ==
- tpcipriv->ndis_adapter.busnumber) &&
- (pcipriv->ndis_adapter.devnumber ==
- tpcipriv->ndis_adapter.devnumber) &&
- (pcipriv->ndis_adapter.funcnumber !=
- tpcipriv->ndis_adapter.funcnumber)) {
- find_buddy_priv = true;
- break;
- }
- }
- }
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "find_buddy_priv %d\n", find_buddy_priv);
-
- if (find_buddy_priv)
- *buddy_priv = tpriv;
-
- return find_buddy_priv;
-}
-
-static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
-{
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
- u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
- u8 linkctrl_reg;
- u8 num4bbytes;
-
- num4bbytes = (capabilityoffset + 0x10) / 4;
-
- /*Read Link Control Register */
- pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
-
- pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
-}
-
-static void rtl_pci_parse_configuration(struct pci_dev *pdev,
- struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
-
- u8 tmp;
- u16 linkctrl_reg;
-
- /*Link Control Register */
- pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
- pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
- pcipriv->ndis_adapter.linkctrl_reg);
-
- pci_read_config_byte(pdev, 0x98, &tmp);
- tmp |= BIT(4);
- pci_write_config_byte(pdev, 0x98, tmp);
-
- tmp = 0x17;
- pci_write_config_byte(pdev, 0x70f, tmp);
-}
-
-static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
-{
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
-
- _rtl_pci_update_default_setting(hw);
-
- if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
- /*Always enable ASPM & Clock Req. */
- rtl_pci_enable_aspm(hw);
- RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
- }
-}
-
-static void _rtl_pci_io_handler_init(struct device *dev,
- struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtlpriv->io.dev = dev;
-
- rtlpriv->io.write8_async = pci_write8_async;
- rtlpriv->io.write16_async = pci_write16_async;
- rtlpriv->io.write32_async = pci_write32_async;
-
- rtlpriv->io.read8_sync = pci_read8_sync;
- rtlpriv->io.read16_sync = pci_read16_sync;
- rtlpriv->io.read32_sync = pci_read32_sync;
-}
-
-static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
- struct sk_buff *skb,
- struct rtl_tcb_desc *tcb_desc, u8 tid)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct sk_buff *next_skb;
- u8 additionlen = FCS_LEN;
-
- /* here open is 4, wep/tkip is 8, aes is 12*/
- if (info->control.hw_key)
- additionlen += info->control.hw_key->icv_len;
-
- /* The most skb num is 6 */
- tcb_desc->empkt_num = 0;
- spin_lock_bh(&rtlpriv->locks.waitq_lock);
- skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
- struct ieee80211_tx_info *next_info;
-
- next_info = IEEE80211_SKB_CB(next_skb);
- if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
- tcb_desc->empkt_len[tcb_desc->empkt_num] =
- next_skb->len + additionlen;
- tcb_desc->empkt_num++;
- } else {
- break;
- }
-
- if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
- next_skb))
- break;
-
- if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
- break;
- }
- spin_unlock_bh(&rtlpriv->locks.waitq_lock);
-
- return true;
-}
-
-/* just for early mode now */
-static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct sk_buff *skb = NULL;
- struct ieee80211_tx_info *info = NULL;
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- int tid;
-
- if (!rtlpriv->rtlhal.earlymode_enable)
- return;
-
- if (rtlpriv->dm.supp_phymode_switch &&
- (rtlpriv->easy_concurrent_ctl.switch_in_process ||
- (rtlpriv->buddy_priv &&
- rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
- return;
- /* we just use em for BE/BK/VI/VO */
- for (tid = 7; tid >= 0; tid--) {
- u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
- struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
-
- while (!mac->act_scanning &&
- rtlpriv->psc.rfpwr_state == ERFON) {
- struct rtl_tcb_desc tcb_desc;
-
- memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
- spin_lock_bh(&rtlpriv->locks.waitq_lock);
- if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
- (ring->entries - skb_queue_len(&ring->queue) >
- rtlhal->max_earlymode_num)) {
- skb = skb_dequeue(&mac->skb_waitq[tid]);
- } else {
- spin_unlock_bh(&rtlpriv->locks.waitq_lock);
- break;
- }
- spin_unlock_bh(&rtlpriv->locks.waitq_lock);
-
- /* Some macaddr can't do early mode. like
- * multicast/broadcast/no_qos data
- */
- info = IEEE80211_SKB_CB(skb);
- if (info->flags & IEEE80211_TX_CTL_AMPDU)
- _rtl_update_earlymode_info(hw, skb,
- &tcb_desc, tid);
-
- rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
- }
- }
-}
-
-static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
-
- while (skb_queue_len(&ring->queue)) {
- struct sk_buff *skb;
- struct ieee80211_tx_info *info;
- __le16 fc;
- u8 tid;
- u8 *entry;
-
- if (rtlpriv->use_new_trx_flow)
- entry = (u8 *)(&ring->buffer_desc[ring->idx]);
- else
- entry = (u8 *)(&ring->desc[ring->idx]);
-
- if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
- return;
- ring->idx = (ring->idx + 1) % ring->entries;
-
- skb = __skb_dequeue(&ring->queue);
- pci_unmap_single(rtlpci->pdev,
- rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, true,
- HW_DESC_TXBUFF_ADDR),
- skb->len, PCI_DMA_TODEVICE);
-
- /* remove early mode header */
- if (rtlpriv->rtlhal.earlymode_enable)
- skb_pull(skb, EM_HDR_LEN);
-
- RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
- "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
- ring->idx,
- skb_queue_len(&ring->queue),
- *(u16 *)(skb->data + 22));
-
- if (prio == TXCMD_QUEUE) {
- dev_kfree_skb(skb);
- goto tx_status_ok;
- }
-
- /* for sw LPS, just after NULL skb send out, we can
- * sure AP knows we are sleeping, we should not let
- * rf sleep
- */
- fc = rtl_get_fc(skb);
- if (ieee80211_is_nullfunc(fc)) {
- if (ieee80211_has_pm(fc)) {
- rtlpriv->mac80211.offchan_delay = true;
- rtlpriv->psc.state_inap = true;
- } else {
- rtlpriv->psc.state_inap = false;
- }
- }
- if (ieee80211_is_action(fc)) {
- struct ieee80211_mgmt *action_frame =
- (struct ieee80211_mgmt *)skb->data;
- if (action_frame->u.action.u.ht_smps.action ==
- WLAN_HT_ACTION_SMPS) {
- dev_kfree_skb(skb);
- goto tx_status_ok;
- }
- }
-
- /* update tid tx pkt num */
- tid = rtl_get_tid(skb);
- if (tid <= 7)
- rtlpriv->link_info.tidtx_inperiod[tid]++;
-
- info = IEEE80211_SKB_CB(skb);
- ieee80211_tx_info_clear_status(info);
-
- info->flags |= IEEE80211_TX_STAT_ACK;
- /*info->status.rates[0].count = 1; */
-
- ieee80211_tx_status_irqsafe(hw, skb);
-
- if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
- "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
- prio, ring->idx,
- skb_queue_len(&ring->queue));
-
- ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
- }
-tx_status_ok:
- skb = NULL;
- }
-
- if (((rtlpriv->link_info.num_rx_inperiod +
- rtlpriv->link_info.num_tx_inperiod) > 8) ||
- (rtlpriv->link_info.num_rx_inperiod > 2))
- rtl_lps_leave(hw);
-}
-
-static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
- struct sk_buff *new_skb, u8 *entry,
- int rxring_idx, int desc_idx)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- u32 bufferaddress;
- u8 tmp_one = 1;
- struct sk_buff *skb;
-
- if (likely(new_skb)) {
- skb = new_skb;
- goto remap;
- }
- skb = dev_alloc_skb(rtlpci->rxbuffersize);
- if (!skb)
- return 0;
-
-remap:
- /* just set skb->cb to mapping addr for pci_unmap_single use */
- *((dma_addr_t *)skb->cb) =
- pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
- rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
- bufferaddress = *((dma_addr_t *)skb->cb);
- if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
- return 0;
- rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
- if (rtlpriv->use_new_trx_flow) {
- /* skb->cb may be 64 bit address */
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
- HW_DESC_RX_PREPARE,
- (u8 *)(dma_addr_t *)skb->cb);
- } else {
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
- HW_DESC_RXBUFF_ADDR,
- (u8 *)&bufferaddress);
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
- HW_DESC_RXPKT_LEN,
- (u8 *)&rtlpci->rxbuffersize);
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
- HW_DESC_RXOWN,
- (u8 *)&tmp_one);
- }
- return 1;
-}
-
-/* inorder to receive 8K AMSDU we have set skb to
- * 9100bytes in init rx ring, but if this packet is
- * not a AMSDU, this large packet will be sent to
- * TCP/IP directly, this cause big packet ping fail
- * like: "ping -s 65507", so here we will realloc skb
- * based on the true size of packet, Mac80211
- * Probably will do it better, but does not yet.
- *
- * Some platform will fail when alloc skb sometimes.
- * in this condition, we will send the old skb to
- * mac80211 directly, this will not cause any other
- * issues, but only this packet will be lost by TCP/IP
- */
-static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
- struct sk_buff *skb,
- struct ieee80211_rx_status rx_status)
-{
- if (unlikely(!rtl_action_proc(hw, skb, false))) {
- dev_kfree_skb_any(skb);
- } else {
- struct sk_buff *uskb = NULL;
-
- uskb = dev_alloc_skb(skb->len + 128);
- if (likely(uskb)) {
- memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
- sizeof(rx_status));
- skb_put_data(uskb, skb->data, skb->len);
- dev_kfree_skb_any(skb);
- ieee80211_rx_irqsafe(hw, uskb);
- } else {
- ieee80211_rx_irqsafe(hw, skb);
- }
- }
-}
-
-/*hsisr interrupt handler*/
-static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
- rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
- rtlpci->sys_irq_mask);
-}
-
-static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
- struct ieee80211_rx_status rx_status = { 0 };
- unsigned int count = rtlpci->rxringcount;
- u8 own;
- u8 tmp_one;
- bool unicast = false;
- u8 hw_queue = 0;
- unsigned int rx_remained_cnt = 0;
- struct rtl_stats stats = {
- .signal = 0,
- .rate = 0,
- };
-
- /*RX NORMAL PKT */
- while (count--) {
- struct ieee80211_hdr *hdr;
- __le16 fc;
- u16 len;
- /*rx buffer descriptor */
- struct rtl_rx_buffer_desc *buffer_desc = NULL;
- /*if use new trx flow, it means wifi info */
- struct rtl_rx_desc *pdesc = NULL;
- /*rx pkt */
- struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
- rtlpci->rx_ring[rxring_idx].idx];
- struct sk_buff *new_skb;
-
- if (rtlpriv->use_new_trx_flow) {
- if (rx_remained_cnt == 0)
- rx_remained_cnt =
- rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
- hw_queue);
- if (rx_remained_cnt == 0)
- return;
- buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
- rtlpci->rx_ring[rxring_idx].idx];
- pdesc = (struct rtl_rx_desc *)skb->data;
- } else { /* rx descriptor */
- pdesc = &rtlpci->rx_ring[rxring_idx].desc[
- rtlpci->rx_ring[rxring_idx].idx];
-
- own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
- false,
- HW_DESC_OWN);
- if (own) /* wait data to be filled by hardware */
- return;
- }
-
- /* Reaching this point means: data is filled already
- * AAAAAAttention !!!
- * We can NOT access 'skb' before 'pci_unmap_single'
- */
- pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
- rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
-
- /* get a new skb - if fail, old one will be reused */
- new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
- if (unlikely(!new_skb))
- goto no_new;
- memset(&rx_status, 0, sizeof(rx_status));
- rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
- &rx_status, (u8 *)pdesc, skb);
-
- if (rtlpriv->use_new_trx_flow)
- rtlpriv->cfg->ops->rx_check_dma_ok(hw,
- (u8 *)buffer_desc,
- hw_queue);
-
- len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
- HW_DESC_RXPKT_LEN);
-
- if (skb->end - skb->tail > len) {
- skb_put(skb, len);
- if (rtlpriv->use_new_trx_flow)
- skb_reserve(skb, stats.rx_drvinfo_size +
- stats.rx_bufshift + 24);
- else
- skb_reserve(skb, stats.rx_drvinfo_size +
- stats.rx_bufshift);
- } else {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "skb->end - skb->tail = %d, len is %d\n",
- skb->end - skb->tail, len);
- dev_kfree_skb_any(skb);
- goto new_trx_end;
- }
- /* handle command packet here */
- if (rtlpriv->cfg->ops->rx_command_packet &&
- rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) {
- dev_kfree_skb_any(skb);
- goto new_trx_end;
- }
-
- /*
- * NOTICE This can not be use for mac80211,
- * this is done in mac80211 code,
- * if done here sec DHCP will fail
- * skb_trim(skb, skb->len - 4);
- */
-
- hdr = rtl_get_hdr(skb);
- fc = rtl_get_fc(skb);
-
- if (!stats.crc && !stats.hwerror) {
- memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
- sizeof(rx_status));
-
- if (is_broadcast_ether_addr(hdr->addr1)) {
- ;/*TODO*/
- } else if (is_multicast_ether_addr(hdr->addr1)) {
- ;/*TODO*/
- } else {
- unicast = true;
- rtlpriv->stats.rxbytesunicast += skb->len;
- }
- rtl_is_special_data(hw, skb, false, true);
-
- if (ieee80211_is_data(fc)) {
- rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
- if (unicast)
- rtlpriv->link_info.num_rx_inperiod++;
- }
-
- rtl_collect_scan_list(hw, skb);
-
- /* static bcn for roaming */
- rtl_beacon_statistic(hw, skb);
- rtl_p2p_info(hw, (void *)skb->data, skb->len);
- /* for sw lps */
- rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
- rtl_recognize_peer(hw, (void *)skb->data, skb->len);
- if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
- (rtlpriv->rtlhal.current_bandtype ==
- BAND_ON_2_4G) &&
- (ieee80211_is_beacon(fc) ||
- ieee80211_is_probe_resp(fc))) {
- dev_kfree_skb_any(skb);
- } else {
- rtl_check_beacon_key(hw, (void *)skb->data,
- skb->len);
- _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
- }
- } else {
- dev_kfree_skb_any(skb);
- }
-new_trx_end:
- if (rtlpriv->use_new_trx_flow) {
- rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
- rtlpci->rx_ring[hw_queue].next_rx_rp %=
- RTL_PCI_MAX_RX_COUNT;
-
- rx_remained_cnt--;
- rtl_write_word(rtlpriv, 0x3B4,
- rtlpci->rx_ring[hw_queue].next_rx_rp);
- }
- if (((rtlpriv->link_info.num_rx_inperiod +
- rtlpriv->link_info.num_tx_inperiod) > 8) ||
- (rtlpriv->link_info.num_rx_inperiod > 2))
- rtl_lps_leave(hw);
- skb = new_skb;
-no_new:
- if (rtlpriv->use_new_trx_flow) {
- _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
- rxring_idx,
- rtlpci->rx_ring[rxring_idx].idx);
- } else {
- _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
- rxring_idx,
- rtlpci->rx_ring[rxring_idx].idx);
- if (rtlpci->rx_ring[rxring_idx].idx ==
- rtlpci->rxringcount - 1)
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
- false,
- HW_DESC_RXERO,
- (u8 *)&tmp_one);
- }
- rtlpci->rx_ring[rxring_idx].idx =
- (rtlpci->rx_ring[rxring_idx].idx + 1) %
- rtlpci->rxringcount;
- }
-}
-
-static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
-{
- struct ieee80211_hw *hw = dev_id;
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- unsigned long flags;
- u32 inta = 0;
- u32 intb = 0;
- u32 intc = 0;
- u32 intd = 0;
- irqreturn_t ret = IRQ_HANDLED;
-
- if (rtlpci->irq_enabled == 0)
- return ret;
-
- spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
- rtlpriv->cfg->ops->disable_interrupt(hw);
-
- /*read ISR: 4/8bytes */
- rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb, &intc, &intd);
-
- /*Shared IRQ or HW disappeared */
- if (!inta || inta == 0xffff)
- goto done;
-
- /*<1> beacon related */
- if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "beacon ok interrupt!\n");
- }
-
- if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "beacon err interrupt!\n");
- }
-
- if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
-
- if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "prepare beacon for interrupt!\n");
- tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
- }
-
- /*<2> Tx related */
- if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
-
- if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "Manage ok interrupt!\n");
- _rtl_pci_tx_isr(hw, MGNT_QUEUE);
- }
-
- if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "HIGH_QUEUE ok interrupt!\n");
- _rtl_pci_tx_isr(hw, HIGH_QUEUE);
- }
-
- if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
- rtlpriv->link_info.num_tx_inperiod++;
-
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "BK Tx OK interrupt!\n");
- _rtl_pci_tx_isr(hw, BK_QUEUE);
- }
-
- if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
- rtlpriv->link_info.num_tx_inperiod++;
-
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "BE TX OK interrupt!\n");
- _rtl_pci_tx_isr(hw, BE_QUEUE);
- }
-
- if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
- rtlpriv->link_info.num_tx_inperiod++;
-
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "VI TX OK interrupt!\n");
- _rtl_pci_tx_isr(hw, VI_QUEUE);
- }
-
- if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
- rtlpriv->link_info.num_tx_inperiod++;
-
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "Vo TX OK interrupt!\n");
- _rtl_pci_tx_isr(hw, VO_QUEUE);
- }
-
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
- if (intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
- rtlpriv->link_info.num_tx_inperiod++;
-
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "H2C TX OK interrupt!\n");
- _rtl_pci_tx_isr(hw, H2C_QUEUE);
- }
- }
-
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
- if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
- rtlpriv->link_info.num_tx_inperiod++;
-
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "CMD TX OK interrupt!\n");
- _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
- }
- }
-
- /*<3> Rx related */
- if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
- _rtl_pci_rx_interrupt(hw);
- }
-
- if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "rx descriptor unavailable!\n");
- _rtl_pci_rx_interrupt(hw);
- }
-
- if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
- _rtl_pci_rx_interrupt(hw);
- }
-
- /*<4> fw related*/
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
- if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "firmware interrupt!\n");
- queue_delayed_work(rtlpriv->works.rtl_wq,
- &rtlpriv->works.fwevt_wq, 0);
- }
- }
-
- /*<5> hsisr related*/
- /* Only 8188EE & 8723BE Supported.
- * If Other ICs Come in, System will corrupt,
- * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
- * are not initialized
- */
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
- rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
- if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
- RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
- "hsisr interrupt!\n");
- _rtl_pci_hs_interrupt(hw);
- }
- }
-
- if (rtlpriv->rtlhal.earlymode_enable)
- tasklet_schedule(&rtlpriv->works.irq_tasklet);
-
-done:
- rtlpriv->cfg->ops->enable_interrupt(hw);
- spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
- return ret;
-}
-
-static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
-{
- _rtl_pci_tx_chk_waitq(hw);
-}
-
-static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl8192_tx_ring *ring = NULL;
- struct ieee80211_hdr *hdr = NULL;
- struct ieee80211_tx_info *info = NULL;
- struct sk_buff *pskb = NULL;
- struct rtl_tx_desc *pdesc = NULL;
- struct rtl_tcb_desc tcb_desc;
- /*This is for new trx flow*/
- struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
- u8 temp_one = 1;
- u8 *entry;
-
- memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
- ring = &rtlpci->tx_ring[BEACON_QUEUE];
- pskb = __skb_dequeue(&ring->queue);
- if (rtlpriv->use_new_trx_flow)
- entry = (u8 *)(&ring->buffer_desc[ring->idx]);
- else
- entry = (u8 *)(&ring->desc[ring->idx]);
- if (pskb) {
- pci_unmap_single(rtlpci->pdev,
- rtlpriv->cfg->ops->get_desc(
- hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
- pskb->len, PCI_DMA_TODEVICE);
- kfree_skb(pskb);
- }
-
- /*NB: the beacon data buffer must be 32-bit aligned. */
- pskb = ieee80211_beacon_get(hw, mac->vif);
- if (!pskb)
- return;
- hdr = rtl_get_hdr(pskb);
- info = IEEE80211_SKB_CB(pskb);
- pdesc = &ring->desc[0];
- if (rtlpriv->use_new_trx_flow)
- pbuffer_desc = &ring->buffer_desc[0];
-
- rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
- (u8 *)pbuffer_desc, info, NULL, pskb,
- BEACON_QUEUE, &tcb_desc);
-
- __skb_queue_tail(&ring->queue, pskb);
-
- if (rtlpriv->use_new_trx_flow) {
- temp_one = 4;
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
- HW_DESC_OWN, (u8 *)&temp_one);
- } else {
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
- &temp_one);
- }
-}
-
-static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- u8 i;
- u16 desc_num;
-
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
- desc_num = TX_DESC_NUM_92E;
- else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
- desc_num = TX_DESC_NUM_8822B;
- else
- desc_num = RT_TXDESC_NUM;
-
- for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
- rtlpci->txringcount[i] = desc_num;
-
- /*
- *we just alloc 2 desc for beacon queue,
- *because we just need first desc in hw beacon.
- */
- rtlpci->txringcount[BEACON_QUEUE] = 2;
-
- /*BE queue need more descriptor for performance
- *consideration or, No more tx desc will happen,
- *and may cause mac80211 mem leakage.
- */
- if (!rtl_priv(hw)->use_new_trx_flow)
- rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
-
- rtlpci->rxbuffersize = 9100; /*2048/1024; */
- rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
-}
-
-static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
- struct pci_dev *pdev)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
-
- rtlpci->up_first_time = true;
- rtlpci->being_init_adapter = false;
-
- rtlhal->hw = hw;
- rtlpci->pdev = pdev;
-
- /*Tx/Rx related var */
- _rtl_pci_init_trx_var(hw);
-
- /*IBSS*/
- mac->beacon_interval = 100;
-
- /*AMPDU*/
- mac->min_space_cfg = 0;
- mac->max_mss_density = 0;
- /*set sane AMPDU defaults */
- mac->current_ampdu_density = 7;
- mac->current_ampdu_factor = 3;
-
- /*Retry Limit*/
- mac->retry_short = 7;
- mac->retry_long = 7;
-
- /*QOS*/
- rtlpci->acm_method = EACMWAY2_SW;
-
- /*task */
- tasklet_init(&rtlpriv->works.irq_tasklet,
- (void (*)(unsigned long))_rtl_pci_irq_tasklet,
- (unsigned long)hw);
- tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
- (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
- (unsigned long)hw);
- INIT_WORK(&rtlpriv->works.lps_change_work,
- rtl_lps_change_work_callback);
-}
-
-static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
- unsigned int prio, unsigned int entries)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_tx_buffer_desc *buffer_desc;
- struct rtl_tx_desc *desc;
- dma_addr_t buffer_desc_dma, desc_dma;
- u32 nextdescaddress;
- int i;
-
- /* alloc tx buffer desc for new trx flow*/
- if (rtlpriv->use_new_trx_flow) {
- buffer_desc =
- pci_zalloc_consistent(rtlpci->pdev,
- sizeof(*buffer_desc) * entries,
- &buffer_desc_dma);
-
- if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
- pr_err("Cannot allocate TX ring (prio = %d)\n",
- prio);
- return -ENOMEM;
- }
-
- rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
- rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
-
- rtlpci->tx_ring[prio].cur_tx_rp = 0;
- rtlpci->tx_ring[prio].cur_tx_wp = 0;
- }
-
- /* alloc dma for this ring */
- desc = pci_zalloc_consistent(rtlpci->pdev,
- sizeof(*desc) * entries, &desc_dma);
-
- if (!desc || (unsigned long)desc & 0xFF) {
- pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
- return -ENOMEM;
- }
-
- rtlpci->tx_ring[prio].desc = desc;
- rtlpci->tx_ring[prio].dma = desc_dma;
-
- rtlpci->tx_ring[prio].idx = 0;
- rtlpci->tx_ring[prio].entries = entries;
- skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
- prio, desc);
-
- /* init every desc in this ring */
- if (!rtlpriv->use_new_trx_flow) {
- for (i = 0; i < entries; i++) {
- nextdescaddress = (u32)desc_dma +
- ((i + 1) % entries) *
- sizeof(*desc);
-
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
- true,
- HW_DESC_TX_NEXTDESC_ADDR,
- (u8 *)&nextdescaddress);
- }
- }
- return 0;
-}
-
-static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- int i;
-
- if (rtlpriv->use_new_trx_flow) {
- struct rtl_rx_buffer_desc *entry = NULL;
- /* alloc dma for this ring */
- rtlpci->rx_ring[rxring_idx].buffer_desc =
- pci_zalloc_consistent(rtlpci->pdev,
- sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
- rtlpci->rxringcount,
- &rtlpci->rx_ring[rxring_idx].dma);
- if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
- (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
- pr_err("Cannot allocate RX ring\n");
- return -ENOMEM;
- }
-
- /* init every desc in this ring */
- rtlpci->rx_ring[rxring_idx].idx = 0;
- for (i = 0; i < rtlpci->rxringcount; i++) {
- entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
- if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
- rxring_idx, i))
- return -ENOMEM;
- }
- } else {
- struct rtl_rx_desc *entry = NULL;
- u8 tmp_one = 1;
- /* alloc dma for this ring */
- rtlpci->rx_ring[rxring_idx].desc =
- pci_zalloc_consistent(rtlpci->pdev,
- sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
- rtlpci->rxringcount,
- &rtlpci->rx_ring[rxring_idx].dma);
- if (!rtlpci->rx_ring[rxring_idx].desc ||
- (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
- pr_err("Cannot allocate RX ring\n");
- return -ENOMEM;
- }
-
- /* init every desc in this ring */
- rtlpci->rx_ring[rxring_idx].idx = 0;
-
- for (i = 0; i < rtlpci->rxringcount; i++) {
- entry = &rtlpci->rx_ring[rxring_idx].desc[i];
- if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
- rxring_idx, i))
- return -ENOMEM;
- }
-
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
- HW_DESC_RXERO, &tmp_one);
- }
- return 0;
-}
-
-static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
- unsigned int prio)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
-
- /* free every desc in this ring */
- while (skb_queue_len(&ring->queue)) {
- u8 *entry;
- struct sk_buff *skb = __skb_dequeue(&ring->queue);
-
- if (rtlpriv->use_new_trx_flow)
- entry = (u8 *)(&ring->buffer_desc[ring->idx]);
- else
- entry = (u8 *)(&ring->desc[ring->idx]);
-
- pci_unmap_single(rtlpci->pdev,
- rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
- true,
- HW_DESC_TXBUFF_ADDR),
- skb->len, PCI_DMA_TODEVICE);
- kfree_skb(skb);
- ring->idx = (ring->idx + 1) % ring->entries;
- }
-
- /* free dma of this ring */
- pci_free_consistent(rtlpci->pdev,
- sizeof(*ring->desc) * ring->entries,
- ring->desc, ring->dma);
- ring->desc = NULL;
- if (rtlpriv->use_new_trx_flow) {
- pci_free_consistent(rtlpci->pdev,
- sizeof(*ring->buffer_desc) * ring->entries,
- ring->buffer_desc, ring->buffer_desc_dma);
- ring->buffer_desc = NULL;
- }
-}
-
-static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- int i;
-
- /* free every desc in this ring */
- for (i = 0; i < rtlpci->rxringcount; i++) {
- struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
-
- if (!skb)
- continue;
- pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
- rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
- kfree_skb(skb);
- }
-
- /* free dma of this ring */
- if (rtlpriv->use_new_trx_flow) {
- pci_free_consistent(rtlpci->pdev,
- sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
- rtlpci->rxringcount,
- rtlpci->rx_ring[rxring_idx].buffer_desc,
- rtlpci->rx_ring[rxring_idx].dma);
- rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
- } else {
- pci_free_consistent(rtlpci->pdev,
- sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
- rtlpci->rxringcount,
- rtlpci->rx_ring[rxring_idx].desc,
- rtlpci->rx_ring[rxring_idx].dma);
- rtlpci->rx_ring[rxring_idx].desc = NULL;
- }
-}
-
-static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- int ret;
- int i, rxring_idx;
-
- /* rxring_idx 0:RX_MPDU_QUEUE
- * rxring_idx 1:RX_CMD_QUEUE
- */
- for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
- ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
- if (ret)
- return ret;
- }
-
- for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
- ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
- if (ret)
- goto err_free_rings;
- }
-
- return 0;
-
-err_free_rings:
- for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
- _rtl_pci_free_rx_ring(hw, rxring_idx);
-
- for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
- if (rtlpci->tx_ring[i].desc ||
- rtlpci->tx_ring[i].buffer_desc)
- _rtl_pci_free_tx_ring(hw, i);
-
- return 1;
-}
-
-static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
-{
- u32 i, rxring_idx;
-
- /*free rx rings */
- for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
- _rtl_pci_free_rx_ring(hw, rxring_idx);
-
- /*free tx rings */
- for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
- _rtl_pci_free_tx_ring(hw, i);
-
- return 0;
-}
-
-int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- int i, rxring_idx;
- unsigned long flags;
- u8 tmp_one = 1;
- u32 bufferaddress;
- /* rxring_idx 0:RX_MPDU_QUEUE */
- /* rxring_idx 1:RX_CMD_QUEUE */
- for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
- /* force the rx_ring[RX_MPDU_QUEUE/
- * RX_CMD_QUEUE].idx to the first one
- * new trx flow, do nothing
- */
- if (!rtlpriv->use_new_trx_flow &&
- rtlpci->rx_ring[rxring_idx].desc) {
- struct rtl_rx_desc *entry = NULL;
-
- rtlpci->rx_ring[rxring_idx].idx = 0;
- for (i = 0; i < rtlpci->rxringcount; i++) {
- entry = &rtlpci->rx_ring[rxring_idx].desc[i];
- bufferaddress =
- rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
- false, HW_DESC_RXBUFF_ADDR);
- memset((u8 *)entry, 0,
- sizeof(*rtlpci->rx_ring
- [rxring_idx].desc));/*clear one entry*/
- if (rtlpriv->use_new_trx_flow) {
- /* This is deadcode */
- rtlpriv->cfg->ops->set_desc(hw,
- (u8 *)entry, false,
- HW_DESC_RX_PREPARE,
- (u8 *)&bufferaddress);
- } else {
- rtlpriv->cfg->ops->set_desc(hw,
- (u8 *)entry, false,
- HW_DESC_RXBUFF_ADDR,
- (u8 *)&bufferaddress);
- rtlpriv->cfg->ops->set_desc(hw,
- (u8 *)entry, false,
- HW_DESC_RXPKT_LEN,
- (u8 *)&rtlpci->rxbuffersize);
- rtlpriv->cfg->ops->set_desc(hw,
- (u8 *)entry, false,
- HW_DESC_RXOWN,
- (u8 *)&tmp_one);
- }
- }
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
- HW_DESC_RXERO, (u8 *)&tmp_one);
- }
- rtlpci->rx_ring[rxring_idx].idx = 0;
- }
-
- /*
- *after reset, release previous pending packet,
- *and force the tx idx to the first one
- */
- spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
- for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
- if (rtlpci->tx_ring[i].desc ||
- rtlpci->tx_ring[i].buffer_desc) {
- struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
-
- while (skb_queue_len(&ring->queue)) {
- u8 *entry;
- struct sk_buff *skb =
- __skb_dequeue(&ring->queue);
- if (rtlpriv->use_new_trx_flow)
- entry = (u8 *)(&ring->buffer_desc
- [ring->idx]);
- else
- entry = (u8 *)(&ring->desc[ring->idx]);
-
- pci_unmap_single(rtlpci->pdev,
- rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
- true, HW_DESC_TXBUFF_ADDR),
- skb->len, PCI_DMA_TODEVICE);
- dev_kfree_skb_irq(skb);
- ring->idx = (ring->idx + 1) % ring->entries;
- }
-
- if (rtlpriv->use_new_trx_flow) {
- rtlpci->tx_ring[i].cur_tx_rp = 0;
- rtlpci->tx_ring[i].cur_tx_wp = 0;
- }
-
- ring->idx = 0;
- ring->entries = rtlpci->txringcount[i];
- }
- }
- spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
-
- return 0;
-}
-
-static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- struct sk_buff *skb)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_sta_info *sta_entry = NULL;
- u8 tid = rtl_get_tid(skb);
- __le16 fc = rtl_get_fc(skb);
-
- if (!sta)
- return false;
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
-
- if (!rtlpriv->rtlhal.earlymode_enable)
- return false;
- if (ieee80211_is_nullfunc(fc))
- return false;
- if (ieee80211_is_qos_nullfunc(fc))
- return false;
- if (ieee80211_is_pspoll(fc))
- return false;
- if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
- return false;
- if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
- return false;
- if (tid > 7)
- return false;
-
- /* maybe every tid should be checked */
- if (!rtlpriv->link_info.higher_busytxtraffic[tid])
- return false;
-
- spin_lock_bh(&rtlpriv->locks.waitq_lock);
- skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
- spin_unlock_bh(&rtlpriv->locks.waitq_lock);
-
- return true;
-}
-
-static int rtl_pci_tx(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- struct sk_buff *skb,
- struct rtl_tcb_desc *ptcb_desc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_sta_info *sta_entry = NULL;
- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
- struct rtl8192_tx_ring *ring;
- struct rtl_tx_desc *pdesc;
- struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
- u16 idx;
- u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
- unsigned long flags;
- struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
- __le16 fc = rtl_get_fc(skb);
- u8 *pda_addr = hdr->addr1;
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- /*ssn */
- u8 tid = 0;
- u16 seq_number = 0;
- u8 own;
- u8 temp_one = 1;
-
- if (ieee80211_is_mgmt(fc))
- rtl_tx_mgmt_proc(hw, skb);
-
- if (rtlpriv->psc.sw_ps_enabled) {
- if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
- !ieee80211_has_pm(fc))
- hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
- }
-
- rtl_action_proc(hw, skb, true);
-
- if (is_multicast_ether_addr(pda_addr))
- rtlpriv->stats.txbytesmulticast += skb->len;
- else if (is_broadcast_ether_addr(pda_addr))
- rtlpriv->stats.txbytesbroadcast += skb->len;
- else
- rtlpriv->stats.txbytesunicast += skb->len;
-
- spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
- ring = &rtlpci->tx_ring[hw_queue];
- if (hw_queue != BEACON_QUEUE) {
- if (rtlpriv->use_new_trx_flow)
- idx = ring->cur_tx_wp;
- else
- idx = (ring->idx + skb_queue_len(&ring->queue)) %
- ring->entries;
- } else {
- idx = 0;
- }
-
- pdesc = &ring->desc[idx];
- if (rtlpriv->use_new_trx_flow) {
- ptx_bd_desc = &ring->buffer_desc[idx];
- } else {
- own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
- true, HW_DESC_OWN);
-
- if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
- hw_queue, ring->idx, idx,
- skb_queue_len(&ring->queue));
-
- spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
- flags);
- return skb->len;
- }
- }
-
- if (rtlpriv->cfg->ops->get_available_desc &&
- rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "get_available_desc fail\n");
- spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
- return skb->len;
- }
-
- if (ieee80211_is_data_qos(fc)) {
- tid = rtl_get_tid(skb);
- if (sta) {
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- seq_number = (le16_to_cpu(hdr->seq_ctrl) &
- IEEE80211_SCTL_SEQ) >> 4;
- seq_number += 1;
-
- if (!ieee80211_has_morefrags(hdr->frame_control))
- sta_entry->tids[tid].seq_number = seq_number;
- }
- }
-
- if (ieee80211_is_data(fc))
- rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
-
- rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
- (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
-
- __skb_queue_tail(&ring->queue, skb);
-
- if (rtlpriv->use_new_trx_flow) {
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
- HW_DESC_OWN, &hw_queue);
- } else {
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
- HW_DESC_OWN, &temp_one);
- }
-
- if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
- hw_queue != BEACON_QUEUE) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
- "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
- hw_queue, ring->idx, idx,
- skb_queue_len(&ring->queue));
-
- ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
- }
-
- spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
-
- rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
-
- return 0;
-}
-
-static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- u16 i = 0;
- int queue_id;
- struct rtl8192_tx_ring *ring;
-
- if (mac->skip_scan)
- return;
-
- for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
- u32 queue_len;
-
- if (((queues >> queue_id) & 0x1) == 0) {
- queue_id--;
- continue;
- }
- ring = &pcipriv->dev.tx_ring[queue_id];
- queue_len = skb_queue_len(&ring->queue);
- if (queue_len == 0 || queue_id == BEACON_QUEUE ||
- queue_id == TXCMD_QUEUE) {
- queue_id--;
- continue;
- } else {
- msleep(20);
- i++;
- }
-
- /* we just wait 1s for all queues */
- if (rtlpriv->psc.rfpwr_state == ERFOFF ||
- is_hal_stop(rtlhal) || i >= 200)
- return;
- }
-}
-
-static void rtl_pci_deinit(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- _rtl_pci_deinit_trx_ring(hw);
-
- synchronize_irq(rtlpci->pdev->irq);
- tasklet_kill(&rtlpriv->works.irq_tasklet);
- cancel_work_sync(&rtlpriv->works.lps_change_work);
-
- flush_workqueue(rtlpriv->works.rtl_wq);
- destroy_workqueue(rtlpriv->works.rtl_wq);
-}
-
-static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
-{
- int err;
-
- _rtl_pci_init_struct(hw, pdev);
-
- err = _rtl_pci_init_trx_ring(hw);
- if (err) {
- pr_err("tx ring initialization failed\n");
- return err;
- }
-
- return 0;
-}
-
-static int rtl_pci_start(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
-
- int err;
-
- rtl_pci_reset_trx_ring(hw);
-
- rtlpci->driver_is_goingto_unload = false;
- if (rtlpriv->cfg->ops->get_btc_status &&
- rtlpriv->cfg->ops->get_btc_status()) {
- rtlpriv->btcoexist.btc_info.ap_num = 36;
- rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
- rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
- } else if (rtlpriv->btcoexist.btc_ops) {
- rtlpriv->btcoexist.btc_ops->btc_init_variables_wifi_only(
- rtlpriv);
- }
-
- err = rtlpriv->cfg->ops->hw_init(hw);
- if (err) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "Failed to config hardware!\n");
- return err;
- }
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
- &rtlmac->retry_long);
-
- rtlpriv->cfg->ops->enable_interrupt(hw);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
-
- rtl_init_rx_config(hw);
-
- /*should be after adapter start and interrupt enable. */
- set_hal_start(rtlhal);
-
- RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
-
- rtlpci->up_first_time = false;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
- return 0;
-}
-
-static void rtl_pci_stop(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- unsigned long flags;
- u8 rf_timeout = 0;
-
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
-
- if (rtlpriv->btcoexist.btc_ops)
- rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
-
- /*
- *should be before disable interrupt&adapter
- *and will do it immediately.
- */
- set_hal_stop(rtlhal);
-
- rtlpci->driver_is_goingto_unload = true;
- rtlpriv->cfg->ops->disable_interrupt(hw);
- cancel_work_sync(&rtlpriv->works.lps_change_work);
-
- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
- while (ppsc->rfchange_inprogress) {
- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
- if (rf_timeout > 100) {
- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
- break;
- }
- mdelay(1);
- rf_timeout++;
- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
- }
- ppsc->rfchange_inprogress = true;
- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
-
- rtlpriv->cfg->ops->hw_disable(hw);
- /* some things are not needed if firmware not available */
- if (!rtlpriv->max_fw_size)
- return;
- rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
-
- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
- ppsc->rfchange_inprogress = false;
- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
-
- rtl_pci_enable_aspm(hw);
-}
-
-static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
- struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct pci_dev *bridge_pdev = pdev->bus->self;
- u16 venderid;
- u16 deviceid;
- u8 revisionid;
- u16 irqline;
- u8 tmp;
-
- pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
- venderid = pdev->vendor;
- deviceid = pdev->device;
- pci_read_config_byte(pdev, 0x8, &revisionid);
- pci_read_config_word(pdev, 0x3C, &irqline);
-
- /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
- * r8192e_pci, and RTL8192SE, which uses this driver. If the
- * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
- * the correct driver is r8192e_pci, thus this routine should
- * return false.
- */
- if (deviceid == RTL_PCI_8192SE_DID &&
- revisionid == RTL_PCI_REVISION_ID_8192PCIE)
- return false;
-
- if (deviceid == RTL_PCI_8192_DID ||
- deviceid == RTL_PCI_0044_DID ||
- deviceid == RTL_PCI_0047_DID ||
- deviceid == RTL_PCI_8192SE_DID ||
- deviceid == RTL_PCI_8174_DID ||
- deviceid == RTL_PCI_8173_DID ||
- deviceid == RTL_PCI_8172_DID ||
- deviceid == RTL_PCI_8171_DID) {
- switch (revisionid) {
- case RTL_PCI_REVISION_ID_8192PCIE:
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "8192 PCI-E is found - vid/did=%x/%x\n",
- venderid, deviceid);
- rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
- return false;
- case RTL_PCI_REVISION_ID_8192SE:
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "8192SE is found - vid/did=%x/%x\n",
- venderid, deviceid);
- rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
- break;
- default:
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "Err: Unknown device - vid/did=%x/%x\n",
- venderid, deviceid);
- rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
- break;
- }
- } else if (deviceid == RTL_PCI_8723AE_DID) {
- rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "8723AE PCI-E is found - vid/did=%x/%x\n",
- venderid, deviceid);
- } else if (deviceid == RTL_PCI_8192CET_DID ||
- deviceid == RTL_PCI_8192CE_DID ||
- deviceid == RTL_PCI_8191CE_DID ||
- deviceid == RTL_PCI_8188CE_DID) {
- rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "8192C PCI-E is found - vid/did=%x/%x\n",
- venderid, deviceid);
- } else if (deviceid == RTL_PCI_8192DE_DID ||
- deviceid == RTL_PCI_8192DE_DID2) {
- rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "8192D PCI-E is found - vid/did=%x/%x\n",
- venderid, deviceid);
- } else if (deviceid == RTL_PCI_8188EE_DID) {
- rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Find adapter, Hardware type is 8188EE\n");
- } else if (deviceid == RTL_PCI_8723BE_DID) {
- rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Find adapter, Hardware type is 8723BE\n");
- } else if (deviceid == RTL_PCI_8192EE_DID) {
- rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Find adapter, Hardware type is 8192EE\n");
- } else if (deviceid == RTL_PCI_8821AE_DID) {
- rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Find adapter, Hardware type is 8821AE\n");
- } else if (deviceid == RTL_PCI_8812AE_DID) {
- rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Find adapter, Hardware type is 8812AE\n");
- } else if (deviceid == RTL_PCI_8822BE_DID) {
- rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
- rtlhal->bandset = BAND_ON_BOTH;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Find adapter, Hardware type is 8822BE\n");
- } else {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "Err: Unknown device - vid/did=%x/%x\n",
- venderid, deviceid);
-
- rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
- }
-
- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
- if (revisionid == 0 || revisionid == 1) {
- if (revisionid == 0) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Find 92DE MAC0\n");
- rtlhal->interfaceindex = 0;
- } else if (revisionid == 1) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Find 92DE MAC1\n");
- rtlhal->interfaceindex = 1;
- }
- } else {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
- venderid, deviceid, revisionid);
- rtlhal->interfaceindex = 0;
- }
- }
-
- switch (rtlhal->hw_type) {
- case HARDWARE_TYPE_RTL8192EE:
- case HARDWARE_TYPE_RTL8822BE:
- /* use new trx flow */
- rtlpriv->use_new_trx_flow = true;
- break;
-
- default:
- rtlpriv->use_new_trx_flow = false;
- break;
- }
-
- /*find bus info */
- pcipriv->ndis_adapter.busnumber = pdev->bus->number;
- pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
- pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
-
- /*find bridge info */
- pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
- /* some ARM have no bridge_pdev and will crash here
- * so we should check if bridge_pdev is NULL
- */
- if (bridge_pdev) {
- /*find bridge info if available */
- pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
- for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
- if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
- pcipriv->ndis_adapter.pcibridge_vendor = tmp;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "Pci Bridge Vendor is found index: %d\n",
- tmp);
- break;
- }
- }
- }
-
- if (pcipriv->ndis_adapter.pcibridge_vendor !=
- PCI_BRIDGE_VENDOR_UNKNOWN) {
- pcipriv->ndis_adapter.pcibridge_busnum =
- bridge_pdev->bus->number;
- pcipriv->ndis_adapter.pcibridge_devnum =
- PCI_SLOT(bridge_pdev->devfn);
- pcipriv->ndis_adapter.pcibridge_funcnum =
- PCI_FUNC(bridge_pdev->devfn);
- pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
- pci_pcie_cap(bridge_pdev);
- pcipriv->ndis_adapter.num4bytes =
- (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
-
- rtl_pci_get_linkcontrol_field(hw);
-
- if (pcipriv->ndis_adapter.pcibridge_vendor ==
- PCI_BRIDGE_VENDOR_AMD) {
- pcipriv->ndis_adapter.amd_l1_patch =
- rtl_pci_get_amd_l1_patch(hw);
- }
- }
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
- pcipriv->ndis_adapter.busnumber,
- pcipriv->ndis_adapter.devnumber,
- pcipriv->ndis_adapter.funcnumber,
- pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
- pcipriv->ndis_adapter.pcibridge_busnum,
- pcipriv->ndis_adapter.pcibridge_devnum,
- pcipriv->ndis_adapter.pcibridge_funcnum,
- pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
- pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
- pcipriv->ndis_adapter.pcibridge_linkctrlreg,
- pcipriv->ndis_adapter.amd_l1_patch);
-
- rtl_pci_parse_configuration(pdev, hw);
- list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
-
- return true;
-}
-
-static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
- int ret;
-
- ret = pci_enable_msi(rtlpci->pdev);
- if (ret < 0)
- return ret;
-
- ret = request_irq(rtlpci->pdev->irq, _rtl_pci_interrupt,
- IRQF_SHARED, KBUILD_MODNAME, hw);
- if (ret < 0) {
- pci_disable_msi(rtlpci->pdev);
- return ret;
- }
-
- rtlpci->using_msi = true;
-
- RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
- "MSI Interrupt Mode!\n");
- return 0;
-}
-
-static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
- int ret;
-
- ret = request_irq(rtlpci->pdev->irq, _rtl_pci_interrupt,
- IRQF_SHARED, KBUILD_MODNAME, hw);
- if (ret < 0)
- return ret;
-
- rtlpci->using_msi = false;
- RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
- "Pin-based Interrupt Mode!\n");
- return 0;
-}
-
-static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
-{
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
- int ret;
-
- if (rtlpci->msi_support) {
- ret = rtl_pci_intr_mode_msi(hw);
- if (ret < 0)
- ret = rtl_pci_intr_mode_legacy(hw);
- } else {
- ret = rtl_pci_intr_mode_legacy(hw);
- }
- return ret;
-}
-
-static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
-{
- u8 value;
-
- pci_read_config_byte(pdev, 0x719, &value);
-
- /* 0x719 Bit5 is DMA64 bit fetch. */
- if (dma64)
- value |= BIT(5);
- else
- value &= ~BIT(5);
-
- pci_write_config_byte(pdev, 0x719, value);
-}
-
-int rtl_pci_probe(struct pci_dev *pdev,
- const struct pci_device_id *id)
-{
- struct ieee80211_hw *hw = NULL;
-
- struct rtl_priv *rtlpriv = NULL;
- struct rtl_pci_priv *pcipriv = NULL;
- struct rtl_pci *rtlpci;
- unsigned long pmem_start, pmem_len, pmem_flags;
- int err;
-
- err = rtl_core_module_init();
- if (err)
- return err;
- err = pci_enable_device(pdev);
- if (err) {
- WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
- pci_name(pdev));
- return err;
- }
-
- if (((struct rtl_hal_cfg *)(id->driver_data))->mod_params->dma64 &&
- !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
- if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
- WARN_ONCE(true,
- "Unable to obtain 64bit DMA for consistent allocations\n");
- err = -ENOMEM;
- goto fail1;
- }
-
- platform_enable_dma64(pdev, true);
- } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
- if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
- WARN_ONCE(true,
- "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
- err = -ENOMEM;
- goto fail1;
- }
-
- platform_enable_dma64(pdev, false);
- }
-
- pci_set_master(pdev);
-
- hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
- sizeof(struct rtl_priv), &rtl_ops);
- if (!hw) {
- WARN_ONCE(true,
- "%s : ieee80211 alloc failed\n", pci_name(pdev));
- err = -ENOMEM;
- goto fail1;
- }
-
- SET_IEEE80211_DEV(hw, &pdev->dev);
- pci_set_drvdata(pdev, hw);
-
- rtlpriv = hw->priv;
- rtlpriv->hw = hw;
- pcipriv = (void *)rtlpriv->priv;
- pcipriv->dev.pdev = pdev;
- init_completion(&rtlpriv->firmware_loading_complete);
- /*proximity init here*/
- rtlpriv->proximity.proxim_on = false;
-
- pcipriv = (void *)rtlpriv->priv;
- pcipriv->dev.pdev = pdev;
-
- /* init cfg & intf_ops */
- rtlpriv->rtlhal.interface = INTF_PCI;
- rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
- rtlpriv->intf_ops = &rtl_pci_ops;
- rtlpriv->glb_var = &rtl_global_var;
-
- /* MEM map */
- err = pci_request_regions(pdev, KBUILD_MODNAME);
- if (err) {
- WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
- goto fail1;
- }
-
- pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
- pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
- pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
-
- /*shared mem start */
- rtlpriv->io.pci_mem_start =
- (unsigned long)pci_iomap(pdev,
- rtlpriv->cfg->bar_id, pmem_len);
- if (rtlpriv->io.pci_mem_start == 0) {
- WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
- err = -ENOMEM;
- goto fail2;
- }
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
- pmem_start, pmem_len, pmem_flags,
- rtlpriv->io.pci_mem_start);
-
- /* Disable Clk Request */
- pci_write_config_byte(pdev, 0x81, 0);
- /* leave D3 mode */
- pci_write_config_byte(pdev, 0x44, 0);
- pci_write_config_byte(pdev, 0x04, 0x06);
- pci_write_config_byte(pdev, 0x04, 0x07);
-
- /* find adapter */
- if (!_rtl_pci_find_adapter(pdev, hw)) {
- err = -ENODEV;
- goto fail2;
- }
-
- /* Init IO handler */
- _rtl_pci_io_handler_init(&pdev->dev, hw);
-
- /*like read eeprom and so on */
- rtlpriv->cfg->ops->read_eeprom_info(hw);
-
- if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
- pr_err("Can't init_sw_vars\n");
- err = -ENODEV;
- goto fail3;
- }
- rtlpriv->cfg->ops->init_sw_leds(hw);
-
- /*aspm */
- rtl_pci_init_aspm(hw);
-
- /* Init mac80211 sw */
- err = rtl_init_core(hw);
- if (err) {
- pr_err("Can't allocate sw for mac80211\n");
- goto fail3;
- }
-
- /* Init PCI sw */
- err = rtl_pci_init(hw, pdev);
- if (err) {
- pr_err("Failed to init PCI\n");
- goto fail3;
- }
-
- err = ieee80211_register_hw(hw);
- if (err) {
- pr_err("Can't register mac80211 hw.\n");
- err = -ENODEV;
- goto fail3;
- }
- rtlpriv->mac80211.mac80211_registered = 1;
-
- /* add for debug */
- rtl_debug_add_one(hw);
-
- /*init rfkill */
- rtl_init_rfkill(hw); /* Init PCI sw */
-
- rtlpci = rtl_pcidev(pcipriv);
- err = rtl_pci_intr_mode_decide(hw);
- if (err) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "%s: failed to register IRQ handler\n",
- wiphy_name(hw->wiphy));
- goto fail3;
- }
- rtlpci->irq_alloc = 1;
-
- set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
- return 0;
-
-fail3:
- pci_set_drvdata(pdev, NULL);
- rtl_deinit_core(hw);
-
-fail2:
- if (rtlpriv->io.pci_mem_start != 0)
- pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
-
- pci_release_regions(pdev);
- complete(&rtlpriv->firmware_loading_complete);
-
-fail1:
- if (hw)
- ieee80211_free_hw(hw);
- pci_disable_device(pdev);
-
- return err;
-}
-
-void rtl_pci_disconnect(struct pci_dev *pdev)
-{
- struct ieee80211_hw *hw = pci_get_drvdata(pdev);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
- struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
-
- /* just in case driver is removed before firmware callback */
- wait_for_completion(&rtlpriv->firmware_loading_complete);
- clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
-
- /* remove form debug */
- rtl_debug_remove_one(hw);
-
- /*ieee80211_unregister_hw will call ops_stop */
- if (rtlmac->mac80211_registered == 1) {
- ieee80211_unregister_hw(hw);
- rtlmac->mac80211_registered = 0;
- } else {
- rtl_deinit_deferred_work(hw);
- rtlpriv->intf_ops->adapter_stop(hw);
- }
- rtlpriv->cfg->ops->disable_interrupt(hw);
-
- /*deinit rfkill */
- rtl_deinit_rfkill(hw);
-
- rtl_pci_deinit(hw);
- rtl_deinit_core(hw);
- rtlpriv->cfg->ops->deinit_sw_vars(hw);
-
- if (rtlpci->irq_alloc) {
- free_irq(rtlpci->pdev->irq, hw);
- rtlpci->irq_alloc = 0;
- }
-
- if (rtlpci->using_msi)
- pci_disable_msi(rtlpci->pdev);
-
- list_del(&rtlpriv->list);
- if (rtlpriv->io.pci_mem_start != 0) {
- pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
- pci_release_regions(pdev);
- }
-
- pci_disable_device(pdev);
-
- rtl_pci_disable_aspm(hw);
-
- pci_set_drvdata(pdev, NULL);
-
- ieee80211_free_hw(hw);
- rtl_core_module_exit();
-}
-
-#ifdef CONFIG_PM_SLEEP
-/***************************************
- * kernel pci power state define:
- * PCI_D0 ((pci_power_t __force) 0)
- * PCI_D1 ((pci_power_t __force) 1)
- * PCI_D2 ((pci_power_t __force) 2)
- * PCI_D3hot ((pci_power_t __force) 3)
- * PCI_D3cold ((pci_power_t __force) 4)
- * PCI_UNKNOWN ((pci_power_t __force) 5)
-
- * This function is called when system
- * goes into suspend state mac80211 will
- * call rtl_mac_stop() from the mac80211
- * suspend function first, So there is
- * no need to call hw_disable here.
- ****************************************/
-int rtl_pci_suspend(struct device *dev)
-{
- struct pci_dev *pdev = to_pci_dev(dev);
- struct ieee80211_hw *hw = pci_get_drvdata(pdev);
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtlpriv->cfg->ops->hw_suspend(hw);
- rtl_deinit_rfkill(hw);
-
- return 0;
-}
-
-int rtl_pci_resume(struct device *dev)
-{
- struct pci_dev *pdev = to_pci_dev(dev);
- struct ieee80211_hw *hw = pci_get_drvdata(pdev);
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtlpriv->cfg->ops->hw_resume(hw);
- rtl_init_rfkill(hw);
- return 0;
-}
-#endif /* CONFIG_PM_SLEEP */
-
-const struct rtl_intf_ops rtl_pci_ops = {
- .read_efuse_byte = read_efuse_byte,
- .adapter_start = rtl_pci_start,
- .adapter_stop = rtl_pci_stop,
- .check_buddy_priv = rtl_pci_check_buddy_priv,
- .adapter_tx = rtl_pci_tx,
- .flush = rtl_pci_flush,
- .reset_trx_ring = rtl_pci_reset_trx_ring,
- .waitq_insert = rtl_pci_tx_chk_waitq_insert,
-
- .disable_aspm = rtl_pci_disable_aspm,
- .enable_aspm = rtl_pci_enable_aspm,
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_PCI_H__
-#define __RTL_PCI_H__
-
-#include <linux/pci.h>
-/* 1: MSDU packet queue,
- * 2: Rx Command Queue
- */
-#define RTL_PCI_RX_MPDU_QUEUE 0
-#define RTL_PCI_RX_CMD_QUEUE 1
-#define RTL_PCI_MAX_RX_QUEUE 2
-
-#define RTL_PCI_MAX_RX_COUNT 512/*64*/
-#define RTL_PCI_MAX_TX_QUEUE_COUNT 9
-
-#define RT_TXDESC_NUM 128
-#define TX_DESC_NUM_92E 512
-#define TX_DESC_NUM_8822B 512
-#define RT_TXDESC_NUM_BE_QUEUE 256
-
-#define BK_QUEUE 0
-#define BE_QUEUE 1
-#define VI_QUEUE 2
-#define VO_QUEUE 3
-#define BEACON_QUEUE 4
-#define TXCMD_QUEUE 5
-#define MGNT_QUEUE 6
-#define HIGH_QUEUE 7
-#define HCCA_QUEUE 8
-#define H2C_QUEUE TXCMD_QUEUE /* In 8822B */
-
-#define RTL_PCI_DEVICE(vend, dev, cfg) \
- .vendor = (vend), \
- .device = (dev), \
- .subvendor = PCI_ANY_ID, \
- .subdevice = PCI_ANY_ID,\
- .driver_data = (kernel_ulong_t)&(cfg)
-
-#define INTEL_VENDOR_ID 0x8086
-#define SIS_VENDOR_ID 0x1039
-#define ATI_VENDOR_ID 0x1002
-#define ATI_DEVICE_ID 0x7914
-#define AMD_VENDOR_ID 0x1022
-
-#define PCI_MAX_BRIDGE_NUMBER 255
-#define PCI_MAX_DEVICES 32
-#define PCI_MAX_FUNCTION 8
-
-#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
-#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
-
-#define PCI_CLASS_BRIDGE_DEV 0x06
-#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
-#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
-#define PCI_CAP_ID_EXP 0x10
-
-#define U1DONTCARE 0xFF
-#define U2DONTCARE 0xFFFF
-#define U4DONTCARE 0xFFFFFFFF
-
-#define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
-#define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
-#define RTL_PCI_8174_DID 0x8174 /*8192 SE */
-#define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
-#define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
-#define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
-#define RTL_PCI_8723AE_DID 0x8723 /*8723AE */
-#define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
-#define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
-#define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
-#define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
-#define RTL_PCI_700F_DID 0x700F
-#define RTL_PCI_701F_DID 0x701F
-#define RTL_PCI_DLINK_DID 0x3304
-#define RTL_PCI_8723AE_DID 0x8723 /*8723e */
-#define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
-#define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
-#define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
-#define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
-#define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
-#define RTL_PCI_8192DE_DID 0x8193 /*8192de */
-#define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
-#define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/
-#define RTL_PCI_8723BE_DID 0xB723 /*8723be*/
-#define RTL_PCI_8192EE_DID 0x818B /*8192ee*/
-#define RTL_PCI_8821AE_DID 0x8821 /*8821ae*/
-#define RTL_PCI_8812AE_DID 0x8812 /*8812ae*/
-#define RTL_PCI_8822BE_DID 0xB822 /*8822be*/
-
-/*8192 support 16 pages of IO registers*/
-#define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
-#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
-#define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
-#define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
-#define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
-
-#define RTL_PCI_REVISION_ID_8190PCI 0x00
-#define RTL_PCI_REVISION_ID_8192PCIE 0x01
-#define RTL_PCI_REVISION_ID_8192SE 0x10
-#define RTL_PCI_REVISION_ID_8192CE 0x1
-#define RTL_PCI_REVISION_ID_8192DE 0x0
-
-#define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
-
-enum pci_bridge_vendor {
- PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */
- PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/
- PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/
- PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/
- PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/
- PCI_BRIDGE_VENDOR_MAX,
-};
-
-struct rtl_pci_capabilities_header {
- u8 capability_id;
- u8 next;
-};
-
-/* In new TRX flow, Buffer_desc is new concept
- * But TX wifi info == TX descriptor in old flow
- * RX wifi info == RX descriptor in old flow
- */
-struct rtl_tx_buffer_desc {
- u32 dword[4 * (1 << (BUFDESC_SEG_NUM + 1))];
-} __packed;
-
-struct rtl_tx_desc {
- u32 dword[16];
-} __packed;
-
-struct rtl_rx_buffer_desc { /*rx buffer desc*/
- u32 dword[4];
-} __packed;
-
-struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
- u32 dword[8];
-} __packed;
-
-struct rtl_tx_cmd_desc {
- u32 dword[16];
-} __packed;
-
-struct rtl8192_tx_ring {
- struct rtl_tx_desc *desc;
- dma_addr_t dma;
- unsigned int idx;
- unsigned int entries;
- struct sk_buff_head queue;
- /*add for new trx flow*/
- struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
- dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
- u16 cur_tx_wp; /* current_tx_write_point */
- u16 cur_tx_rp; /* current_tx_read_point */
-};
-
-struct rtl8192_rx_ring {
- struct rtl_rx_desc *desc;
- dma_addr_t dma;
- unsigned int idx;
- struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
- /*add for new trx flow*/
- struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
- u16 next_rx_rp; /* next_rx_read_point */
-};
-
-struct rtl_pci {
- struct pci_dev *pdev;
- bool irq_enabled;
-
- bool driver_is_goingto_unload;
- bool up_first_time;
- bool first_init;
- bool being_init_adapter;
- bool init_ready;
-
- /*Tx */
- struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
- int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
- u32 transmit_config;
-
- /*Rx */
- struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
- int rxringcount;
- u16 rxbuffersize;
- u32 receive_config;
-
- /*irq */
- u8 irq_alloc;
- u32 irq_mask[4]; /* 0-1: normal, 2: unused, 3: h2c */
- u32 sys_irq_mask;
-
- /*Bcn control register setting */
- u32 reg_bcn_ctrl_val;
-
- /*ASPM*/
- u8 const_pci_aspm;
- u8 const_amdpci_aspm;
- u8 const_hwsw_rfoff_d3;
- u8 const_support_pciaspm;
- /*pci-e bridge */
- u8 const_hostpci_aspm_setting;
- /*pci-e device */
- u8 const_devicepci_aspm_setting;
- /* If it supports ASPM, Offset[560h] = 0x40,
- * otherwise Offset[560h] = 0x00.
- */
- bool support_aspm;
- bool support_backdoor;
-
- /*QOS & EDCA */
- enum acm_method acm_method;
-
- u16 shortretry_limit;
- u16 longretry_limit;
-
- /* MSI support */
- bool msi_support;
- bool using_msi;
- /* interrupt clear before set */
- bool int_clear;
-};
-
-struct mp_adapter {
- u8 linkctrl_reg;
-
- u8 busnumber;
- u8 devnumber;
- u8 funcnumber;
-
- u8 pcibridge_busnum;
- u8 pcibridge_devnum;
- u8 pcibridge_funcnum;
-
- u8 pcibridge_vendor;
- u16 pcibridge_vendorid;
- u16 pcibridge_deviceid;
-
- u8 num4bytes;
-
- u8 pcibridge_pciehdr_offset;
- u8 pcibridge_linkctrlreg;
-
- bool amd_l1_patch;
-};
-
-struct rtl_pci_priv {
- struct bt_coexist_info bt_coexist;
- struct rtl_led_ctl ledctl;
- struct rtl_pci dev;
- struct mp_adapter ndis_adapter;
-};
-
-#define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
-#define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
-
-int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
-
-extern const struct rtl_intf_ops rtl_pci_ops;
-
-int rtl_pci_probe(struct pci_dev *pdev,
- const struct pci_device_id *id);
-void rtl_pci_disconnect(struct pci_dev *pdev);
-#ifdef CONFIG_PM_SLEEP
-int rtl_pci_suspend(struct device *dev);
-int rtl_pci_resume(struct device *dev);
-#endif /* CONFIG_PM_SLEEP */
-static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
-{
- return readb((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
-}
-
-static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
-{
- return readw((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
-}
-
-static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
-{
- return readl((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
-}
-
-static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
-{
- writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
-}
-
-static inline void pci_write16_async(struct rtl_priv *rtlpriv,
- u32 addr, u16 val)
-{
- writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
-}
-
-static inline void pci_write32_async(struct rtl_priv *rtlpriv,
- u32 addr, u32 val)
-{
- writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
-}
-
-static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size)
-{
- if (rp <= wp)
- return size - 1 + rp - wp;
- return rp - wp - 1;
-}
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, \
- _delta_thermal) \
- do { \
- for (_offset = 0; _offset < _size; _offset++) { \
- if (_delta_thermal < \
- thermal_threshold[_direction][_offset]) { \
- if (_offset != 0) \
- _offset--; \
- break; \
- } \
- } \
- if (_offset >= _size) \
- _offset = _size - 1; \
- } while (0)
-
-static inline void phydm_set_calibrate_info_up(
- struct phy_dm_struct *dm, struct txpwrtrack_cfg *c, u8 delta,
- struct dm_rf_calibration_struct *cali_info,
- u8 *delta_swing_table_idx_tup_a, u8 *delta_swing_table_idx_tup_b,
- u8 *delta_swing_table_idx_tup_c, u8 *delta_swing_table_idx_tup_d)
-{
- u8 p = 0;
-
- for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++) {
- cali_info->delta_power_index_last[p] =
- cali_info->delta_power_index
- [p]; /*recording poer index offset*/
- switch (p) {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_swing_table_idx_tup_b[%d] = %d\n",
- delta, delta_swing_table_idx_tup_b[delta]);
-
- cali_info->delta_power_index[p] =
- delta_swing_table_idx_tup_b[delta];
- /*Record delta swing for mix mode pwr tracking*/
- cali_info->absolute_ofdm_swing_idx[p] =
- delta_swing_table_idx_tup_b[delta];
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n",
- cali_info->absolute_ofdm_swing_idx[p]);
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_swing_table_idx_tup_c[%d] = %d\n",
- delta, delta_swing_table_idx_tup_c[delta]);
-
- cali_info->delta_power_index[p] =
- delta_swing_table_idx_tup_c[delta];
- /*Record delta swing for mix mode pwr tracking*/
- cali_info->absolute_ofdm_swing_idx[p] =
- delta_swing_table_idx_tup_c[delta];
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n",
- cali_info->absolute_ofdm_swing_idx[p]);
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_swing_table_idx_tup_d[%d] = %d\n",
- delta, delta_swing_table_idx_tup_d[delta]);
-
- cali_info->delta_power_index[p] =
- delta_swing_table_idx_tup_d[delta];
- /*Record delta swing for mix mode pwr tracking*/
- cali_info->absolute_ofdm_swing_idx[p] =
- delta_swing_table_idx_tup_d[delta];
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n",
- cali_info->absolute_ofdm_swing_idx[p]);
- break;
-
- default:
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_swing_table_idx_tup_a[%d] = %d\n",
- delta, delta_swing_table_idx_tup_a[delta]);
-
- cali_info->delta_power_index[p] =
- delta_swing_table_idx_tup_a[delta];
- /*Record delta swing for mix mode pwr tracking*/
- cali_info->absolute_ofdm_swing_idx[p] =
- delta_swing_table_idx_tup_a[delta];
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n",
- cali_info->absolute_ofdm_swing_idx[p]);
- break;
- }
- }
-}
-
-static inline void phydm_set_calibrate_info_down(
- struct phy_dm_struct *dm, struct txpwrtrack_cfg *c, u8 delta,
- struct dm_rf_calibration_struct *cali_info,
- u8 *delta_swing_table_idx_tdown_a, u8 *delta_swing_table_idx_tdown_b,
- u8 *delta_swing_table_idx_tdown_c, u8 *delta_swing_table_idx_tdown_d)
-{
- u8 p = 0;
-
- for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++) {
- cali_info->delta_power_index_last[p] =
- cali_info->delta_power_index
- [p]; /*recording poer index offset*/
-
- switch (p) {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_swing_table_idx_tdown_b[%d] = %d\n",
- delta,
- delta_swing_table_idx_tdown_b[delta]);
- cali_info->delta_power_index[p] =
- -1 * delta_swing_table_idx_tdown_b[delta];
- /*Record delta swing for mix mode pwr tracking*/
- cali_info->absolute_ofdm_swing_idx[p] =
- -1 * delta_swing_table_idx_tdown_b[delta];
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n",
- cali_info->absolute_ofdm_swing_idx[p]);
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_swing_table_idx_tdown_c[%d] = %d\n",
- delta,
- delta_swing_table_idx_tdown_c[delta]);
- cali_info->delta_power_index[p] =
- -1 * delta_swing_table_idx_tdown_c[delta];
- /*Record delta swing for mix mode pwr tracking*/
- cali_info->absolute_ofdm_swing_idx[p] =
- -1 * delta_swing_table_idx_tdown_c[delta];
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n",
- cali_info->absolute_ofdm_swing_idx[p]);
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_swing_table_idx_tdown_d[%d] = %d\n",
- delta,
- delta_swing_table_idx_tdown_d[delta]);
- cali_info->delta_power_index[p] =
- -1 * delta_swing_table_idx_tdown_d[delta];
- /*Record delta swing for mix mode pwr tracking*/
- cali_info->absolute_ofdm_swing_idx[p] =
- -1 * delta_swing_table_idx_tdown_d[delta];
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n",
- cali_info->absolute_ofdm_swing_idx[p]);
- break;
-
- default:
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_swing_table_idx_tdown_a[%d] = %d\n",
- delta,
- delta_swing_table_idx_tdown_a[delta]);
- cali_info->delta_power_index[p] =
- -1 * delta_swing_table_idx_tdown_a[delta];
- /*Record delta swing for mix mode pwr tracking*/
- cali_info->absolute_ofdm_swing_idx[p] =
- -1 * delta_swing_table_idx_tdown_a[delta];
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n",
- cali_info->absolute_ofdm_swing_idx[p]);
- break;
- }
- }
-}
-
-static inline void phydm_odm_tx_power_set(struct phy_dm_struct *dm,
- struct txpwrtrack_cfg *c,
- u8 indexforchannel, u8 flag)
-{
- u8 p = 0;
-
- if (dm->support_ic_type == ODM_RTL8188E ||
- dm->support_ic_type == ODM_RTL8192E ||
- dm->support_ic_type == ODM_RTL8821 ||
- dm->support_ic_type == ODM_RTL8812 ||
- dm->support_ic_type == ODM_RTL8723B ||
- dm->support_ic_type == ODM_RTL8814A ||
- dm->support_ic_type == ODM_RTL8703B ||
- dm->support_ic_type == ODM_RTL8188F ||
- dm->support_ic_type == ODM_RTL8822B ||
- dm->support_ic_type == ODM_RTL8723D ||
- dm->support_ic_type == ODM_RTL8821C ||
- dm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "**********Enter POWER Tracking MIX_MODE**********\n");
- for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++) {
- if (flag == 0)
- (*c->odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
- 0);
- else
- (*c->odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
- indexforchannel);
- }
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "**********Enter POWER Tracking BBSWING_MODE**********\n");
- for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++)
- (*c->odm_tx_pwr_track_set_pwr)(dm, BBSWING, p,
- indexforchannel);
- }
-}
-
-void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- /* JJ ADD 20161014 */
-
- if (dm->support_ic_type == ODM_RTL8822B)
- configure_txpower_track_8822b(config);
-}
-
-/* **********************************************************************
- * <20121113, Kordan> This function should be called when tx_agc changed.
- * Otherwise the previous compensation is gone, because we record the
- * delta of temperature between two TxPowerTracking watch dogs.
- *
- * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
- * need to call this function.
- * ***********************************************************************/
-void odm_clear_txpowertracking_state(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
- u8 p = 0;
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
- cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
- dm->rf_calibrate_info.CCK_index = 0;
-
- for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
- cali_info->bb_swing_idx_ofdm_base[p] =
- cali_info->default_ofdm_index;
- cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
- cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
-
- cali_info->power_index_offset[p] = 0;
- cali_info->delta_power_index[p] = 0;
- cali_info->delta_power_index_last[p] = 0;
-
- cali_info->absolute_ofdm_swing_idx[p] =
- 0; /* Initial Mix mode power tracking*/
- cali_info->remnant_ofdm_swing_idx[p] = 0;
- cali_info->kfree_offset[p] = 0;
- }
-
- cali_info->modify_tx_agc_flag_path_a =
- false; /*Initial at Modify Tx Scaling mode*/
- cali_info->modify_tx_agc_flag_path_b =
- false; /*Initial at Modify Tx Scaling mode*/
- cali_info->modify_tx_agc_flag_path_c =
- false; /*Initial at Modify Tx Scaling mode*/
- cali_info->modify_tx_agc_flag_path_d =
- false; /*Initial at Modify Tx Scaling mode*/
- cali_info->remnant_cck_swing_idx = 0;
- cali_info->thermal_value = rtlefu->eeprom_thermalmeter;
-
- cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
- cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
-}
-
-void odm_txpowertracking_callback_thermal_meter(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
- void *adapter = dm->adapter;
-
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
- s8 diff_DPK[4]; /* use 'for..loop' to initialize */
- u8 thermal_value_avg_count = 0;
- u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
-
- /* OFDM BB Swing should be less than +3.0dB (required by Arthur) */
- u8 OFDM_min_index = 0;
- /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
- u8 indexforchannel = 0;
- u8 power_tracking_type = 0; /* no specify type */
- u8 xtal_offset_eanble = 0;
-
- struct txpwrtrack_cfg c;
-
- /* 4 1. The following TWO tables decide the final index of
- * OFDM/CCK swing table.
- */
- u8 *delta_swing_table_idx_tup_a = NULL;
- u8 *delta_swing_table_idx_tdown_a = NULL;
- u8 *delta_swing_table_idx_tup_b = NULL;
- u8 *delta_swing_table_idx_tdown_b = NULL;
- /*for 8814 add by Yu Chen*/
- u8 *delta_swing_table_idx_tup_c = NULL;
- u8 *delta_swing_table_idx_tdown_c = NULL;
- u8 *delta_swing_table_idx_tup_d = NULL;
- u8 *delta_swing_table_idx_tdown_d = NULL;
- /*for Xtal Offset by James.Tung*/
- s8 *delta_swing_table_xtal_up = NULL;
- s8 *delta_swing_table_xtal_down = NULL;
-
- /* 4 2. Initialization ( 7 steps in total ) */
-
- configure_txpower_track(dm, &c);
-
- (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a,
- (u8 **)&delta_swing_table_idx_tdown_a,
- (u8 **)&delta_swing_table_idx_tup_b,
- (u8 **)&delta_swing_table_idx_tdown_b);
-
- if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
- (*c.get_delta_swing_table8814only)(
- dm, (u8 **)&delta_swing_table_idx_tup_c,
- (u8 **)&delta_swing_table_idx_tdown_c,
- (u8 **)&delta_swing_table_idx_tup_d,
- (u8 **)&delta_swing_table_idx_tdown_d);
- /* JJ ADD 20161014 */
- if (dm->support_ic_type &
- (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/
- (*c.get_delta_swing_xtal_table)(
- dm, (s8 **)&delta_swing_table_xtal_up,
- (s8 **)&delta_swing_table_xtal_down);
-
- cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
- cali_info->is_txpowertracking_init = true;
-
- /*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
- *<Kordan> We should keep updating ctrl variable according to HalData.
- *<Kordan> rf_calibrate_info.rega24 will be initialized when
- *ODM HW configuring, but MP configures with para files.
- */
- if (dm->mp_mode)
- cali_info->rega24 = 0x090e1317;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "===>%s\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
- __func__, cali_info->bb_swing_idx_cck_base,
- cali_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A],
- cali_info->default_ofdm_index);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "cali_info->txpowertrack_control=%d, rtlefu->eeprom_thermalmeter %d\n",
- cali_info->txpowertrack_control, rtlefu->eeprom_thermalmeter);
-
- thermal_value =
- (u8)odm_get_rf_reg(dm, ODM_RF_PATH_A, c.thermal_reg_addr,
- 0xfc00); /* 0x42: RF Reg[15:10] 88E */
-
- /*add log by zhao he, check c80/c94/c14/ca0 value*/
- if (dm->support_ic_type == ODM_RTL8723D) {
- regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
- regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
- regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
- regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n",
- regc80, regcd0, regcd4, regab4);
- }
- /* JJ ADD 20161014 */
- if (dm->support_ic_type == ODM_RTL8710B) {
- regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
- regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
- regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
- regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n",
- regc80, regcd0, regcd4, regab4);
- }
-
- if (!cali_info->txpowertrack_control)
- return;
-
- /*4 3. Initialize ThermalValues of rf_calibrate_info*/
-
- if (cali_info->is_reloadtxpowerindex)
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "reload ofdm index for band switch\n");
-
- /*4 4. Calculate average thermal meter*/
-
- cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] =
- thermal_value;
- cali_info->thermal_value_avg_index++;
- if (cali_info->thermal_value_avg_index ==
- c.average_thermal_num) /*Average times = c.average_thermal_num*/
- cali_info->thermal_value_avg_index = 0;
-
- for (i = 0; i < c.average_thermal_num; i++) {
- if (cali_info->thermal_value_avg[i]) {
- thermal_value_avg += cali_info->thermal_value_avg[i];
- thermal_value_avg_count++;
- }
- }
-
- if (thermal_value_avg_count) {
- /* Calculate Average thermal_value after average enough times */
- thermal_value =
- (u8)(thermal_value_avg / thermal_value_avg_count);
- cali_info->thermal_value_delta =
- thermal_value - rtlefu->eeprom_thermalmeter;
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n",
- thermal_value, rtlefu->eeprom_thermalmeter);
- }
-
- /* 4 5. Calculate delta, delta_LCK, delta_IQK. */
-
- /* "delta" is used to determine whether thermal value changes or not*/
- delta = (thermal_value > cali_info->thermal_value) ?
- (thermal_value - cali_info->thermal_value) :
- (cali_info->thermal_value - thermal_value);
- delta_LCK = (thermal_value > cali_info->thermal_value_lck) ?
- (thermal_value - cali_info->thermal_value_lck) :
- (cali_info->thermal_value_lck - thermal_value);
- delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ?
- (thermal_value - cali_info->thermal_value_iqk) :
- (cali_info->thermal_value_iqk - thermal_value);
-
- if (cali_info->thermal_value_iqk ==
- 0xff) { /*no PG, use thermal value for IQK*/
- cali_info->thermal_value_iqk = thermal_value;
- delta_IQK =
- (thermal_value > cali_info->thermal_value_iqk) ?
- (thermal_value - cali_info->thermal_value_iqk) :
- (cali_info->thermal_value_iqk - thermal_value);
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "no PG, use thermal_value for IQK\n");
- }
-
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
- diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
-
- /*4 6. If necessary, do LCK.*/
-
- if (!(dm->support_ic_type &
- ODM_RTL8821)) { /*no PG, do LCK at initial status*/
- if (cali_info->thermal_value_lck == 0xff) {
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "no PG, do LCK\n");
- cali_info->thermal_value_lck = thermal_value;
-
- /*Use RTLCK, so close power tracking driver LCK*/
- if (!(dm->support_ic_type & ODM_RTL8814A) &&
- c.phy_lc_calibrate)
- (*c.phy_lc_calibrate)(dm);
-
- delta_LCK =
- (thermal_value > cali_info->thermal_value_lck) ?
- (thermal_value -
- cali_info->thermal_value_lck) :
- (cali_info->thermal_value_lck -
- thermal_value);
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n",
- delta, delta_LCK, delta_IQK);
-
- /*Delta temperature is equal to or larger than 20 centigrade.*/
- if (delta_LCK >= c.threshold_iqk) {
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_LCK(%d) >= threshold_iqk(%d)\n",
- delta_LCK, c.threshold_iqk);
- cali_info->thermal_value_lck = thermal_value;
-
- /*Use RTLCK, so close power tracking driver LCK*/
- if (!(dm->support_ic_type & ODM_RTL8814A) &&
- c.phy_lc_calibrate)
- (*c.phy_lc_calibrate)(dm);
- }
- }
-
- /*3 7. If necessary, move the index of swing table to adjust Tx power.*/
-
- if (delta > 0 && cali_info->txpowertrack_control) {
- /* "delta" here is used to record the abs value of difference.*/
- delta = thermal_value > rtlefu->eeprom_thermalmeter ?
- (thermal_value - rtlefu->eeprom_thermalmeter) :
- (rtlefu->eeprom_thermalmeter - thermal_value);
- if (delta >= TXPWR_TRACK_TABLE_SIZE)
- delta = TXPWR_TRACK_TABLE_SIZE - 1;
-
- /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
-
- if (thermal_value > rtlefu->eeprom_thermalmeter) {
- phydm_set_calibrate_info_up(
- dm, &c, delta, cali_info,
- delta_swing_table_idx_tup_a,
- delta_swing_table_idx_tup_b,
- delta_swing_table_idx_tup_c,
- delta_swing_table_idx_tup_d);
- /* JJ ADD 20161014 */
- if (dm->support_ic_type &
- (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
- /*Save xtal_offset from Xtal table*/
-
- /*recording last Xtal offset*/
- cali_info->xtal_offset_last =
- cali_info->xtal_offset;
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "[Xtal] delta_swing_table_xtal_up[%d] = %d\n",
- delta,
- delta_swing_table_xtal_up[delta]);
- cali_info->xtal_offset =
- delta_swing_table_xtal_up[delta];
- xtal_offset_eanble =
- (cali_info->xtal_offset_last ==
- cali_info->xtal_offset) ?
- 0 :
- 1;
- }
-
- } else {
- phydm_set_calibrate_info_down(
- dm, &c, delta, cali_info,
- delta_swing_table_idx_tdown_a,
- delta_swing_table_idx_tdown_b,
- delta_swing_table_idx_tdown_c,
- delta_swing_table_idx_tdown_d);
- /* JJ ADD 20161014 */
- if (dm->support_ic_type &
- (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
- /*Save xtal_offset from Xtal table*/
-
- /*recording last Xtal offset*/
- cali_info->xtal_offset_last =
- cali_info->xtal_offset;
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "[Xtal] delta_swing_table_xtal_down[%d] = %d\n",
- delta,
- delta_swing_table_xtal_down[delta]);
- cali_info->xtal_offset =
- delta_swing_table_xtal_down[delta];
- xtal_offset_eanble =
- (cali_info->xtal_offset_last ==
- cali_info->xtal_offset) ?
- 0 :
- 1;
- }
- }
-
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n",
- p);
-
- if (cali_info->delta_power_index[p] ==
- cali_info->delta_power_index_last[p]) {
- /* If Thermal value changes but lookup table
- * value still the same
- */
- cali_info->power_index_offset[p] = 0;
- } else {
- /*Power idx diff between 2 times Pwr Tracking*/
- cali_info->power_index_offset[p] =
- cali_info->delta_power_index[p] -
- cali_info->delta_power_index_last[p];
- }
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n",
- p, cali_info->power_index_offset[p],
- cali_info->delta_power_index[p],
- cali_info->delta_power_index_last[p]);
-
- cali_info->OFDM_index[p] =
- cali_info->bb_swing_idx_ofdm_base[p] +
- cali_info->power_index_offset[p];
- cali_info->CCK_index =
- cali_info->bb_swing_idx_cck_base +
- cali_info->power_index_offset[p];
-
- cali_info->bb_swing_idx_cck = cali_info->CCK_index;
- cali_info->bb_swing_idx_ofdm[p] =
- cali_info->OFDM_index[p];
-
- /*******Print BB Swing base and index Offset**********/
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n",
- cali_info->bb_swing_idx_cck,
- cali_info->bb_swing_idx_cck_base,
- cali_info->power_index_offset[p]);
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n",
- cali_info->bb_swing_idx_ofdm[p], p,
- cali_info->bb_swing_idx_ofdm_base[p],
- cali_info->power_index_offset[p]);
-
- /*4 7.1 Handle boundary conditions of index.*/
-
- if (cali_info->OFDM_index[p] >
- c.swing_table_size_ofdm - 1)
- cali_info->OFDM_index[p] =
- c.swing_table_size_ofdm - 1;
- else if (cali_info->OFDM_index[p] <= OFDM_min_index)
- cali_info->OFDM_index[p] = OFDM_min_index;
- }
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "\n\n========================================================================================================\n");
-
- if (cali_info->CCK_index > c.swing_table_size_cck - 1)
- cali_info->CCK_index = c.swing_table_size_cck - 1;
- else if (cali_info->CCK_index <= 0)
- cali_info->CCK_index = 0;
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
- cali_info->txpowertrack_control, thermal_value,
- cali_info->thermal_value);
-
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
- cali_info->power_index_offset[p] = 0;
- }
-
- /*Print Swing base & current*/
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
- cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);
-
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
- cali_info->OFDM_index[p], p,
- cali_info->bb_swing_idx_ofdm_base[p]);
-
- if ((dm->support_ic_type & ODM_RTL8814A)) {
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "power_tracking_type=%d\n", power_tracking_type);
-
- if (power_tracking_type == 0) {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "**********Enter POWER Tracking MIX_MODE**********\n");
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
- (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
- 0);
- } else if (power_tracking_type == 1) {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
- (*c.odm_tx_pwr_track_set_pwr)(
- dm, MIX_2G_TSSI_5G_MODE, p, 0);
- } else if (power_tracking_type == 2) {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
- (*c.odm_tx_pwr_track_set_pwr)(
- dm, MIX_5G_TSSI_2G_MODE, p, 0);
- } else if (power_tracking_type == 3) {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "**********Enter POWER Tracking TSSI MODE**********\n");
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
- (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p,
- 0);
- }
- /*Record last Power Tracking Thermal value*/
- cali_info->thermal_value = thermal_value;
-
- } else if ((cali_info->power_index_offset[ODM_RF_PATH_A] != 0 ||
- cali_info->power_index_offset[ODM_RF_PATH_B] != 0 ||
- cali_info->power_index_offset[ODM_RF_PATH_C] != 0 ||
- cali_info->power_index_offset[ODM_RF_PATH_D] != 0) &&
- cali_info->txpowertrack_control &&
- (rtlefu->eeprom_thermalmeter != 0xff)) {
- /* 4 7.2 Configure the Swing Table to adjust Tx Power. */
-
- /*Always true after Tx Power is adjusted by power tracking.*/
- cali_info->is_tx_power_changed = true;
- /* 2012/04/23 MH According to Luke's suggestion, we can not
- * write BB digital to increase TX power. Otherwise, EVM will
- * be bad.
- */
- /* 2012/04/25 MH Add for tx power tracking to set tx power in
- * tx agc for 88E.
- */
- if (thermal_value > cali_info->thermal_value) {
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
- /* print temperature increasing */
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
- p, cali_info->power_index_offset[p],
- delta, thermal_value,
- rtlefu->eeprom_thermalmeter,
- cali_info->thermal_value);
- }
- } else if (thermal_value <
- cali_info->thermal_value) { /*Low temperature*/
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
- /* print temperature decreasing */
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
- p, cali_info->power_index_offset[p],
- delta, thermal_value,
- rtlefu->eeprom_thermalmeter,
- cali_info->thermal_value);
- }
- }
-
- if (thermal_value > rtlefu->eeprom_thermalmeter) {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "Temperature(%d) higher than PG value(%d)\n",
- thermal_value, rtlefu->eeprom_thermalmeter);
-
- phydm_odm_tx_power_set(dm, &c, indexforchannel, 0);
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "Temperature(%d) lower than PG value(%d)\n",
- thermal_value, rtlefu->eeprom_thermalmeter);
- phydm_odm_tx_power_set(dm, &c, indexforchannel, 1);
- }
-
- /*Record last time Power Tracking result as base.*/
- cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
-
- for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
- cali_info->bb_swing_idx_ofdm_base[p] =
- cali_info->bb_swing_idx_ofdm[p];
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "cali_info->thermal_value = %d thermal_value= %d\n",
- cali_info->thermal_value, thermal_value);
-
- /*Record last Power Tracking Thermal value*/
- cali_info->thermal_value = thermal_value;
- }
-
- if (dm->support_ic_type == ODM_RTL8703B ||
- dm->support_ic_type == ODM_RTL8723D ||
- dm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */
-
- if (xtal_offset_eanble != 0 &&
- cali_info->txpowertrack_control &&
- rtlefu->eeprom_thermalmeter != 0xff) {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "**********Enter Xtal Tracking**********\n");
-
- if (thermal_value > rtlefu->eeprom_thermalmeter) {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "Temperature(%d) higher than PG value(%d)\n",
- thermal_value,
- rtlefu->eeprom_thermalmeter);
- (*c.odm_txxtaltrack_set_xtal)(dm);
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "Temperature(%d) lower than PG value(%d)\n",
- thermal_value,
- rtlefu->eeprom_thermalmeter);
- (*c.odm_txxtaltrack_set_xtal)(dm);
- }
- }
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "**********End Xtal Tracking**********\n");
- }
-
- if (!IS_HARDWARE_TYPE_8723B(adapter)) {
- /* Delta temperature is equal to or larger than 20 centigrade
- * (When threshold is 8).
- */
- if (delta_IQK >= c.threshold_iqk) {
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "delta_IQK(%d) >= threshold_iqk(%d)\n",
- delta_IQK, c.threshold_iqk);
- if (!cali_info->is_iqk_in_progress)
- (*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
- }
- }
- if (cali_info->dpk_thermal[ODM_RF_PATH_A] != 0) {
- if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) {
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
- odm_set_bb_reg(
- dm, 0xcc4,
- BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10),
- (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk));
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
- } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) {
- s32 value = 0x20 +
- (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk);
-
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
- odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) |
- BIT(11) | BIT(10),
- value);
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
- } else {
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
- odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) |
- BIT(11) | BIT(10),
- 0);
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
- }
- }
- if (cali_info->dpk_thermal[ODM_RF_PATH_B] != 0) {
- if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) {
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
- odm_set_bb_reg(
- dm, 0xec4,
- BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10),
- (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk));
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
- } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) {
- s32 value = 0x20 +
- (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk);
-
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
- odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) |
- BIT(11) | BIT(10),
- value);
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
- } else {
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
- odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) |
- BIT(11) | BIT(10),
- 0);
- odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
- }
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK, "<===%s\n", __func__);
-
- cali_info->tx_powercount = 0;
-}
-
-/* 3============================================================
- * 3 IQ Calibration
- * 3============================================================
- */
-
-void odm_reset_iqk_result(void *dm_void) { return; }
-
-u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
-{
- u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
- 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
- 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
- 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136,
- 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165};
- u8 place = chnl;
-
- if (chnl > 14) {
- for (place = 14; place < sizeof(channel_all); place++) {
- if (channel_all[place] == chnl)
- return place - 13;
- }
- }
- return 0;
-}
-
-static void odm_iq_calibrate(struct phy_dm_struct *dm)
-{
- void *adapter = dm->adapter;
-
- if (IS_HARDWARE_TYPE_8812AU(adapter))
- return;
-
- if (dm->is_linked) {
- if ((*dm->channel != dm->pre_channel) &&
- (!*dm->is_scan_in_process)) {
- dm->pre_channel = *dm->channel;
- dm->linked_interval = 0;
- }
-
- if (dm->linked_interval < 3)
- dm->linked_interval++;
-
- if (dm->linked_interval == 2) {
- if (IS_HARDWARE_TYPE_8814A(adapter))
- ;
-
- else if (IS_HARDWARE_TYPE_8822B(adapter))
- phy_iq_calibrate_8822b(dm, false);
- }
- } else {
- dm->linked_interval = 0;
- }
-}
-
-void phydm_rf_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- odm_txpowertracking_init(dm);
-
- odm_clear_txpowertracking_state(dm);
-}
-
-void phydm_rf_watchdog(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- odm_txpowertracking_check(dm);
- if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- odm_iq_calibrate(dm);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __HAL_PHY_RF_H__
-#define __HAL_PHY_RF_H__
-
-#include "phydm_kfree.h"
-
-#include "rtl8822b/phydm_iqk_8822b.h"
-
-#include "phydm_powertracking_ce.h"
-
-enum spur_cal_method { PLL_RESET, AFE_PHASE_SEL };
-
-enum pwrtrack_method {
- BBSWING,
- TXAGC,
- MIX_MODE,
- TSSI_MODE,
- MIX_2G_TSSI_5G_MODE,
- MIX_5G_TSSI_2G_MODE
-};
-
-typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
-typedef void (*func_iqk)(void *, u8, u8, u8);
-typedef void (*func_lck)(void *);
-typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
-typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
-typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
-typedef void (*func_set_xtal)(void *);
-
-struct txpwrtrack_cfg {
- u8 swing_table_size_cck;
- u8 swing_table_size_ofdm;
- u8 threshold_iqk;
- u8 threshold_dpk;
- u8 average_thermal_num;
- u8 rf_path_count;
- u32 thermal_reg_addr;
- func_set_pwr odm_tx_pwr_track_set_pwr;
- func_iqk do_iqk;
- func_lck phy_lc_calibrate;
- func_swing get_delta_swing_table;
- func_swing8814only get_delta_swing_table8814only;
- func_swing_xtal get_delta_swing_xtal_table;
- func_set_xtal odm_txxtaltrack_set_xtal;
-};
-
-void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
-
-void odm_clear_txpowertracking_state(void *dm_void);
-
-void odm_txpowertracking_callback_thermal_meter(void *dm);
-
-#define ODM_TARGET_CHNL_NUM_2G_5G 59
-
-void odm_reset_iqk_result(void *dm_void);
-u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
-
-void phydm_rf_init(void *dm_void);
-void phydm_rf_watchdog(void *dm_void);
-
-#endif /* #ifndef __HAL_PHY_RF_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-static const u16 db_invert_table[12][8] = {
- {1, 1, 1, 2, 2, 2, 2, 3},
- {3, 3, 4, 4, 4, 5, 6, 6},
- {7, 8, 9, 10, 11, 13, 14, 16},
- {18, 20, 22, 25, 28, 32, 35, 40},
- {45, 50, 56, 63, 71, 79, 89, 100},
- {112, 126, 141, 158, 178, 200, 224, 251},
- {282, 316, 355, 398, 447, 501, 562, 631},
- {708, 794, 891, 1000, 1122, 1259, 1413, 1585},
- {1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
- {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000},
- {11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119},
- {28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535},
-};
-
-/* ************************************************************
- * Local Function predefine.
- * *************************************************************/
-
-/* START------------COMMON INFO RELATED--------------- */
-
-static void odm_update_power_training_state(struct phy_dm_struct *dm);
-
-/* ************************************************************
- * 3 Export Interface
- * *************************************************************/
-
-/*Y = 10*log(X)*/
-s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)
-{
- s32 integer = 0, decimal = 0;
- u32 i;
-
- if (X == 0)
- X = 1; /* log2(x), x can't be 0 */
-
- for (i = (total_bit - 1); i > 0; i--) {
- if (X & BIT(i)) {
- integer = i;
- if (i > 0) {
- /* decimal is 0.5dB*3=1.5dB~=2dB */
- decimal = (X & BIT(i - 1)) ? 2 : 0;
- }
- break;
- }
- }
-
- return 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */;
-}
-
-s32 odm_sign_conversion(s32 value, u32 total_bit)
-{
- if (value & BIT(total_bit - 1))
- value -= BIT(total_bit);
- return value;
-}
-
-void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
- u8 seq_length)
-{
- u8 i = 0, j = 0;
- u32 tmp_a, tmp_b;
- u32 tmp_idx_a, tmp_idx_b;
-
- for (i = 0; i < seq_length; i++) {
- rank_idx[i] = i;
- /**/
- }
-
- for (i = 0; i < (seq_length - 1); i++) {
- for (j = 0; j < (seq_length - 1 - i); j++) {
- tmp_a = value[j];
- tmp_b = value[j + 1];
-
- tmp_idx_a = rank_idx[j];
- tmp_idx_b = rank_idx[j + 1];
-
- if (tmp_a < tmp_b) {
- value[j] = tmp_b;
- value[j + 1] = tmp_a;
-
- rank_idx[j] = tmp_idx_b;
- rank_idx[j + 1] = tmp_idx_a;
- }
- }
- }
-
- for (i = 0; i < seq_length; i++) {
- idx_out[rank_idx[i]] = i + 1;
- /**/
- }
-}
-
-void odm_init_mp_driver_status(struct phy_dm_struct *dm)
-{
- dm->mp_mode = false;
-}
-
-static void odm_update_mp_driver_status(struct phy_dm_struct *dm)
-{
- /* Do nothing. */
-}
-
-static void phydm_init_trx_antenna_setting(struct phy_dm_struct *dm)
-{
- /*#if (RTL8814A_SUPPORT == 1)*/
-
- if (dm->support_ic_type & (ODM_RTL8814A)) {
- u8 rx_ant = 0, tx_ant = 0;
-
- rx_ant = (u8)odm_get_bb_reg(dm, ODM_REG(BB_RX_PATH, dm),
- ODM_BIT(BB_RX_PATH, dm));
- tx_ant = (u8)odm_get_bb_reg(dm, ODM_REG(BB_TX_PATH, dm),
- ODM_BIT(BB_TX_PATH, dm));
- dm->tx_ant_status = (tx_ant & 0xf);
- dm->rx_ant_status = (rx_ant & 0xf);
- } else if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C |
- ODM_RTL8710B)) { /* JJ ADD 20161014 */
- dm->tx_ant_status = 0x1;
- dm->rx_ant_status = 0x1;
- }
- /*#endif*/
-}
-
-static void phydm_traffic_load_decision(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- /*---TP & Traffic-load calculation---*/
-
- if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
- dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
-
- if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
- dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
-
- dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
- dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
- dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
- dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
-
- dm->tx_tp = ((dm->tx_tp) >> 1) +
- (u32)(((dm->cur_tx_ok_cnt) >> 18) >>
- 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
- dm->rx_tp = ((dm->rx_tp) >> 1) +
- (u32)(((dm->cur_rx_ok_cnt) >> 18) >>
- 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
- dm->total_tp = dm->tx_tp + dm->rx_tp;
-
- dm->pre_traffic_load = dm->traffic_load;
-
- if (dm->cur_tx_ok_cnt > 1875000 ||
- dm->cur_rx_ok_cnt >
- 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
-
- dm->traffic_load = TRAFFIC_HIGH;
- /**/
- } else if (
- dm->cur_tx_ok_cnt > 500000 ||
- dm->cur_rx_ok_cnt >
- 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
-
- dm->traffic_load = TRAFFIC_MID;
- /**/
- } else if (
- dm->cur_tx_ok_cnt > 100000 ||
- dm->cur_rx_ok_cnt >
- 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
-
- dm->traffic_load = TRAFFIC_LOW;
- /**/
- } else {
- dm->traffic_load = TRAFFIC_ULTRA_LOW;
- /**/
- }
-}
-
-static void phydm_config_ofdm_tx_path(struct phy_dm_struct *dm, u32 path) {}
-
-void phydm_config_ofdm_rx_path(struct phy_dm_struct *dm, u32 path)
-{
- u8 ofdm_rx_path = 0;
-
- if (dm->support_ic_type & (ODM_RTL8192E)) {
- } else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
- if (path == PHYDM_A) {
- ofdm_rx_path = 1;
- /**/
- } else if (path == PHYDM_B) {
- ofdm_rx_path = 2;
- /**/
- } else if (path == PHYDM_AB) {
- ofdm_rx_path = 3;
- /**/
- }
-
- odm_set_bb_reg(dm, 0x808, MASKBYTE0,
- ((ofdm_rx_path << 4) | ofdm_rx_path));
- }
-}
-
-static void phydm_config_cck_rx_antenna_init(struct phy_dm_struct *dm) {}
-
-static void phydm_config_cck_rx_path(struct phy_dm_struct *dm, u8 path,
- u8 path_div_en)
-{
-}
-
-void phydm_config_trx_path(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- /* CCK */
- if (dm_value[0] == 0) {
- if (dm_value[1] == 1) { /*TX*/
- if (dm_value[2] == 1)
- odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8);
- else if (dm_value[2] == 2)
- odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4);
- else if (dm_value[2] == 3)
- odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc);
- } else if (dm_value[1] == 2) { /*RX*/
-
- phydm_config_cck_rx_antenna_init(dm);
-
- if (dm_value[2] == 1)
- phydm_config_cck_rx_path(dm, PHYDM_A,
- CCA_PATHDIV_DISABLE);
- else if (dm_value[2] == 2)
- phydm_config_cck_rx_path(dm, PHYDM_B,
- CCA_PATHDIV_DISABLE);
- else if (dm_value[2] == 3 &&
- dm_value[3] == 1) /*enable path diversity*/
- phydm_config_cck_rx_path(dm, PHYDM_AB,
- CCA_PATHDIV_ENABLE);
- else if (dm_value[2] == 3 && dm_value[3] != 1)
- phydm_config_cck_rx_path(dm, PHYDM_B,
- CCA_PATHDIV_DISABLE);
- }
- }
- /* OFDM */
- else if (dm_value[0] == 1) {
- if (dm_value[1] == 1) { /*TX*/
- phydm_config_ofdm_tx_path(dm, dm_value[2]);
- /**/
- } else if (dm_value[1] == 2) { /*RX*/
- phydm_config_ofdm_rx_path(dm, dm_value[2]);
- /**/
- }
- }
-
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
- (dm_value[0] == 1) ? "OFDM" : "CCK",
- (dm_value[1] == 1) ? "TX" : "RX",
- (dm_value[2] & 0x1) ? "A" : "", (dm_value[2] & 0x2) ? "B" : "",
- (dm_value[2] & 0x4) ? "C" : "", (dm_value[2] & 0x8) ? "D" : "");
-}
-
-static void phydm_init_cck_setting(struct phy_dm_struct *dm)
-{
- dm->is_cck_high_power = (bool)odm_get_bb_reg(
- dm, ODM_REG(CCK_RPT_FORMAT, dm), ODM_BIT(CCK_RPT_FORMAT, dm));
-
- /* JJ ADD 20161014 */
- /* JJ ADD 20161014 */
- if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F |
- ODM_RTL8821C | ODM_RTL8710B))
- dm->cck_new_agc = odm_get_bb_reg(dm, 0xa9c, BIT(17)) ?
- true :
- false; /*1: new agc 0: old agc*/
- else
- dm->cck_new_agc = false;
-}
-
-static void phydm_init_soft_ml_setting(struct phy_dm_struct *dm)
-{
- if (!dm->mp_mode) {
- if (dm->support_ic_type & ODM_RTL8822B)
- odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0xc10a0000);
- }
-}
-
-static void phydm_init_hw_info_by_rfe(struct phy_dm_struct *dm)
-{
- if (dm->support_ic_type & ODM_RTL8822B)
- phydm_init_hw_info_by_rfe_type_8822b(dm);
-}
-
-static void odm_common_info_self_init(struct phy_dm_struct *dm)
-{
- phydm_init_cck_setting(dm);
- dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, ODM_REG(BB_RX_PATH, dm),
- ODM_BIT(BB_RX_PATH, dm));
- odm_init_mp_driver_status(dm);
- phydm_init_trx_antenna_setting(dm);
- phydm_init_soft_ml_setting(dm);
-
- dm->phydm_period = PHYDM_WATCH_DOG_PERIOD;
- dm->phydm_sys_up_time = 0;
-
- if (dm->support_ic_type & ODM_IC_1SS)
- dm->num_rf_path = 1;
- else if (dm->support_ic_type & ODM_IC_2SS)
- dm->num_rf_path = 2;
- else if (dm->support_ic_type & ODM_IC_3SS)
- dm->num_rf_path = 3;
- else if (dm->support_ic_type & ODM_IC_4SS)
- dm->num_rf_path = 4;
-
- dm->tx_rate = 0xFF;
-
- dm->number_linked_client = 0;
- dm->pre_number_linked_client = 0;
- dm->number_active_client = 0;
- dm->pre_number_active_client = 0;
-
- dm->last_tx_ok_cnt = 0;
- dm->last_rx_ok_cnt = 0;
- dm->tx_tp = 0;
- dm->rx_tp = 0;
- dm->total_tp = 0;
- dm->traffic_load = TRAFFIC_LOW;
-
- dm->nbi_set_result = 0;
- dm->is_init_hw_info_by_rfe = false;
- dm->pre_dbg_priority = BB_DBGPORT_RELEASE;
-}
-
-static void odm_common_info_self_update(struct phy_dm_struct *dm)
-{
- u8 entry_cnt = 0, num_active_client = 0;
- u32 i, one_entry_macid = 0;
- struct rtl_sta_info *entry;
-
- /* THis variable cannot be used because it is wrong*/
- if (*dm->band_width == ODM_BW40M) {
- if (*dm->sec_ch_offset == 1)
- dm->control_channel = *dm->channel - 2;
- else if (*dm->sec_ch_offset == 2)
- dm->control_channel = *dm->channel + 2;
- } else {
- dm->control_channel = *dm->channel;
- }
-
- for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
- entry = dm->odm_sta_info[i];
- if (IS_STA_VALID(entry)) {
- entry_cnt++;
- if (entry_cnt == 1)
- one_entry_macid = i;
- }
- }
-
- if (entry_cnt == 1) {
- dm->is_one_entry_only = true;
- dm->one_entry_macid = one_entry_macid;
- } else {
- dm->is_one_entry_only = false;
- }
-
- dm->pre_number_linked_client = dm->number_linked_client;
- dm->pre_number_active_client = dm->number_active_client;
-
- dm->number_linked_client = entry_cnt;
- dm->number_active_client = num_active_client;
-
- /* Update MP driver status*/
- odm_update_mp_driver_status(dm);
-
- /*Traffic load information update*/
- phydm_traffic_load_decision(dm);
-
- dm->phydm_sys_up_time += dm->phydm_period;
-}
-
-static void odm_common_info_self_reset(struct phy_dm_struct *dm)
-{
- dm->phy_dbg_info.num_qry_beacon_pkt = 0;
-}
-
-void *phydm_get_structure(struct phy_dm_struct *dm, u8 structure_type)
-
-{
- void *p_struct = NULL;
-
- switch (structure_type) {
- case PHYDM_FALSEALMCNT:
- p_struct = &dm->false_alm_cnt;
- break;
-
- case PHYDM_CFOTRACK:
- p_struct = &dm->dm_cfo_track;
- break;
-
- case PHYDM_ADAPTIVITY:
- p_struct = &dm->adaptivity;
- break;
-
- default:
- break;
- }
-
- return p_struct;
-}
-
-static void odm_hw_setting(struct phy_dm_struct *dm)
-{
- if (dm->support_ic_type & ODM_RTL8822B)
- phydm_hwsetting_8822b(dm);
-}
-
-static void phydm_supportability_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 support_ability = 0;
-
- if (dm->support_ic_type != ODM_RTL8821C)
- return;
-
- switch (dm->support_ic_type) {
- /*---------------AC Series-------------------*/
-
- case ODM_RTL8822B:
- support_ability |= ODM_BB_DIG | ODM_BB_FA_CNT | ODM_BB_CCK_PD |
- ODM_BB_CFO_TRACKING | ODM_BB_RATE_ADAPTIVE |
- ODM_BB_RSSI_MONITOR | ODM_BB_RA_MASK |
- ODM_RF_TX_PWR_TRACK;
- break;
-
- default:
- support_ability |= ODM_BB_DIG | ODM_BB_FA_CNT | ODM_BB_CCK_PD |
- ODM_BB_CFO_TRACKING | ODM_BB_RATE_ADAPTIVE |
- ODM_BB_RSSI_MONITOR | ODM_BB_RA_MASK |
- ODM_RF_TX_PWR_TRACK;
-
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "[Warning] Supportability Init Warning !!!\n");
- break;
- }
-
- if (*dm->enable_antdiv)
- support_ability |= ODM_BB_ANT_DIV;
-
- if (*dm->enable_adaptivity) {
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "ODM adaptivity is set to Enabled!!!\n");
-
- support_ability |= ODM_BB_ADAPTIVITY;
-
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "ODM adaptivity is set to disabled!!!\n");
- /**/
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "PHYDM support_ability = ((0x%x))\n",
- support_ability);
- odm_cmn_info_init(dm, ODM_CMNINFO_ABILITY, support_ability);
-}
-
-/*
- * 2011/09/21 MH Add to describe different team necessary resource allocate??
- */
-void odm_dm_init(struct phy_dm_struct *dm)
-{
- phydm_supportability_init(dm);
- odm_common_info_self_init(dm);
- odm_dig_init(dm);
- phydm_nhm_counter_statistics_init(dm);
- phydm_adaptivity_init(dm);
- phydm_ra_info_init(dm);
- odm_rate_adaptive_mask_init(dm);
- odm_cfo_tracking_init(dm);
- odm_edca_turbo_init(dm);
- odm_rssi_monitor_init(dm);
- phydm_rf_init(dm);
- odm_txpowertracking_init(dm);
-
- if (dm->support_ic_type & ODM_RTL8822B)
- phydm_txcurrentcalibration(dm);
-
- odm_antenna_diversity_init(dm);
- odm_auto_channel_select_init(dm);
- odm_dynamic_tx_power_init(dm);
- phydm_init_ra_info(dm);
- adc_smp_init(dm);
-
- phydm_beamforming_init(dm);
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- /* 11n series */
- odm_dynamic_bb_power_saving_init(dm);
- }
-
- phydm_psd_init(dm);
-}
-
-void odm_dm_reset(struct phy_dm_struct *dm)
-{
- struct dig_thres *dig_tab = &dm->dm_dig_table;
-
- odm_ant_div_reset(dm);
- phydm_set_edcca_threshold_api(dm, dig_tab->cur_ig_value);
-}
-
-void phydm_support_ability_debug(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 pre_support_ability;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- pre_support_ability = dm->support_ability;
- PHYDM_SNPRINTF(output + used, out_len - used, "\n%s\n",
- "================================");
- if (dm_value[0] == 100) {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "[Supportability] PhyDM Selection\n");
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "================================");
- PHYDM_SNPRINTF(
- output + used, out_len - used, "00. (( %s ))DIG\n",
- ((dm->support_ability & ODM_BB_DIG) ? ("V") : (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "01. (( %s ))RA_MASK\n",
- ((dm->support_ability & ODM_BB_RA_MASK) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "02. (( %s ))DYNAMIC_TXPWR\n",
- ((dm->support_ability & ODM_BB_DYNAMIC_TXPWR) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "03. (( %s ))FA_CNT\n",
- ((dm->support_ability & ODM_BB_FA_CNT) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "04. (( %s ))RSSI_MONITOR\n",
- ((dm->support_ability & ODM_BB_RSSI_MONITOR) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "05. (( %s ))CCK_PD\n",
- ((dm->support_ability & ODM_BB_CCK_PD) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "06. (( %s ))ANT_DIV\n",
- ((dm->support_ability & ODM_BB_ANT_DIV) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "08. (( %s ))PWR_TRAIN\n",
- ((dm->support_ability & ODM_BB_PWR_TRAIN) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "09. (( %s ))RATE_ADAPTIVE\n",
- ((dm->support_ability & ODM_BB_RATE_ADAPTIVE) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "10. (( %s ))PATH_DIV\n",
- ((dm->support_ability & ODM_BB_PATH_DIV) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "13. (( %s ))ADAPTIVITY\n",
- ((dm->support_ability & ODM_BB_ADAPTIVITY) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "14. (( %s ))struct cfo_tracking\n",
- ((dm->support_ability & ODM_BB_CFO_TRACKING) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "15. (( %s ))NHM_CNT\n",
- ((dm->support_ability & ODM_BB_NHM_CNT) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "16. (( %s ))PRIMARY_CCA\n",
- ((dm->support_ability & ODM_BB_PRIMARY_CCA) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "17. (( %s ))TXBF\n",
- ((dm->support_ability & ODM_BB_TXBF) ? ("V") : (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "18. (( %s ))DYNAMIC_ARFR\n",
- ((dm->support_ability & ODM_BB_DYNAMIC_ARFR) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "20. (( %s ))EDCA_TURBO\n",
- ((dm->support_ability & ODM_MAC_EDCA_TURBO) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "21. (( %s ))DYNAMIC_RX_PATH\n",
- ((dm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "24. (( %s ))TX_PWR_TRACK\n",
- ((dm->support_ability & ODM_RF_TX_PWR_TRACK) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "25. (( %s ))RX_GAIN_TRACK\n",
- ((dm->support_ability & ODM_RF_RX_GAIN_TRACK) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "26. (( %s ))RF_CALIBRATION\n",
- ((dm->support_ability & ODM_RF_CALIBRATION) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "================================");
- } else {
- if (dm_value[1] == 1) { /* enable */
- dm->support_ability |= BIT(dm_value[0]);
- } else if (dm_value[1] == 2) /* disable */
- dm->support_ability &= ~(BIT(dm_value[0]));
- else {
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "[Warning!!!] 1:enable, 2:disable");
- }
- }
- PHYDM_SNPRINTF(output + used, out_len - used,
- "pre-support_ability = 0x%x\n", pre_support_ability);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Curr-support_ability = 0x%x\n", dm->support_ability);
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "================================");
-}
-
-void phydm_watchdog_mp(struct phy_dm_struct *dm) {}
-/*
- * 2011/09/20 MH This is the entry pointer for all team to execute HW outsrc DM.
- * You can not add any dummy function here, be care, you can only use DM struct
- * to perform any new ODM_DM.
- */
-void odm_dm_watchdog(struct phy_dm_struct *dm)
-{
- odm_common_info_self_update(dm);
- phydm_basic_dbg_message(dm);
- odm_hw_setting(dm);
-
- odm_false_alarm_counter_statistics(dm);
- phydm_noisy_detection(dm);
-
- odm_rssi_monitor_check(dm);
-
- if (*dm->is_power_saving) {
- odm_dig_by_rssi_lps(dm);
- phydm_adaptivity(dm);
- odm_antenna_diversity(
- dm); /*enable AntDiv in PS mode, request from SD4 Jeff*/
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "DMWatchdog in power saving mode\n");
- return;
- }
-
- phydm_check_adaptivity(dm);
- odm_update_power_training_state(dm);
- odm_DIG(dm);
- phydm_adaptivity(dm);
- odm_cck_packet_detection_thresh(dm);
-
- phydm_ra_info_watchdog(dm);
- odm_edca_turbo_check(dm);
- odm_cfo_tracking(dm);
- odm_dynamic_tx_power(dm);
- odm_antenna_diversity(dm);
-
- phydm_beamforming_watchdog(dm);
-
- phydm_rf_watchdog(dm);
-
- odm_dtc(dm);
-
- odm_common_info_self_reset(dm);
-}
-
-/*
- * Init /.. Fixed HW value. Only init time.
- */
-void odm_cmn_info_init(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
- u32 value)
-{
- /* This section is used for init value */
- switch (cmn_info) {
- /* Fixed ODM value. */
- case ODM_CMNINFO_ABILITY:
- dm->support_ability = (u32)value;
- break;
-
- case ODM_CMNINFO_RF_TYPE:
- dm->rf_type = (u8)value;
- break;
-
- case ODM_CMNINFO_PLATFORM:
- dm->support_platform = (u8)value;
- break;
-
- case ODM_CMNINFO_INTERFACE:
- dm->support_interface = (u8)value;
- break;
-
- case ODM_CMNINFO_MP_TEST_CHIP:
- dm->is_mp_chip = (u8)value;
- break;
-
- case ODM_CMNINFO_IC_TYPE:
- dm->support_ic_type = value;
- break;
-
- case ODM_CMNINFO_CUT_VER:
- dm->cut_version = (u8)value;
- break;
-
- case ODM_CMNINFO_FAB_VER:
- dm->fab_version = (u8)value;
- break;
-
- case ODM_CMNINFO_RFE_TYPE:
- dm->rfe_type = (u8)value;
- phydm_init_hw_info_by_rfe(dm);
- break;
-
- case ODM_CMNINFO_RF_ANTENNA_TYPE:
- dm->ant_div_type = (u8)value;
- break;
-
- case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
- dm->with_extenal_ant_switch = (u8)value;
- break;
-
- case ODM_CMNINFO_BE_FIX_TX_ANT:
- dm->dm_fat_table.b_fix_tx_ant = (u8)value;
- break;
-
- case ODM_CMNINFO_BOARD_TYPE:
- if (!dm->is_init_hw_info_by_rfe)
- dm->board_type = (u8)value;
- break;
-
- case ODM_CMNINFO_PACKAGE_TYPE:
- if (!dm->is_init_hw_info_by_rfe)
- dm->package_type = (u8)value;
- break;
-
- case ODM_CMNINFO_EXT_LNA:
- if (!dm->is_init_hw_info_by_rfe)
- dm->ext_lna = (u8)value;
- break;
-
- case ODM_CMNINFO_5G_EXT_LNA:
- if (!dm->is_init_hw_info_by_rfe)
- dm->ext_lna_5g = (u8)value;
- break;
-
- case ODM_CMNINFO_EXT_PA:
- if (!dm->is_init_hw_info_by_rfe)
- dm->ext_pa = (u8)value;
- break;
-
- case ODM_CMNINFO_5G_EXT_PA:
- if (!dm->is_init_hw_info_by_rfe)
- dm->ext_pa_5g = (u8)value;
- break;
-
- case ODM_CMNINFO_GPA:
- if (!dm->is_init_hw_info_by_rfe)
- dm->type_gpa = (u16)value;
- break;
-
- case ODM_CMNINFO_APA:
- if (!dm->is_init_hw_info_by_rfe)
- dm->type_apa = (u16)value;
- break;
-
- case ODM_CMNINFO_GLNA:
- if (!dm->is_init_hw_info_by_rfe)
- dm->type_glna = (u16)value;
- break;
-
- case ODM_CMNINFO_ALNA:
- if (!dm->is_init_hw_info_by_rfe)
- dm->type_alna = (u16)value;
- break;
-
- case ODM_CMNINFO_EXT_TRSW:
- if (!dm->is_init_hw_info_by_rfe)
- dm->ext_trsw = (u8)value;
- break;
- case ODM_CMNINFO_EXT_LNA_GAIN:
- dm->ext_lna_gain = (u8)value;
- break;
- case ODM_CMNINFO_PATCH_ID:
- dm->patch_id = (u8)value;
- break;
- case ODM_CMNINFO_BINHCT_TEST:
- dm->is_in_hct_test = (bool)value;
- break;
- case ODM_CMNINFO_BWIFI_TEST:
- dm->wifi_test = (u8)value;
- break;
- case ODM_CMNINFO_SMART_CONCURRENT:
- dm->is_dual_mac_smart_concurrent = (bool)value;
- break;
- case ODM_CMNINFO_DOMAIN_CODE_2G:
- dm->odm_regulation_2_4g = (u8)value;
- break;
- case ODM_CMNINFO_DOMAIN_CODE_5G:
- dm->odm_regulation_5g = (u8)value;
- break;
- case ODM_CMNINFO_CONFIG_BB_RF:
- dm->config_bbrf = (bool)value;
- break;
- case ODM_CMNINFO_IQKFWOFFLOAD:
- dm->iqk_fw_offload = (u8)value;
- break;
- case ODM_CMNINFO_IQKPAOFF:
- dm->rf_calibrate_info.is_iqk_pa_off = (bool)value;
- break;
- case ODM_CMNINFO_REGRFKFREEENABLE:
- dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
- break;
- case ODM_CMNINFO_RFKFREEENABLE:
- dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
- break;
- case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
- dm->normal_rx_path = (u8)value;
- break;
- case ODM_CMNINFO_EFUSE0X3D8:
- dm->efuse0x3d8 = (u8)value;
- break;
- case ODM_CMNINFO_EFUSE0X3D7:
- dm->efuse0x3d7 = (u8)value;
- break;
- /* To remove the compiler warning, must add an empty default statement
- * to handle the other values.
- */
- default:
- /* do nothing */
- break;
- }
-}
-
-void odm_cmn_info_hook(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
- void *value)
-{
- /* */
- /* Hook call by reference pointer. */
- /* */
- switch (cmn_info) {
- /* */
- /* Dynamic call by reference pointer. */
- /* */
- case ODM_CMNINFO_MAC_PHY_MODE:
- dm->mac_phy_mode = (u8 *)value;
- break;
-
- case ODM_CMNINFO_TX_UNI:
- dm->num_tx_bytes_unicast = (u64 *)value;
- break;
-
- case ODM_CMNINFO_RX_UNI:
- dm->num_rx_bytes_unicast = (u64 *)value;
- break;
-
- case ODM_CMNINFO_WM_MODE:
- dm->wireless_mode = (u8 *)value;
- break;
-
- case ODM_CMNINFO_BAND:
- dm->band_type = (u8 *)value;
- break;
-
- case ODM_CMNINFO_SEC_CHNL_OFFSET:
- dm->sec_ch_offset = (u8 *)value;
- break;
-
- case ODM_CMNINFO_SEC_MODE:
- dm->security = (u8 *)value;
- break;
-
- case ODM_CMNINFO_BW:
- dm->band_width = (u8 *)value;
- break;
-
- case ODM_CMNINFO_CHNL:
- dm->channel = (u8 *)value;
- break;
-
- case ODM_CMNINFO_DMSP_GET_VALUE:
- dm->is_get_value_from_other_mac = (bool *)value;
- break;
-
- case ODM_CMNINFO_BUDDY_ADAPTOR:
- dm->buddy_adapter = (void **)value;
- break;
-
- case ODM_CMNINFO_DMSP_IS_MASTER:
- dm->is_master_of_dmsp = (bool *)value;
- break;
-
- case ODM_CMNINFO_SCAN:
- dm->is_scan_in_process = (bool *)value;
- break;
-
- case ODM_CMNINFO_POWER_SAVING:
- dm->is_power_saving = (bool *)value;
- break;
-
- case ODM_CMNINFO_ONE_PATH_CCA:
- dm->one_path_cca = (u8 *)value;
- break;
-
- case ODM_CMNINFO_DRV_STOP:
- dm->is_driver_stopped = (bool *)value;
- break;
-
- case ODM_CMNINFO_PNP_IN:
- dm->is_driver_is_going_to_pnp_set_power_sleep = (bool *)value;
- break;
-
- case ODM_CMNINFO_INIT_ON:
- dm->pinit_adpt_in_progress = (bool *)value;
- break;
-
- case ODM_CMNINFO_ANT_TEST:
- dm->antenna_test = (u8 *)value;
- break;
-
- case ODM_CMNINFO_NET_CLOSED:
- dm->is_net_closed = (bool *)value;
- break;
-
- case ODM_CMNINFO_FORCED_RATE:
- dm->forced_data_rate = (u16 *)value;
- break;
- case ODM_CMNINFO_ANT_DIV:
- dm->enable_antdiv = (u8 *)value;
- break;
- case ODM_CMNINFO_ADAPTIVITY:
- dm->enable_adaptivity = (u8 *)value;
- break;
- case ODM_CMNINFO_FORCED_IGI_LB:
- dm->pu1_forced_igi_lb = (u8 *)value;
- break;
-
- case ODM_CMNINFO_P2P_LINK:
- dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
- break;
-
- case ODM_CMNINFO_IS1ANTENNA:
- dm->is_1_antenna = (bool *)value;
- break;
-
- case ODM_CMNINFO_RFDEFAULTPATH:
- dm->rf_default_path = (u8 *)value;
- break;
-
- case ODM_CMNINFO_FCS_MODE:
- dm->is_fcs_mode_enable = (bool *)value;
- break;
- /*add by YuChen for beamforming PhyDM*/
- case ODM_CMNINFO_HUBUSBMODE:
- dm->hub_usb_mode = (u8 *)value;
- break;
- case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
- dm->is_fw_dw_rsvd_page_in_progress = (bool *)value;
- break;
- case ODM_CMNINFO_TX_TP:
- dm->current_tx_tp = (u32 *)value;
- break;
- case ODM_CMNINFO_RX_TP:
- dm->current_rx_tp = (u32 *)value;
- break;
- case ODM_CMNINFO_SOUNDING_SEQ:
- dm->sounding_seq = (u8 *)value;
- break;
- case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
- dm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)value;
- break;
- case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
- dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
- break;
-
- default:
- /*do nothing*/
- break;
- }
-}
-
-void odm_cmn_info_ptr_array_hook(struct phy_dm_struct *dm,
- enum odm_cmninfo cmn_info, u16 index,
- void *value)
-{
- /*Hook call by reference pointer.*/
- switch (cmn_info) {
- /*Dynamic call by reference pointer. */
- case ODM_CMNINFO_STA_STATUS:
- dm->odm_sta_info[index] = (struct rtl_sta_info *)value;
-
- if (IS_STA_VALID(dm->odm_sta_info[index]))
- dm->platform2phydm_macid_table[index] = index;
-
- break;
- /* To remove the compiler warning, must add an empty default statement
- * to handle the other values.
- */
- default:
- /* do nothing */
- break;
- }
-}
-
-/*
- * Update band/CHannel/.. The values are dynamic but non-per-packet.
- */
-void odm_cmn_info_update(struct phy_dm_struct *dm, u32 cmn_info, u64 value)
-{
- /* This init variable may be changed in run time. */
- switch (cmn_info) {
- case ODM_CMNINFO_LINK_IN_PROGRESS:
- dm->is_link_in_process = (bool)value;
- break;
-
- case ODM_CMNINFO_ABILITY:
- dm->support_ability = (u32)value;
- break;
-
- case ODM_CMNINFO_RF_TYPE:
- dm->rf_type = (u8)value;
- break;
-
- case ODM_CMNINFO_WIFI_DIRECT:
- dm->is_wifi_direct = (bool)value;
- break;
-
- case ODM_CMNINFO_WIFI_DISPLAY:
- dm->is_wifi_display = (bool)value;
- break;
-
- case ODM_CMNINFO_LINK:
- dm->is_linked = (bool)value;
- break;
-
- case ODM_CMNINFO_CMW500LINK:
- dm->is_linkedcmw500 = (bool)value;
- break;
-
- case ODM_CMNINFO_LPSPG:
- dm->is_in_lps_pg = (bool)value;
- break;
-
- case ODM_CMNINFO_STATION_STATE:
- dm->bsta_state = (bool)value;
- break;
-
- case ODM_CMNINFO_RSSI_MIN:
- dm->rssi_min = (u8)value;
- break;
-
- case ODM_CMNINFO_DBG_COMP:
- dm->debug_components = (u32)value;
- break;
-
- case ODM_CMNINFO_DBG_LEVEL:
- dm->debug_level = (u32)value;
- break;
- case ODM_CMNINFO_RA_THRESHOLD_HIGH:
- dm->rate_adaptive.high_rssi_thresh = (u8)value;
- break;
-
- case ODM_CMNINFO_RA_THRESHOLD_LOW:
- dm->rate_adaptive.low_rssi_thresh = (u8)value;
- break;
- /* The following is for BT HS mode and BT coexist mechanism. */
- case ODM_CMNINFO_BT_ENABLED:
- dm->is_bt_enabled = (bool)value;
- break;
-
- case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
- dm->is_bt_connect_process = (bool)value;
- break;
-
- case ODM_CMNINFO_BT_HS_RSSI:
- dm->bt_hs_rssi = (u8)value;
- break;
-
- case ODM_CMNINFO_BT_OPERATION:
- dm->is_bt_hs_operation = (bool)value;
- break;
-
- case ODM_CMNINFO_BT_LIMITED_DIG:
- dm->is_bt_limited_dig = (bool)value;
- break;
-
- case ODM_CMNINFO_BT_DIG:
- dm->bt_hs_dig_val = (u8)value;
- break;
-
- case ODM_CMNINFO_BT_BUSY:
- dm->is_bt_busy = (bool)value;
- break;
-
- case ODM_CMNINFO_BT_DISABLE_EDCA:
- dm->is_bt_disable_edca_turbo = (bool)value;
- break;
-
- case ODM_CMNINFO_AP_TOTAL_NUM:
- dm->ap_total_num = (u8)value;
- break;
-
- case ODM_CMNINFO_POWER_TRAINING:
- dm->is_disable_power_training = (bool)value;
- break;
-
- default:
- /* do nothing */
- break;
- }
-}
-
-u32 phydm_cmn_info_query(struct phy_dm_struct *dm,
- enum phydm_info_query info_type)
-{
- struct false_alarm_stat *false_alm_cnt =
- (struct false_alarm_stat *)phydm_get_structure(
- dm, PHYDM_FALSEALMCNT);
-
- switch (info_type) {
- case PHYDM_INFO_FA_OFDM:
- return false_alm_cnt->cnt_ofdm_fail;
-
- case PHYDM_INFO_FA_CCK:
- return false_alm_cnt->cnt_cck_fail;
-
- case PHYDM_INFO_FA_TOTAL:
- return false_alm_cnt->cnt_all;
-
- case PHYDM_INFO_CCA_OFDM:
- return false_alm_cnt->cnt_ofdm_cca;
-
- case PHYDM_INFO_CCA_CCK:
- return false_alm_cnt->cnt_cck_cca;
-
- case PHYDM_INFO_CCA_ALL:
- return false_alm_cnt->cnt_cca_all;
-
- case PHYDM_INFO_CRC32_OK_VHT:
- return false_alm_cnt->cnt_vht_crc32_ok;
-
- case PHYDM_INFO_CRC32_OK_HT:
- return false_alm_cnt->cnt_ht_crc32_ok;
-
- case PHYDM_INFO_CRC32_OK_LEGACY:
- return false_alm_cnt->cnt_ofdm_crc32_ok;
-
- case PHYDM_INFO_CRC32_OK_CCK:
- return false_alm_cnt->cnt_cck_crc32_ok;
-
- case PHYDM_INFO_CRC32_ERROR_VHT:
- return false_alm_cnt->cnt_vht_crc32_error;
-
- case PHYDM_INFO_CRC32_ERROR_HT:
- return false_alm_cnt->cnt_ht_crc32_error;
-
- case PHYDM_INFO_CRC32_ERROR_LEGACY:
- return false_alm_cnt->cnt_ofdm_crc32_error;
-
- case PHYDM_INFO_CRC32_ERROR_CCK:
- return false_alm_cnt->cnt_cck_crc32_error;
-
- case PHYDM_INFO_EDCCA_FLAG:
- return false_alm_cnt->edcca_flag;
-
- case PHYDM_INFO_OFDM_ENABLE:
- return false_alm_cnt->ofdm_block_enable;
-
- case PHYDM_INFO_CCK_ENABLE:
- return false_alm_cnt->cck_block_enable;
-
- case PHYDM_INFO_DBG_PORT_0:
- return false_alm_cnt->dbg_port0;
-
- default:
- return 0xffffffff;
- }
-}
-
-void odm_init_all_timers(struct phy_dm_struct *dm) {}
-
-void odm_cancel_all_timers(struct phy_dm_struct *dm) {}
-
-void odm_release_all_timers(struct phy_dm_struct *dm) {}
-
-/* 3============================================================
- * 3 Tx Power Tracking
- * 3============================================================
- */
-
-/* need to ODM CE Platform
- * move to here for ANT detection mechanism using
- */
-
-u32 odm_convert_to_db(u32 value)
-{
- u8 i;
- u8 j;
-
- value = value & 0xFFFF;
-
- for (i = 0; i < 12; i++) {
- if (value <= db_invert_table[i][7])
- break;
- }
-
- if (i >= 12)
- return 96; /* maximum 96 dB */
-
- for (j = 0; j < 8; j++) {
- if (value <= db_invert_table[i][j])
- break;
- }
-
- return (i << 3) + j + 1;
-}
-
-u32 odm_convert_to_linear(u32 value)
-{
- u8 i;
- u8 j;
-
- /* 1dB~96dB */
-
- value = value & 0xFF;
-
- i = (u8)((value - 1) >> 3);
- j = (u8)(value - 1) - (i << 3);
-
- return db_invert_table[i][j];
-}
-
-/*
- * ODM multi-port consideration, added by Roger, 2013.10.01.
- */
-void odm_asoc_entry_init(struct phy_dm_struct *dm) {}
-
-/* Justin: According to the current RRSI to adjust Response Frame TX power */
-void odm_dtc(struct phy_dm_struct *dm) {}
-
-static void odm_update_power_training_state(struct phy_dm_struct *dm)
-{
- struct false_alarm_stat *false_alm_cnt =
- (struct false_alarm_stat *)phydm_get_structure(
- dm, PHYDM_FALSEALMCNT);
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- u32 score = 0;
-
- if (!(dm->support_ability & ODM_BB_PWR_TRAIN))
- return;
-
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "%s()============>\n", __func__);
- dm->is_change_state = false;
-
- /* Debug command */
- if (dm->force_power_training_state) {
- if (dm->force_power_training_state == 1 &&
- !dm->is_disable_power_training) {
- dm->is_change_state = true;
- dm->is_disable_power_training = true;
- } else if (dm->force_power_training_state == 2 &&
- dm->is_disable_power_training) {
- dm->is_change_state = true;
- dm->is_disable_power_training = false;
- }
-
- dm->PT_score = 0;
- dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
- dm->phy_dbg_info.num_qry_phy_status_cck = 0;
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "%s(): force_power_training_state = %d\n",
- __func__, dm->force_power_training_state);
- return;
- }
-
- if (!dm->is_linked)
- return;
-
- /* First connect */
- if (dm->is_linked && !dig_tab->is_media_connect_0) {
- dm->PT_score = 0;
- dm->is_change_state = true;
- dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
- dm->phy_dbg_info.num_qry_phy_status_cck = 0;
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "%s(): First Connect\n",
- __func__);
- return;
- }
-
- /* Compute score */
- if (dm->nhm_cnt_0 >= 215) {
- score = 2;
- } else if (dm->nhm_cnt_0 >= 190) {
- score = 1; /* unknown state */
- } else {
- u32 rx_pkt_cnt;
-
- rx_pkt_cnt = (u32)(dm->phy_dbg_info.num_qry_phy_status_ofdm) +
- (u32)(dm->phy_dbg_info.num_qry_phy_status_cck);
-
- if ((false_alm_cnt->cnt_cca_all > 31 && rx_pkt_cnt > 31) &&
- false_alm_cnt->cnt_cca_all >= rx_pkt_cnt) {
- if ((rx_pkt_cnt + (rx_pkt_cnt >> 1)) <=
- false_alm_cnt->cnt_cca_all)
- score = 0;
- else if ((rx_pkt_cnt + (rx_pkt_cnt >> 2)) <=
- false_alm_cnt->cnt_cca_all)
- score = 1;
- else
- score = 2;
- }
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "%s(): rx_pkt_cnt = %d, cnt_cca_all = %d\n",
- __func__, rx_pkt_cnt, false_alm_cnt->cnt_cca_all);
- }
- ODM_RT_TRACE(
- dm, ODM_COMP_RA_MASK,
- "%s(): num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n",
- __func__, (u32)(dm->phy_dbg_info.num_qry_phy_status_ofdm),
- (u32)(dm->phy_dbg_info.num_qry_phy_status_cck));
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "%s(): nhm_cnt_0 = %d, score = %d\n",
- __func__, dm->nhm_cnt_0, score);
-
- /* smoothing */
- dm->PT_score = (score << 4) + (dm->PT_score >> 1) + (dm->PT_score >> 2);
- score = (dm->PT_score + 32) >> 6;
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "%s(): PT_score = %d, score after smoothing = %d\n",
- __func__, dm->PT_score, score);
-
- /* mode decision */
- if (score == 2) {
- if (dm->is_disable_power_training) {
- dm->is_change_state = true;
- dm->is_disable_power_training = false;
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "%s(): Change state\n", __func__);
- }
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "%s(): Enable Power Training\n", __func__);
- } else if (score == 0) {
- if (!dm->is_disable_power_training) {
- dm->is_change_state = true;
- dm->is_disable_power_training = true;
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "%s(): Change state\n", __func__);
- }
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "%s(): Disable Power Training\n", __func__);
- }
-
- dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
- dm->phy_dbg_info.num_qry_phy_status_cck = 0;
-}
-
-/*===========================================================*/
-/* The following is for compile only*/
-/*===========================================================*/
-/*#define TARGET_CHNL_NUM_2G_5G 59*/
-/*===========================================================*/
-
-void phydm_noisy_detection(struct phy_dm_struct *dm)
-{
- u32 total_fa_cnt, total_cca_cnt;
- u32 score = 0, i, score_smooth;
-
- total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
- total_fa_cnt = dm->false_alm_cnt.cnt_all;
-
- for (i = 0; i <= 16; i++) {
- if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
- score = 16 - i;
- break;
- }
- }
-
- /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
- dm->noisy_decision_smooth =
- (dm->noisy_decision_smooth >> 1) + (score << 2);
-
- /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
- score_smooth = (total_cca_cnt >= 300) ?
- ((dm->noisy_decision_smooth + 3) >> 3) :
- 0;
-
- dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
- ODM_RT_TRACE(
- dm, ODM_COMP_NOISY_DETECT,
- "[NoisyDetection] total_cca_cnt=%d, total_fa_cnt=%d, noisy_decision_smooth=%d, score=%d, score_smooth=%d, dm->noisy_decision=%d\n",
- total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
- score_smooth, dm->noisy_decision);
-}
-
-void phydm_set_ext_switch(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 ext_ant_switch = dm_value[0];
-
- if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
- /*Output Pin Settings*/
- odm_set_mac_reg(dm, 0x4C, BIT(23),
- 0); /*select DPDT_P and DPDT_N as output pin*/
- odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /*by WLAN control*/
-
- odm_set_bb_reg(dm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/
- odm_set_bb_reg(dm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/
-
- if (ext_ant_switch == MAIN_ANT) {
- odm_set_bb_reg(dm, 0xCB4, (BIT(29) | BIT(28)), 1);
- ODM_RT_TRACE(
- dm, ODM_COMP_API,
- "***8821A set ant switch = 2b'01 (Main)\n");
- } else if (ext_ant_switch == AUX_ANT) {
- odm_set_bb_reg(dm, 0xCB4, BIT(29) | BIT(28), 2);
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "***8821A set ant switch = 2b'10 (Aux)\n");
- }
- }
-}
-
-static void phydm_csi_mask_enable(void *dm_void, u32 enable)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 reg_value = 0;
-
- reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- odm_set_bb_reg(dm, 0xD2C, BIT(28), reg_value);
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n",
- reg_value);
-
- } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, 0x874, BIT(0), reg_value);
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n",
- reg_value);
- }
-}
-
-static void phydm_clean_all_csi_mask(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- odm_set_bb_reg(dm, 0xD40, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0xD44, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0xD48, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0xD4c, MASKDWORD, 0);
-
- } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, 0x880, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0x884, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0x888, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0x88c, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0x890, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0x894, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0x898, MASKDWORD, 0);
- odm_set_bb_reg(dm, 0x89c, MASKDWORD, 0);
- }
-}
-
-static void phydm_set_csi_mask_reg(void *dm_void, u32 tone_idx_tmp,
- u8 tone_direction)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 byte_offset, bit_offset;
- u32 target_reg;
- u8 reg_tmp_value;
- u32 tone_num = 64;
- u32 tone_num_shift = 0;
- u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
-
- /* calculate real tone idx*/
- if ((tone_idx_tmp % 10) >= 5)
- tone_idx_tmp += 10;
-
- tone_idx_tmp = (tone_idx_tmp / 10);
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- tone_num = 64;
- csi_mask_reg_p = 0xD40;
- csi_mask_reg_n = 0xD48;
-
- } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- tone_num = 128;
- csi_mask_reg_p = 0x880;
- csi_mask_reg_n = 0x890;
- }
-
- if (tone_direction == FREQ_POSITIVE) {
- if (tone_idx_tmp >= (tone_num - 1))
- tone_idx_tmp = tone_num - 1;
-
- byte_offset = (u8)(tone_idx_tmp >> 3);
- bit_offset = (u8)(tone_idx_tmp & 0x7);
- target_reg = csi_mask_reg_p + byte_offset;
-
- } else {
- tone_num_shift = tone_num;
-
- if (tone_idx_tmp >= tone_num)
- tone_idx_tmp = tone_num;
-
- tone_idx_tmp = tone_num - tone_idx_tmp;
-
- byte_offset = (u8)(tone_idx_tmp >> 3);
- bit_offset = (u8)(tone_idx_tmp & 0x7);
- target_reg = csi_mask_reg_n + byte_offset;
- }
-
- reg_tmp_value = odm_read_1byte(dm, target_reg);
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
- (tone_idx_tmp + tone_num_shift), target_reg,
- reg_tmp_value);
- reg_tmp_value |= BIT(bit_offset);
- odm_write_1byte(dm, target_reg, reg_tmp_value);
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n",
- (tone_idx_tmp + tone_num_shift), target_reg,
- reg_tmp_value);
-}
-
-static void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 nbi_table_128[NBI_TABLE_SIZE_128] = {
- 25, 55, 85, 115, 135, 155, 185, 205, 225, 245,
- /*1~10*/ /*tone_idx X 10*/
- 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/
- 485, 505, 525, 555, 585, 615, 635}; /*21~27*/
-
- u32 nbi_table_256[NBI_TABLE_SIZE_256] = {
- 25, 55, 85, 115, 135, 155, 175, 195, 225,
- 245, /*1~10*/
- 265, 285, 305, 325, 345, 365, 385, 405, 425,
- 445, /*11~20*/
- 465, 485, 505, 525, 545, 565, 585, 605, 625,
- 645, /*21~30*/
- 665, 695, 715, 735, 755, 775, 795, 815, 835,
- 855, /*31~40*/
- 875, 895, 915, 935, 955, 975, 995, 1015, 1035,
- 1055, /*41~50*/
- 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275}; /*51~59*/
-
- u32 reg_idx = 0;
- u32 i;
- u8 nbi_table_idx = FFT_128_TYPE;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- nbi_table_idx = FFT_128_TYPE;
- } else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {
- nbi_table_idx = FFT_256_TYPE;
- } else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
- if (bw == 80)
- nbi_table_idx = FFT_256_TYPE;
- else /*20M, 40M*/
- nbi_table_idx = FFT_128_TYPE;
- }
-
- if (nbi_table_idx == FFT_128_TYPE) {
- for (i = 0; i < NBI_TABLE_SIZE_128; i++) {
- if (tone_idx_tmp < nbi_table_128[i]) {
- reg_idx = i + 1;
- break;
- }
- }
-
- } else if (nbi_table_idx == FFT_256_TYPE) {
- for (i = 0; i < NBI_TABLE_SIZE_256; i++) {
- if (tone_idx_tmp < nbi_table_256[i]) {
- reg_idx = i + 1;
- break;
- }
- }
- }
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- odm_set_bb_reg(dm, 0xc40, 0x1f000000, reg_idx);
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "Set tone idx: Reg0xC40[28:24] = ((0x%x))\n",
- reg_idx);
- /**/
- } else {
- odm_set_bb_reg(dm, 0x87c, 0xfc000, reg_idx);
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n",
- reg_idx);
- /**/
- }
-}
-
-static void phydm_nbi_enable(void *dm_void, u32 enable)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 reg_value = 0;
-
- reg_value = (enable == NBI_ENABLE) ? 1 : 0;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- odm_set_bb_reg(dm, 0xc40, BIT(9), reg_value);
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value);
-
- } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, 0x87c, BIT(13), reg_value);
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value);
- }
-}
-
-static u8 phydm_calculate_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch,
- u32 *fc_in)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 fc = *fc_in;
- u32 start_ch_per_40m[NUM_START_CH_40M + 1] = {
- 36, 44, 52, 60, 100, 108, 116, 124,
- 132, 140, 149, 157, 165, 173, 173 + 8,
- };
- u32 start_ch_per_80m[NUM_START_CH_80M + 1] = {
- 36, 52, 100, 116, 132, 149, 165, 165 + 16,
- };
- u32 *start_ch = &start_ch_per_40m[0];
- u32 num_start_channel = NUM_START_CH_40M;
- u32 channel_offset = 0;
- u32 i;
-
- /*2.4G*/
- if (channel <= 14 && channel > 0) {
- if (bw == 80)
- return SET_ERROR;
-
- fc = 2412 + (channel - 1) * 5;
-
- if (bw == 40 && second_ch == PHYDM_ABOVE) {
- if (channel >= 10) {
- ODM_RT_TRACE(
- dm, ODM_COMP_API,
- "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
- channel, second_ch);
- return SET_ERROR;
- }
- fc += 10;
- } else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
- if (channel <= 2) {
- ODM_RT_TRACE(
- dm, ODM_COMP_API,
- "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
- channel, second_ch);
- return SET_ERROR;
- }
- fc -= 10;
- }
- }
- /*5G*/
- else if (channel >= 36 && channel <= 177) {
- if (bw == 20) {
- fc = 5180 + (channel - 36) * 5;
- *fc_in = fc;
- return SET_SUCCESS;
- }
-
- if (bw == 40) {
- num_start_channel = NUM_START_CH_40M;
- start_ch = &start_ch_per_40m[0];
- channel_offset = CH_OFFSET_40M;
- } else if (bw == 80) {
- num_start_channel = NUM_START_CH_80M;
- start_ch = &start_ch_per_80m[0];
- channel_offset = CH_OFFSET_80M;
- }
-
- for (i = 0; i < num_start_channel; i++) {
- if (channel < start_ch[i + 1]) {
- channel = start_ch[i] + channel_offset;
- break;
- }
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_API, "Mod_CH = ((%d))\n", channel);
-
- fc = 5180 + (channel - 36) * 5;
-
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n",
- channel);
- return SET_ERROR;
- }
-
- *fc_in = fc;
-
- return SET_SUCCESS;
-}
-
-static u8 phydm_calculate_intf_distance(void *dm_void, u32 bw, u32 fc,
- u32 f_interference,
- u32 *tone_idx_tmp_in)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 bw_up, bw_low;
- u32 int_distance;
- u32 tone_idx_tmp;
- u8 set_result = SET_NO_NEED;
-
- bw_up = fc + bw / 2;
- bw_low = fc - bw / 2;
-
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
- fc, bw_up, f_interference);
-
- if (f_interference >= bw_low && f_interference <= bw_up) {
- int_distance = (fc >= f_interference) ? (fc - f_interference) :
- (f_interference - fc);
- tone_idx_tmp =
- int_distance << 5; /* =10*(int_distance /0.3125) */
- ODM_RT_TRACE(
- dm, ODM_COMP_API,
- "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n",
- int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10));
- *tone_idx_tmp_in = tone_idx_tmp;
- set_result = SET_SUCCESS;
- }
-
- return set_result;
-}
-
-static u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
- u32 f_interference, u32 second_ch)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 fc;
- u8 tone_direction;
- u32 tone_idx_tmp;
- u8 set_result = SET_SUCCESS;
-
- if (enable == CSI_MASK_DISABLE) {
- set_result = SET_SUCCESS;
- phydm_clean_all_csi_mask(dm);
-
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_API,
- "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
- channel, bw, f_interference,
- (((bw == 20) || (channel > 14)) ?
- "Don't care" :
- (second_ch == PHYDM_ABOVE) ? "H" : "L"));
-
- /*calculate fc*/
- if (phydm_calculate_fc(dm, channel, bw, second_ch, &fc) ==
- SET_ERROR) {
- set_result = SET_ERROR;
- } else {
- /*calculate interference distance*/
- if (phydm_calculate_intf_distance(
- dm, bw, fc, f_interference,
- &tone_idx_tmp) == SET_SUCCESS) {
- tone_direction = (f_interference >= fc) ?
- FREQ_POSITIVE :
- FREQ_NEGATIVE;
- phydm_set_csi_mask_reg(dm, tone_idx_tmp,
- tone_direction);
- set_result = SET_SUCCESS;
- } else {
- set_result = SET_NO_NEED;
- }
- }
- }
-
- if (set_result == SET_SUCCESS)
- phydm_csi_mask_enable(dm, enable);
- else
- phydm_csi_mask_enable(dm, CSI_MASK_DISABLE);
-
- return set_result;
-}
-
-u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
- u32 f_interference, u32 second_ch)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 fc;
- u32 tone_idx_tmp;
- u8 set_result = SET_SUCCESS;
-
- if (enable == NBI_DISABLE) {
- set_result = SET_SUCCESS;
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_API,
- "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
- channel, bw, f_interference,
- (((second_ch == PHYDM_DONT_CARE) || (bw == 20) ||
- (channel > 14)) ?
- "Don't care" :
- (second_ch == PHYDM_ABOVE) ? "H" : "L"));
-
- /*calculate fc*/
- if (phydm_calculate_fc(dm, channel, bw, second_ch, &fc) ==
- SET_ERROR) {
- set_result = SET_ERROR;
- } else {
- /*calculate interference distance*/
- if (phydm_calculate_intf_distance(
- dm, bw, fc, f_interference,
- &tone_idx_tmp) == SET_SUCCESS) {
- phydm_set_nbi_reg(dm, tone_idx_tmp, bw);
- set_result = SET_SUCCESS;
- } else {
- set_result = SET_NO_NEED;
- }
- }
- }
-
- if (set_result == SET_SUCCESS)
- phydm_nbi_enable(dm, enable);
- else
- phydm_nbi_enable(dm, NBI_DISABLE);
-
- return set_result;
-}
-
-void phydm_api_debug(void *dm_void, u32 function_map, u32 *const dm_value,
- u32 *_used, char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 used = *_used;
- u32 out_len = *_out_len;
- u32 channel = dm_value[1];
- u32 bw = dm_value[2];
- u32 f_interference = dm_value[3];
- u32 second_ch = dm_value[4];
- u8 set_result = 0;
-
- /*PHYDM_API_NBI*/
- /*--------------------------------------------------------------------*/
- if (function_map == PHYDM_API_NBI) {
- if (dm_value[0] == 100) {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n");
- return;
-
- } else if (dm_value[0] == NBI_ENABLE) {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
- channel, bw, f_interference,
- ((second_ch == PHYDM_DONT_CARE) || (bw == 20) ||
- (channel > 14)) ?
- "Don't care" :
- ((second_ch == PHYDM_ABOVE) ? "H" :
- "L"));
- set_result =
- phydm_nbi_setting(dm, NBI_ENABLE, channel, bw,
- f_interference, second_ch);
-
- } else if (dm_value[0] == NBI_DISABLE) {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "[Disable NBI]\n");
- set_result =
- phydm_nbi_setting(dm, NBI_DISABLE, channel, bw,
- f_interference, second_ch);
-
- } else {
- set_result = SET_ERROR;
- }
-
- PHYDM_SNPRINTF(
- output + used, out_len - used, "[NBI set result: %s]\n",
- (set_result == SET_SUCCESS) ?
- "Success" :
- ((set_result == SET_NO_NEED) ? "No need" :
- "Error"));
- }
-
- /*PHYDM_CSI_MASK*/
- /*--------------------------------------------------------------------*/
- else if (function_map == PHYDM_API_CSI_MASK) {
- if (dm_value[0] == 100) {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n");
- return;
-
- } else if (dm_value[0] == CSI_MASK_ENABLE) {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
- channel, bw, f_interference,
- (channel > 14) ?
- "Don't care" :
- (((second_ch == PHYDM_DONT_CARE) ||
- (bw == 20) || (channel > 14)) ?
- "H" :
- "L"));
- set_result = phydm_csi_mask_setting(
- dm, CSI_MASK_ENABLE, channel, bw,
- f_interference, second_ch);
-
- } else if (dm_value[0] == CSI_MASK_DISABLE) {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "[Disable CSI MASK]\n");
- set_result = phydm_csi_mask_setting(
- dm, CSI_MASK_DISABLE, channel, bw,
- f_interference, second_ch);
-
- } else {
- set_result = SET_ERROR;
- }
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "[CSI MASK set result: %s]\n",
- (set_result == SET_SUCCESS) ?
- "Success" :
- ((set_result == SET_NO_NEED) ?
- "No need" :
- "Error"));
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __HALDMOUTSRC_H__
-#define __HALDMOUTSRC_H__
-
-/*============================================================*/
-/*include files*/
-/*============================================================*/
-#include "phydm_pre_define.h"
-#include "phydm_dig.h"
-#include "phydm_edcaturbocheck.h"
-#include "phydm_antdiv.h"
-#include "phydm_dynamicbbpowersaving.h"
-#include "phydm_rainfo.h"
-#include "phydm_dynamictxpower.h"
-#include "phydm_cfotracking.h"
-#include "phydm_acs.h"
-#include "phydm_adaptivity.h"
-#include "phydm_iqk.h"
-#include "phydm_dfs.h"
-#include "phydm_ccx.h"
-#include "txbf/phydm_hal_txbf_api.h"
-
-#include "phydm_adc_sampling.h"
-#include "phydm_dynamic_rx_path.h"
-#include "phydm_psd.h"
-
-#include "phydm_beamforming.h"
-
-#include "phydm_noisemonitor.h"
-#include "halphyrf_ce.h"
-
-/*============================================================*/
-/*Definition */
-/*============================================================*/
-
-/* Traffic load decision */
-#define TRAFFIC_ULTRA_LOW 1
-#define TRAFFIC_LOW 2
-#define TRAFFIC_MID 3
-#define TRAFFIC_HIGH 4
-
-#define NONE 0
-
-/*NBI API------------------------------------*/
-#define NBI_ENABLE 1
-#define NBI_DISABLE 2
-
-#define NBI_TABLE_SIZE_128 27
-#define NBI_TABLE_SIZE_256 59
-
-#define NUM_START_CH_80M 7
-#define NUM_START_CH_40M 14
-
-#define CH_OFFSET_40M 2
-#define CH_OFFSET_80M 6
-
-/*CSI MASK API------------------------------------*/
-#define CSI_MASK_ENABLE 1
-#define CSI_MASK_DISABLE 2
-
-/*------------------------------------------------*/
-
-#define FFT_128_TYPE 1
-#define FFT_256_TYPE 2
-
-#define SET_SUCCESS 1
-#define SET_ERROR 2
-#define SET_NO_NEED 3
-
-#define FREQ_POSITIVE 1
-#define FREQ_NEGATIVE 2
-
-#define PHYDM_WATCH_DOG_PERIOD 2
-
-/*============================================================*/
-/*structure and define*/
-/*============================================================*/
-
-/*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/
-/*We need to remove to other position???*/
-
-struct rtl8192cd_priv {
- u8 temp;
-};
-
-struct dyn_primary_cca {
- u8 pri_cca_flag;
- u8 intf_flag;
- u8 intf_type;
- u8 dup_rts_flag;
- u8 monitor_flag;
- u8 ch_offset;
- u8 mf_state;
-};
-
-#define dm_type_by_fw 0
-#define dm_type_by_driver 1
-
-/*Declare for common info*/
-
-#define IQK_THRESHOLD 8
-#define DPK_THRESHOLD 4
-
-struct dm_phy_status_info {
- /* */
- /* Be care, if you want to add any element please insert between */
- /* rx_pwdb_all & signal_strength. */
- /* */
- u8 rx_pwdb_all;
- u8 signal_quality; /* in 0-100 index. */
- s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */
- u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */
- u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
- s16 cfo_short[4]; /* per-path's cfo_short */
- s16 cfo_tail[4]; /* per-path's cfo_tail */
- s8 rx_power; /* in dBm Translate from PWdB */
- s8 recv_signal_power; /* Real power in dBm for this packet,
- * no beautification and aggregation.
- * Keep this raw info to be used for the other
- * procedures.
- */
- u8 bt_rx_rssi_percentage;
- u8 signal_strength; /* in 0-100 index. */
- s8 rx_pwr[4]; /* per-path's pwdb */
- s8 rx_snr[4]; /* per-path's SNR */
- /* s8 BB_Backup[13]; backup reg. */
- u8 rx_count : 2; /* RX path counter---*/
- u8 band_width : 2;
- u8 rxsc : 4; /* sub-channel---*/
- u8 bt_coex_pwr_adjust;
- u8 channel; /* channel number---*/
- bool is_mu_packet; /* is MU packet or not---*/
- bool is_beamformed; /* BF packet---*/
-};
-
-struct dm_per_pkt_info {
- u8 data_rate;
- u8 station_id;
- bool is_packet_match_bssid;
- bool is_packet_to_self;
- bool is_packet_beacon;
- bool is_to_self;
- u8 ppdu_cnt;
-};
-
-struct odm_phy_dbg_info {
- /*ODM Write,debug info*/
- s8 rx_snr_db[4];
- u32 num_qry_phy_status;
- u32 num_qry_phy_status_cck;
- u32 num_qry_phy_status_ofdm;
- u32 num_qry_mu_pkt;
- u32 num_qry_bf_pkt;
- u32 num_qry_mu_vht_pkt[40];
- u32 num_qry_vht_pkt[40];
- bool is_ldpc_pkt;
- bool is_stbc_pkt;
- u8 num_of_ppdu[4];
- u8 gid_num[4];
- u8 num_qry_beacon_pkt;
- /* Others */
- s32 rx_evm[4];
-};
-
-/*2011/20/20 MH For MP driver RT_WLAN_STA = struct rtl_sta_info*/
-/*Please declare below ODM relative info in your STA info structure.*/
-
-struct odm_sta_info {
- /*Driver Write*/
- bool is_used; /*record the sta status link or not?*/
- u8 iot_peer; /*Enum value. HT_IOT_PEER_E*/
-
- /*ODM Write*/
- /*PHY_STATUS_INFO*/
- u8 rssi_path[4];
- u8 rssi_ave;
- u8 RXEVM[4];
- u8 RXSNR[4];
-};
-
-enum odm_cmninfo {
- /*Fixed value*/
- /*-----------HOOK BEFORE REG INIT-----------*/
- ODM_CMNINFO_PLATFORM = 0,
- ODM_CMNINFO_ABILITY,
- ODM_CMNINFO_INTERFACE,
- ODM_CMNINFO_MP_TEST_CHIP,
- ODM_CMNINFO_IC_TYPE,
- ODM_CMNINFO_CUT_VER,
- ODM_CMNINFO_FAB_VER,
- ODM_CMNINFO_RF_TYPE,
- ODM_CMNINFO_RFE_TYPE,
- ODM_CMNINFO_BOARD_TYPE,
- ODM_CMNINFO_PACKAGE_TYPE,
- ODM_CMNINFO_EXT_LNA,
- ODM_CMNINFO_5G_EXT_LNA,
- ODM_CMNINFO_EXT_PA,
- ODM_CMNINFO_5G_EXT_PA,
- ODM_CMNINFO_GPA,
- ODM_CMNINFO_APA,
- ODM_CMNINFO_GLNA,
- ODM_CMNINFO_ALNA,
- ODM_CMNINFO_EXT_TRSW,
- ODM_CMNINFO_DPK_EN,
- ODM_CMNINFO_EXT_LNA_GAIN,
- ODM_CMNINFO_PATCH_ID,
- ODM_CMNINFO_BINHCT_TEST,
- ODM_CMNINFO_BWIFI_TEST,
- ODM_CMNINFO_SMART_CONCURRENT,
- ODM_CMNINFO_CONFIG_BB_RF,
- ODM_CMNINFO_DOMAIN_CODE_2G,
- ODM_CMNINFO_DOMAIN_CODE_5G,
- ODM_CMNINFO_IQKFWOFFLOAD,
- ODM_CMNINFO_IQKPAOFF,
- ODM_CMNINFO_HUBUSBMODE,
- ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
- ODM_CMNINFO_TX_TP,
- ODM_CMNINFO_RX_TP,
- ODM_CMNINFO_SOUNDING_SEQ,
- ODM_CMNINFO_REGRFKFREEENABLE,
- ODM_CMNINFO_RFKFREEENABLE,
- ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
- ODM_CMNINFO_EFUSE0X3D8,
- ODM_CMNINFO_EFUSE0X3D7,
- /*-----------HOOK BEFORE REG INIT-----------*/
-
- /*Dynamic value:*/
-
- /*--------- POINTER REFERENCE-----------*/
- ODM_CMNINFO_MAC_PHY_MODE,
- ODM_CMNINFO_TX_UNI,
- ODM_CMNINFO_RX_UNI,
- ODM_CMNINFO_WM_MODE,
- ODM_CMNINFO_BAND,
- ODM_CMNINFO_SEC_CHNL_OFFSET,
- ODM_CMNINFO_SEC_MODE,
- ODM_CMNINFO_BW,
- ODM_CMNINFO_CHNL,
- ODM_CMNINFO_FORCED_RATE,
- ODM_CMNINFO_ANT_DIV,
- ODM_CMNINFO_ADAPTIVITY,
- ODM_CMNINFO_DMSP_GET_VALUE,
- ODM_CMNINFO_BUDDY_ADAPTOR,
- ODM_CMNINFO_DMSP_IS_MASTER,
- ODM_CMNINFO_SCAN,
- ODM_CMNINFO_POWER_SAVING,
- ODM_CMNINFO_ONE_PATH_CCA,
- ODM_CMNINFO_DRV_STOP,
- ODM_CMNINFO_PNP_IN,
- ODM_CMNINFO_INIT_ON,
- ODM_CMNINFO_ANT_TEST,
- ODM_CMNINFO_NET_CLOSED,
- ODM_CMNINFO_FORCED_IGI_LB,
- ODM_CMNINFO_P2P_LINK,
- ODM_CMNINFO_FCS_MODE,
- ODM_CMNINFO_IS1ANTENNA,
- ODM_CMNINFO_RFDEFAULTPATH,
- ODM_CMNINFO_DFS_MASTER_ENABLE,
- ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
- ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
- /*--------- POINTER REFERENCE-----------*/
-
- /*------------CALL BY VALUE-------------*/
- ODM_CMNINFO_WIFI_DIRECT,
- ODM_CMNINFO_WIFI_DISPLAY,
- ODM_CMNINFO_LINK_IN_PROGRESS,
- ODM_CMNINFO_LINK,
- ODM_CMNINFO_CMW500LINK,
- ODM_CMNINFO_LPSPG,
- ODM_CMNINFO_STATION_STATE,
- ODM_CMNINFO_RSSI_MIN,
- ODM_CMNINFO_DBG_COMP,
- ODM_CMNINFO_DBG_LEVEL,
- ODM_CMNINFO_RA_THRESHOLD_HIGH,
- ODM_CMNINFO_RA_THRESHOLD_LOW,
- ODM_CMNINFO_RF_ANTENNA_TYPE,
- ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
- ODM_CMNINFO_BE_FIX_TX_ANT,
- ODM_CMNINFO_BT_ENABLED,
- ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
- ODM_CMNINFO_BT_HS_RSSI,
- ODM_CMNINFO_BT_OPERATION,
- ODM_CMNINFO_BT_LIMITED_DIG,
- ODM_CMNINFO_BT_DIG,
- ODM_CMNINFO_BT_BUSY,
- ODM_CMNINFO_BT_DISABLE_EDCA,
- ODM_CMNINFO_AP_TOTAL_NUM,
- ODM_CMNINFO_POWER_TRAINING,
- ODM_CMNINFO_DFS_REGION_DOMAIN,
- /*------------CALL BY VALUE-------------*/
-
- /*Dynamic ptr array hook itms.*/
- ODM_CMNINFO_STA_STATUS,
- ODM_CMNINFO_MAX,
-
-};
-
-enum phydm_info_query {
- PHYDM_INFO_FA_OFDM,
- PHYDM_INFO_FA_CCK,
- PHYDM_INFO_FA_TOTAL,
- PHYDM_INFO_CCA_OFDM,
- PHYDM_INFO_CCA_CCK,
- PHYDM_INFO_CCA_ALL,
- PHYDM_INFO_CRC32_OK_VHT,
- PHYDM_INFO_CRC32_OK_HT,
- PHYDM_INFO_CRC32_OK_LEGACY,
- PHYDM_INFO_CRC32_OK_CCK,
- PHYDM_INFO_CRC32_ERROR_VHT,
- PHYDM_INFO_CRC32_ERROR_HT,
- PHYDM_INFO_CRC32_ERROR_LEGACY,
- PHYDM_INFO_CRC32_ERROR_CCK,
- PHYDM_INFO_EDCCA_FLAG,
- PHYDM_INFO_OFDM_ENABLE,
- PHYDM_INFO_CCK_ENABLE,
- PHYDM_INFO_DBG_PORT_0
-};
-
-enum phydm_api {
- PHYDM_API_NBI = 1,
- PHYDM_API_CSI_MASK,
-
-};
-
-/*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/
-enum odm_ability {
- /*BB ODM section BIT 0-19*/
- ODM_BB_DIG = BIT(0),
- ODM_BB_RA_MASK = BIT(1),
- ODM_BB_DYNAMIC_TXPWR = BIT(2),
- ODM_BB_FA_CNT = BIT(3),
- ODM_BB_RSSI_MONITOR = BIT(4),
- ODM_BB_CCK_PD = BIT(5),
- ODM_BB_ANT_DIV = BIT(6),
- ODM_BB_PWR_TRAIN = BIT(8),
- ODM_BB_RATE_ADAPTIVE = BIT(9),
- ODM_BB_PATH_DIV = BIT(10),
- ODM_BB_ADAPTIVITY = BIT(13),
- ODM_BB_CFO_TRACKING = BIT(14),
- ODM_BB_NHM_CNT = BIT(15),
- ODM_BB_PRIMARY_CCA = BIT(16),
- ODM_BB_TXBF = BIT(17),
- ODM_BB_DYNAMIC_ARFR = BIT(18),
-
- ODM_MAC_EDCA_TURBO = BIT(20),
- ODM_BB_DYNAMIC_RX_PATH = BIT(21),
-
- /*RF ODM section BIT 24-31*/
- ODM_RF_TX_PWR_TRACK = BIT(24),
- ODM_RF_RX_GAIN_TRACK = BIT(25),
- ODM_RF_CALIBRATION = BIT(26),
-
-};
-
-/*ODM_CMNINFO_ONE_PATH_CCA*/
-enum odm_cca_path {
- ODM_CCA_2R = 0,
- ODM_CCA_1R_A = 1,
- ODM_CCA_1R_B = 2,
-};
-
-enum cca_pathdiv_en {
- CCA_PATHDIV_DISABLE = 0,
- CCA_PATHDIV_ENABLE = 1,
-
-};
-
-enum phy_reg_pg_type {
- PHY_REG_PG_RELATIVE_VALUE = 0,
- PHY_REG_PG_EXACT_VALUE = 1
-};
-
-/*2011/09/22 MH Copy from SD4 defined structure.
- *We use to support PHY DM integration.
- */
-
-struct phy_dm_struct {
- /*Add for different team use temporarily*/
- void *adapter; /*For CE/NIC team*/
- struct rtl8192cd_priv *priv; /*For AP/ADSL team*/
- /*When you use adapter or priv pointer,
- *you must make sure the pointer is ready.
- */
- bool odm_ready;
-
- struct rtl8192cd_priv fake_priv;
-
- enum phy_reg_pg_type phy_reg_pg_value_type;
- u8 phy_reg_pg_version;
-
- u32 debug_components;
- u32 fw_debug_components;
- u32 debug_level;
-
- u32 num_qry_phy_status_all; /*CCK + OFDM*/
- u32 last_num_qry_phy_status_all;
- u32 rx_pwdb_ave;
- bool MPDIG_2G; /*off MPDIG*/
- u8 times_2g;
- bool is_init_hw_info_by_rfe;
-
- /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
- bool is_cck_high_power;
- u8 rf_path_rx_enable;
- u8 control_channel;
- /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
-
- /* 1 COMMON INFORMATION */
-
- /*Init value*/
- /*-----------HOOK BEFORE REG INIT-----------*/
- /*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/
- u8 support_platform;
- /* ODM Platform info WIN/AP/CE = 1/2/3 */
- u8 normal_rx_path;
- /*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ... = 1/2/3/...*/
- u32 support_ability;
- /*ODM PCIE/USB/SDIO = 1/2/3*/
- u8 support_interface;
- /*ODM composite or independent. Bit oriented/ 92C+92D+ .... or
- *any other type = 1/2/3/...
- */
- u32 support_ic_type;
- /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
- u8 cut_version;
- /*Fab version TSMC/UMC = 0/1*/
- u8 fab_version;
- /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
- u8 rf_type;
- u8 rfe_type;
- /*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/
- /*Enable Function DPK OFF/ON = 0/1*/
- u8 dpk_en;
- u8 board_type;
- u8 package_type;
- u16 type_glna;
- u16 type_gpa;
- u16 type_alna;
- u16 type_apa;
- /*with external LNA NO/Yes = 0/1*/
- u8 ext_lna; /*2G*/
- u8 ext_lna_5g; /*5G*/
- /*with external PA NO/Yes = 0/1*/
- u8 ext_pa; /*2G*/
- u8 ext_pa_5g; /*5G*/
- /*with Efuse number*/
- u8 efuse0x3d7;
- u8 efuse0x3d8;
- /*with external TRSW NO/Yes = 0/1*/
- u8 ext_trsw;
- u8 ext_lna_gain; /*2G*/
- u8 patch_id; /*Customer ID*/
- bool is_in_hct_test;
- u8 wifi_test;
-
- bool is_dual_mac_smart_concurrent;
- u32 bk_support_ability;
- u8 ant_div_type;
- u8 with_extenal_ant_switch;
- bool config_bbrf;
- u8 odm_regulation_2_4g;
- u8 odm_regulation_5g;
- u8 iqk_fw_offload;
- bool cck_new_agc;
- u8 phydm_period;
- u32 phydm_sys_up_time;
- u8 num_rf_path;
- /*-----------HOOK BEFORE REG INIT-----------*/
-
- /*Dynamic value*/
-
- /*--------- POINTER REFERENCE-----------*/
-
- u8 u1_byte_temp;
- bool BOOLEAN_temp;
- void *PADAPTER_temp;
-
- /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/
- u8 *mac_phy_mode;
- /*TX Unicast byte count*/
- u64 *num_tx_bytes_unicast;
- /*RX Unicast byte count*/
- u64 *num_rx_bytes_unicast;
- /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/
- u8 *wireless_mode;
- /*Frequence band 2.4G/5G = 0/1*/
- u8 *band_type;
- /*Secondary channel offset don't_care/below/above = 0/1/2*/
- u8 *sec_ch_offset;
- /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/
- u8 *security;
- /*BW info 20M/40M/80M = 0/1/2*/
- u8 *band_width;
- /*Central channel location Ch1/Ch2/....*/
- u8 *channel; /*central channel number*/
- bool dpk_done;
- /*Common info for 92D DMSP*/
-
- bool *is_get_value_from_other_mac;
- void **buddy_adapter;
- bool *is_master_of_dmsp; /* MAC0: master, MAC1: slave */
- /*Common info for status*/
- bool *is_scan_in_process;
- bool *is_power_saving;
- /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
- u8 *one_path_cca;
- u8 *antenna_test;
- bool *is_net_closed;
- u8 *pu1_forced_igi_lb;
- bool *is_fcs_mode_enable;
- /*--------- For 8723B IQK-----------*/
- bool *is_1_antenna;
- u8 *rf_default_path;
- /* 0:S1, 1:S0 */
-
- /*--------- POINTER REFERENCE-----------*/
- u16 *forced_data_rate;
- u8 *enable_antdiv;
- u8 *enable_adaptivity;
- u8 *hub_usb_mode;
- bool *is_fw_dw_rsvd_page_in_progress;
- u32 *current_tx_tp;
- u32 *current_rx_tp;
- u8 *sounding_seq;
- /*------------CALL BY VALUE-------------*/
- bool is_link_in_process;
- bool is_wifi_direct;
- bool is_wifi_display;
- bool is_linked;
- bool is_linkedcmw500;
- bool is_in_lps_pg;
- bool bsta_state;
- u8 rssi_min;
- u8 interface_index; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/
- bool is_mp_chip;
- bool is_one_entry_only;
- bool mp_mode;
- u32 one_entry_macid;
- u8 pre_number_linked_client;
- u8 number_linked_client;
- u8 pre_number_active_client;
- u8 number_active_client;
- /*Common info for BTDM*/
- bool is_bt_enabled; /*BT is enabled*/
- bool is_bt_connect_process; /*BT HS is under connection progress.*/
- u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/
- bool is_bt_hs_operation; /*BT HS mode is under progress*/
- u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/
- bool is_bt_disable_edca_turbo; /*Under some condition, don't enable*/
- bool is_bt_busy; /*BT is busy.*/
- bool is_bt_limited_dig; /*BT is busy.*/
- bool is_disable_phy_api;
- /*------------CALL BY VALUE-------------*/
- u8 rssi_a;
- u8 rssi_b;
- u8 rssi_c;
- u8 rssi_d;
- u64 rssi_trsw;
- u64 rssi_trsw_h;
- u64 rssi_trsw_l;
- u64 rssi_trsw_iso;
- u8 tx_ant_status;
- u8 rx_ant_status;
- u8 cck_lna_idx;
- u8 cck_vga_idx;
- u8 curr_station_id;
- u8 ofdm_agc_idx[4];
-
- u8 rx_rate;
- bool is_noisy_state;
- u8 tx_rate;
- u8 linked_interval;
- u8 pre_channel;
- u32 txagc_offset_value_a;
- bool is_txagc_offset_positive_a;
- u32 txagc_offset_value_b;
- bool is_txagc_offset_positive_b;
- u32 tx_tp;
- u32 rx_tp;
- u32 total_tp;
- u64 cur_tx_ok_cnt;
- u64 cur_rx_ok_cnt;
- u64 last_tx_ok_cnt;
- u64 last_rx_ok_cnt;
- u32 bb_swing_offset_a;
- bool is_bb_swing_offset_positive_a;
- u32 bb_swing_offset_b;
- bool is_bb_swing_offset_positive_b;
- u8 igi_lower_bound;
- u8 igi_upper_bound;
- u8 antdiv_rssi;
- u8 fat_comb_a;
- u8 fat_comb_b;
- u8 antdiv_intvl;
- u8 ant_type;
- u8 pre_ant_type;
- u8 antdiv_period;
- u8 evm_antdiv_period;
- u8 antdiv_select;
- u8 path_select;
- u8 antdiv_evm_en;
- u8 bdc_holdstate;
- u8 ndpa_period;
- bool h2c_rarpt_connect;
- bool cck_agc_report_type;
-
- u8 dm_dig_max_TH;
- u8 dm_dig_min_TH;
- u8 print_agc;
- u8 traffic_load;
- u8 pre_traffic_load;
- /*8821C Antenna BTG/WLG/WLA Select*/
- u8 current_rf_set_8821c;
- u8 default_rf_set_8821c;
- /*For Adaptivtiy*/
- u16 nhm_cnt_0;
- u16 nhm_cnt_1;
- s8 TH_L2H_default;
- s8 th_edcca_hl_diff_default;
- s8 th_l2h_ini;
- s8 th_edcca_hl_diff;
- s8 th_l2h_ini_mode2;
- s8 th_edcca_hl_diff_mode2;
- bool carrier_sense_enable;
- u8 adaptivity_igi_upper;
- bool adaptivity_flag;
- u8 dc_backoff;
- bool adaptivity_enable;
- u8 ap_total_num;
- bool edcca_enable;
- u8 pre_dbg_priority;
- struct adaptivity_statistics adaptivity;
- /*For Adaptivtiy*/
- u8 last_usb_hub;
- u8 tx_bf_data_rate;
-
- u8 nbi_set_result;
-
- u8 c2h_cmd_start;
- u8 fw_debug_trace[60];
- u8 pre_c2h_seq;
- bool fw_buff_is_enpty;
- u32 data_frame_num;
-
- /*for noise detection*/
- bool noisy_decision; /*b_noisy*/
- bool pre_b_noisy;
- u32 noisy_decision_smooth;
- bool is_disable_dym_ecs;
-
- struct odm_noise_monitor noise_level;
- /*Define STA info.*/
- /*odm_sta_info*/
- /*2012/01/12 MH For MP,
- *we need to reduce one array pointer for default port.??
- */
- struct rtl_sta_info *odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
- u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];
- /* platform_macid_table[platform_macid] = phydm_macid */
- s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM];
-
- /*2012/02/14 MH Add to share 88E ra with other SW team.*/
- /*We need to colelct all support abilit to a proper area.*/
-
- bool ra_support88e;
-
- struct odm_phy_dbg_info phy_dbg_info;
-
- /*ODM Structure*/
- struct fast_antenna_training dm_fat_table;
- struct dig_thres dm_dig_table;
- struct dyn_pwr_saving dm_ps_table;
- struct dyn_primary_cca dm_pri_cca;
- struct ra_table dm_ra_table;
- struct false_alarm_stat false_alm_cnt;
- struct false_alarm_stat flase_alm_cnt_buddy_adapter;
- struct sw_antenna_switch dm_swat_table;
- struct cfo_tracking dm_cfo_track;
- struct acs_info dm_acs;
- struct ccx_info dm_ccx_info;
- struct psd_info dm_psd_table;
-
- struct rt_adcsmp adcsmp;
-
- struct dm_iqk_info IQK_info;
-
- struct edca_turbo dm_edca_table;
- u32 WMMEDCA_BE;
-
- bool *is_driver_stopped;
- bool *is_driver_is_going_to_pnp_set_power_sleep;
- bool *pinit_adpt_in_progress;
-
- /*PSD*/
- bool is_user_assign_level;
- u8 RSSI_BT; /*come from BT*/
- bool is_psd_in_process;
- bool is_psd_active;
- bool is_dm_initial_gain_enable;
-
- /*MPT DIG*/
- struct timer_list mpt_dig_timer;
-
- /*for rate adaptive, in fact, 88c/92c fw will handle this*/
- u8 is_use_ra_mask;
-
- /* for dynamic SoML control */
- bool bsomlenabled;
-
- struct odm_rate_adaptive rate_adaptive;
- struct dm_rf_calibration_struct rf_calibrate_info;
- u32 n_iqk_cnt;
- u32 n_iqk_ok_cnt;
- u32 n_iqk_fail_cnt;
-
- /*Power Training*/
- u8 force_power_training_state;
- bool is_change_state;
- u32 PT_score;
- u64 ofdm_rx_cnt;
- u64 cck_rx_cnt;
- bool is_disable_power_training;
- u8 dynamic_tx_high_power_lvl;
- u8 last_dtp_lvl;
- u32 tx_agc_ofdm_18_6;
- u8 rx_pkt_type;
-
- /*ODM relative time.*/
- struct timer_list path_div_switch_timer;
- /*2011.09.27 add for path Diversity*/
- struct timer_list cck_path_diversity_timer;
- struct timer_list fast_ant_training_timer;
- struct timer_list sbdcnt_timer;
-
- /*ODM relative workitem.*/
-};
-
-enum phydm_structure_type {
- PHYDM_FALSEALMCNT,
- PHYDM_CFOTRACK,
- PHYDM_ADAPTIVITY,
- PHYDM_ROMINFO,
-
-};
-
-enum odm_rf_content {
- odm_radioa_txt = 0x1000,
- odm_radiob_txt = 0x1001,
- odm_radioc_txt = 0x1002,
- odm_radiod_txt = 0x1003
-};
-
-enum odm_bb_config_type {
- CONFIG_BB_PHY_REG,
- CONFIG_BB_AGC_TAB,
- CONFIG_BB_AGC_TAB_2G,
- CONFIG_BB_AGC_TAB_5G,
- CONFIG_BB_PHY_REG_PG,
- CONFIG_BB_PHY_REG_MP,
- CONFIG_BB_AGC_TAB_DIFF,
-};
-
-enum odm_rf_config_type {
- CONFIG_RF_RADIO,
- CONFIG_RF_TXPWR_LMT,
-};
-
-enum odm_fw_config_type {
- CONFIG_FW_NIC,
- CONFIG_FW_NIC_2,
- CONFIG_FW_AP,
- CONFIG_FW_AP_2,
- CONFIG_FW_MP,
- CONFIG_FW_WOWLAN,
- CONFIG_FW_WOWLAN_2,
- CONFIG_FW_AP_WOWLAN,
- CONFIG_FW_BT,
-};
-
-/*status code*/
-enum rt_status {
- RT_STATUS_SUCCESS,
- RT_STATUS_FAILURE,
- RT_STATUS_PENDING,
- RT_STATUS_RESOURCE,
- RT_STATUS_INVALID_CONTEXT,
- RT_STATUS_INVALID_PARAMETER,
- RT_STATUS_NOT_SUPPORT,
- RT_STATUS_OS_API_FAILED,
-};
-
-/*===========================================================*/
-/*AGC RX High Power mode*/
-/*===========================================================*/
-#define lna_low_gain_1 0x64
-#define lna_low_gain_2 0x5A
-#define lna_low_gain_3 0x58
-
-#define FA_RXHP_TH1 5000
-#define FA_RXHP_TH2 1500
-#define FA_RXHP_TH3 800
-#define FA_RXHP_TH4 600
-#define FA_RXHP_TH5 500
-
-enum dm_1r_cca {
- CCA_1R = 0,
- CCA_2R = 1,
- CCA_MAX = 2,
-};
-
-enum dm_rf {
- rf_save = 0,
- rf_normal = 1,
- RF_MAX = 2,
-};
-
-/*check Sta pointer valid or not*/
-
-#define IS_STA_VALID(sta) (sta)
-
-u32 odm_convert_to_db(u32 value);
-
-u32 odm_convert_to_linear(u32 value);
-
-s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
-
-s32 odm_sign_conversion(s32 value, u32 total_bit);
-
-void odm_init_mp_driver_status(struct phy_dm_struct *dm);
-
-void phydm_txcurrentcalibration(struct phy_dm_struct *dm);
-
-void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
- u8 seq_length);
-
-void odm_dm_init(struct phy_dm_struct *dm);
-
-void odm_dm_reset(struct phy_dm_struct *dm);
-
-void phydm_support_ability_debug(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len);
-
-void phydm_config_ofdm_rx_path(struct phy_dm_struct *dm, u32 path);
-
-void phydm_config_trx_path(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len);
-
-void odm_dm_watchdog(struct phy_dm_struct *dm);
-
-void phydm_watchdog_mp(struct phy_dm_struct *dm);
-
-void odm_cmn_info_init(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
- u32 value);
-
-void odm_cmn_info_hook(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
- void *value);
-
-void odm_cmn_info_ptr_array_hook(struct phy_dm_struct *dm,
- enum odm_cmninfo cmn_info, u16 index,
- void *value);
-
-void odm_cmn_info_update(struct phy_dm_struct *dm, u32 cmn_info, u64 value);
-
-u32 phydm_cmn_info_query(struct phy_dm_struct *dm,
- enum phydm_info_query info_type);
-
-void odm_init_all_timers(struct phy_dm_struct *dm);
-
-void odm_cancel_all_timers(struct phy_dm_struct *dm);
-
-void odm_release_all_timers(struct phy_dm_struct *dm);
-
-void odm_asoc_entry_init(struct phy_dm_struct *dm);
-
-void *phydm_get_structure(struct phy_dm_struct *dm, u8 structure_type);
-
-/*===========================================================*/
-/* The following is for compile only*/
-/*===========================================================*/
-
-#define IS_HARDWARE_TYPE_8188E(_adapter) false
-#define IS_HARDWARE_TYPE_8188F(_adapter) false
-#define IS_HARDWARE_TYPE_8703B(_adapter) false
-#define IS_HARDWARE_TYPE_8723D(_adapter) false
-#define IS_HARDWARE_TYPE_8821C(_adapter) false
-#define IS_HARDWARE_TYPE_8812AU(_adapter) false
-#define IS_HARDWARE_TYPE_8814A(_adapter) false
-#define IS_HARDWARE_TYPE_8814AU(_adapter) false
-#define IS_HARDWARE_TYPE_8814AE(_adapter) false
-#define IS_HARDWARE_TYPE_8814AS(_adapter) false
-#define IS_HARDWARE_TYPE_8723BU(_adapter) false
-#define IS_HARDWARE_TYPE_8822BU(_adapter) false
-#define IS_HARDWARE_TYPE_8822BS(_adapter) false
-#define IS_HARDWARE_TYPE_JAGUAR(_adapter) \
- (IS_HARDWARE_TYPE_8812(_adapter) || IS_HARDWARE_TYPE_8821(_adapter))
-#define IS_HARDWARE_TYPE_8723AE(_adapter) false
-#define IS_HARDWARE_TYPE_8192C(_adapter) false
-#define IS_HARDWARE_TYPE_8192D(_adapter) false
-#define RF_T_METER_92D 0x42
-
-#define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) \
- LE_BITS_TO_1BYTE(__prx_status_desc + 12, 0, 6)
-
-#define REG_CONFIG_RAM64X16 0xb2c
-
-#define TARGET_CHNL_NUM_2G_5G 59
-
-/* *********************************************************** */
-
-void odm_dtc(struct phy_dm_struct *dm);
-
-void phydm_noisy_detection(struct phy_dm_struct *dm);
-
-void phydm_set_ext_switch(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len);
-
-void phydm_api_debug(void *dm_void, u32 function_map, u32 *const dm_value,
- u32 *_used, char *output, u32 *_out_len);
-
-u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
- u32 f_interference, u32 second_ch);
-#endif /* __HALDMOUTSRC_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-u8 odm_get_auto_channel_select_result(void *dm_void, u8 band)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct acs_info *acs = &dm->dm_acs;
- u8 result;
-
- if (band == ODM_BAND_2_4G) {
- ODM_RT_TRACE(
- dm, ODM_COMP_ACS,
- "[struct acs_info] %s(): clean_channel_2g(%d)\n",
- __func__, acs->clean_channel_2g);
- result = (u8)acs->clean_channel_2g;
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_ACS,
- "[struct acs_info] %s(): clean_channel_5g(%d)\n",
- __func__, acs->clean_channel_5g);
- result = (u8)acs->clean_channel_5g;
- }
-
- return result;
-}
-
-static void odm_auto_channel_select_setting(void *dm_void, bool is_enable)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u16 period = 0x2710; /* 40ms in default */
- u16 nhm_type = 0x7;
-
- ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
-
- if (is_enable) {
- /* 20 ms */
- period = 0x1388;
- nhm_type = 0x1;
- }
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- /* PHY parameters initialize for ac series */
-
- /* 0x990[31:16]=0x2710
- * Time duration for NHM unit: 4us, 0x2710=40ms
- */
- odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, period);
- } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- /* PHY parameters initialize for n series */
-
- /* 0x894[31:16]=0x2710
- * Time duration for NHM unit: 4us, 0x2710=40ms
- */
- odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11N + 2, period);
- }
-}
-
-void odm_auto_channel_select_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct acs_info *acs = &dm->dm_acs;
- u8 i;
-
- if (!(dm->support_ability & ODM_BB_NHM_CNT))
- return;
-
- if (acs->is_force_acs_result)
- return;
-
- ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
-
- acs->clean_channel_2g = 1;
- acs->clean_channel_5g = 36;
-
- for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) {
- acs->channel_info_2g[0][i] = 0;
- acs->channel_info_2g[1][i] = 0;
- }
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) {
- acs->channel_info_5g[0][i] = 0;
- acs->channel_info_5g[1][i] = 0;
- }
- }
-}
-
-void odm_auto_channel_select_reset(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct acs_info *acs = &dm->dm_acs;
-
- if (!(dm->support_ability & ODM_BB_NHM_CNT))
- return;
-
- if (acs->is_force_acs_result)
- return;
-
- ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
-
- odm_auto_channel_select_setting(dm, true); /* for 20ms measurement */
- phydm_nhm_counter_statistics_reset(dm);
-}
-
-void odm_auto_channel_select(void *dm_void, u8 channel)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct acs_info *acs = &dm->dm_acs;
- u8 channel_idx = 0, search_idx = 0;
- u16 max_score = 0;
-
- if (!(dm->support_ability & ODM_BB_NHM_CNT)) {
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): Return: support_ability ODM_BB_NHM_CNT is disabled\n",
- __func__);
- return;
- }
-
- if (acs->is_force_acs_result) {
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): Force 2G clean channel = %d, 5G clean channel = %d\n",
- __func__, acs->clean_channel_2g, acs->clean_channel_5g);
- return;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s(): channel = %d=========>\n",
- __func__, channel);
-
- phydm_get_nhm_counter_statistics(dm);
- odm_auto_channel_select_setting(dm, false);
-
- if (channel >= 1 && channel <= 14) {
- channel_idx = channel - 1;
- acs->channel_info_2g[1][channel_idx]++;
-
- if (acs->channel_info_2g[1][channel_idx] >= 2)
- acs->channel_info_2g[0][channel_idx] =
- (acs->channel_info_2g[0][channel_idx] >> 1) +
- (acs->channel_info_2g[0][channel_idx] >> 2) +
- (dm->nhm_cnt_0 >> 2);
- else
- acs->channel_info_2g[0][channel_idx] = dm->nhm_cnt_0;
-
- ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s(): nhm_cnt_0 = %d\n",
- __func__, dm->nhm_cnt_0);
- ODM_RT_TRACE(
- dm, ODM_COMP_ACS,
- "%s(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n",
- __func__, channel_idx,
- acs->channel_info_2g[0][channel_idx], channel_idx,
- acs->channel_info_2g[1][channel_idx]);
-
- for (search_idx = 0; search_idx < ODM_MAX_CHANNEL_2G;
- search_idx++) {
- if (acs->channel_info_2g[1][search_idx] != 0 &&
- acs->channel_info_2g[0][search_idx] >= max_score) {
- max_score = acs->channel_info_2g[0][search_idx];
- acs->clean_channel_2g = search_idx + 1;
- }
- }
- ODM_RT_TRACE(
- dm, ODM_COMP_ACS,
- "(1)%s(): 2G: clean_channel_2g = %d, max_score = %d\n",
- __func__, acs->clean_channel_2g, max_score);
-
- } else if (channel >= 36) {
- /* Need to do */
- acs->clean_channel_5g = channel;
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMACS_H__
-#define __PHYDMACS_H__
-
-#define ACS_VERSION "1.1" /*20150729 by YuChen*/
-#define CLM_VERSION "1.0"
-
-#define ODM_MAX_CHANNEL_2G 14
-#define ODM_MAX_CHANNEL_5G 24
-
-/* For phydm_auto_channel_select_setting_ap() */
-#define STORE_DEFAULT_NHM_SETTING 0
-#define RESTORE_DEFAULT_NHM_SETTING 1
-#define ACS_NHM_SETTING 2
-
-struct acs_info {
- bool is_force_acs_result;
- u8 clean_channel_2g;
- u8 clean_channel_5g;
- /* channel_info[1]: channel score, channel_info[2]:channel_scan_times */
- u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G];
- u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G];
-};
-
-void odm_auto_channel_select_init(void *dm_void);
-
-void odm_auto_channel_select_reset(void *dm_void);
-
-void odm_auto_channel_select(void *dm_void, u8 channel);
-
-u8 odm_get_auto_channel_select_result(void *dm_void, u8 band);
-
-#endif /* #ifndef __PHYDMACS_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-void phydm_check_adaptivity(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct adaptivity_statistics *adaptivity =
- (struct adaptivity_statistics *)phydm_get_structure(
- dm, PHYDM_ADAPTIVITY);
-
- if (dm->support_ability & ODM_BB_ADAPTIVITY) {
- if (adaptivity->dynamic_link_adaptivity ||
- adaptivity->acs_for_adaptivity) {
- if (dm->is_linked && !adaptivity->is_check) {
- phydm_nhm_counter_statistics(dm);
- phydm_check_environment(dm);
- } else if (!dm->is_linked) {
- adaptivity->is_check = false;
- }
- } else {
- dm->adaptivity_enable = true;
-
- if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA |
- ODM_IC_11N_GAIN_IDX_EDCCA))
- dm->adaptivity_flag = false;
- else
- dm->adaptivity_flag = true;
- }
- } else {
- dm->adaptivity_enable = false;
- dm->adaptivity_flag = false;
- }
-}
-
-void phydm_nhm_counter_statistics_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- /*PHY parameters initialize for n series*/
-
- /*0x894[31:16]=0x0xC350
- *Time duration for NHM unit: us, 0xc350=200ms
- */
- odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11N + 2, 0xC350);
- /*0x890[31:16]=0xffff th_9, th_10*/
- odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff);
- /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/
- odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50);
- /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/
- odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff);
- /*0xe28[7:0]=0xff th_8*/
- odm_set_bb_reg(dm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff);
- /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N,
- BIT(10) | BIT(9) | BIT(8), 0x1);
- /*0xc0c[7]=1 max power among all RX ants*/
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1);
- } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- /*PHY parameters initialize for ac series*/
-
- odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, 0xC350);
- /*0x994[31:16]=0xffff th_9, th_10*/
- odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff);
- /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/
- odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50);
- /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/
- odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff);
- /*0x9a0[7:0]=0xff th_8*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff);
- /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC,
- BIT(8) | BIT(9) | BIT(10), 0x1);
- /*0x9e8[7]=1 max power among all RX ants*/
- odm_set_bb_reg(dm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1);
- }
-}
-
-void phydm_nhm_counter_statistics(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (!(dm->support_ability & ODM_BB_NHM_CNT))
- return;
-
- /*Get NHM report*/
- phydm_get_nhm_counter_statistics(dm);
-
- /*Reset NHM counter*/
- phydm_nhm_counter_statistics_reset(dm);
-}
-
-void phydm_get_nhm_counter_statistics(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 value32 = 0;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- value32 = odm_get_bb_reg(dm, ODM_REG_NHM_CNT_11AC, MASKDWORD);
- else if (dm->support_ic_type & ODM_IC_11N_SERIES)
- value32 = odm_get_bb_reg(dm, ODM_REG_NHM_CNT_11N, MASKDWORD);
-
- dm->nhm_cnt_0 = (u8)(value32 & MASKBYTE0);
- dm->nhm_cnt_1 = (u8)((value32 & MASKBYTE1) >> 8);
-}
-
-void phydm_nhm_counter_statistics_reset(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
- } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
- }
-}
-
-void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES)
- odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
- MASKBYTE2 | MASKBYTE0,
- (u32)((u8)L2H | (u8)H2L << 16));
- else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
- (u16)((u8)L2H | (u8)H2L << 8));
-}
-
-static void phydm_set_lna(void *dm_void, enum phydm_set_lna type)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) {
- if (type == phydm_disable_lna) {
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
- 0x0000f);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
- 0x37f82); /*disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- if (dm->rf_type > ODM_1T1R) {
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
- 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
- 0x18000);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
- 0x0000f);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
- 0x37f82);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
- 0x0);
- }
- } else if (type == phydm_enable_lna) {
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
- 0x0000f);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
- 0x77f82); /*back to normal*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- if (dm->rf_type > ODM_1T1R) {
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
- 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
- 0x18000);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
- 0x0000f);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
- 0x77f82);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
- 0x0);
- }
- }
- } else if (dm->support_ic_type & ODM_RTL8723B) {
- if (type == phydm_disable_lna) {
- /*S0*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
- 0x0001f);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
- 0xe6137); /*disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- /*S1*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
- odm_set_rf_reg(
- dm, ODM_RF_PATH_A, 0x43, 0xfffff,
- 0x3008d); /*select Rx mode and disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
- } else if (type == phydm_enable_lna) {
- /*S0*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
- 0x0001f);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
- 0xe6177); /*disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- /*S1*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
- odm_set_rf_reg(
- dm, ODM_RF_PATH_A, 0x43, 0xfffff,
- 0x300bd); /*select Rx mode and disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
- }
-
- } else if (dm->support_ic_type & ODM_RTL8812) {
- if (type == phydm_disable_lna) {
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
- 0x3f7ff);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
- 0xc22bf); /*disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- if (dm->rf_type > ODM_1T1R) {
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
- 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
- 0x3f7ff);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
- 0xc22bf); /*disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
- 0x0);
- }
- } else if (type == phydm_enable_lna) {
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
- 0x3f7ff);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
- 0xc26bf); /*disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- if (dm->rf_type > ODM_1T1R) {
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
- 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
- 0x3f7ff);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
- 0xc26bf); /*disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
- 0x0);
- }
- }
- } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
- if (type == phydm_disable_lna) {
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
- 0x0002f);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
- 0xfb09b); /*disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- } else if (type == phydm_enable_lna) {
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
- 0x18000); /*select Rx mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
- 0x0002f);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
- 0xfb0bb); /*disable LNA*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- }
- }
-}
-
-void phydm_set_trx_mux(void *dm_void, enum phydm_trx_mux_type tx_mode,
- enum phydm_trx_mux_type rx_mode)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- /*set TXmod to standby mode to remove outside noise affect*/
- odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N,
- BIT(3) | BIT(2) | BIT(1), tx_mode);
- /*set RXmod to standby mode to remove outside noise affect*/
- odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N,
- BIT(22) | BIT(21) | BIT(20), rx_mode);
- if (dm->rf_type > ODM_1T1R) {
- /*set TXmod to standby mode to rm outside noise affect*/
- odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B,
- BIT(3) | BIT(2) | BIT(1), tx_mode);
- /*set RXmod to standby mode to rm outside noise affect*/
- odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B,
- BIT(22) | BIT(21) | BIT(20), rx_mode);
- }
- } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- /*set TXmod to standby mode to remove outside noise affect*/
- odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC,
- BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode);
- /*set RXmod to standby mode to remove outside noise affect*/
- odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC,
- BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode);
- if (dm->rf_type > ODM_1T1R) {
- /*set TXmod to standby mode to rm outside noise affect*/
- odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B,
- BIT(11) | BIT(10) | BIT(9) | BIT(8),
- tx_mode);
- /*set RXmod to standby mode to rm outside noise affect*/
- odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B,
- BIT(7) | BIT(6) | BIT(5) | BIT(4),
- rx_mode);
- }
- }
-}
-
-void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (state == phydm_ignore_edcca) {
- /*ignore EDCCA reg520[15]=1*/
- odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 1);
- } else { /*don't set MAC ignore EDCCA signal*/
- /*don't ignore EDCCA reg520[15]=0*/
- odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 0);
- }
- ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "EDCCA enable state = %d\n",
- state);
-}
-
-bool phydm_cal_nhm_cnt(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u16 base = 0;
-
- base = dm->nhm_cnt_0 + dm->nhm_cnt_1;
-
- if (base != 0) {
- dm->nhm_cnt_0 = ((dm->nhm_cnt_0) << 8) / base;
- dm->nhm_cnt_1 = ((dm->nhm_cnt_1) << 8) / base;
- }
- if ((dm->nhm_cnt_0 - dm->nhm_cnt_1) >= 100)
- return true; /*clean environment*/
- else
- return false; /*noisy environment*/
-}
-
-void phydm_check_environment(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct adaptivity_statistics *adaptivity =
- (struct adaptivity_statistics *)phydm_get_structure(
- dm, PHYDM_ADAPTIVITY);
- bool is_clean_environment = false;
-
- if (adaptivity->is_first_link) {
- if (dm->support_ic_type &
- (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
- dm->adaptivity_flag = false;
- else
- dm->adaptivity_flag = true;
-
- adaptivity->is_first_link = false;
- return;
- }
-
- if (adaptivity->nhm_wait < 3) { /*Start enter NHM after 4 nhm_wait*/
- adaptivity->nhm_wait++;
- phydm_nhm_counter_statistics(dm);
- return;
- }
-
- phydm_nhm_counter_statistics(dm);
- is_clean_environment = phydm_cal_nhm_cnt(dm);
-
- if (is_clean_environment) {
- dm->th_l2h_ini =
- adaptivity->th_l2h_ini_backup; /*adaptivity mode*/
- dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
-
- dm->adaptivity_enable = true;
-
- if (dm->support_ic_type &
- (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
- dm->adaptivity_flag = false;
- else
- dm->adaptivity_flag = true;
- } else {
- if (!adaptivity->acs_for_adaptivity) {
- dm->th_l2h_ini = dm->th_l2h_ini_mode2; /*mode2*/
- dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
-
- dm->adaptivity_flag = false;
- dm->adaptivity_enable = false;
- }
- }
-
- adaptivity->nhm_wait = 0;
- adaptivity->is_first_link = true;
- adaptivity->is_check = true;
-}
-
-void phydm_search_pwdb_lower_bound(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct adaptivity_statistics *adaptivity =
- (struct adaptivity_statistics *)phydm_get_structure(
- dm, PHYDM_ADAPTIVITY);
- u32 value32 = 0, reg_value32 = 0;
- u8 cnt, try_count = 0;
- u8 tx_edcca1 = 0, tx_edcca0 = 0;
- bool is_adjust = true;
- s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;
- s8 diff;
- u8 IGI = adaptivity->igi_base + 30 + (u8)dm->th_l2h_ini -
- (u8)dm->th_edcca_hl_diff;
-
- if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
- ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) {
- phydm_set_lna(dm, phydm_disable_lna);
- } else {
- phydm_set_trx_mux(dm, phydm_standby_mode, phydm_standby_mode);
- odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);
- }
-
- diff = igi_target - (s8)IGI;
- th_l2h_dmc = dm->th_l2h_ini + diff;
- if (th_l2h_dmc > 10)
- th_l2h_dmc = 10;
- th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
-
- phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
- ODM_delay_ms(30);
-
- while (is_adjust) {
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x0);
- reg_value32 =
- odm_get_bb_reg(dm, ODM_REG_RPT_11N, MASKDWORD);
- } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD,
- 0x0);
- reg_value32 =
- odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- }
- while (reg_value32 & BIT(3) && try_count < 3) {
- ODM_delay_ms(3);
- try_count = try_count + 1;
- if (dm->support_ic_type & ODM_IC_11N_SERIES)
- reg_value32 = odm_get_bb_reg(
- dm, ODM_REG_RPT_11N, MASKDWORD);
- else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- reg_value32 = odm_get_bb_reg(
- dm, ODM_REG_RPT_11AC, MASKDWORD);
- }
- try_count = 0;
-
- for (cnt = 0; cnt < 20; cnt++) {
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N,
- MASKDWORD, 0x208);
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11N,
- MASKDWORD);
- } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC,
- MASKDWORD, 0x209);
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC,
- MASKDWORD);
- }
- if (value32 & BIT(30) &&
- (dm->support_ic_type &
- (ODM_RTL8723B | ODM_RTL8188E)))
- tx_edcca1 = tx_edcca1 + 1;
- else if (value32 & BIT(29))
- tx_edcca1 = tx_edcca1 + 1;
- else
- tx_edcca0 = tx_edcca0 + 1;
- }
-
- if (tx_edcca1 > 1) {
- IGI = IGI - 1;
- th_l2h_dmc = th_l2h_dmc + 1;
- if (th_l2h_dmc > 10)
- th_l2h_dmc = 10;
- th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
-
- phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
- if (th_l2h_dmc == 10) {
- is_adjust = false;
- adaptivity->h2l_lb = th_h2l_dmc;
- adaptivity->l2h_lb = th_l2h_dmc;
- dm->adaptivity_igi_upper = IGI;
- }
-
- tx_edcca1 = 0;
- tx_edcca0 = 0;
-
- } else {
- is_adjust = false;
- adaptivity->h2l_lb = th_h2l_dmc;
- adaptivity->l2h_lb = th_l2h_dmc;
- dm->adaptivity_igi_upper = IGI;
- tx_edcca1 = 0;
- tx_edcca0 = 0;
- }
- }
-
- dm->adaptivity_igi_upper = dm->adaptivity_igi_upper - dm->dc_backoff;
- adaptivity->h2l_lb = adaptivity->h2l_lb + dm->dc_backoff;
- adaptivity->l2h_lb = adaptivity->l2h_lb + dm->dc_backoff;
-
- if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
- ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) {
- phydm_set_lna(dm, phydm_enable_lna);
- } else {
- phydm_set_trx_mux(dm, phydm_tx_mode, phydm_rx_mode);
- odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);
- }
-
- phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
-}
-
-static bool phydm_re_search_condition(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 adaptivity_igi_upper;
- u8 count = 0;
-
- adaptivity_igi_upper = dm->adaptivity_igi_upper + dm->dc_backoff;
-
- if (adaptivity_igi_upper <= 0x26 && count < 3) {
- count = count + 1;
- return true;
- }
-
- return false;
-}
-
-void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
- u32 value)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct adaptivity_statistics *adaptivity =
- (struct adaptivity_statistics *)phydm_get_structure(
- dm, PHYDM_ADAPTIVITY);
-
- switch (cmn_info) {
- case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
- dm->carrier_sense_enable = (bool)value;
- break;
-
- case PHYDM_ADAPINFO_DCBACKOFF:
- dm->dc_backoff = (u8)value;
- break;
-
- case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
- adaptivity->dynamic_link_adaptivity = (bool)value;
- break;
-
- case PHYDM_ADAPINFO_TH_L2H_INI:
- dm->th_l2h_ini = (s8)value;
- break;
-
- case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
- dm->th_edcca_hl_diff = (s8)value;
- break;
-
- case PHYDM_ADAPINFO_AP_NUM_TH:
- adaptivity->ap_num_th = (u8)value;
- break;
-
- default:
- break;
- }
-}
-
-void phydm_adaptivity_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct adaptivity_statistics *adaptivity =
- (struct adaptivity_statistics *)phydm_get_structure(
- dm, PHYDM_ADAPTIVITY);
- s8 igi_target = 0x32;
-
- if (!dm->carrier_sense_enable) {
- if (dm->th_l2h_ini == 0)
- dm->th_l2h_ini = 0xf5;
- } else {
- dm->th_l2h_ini = 0xa;
- }
-
- if (dm->th_edcca_hl_diff == 0)
- dm->th_edcca_hl_diff = 7;
- if (dm->wifi_test || dm->mp_mode) {
- /*even no adaptivity, we still enable EDCCA, AP use mib ctrl*/
- dm->edcca_enable = false;
- } else {
- dm->edcca_enable = true;
- }
-
- dm->adaptivity_igi_upper = 0;
- dm->adaptivity_enable =
- false; /*use this flag to decide enable or disable*/
-
- dm->th_l2h_ini_mode2 = 20;
- dm->th_edcca_hl_diff_mode2 = 8;
- adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
- adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
-
- adaptivity->igi_base = 0x32;
- adaptivity->igi_target = 0x1c;
- adaptivity->h2l_lb = 0;
- adaptivity->l2h_lb = 0;
- adaptivity->nhm_wait = 0;
- adaptivity->is_check = false;
- adaptivity->is_first_link = true;
- adaptivity->adajust_igi_level = 0;
- adaptivity->is_stop_edcca = false;
- adaptivity->backup_h2l = 0;
- adaptivity->backup_l2h = 0;
-
- phydm_mac_edcca_state(dm, phydm_dont_ignore_edcca);
-
- /*Search pwdB lower bound*/
- if (dm->support_ic_type & ODM_IC_11N_SERIES)
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x208);
- else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x209);
-
- if (dm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) {
- if (dm->support_ic_type & ODM_RTL8197F) {
- /*set to page B1*/
- odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1);
- /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
- odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_97F,
- BIT(27) | BIT(26), 0x1);
- odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0);
- } else {
- /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
- odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_11N,
- BIT(21) | BIT(20), 0x1);
- }
- }
- /*8814a no need to find pwdB lower bound, maybe*/
- if (dm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) {
- /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
- odm_set_bb_reg(dm, ODM_REG_ACBB_EDCCA_ENHANCE,
- BIT(29) | BIT(28), 0x1);
- }
-
- if (!(dm->support_ic_type &
- (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
- phydm_search_pwdb_lower_bound(dm);
- if (phydm_re_search_condition(dm))
- phydm_search_pwdb_lower_bound(dm);
- }
-
- /*we need to consider PwdB upper bound for 8814 later IC*/
- adaptivity->adajust_igi_level =
- (u8)((dm->th_l2h_ini + igi_target) - pwdb_upper_bound +
- dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/
-
- ODM_RT_TRACE(
- dm, PHYDM_COMP_ADAPTIVITY,
- "th_l2h_ini = 0x%x, th_edcca_hl_diff = 0x%x, adaptivity->adajust_igi_level = 0x%x\n",
- dm->th_l2h_ini, dm->th_edcca_hl_diff,
- adaptivity->adajust_igi_level);
-
- /*Check this later on Windows*/
- /*phydm_set_edcca_threshold_api(dm, dig_tab->cur_ig_value);*/
-}
-
-void phydm_adaptivity(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- u8 IGI = dig_tab->cur_ig_value;
- s8 th_l2h_dmc, th_h2l_dmc;
- s8 diff = 0, igi_target;
- struct adaptivity_statistics *adaptivity =
- (struct adaptivity_statistics *)phydm_get_structure(
- dm, PHYDM_ADAPTIVITY);
-
- if (!dm->edcca_enable || adaptivity->is_stop_edcca) {
- ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "Disable EDCCA!!!\n");
- return;
- }
-
- if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
- ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
- "adaptivity disable, enable EDCCA mode!!!\n");
- dm->th_l2h_ini = dm->th_l2h_ini_mode2;
- dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
- }
-
- ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "%s() =====>\n", __func__);
- ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
- "igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
- adaptivity->igi_base, dm->th_l2h_ini,
- dm->th_edcca_hl_diff);
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- /*fix AC series when enable EDCCA hang issue*/
- odm_set_bb_reg(dm, 0x800, BIT(10), 1); /*ADC_mask disable*/
- odm_set_bb_reg(dm, 0x800, BIT(10), 0); /*ADC_mask enable*/
- }
- if (*dm->band_width == ODM_BW20M) /*CHANNEL_WIDTH_20*/
- igi_target = adaptivity->igi_base;
- else if (*dm->band_width == ODM_BW40M)
- igi_target = adaptivity->igi_base + 2;
- else if (*dm->band_width == ODM_BW80M)
- igi_target = adaptivity->igi_base + 2;
- else
- igi_target = adaptivity->igi_base;
- adaptivity->igi_target = (u8)igi_target;
-
- ODM_RT_TRACE(
- dm, PHYDM_COMP_ADAPTIVITY,
- "band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d, acs_for_adaptivity = %d\n",
- (*dm->band_width == ODM_BW80M) ?
- "80M" :
- ((*dm->band_width == ODM_BW40M) ? "40M" : "20M"),
- igi_target, adaptivity->dynamic_link_adaptivity,
- adaptivity->acs_for_adaptivity);
- ODM_RT_TRACE(
- dm, PHYDM_COMP_ADAPTIVITY,
- "rssi_min = %d, adaptivity->adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n",
- dm->rssi_min, adaptivity->adajust_igi_level,
- dm->adaptivity_flag, dm->adaptivity_enable);
-
- if (adaptivity->dynamic_link_adaptivity && !dm->is_linked &&
- !dm->adaptivity_enable) {
- phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
- ODM_RT_TRACE(
- dm, PHYDM_COMP_ADAPTIVITY,
- "In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n");
- return;
- }
-
- if (dm->support_ic_type &
- (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
- if (adaptivity->adajust_igi_level > IGI &&
- dm->adaptivity_enable)
- diff = adaptivity->adajust_igi_level - IGI;
-
- th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
- th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
- } else {
- diff = igi_target - (s8)IGI;
- th_l2h_dmc = dm->th_l2h_ini + diff;
- if (th_l2h_dmc > 10 && dm->adaptivity_enable)
- th_l2h_dmc = 10;
-
- th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
-
- /*replace lower bound to prevent EDCCA always equal 1*/
- if (th_h2l_dmc < adaptivity->h2l_lb)
- th_h2l_dmc = adaptivity->h2l_lb;
- if (th_l2h_dmc < adaptivity->l2h_lb)
- th_l2h_dmc = adaptivity->l2h_lb;
- }
- ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
- "IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI,
- th_l2h_dmc, th_h2l_dmc);
- ODM_RT_TRACE(
- dm, PHYDM_COMP_ADAPTIVITY,
- "adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
- dm->adaptivity_igi_upper, adaptivity->h2l_lb,
- adaptivity->l2h_lb);
-
- phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
-
- if (dm->adaptivity_enable)
- odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);
-}
-
-/*This is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
-void phydm_pause_edcca(void *dm_void, bool is_pasue_edcca)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct adaptivity_statistics *adaptivity =
- (struct adaptivity_statistics *)phydm_get_structure(
- dm, PHYDM_ADAPTIVITY);
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- u8 IGI = dig_tab->cur_ig_value;
- s8 diff = 0;
-
- if (is_pasue_edcca) {
- adaptivity->is_stop_edcca = true;
-
- if (dm->support_ic_type &
- (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
- if (adaptivity->adajust_igi_level > IGI)
- diff = adaptivity->adajust_igi_level - IGI;
-
- adaptivity->backup_l2h =
- dm->th_l2h_ini - diff + adaptivity->igi_target;
- adaptivity->backup_h2l =
- adaptivity->backup_l2h - dm->th_edcca_hl_diff;
- } else {
- diff = adaptivity->igi_target - (s8)IGI;
- adaptivity->backup_l2h = dm->th_l2h_ini + diff;
- if (adaptivity->backup_l2h > 10)
- adaptivity->backup_l2h = 10;
-
- adaptivity->backup_h2l =
- adaptivity->backup_l2h - dm->th_edcca_hl_diff;
-
- /*replace lower bound to prevent EDCCA always equal 1*/
- if (adaptivity->backup_h2l < adaptivity->h2l_lb)
- adaptivity->backup_h2l = adaptivity->h2l_lb;
- if (adaptivity->backup_l2h < adaptivity->l2h_lb)
- adaptivity->backup_l2h = adaptivity->l2h_lb;
- }
- ODM_RT_TRACE(
- dm, PHYDM_COMP_ADAPTIVITY,
- "pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n",
- adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
-
- /*Disable EDCCA*/
- phydm_pause_edcca_work_item_callback(dm);
-
- } else {
- adaptivity->is_stop_edcca = false;
- ODM_RT_TRACE(
- dm, PHYDM_COMP_ADAPTIVITY,
- "resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n",
- adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
- /*Resume EDCCA*/
- phydm_resume_edcca_work_item_callback(dm);
- }
-}
-
-void phydm_pause_edcca_work_item_callback(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES)
- odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
- MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16));
- else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
- (u16)(0x7f | 0x7f << 8));
-}
-
-void phydm_resume_edcca_work_item_callback(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct adaptivity_statistics *adaptivity =
- (struct adaptivity_statistics *)phydm_get_structure(
- dm, PHYDM_ADAPTIVITY);
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES)
- odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
- MASKBYTE2 | MASKBYTE0,
- (u32)((u8)adaptivity->backup_l2h |
- (u8)adaptivity->backup_h2l << 16));
- else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
- (u16)((u8)adaptivity->backup_l2h |
- (u8)adaptivity->backup_h2l << 8));
-}
-
-void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct adaptivity_statistics *adaptivity =
- (struct adaptivity_statistics *)phydm_get_structure(
- dm, PHYDM_ADAPTIVITY);
- s8 th_l2h_dmc, th_h2l_dmc;
- s8 diff = 0, igi_target = 0x32;
-
- if (dm->support_ability & ODM_BB_ADAPTIVITY) {
- if (dm->support_ic_type &
- (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
- if (adaptivity->adajust_igi_level > IGI)
- diff = adaptivity->adajust_igi_level - IGI;
-
- th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
- th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
- } else {
- diff = igi_target - (s8)IGI;
- th_l2h_dmc = dm->th_l2h_ini + diff;
- if (th_l2h_dmc > 10)
- th_l2h_dmc = 10;
-
- th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
-
- /*replace lower bound to prevent EDCCA always equal 1*/
- if (th_h2l_dmc < adaptivity->h2l_lb)
- th_h2l_dmc = adaptivity->h2l_lb;
- if (th_l2h_dmc < adaptivity->l2h_lb)
- th_l2h_dmc = adaptivity->l2h_lb;
- }
- ODM_RT_TRACE(
- dm, PHYDM_COMP_ADAPTIVITY,
- "API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n",
- IGI, th_l2h_dmc, th_h2l_dmc);
- ODM_RT_TRACE(
- dm, PHYDM_COMP_ADAPTIVITY,
- "API :adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
- dm->adaptivity_igi_upper, adaptivity->h2l_lb,
- adaptivity->l2h_lb);
-
- phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMADAPTIVITY_H__
-#define __PHYDMADAPTIVITY_H__
-
-/*20160902 changed by Kevin, refine method for searching pwdb lower bound*/
-#define ADAPTIVITY_VERSION "9.3.5"
-
-#define pwdb_upper_bound 7
-#define dfir_loss 5
-
-enum phydm_adapinfo {
- PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
- PHYDM_ADAPINFO_DCBACKOFF,
- PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
- PHYDM_ADAPINFO_TH_L2H_INI,
- PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
- PHYDM_ADAPINFO_AP_NUM_TH
-
-};
-
-enum phydm_set_lna {
- phydm_disable_lna = 0,
- phydm_enable_lna = 1,
-};
-
-enum phydm_trx_mux_type {
- phydm_shutdown = 0,
- phydm_standby_mode = 1,
- phydm_tx_mode = 2,
- phydm_rx_mode = 3
-};
-
-enum phydm_mac_edcca_type {
- phydm_ignore_edcca = 0,
- phydm_dont_ignore_edcca = 1
-};
-
-struct adaptivity_statistics {
- s8 th_l2h_ini_backup;
- s8 th_edcca_hl_diff_backup;
- s8 igi_base;
- u8 igi_target;
- u8 nhm_wait;
- s8 h2l_lb;
- s8 l2h_lb;
- bool is_first_link;
- bool is_check;
- bool dynamic_link_adaptivity;
- u8 ap_num_th;
- u8 adajust_igi_level;
- bool acs_for_adaptivity;
- s8 backup_l2h;
- s8 backup_h2l;
- bool is_stop_edcca;
-};
-
-void phydm_pause_edcca(void *dm_void, bool is_pasue_edcca);
-
-void phydm_check_adaptivity(void *dm_void);
-
-void phydm_check_environment(void *dm_void);
-
-void phydm_nhm_counter_statistics_init(void *dm_void);
-
-void phydm_nhm_counter_statistics(void *dm_void);
-
-void phydm_nhm_counter_statistics_reset(void *dm_void);
-
-void phydm_get_nhm_counter_statistics(void *dm_void);
-
-void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state);
-
-void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H);
-
-void phydm_set_trx_mux(void *dm_void, enum phydm_trx_mux_type tx_mode,
- enum phydm_trx_mux_type rx_mode);
-
-bool phydm_cal_nhm_cnt(void *dm_void);
-
-void phydm_search_pwdb_lower_bound(void *dm_void);
-
-void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
- u32 value);
-
-void phydm_adaptivity_init(void *dm_void);
-
-void phydm_adaptivity(void *dm_void);
-
-void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI);
-
-void phydm_pause_edcca_work_item_callback(void *dm_void);
-
-void phydm_resume_edcca_work_item_callback(void *dm_void);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-static bool phydm_la_buffer_allocate(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
- bool ret = false;
-
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA mode BufferAllocate]\n");
-
- if (adc_smp_buf->length == 0) {
- odm_allocate_memory(dm, (void **)&adc_smp_buf->octet,
- adc_smp_buf->buffer_size);
- if (!adc_smp_buf->octet) {
- ret = false;
- } else {
- adc_smp_buf->length = adc_smp_buf->buffer_size;
- ret = true;
- }
- }
-
- return ret;
-}
-
-static void phydm_la_get_tx_pkt_buf(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
- u32 i = 0, value32, data_l = 0, data_h = 0;
- u32 addr, finish_addr;
- u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) -
- 1; /*end_addr = 0x3ffff;*/
- bool is_round_up;
- static u32 page = 0xFF;
- u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0;
-
- odm_memory_set(dm, adc_smp_buf->octet, 0, adc_smp_buf->length);
- odm_write_1byte(dm, 0x0106, 0x69);
-
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "GetTxPktBuf\n");
-
- value32 = odm_read_4byte(dm, 0x7c0);
- is_round_up = (bool)((value32 & BIT(31)) >> 31);
- /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
- finish_addr = (value32 & 0x7FFF0000) >> 16;
-
- if (is_round_up) {
- addr = (finish_addr + 1) << 3;
- ODM_RT_TRACE(
- dm, ODM_COMP_UNCOND,
- "is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n",
- is_round_up, finish_addr, value32);
- /*Byte to 64Byte*/
- smp_number = (adc_smp_buf->buffer_size) >> 3;
- } else {
- addr = adc_smp_buf->start_pos;
-
- addr_8byte = addr >> 3;
- if (addr_8byte > finish_addr)
- smp_number = addr_8byte - finish_addr;
- else
- smp_number = finish_addr - addr_8byte;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_UNCOND,
- "is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n",
- is_round_up, finish_addr, addr_8byte, smp_number);
- }
-
- if (dm->support_ic_type & ODM_RTL8197F) {
- /*64K byte*/
- for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) {
- if ((addr & 0xfff) == 0)
- odm_set_bb_reg(dm, 0x0140, MASKLWORD,
- 0x780 + (addr >> 12));
- data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
- MASKDWORD);
- data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
- MASKDWORD);
-
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
- data_l);
- }
- } else {
- while (addr != (finish_addr << 3)) {
- if (page != (addr >> 12)) {
- /*Reg140=0x780+(addr>>12),
- *addr=0x30~0x3F, total 16 pages
- */
- page = addr >> 12;
- }
- odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + page);
-
- /*pDataL = 0x8000+(addr&0xfff);*/
- data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
- MASKDWORD);
- data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
- MASKDWORD);
-
- adc_smp_buf->octet[i] = data_h;
- adc_smp_buf->octet[i + 1] = data_l;
-
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
- data_l);
-
- i = i + 2;
-
- if ((addr + 8) >= end_addr)
- addr = adc_smp_buf->start_pos;
- else
- addr = addr + 8;
-
- smp_cnt++;
- if (smp_cnt >= (smp_number - 1))
- break;
- }
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "smp_cnt = ((%d))\n",
- smp_cnt);
- }
-}
-
-static void phydm_la_mode_set_mac_iq_dump(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- u32 reg_value;
-
- odm_write_1byte(dm, 0x7c0, 0); /*clear all 0x7c0*/
- odm_set_mac_reg(dm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/
-
- if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) {
- adc_smp->is_bb_trigger = 0;
- odm_set_mac_reg(dm, 0x7c0, BIT(2),
- 1); /*polling bit for MAC mode*/
- odm_set_mac_reg(
- dm, 0x7c0, BIT(4) | BIT(3),
- adc_smp->la_trigger_edge); /*trigger mode for MAC*/
-
- ODM_RT_TRACE(
- dm, ODM_COMP_UNCOND,
- "[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n",
- adc_smp->la_mac_ref_mask, adc_smp->la_trig_sig_sel,
- adc_smp->la_dbg_port);
- /*[Set MAC Debug Port]*/
- odm_set_mac_reg(dm, 0xF4, BIT(16), 1);
- odm_set_mac_reg(dm, 0x38, 0xff0000, adc_smp->la_dbg_port);
- odm_set_mac_reg(dm, 0x7c4, MASKDWORD, adc_smp->la_mac_ref_mask);
- odm_set_mac_reg(dm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel);
-
- } else {
- adc_smp->is_bb_trigger = 1;
- odm_set_mac_reg(dm, 0x7c0, BIT(1),
- 1); /*polling bit for BB ADC mode*/
-
- if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
- odm_set_mac_reg(
- dm, 0x7c0, BIT(3),
- 1); /*polling bit for MAC trigger event*/
- odm_set_mac_reg(dm, 0x7c0, BIT(7) | BIT(6),
- adc_smp->la_trig_sig_sel);
-
- if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
- odm_set_mac_reg(
- dm, 0x7c0, BIT(5),
- 1); /* manual trigger 0x7C0[5] = 0->1*/
- }
- }
-
- reg_value = odm_get_bb_reg(dm, 0x7c0, 0xff);
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
-}
-
-static void phydm_la_mode_set_dma_type(void *dm_void, u8 la_dma_type)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "2. [LA mode DMA setting] Dma_type = ((%d))\n",
- la_dma_type);
-
- if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
- odm_set_bb_reg(dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
- else
- odm_set_bb_reg(dm, odm_adc_trigger_jaguar2, 0xf00,
- la_dma_type); /*0x95C[11:8]*/
-}
-
-static void phydm_adc_smp_start(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- u8 tmp_u1b;
- u8 while_cnt = 0;
- u8 polling_ok = false, target_polling_bit;
-
- phydm_la_mode_bb_setting(dm);
- phydm_la_mode_set_dma_type(dm, adc_smp->la_dma_type);
- phydm_la_mode_set_trigger_time(dm, adc_smp->la_trigger_time);
-
- if (dm->support_ic_type & ODM_RTL8197F) {
- odm_set_bb_reg(dm, 0xd00, BIT(26), 0x1);
- } else { /*for 8814A and 8822B?*/
- odm_write_1byte(dm, 0x198c, 0x7);
- odm_write_1byte(dm, 0x8b4, 0x80);
- /* odm_set_bb_reg(dm, 0x8b4, BIT(7), 1); */
- }
-
- phydm_la_mode_set_mac_iq_dump(dm);
- /* return; */
-
- target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
- do { /*Poll time always use 100ms, when it exceed 2s, break while loop*/
- tmp_u1b = odm_read_1byte(dm, 0x7c0);
-
- if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) {
- ODM_RT_TRACE(
- dm, ODM_COMP_UNCOND,
- "[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
- break;
-
- } else if (tmp_u1b & target_polling_bit) {
- ODM_delay_ms(100);
- while_cnt = while_cnt + 1;
- continue;
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "[LA Query OK] polling_bit=((0x%x))\n",
- target_polling_bit);
- polling_ok = true;
- if (dm->support_ic_type & ODM_RTL8197F)
- odm_set_bb_reg(dm, 0x7c0, BIT(0), 0x0);
- break;
- }
- } while (while_cnt < 20);
-
- if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
- if (polling_ok)
- phydm_la_get_tx_pkt_buf(dm);
- else
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "[Polling timeout]\n");
- }
-
- if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
- adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
-
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "[LA mode] LA_pattern_count = ((%d))\n",
- adc_smp->la_count);
-
- adc_smp_stop(dm);
-
- if (adc_smp->la_count == 0) {
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "LA Dump finished ---------->\n\n\n");
- /**/
- } else {
- adc_smp->la_count--;
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "LA Dump more ---------->\n\n\n");
- adc_smp_set(dm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel,
- adc_smp->la_dma_type, adc_smp->la_trigger_time, 0);
- }
-}
-
-void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
- u8 dma_data_sig_sel, u32 trigger_time, u16 polling_time)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- bool is_set_success = true;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
-
- adc_smp->la_trig_mode = trig_mode;
- adc_smp->la_trig_sig_sel = trig_sig_sel;
- adc_smp->la_dma_type = dma_data_sig_sel;
- adc_smp->la_trigger_time = trigger_time;
-
- if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
- is_set_success = false;
- else if (adc_smp->adc_smp_buf.length == 0)
- is_set_success = phydm_la_buffer_allocate(dm);
-
- if (is_set_success) {
- adc_smp->adc_smp_state = ADCSMP_STATE_SET;
-
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "[LA Set Success] LA_State=((%d))\n",
- adc_smp->adc_smp_state);
-
- phydm_adc_smp_start(dm);
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
- "[LA Set Fail] LA_State=((%d))\n",
- adc_smp->adc_smp_state);
- }
-}
-
-void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
- u32 used = *pused;
- u32 i;
-
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%s adc_smp_state %d", __func__,
- adc_smp->adc_smp_state);
-
- for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) {
- PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
- adc_smp_buf->octet[i],
- adc_smp_buf->octet[i + 1]);
- }
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\n");
- *pused = used;
-}
-
-s32 adc_smp_get_sample_counts(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
-
- return (adc_smp_buf->length >> 2) - 2;
-}
-
-s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
- u32 index)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
- u32 used = 0;
-
- if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Error: la data is not ready yet ...\n");
- return -1;
- }
-
- if (index < ((adc_smp_buf->length >> 2) - 2)) {
- PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
- adc_smp_buf->octet[index],
- adc_smp_buf->octet[index + 1]);
- }
- return 0;
-}
-
-void adc_smp_stop(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
-
- adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA_Stop] LA_state = ((%d))\n",
- adc_smp->adc_smp_state);
-}
-
-void adc_smp_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
-
- adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
-
- if (dm->support_ic_type & ODM_RTL8814A) {
- adc_smp_buf->start_pos = 0x30000;
- adc_smp_buf->buffer_size = 0x10000;
- } else if (dm->support_ic_type & ODM_RTL8822B) {
- adc_smp_buf->start_pos = 0x20000;
- adc_smp_buf->buffer_size = 0x20000;
- } else if (dm->support_ic_type & ODM_RTL8197F) {
- adc_smp_buf->start_pos = 0x00000;
- adc_smp_buf->buffer_size = 0x10000;
- } else if (dm->support_ic_type & ODM_RTL8821C) {
- adc_smp_buf->start_pos = 0x8000;
- adc_smp_buf->buffer_size = 0x8000;
- }
-}
-
-void adc_smp_de_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
-
- adc_smp_stop(dm);
-
- if (adc_smp_buf->length != 0x0) {
- odm_free_memory(dm, adc_smp_buf->octet, adc_smp_buf->length);
- adc_smp_buf->length = 0x0;
- }
-}
-
-void phydm_la_mode_bb_setting(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
-
- u8 trig_mode = adc_smp->la_trig_mode;
- u32 trig_sig_sel = adc_smp->la_trig_sig_sel;
- u32 dbg_port = adc_smp->la_dbg_port;
- u8 is_trigger_edge = adc_smp->la_trigger_edge;
- u8 sampling_rate = adc_smp->la_smp_rate;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_UNCOND,
- "1. [LA mode bb_setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n",
- trig_mode, dbg_port, is_trigger_edge, sampling_rate,
- trig_sig_sel);
-
- if (trig_mode == PHYDM_MAC_TRIG)
- trig_sig_sel = 0; /*ignore this setting*/
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- if (trig_mode == PHYDM_ADC_RF0_TRIG) {
- /*DBGOUT_RFC_a[31:0]*/
- odm_set_bb_reg(dm, 0x8f8,
- BIT(25) | BIT(24) | BIT(23) | BIT(22),
- 9);
- } else if (trig_mode == PHYDM_ADC_RF1_TRIG) {
- /*DBGOUT_RFC_b[31:0]*/
- odm_set_bb_reg(dm, 0x8f8,
- BIT(25) | BIT(24) | BIT(23) | BIT(22),
- 8);
- } else {
- odm_set_bb_reg(dm, 0x8f8,
- BIT(25) | BIT(24) | BIT(23) | BIT(22),
- 0);
- }
- /*
- * (0:) '{ofdm_dbg[31:0]}'
- * (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'
- * (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'
- * (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'
- * (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'
- * (5:) '{dbg_iqk_anta}'
- * (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'
- * (7:) '{dbg_iqk_antb}'
- * (8:) '{DBGOUT_RFC_b[31:0]}'
- * (9:) '{DBGOUT_RFC_a[31:0]}'
- * (a:) '{dbg_ofdm}'
- * (b:) '{dbg_cck}'
- */
-
- /*disable dbg clk gating*/
- odm_set_bb_reg(dm, 0x198C, BIT(2) | BIT(1) | BIT(0), 7);
-
- /*0x95C[4:0], BB debug port bit*/
- odm_set_bb_reg(dm, 0x95C, 0x1f, trig_sig_sel);
- odm_set_bb_reg(dm, 0x8FC, MASKDWORD, dbg_port);
- /*0: posedge, 1: negedge*/
- odm_set_bb_reg(dm, 0x95C, BIT(31), is_trigger_edge);
- odm_set_bb_reg(dm, 0x95c, 0xe0, sampling_rate);
- /* (0:) '80MHz'
- * (1:) '40MHz'
- * (2:) '20MHz'
- * (3:) '10MHz'
- * (4:) '5MHz'
- * (5:) '2.5MHz'
- * (6:) '1.25MHz'
- * (7:) '160MHz (for BW160 ic)'
- */
- } else {
- /*0x9A0[4:0], BB debug port bit*/
- odm_set_bb_reg(dm, 0x9a0, 0x1f, trig_sig_sel);
- odm_set_bb_reg(dm, 0x908, MASKDWORD, dbg_port);
- /*0: posedge, 1: negedge*/
- odm_set_bb_reg(dm, 0x9A0, BIT(31), is_trigger_edge);
- odm_set_bb_reg(dm, 0x9A0, 0xe0, sampling_rate);
- /* (0:) '80MHz'
- * (1:) '40MHz'
- * (2:) '20MHz'
- * (3:) '10MHz'
- * (4:) '5MHz'
- * (5:) '2.5MHz'
- * (6:) '1.25MHz'
- * (7:) '160MHz (for BW160 ic)'
- */
- }
-}
-
-void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 trigger_time_unit_num;
- u32 time_unit = 0;
-
- if (trigger_time_mu_sec < 128)
- time_unit = 0; /*unit: 1mu sec*/
- else if (trigger_time_mu_sec < 256)
- time_unit = 1; /*unit: 2mu sec*/
- else if (trigger_time_mu_sec < 512)
- time_unit = 2; /*unit: 4mu sec*/
- else if (trigger_time_mu_sec < 1024)
- time_unit = 3; /*unit: 8mu sec*/
- else if (trigger_time_mu_sec < 2048)
- time_unit = 4; /*unit: 16mu sec*/
- else if (trigger_time_mu_sec < 4096)
- time_unit = 5; /*unit: 32mu sec*/
- else if (trigger_time_mu_sec < 8192)
- time_unit = 6; /*unit: 64mu sec*/
-
- trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_UNCOND,
- "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
- trigger_time_unit_num, time_unit);
-
- odm_set_mac_reg(dm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
- odm_set_mac_reg(dm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
-}
-
-void phydm_lamode_trigger_setting(void *dm_void, char input[][16], u32 *_used,
- char *output, u32 *_out_len, u32 input_num)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- u8 trig_mode, dma_data_sig_sel;
- u32 trig_sig_sel;
- bool is_enable_la_mode;
- u32 trigger_time_mu_sec;
- char help[] = "-h";
- u32 var1[10] = {0};
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
- is_enable_la_mode = (bool)var1[0];
- /*dbg_print("echo cmd input_num = %d\n", input_num);*/
-
- if ((strcmp(input[1], help) == 0)) {
- PHYDM_SNPRINTF(output + used,
- out_len - used,
- "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC}\n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime}\n {polling_time/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n");
- } else if (is_enable_la_mode) {
- PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
-
- trig_mode = (u8)var1[1];
-
- if (trig_mode == PHYDM_MAC_TRIG)
- PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
- else
- PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
- trig_sig_sel = var1[2];
-
- PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
- PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
- PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
- PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
- PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
- PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
- PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
-
- dma_data_sig_sel = (u8)var1[3];
- trigger_time_mu_sec = var1[4]; /* unit: us */
-
- adc_smp->la_mac_ref_mask = var1[5];
- adc_smp->la_dbg_port = var1[6];
- adc_smp->la_trigger_edge = (u8)var1[7];
- adc_smp->la_smp_rate = (u8)(var1[8] & 0x7);
- adc_smp->la_count = var1[9];
-
- ODM_RT_TRACE(
- dm, ODM_COMP_UNCOND,
- "echo lamode %d %d %d %d %d %d %x %d %d %d\n",
- var1[0], var1[1], var1[2], var1[3], var1[4],
- var1[5], var1[6], var1[7], var1[8], var1[9]);
-
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
- trig_mode, trig_sig_sel, dma_data_sig_sel);
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
- trigger_time_mu_sec, adc_smp->la_mac_ref_mask,
- adc_smp->la_dbg_port);
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
- adc_smp->la_trigger_edge,
- (80 >> adc_smp->la_smp_rate),
- adc_smp->la_count);
-
- adc_smp_set(dm, trig_mode, trig_sig_sel,
- dma_data_sig_sel, trigger_time_mu_sec, 0);
-
- } else {
- adc_smp_stop(dm);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Disable LA mode\n");
- }
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __INC_ADCSMP_H
-#define __INC_ADCSMP_H
-
-#define DYNAMIC_LA_MODE "1.0" /*2016.07.15 Dino */
-
-struct rt_adcsmp_string {
- u32 *octet;
- u32 length;
- u32 buffer_size;
- u32 start_pos;
-};
-
-enum rt_adcsmp_trig_sel {
- PHYDM_ADC_BB_TRIG = 0,
- PHYDM_ADC_MAC_TRIG = 1,
- PHYDM_ADC_RF0_TRIG = 2,
- PHYDM_ADC_RF1_TRIG = 3,
- PHYDM_MAC_TRIG = 4
-};
-
-enum rt_adcsmp_trig_sig_sel {
- ADCSMP_TRIG_CRCOK = 0,
- ADCSMP_TRIG_CRCFAIL = 1,
- ADCSMP_TRIG_CCA = 2,
- ADCSMP_TRIG_REG = 3
-};
-
-enum rt_adcsmp_state {
- ADCSMP_STATE_IDLE = 0,
- ADCSMP_STATE_SET = 1,
- ADCSMP_STATE_QUERY = 2
-};
-
-struct rt_adcsmp {
- struct rt_adcsmp_string adc_smp_buf;
- enum rt_adcsmp_state adc_smp_state;
- u8 la_trig_mode;
- u32 la_trig_sig_sel;
- u8 la_dma_type;
- u32 la_trigger_time;
- u32 la_mac_ref_mask;
- u32 la_dbg_port;
- u8 la_trigger_edge;
- u8 la_smp_rate;
- u32 la_count;
- u8 is_bb_trigger;
- u8 la_work_item_index;
-};
-
-void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
- u8 dma_data_sig_sel, u32 trigger_time, u16 polling_time);
-
-void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused);
-
-s32 adc_smp_get_sample_counts(void *dm_void);
-
-s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
- u32 index);
-
-void adc_smp_stop(void *dm_void);
-
-void adc_smp_init(void *dm_void);
-
-void adc_smp_de_init(void *dm_void);
-
-void phydm_la_mode_bb_setting(void *dm_void);
-
-void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec);
-
-void phydm_lamode_trigger_setting(void *dm_void, char input[][16], u32 *_used,
- char *output, u32 *_out_len, u32 input_num);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-/* ******************************************************
- * when antenna test utility is on or some testing need to disable antenna
- * diversity, call this function to disable all ODM related mechanisms which
- * will switch antenna.
- * *******************************************************/
-void odm_stop_antenna_switch_dm(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- /* disable ODM antenna diversity */
- dm->support_ability &= ~ODM_BB_ANT_DIV;
- ODM_RT_TRACE(dm, ODM_COMP_ANT_DIV, "STOP Antenna Diversity\n");
-}
-
-void phydm_enable_antenna_diversity(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- dm->support_ability |= ODM_BB_ANT_DIV;
- ODM_RT_TRACE(dm, ODM_COMP_ANT_DIV,
- "AntDiv is enabled & Re-Init AntDiv\n");
- odm_antenna_diversity_init(dm);
-}
-
-void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
- )
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type == ODM_RTL8723B) {
- if (ant_setting == 0) /* ant A*/
- odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000000);
- else if (ant_setting == 1)
- odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000280);
- } else if (dm->support_ic_type == ODM_RTL8723D) {
- if (ant_setting == 0) /* ant A*/
- odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0000);
- else if (ant_setting == 1)
- odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0280);
- }
-}
-
-/* ****************************************************** */
-
-void odm_sw_ant_div_rest_after_link(void *dm_void) {}
-
-void odm_ant_div_reset(void *dm_void) {}
-
-void odm_antenna_diversity_init(void *dm_void) {}
-
-void odm_antenna_diversity(void *dm_void) {}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMANTDIV_H__
-#define __PHYDMANTDIV_H__
-
-/* 2.0 2014.11.04
- * 2.1 2015.01.13 Dino
- * 2.2 2015.01.16 Dino
- * 3.1 2015.07.29 YuChen, remove 92c 92d 8723a
- * 3.2 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B
- * 3.3 2015.08.12 Stanley. 8723B does not need to check the antenna is control
- * by BT, because antenna diversity only works when BT is disable
- * or radio off
- * 3.4 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna
- * Diversity
- * 3.5 2015.10.07 Stanley Always check antenna detection result from BT-coex.
- * for 8723B, not from PHYDM
- * 3.6 2015.11.16 Stanley
- * 3.7 2015.11.20 Dino Add SmartAnt FAT Patch
- * 3.8 2015.12.21 Dino, Add SmartAnt dynamic training packet num
- * 3.9 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and
- * add cmd for adjust truth table
- */
-#define ANTDIV_VERSION "3.9"
-
-/* 1 ============================================================
- * 1 Definition
- * 1 ============================================================
- */
-
-#define ANTDIV_INIT 0xff
-#define MAIN_ANT 1 /*ant A or ant Main or S1*/
-#define AUX_ANT 2 /*AntB or ant Aux or S0*/
-#define MAX_ANT 3 /* 3 for AP using*/
-
-#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D,
- * TX fixed at S1
- */
-#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D,
- * TX fixed at S1
- */
-/*smart antenna*/
-#define SUPPORT_RF_PATH_NUM 4
-#define SUPPORT_BEAM_PATTERN_NUM 4
-#define NUM_ANTENNA_8821A 2
-
-#define SUPPORT_BEAM_SET_PATTERN_NUM 8
-
-#define NO_FIX_TX_ANT 0
-#define FIX_TX_AT_MAIN 1
-#define FIX_AUX_AT_MAIN 2
-
-/* Antenna Diversty Control type */
-#define ODM_AUTO_ANT 0
-#define ODM_FIX_MAIN_ANT 1
-#define ODM_FIX_AUX_ANT 2
-
-#define ODM_N_ANTDIV_SUPPORT \
- (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | \
- ODM_RTL8723D | ODM_RTL8195A)
-#define ODM_AC_ANTDIV_SUPPORT \
- (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | \
- ODM_RTL8822B | ODM_RTL8814B)
-#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
-#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
-#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
-
-#define ODM_ANTDIV_2G_SUPPORT_IC \
- (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | \
- ODM_RTL8188F | ODM_RTL8723D)
-#define ODM_ANTDIV_5G_SUPPORT_IC \
- (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
-
-#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
-
-#define ODM_ANTDIV_2G BIT(0)
-#define ODM_ANTDIV_5G BIT(1)
-
-#define ANTDIV_ON 1
-#define ANTDIV_OFF 0
-
-#define FAT_ON 1
-#define FAT_OFF 0
-
-#define TX_BY_DESC 1
-#define TX_BY_REG 0
-
-#define RSSI_METHOD 0
-#define EVM_METHOD 1
-#define CRC32_METHOD 2
-
-#define INIT_ANTDIV_TIMMER 0
-#define CANCEL_ANTDIV_TIMMER 1
-#define RELEASE_ANTDIV_TIMMER 2
-
-#define CRC32_FAIL 1
-#define CRC32_OK 0
-
-#define evm_rssi_th_high 25
-#define evm_rssi_th_low 20
-
-#define NORMAL_STATE_MIAN 1
-#define NORMAL_STATE_AUX 2
-#define TRAINING_STATE 3
-
-#define FORCE_RSSI_DIFF 10
-
-#define CSI_ON 1
-#define CSI_OFF 0
-
-#define DIVON_CSIOFF 1
-#define DIVOFF_CSION 2
-
-#define BDC_DIV_TRAIN_STATE 0
-#define bdc_bfer_train_state 1
-#define BDC_DECISION_STATE 2
-#define BDC_BF_HOLD_STATE 3
-#define BDC_DIV_HOLD_STATE 4
-
-#define BDC_MODE_1 1
-#define BDC_MODE_2 2
-#define BDC_MODE_3 3
-#define BDC_MODE_4 4
-#define BDC_MODE_NULL 0xff
-
-/*SW S0S1 antenna diversity*/
-#define SWAW_STEP_INIT 0xff
-#define SWAW_STEP_PEEK 0
-#define SWAW_STEP_DETERMINE 1
-
-#define RSSI_CHECK_RESET_PERIOD 10
-#define RSSI_CHECK_THRESHOLD 50
-
-/*Hong Lin Smart antenna*/
-#define HL_SMTANT_2WIRE_DATA_LEN 24
-
-/* 1 ============================================================
- * 1 structure
- * 1 ============================================================
- */
-
-struct sw_antenna_switch {
- u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD",
- *than check this antenna again
- */
- u8 try_flag;
- s32 pre_rssi;
- u8 cur_antenna;
- u8 pre_antenna;
- u8 rssi_trying;
- u8 reset_idx;
- u8 train_time;
- u8 train_time_flag; /*base on RSSI difference between two antennas*/
- struct timer_list phydm_sw_antenna_switch_timer;
- u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
- bool is_sw_ant_div_by_ctrl_frame;
-
- /* AntDect (Before link Antenna Switch check) need to be moved*/
- u16 single_ant_counter;
- u16 dual_ant_counter;
- u16 aux_fail_detec_counter;
- u16 retry_counter;
- u8 swas_no_link_state;
- u32 swas_no_link_bk_reg948;
- bool ANTA_ON; /*To indicate ant A is or not*/
- bool ANTB_ON; /*To indicate ant B is on or not*/
- bool pre_aux_fail_detec;
- bool rssi_ant_dect_result;
- u8 ant_5g;
- u8 ant_2g;
-};
-
-struct fast_antenna_training {
- u8 bssid[6];
- u8 antsel_rx_keep_0;
- u8 antsel_rx_keep_1;
- u8 antsel_rx_keep_2;
- u8 antsel_rx_keep_3;
- u32 ant_sum_rssi[7];
- u32 ant_rssi_cnt[7];
- u32 ant_ave_rssi[7];
- u8 fat_state;
- u32 train_idx;
- u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
- u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
- u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
- u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
- u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
- u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
- u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
- u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
- u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
- u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
- u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
- u8 rx_idle_ant;
- u8 ant_div_on_off;
- bool is_become_linked;
- u32 min_max_rssi;
- u8 idx_ant_div_counter_2g;
- u8 idx_ant_div_counter_5g;
- u8 ant_div_2g_5g;
-
- u32 cck_ctrl_frame_cnt_main;
- u32 cck_ctrl_frame_cnt_aux;
- u32 ofdm_ctrl_frame_cnt_main;
- u32 ofdm_ctrl_frame_cnt_aux;
- u32 main_ant_ctrl_frame_sum;
- u32 aux_ant_ctrl_frame_sum;
- u32 main_ant_ctrl_frame_cnt;
- u32 aux_ant_ctrl_frame_cnt;
- u8 b_fix_tx_ant;
- bool fix_ant_bfee;
- bool enable_ctrl_frame_antdiv;
- bool use_ctrl_frame_antdiv;
- u8 hw_antsw_occur;
- u8 *p_force_tx_ant_by_desc;
- u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's
- *outer parameter later
- */
- u8 *p_default_s0_s1;
- u8 default_s0_s1;
-};
-
-/* 1 ============================================================
- * 1 enumeration
- * 1 ============================================================
- */
-
-/*Fast antenna training*/
-enum fat_state {
- FAT_BEFORE_LINK_STATE = 0,
- FAT_PREPARE_STATE = 1,
- FAT_TRAINING_STATE = 2,
- FAT_DECISION_STATE = 3
-};
-
-enum ant_div_type {
- NO_ANTDIV = 0xFF,
- CG_TRX_HW_ANTDIV = 0x01,
- CGCS_RX_HW_ANTDIV = 0x02,
- FIXED_HW_ANTDIV = 0x03,
- CG_TRX_SMART_ANTDIV = 0x04,
- CGCS_RX_SW_ANTDIV = 0x05,
- /*8723B intrnal switch S0 S1*/
- S0S1_SW_ANTDIV = 0x06,
- /*TRX S0S1 diversity for 8723D*/
- S0S1_TRX_HW_ANTDIV = 0x07,
- /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and
- *each ant. is equipped with 4 antenna patterns
- */
- HL_SW_SMART_ANT_TYPE1 = 0x10,
- /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
- HL_SW_SMART_ANT_TYPE2 = 0x11,
-};
-
-/* 1 ============================================================
- * 1 function prototype
- * 1 ============================================================
- */
-
-void odm_stop_antenna_switch_dm(void *dm_void);
-
-void phydm_enable_antenna_diversity(void *dm_void);
-
-void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
- );
-
-#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
-
-void odm_sw_ant_div_rest_after_link(void *dm_void);
-
-void odm_ant_div_reset(void *dm_void);
-
-void odm_antenna_diversity_init(void *dm_void);
-
-void odm_antenna_diversity(void *dm_void);
-
-#endif /*#ifndef __ODMANTDIV_H__*/
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __INC_PHYDM_BEAMFORMING_H
-#define __INC_PHYDM_BEAMFORMING_H
-
-/*Beamforming Related*/
-#include "txbf/halcomtxbf.h"
-#include "txbf/haltxbfjaguar.h"
-#include "txbf/haltxbf8822b.h"
-#include "txbf/haltxbfinterface.h"
-
-#define beamforming_gid_paid(adapter, tcb)
-#define phydm_acting_determine(dm, type) false
-#define beamforming_enter(dm, sta_idx)
-#define beamforming_leave(dm, RA)
-#define beamforming_end_fw(dm)
-#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
-#define beamforming_control_v2(dm, idx, mode, BW, period) true
-#define phydm_beamforming_end_sw(dm, _status)
-#define beamforming_timer_callback(dm)
-#define phydm_beamforming_init(dm)
-#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
-#define beamforming_watchdog(dm)
-#define phydm_beamforming_watchdog(dm)
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-/*Set NHM period, threshold, disable ignore cca or not,
- *disable ignore txon or not
- */
-void phydm_nhm_setting(void *dm_void, u8 nhm_setting)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ccx_info *ccx_info = &dm->dm_ccx_info;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- if (nhm_setting == SET_NHM_SETTING) {
- /*Set inexclude_cca, inexclude_txon*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
- ccx_info->nhm_inexclude_cca);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
- ccx_info->nhm_inexclude_txon);
-
- /*Set NHM period*/
- odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
- ccx_info->NHM_period);
-
- /*Set NHM threshold*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
- MASKBYTE0, ccx_info->NHM_th[0]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
- MASKBYTE1, ccx_info->NHM_th[1]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
- MASKBYTE2, ccx_info->NHM_th[2]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
- MASKBYTE3, ccx_info->NHM_th[3]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
- MASKBYTE0, ccx_info->NHM_th[4]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
- MASKBYTE1, ccx_info->NHM_th[5]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
- MASKBYTE2, ccx_info->NHM_th[6]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
- MASKBYTE3, ccx_info->NHM_th[7]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
- ccx_info->NHM_th[8]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
- ccx_info->NHM_th[9]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
- ccx_info->NHM_th[10]);
-
- /*CCX EN*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8),
- CCX_EN);
- } else if (nhm_setting == STORE_NHM_SETTING) {
- /*Store prev. disable_ignore_cca, disable_ignore_txon*/
- ccx_info->NHM_inexclude_cca_restore =
- (enum nhm_inexclude_cca)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9));
- ccx_info->NHM_inexclude_txon_restore =
- (enum nhm_inexclude_txon)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10));
-
- /*Store pervious NHM period*/
- ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
- dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD);
-
- /*Store NHM threshold*/
- ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0);
- ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1);
- ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2);
- ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3);
- ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0);
- ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1);
- ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2);
- ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3);
- ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0);
- ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2);
- ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3);
- } else if (nhm_setting == RESTORE_NHM_SETTING) {
- /*Set disable_ignore_cca, disable_ignore_txon*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
- ccx_info->NHM_inexclude_cca_restore);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
- ccx_info->NHM_inexclude_txon_restore);
-
- /*Set NHM period*/
- odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
- ccx_info->NHM_period);
-
- /*Set NHM threshold*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
- MASKBYTE0, ccx_info->NHM_th_restore[0]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
- MASKBYTE1, ccx_info->NHM_th_restore[1]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
- MASKBYTE2, ccx_info->NHM_th_restore[2]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
- MASKBYTE3, ccx_info->NHM_th_restore[3]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
- MASKBYTE0, ccx_info->NHM_th_restore[4]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
- MASKBYTE1, ccx_info->NHM_th_restore[5]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
- MASKBYTE2, ccx_info->NHM_th_restore[6]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
- MASKBYTE3, ccx_info->NHM_th_restore[7]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
- ccx_info->NHM_th_restore[8]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
- ccx_info->NHM_th_restore[9]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
- ccx_info->NHM_th_restore[10]);
- } else {
- return;
- }
- }
-
- else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- if (nhm_setting == SET_NHM_SETTING) {
- /*Set disable_ignore_cca, disable_ignore_txon*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
- ccx_info->nhm_inexclude_cca);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
- ccx_info->nhm_inexclude_txon);
-
- /*Set NHM period*/
- odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
- ccx_info->NHM_period);
-
- /*Set NHM threshold*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
- MASKBYTE0, ccx_info->NHM_th[0]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
- MASKBYTE1, ccx_info->NHM_th[1]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
- MASKBYTE2, ccx_info->NHM_th[2]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
- MASKBYTE3, ccx_info->NHM_th[3]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
- MASKBYTE0, ccx_info->NHM_th[4]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
- MASKBYTE1, ccx_info->NHM_th[5]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
- MASKBYTE2, ccx_info->NHM_th[6]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
- MASKBYTE3, ccx_info->NHM_th[7]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
- ccx_info->NHM_th[8]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
- ccx_info->NHM_th[9]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
- ccx_info->NHM_th[10]);
-
- /*CCX EN*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(8),
- CCX_EN);
- } else if (nhm_setting == STORE_NHM_SETTING) {
- /*Store prev. disable_ignore_cca, disable_ignore_txon*/
- ccx_info->NHM_inexclude_cca_restore =
- (enum nhm_inexclude_cca)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9));
- ccx_info->NHM_inexclude_txon_restore =
- (enum nhm_inexclude_txon)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10));
-
- /*Store pervious NHM period*/
- ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
- dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD);
-
- /*Store NHM threshold*/
- ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0);
- ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1);
- ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2);
- ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3);
- ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0);
- ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1);
- ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2);
- ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3);
- ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH8_11N, MASKBYTE0);
- ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2);
- ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
- dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3);
- } else if (nhm_setting == RESTORE_NHM_SETTING) {
- /*Set disable_ignore_cca, disable_ignore_txon*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
- ccx_info->NHM_inexclude_cca_restore);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
- ccx_info->NHM_inexclude_txon_restore);
-
- /*Set NHM period*/
- odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
- ccx_info->NHM_period_restore);
-
- /*Set NHM threshold*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
- MASKBYTE0, ccx_info->NHM_th_restore[0]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
- MASKBYTE1, ccx_info->NHM_th_restore[1]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
- MASKBYTE2, ccx_info->NHM_th_restore[2]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
- MASKBYTE3, ccx_info->NHM_th_restore[3]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
- MASKBYTE0, ccx_info->NHM_th_restore[4]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
- MASKBYTE1, ccx_info->NHM_th_restore[5]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
- MASKBYTE2, ccx_info->NHM_th_restore[6]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
- MASKBYTE3, ccx_info->NHM_th_restore[7]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
- ccx_info->NHM_th_restore[8]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
- ccx_info->NHM_th_restore[9]);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
- ccx_info->NHM_th_restore[10]);
- } else {
- return;
- }
- }
-}
-
-void phydm_nhm_trigger(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- /*Trigger NHM*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
- } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- /*Trigger NHM*/
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
- odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
- }
-}
-
-void phydm_get_nhm_result(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 value32;
- struct ccx_info *ccx_info = &dm->dm_ccx_info;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC);
- ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
- ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
- ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
- ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
-
- value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
- ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
- ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
- ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
- ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
-
- value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT11_TO_CNT8_11AC);
- ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0);
- ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8);
- ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
- ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
-
- /*Get NHM duration*/
- value32 = odm_read_4byte(dm, ODM_REG_NHM_DUR_READY_11AC);
- ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
- }
-
- else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N);
- ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
- ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
- ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
- ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
-
- value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
- ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
- ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
- ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
- ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
-
- value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT9_TO_CNT8_11N);
- ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16);
- ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24);
-
- value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
- ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
- ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
-
- /* Get NHM duration */
- value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
- ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
- }
-}
-
-bool phydm_check_nhm_ready(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 value32 = 0;
- u8 i;
- bool ret = false;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- value32 = odm_get_bb_reg(dm,
- ODM_REG_CLM_RESULT_11AC,
- MASKDWORD);
-
- for (i = 0; i < 200; i++) {
- ODM_delay_ms(1);
- if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
- BIT(17))) {
- ret = true;
- break;
- }
- }
- }
-
- else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- value32 = odm_get_bb_reg(dm, ODM_REG_CLM_READY_11N, MASKDWORD);
-
- for (i = 0; i < 200; i++) {
- ODM_delay_ms(1);
- if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
- BIT(17))) {
- ret = true;
- break;
- }
- }
- }
- return ret;
-}
-
-void phydm_clm_setting(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ccx_info *ccx_info = &dm->dm_ccx_info;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD,
- ccx_info->CLM_period); /*4us sample 1 time*/
- odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(8),
- 0x1); /*Enable CCX for CLM*/
-
- } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKLWORD,
- ccx_info->CLM_period); /*4us sample 1 time*/
- odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(8),
- 0x1); /*Enable CCX for CLM*/
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM period = %dus\n", __func__,
- ccx_info->CLM_period * 4);
-}
-
-void phydm_clm_trigger(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0),
- 0x0); /*Trigger CLM*/
- odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0), 0x1);
- } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0),
- 0x0); /*Trigger CLM*/
- odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0), 0x1);
- }
-}
-
-bool phydm_check_cl_mready(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 value32 = 0;
- bool ret = false;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- value32 = odm_get_bb_reg(
- dm, ODM_REG_CLM_RESULT_11AC,
- MASKDWORD); /*make sure CLM calc is ready*/
- else if (dm->support_ic_type & ODM_IC_11N_SERIES)
- value32 = odm_get_bb_reg(
- dm, ODM_REG_CLM_READY_11N,
- MASKDWORD); /*make sure CLM calc is ready*/
-
- if ((dm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16)))
- ret = true;
- else if ((dm->support_ic_type & ODM_IC_11N_SERIES) &&
- (value32 & BIT(16)))
- ret = true;
- else
- ret = false;
-
- ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM ready = %d\n", __func__,
- ret);
-
- return ret;
-}
-
-void phydm_get_cl_mresult(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ccx_info *ccx_info = &dm->dm_ccx_info;
-
- u32 value32 = 0;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC,
- MASKDWORD); /*read CLM calc result*/
- else if (dm->support_ic_type & ODM_IC_11N_SERIES)
- value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11N,
- MASKDWORD); /*read CLM calc result*/
-
- ccx_info->CLM_result = (u16)(value32 & MASKLWORD);
-
- ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM result = %dus\n", __func__,
- ccx_info->CLM_result * 4);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __PHYDMCCX_H__
-#define __PHYDMCCX_H__
-
-#define CCX_EN 1
-
-#define SET_NHM_SETTING 0
-#define STORE_NHM_SETTING 1
-#define RESTORE_NHM_SETTING 2
-
-enum nhm_inexclude_cca { NHM_EXCLUDE_CCA, NHM_INCLUDE_CCA };
-
-enum nhm_inexclude_txon { NHM_EXCLUDE_TXON, NHM_INCLUDE_TXON };
-
-struct ccx_info {
- /*Settings*/
- u8 NHM_th[11];
- u16 NHM_period; /* 4us per unit */
- u16 CLM_period; /* 4us per unit */
- enum nhm_inexclude_txon nhm_inexclude_txon;
- enum nhm_inexclude_cca nhm_inexclude_cca;
-
- /*Previous Settings*/
- u8 NHM_th_restore[11];
- u16 NHM_period_restore; /* 4us per unit */
- u16 CLM_period_restore; /* 4us per unit */
- enum nhm_inexclude_txon NHM_inexclude_txon_restore;
- enum nhm_inexclude_cca NHM_inexclude_cca_restore;
-
- /*Report*/
- u8 NHM_result[12];
- u16 NHM_duration;
- u16 CLM_result;
-
- bool echo_NHM_en;
- bool echo_CLM_en;
- u8 echo_IGI;
-};
-
-/*NHM*/
-
-void phydm_nhm_setting(void *dm_void, u8 nhm_setting);
-
-void phydm_nhm_trigger(void *dm_void);
-
-void phydm_get_nhm_result(void *dm_void);
-
-bool phydm_check_nhm_ready(void *dm_void);
-
-/*CLM*/
-
-void phydm_clm_setting(void *dm_void);
-
-void phydm_clm_trigger(void *dm_void);
-
-bool phydm_check_cl_mready(void *dm_void);
-
-void phydm_get_cl_mresult(void *dm_void);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-static void odm_set_crystal_cap(void *dm_void, u8 crystal_cap)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct cfo_tracking *cfo_track =
- (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
-
- if (cfo_track->crystal_cap == crystal_cap)
- return;
-
- cfo_track->crystal_cap = crystal_cap;
-
- if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
- /* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
- crystal_cap = crystal_cap & 0x3F;
- odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x007ff800,
- (crystal_cap | (crystal_cap << 6)));
- } else if (dm->support_ic_type & ODM_RTL8812) {
- /* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
- crystal_cap = crystal_cap & 0x3F;
- odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x7FF80000,
- (crystal_cap | (crystal_cap << 6)));
- } else if ((dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B |
- ODM_RTL8192E | ODM_RTL8821))) {
- /* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */
- crystal_cap = crystal_cap & 0x3F;
- odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x00FFF000,
- (crystal_cap | (crystal_cap << 6)));
- } else if (dm->support_ic_type & ODM_RTL8814A) {
- /* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
- crystal_cap = crystal_cap & 0x3F;
- odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x07FF8000,
- (crystal_cap | (crystal_cap << 6)));
- } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
- /* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
- crystal_cap = crystal_cap & 0x3F;
- odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
- odm_set_bb_reg(dm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "%s(): Use default setting.\n", __func__);
- odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000,
- (crystal_cap | (crystal_cap << 6)));
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING, "%s(): crystal_cap = 0x%x\n",
- __func__, crystal_cap);
-
- /* JJ modified 20161115 */
-}
-
-static u8 odm_get_default_crytaltal_cap(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 crystal_cap = 0x20;
-
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
-
- crystal_cap = rtlefuse->crystalcap;
-
- crystal_cap = crystal_cap & 0x3f;
-
- return crystal_cap;
-}
-
-static void odm_set_atc_status(void *dm_void, bool atc_status)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct cfo_tracking *cfo_track =
- (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
-
- if (cfo_track->is_atc_status == atc_status)
- return;
-
- odm_set_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm),
- atc_status);
- cfo_track->is_atc_status = atc_status;
-}
-
-static bool odm_get_atc_status(void *dm_void)
-{
- bool atc_status;
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- atc_status = (bool)odm_get_bb_reg(dm, ODM_REG(BB_ATC, dm),
- ODM_BIT(BB_ATC, dm));
- return atc_status;
-}
-
-void odm_cfo_tracking_reset(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct cfo_tracking *cfo_track =
- (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
-
- cfo_track->def_x_cap = odm_get_default_crytaltal_cap(dm);
- cfo_track->is_adjust = true;
-
- if (cfo_track->crystal_cap > cfo_track->def_x_cap) {
- odm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "%s(): approch default value (0x%x)\n", __func__,
- cfo_track->crystal_cap);
- } else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {
- odm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "%s(): approch default value (0x%x)\n", __func__,
- cfo_track->crystal_cap);
- }
-
- odm_set_atc_status(dm, true);
-}
-
-void odm_cfo_tracking_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct cfo_tracking *cfo_track =
- (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
-
- cfo_track->crystal_cap = odm_get_default_crytaltal_cap(dm);
- cfo_track->def_x_cap = cfo_track->crystal_cap;
- cfo_track->is_atc_status = odm_get_atc_status(dm);
- cfo_track->is_adjust = true;
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING, "%s()=========>\n", __func__);
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "%s(): is_atc_status = %d, crystal_cap = 0x%x\n", __func__,
- cfo_track->is_atc_status, cfo_track->def_x_cap);
-
- /* Crystal cap. control by WiFi */
- if (dm->support_ic_type & ODM_RTL8822B)
- odm_set_bb_reg(dm, 0x10, 0x40, 0x1);
-}
-
-void odm_cfo_tracking(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct cfo_tracking *cfo_track =
- (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
- s32 cfo_ave = 0;
- u32 cfo_rpt_sum, cfo_khz_avg[4] = {0};
- s32 cfo_ave_diff;
- s8 crystal_cap = cfo_track->crystal_cap;
- u8 adjust_xtal = 1, i, valid_path_cnt = 0;
-
- /* 4 Support ability */
- if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) {
- ODM_RT_TRACE(
- dm, ODM_COMP_CFO_TRACKING,
- "%s(): Return: support_ability ODM_BB_CFO_TRACKING is disabled\n",
- __func__);
- return;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING, "%s()=========>\n", __func__);
-
- if (!dm->is_linked || !dm->is_one_entry_only) {
- /* 4 No link or more than one entry */
- odm_cfo_tracking_reset(dm);
- ODM_RT_TRACE(
- dm, ODM_COMP_CFO_TRACKING,
- "%s(): Reset: is_linked = %d, is_one_entry_only = %d\n",
- __func__, dm->is_linked, dm->is_one_entry_only);
- } else {
- /* 3 1. CFO Tracking */
- /* 4 1.1 No new packet */
- if (cfo_track->packet_count == cfo_track->packet_count_pre) {
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "%s(): packet counter doesn't change\n",
- __func__);
- return;
- }
- cfo_track->packet_count_pre = cfo_track->packet_count;
-
- /* 4 1.2 Calculate CFO */
- for (i = 0; i < dm->num_rf_path; i++) {
- if (cfo_track->CFO_cnt[i] == 0)
- continue;
-
- valid_path_cnt++;
- cfo_rpt_sum =
- (u32)((cfo_track->CFO_tail[i] < 0) ?
- (0 - cfo_track->CFO_tail[i]) :
- cfo_track->CFO_tail[i]);
- cfo_khz_avg[i] = CFO_HW_RPT_2_MHZ(cfo_rpt_sum) /
- cfo_track->CFO_cnt[i];
-
- ODM_RT_TRACE(
- dm, ODM_COMP_CFO_TRACKING,
- "[path %d] cfo_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n",
- i, cfo_rpt_sum, cfo_track->CFO_cnt[i],
- ((cfo_track->CFO_tail[i] < 0) ? "-" : " "),
- cfo_khz_avg[i]);
- }
-
- for (i = 0; i < valid_path_cnt; i++) {
- if (cfo_track->CFO_tail[i] < 0) {
- /* */
- cfo_ave += (0 - (s32)cfo_khz_avg[i]);
- } else {
- cfo_ave += (s32)cfo_khz_avg[i];
- }
- }
-
- if (valid_path_cnt >= 2)
- cfo_ave = cfo_ave / valid_path_cnt;
-
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "valid_path_cnt = ((%d)), cfo_ave = ((%d kHz))\n",
- valid_path_cnt, cfo_ave);
-
- /*reset counter*/
- for (i = 0; i < dm->num_rf_path; i++) {
- cfo_track->CFO_tail[i] = 0;
- cfo_track->CFO_cnt[i] = 0;
- }
-
- /* 4 1.3 Avoid abnormal large CFO */
- cfo_ave_diff = (cfo_track->CFO_ave_pre >= cfo_ave) ?
- (cfo_track->CFO_ave_pre - cfo_ave) :
- (cfo_ave - cfo_track->CFO_ave_pre);
- if (cfo_ave_diff > 20 && cfo_track->large_cfo_hit == 0 &&
- !cfo_track->is_adjust) {
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "%s(): first large CFO hit\n", __func__);
- cfo_track->large_cfo_hit = 1;
- return;
- }
-
- cfo_track->large_cfo_hit = 0;
- cfo_track->CFO_ave_pre = cfo_ave;
-
- /* 4 1.4 Dynamic Xtal threshold */
- if (!cfo_track->is_adjust) {
- if (cfo_ave > CFO_TH_XTAL_HIGH ||
- cfo_ave < (-CFO_TH_XTAL_HIGH))
- cfo_track->is_adjust = true;
- } else {
- if (cfo_ave < CFO_TH_XTAL_LOW &&
- cfo_ave > (-CFO_TH_XTAL_LOW))
- cfo_track->is_adjust = false;
- }
-
- /* 4 1.5 BT case: Disable CFO tracking */
- if (dm->is_bt_enabled) {
- cfo_track->is_adjust = false;
- odm_set_crystal_cap(dm, cfo_track->def_x_cap);
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "%s(): Disable CFO tracking for BT!!\n",
- __func__);
- }
-
- /* 4 1.7 Adjust Crystal Cap. */
- if (cfo_track->is_adjust) {
- if (cfo_ave > CFO_TH_XTAL_LOW)
- crystal_cap = crystal_cap + adjust_xtal;
- else if (cfo_ave < (-CFO_TH_XTAL_LOW))
- crystal_cap = crystal_cap - adjust_xtal;
-
- if (crystal_cap > 0x3f)
- crystal_cap = 0x3f;
- else if (crystal_cap < 0)
- crystal_cap = 0;
-
- odm_set_crystal_cap(dm, (u8)crystal_cap);
- }
- ODM_RT_TRACE(
- dm, ODM_COMP_CFO_TRACKING,
- "%s(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
- __func__, cfo_track->crystal_cap, cfo_track->def_x_cap);
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- return;
-
- /* 3 2. Dynamic ATC switch */
- if (cfo_ave < CFO_TH_ATC && cfo_ave > -CFO_TH_ATC) {
- odm_set_atc_status(dm, false);
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "%s(): Disable ATC!!\n", __func__);
- } else {
- odm_set_atc_status(dm, true);
- ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
- "%s(): Enable ATC!!\n", __func__);
- }
- }
-}
-
-void odm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail, u8 num_ss)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_per_pkt_info *pktinfo =
- (struct dm_per_pkt_info *)pktinfo_void;
- struct cfo_tracking *cfo_track =
- (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
- u8 i;
-
- if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
- return;
-
- if (pktinfo->is_packet_match_bssid) {
- if (num_ss > dm->num_rf_path) /*For fool proof*/
- num_ss = dm->num_rf_path;
-
- /* 3 Update CFO report for path-A & path-B */
- /* Only paht-A and path-B have CFO tail and short CFO */
- for (i = 0; i < num_ss; i++) {
- cfo_track->CFO_tail[i] += pcfotail[i];
- cfo_track->CFO_cnt[i]++;
- }
-
- /* 3 Update packet counter */
- if (cfo_track->packet_count == 0xffffffff)
- cfo_track->packet_count = 0;
- else
- cfo_track->packet_count++;
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMCFOTRACK_H__
-#define __PHYDMCFOTRACK_H__
-
-#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/
-
-#define CFO_TH_XTAL_HIGH 20 /* kHz */
-#define CFO_TH_XTAL_LOW 10 /* kHz */
-#define CFO_TH_ATC 80 /* kHz */
-
-struct cfo_tracking {
- bool is_atc_status;
- bool large_cfo_hit;
- bool is_adjust;
- u8 crystal_cap;
- u8 def_x_cap;
- s32 CFO_tail[4];
- u32 CFO_cnt[4];
- s32 CFO_ave_pre;
- u32 packet_count;
- u32 packet_count_pre;
-
- bool is_force_xtal_cap;
- bool is_reset;
-};
-
-void odm_cfo_tracking_reset(void *dm_void);
-
-void odm_cfo_tracking_init(void *dm_void);
-
-void odm_cfo_tracking(void *dm_void);
-
-void odm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
- u8 num_ss);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-#include <linux/kernel.h>
-
-bool phydm_api_set_txagc(struct phy_dm_struct *, u32, enum odm_rf_radio_path,
- u8, bool);
-static inline void phydm_check_dmval_txagc(struct phy_dm_struct *dm, u32 used,
- u32 out_len, u32 *const dm_value,
- char *output)
-{
- if ((u8)dm_value[2] != 0xff) {
- if (phydm_api_set_txagc(dm, dm_value[3],
- (enum odm_rf_radio_path)dm_value[1],
- (u8)dm_value[2], true))
- PHYDM_SNPRINTF(output + used, out_len - used,
- " %s%d %s%x%s%x\n", "Write path-",
- dm_value[1], "rate index-0x",
- dm_value[2], " = 0x", dm_value[3]);
- else
- PHYDM_SNPRINTF(output + used, out_len - used,
- " %s%d %s%x%s\n", "Write path-",
- (dm_value[1] & 0x1), "rate index-0x",
- (dm_value[2] & 0x7f), " fail");
- } else {
- u8 i;
- u32 power_index;
- bool status = true;
-
- power_index = (dm_value[3] & 0x3f);
-
- if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
- power_index = (power_index << 24) |
- (power_index << 16) | (power_index << 8) |
- (power_index);
- for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4)
- status &= phydm_api_set_txagc(dm, power_index,
- (enum odm_rf_radio_path)
- dm_value[1],
- i, false);
- } else if (dm->support_ic_type & ODM_RTL8197F) {
- for (i = 0; i <= ODM_RATEMCS15; i++)
- status &= phydm_api_set_txagc(dm, power_index,
- (enum odm_rf_radio_path)
- dm_value[1],
- i, false);
- }
-
- if (status)
- PHYDM_SNPRINTF(output + used, out_len - used,
- " %s%d %s%x\n",
- "Write all TXAGC of path-", dm_value[1],
- " = 0x", dm_value[3]);
- else
- PHYDM_SNPRINTF(output + used, out_len - used,
- " %s%d %s\n",
- "Write all TXAGC of path-", dm_value[1],
- " fail");
- }
-}
-
-static inline void phydm_print_nhm_trigger(char *output, u32 used, u32 out_len,
- struct ccx_info *ccx_info)
-{
- int i;
-
- for (i = 0; i <= 10; i++) {
- if (i == 5)
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "\r\n NHM_th[%d] = 0x%x, echo_IGI = 0x%x", i,
- ccx_info->NHM_th[i], ccx_info->echo_IGI);
- else if (i == 10)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n NHM_th[%d] = 0x%x\n", i,
- ccx_info->NHM_th[i]);
- else
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n NHM_th[%d] = 0x%x", i,
- ccx_info->NHM_th[i]);
- }
-}
-
-static inline void phydm_print_nhm_result(char *output, u32 used, u32 out_len,
- struct ccx_info *ccx_info)
-{
- int i;
-
- for (i = 0; i <= 11; i++) {
- if (i == 5)
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "\r\n nhm_result[%d] = %d, echo_IGI = 0x%x", i,
- ccx_info->NHM_result[i], ccx_info->echo_IGI);
- else if (i == 11)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n nhm_result[%d] = %d\n", i,
- ccx_info->NHM_result[i]);
- else
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n nhm_result[%d] = %d", i,
- ccx_info->NHM_result[i]);
- }
-}
-
-static inline void phydm_print_csi(struct phy_dm_struct *dm, u32 used,
- u32 out_len, char *output)
-{
- int index, ptr;
- u32 dword_h, dword_l;
-
- for (index = 0; index < 80; index++) {
- ptr = index + 256;
-
- if (ptr > 311)
- ptr -= 312;
-
- odm_set_bb_reg(dm, 0x1910, 0x03FF0000, ptr); /*Select Address*/
- dword_h = odm_get_bb_reg(dm, 0xF74, MASKDWORD);
- dword_l = odm_get_bb_reg(dm, 0xF5C, MASKDWORD);
-
- PHYDM_SNPRINTF(output + used,
- out_len - used,
- "%02x %02x %02x %02x %02x %02x %02x %02x\n",
- dword_l & MASKBYTE0,
- (dword_l & MASKBYTE1) >> 8,
- (dword_l & MASKBYTE2) >> 16,
- (dword_l & MASKBYTE3) >> 24,
- dword_h & MASKBYTE0,
- (dword_h & MASKBYTE1) >> 8,
- (dword_h & MASKBYTE2) >> 16,
- (dword_h & MASKBYTE3) >> 24);
- }
-}
-
-void phydm_init_debug_setting(struct phy_dm_struct *dm)
-{
- dm->debug_level = ODM_DBG_TRACE;
-
- dm->fw_debug_components = 0;
- dm->debug_components = 0;
-
- dm->fw_buff_is_enpty = true;
- dm->pre_c2h_seq = 0;
-}
-
-u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 dbg_port_result = false;
-
- if (curr_dbg_priority > dm->pre_dbg_priority) {
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, 0x8fc, MASKDWORD, debug_port);
- /**/
- } else /*if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ {
- odm_set_bb_reg(dm, 0x908, MASKDWORD, debug_port);
- /**/
- }
- ODM_RT_TRACE(
- dm, ODM_COMP_API,
- "DbgPort set success, Reg((0x%x)), Cur_priority=((%d)), Pre_priority=((%d))\n",
- debug_port, curr_dbg_priority, dm->pre_dbg_priority);
- dm->pre_dbg_priority = curr_dbg_priority;
- dbg_port_result = true;
- }
-
- return dbg_port_result;
-}
-
-void phydm_release_bb_dbg_port(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- dm->pre_dbg_priority = BB_DBGPORT_RELEASE;
- ODM_RT_TRACE(dm, ODM_COMP_API, "Release BB dbg_port\n");
-}
-
-u32 phydm_get_bb_dbg_port_value(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 dbg_port_value = 0;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- dbg_port_value = odm_get_bb_reg(dm, 0xfa0, MASKDWORD);
- /**/
- } else /*if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ {
- dbg_port_value = odm_get_bb_reg(dm, 0xdf4, MASKDWORD);
- /**/
- }
- ODM_RT_TRACE(dm, ODM_COMP_API, "dbg_port_value = 0x%x\n",
- dbg_port_value);
- return dbg_port_value;
-}
-
-static void phydm_bb_rx_hang_info(void *dm_void, u32 *_used, char *output,
- u32 *_out_len)
-{
- u32 value32 = 0;
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES)
- return;
-
- value32 = odm_get_bb_reg(dm, 0xF80, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = 0x%x",
- "rptreg of sc/bw/ht/...", value32);
-
- if (dm->support_ic_type & ODM_RTL8822B)
- odm_set_bb_reg(dm, 0x198c, BIT(2) | BIT(1) | BIT(0), 7);
-
- /* dbg_port = basic state machine */
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "basic state machine",
- value32);
- }
-
- /* dbg_port = state machine */
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "state machine", value32);
- }
-
- /* dbg_port = CCA-related*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "CCA-related", value32);
- }
-
- /* dbg_port = edcca/rxd*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "edcca/rxd", value32);
- }
-
- /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x",
- "rx_state/mux_state/ADC_MASK_OFDM", value32);
- }
-
- /* dbg_port = bf-related*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "bf-related", value32);
- }
-
- /* dbg_port = bf-related*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "bf-related", value32);
- }
-
- /* dbg_port = txon/rxd*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "txon/rxd", value32);
- }
-
- /* dbg_port = l_rate/l_length*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "l_rate/l_length", value32);
- }
-
- /* dbg_port = rxd/rxd_hit*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
- }
-
- /* dbg_port = dis_cca*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "dis_cca", value32);
- }
-
- /* dbg_port = tx*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "tx", value32);
- }
-
- /* dbg_port = rx plcp*/
- {
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "rx plcp", value32);
-
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "rx plcp", value32);
-
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "rx plcp", value32);
-
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);
- value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "0x8fc", value32);
-
- value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = 0x%x", "rx plcp", value32);
- }
-}
-
-static void phydm_bb_debug_info_n_series(void *dm_void, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- u32 value32 = 0, value32_1 = 0;
- u8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0;
- u8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0;
-
- s8 rxevm_0 = 0, rxevm_1 = 0;
- s32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0;
- s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0;
- s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0;
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s\n",
- "BB Report Info");
-
- /*AGC result*/
- value32 = odm_get_bb_reg(dm, 0xdd0, MASKDWORD);
- rf_gain_a = (u8)(value32 & 0x3f);
- rf_gain_a = rf_gain_a << 1;
-
- rf_gain_b = (u8)((value32 >> 8) & 0x3f);
- rf_gain_b = rf_gain_b << 1;
-
- rf_gain_c = (u8)((value32 >> 16) & 0x3f);
- rf_gain_c = rf_gain_c << 1;
-
- rf_gain_d = (u8)((value32 >> 24) & 0x3f);
- rf_gain_d = rf_gain_d << 1;
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d / %d",
- "OFDM RX RF Gain(A/B/C/D)", rf_gain_a, rf_gain_b,
- rf_gain_c, rf_gain_d);
-
- /*SNR report*/
- value32 = odm_get_bb_reg(dm, 0xdd4, MASKDWORD);
- rx_snr_a = (u8)(value32 & 0xff);
- rx_snr_a = rx_snr_a >> 1;
-
- rx_snr_b = (u8)((value32 >> 8) & 0xff);
- rx_snr_b = rx_snr_b >> 1;
-
- rx_snr_c = (u8)((value32 >> 16) & 0xff);
- rx_snr_c = rx_snr_c >> 1;
-
- rx_snr_d = (u8)((value32 >> 24) & 0xff);
- rx_snr_d = rx_snr_d >> 1;
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)",
- rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d);
-
- /* PostFFT related info*/
- value32 = odm_get_bb_reg(dm, 0xdd8, MASKDWORD);
-
- rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
- rxevm_0 /= 2;
- if (rxevm_0 < -63)
- rxevm_0 = 0;
-
- rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
- rxevm_1 /= 2;
- if (rxevm_1 < -63)
- rxevm_1 = 0;
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "RXEVM (1ss/2ss)", rxevm_0, rxevm_1);
-
- /*CFO Report Info*/
- odm_set_bb_reg(dm, 0xd00, BIT(26), 1);
-
- /*Short CFO*/
- value32 = odm_get_bb_reg(dm, 0xdac, MASKDWORD);
- value32_1 = odm_get_bb_reg(dm, 0xdb0, MASKDWORD);
-
- short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/
- short_cfo_a = (s32)((value32 & 0x0fff0000) >> 16);
-
- long_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
- long_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
-
- /*SFO 2's to dec*/
- if (short_cfo_a > 2047)
- short_cfo_a = short_cfo_a - 4096;
- if (short_cfo_b > 2047)
- short_cfo_b = short_cfo_b - 4096;
-
- short_cfo_a = (short_cfo_a * 312500) / 2048;
- short_cfo_b = (short_cfo_b * 312500) / 2048;
-
- /*LFO 2's to dec*/
-
- if (long_cfo_a > 4095)
- long_cfo_a = long_cfo_a - 8192;
-
- if (long_cfo_b > 4095)
- long_cfo_b = long_cfo_b - 8192;
-
- long_cfo_a = long_cfo_a * 312500 / 4096;
- long_cfo_b = long_cfo_b * 312500 / 4096;
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
- "CFO Report Info");
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "Short CFO(Hz) <A/B>", short_cfo_a, short_cfo_b);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "Long CFO(Hz) <A/B>", long_cfo_a, long_cfo_b);
-
- /*SCFO*/
- value32 = odm_get_bb_reg(dm, 0xdb8, MASKDWORD);
- value32_1 = odm_get_bb_reg(dm, 0xdb4, MASKDWORD);
-
- scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/
- scfo_a = (s32)((value32 & 0x07ff0000) >> 16);
-
- if (scfo_a > 1023)
- scfo_a = scfo_a - 2048;
-
- if (scfo_b > 1023)
- scfo_b = scfo_b - 2048;
-
- scfo_a = scfo_a * 312500 / 1024;
- scfo_b = scfo_b * 312500 / 1024;
-
- avg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
- avg_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
-
- if (avg_cfo_a > 4095)
- avg_cfo_a = avg_cfo_a - 8192;
-
- if (avg_cfo_b > 4095)
- avg_cfo_b = avg_cfo_b - 8192;
-
- avg_cfo_a = avg_cfo_a * 312500 / 4096;
- avg_cfo_b = avg_cfo_b * 312500 / 4096;
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "value SCFO(Hz) <A/B>", scfo_a, scfo_b);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "Avg CFO(Hz) <A/B>", avg_cfo_a, avg_cfo_b);
-
- value32 = odm_get_bb_reg(dm, 0xdbc, MASKDWORD);
- value32_1 = odm_get_bb_reg(dm, 0xde0, MASKDWORD);
-
- cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/
- cfo_end_a = (s32)((value32 & 0x1fff0000) >> 16);
-
- if (cfo_end_a > 4095)
- cfo_end_a = cfo_end_a - 8192;
-
- if (cfo_end_b > 4095)
- cfo_end_b = cfo_end_b - 8192;
-
- cfo_end_a = cfo_end_a * 312500 / 4096;
- cfo_end_b = cfo_end_b * 312500 / 4096;
-
- acq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
- acq_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
-
- if (acq_cfo_a > 4095)
- acq_cfo_a = acq_cfo_a - 8192;
-
- if (acq_cfo_b > 4095)
- acq_cfo_b = acq_cfo_b - 8192;
-
- acq_cfo_a = acq_cfo_a * 312500 / 4096;
- acq_cfo_b = acq_cfo_b * 312500 / 4096;
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "End CFO(Hz) <A/B>", cfo_end_a, cfo_end_b);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "ACQ CFO(Hz) <A/B>", acq_cfo_a, acq_cfo_b);
-}
-
-static void phydm_bb_debug_info(void *dm_void, u32 *_used, char *output,
- u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- char *tmp_string = NULL;
-
- u8 rx_ht_bw, rx_vht_bw, rxsc, rx_ht, rx_bw;
- static u8 v_rx_bw;
- u32 value32, value32_1, value32_2, value32_3;
- s32 sfo_a, sfo_b, sfo_c, sfo_d;
- s32 lfo_a, lfo_b, lfo_c, lfo_d;
- static u8 MCSS, tail, parity, rsv, vrsv, idx, smooth, htsound, agg,
- stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts,
- vtxops, vrsv2, vbrsv, bf, vbcrc;
- static u16 h_length, htcrc8, length;
- static u16 vpaid;
- static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;
- static u8 hmcss, hrx_bw;
-
- u8 pwdb;
- s8 rxevm_0, rxevm_1, rxevm_2;
- u8 rf_gain_path_a, rf_gain_path_b, rf_gain_path_c, rf_gain_path_d;
- u8 rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, rx_snr_path_d;
- s32 sig_power;
-
- const char *L_rate[8] = {"6M", "9M", "12M", "18M",
- "24M", "36M", "48M", "54M"};
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- phydm_bb_debug_info_n_series(dm, &used, output, &out_len);
- return;
- }
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s\n",
- "BB Report Info");
-
- /*BW & mode Detection*/
-
- value32 = odm_get_bb_reg(dm, 0xf80, MASKDWORD);
- value32_2 = value32;
- rx_ht_bw = (u8)(value32 & 0x1);
- rx_vht_bw = (u8)((value32 >> 1) & 0x3);
- rxsc = (u8)(value32 & 0x78);
- value32_1 = (value32 & 0x180) >> 7;
- rx_ht = (u8)(value32_1);
-
- rx_bw = 0;
-
- if (rx_ht == 2) {
- if (rx_vht_bw == 0)
- tmp_string = "20M";
- else if (rx_vht_bw == 1)
- tmp_string = "40M";
- else
- tmp_string = "80M";
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s %s %s", "mode", "VHT", tmp_string);
- rx_bw = rx_vht_bw;
- } else if (rx_ht == 1) {
- if (rx_ht_bw == 0)
- tmp_string = "20M";
- else if (rx_ht_bw == 1)
- tmp_string = "40M";
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s %s %s", "mode", "HT", tmp_string);
- rx_bw = rx_ht_bw;
- } else {
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s %s",
- "mode", "Legacy");
- }
- if (rx_ht != 0) {
- if (rxsc == 0)
- tmp_string = "duplicate/full bw";
- else if (rxsc == 1)
- tmp_string = "usc20-1";
- else if (rxsc == 2)
- tmp_string = "lsc20-1";
- else if (rxsc == 3)
- tmp_string = "usc20-2";
- else if (rxsc == 4)
- tmp_string = "lsc20-2";
- else if (rxsc == 9)
- tmp_string = "usc40";
- else if (rxsc == 10)
- tmp_string = "lsc40";
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s",
- tmp_string);
- }
-
- /* RX signal power and AGC related info*/
-
- value32 = odm_get_bb_reg(dm, 0xF90, MASKDWORD);
- pwdb = (u8)((value32 & MASKBYTE1) >> 8);
- pwdb = pwdb >> 1;
- sig_power = -110 + pwdb;
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d",
- "OFDM RX Signal Power(dB)", sig_power);
-
- value32 = odm_get_bb_reg(dm, 0xd14, MASKDWORD);
- rx_snr_path_a = (u8)(value32 & 0xFF) >> 1;
- rf_gain_path_a = (s8)((value32 & MASKBYTE1) >> 8);
- rf_gain_path_a *= 2;
- value32 = odm_get_bb_reg(dm, 0xd54, MASKDWORD);
- rx_snr_path_b = (u8)(value32 & 0xFF) >> 1;
- rf_gain_path_b = (s8)((value32 & MASKBYTE1) >> 8);
- rf_gain_path_b *= 2;
- value32 = odm_get_bb_reg(dm, 0xd94, MASKDWORD);
- rx_snr_path_c = (u8)(value32 & 0xFF) >> 1;
- rf_gain_path_c = (s8)((value32 & MASKBYTE1) >> 8);
- rf_gain_path_c *= 2;
- value32 = odm_get_bb_reg(dm, 0xdd4, MASKDWORD);
- rx_snr_path_d = (u8)(value32 & 0xFF) >> 1;
- rf_gain_path_d = (s8)((value32 & MASKBYTE1) >> 8);
- rf_gain_path_d *= 2;
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d / %d",
- "OFDM RX RF Gain(A/B/C/D)", rf_gain_path_a,
- rf_gain_path_b, rf_gain_path_c, rf_gain_path_d);
-
- /* RX counter related info*/
-
- value32 = odm_get_bb_reg(dm, 0xF08, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d",
- "OFDM CCA counter", ((value32 & 0xFFFF0000) >> 16));
-
- value32 = odm_get_bb_reg(dm, 0xFD0, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d",
- "OFDM SBD Fail counter", value32 & 0xFFFF);
-
- value32 = odm_get_bb_reg(dm, 0xFC4, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "VHT SIGA/SIGB CRC8 Fail counter", value32 & 0xFFFF,
- ((value32 & 0xFFFF0000) >> 16));
-
- value32 = odm_get_bb_reg(dm, 0xFCC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d",
- "CCK CCA counter", value32 & 0xFFFF);
-
- value32 = odm_get_bb_reg(dm, 0xFBC, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "LSIG (parity Fail/rate Illegal) counter",
- value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
-
- value32_1 = odm_get_bb_reg(dm, 0xFC8, MASKDWORD);
- value32_2 = odm_get_bb_reg(dm, 0xFC0, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "HT/VHT MCS NOT SUPPORT counter",
- ((value32_2 & 0xFFFF0000) >> 16), value32_1 & 0xFFFF);
-
- /* PostFFT related info*/
- value32 = odm_get_bb_reg(dm, 0xF8c, MASKDWORD);
- rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
- rxevm_0 /= 2;
- if (rxevm_0 < -63)
- rxevm_0 = 0;
-
- rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
- rxevm_1 /= 2;
- value32 = odm_get_bb_reg(dm, 0xF88, MASKDWORD);
- rxevm_2 = (s8)((value32 & MASKBYTE2) >> 16);
- rxevm_2 /= 2;
-
- if (rxevm_1 < -63)
- rxevm_1 = 0;
- if (rxevm_2 < -63)
- rxevm_2 = 0;
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)",
- rxevm_0, rxevm_1, rxevm_2);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)",
- rx_snr_path_a, rx_snr_path_b, rx_snr_path_c,
- rx_snr_path_d);
-
- value32 = odm_get_bb_reg(dm, 0xF8C, MASKDWORD);
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s = %d / %d",
- "CSI_1st /CSI_2nd", value32 & 0xFFFF,
- ((value32 & 0xFFFF0000) >> 16));
-
- /*BW & mode Detection*/
-
- /*Reset Page F counter*/
- odm_set_bb_reg(dm, 0xB58, BIT(0), 1);
- odm_set_bb_reg(dm, 0xB58, BIT(0), 0);
-
- /*CFO Report Info*/
- /*Short CFO*/
- value32 = odm_get_bb_reg(dm, 0xd0c, MASKDWORD);
- value32_1 = odm_get_bb_reg(dm, 0xd4c, MASKDWORD);
- value32_2 = odm_get_bb_reg(dm, 0xd8c, MASKDWORD);
- value32_3 = odm_get_bb_reg(dm, 0xdcc, MASKDWORD);
-
- sfo_a = (s32)(value32 & 0xfff);
- sfo_b = (s32)(value32_1 & 0xfff);
- sfo_c = (s32)(value32_2 & 0xfff);
- sfo_d = (s32)(value32_3 & 0xfff);
-
- lfo_a = (s32)(value32 >> 16);
- lfo_b = (s32)(value32_1 >> 16);
- lfo_c = (s32)(value32_2 >> 16);
- lfo_d = (s32)(value32_3 >> 16);
-
- /*SFO 2's to dec*/
- if (sfo_a > 2047)
- sfo_a = sfo_a - 4096;
- sfo_a = (sfo_a * 312500) / 2048;
- if (sfo_b > 2047)
- sfo_b = sfo_b - 4096;
- sfo_b = (sfo_b * 312500) / 2048;
- if (sfo_c > 2047)
- sfo_c = sfo_c - 4096;
- sfo_c = (sfo_c * 312500) / 2048;
- if (sfo_d > 2047)
- sfo_d = sfo_d - 4096;
- sfo_d = (sfo_d * 312500) / 2048;
-
- /*LFO 2's to dec*/
-
- if (lfo_a > 4095)
- lfo_a = lfo_a - 8192;
-
- if (lfo_b > 4095)
- lfo_b = lfo_b - 8192;
-
- if (lfo_c > 4095)
- lfo_c = lfo_c - 8192;
-
- if (lfo_d > 4095)
- lfo_d = lfo_d - 8192;
- lfo_a = lfo_a * 312500 / 4096;
- lfo_b = lfo_b * 312500 / 4096;
- lfo_c = lfo_c * 312500 / 4096;
- lfo_d = lfo_d * 312500 / 4096;
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
- "CFO Report Info");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d /%d",
- "Short CFO(Hz) <A/B/C/D>", sfo_a, sfo_b, sfo_c, sfo_d);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d /%d",
- "Long CFO(Hz) <A/B/C/D>", lfo_a, lfo_b, lfo_c, lfo_d);
-
- /*SCFO*/
- value32 = odm_get_bb_reg(dm, 0xd10, MASKDWORD);
- value32_1 = odm_get_bb_reg(dm, 0xd50, MASKDWORD);
- value32_2 = odm_get_bb_reg(dm, 0xd90, MASKDWORD);
- value32_3 = odm_get_bb_reg(dm, 0xdd0, MASKDWORD);
-
- sfo_a = (s32)(value32 & 0x7ff);
- sfo_b = (s32)(value32_1 & 0x7ff);
- sfo_c = (s32)(value32_2 & 0x7ff);
- sfo_d = (s32)(value32_3 & 0x7ff);
-
- if (sfo_a > 1023)
- sfo_a = sfo_a - 2048;
-
- if (sfo_b > 2047)
- sfo_b = sfo_b - 4096;
-
- if (sfo_c > 2047)
- sfo_c = sfo_c - 4096;
-
- if (sfo_d > 2047)
- sfo_d = sfo_d - 4096;
-
- sfo_a = sfo_a * 312500 / 1024;
- sfo_b = sfo_b * 312500 / 1024;
- sfo_c = sfo_c * 312500 / 1024;
- sfo_d = sfo_d * 312500 / 1024;
-
- lfo_a = (s32)(value32 >> 16);
- lfo_b = (s32)(value32_1 >> 16);
- lfo_c = (s32)(value32_2 >> 16);
- lfo_d = (s32)(value32_3 >> 16);
-
- if (lfo_a > 4095)
- lfo_a = lfo_a - 8192;
-
- if (lfo_b > 4095)
- lfo_b = lfo_b - 8192;
-
- if (lfo_c > 4095)
- lfo_c = lfo_c - 8192;
-
- if (lfo_d > 4095)
- lfo_d = lfo_d - 8192;
- lfo_a = lfo_a * 312500 / 4096;
- lfo_b = lfo_b * 312500 / 4096;
- lfo_c = lfo_c * 312500 / 4096;
- lfo_d = lfo_d * 312500 / 4096;
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d /%d",
- "value SCFO(Hz) <A/B/C/D>", sfo_a, sfo_b, sfo_c, sfo_d);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d /%d", "ACQ CFO(Hz) <A/B/C/D>",
- lfo_a, lfo_b, lfo_c, lfo_d);
-
- value32 = odm_get_bb_reg(dm, 0xd14, MASKDWORD);
- value32_1 = odm_get_bb_reg(dm, 0xd54, MASKDWORD);
- value32_2 = odm_get_bb_reg(dm, 0xd94, MASKDWORD);
- value32_3 = odm_get_bb_reg(dm, 0xdd4, MASKDWORD);
-
- lfo_a = (s32)(value32 >> 16);
- lfo_b = (s32)(value32_1 >> 16);
- lfo_c = (s32)(value32_2 >> 16);
- lfo_d = (s32)(value32_3 >> 16);
-
- if (lfo_a > 4095)
- lfo_a = lfo_a - 8192;
-
- if (lfo_b > 4095)
- lfo_b = lfo_b - 8192;
-
- if (lfo_c > 4095)
- lfo_c = lfo_c - 8192;
-
- if (lfo_d > 4095)
- lfo_d = lfo_d - 8192;
-
- lfo_a = lfo_a * 312500 / 4096;
- lfo_b = lfo_b * 312500 / 4096;
- lfo_c = lfo_c * 312500 / 4096;
- lfo_d = lfo_d * 312500 / 4096;
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d / %d / %d /%d", "End CFO(Hz) <A/B/C/D>",
- lfo_a, lfo_b, lfo_c, lfo_d);
-
- value32 = odm_get_bb_reg(dm, 0xf20, MASKDWORD); /*L SIG*/
-
- tail = (u8)((value32 & 0xfc0000) >> 16);
- parity = (u8)((value32 & 0x20000) >> 16);
- length = (u16)((value32 & 0x1ffe00) >> 8);
- rsv = (u8)(value32 & 0x10);
- MCSS = (u8)(value32 & 0x0f);
-
- switch (MCSS) {
- case 0x0b:
- idx = 0;
- break;
- case 0x0f:
- idx = 1;
- break;
- case 0x0a:
- idx = 2;
- break;
- case 0x0e:
- idx = 3;
- break;
- case 0x09:
- idx = 4;
- break;
- case 0x08:
- idx = 5;
- break;
- case 0x0c:
- idx = 6;
- break;
- default:
- idx = 6;
- break;
- }
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s", "L-SIG");
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s : %s", "rate",
- L_rate[idx]);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %x / %x / %x", "Rsv/length/parity", rsv,
- rx_bw, length);
-
- value32 = odm_get_bb_reg(dm, 0xf2c, MASKDWORD); /*HT SIG*/
- if (rx_ht == 1) {
- hmcss = (u8)(value32 & 0x7F);
- hrx_bw = (u8)(value32 & 0x80);
- h_length = (u16)((value32 >> 8) & 0xffff);
- }
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s", "HT-SIG1");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %x / %x / %x", "MCS/BW/length", hmcss,
- hrx_bw, h_length);
-
- value32 = odm_get_bb_reg(dm, 0xf30, MASKDWORD); /*HT SIG*/
-
- if (rx_ht == 1) {
- smooth = (u8)(value32 & 0x01);
- htsound = (u8)(value32 & 0x02);
- rsv = (u8)(value32 & 0x04);
- agg = (u8)(value32 & 0x08);
- stbc = (u8)(value32 & 0x30);
- fec = (u8)(value32 & 0x40);
- sgi = (u8)(value32 & 0x80);
- htltf = (u8)((value32 & 0x300) >> 8);
- htcrc8 = (u16)((value32 & 0x3fc00) >> 8);
- tail = (u8)((value32 & 0xfc0000) >> 16);
- }
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s", "HT-SIG2");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %x / %x / %x / %x / %x / %x",
- "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", smooth,
- htsound, rsv, agg, stbc, fec);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %x / %x / %x / %x",
- "SGI/E-HT-LTFs/CRC/tail", sgi, htltf, htcrc8, tail);
-
- value32 = odm_get_bb_reg(dm, 0xf2c, MASKDWORD); /*VHT SIG A1*/
- if (rx_ht == 2) {
- /* value32 = odm_get_bb_reg(dm, 0xf2c,MASKDWORD);*/
- v_rx_bw = (u8)(value32 & 0x03);
- vrsv = (u8)(value32 & 0x04);
- vstbc = (u8)(value32 & 0x08);
- vgid = (u8)((value32 & 0x3f0) >> 4);
- v_nsts = (u8)(((value32 & 0x1c00) >> 8) + 1);
- vpaid = (u16)(value32 & 0x3fe);
- vtxops = (u8)((value32 & 0x400000) >> 20);
- vrsv2 = (u8)((value32 & 0x800000) >> 20);
- }
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
- "VHT-SIG-A1");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x",
- "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, vrsv,
- vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);
-
- value32 = odm_get_bb_reg(dm, 0xf30, MASKDWORD); /*VHT SIG*/
-
- if (rx_ht == 2) {
- /*value32 = odm_get_bb_reg(dm, 0xf30,MASKDWORD); */ /*VHT SIG*/
-
- /* sgi=(u8)(value32&0x01); */
- sgiext = (u8)(value32 & 0x03);
- /* fec = (u8)(value32&0x04); */
- fecext = (u8)(value32 & 0x0C);
-
- v_mcss = (u8)(value32 & 0xf0);
- bf = (u8)((value32 & 0x100) >> 8);
- vrsv = (u8)((value32 & 0x200) >> 8);
- vhtcrc8 = (u16)((value32 & 0x3fc00) >> 8);
- v_tail = (u8)((value32 & 0xfc0000) >> 16);
- }
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
- "VHT-SIG-A2");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x",
- "SGI/FEC/MCS/BF/Rsv/CRC/tail", sgiext, fecext, v_mcss,
- bf, vrsv, vhtcrc8, v_tail);
-
- value32 = odm_get_bb_reg(dm, 0xf34, MASKDWORD); /*VHT SIG*/
- {
- v_length = (u16)(value32 & 0x1fffff);
- vbrsv = (u8)((value32 & 0x600000) >> 20);
- vb_tail = (u16)((value32 & 0x1f800000) >> 20);
- vbcrc = (u8)((value32 & 0x80000000) >> 28);
- }
- PHYDM_SNPRINTF(output + used, out_len - used, "\r\n %-35s",
- "VHT-SIG-B");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %x / %x / %x / %x", "length/Rsv/tail/CRC",
- v_length, vbrsv, vb_tail, vbcrc);
-
- /*for Condition number*/
- if (dm->support_ic_type & ODM_RTL8822B) {
- s32 condition_num = 0;
- char *factor = NULL;
-
- /*enable report condition number*/
- odm_set_bb_reg(dm, 0x1988, BIT(22), 0x1);
-
- condition_num = odm_get_bb_reg(dm, 0xf84, MASKDWORD);
- condition_num = (condition_num & 0x3ffff) >> 4;
-
- if (*dm->band_width == ODM_BW80M) {
- factor = "256/234";
- } else if (*dm->band_width == ODM_BW40M) {
- factor = "128/108";
- } else if (*dm->band_width == ODM_BW20M) {
- if (rx_ht == 2 || rx_ht == 1)
- factor = "64/52"; /*HT or VHT*/
- else
- factor = "64/48"; /*legacy*/
- }
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n %-35s = %d (factor = %s)",
- "Condition number", condition_num, factor);
- }
-}
-
-void phydm_basic_dbg_message(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct false_alarm_stat *false_alm_cnt =
- (struct false_alarm_stat *)phydm_get_structure(
- dm, PHYDM_FALSEALMCNT);
- struct cfo_tracking *cfo_track =
- (struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- struct ra_table *ra_tab = &dm->dm_ra_table;
- u16 macid, phydm_macid, client_cnt = 0;
- struct rtl_sta_info *entry;
- s32 tmp_val = 0;
- u8 tmp_val_u1 = 0;
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "[PHYDM Common MSG] System up time: ((%d sec))----->\n",
- dm->phydm_sys_up_time);
-
- if (dm->is_linked) {
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "ID=%d, BW=((%d)), CH=((%d))\n",
- dm->curr_station_id, 20 << *dm->band_width,
- *dm->channel);
-
- /*Print RX rate*/
- if (dm->rx_rate <= ODM_RATE11M)
- ODM_RT_TRACE(
- dm, ODM_COMP_COMMON,
- "[CCK AGC Report] LNA_idx = 0x%x, VGA_idx = 0x%x\n",
- dm->cck_lna_idx, dm->cck_vga_idx);
- else
- ODM_RT_TRACE(
- dm, ODM_COMP_COMMON,
- "[OFDM AGC Report] { 0x%x, 0x%x, 0x%x, 0x%x }\n",
- dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],
- dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "RSSI: { %d, %d, %d, %d }, rx_rate:",
- (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,
- (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,
- (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,
- (dm->rssi_d == 0xff) ? 0 : dm->rssi_d);
-
- phydm_print_rate(dm, dm->rx_rate, ODM_COMP_COMMON);
-
- /*Print TX rate*/
- for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
- entry = dm->odm_sta_info[macid];
- if (!IS_STA_VALID(entry))
- continue;
-
- phydm_macid = (dm->platform2phydm_macid_table[macid]);
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "TXRate [%d]:",
- macid);
- phydm_print_rate(dm, ra_tab->link_tx_rate[macid],
- ODM_COMP_COMMON);
-
- client_cnt++;
-
- if (client_cnt == dm->number_linked_client)
- break;
- }
-
- ODM_RT_TRACE(
- dm, ODM_COMP_COMMON,
- "TP { TX, RX, total} = {%d, %d, %d }Mbps, traffic_load = (%d))\n",
- dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);
-
- tmp_val_u1 =
- (cfo_track->crystal_cap > cfo_track->def_x_cap) ?
- (cfo_track->crystal_cap -
- cfo_track->def_x_cap) :
- (cfo_track->def_x_cap - cfo_track->crystal_cap);
- ODM_RT_TRACE(
- dm, ODM_COMP_COMMON,
- "CFO_avg = ((%d kHz)) , CrystalCap_tracking = ((%s%d))\n",
- cfo_track->CFO_ave_pre,
- ((cfo_track->crystal_cap > cfo_track->def_x_cap) ? "+" :
- "-"),
- tmp_val_u1);
-
- /* Condition number */
- if (dm->support_ic_type == ODM_RTL8822B) {
- tmp_val = phydm_get_condition_number_8822B(dm);
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "Condition number = ((%d))\n", tmp_val);
- }
-
- /*STBC or LDPC pkt*/
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "LDPC = %s, STBC = %s\n",
- (dm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N",
- (dm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N");
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "No Link !!!\n");
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
- false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca,
- false_alm_cnt->cnt_cca_all);
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
- false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail,
- false_alm_cnt->cnt_all);
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES)
- ODM_RT_TRACE(
- dm, ODM_COMP_COMMON,
- "[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n",
- false_alm_cnt->cnt_parity_fail,
- false_alm_cnt->cnt_rate_illegal,
- false_alm_cnt->cnt_crc8_fail,
- false_alm_cnt->cnt_mcs_fail,
- false_alm_cnt->cnt_fast_fsync,
- false_alm_cnt->cnt_sb_search_fail);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_COMMON,
- "is_linked = %d, Num_client = %d, rssi_min = %d, current_igi = 0x%x, bNoisy=%d\n\n",
- dm->is_linked, dm->number_linked_client, dm->rssi_min,
- dig_tab->cur_ig_value, dm->noisy_decision);
-}
-
-void phydm_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- char *cut = NULL;
- char *ic_type = NULL;
- u32 used = *_used;
- u32 out_len = *_out_len;
- u32 date = 0;
- char *commit_by = NULL;
- u32 release_ver = 0;
-
- PHYDM_SNPRINTF(output + used, out_len - used, "%-35s\n",
- "% Basic Profile %");
-
- if (dm->support_ic_type == ODM_RTL8188E) {
- } else if (dm->support_ic_type == ODM_RTL8822B) {
- ic_type = "RTL8822B";
- date = RELEASE_DATE_8822B;
- commit_by = COMMIT_BY_8822B;
- release_ver = RELEASE_VERSION_8822B;
- }
-
- /* JJ ADD 20161014 */
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- " %-35s: %s (MP Chip: %s)\n", "IC type", ic_type,
- dm->is_mp_chip ? "Yes" : "No");
-
- if (dm->cut_version == ODM_CUT_A)
- cut = "A";
- else if (dm->cut_version == ODM_CUT_B)
- cut = "B";
- else if (dm->cut_version == ODM_CUT_C)
- cut = "C";
- else if (dm->cut_version == ODM_CUT_D)
- cut = "D";
- else if (dm->cut_version == ODM_CUT_E)
- cut = "E";
- else if (dm->cut_version == ODM_CUT_F)
- cut = "F";
- else if (dm->cut_version == ODM_CUT_I)
- cut = "I";
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "cut version", cut);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %d\n",
- "PHY Parameter version", odm_get_hw_img_version(dm));
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %d\n",
- "PHY Parameter Commit date", date);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "PHY Parameter Commit by", commit_by);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %d\n",
- "PHY Parameter Release version", release_ver);
-
- {
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- " %-35s: %d (Subversion: %d)\n", "FW version",
- rtlhal->fw_version, rtlhal->fw_subversion);
- }
- /* 1 PHY DM version List */
- PHYDM_SNPRINTF(output + used, out_len - used, "%-35s\n",
- "% PHYDM version %");
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "Code base", PHYDM_CODE_BASE);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "Release Date", PHYDM_RELEASE_DATE);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "adaptivity", ADAPTIVITY_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n", "DIG",
- DIG_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "Dynamic BB PowerSaving", DYNAMIC_BBPWRSAV_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "CFO Tracking", CFO_TRACKING_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "Antenna Diversity", ANTDIV_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "Power Tracking", POWRTRACKING_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "Dynamic TxPower", DYNAMIC_TXPWR_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "RA Info", RAINFO_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "Auto channel Selection", ACS_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "EDCA Turbo", EDCATURBO_VERSION);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "LA mode", DYNAMIC_LA_MODE);
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "Dynamic RX path", DYNAMIC_RX_PATH_VERSION);
-
- if (dm->support_ic_type & ODM_RTL8822B)
- PHYDM_SNPRINTF(output + used, out_len - used, " %-35s: %s\n",
- "PHY config 8822B", PHY_CONFIG_VERSION_8822B);
-
- *_used = used;
- *_out_len = out_len;
-}
-
-void phydm_fw_trace_en_h2c(void *dm_void, bool enable, u32 fw_debug_component,
- u32 monitor_mode, u32 macid)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 h2c_parameter[7] = {0};
- u8 cmd_length;
-
- if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
- h2c_parameter[0] = enable;
- h2c_parameter[1] = (u8)(fw_debug_component & MASKBYTE0);
- h2c_parameter[2] = (u8)((fw_debug_component & MASKBYTE1) >> 8);
- h2c_parameter[3] = (u8)((fw_debug_component & MASKBYTE2) >> 16);
- h2c_parameter[4] = (u8)((fw_debug_component & MASKBYTE3) >> 24);
- h2c_parameter[5] = (u8)monitor_mode;
- h2c_parameter[6] = (u8)macid;
- cmd_length = 7;
-
- } else {
- h2c_parameter[0] = enable;
- h2c_parameter[1] = (u8)monitor_mode;
- h2c_parameter[2] = (u8)macid;
- cmd_length = 3;
- }
-
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "---->\n");
- if (monitor_mode == 0)
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "[H2C] FW_debug_en: (( %d ))\n", enable);
- else
- ODM_RT_TRACE(
- dm, ODM_FW_DEBUG_TRACE,
- "[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n",
- enable, monitor_mode, macid);
- odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter);
-}
-
-bool phydm_api_set_txagc(struct phy_dm_struct *dm, u32 power_index,
- enum odm_rf_radio_path path, u8 hw_rate,
- bool is_single_rate)
-{
- bool ret = false;
-
- if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
- if (is_single_rate) {
- if (dm->support_ic_type == ODM_RTL8822B)
- ret = phydm_write_txagc_1byte_8822b(
- dm, power_index, path, hw_rate);
-
- } else {
- if (dm->support_ic_type == ODM_RTL8822B)
- ret = config_phydm_write_txagc_8822b(
- dm, power_index, path, hw_rate);
- }
- }
-
- return ret;
-}
-
-static u8 phydm_api_get_txagc(struct phy_dm_struct *dm,
- enum odm_rf_radio_path path, u8 hw_rate)
-{
- u8 ret = 0;
-
- if (dm->support_ic_type & ODM_RTL8822B)
- ret = config_phydm_read_txagc_8822b(dm, path, hw_rate);
-
- return ret;
-}
-
-static bool phydm_api_switch_bw_channel(struct phy_dm_struct *dm, u8 central_ch,
- u8 primary_ch_idx,
- enum odm_bw bandwidth)
-{
- bool ret = false;
-
- if (dm->support_ic_type & ODM_RTL8822B)
- ret = config_phydm_switch_channel_bw_8822b(
- dm, central_ch, primary_ch_idx, bandwidth);
-
- return ret;
-}
-
-bool phydm_api_trx_mode(struct phy_dm_struct *dm, enum odm_rf_path tx_path,
- enum odm_rf_path rx_path, bool is_tx2_path)
-{
- bool ret = false;
-
- if (dm->support_ic_type & ODM_RTL8822B)
- ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path,
- is_tx2_path);
-
- return ret;
-}
-
-static void phydm_get_per_path_txagc(void *dm_void, u8 path, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 rate_idx;
- u8 txagc;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- if (((dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) &&
- path <= ODM_RF_PATH_B) ||
- ((dm->support_ic_type & (ODM_RTL8821C)) &&
- path <= ODM_RF_PATH_A)) {
- for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) {
- if (rate_idx == ODM_RATE1M)
- PHYDM_SNPRINTF(output + used, out_len - used,
- " %-35s\n", "CCK====>");
- else if (rate_idx == ODM_RATE6M)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n %-35s\n", "OFDM====>");
- else if (rate_idx == ODM_RATEMCS0)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n %-35s\n", "HT 1ss====>");
- else if (rate_idx == ODM_RATEMCS8)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n %-35s\n", "HT 2ss====>");
- else if (rate_idx == ODM_RATEMCS16)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n %-35s\n", "HT 3ss====>");
- else if (rate_idx == ODM_RATEMCS24)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n %-35s\n", "HT 4ss====>");
- else if (rate_idx == ODM_RATEVHTSS1MCS0)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n %-35s\n", "VHT 1ss====>");
- else if (rate_idx == ODM_RATEVHTSS2MCS0)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n %-35s\n", "VHT 2ss====>");
- else if (rate_idx == ODM_RATEVHTSS3MCS0)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n %-35s\n", "VHT 3ss====>");
- else if (rate_idx == ODM_RATEVHTSS4MCS0)
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n %-35s\n", "VHT 4ss====>");
-
- txagc = phydm_api_get_txagc(
- dm, (enum odm_rf_radio_path)path, rate_idx);
- if (config_phydm_read_txagc_check(txagc))
- PHYDM_SNPRINTF(output + used, out_len - used,
- " 0x%02x ", txagc);
- else
- PHYDM_SNPRINTF(output + used, out_len - used,
- " 0x%s ", "xx");
- }
- }
-}
-
-static void phydm_get_txagc(void *dm_void, u32 *_used, char *output,
- u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- /* path-A */
- PHYDM_SNPRINTF(output + used, out_len - used, "%-35s\n",
- "path-A====================");
- phydm_get_per_path_txagc(dm, ODM_RF_PATH_A, _used, output, _out_len);
-
- /* path-B */
- PHYDM_SNPRINTF(output + used, out_len - used, "\n%-35s\n",
- "path-B====================");
- phydm_get_per_path_txagc(dm, ODM_RF_PATH_B, _used, output, _out_len);
-
- /* path-C */
- PHYDM_SNPRINTF(output + used, out_len - used, "\n%-35s\n",
- "path-C====================");
- phydm_get_per_path_txagc(dm, ODM_RF_PATH_C, _used, output, _out_len);
-
- /* path-D */
- PHYDM_SNPRINTF(output + used, out_len - used, "\n%-35s\n",
- "path-D====================");
- phydm_get_per_path_txagc(dm, ODM_RF_PATH_D, _used, output, _out_len);
-}
-
-static void phydm_set_txagc(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- /*dm_value[1] = path*/
- /*dm_value[2] = hw_rate*/
- /*dm_value[3] = power_index*/
-
- if (dm->support_ic_type &
- (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) {
- if (dm_value[1] <= 1) {
- phydm_check_dmval_txagc(dm, used, out_len, dm_value,
- output);
- } else {
- PHYDM_SNPRINTF(output + used, out_len - used,
- " %s%d %s%x%s\n", "Write path-",
- (dm_value[1] & 0x1), "rate index-0x",
- (dm_value[2] & 0x7f), " fail");
- }
- }
-}
-
-static void phydm_debug_trace(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 pre_debug_components, one = 1;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- pre_debug_components = dm->debug_components;
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\n%s\n",
- "================================");
- if (dm_value[0] == 100) {
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "[Debug Message] PhyDM Selection");
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "================================");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "00. (( %s ))DIG\n",
- ((dm->debug_components & ODM_COMP_DIG) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "01. (( %s ))RA_MASK\n",
- ((dm->debug_components & ODM_COMP_RA_MASK) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "02. (( %s ))DYNAMIC_TXPWR\n",
- ((dm->debug_components & ODM_COMP_DYNAMIC_TXPWR) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "03. (( %s ))FA_CNT\n",
- ((dm->debug_components & ODM_COMP_FA_CNT) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "04. (( %s ))RSSI_MONITOR\n",
- ((dm->debug_components & ODM_COMP_RSSI_MONITOR) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "05. (( %s ))SNIFFER\n",
- ((dm->debug_components & ODM_COMP_SNIFFER) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "06. (( %s ))ANT_DIV\n",
- ((dm->debug_components & ODM_COMP_ANT_DIV) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "07. (( %s ))DFS\n",
- ((dm->debug_components & ODM_COMP_DFS) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "08. (( %s ))NOISY_DETECT\n",
- ((dm->debug_components & ODM_COMP_NOISY_DETECT) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "09. (( %s ))RATE_ADAPTIVE\n",
- ((dm->debug_components & ODM_COMP_RATE_ADAPTIVE) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "10. (( %s ))PATH_DIV\n",
- ((dm->debug_components & ODM_COMP_PATH_DIV) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "12. (( %s ))DYNAMIC_PRICCA\n",
- ((dm->debug_components & ODM_COMP_DYNAMIC_PRICCA) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "14. (( %s ))MP\n",
- ((dm->debug_components & ODM_COMP_MP) ? ("V") : (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "15. (( %s ))struct cfo_tracking\n",
- ((dm->debug_components & ODM_COMP_CFO_TRACKING) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "16. (( %s ))struct acs_info\n",
- ((dm->debug_components & ODM_COMP_ACS) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "17. (( %s ))ADAPTIVITY\n",
- ((dm->debug_components & PHYDM_COMP_ADAPTIVITY) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "18. (( %s ))RA_DBG\n",
- ((dm->debug_components & PHYDM_COMP_RA_DBG) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "19. (( %s ))TXBF\n",
- ((dm->debug_components & PHYDM_COMP_TXBF) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "20. (( %s ))EDCA_TURBO\n",
- ((dm->debug_components & ODM_COMP_EDCA_TURBO) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "22. (( %s ))FW_DEBUG_TRACE\n",
- ((dm->debug_components & ODM_FW_DEBUG_TRACE) ?
- ("V") :
- (".")));
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "24. (( %s ))TX_PWR_TRACK\n",
- ((dm->debug_components & ODM_COMP_TX_PWR_TRACK) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "26. (( %s ))CALIBRATION\n",
- ((dm->debug_components & ODM_COMP_CALIBRATION) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "28. (( %s ))PHY_CONFIG\n",
- ((dm->debug_components & ODM_PHY_CONFIG) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "29. (( %s ))INIT\n",
- ((dm->debug_components & ODM_COMP_INIT) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(
- output + used, out_len - used, "30. (( %s ))COMMON\n",
- ((dm->debug_components & ODM_COMP_COMMON) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "31. (( %s ))API\n",
- ((dm->debug_components & ODM_COMP_API) ? ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "================================");
-
- } else if (dm_value[0] == 101) {
- dm->debug_components = 0;
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "Disable all debug components");
- } else {
- if (dm_value[1] == 1) /*enable*/
- dm->debug_components |= (one << dm_value[0]);
- else if (dm_value[1] == 2) /*disable*/
- dm->debug_components &= ~(one << dm_value[0]);
- else
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "[Warning!!!] 1:enable, 2:disable");
- }
- PHYDM_SNPRINTF(output + used, out_len - used,
- "pre-DbgComponents = 0x%x\n", pre_debug_components);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Curr-DbgComponents = 0x%x\n", dm->debug_components);
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "================================");
-}
-
-static void phydm_fw_debug_trace(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 pre_fw_debug_components, one = 1;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- pre_fw_debug_components = dm->fw_debug_components;
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\n%s\n",
- "================================");
- if (dm_value[0] == 100) {
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "[FW Debug Component]");
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "================================");
- PHYDM_SNPRINTF(
- output + used, out_len - used, "00. (( %s ))RA\n",
- ((dm->fw_debug_components & PHYDM_FW_COMP_RA) ? ("V") :
- (".")));
-
- if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "01. (( %s ))MU\n",
- ((dm->fw_debug_components & PHYDM_FW_COMP_MU) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "02. (( %s ))path Div\n",
- ((dm->fw_debug_components &
- PHYDM_FW_COMP_PHY_CONFIG) ?
- ("V") :
- (".")));
- PHYDM_SNPRINTF(output + used, out_len - used,
- "03. (( %s ))Phy Config\n",
- ((dm->fw_debug_components &
- PHYDM_FW_COMP_PHY_CONFIG) ?
- ("V") :
- (".")));
- }
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "================================");
-
- } else {
- if (dm_value[0] == 101) {
- dm->fw_debug_components = 0;
- PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
- "Clear all fw debug components");
- } else {
- if (dm_value[1] == 1) /*enable*/
- dm->fw_debug_components |= (one << dm_value[0]);
- else if (dm_value[1] == 2) /*disable*/
- dm->fw_debug_components &=
- ~(one << dm_value[0]);
- else
- PHYDM_SNPRINTF(
- output + used, out_len - used, "%s\n",
- "[Warning!!!] 1:enable, 2:disable");
- }
-
- if (dm->fw_debug_components == 0) {
- dm->debug_components &= ~ODM_FW_DEBUG_TRACE;
- phydm_fw_trace_en_h2c(
- dm, false, dm->fw_debug_components, dm_value[2],
- dm_value[3]); /*H2C to enable C2H Msg*/
- } else {
- dm->debug_components |= ODM_FW_DEBUG_TRACE;
- phydm_fw_trace_en_h2c(
- dm, true, dm->fw_debug_components, dm_value[2],
- dm_value[3]); /*H2C to enable C2H Msg*/
- }
- }
-}
-
-static void phydm_dump_bb_reg(void *dm_void, u32 *_used, char *output,
- u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 addr = 0;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- /* For Nseries IC we only need to dump page8 to pageF using 3 digits*/
- for (addr = 0x800; addr < 0xfff; addr += 4) {
- if (dm->support_ic_type & ODM_IC_11N_SERIES)
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%03x 0x%08x\n", addr,
- odm_get_bb_reg(dm, addr, MASKDWORD));
- else
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%04x 0x%08x\n", addr,
- odm_get_bb_reg(dm, addr, MASKDWORD));
- }
-
- if (dm->support_ic_type &
- (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)) {
- if (dm->rf_type > ODM_2T2R) {
- for (addr = 0x1800; addr < 0x18ff; addr += 4)
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%04x 0x%08x\n", addr,
- odm_get_bb_reg(dm, addr, MASKDWORD));
- }
-
- if (dm->rf_type > ODM_3T3R) {
- for (addr = 0x1a00; addr < 0x1aff; addr += 4)
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%04x 0x%08x\n", addr,
- odm_get_bb_reg(dm, addr, MASKDWORD));
- }
-
- for (addr = 0x1900; addr < 0x19ff; addr += 4)
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%04x 0x%08x\n", addr,
- odm_get_bb_reg(dm, addr, MASKDWORD));
-
- for (addr = 0x1c00; addr < 0x1cff; addr += 4)
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%04x 0x%08x\n", addr,
- odm_get_bb_reg(dm, addr, MASKDWORD));
-
- for (addr = 0x1f00; addr < 0x1fff; addr += 4)
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%04x 0x%08x\n", addr,
- odm_get_bb_reg(dm, addr, MASKDWORD));
- }
-}
-
-static void phydm_dump_all_reg(void *dm_void, u32 *_used, char *output,
- u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 addr = 0;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- /* dump MAC register */
- PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
- "MAC==========\n");
- for (addr = 0; addr < 0x7ff; addr += 4)
- PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
- "0x%04x 0x%08x\n", addr,
- odm_get_bb_reg(dm, addr, MASKDWORD));
-
- for (addr = 0x1000; addr < 0x17ff; addr += 4)
- PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
- "0x%04x 0x%08x\n", addr,
- odm_get_bb_reg(dm, addr, MASKDWORD));
-
- /* dump BB register */
- PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
- "BB==========\n");
- phydm_dump_bb_reg(dm, &used, output, &out_len);
-
- /* dump RF register */
- PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
- "RF-A==========\n");
- for (addr = 0; addr < 0xFF; addr++)
- PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
- "0x%02x 0x%05x\n", addr,
- odm_get_rf_reg(dm, ODM_RF_PATH_A, addr,
- RFREGOFFSETMASK));
-
- if (dm->rf_type > ODM_1T1R) {
- PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
- "RF-B==========\n");
- for (addr = 0; addr < 0xFF; addr++)
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%02x 0x%05x\n", addr,
- odm_get_rf_reg(dm, ODM_RF_PATH_B, addr,
- RFREGOFFSETMASK));
- }
-
- if (dm->rf_type > ODM_2T2R) {
- PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
- "RF-C==========\n");
- for (addr = 0; addr < 0xFF; addr++)
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%02x 0x%05x\n", addr,
- odm_get_rf_reg(dm, ODM_RF_PATH_C, addr,
- RFREGOFFSETMASK));
- }
-
- if (dm->rf_type > ODM_3T3R) {
- PHYDM_VAST_INFO_SNPRINTF(output + used, out_len - used,
- "RF-D==========\n");
- for (addr = 0; addr < 0xFF; addr++)
- PHYDM_VAST_INFO_SNPRINTF(
- output + used, out_len - used,
- "0x%02x 0x%05x\n", addr,
- odm_get_rf_reg(dm, ODM_RF_PATH_D, addr,
- RFREGOFFSETMASK));
- }
-}
-
-static void phydm_enable_big_jump(struct phy_dm_struct *dm, bool state)
-{
- struct dig_thres *dig_tab = &dm->dm_dig_table;
-
- if (!state) {
- dm->dm_dig_table.enable_adjust_big_jump = false;
- odm_set_bb_reg(dm, 0x8c8, 0xfe,
- ((dig_tab->big_jump_step3 << 5) |
- (dig_tab->big_jump_step2 << 3) |
- dig_tab->big_jump_step1));
- } else {
- dm->dm_dig_table.enable_adjust_big_jump = true;
- }
-}
-
-static void phydm_show_rx_rate(struct phy_dm_struct *dm, u32 *_used,
- char *output, u32 *_out_len)
-{
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "=====Rx SU rate Statistics=====\n");
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n",
- dm->phy_dbg_info.num_qry_vht_pkt[0],
- dm->phy_dbg_info.num_qry_vht_pkt[1],
- dm->phy_dbg_info.num_qry_vht_pkt[2],
- dm->phy_dbg_info.num_qry_vht_pkt[3]);
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n",
- dm->phy_dbg_info.num_qry_vht_pkt[4],
- dm->phy_dbg_info.num_qry_vht_pkt[5],
- dm->phy_dbg_info.num_qry_vht_pkt[6],
- dm->phy_dbg_info.num_qry_vht_pkt[7]);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "1SS MCS8 = %d, 1SS MCS9 = %d\n",
- dm->phy_dbg_info.num_qry_vht_pkt[8],
- dm->phy_dbg_info.num_qry_vht_pkt[9]);
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n",
- dm->phy_dbg_info.num_qry_vht_pkt[10],
- dm->phy_dbg_info.num_qry_vht_pkt[11],
- dm->phy_dbg_info.num_qry_vht_pkt[12],
- dm->phy_dbg_info.num_qry_vht_pkt[13]);
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n",
- dm->phy_dbg_info.num_qry_vht_pkt[14],
- dm->phy_dbg_info.num_qry_vht_pkt[15],
- dm->phy_dbg_info.num_qry_vht_pkt[16],
- dm->phy_dbg_info.num_qry_vht_pkt[17]);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "2SS MCS8 = %d, 2SS MCS9 = %d\n",
- dm->phy_dbg_info.num_qry_vht_pkt[18],
- dm->phy_dbg_info.num_qry_vht_pkt[19]);
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "=====Rx MU rate Statistics=====\n");
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n",
- dm->phy_dbg_info.num_qry_mu_vht_pkt[0],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[1],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[2],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[3]);
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n",
- dm->phy_dbg_info.num_qry_mu_vht_pkt[4],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[5],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[6],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[7]);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "1SS MCS8 = %d, 1SS MCS9 = %d\n",
- dm->phy_dbg_info.num_qry_mu_vht_pkt[8],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[9]);
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n",
- dm->phy_dbg_info.num_qry_mu_vht_pkt[10],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[11],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[12],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[13]);
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n",
- dm->phy_dbg_info.num_qry_mu_vht_pkt[14],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[15],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[16],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[17]);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "2SS MCS8 = %d, 2SS MCS9 = %d\n",
- dm->phy_dbg_info.num_qry_mu_vht_pkt[18],
- dm->phy_dbg_info.num_qry_mu_vht_pkt[19]);
-}
-
-struct phydm_command {
- char name[16];
- u8 id;
-};
-
-enum PHYDM_CMD_ID {
- PHYDM_HELP,
- PHYDM_DEMO,
- PHYDM_RA,
- PHYDM_PROFILE,
- PHYDM_ANTDIV,
- PHYDM_PATHDIV,
- PHYDM_DEBUG,
- PHYDM_FW_DEBUG,
- PHYDM_SUPPORT_ABILITY,
- PHYDM_GET_TXAGC,
- PHYDM_SET_TXAGC,
- PHYDM_SMART_ANT,
- PHYDM_API,
- PHYDM_TRX_PATH,
- PHYDM_LA_MODE,
- PHYDM_DUMP_REG,
- PHYDM_MU_MIMO,
- PHYDM_HANG,
- PHYDM_BIG_JUMP,
- PHYDM_SHOW_RXRATE,
- PHYDM_NBI_EN,
- PHYDM_CSI_MASK_EN,
- PHYDM_DFS,
- PHYDM_IQK,
- PHYDM_NHM,
- PHYDM_CLM,
- PHYDM_BB_INFO,
- PHYDM_TXBF,
- PHYDM_PAUSE_DIG_EN,
- PHYDM_H2C,
- PHYDM_ANT_SWITCH,
- PHYDM_DYNAMIC_RA_PATH,
- PHYDM_PSD,
- PHYDM_DEBUG_PORT
-};
-
-static struct phydm_command phy_dm_ary[] = {
- {"-h", PHYDM_HELP}, /*do not move this element to other position*/
- {"demo", PHYDM_DEMO}, /*do not move this element to other position*/
- {"ra", PHYDM_RA},
- {"profile", PHYDM_PROFILE},
- {"antdiv", PHYDM_ANTDIV},
- {"pathdiv", PHYDM_PATHDIV},
- {"dbg", PHYDM_DEBUG},
- {"fw_dbg", PHYDM_FW_DEBUG},
- {"ability", PHYDM_SUPPORT_ABILITY},
- {"get_txagc", PHYDM_GET_TXAGC},
- {"set_txagc", PHYDM_SET_TXAGC},
- {"smtant", PHYDM_SMART_ANT},
- {"api", PHYDM_API},
- {"trxpath", PHYDM_TRX_PATH},
- {"lamode", PHYDM_LA_MODE},
- {"dumpreg", PHYDM_DUMP_REG},
- {"mu", PHYDM_MU_MIMO},
- {"hang", PHYDM_HANG},
- {"bigjump", PHYDM_BIG_JUMP},
- {"rxrate", PHYDM_SHOW_RXRATE},
- {"nbi", PHYDM_NBI_EN},
- {"csi_mask", PHYDM_CSI_MASK_EN},
- {"dfs", PHYDM_DFS},
- {"iqk", PHYDM_IQK},
- {"nhm", PHYDM_NHM},
- {"clm", PHYDM_CLM},
- {"bbinfo", PHYDM_BB_INFO},
- {"txbf", PHYDM_TXBF},
- {"pause_dig", PHYDM_PAUSE_DIG_EN},
- {"h2c", PHYDM_H2C},
- {"ant_switch", PHYDM_ANT_SWITCH},
- {"drp", PHYDM_DYNAMIC_RA_PATH},
- {"psd", PHYDM_PSD},
- {"dbgport", PHYDM_DEBUG_PORT},
-};
-
-void phydm_cmd_parser(struct phy_dm_struct *dm, char input[][MAX_ARGV],
- u32 input_num, u8 flag, char *output, u32 out_len)
-{
- u32 used = 0;
- u8 id = 0;
- int var1[10] = {0};
- int i, input_idx = 0, phydm_ary_size;
- char help[] = "-h";
-
- bool is_enable_dbg_mode;
- u8 central_ch, primary_ch_idx, bandwidth;
-
- if (flag == 0) {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "GET, nothing to print\n");
- return;
- }
-
- PHYDM_SNPRINTF(output + used, out_len - used, "\n");
-
- /* Parsing Cmd ID */
- if (input_num) {
- phydm_ary_size = ARRAY_SIZE(phy_dm_ary);
- for (i = 0; i < phydm_ary_size; i++) {
- if (strcmp(phy_dm_ary[i].name, input[0]) == 0) {
- id = phy_dm_ary[i].id;
- break;
- }
- }
- if (i == phydm_ary_size) {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "SET, command not found!\n");
- return;
- }
- }
-
- switch (id) {
- case PHYDM_HELP: {
- PHYDM_SNPRINTF(output + used, out_len - used, "BB cmd ==>\n");
- for (i = 0; i < phydm_ary_size - 2; i++) {
- PHYDM_SNPRINTF(output + used, out_len - used,
- " %-5d: %s\n", i,
- phy_dm_ary[i + 2].name);
- /**/
- }
- } break;
-
- case PHYDM_DEMO: { /*echo demo 10 0x3a z abcde >cmd*/
- u32 directory = 0;
-
- char char_temp;
-
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Decimal value = %d\n", directory);
- PHYDM_SSCANF(input[2], DCMD_HEX, &directory);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Hex value = 0x%x\n", directory);
- PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp);
- PHYDM_SNPRINTF(output + used, out_len - used, "Char = %c\n",
- char_temp);
- PHYDM_SNPRINTF(output + used, out_len - used, "String = %s\n",
- input[4]);
- } break;
-
- case PHYDM_RA:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
-
- input_idx++;
- }
- }
-
- if (input_idx >= 1) {
- phydm_RA_debug_PCR(dm, (u32 *)var1, &used, output,
- &out_len);
- }
-
- break;
-
- case PHYDM_ANTDIV:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
-
- input_idx++;
- }
- }
-
- break;
-
- case PHYDM_PATHDIV:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
-
- input_idx++;
- }
- }
-
- break;
-
- case PHYDM_DEBUG:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
-
- input_idx++;
- }
- }
-
- if (input_idx >= 1) {
- phydm_debug_trace(dm, (u32 *)var1, &used, output,
- &out_len);
- }
-
- break;
-
- case PHYDM_FW_DEBUG:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
- input_idx++;
- }
- }
-
- if (input_idx >= 1)
- phydm_fw_debug_trace(dm, (u32 *)var1, &used, output,
- &out_len);
-
- break;
-
- case PHYDM_SUPPORT_ABILITY:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
-
- input_idx++;
- }
- }
-
- if (input_idx >= 1) {
- phydm_support_ability_debug(dm, (u32 *)var1, &used,
- output, &out_len);
- }
-
- break;
-
- case PHYDM_SMART_ANT:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
- input_idx++;
- }
- }
-
- break;
-
- case PHYDM_API:
- if (!(dm->support_ic_type &
- (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C))) {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "This IC doesn't support PHYDM API function\n");
- }
-
- for (i = 0; i < 4; i++) {
- if (input[i + 1])
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
- }
-
- is_enable_dbg_mode = (bool)var1[0];
- central_ch = (u8)var1[1];
- primary_ch_idx = (u8)var1[2];
- bandwidth = (enum odm_bw)var1[3];
-
- if (is_enable_dbg_mode) {
- dm->is_disable_phy_api = false;
- phydm_api_switch_bw_channel(dm, central_ch,
- primary_ch_idx,
- (enum odm_bw)bandwidth);
- dm->is_disable_phy_api = true;
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n",
- central_ch, primary_ch_idx, bandwidth);
- } else {
- dm->is_disable_phy_api = false;
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Disable API debug mode\n");
- }
- break;
-
- case PHYDM_PROFILE: /*echo profile, >cmd*/
- phydm_basic_profile(dm, &used, output, &out_len);
- break;
-
- case PHYDM_GET_TXAGC:
- phydm_get_txagc(dm, &used, output, &out_len);
- break;
-
- case PHYDM_SET_TXAGC: {
- bool is_enable_dbg_mode;
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
- input_idx++;
- }
- }
-
- if ((strcmp(input[1], help) == 0)) {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "{En} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n");
- /**/
-
- } else {
- is_enable_dbg_mode = (bool)var1[0];
- if (is_enable_dbg_mode) {
- dm->is_disable_phy_api = false;
- phydm_set_txagc(dm, (u32 *)var1, &used, output,
- &out_len);
- dm->is_disable_phy_api = true;
- } else {
- dm->is_disable_phy_api = false;
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Disable API debug mode\n");
- }
- }
- } break;
-
- case PHYDM_TRX_PATH:
-
- for (i = 0; i < 4; i++) {
- if (input[i + 1])
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
- }
- if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) {
- u8 tx_path, rx_path;
- bool is_enable_dbg_mode, is_tx2_path;
-
- is_enable_dbg_mode = (bool)var1[0];
- tx_path = (u8)var1[1];
- rx_path = (u8)var1[2];
- is_tx2_path = (bool)var1[3];
-
- if (is_enable_dbg_mode) {
- dm->is_disable_phy_api = false;
- phydm_api_trx_mode(
- dm, (enum odm_rf_path)tx_path,
- (enum odm_rf_path)rx_path, is_tx2_path);
- dm->is_disable_phy_api = true;
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "tx_path = 0x%x, rx_path = 0x%x, is_tx2_path = %d\n",
- tx_path, rx_path, is_tx2_path);
- } else {
- dm->is_disable_phy_api = false;
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Disable API debug mode\n");
- }
- } else {
- phydm_config_trx_path(dm, (u32 *)var1, &used, output,
- &out_len);
- }
- break;
-
- case PHYDM_LA_MODE:
-
- dm->support_ability &= ~(ODM_BB_FA_CNT);
- phydm_lamode_trigger_setting(dm, &input[0], &used, output,
- &out_len, input_num);
- dm->support_ability |= ODM_BB_FA_CNT;
-
- break;
-
- case PHYDM_DUMP_REG: {
- u8 type = 0;
-
- if (input[1]) {
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
- type = (u8)var1[0];
- }
-
- if (type == 0)
- phydm_dump_bb_reg(dm, &used, output, &out_len);
- else if (type == 1)
- phydm_dump_all_reg(dm, &used, output, &out_len);
- } break;
-
- case PHYDM_MU_MIMO:
-
- if (input[1])
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
- else
- var1[0] = 0;
-
- if (var1[0] == 1) {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Get MU BFee CSI\n");
- odm_set_bb_reg(dm, 0x9e8, BIT(17) | BIT(16),
- 2); /*Read BFee*/
- odm_set_bb_reg(dm, 0x1910, BIT(15),
- 1); /*Select BFee's CSI report*/
- odm_set_bb_reg(dm, 0x19b8, BIT(6),
- 1); /*set as CSI report*/
- odm_set_bb_reg(dm, 0x19a8, 0xFFFF,
- 0xFFFF); /*disable gated_clk*/
- phydm_print_csi(dm, used, out_len, output);
-
- } else if (var1[0] == 2) {
- PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Get MU BFer's STA%d CSI\n", var1[1]);
- odm_set_bb_reg(dm, 0x9e8, BIT(24), 0); /*Read BFer*/
- odm_set_bb_reg(dm, 0x9e8, BIT(25),
- 1); /*enable Read/Write RAM*/
- odm_set_bb_reg(dm, 0x9e8, BIT(30) | BIT(29) | BIT(28),
- var1[1]); /*read which STA's CSI report*/
- odm_set_bb_reg(dm, 0x1910, BIT(15),
- 0); /*select BFer's CSI*/
- odm_set_bb_reg(dm, 0x19e0, 0x00003FC0,
- 0xFF); /*disable gated_clk*/
- phydm_print_csi(dm, used, out_len, output);
- }
- break;
-
- case PHYDM_BIG_JUMP: {
- if (input[1]) {
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
- phydm_enable_big_jump(dm, (bool)(var1[0]));
- } else {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "unknown command!\n");
- }
- break;
- }
-
- case PHYDM_HANG:
- phydm_bb_rx_hang_info(dm, &used, output, &out_len);
- break;
-
- case PHYDM_SHOW_RXRATE: {
- u8 rate_idx;
-
- if (input[1])
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-
- if (var1[0] == 1) {
- phydm_show_rx_rate(dm, &used, output, &out_len);
- } else {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Reset Rx rate counter\n");
-
- for (rate_idx = 0; rate_idx < 40; rate_idx++) {
- dm->phy_dbg_info.num_qry_vht_pkt[rate_idx] = 0;
- dm->phy_dbg_info.num_qry_mu_vht_pkt[rate_idx] =
- 0;
- }
- }
- } break;
-
- case PHYDM_NBI_EN:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
- input_idx++;
- }
- }
-
- if (input_idx >= 1) {
- phydm_api_debug(dm, PHYDM_API_NBI, (u32 *)var1, &used,
- output, &out_len);
- /**/
- }
-
- break;
-
- case PHYDM_CSI_MASK_EN:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
- input_idx++;
- }
- }
-
- if (input_idx >= 1) {
- phydm_api_debug(dm, PHYDM_API_CSI_MASK, (u32 *)var1,
- &used, output, &out_len);
- /**/
- }
-
- break;
-
- case PHYDM_DFS:
- break;
-
- case PHYDM_IQK:
- break;
-
- case PHYDM_NHM: {
- u8 target_rssi;
- u16 nhm_period = 0xC350; /* 200ms */
- u8 IGI;
- struct ccx_info *ccx_info = &dm->dm_ccx_info;
-
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-
- if (input_num == 1) {
- ccx_info->echo_NHM_en = false;
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n Trigger NHM: echo nhm 1\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r (Exclude CCA)\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r Trigger NHM: echo nhm 2\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r (Include CCA)\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r Get NHM results: echo nhm 3\n");
-
- return;
- }
-
- /* NMH trigger */
- if (var1[0] <= 2 && var1[0] != 0) {
- ccx_info->echo_NHM_en = true;
- ccx_info->echo_IGI =
- (u8)odm_get_bb_reg(dm, 0xC50, MASKBYTE0);
-
- target_rssi = ccx_info->echo_IGI - 10;
-
- ccx_info->NHM_th[0] = (target_rssi - 15 + 10) * 2;
-
- for (i = 1; i <= 10; i++)
- ccx_info->NHM_th[i] =
- ccx_info->NHM_th[0] + 6 * i;
-
- /* 4 1. store previous NHM setting */
- phydm_nhm_setting(dm, STORE_NHM_SETTING);
-
- /* 4 2. Set NHM period, 0x990[31:16]=0xC350,
- * Time duration for NHM unit: 4us, 0xC350=200ms
- */
- ccx_info->NHM_period = nhm_period;
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n Monitor NHM for %d us",
- nhm_period * 4);
-
- /* 4 3. Set NHM inexclude_txon, inexclude_cca, ccx_en */
-
- ccx_info->nhm_inexclude_cca = (var1[0] == 1) ?
- NHM_EXCLUDE_CCA :
- NHM_INCLUDE_CCA;
- ccx_info->nhm_inexclude_txon = NHM_EXCLUDE_TXON;
-
- phydm_nhm_setting(dm, SET_NHM_SETTING);
- phydm_print_nhm_trigger(output, used, out_len,
- ccx_info);
-
- /* 4 4. Trigger NHM */
- phydm_nhm_trigger(dm);
- }
-
- /*Get NHM results*/
- else if (var1[0] == 3) {
- IGI = (u8)odm_get_bb_reg(dm, 0xC50, MASKBYTE0);
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n Cur_IGI = 0x%x", IGI);
-
- phydm_get_nhm_result(dm);
-
- /* 4 Resotre NHM setting */
- phydm_nhm_setting(dm, RESTORE_NHM_SETTING);
- phydm_print_nhm_result(output, used, out_len, ccx_info);
-
- ccx_info->echo_NHM_en = false;
- } else {
- ccx_info->echo_NHM_en = false;
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n Trigger NHM: echo nhm 1\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r (Exclude CCA)\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r Trigger NHM: echo nhm 2\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r (Include CCA)\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r Get NHM results: echo nhm 3\n");
-
- return;
- }
- } break;
-
- case PHYDM_CLM: {
- struct ccx_info *ccx_info = &dm->dm_ccx_info;
-
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-
- if (input_num == 1) {
- ccx_info->echo_CLM_en = false;
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n Trigger CLM: echo clm 1\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r Get CLM results: echo clm 2\n");
- return;
- }
-
- /* Set & trigger CLM */
- if (var1[0] == 1) {
- ccx_info->echo_CLM_en = true;
- ccx_info->CLM_period = 0xC350; /*100ms*/
- phydm_clm_setting(dm);
- phydm_clm_trigger(dm);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n Monitor CLM for 200ms\n");
- }
-
- /* Get CLM results */
- else if (var1[0] == 2) {
- ccx_info->echo_CLM_en = false;
- phydm_get_cl_mresult(dm);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n CLM_result = %d us\n",
- ccx_info->CLM_result * 4);
-
- } else {
- ccx_info->echo_CLM_en = false;
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\n\r Error command !\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r Trigger CLM: echo clm 1\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r Get CLM results: echo clm 2\n");
- }
- } break;
-
- case PHYDM_BB_INFO: {
- s32 value32 = 0;
-
- phydm_bb_debug_info(dm, &used, output, &out_len);
-
- if (dm->support_ic_type & ODM_RTL8822B && input[1]) {
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
- odm_set_bb_reg(dm, 0x1988, 0x003fff00, var1[0]);
- value32 = odm_get_bb_reg(dm, 0xf84, MASKDWORD);
- value32 = (value32 & 0xff000000) >> 24;
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "\r\n %-35s = condition num = %d, subcarriers = %d\n",
- "Over condition num subcarrier", var1[0],
- value32);
- odm_set_bb_reg(dm, 0x1988, BIT(22),
- 0x0); /*disable report condition number*/
- }
- } break;
-
- case PHYDM_TXBF: {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "\r\n no TxBF !!\n");
- } break;
-
- case PHYDM_PAUSE_DIG_EN:
-
- for (i = 0; i < 5; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
- input_idx++;
- }
- }
-
- if (input_idx >= 1) {
- if (var1[0] == 0) {
- odm_pause_dig(dm, PHYDM_PAUSE,
- PHYDM_PAUSE_LEVEL_7, (u8)var1[1]);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Set IGI_value = ((%x))\n",
- var1[1]);
- } else if (var1[0] == 1) {
- odm_pause_dig(dm, PHYDM_RESUME,
- PHYDM_PAUSE_LEVEL_7, (u8)var1[1]);
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Resume IGI_value\n");
- } else {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "echo (1:pause, 2resume) (IGI_value)\n");
- }
- }
- break;
- case PHYDM_H2C:
-
- for (i = 0; i < 8; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
- input_idx++;
- }
- }
-
- if (input_idx >= 1)
- phydm_h2C_debug(dm, (u32 *)var1, &used, output,
- &out_len);
-
- break;
-
- case PHYDM_ANT_SWITCH:
-
- for (i = 0; i < 8; i++) {
- if (input[i + 1]) {
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
- input_idx++;
- }
- }
-
- if (input_idx >= 1) {
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Not Support IC");
- }
-
- break;
-
- case PHYDM_DYNAMIC_RA_PATH:
-
- PHYDM_SNPRINTF(output + used, out_len - used, "Not Support IC");
-
- break;
-
- case PHYDM_PSD:
-
- phydm_psd_debug(dm, &input[0], &used, output, &out_len,
- input_num);
-
- break;
-
- case PHYDM_DEBUG_PORT: {
- u32 dbg_port_value;
-
- PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]);
-
- if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3,
- var1[0])) { /*set debug port to 0x0*/
-
- dbg_port_value = phydm_get_bb_dbg_port_value(dm);
- phydm_release_bb_dbg_port(dm);
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Debug Port[0x%x] = ((0x%x))\n", var1[1],
- dbg_port_value);
- }
- } break;
-
- default:
- PHYDM_SNPRINTF(output + used, out_len - used,
- "SET, unknown command!\n");
- break;
- }
-}
-
-s32 phydm_cmd(struct phy_dm_struct *dm, char *input, u32 in_len, u8 flag,
- char *output, u32 out_len)
-{
- char *token;
- u32 argc = 0;
- char argv[MAX_ARGC][MAX_ARGV];
-
- do {
- token = strsep(&input, ", ");
- if (token) {
- strcpy(argv[argc], token);
- argc++;
- } else {
- break;
- }
- } while (argc < MAX_ARGC);
-
- if (argc == 1)
- argv[0][strlen(argv[0]) - 1] = '\0';
-
- phydm_cmd_parser(dm, argv, argc, flag, output, out_len);
-
- return 0;
-}
-
-void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- /*u8 debug_trace_11byte[60];*/
- u8 freg_num, c2h_seq, buf_0 = 0;
-
- if (!(dm->support_ic_type & PHYDM_IC_3081_SERIES))
- return;
-
- if (cmd_len > 12)
- return;
-
- buf_0 = cmd_buf[0];
- freg_num = (buf_0 & 0xf);
- c2h_seq = (buf_0 & 0xf0) >> 4;
-
- if (c2h_seq != dm->pre_c2h_seq && !dm->fw_buff_is_enpty) {
- dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "[FW Dbg Queue Overflow] %s\n",
- dm->fw_debug_trace);
- dm->c2h_cmd_start = 0;
- }
-
- if ((cmd_len - 1) > (60 - dm->c2h_cmd_start)) {
- dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "[FW Dbg Queue error: wrong C2H length] %s\n",
- dm->fw_debug_trace);
- dm->c2h_cmd_start = 0;
- return;
- }
-
- strncpy((char *)&dm->fw_debug_trace[dm->c2h_cmd_start],
- (char *)&cmd_buf[1], (cmd_len - 1));
- dm->c2h_cmd_start += (cmd_len - 1);
- dm->fw_buff_is_enpty = false;
-
- if (freg_num == 0 || dm->c2h_cmd_start >= 60) {
- if (dm->c2h_cmd_start < 60)
- dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
- else
- dm->fw_debug_trace[59] = '\0';
-
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "[FW DBG Msg] %s\n",
- dm->fw_debug_trace);
- /*dbg_print("[FW DBG Msg] %s\n", dm->fw_debug_trace);*/
- dm->c2h_cmd_start = 0;
- dm->fw_buff_is_enpty = true;
- }
-
- dm->pre_c2h_seq = c2h_seq;
-}
-
-void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 function = buffer[0];
- u8 dbg_num = buffer[1];
- u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]);
- u16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]);
- u16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]);
- u16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]);
- u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]);
-
- if (cmd_len > 12)
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "[FW Msg] Invalid cmd length (( %d )) >12\n",
- cmd_len);
-
- /*--------------------------------------------*/
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function,
- dbg_num, content_0, content_1, content_2, content_3,
- content_4);
- /*--------------------------------------------*/
-}
-
-void phydm_fw_trace_handler_8051(void *dm_void, u8 *buffer, u8 cmd_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- int i = 0;
- u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0,
- extend_c2h_dbg_seq = 0;
- u8 fw_debug_trace[128];
- u8 *extend_c2h_dbg_content = NULL;
-
- if (cmd_len > 127)
- return;
-
- extend_c2h_sub_id = buffer[0];
- extend_c2h_dbg_len = buffer[1];
- extend_c2h_dbg_content = buffer + 2; /*DbgSeq+DbgContent for show HEX*/
-
-go_backfor_aggre_dbg_pkt:
- i = 0;
- extend_c2h_dbg_seq = buffer[2];
- extend_c2h_dbg_content = buffer + 3;
-
- for (;; i++) {
- fw_debug_trace[i] = extend_c2h_dbg_content[i];
- if (extend_c2h_dbg_content[i + 1] == '\0') {
- fw_debug_trace[i + 1] = '\0';
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "[FW DBG Msg] %s",
- &fw_debug_trace[0]);
- break;
- } else if (extend_c2h_dbg_content[i] == '\n') {
- fw_debug_trace[i + 1] = '\0';
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "[FW DBG Msg] %s",
- &fw_debug_trace[0]);
- buffer = extend_c2h_dbg_content + i + 3;
- goto go_backfor_aggre_dbg_pkt;
- }
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __ODM_DBG_H__
-#define __ODM_DBG_H__
-
-/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
-/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
-#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/
-#define ODM_DBG_TRACE 5
-
-/*FW DBG MSG*/
-#define RATE_DECISION BIT(0)
-#define INIT_RA_TABLE BIT(1)
-#define RATE_UP BIT(2)
-#define RATE_DOWN BIT(3)
-#define TRY_DONE BIT(4)
-#define RA_H2C BIT(5)
-#define F_RATE_AP_RPT BIT(7)
-
-/* -----------------------------------------------------------------------------
- * Define the tracing components
- *
- * -----------------------------------------------------------------------------
- */
-/*BB FW Functions*/
-#define PHYDM_FW_COMP_RA BIT(0)
-#define PHYDM_FW_COMP_MU BIT(1)
-#define PHYDM_FW_COMP_PATH_DIV BIT(2)
-#define PHYDM_FW_COMP_PHY_CONFIG BIT(3)
-
-/*BB Driver Functions*/
-#define ODM_COMP_DIG BIT(0)
-#define ODM_COMP_RA_MASK BIT(1)
-#define ODM_COMP_DYNAMIC_TXPWR BIT(2)
-#define ODM_COMP_FA_CNT BIT(3)
-#define ODM_COMP_RSSI_MONITOR BIT(4)
-#define ODM_COMP_SNIFFER BIT(5)
-#define ODM_COMP_ANT_DIV BIT(6)
-#define ODM_COMP_DFS BIT(7)
-#define ODM_COMP_NOISY_DETECT BIT(8)
-#define ODM_COMP_RATE_ADAPTIVE BIT(9)
-#define ODM_COMP_PATH_DIV BIT(10)
-#define ODM_COMP_CCX BIT(11)
-
-#define ODM_COMP_DYNAMIC_PRICCA BIT(12)
-/*BIT13 TBD*/
-#define ODM_COMP_MP BIT(14)
-#define ODM_COMP_CFO_TRACKING BIT(15)
-#define ODM_COMP_ACS BIT(16)
-#define PHYDM_COMP_ADAPTIVITY BIT(17)
-#define PHYDM_COMP_RA_DBG BIT(18)
-#define PHYDM_COMP_TXBF BIT(19)
-/* MAC Functions */
-#define ODM_COMP_EDCA_TURBO BIT(20)
-#define ODM_COMP_DYNAMIC_RX_PATH BIT(21)
-#define ODM_FW_DEBUG_TRACE BIT(22)
-/* RF Functions */
-/*BIT23 TBD*/
-#define ODM_COMP_TX_PWR_TRACK BIT(24)
-/*BIT25 TBD*/
-#define ODM_COMP_CALIBRATION BIT(26)
-/* Common Functions */
-/*BIT27 TBD*/
-#define ODM_PHY_CONFIG BIT(28)
-#define ODM_COMP_INIT BIT(29)
-#define ODM_COMP_COMMON BIT(30)
-#define ODM_COMP_API BIT(31)
-
-#define ODM_COMP_UNCOND 0xFFFFFFFF
-
-/*------------------------Export Marco Definition---------------------------*/
-
-#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
-
-#define ODM_RT_TRACE(dm, comp, fmt, ...) \
- do { \
- if (((comp) & dm->debug_components) || \
- ((comp) == ODM_COMP_UNCOND)) \
- RT_TRACE(dm->adapter, COMP_PHYDM, DBG_DMESG, fmt, \
- ##__VA_ARGS__); \
- } while (0)
-
-#define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/
-#define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/
-#define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/
-#define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/
-
-void phydm_init_debug_setting(struct phy_dm_struct *dm);
-
-u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
-
-void phydm_release_bb_dbg_port(void *dm_void);
-
-u32 phydm_get_bb_dbg_port_value(void *dm_void);
-
-void phydm_basic_dbg_message(void *dm_void);
-
-#define PHYDM_DBGPRINT 0
-#define MAX_ARGC 20
-#define MAX_ARGV 16
-#define DCMD_DECIMAL "%d"
-#define DCMD_CHAR "%c"
-#define DCMD_HEX "%x"
-
-#define PHYDM_SSCANF(x, y, z) \
- do { \
- if (sscanf(x, y, z) != 1) \
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, \
- "%s:%d sscanf fail!", __func__, \
- __LINE__); \
- } while (0)
-
-#define PHYDM_VAST_INFO_SNPRINTF(msg, ...) \
- do { \
- snprintf(msg, ##__VA_ARGS__); \
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output); \
- } while (0)
-
-#if (PHYDM_DBGPRINT == 1)
-#define PHYDM_SNPRINTF(msg, ...) \
- do { \
- snprintf(msg, ##__VA_ARGS__); \
- ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output); \
- } while (0)
-#else
-#define PHYDM_SNPRINTF(msg, ...) \
- do { \
- if (out_len > used) \
- used += snprintf(msg, ##__VA_ARGS__); \
- } while (0)
-#endif
-
-void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
- u32 *_out_len);
-s32 phydm_cmd(struct phy_dm_struct *dm, char *input, u32 in_len, u8 flag,
- char *output, u32 out_len);
-void phydm_cmd_parser(struct phy_dm_struct *dm, char input[][16], u32 input_num,
- u8 flag, char *output, u32 out_len);
-
-bool phydm_api_trx_mode(struct phy_dm_struct *dm, enum odm_rf_path tx_path,
- enum odm_rf_path rx_path, bool is_tx2_path);
-
-void phydm_fw_trace_en_h2c(void *dm_void, bool enable, u32 fw_debug_component,
- u32 monitor_mode, u32 macid);
-
-void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-
-void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
-
-void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-
-#endif /* __ODM_DBG_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDM_DFS_H__
-#define __PHYDM_DFS_H__
-
-#define DFS_VERSION "0.0"
-
-/* ============================================================
- * Definition
- * ============================================================
- */
-
-/* ============================================================
- * 1 structure
- * ============================================================
- */
-
-/* ============================================================
- * enumeration
- * ============================================================
- */
-
-enum phydm_dfs_region_domain {
- PHYDM_DFS_DOMAIN_UNKNOWN = 0,
- PHYDM_DFS_DOMAIN_FCC = 1,
- PHYDM_DFS_DOMAIN_MKK = 2,
- PHYDM_DFS_DOMAIN_ETSI = 3,
-};
-
-/* ============================================================
- * function prototype
- * ============================================================
- */
-#define phydm_dfs_master_enabled(dm) false
-
-#endif /*#ifndef __PHYDM_DFS_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-static int get_igi_for_diff(int);
-
-static inline void phydm_check_ap_write_dig(struct phy_dm_struct *dm,
- u8 current_igi)
-{
- switch (*dm->one_path_cca) {
- case ODM_CCA_2R:
- odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm),
- current_igi);
-
- if (dm->rf_type > ODM_1T1R)
- odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm),
- current_igi);
- break;
- case ODM_CCA_1R_A:
- odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm),
- current_igi);
- if (dm->rf_type != ODM_1T1R)
- odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm),
- get_igi_for_diff(current_igi));
- break;
- case ODM_CCA_1R_B:
- odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm),
- get_igi_for_diff(current_igi));
- if (dm->rf_type != ODM_1T1R)
- odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm),
- current_igi);
- break;
- }
-}
-
-static inline u8 phydm_get_current_igi(u8 dig_max_of_min, u8 rssi_min,
- u8 current_igi)
-{
- if (rssi_min < dig_max_of_min) {
- if (current_igi < rssi_min)
- return rssi_min;
- } else {
- if (current_igi < dig_max_of_min)
- return dig_max_of_min;
- }
- return current_igi;
-}
-
-void odm_change_dynamic_init_gain_thresh(void *dm_void, u32 dm_type,
- u32 dm_value)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
-
- if (dm_type == DIG_TYPE_THRESH_HIGH) {
- dig_tab->rssi_high_thresh = dm_value;
- } else if (dm_type == DIG_TYPE_THRESH_LOW) {
- dig_tab->rssi_low_thresh = dm_value;
- } else if (dm_type == DIG_TYPE_ENABLE) {
- dig_tab->dig_enable_flag = true;
- } else if (dm_type == DIG_TYPE_DISABLE) {
- dig_tab->dig_enable_flag = false;
- } else if (dm_type == DIG_TYPE_BACKOFF) {
- if (dm_value > 30)
- dm_value = 30;
- dig_tab->backoff_val = (u8)dm_value;
- } else if (dm_type == DIG_TYPE_RX_GAIN_MIN) {
- if (dm_value == 0)
- dm_value = 0x1;
- dig_tab->rx_gain_range_min = (u8)dm_value;
- } else if (dm_type == DIG_TYPE_RX_GAIN_MAX) {
- if (dm_value > 0x50)
- dm_value = 0x50;
- dig_tab->rx_gain_range_max = (u8)dm_value;
- }
-} /* dm_change_dynamic_init_gain_thresh */
-
-static int get_igi_for_diff(int value_IGI)
-{
-#define ONERCCA_LOW_TH 0x30
-#define ONERCCA_LOW_DIFF 8
-
- if (value_IGI < ONERCCA_LOW_TH) {
- if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
- return ONERCCA_LOW_TH;
- else
- return value_IGI + ONERCCA_LOW_DIFF;
- }
-
- return value_IGI;
-}
-
-static void odm_fa_threshold_check(void *dm_void, bool is_dfs_band,
- bool is_performance, u32 rx_tp, u32 tx_tp,
- u32 *dm_FA_thres)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->is_linked && (is_performance || is_dfs_band)) {
- /*For NIC*/
- dm_FA_thres[0] = DM_DIG_FA_TH0;
- dm_FA_thres[1] = DM_DIG_FA_TH1;
- dm_FA_thres[2] = DM_DIG_FA_TH2;
- } else {
- if (is_dfs_band) {
- /* For DFS band and no link */
- dm_FA_thres[0] = 250;
- dm_FA_thres[1] = 1000;
- dm_FA_thres[2] = 2000;
- } else {
- dm_FA_thres[0] = 2000;
- dm_FA_thres[1] = 4000;
- dm_FA_thres[2] = 5000;
- }
- }
-}
-
-static u8 odm_forbidden_igi_check(void *dm_void, u8 dig_dynamic_min,
- u8 current_igi)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- struct false_alarm_stat *fa_cnt =
- (struct false_alarm_stat *)phydm_get_structure(
- dm, PHYDM_FALSEALMCNT);
- u8 rx_gain_range_min = dig_tab->rx_gain_range_min;
-
- if (dig_tab->large_fa_timeout) {
- if (--dig_tab->large_fa_timeout == 0)
- dig_tab->large_fa_hit = 0;
- }
-
- if (fa_cnt->cnt_all > 10000) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Abnormally false alarm case.\n", __func__);
-
- if (dig_tab->large_fa_hit != 3)
- dig_tab->large_fa_hit++;
-
- if (dig_tab->forbidden_igi < current_igi) {
- dig_tab->forbidden_igi = current_igi;
- dig_tab->large_fa_hit = 1;
- dig_tab->large_fa_timeout = LARGE_FA_TIMEOUT;
- }
-
- if (dig_tab->large_fa_hit >= 3) {
- if ((dig_tab->forbidden_igi + 2) >
- dig_tab->rx_gain_range_max)
- rx_gain_range_min = dig_tab->rx_gain_range_max;
- else
- rx_gain_range_min =
- (dig_tab->forbidden_igi + 2);
- dig_tab->recover_cnt = 1800;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): Abnormally false alarm case: recover_cnt = %d\n",
- __func__, dig_tab->recover_cnt);
- }
- }
-
- else if (fa_cnt->cnt_all > 2000) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "Abnormally false alarm case.\n");
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "cnt_all=%d, cnt_all_pre=%d, current_igi=0x%x, pre_ig_value=0x%x\n",
- fa_cnt->cnt_all, fa_cnt->cnt_all_pre, current_igi,
- dig_tab->pre_ig_value);
-
- /* fa_cnt->cnt_all = 1.1875*fa_cnt->cnt_all_pre */
- if ((fa_cnt->cnt_all >
- (fa_cnt->cnt_all_pre + (fa_cnt->cnt_all_pre >> 3) +
- (fa_cnt->cnt_all_pre >> 4))) &&
- current_igi < dig_tab->pre_ig_value) {
- if (dig_tab->large_fa_hit != 3)
- dig_tab->large_fa_hit++;
-
- if (dig_tab->forbidden_igi < current_igi) {
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "Updating forbidden_igi by current_igi, forbidden_igi=0x%x, current_igi=0x%x\n",
- dig_tab->forbidden_igi, current_igi);
-
- dig_tab->forbidden_igi = current_igi;
- dig_tab->large_fa_hit = 1;
- dig_tab->large_fa_timeout = LARGE_FA_TIMEOUT;
- }
- }
-
- if (dig_tab->large_fa_hit >= 3) {
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "FaHit is greater than 3, rx_gain_range_max=0x%x, rx_gain_range_min=0x%x, forbidden_igi=0x%x\n",
- dig_tab->rx_gain_range_max, rx_gain_range_min,
- dig_tab->forbidden_igi);
-
- if ((dig_tab->forbidden_igi + 1) >
- dig_tab->rx_gain_range_max)
- rx_gain_range_min = dig_tab->rx_gain_range_max;
- else
- rx_gain_range_min =
- (dig_tab->forbidden_igi + 1);
-
- dig_tab->recover_cnt = 1200;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "Abnormally false alarm case: recover_cnt = %d, rx_gain_range_min = 0x%x\n",
- dig_tab->recover_cnt, rx_gain_range_min);
- }
- } else {
- if (dig_tab->recover_cnt != 0) {
- dig_tab->recover_cnt--;
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Normal Case: recover_cnt = %d\n",
- __func__, dig_tab->recover_cnt);
- return rx_gain_range_min;
- }
-
- if (dig_tab->large_fa_hit >= 3) {
- dig_tab->large_fa_hit = 0;
- return rx_gain_range_min;
- }
-
- if ((dig_tab->forbidden_igi - 2) <
- dig_dynamic_min) { /* DM_DIG_MIN) */
- dig_tab->forbidden_igi =
- dig_dynamic_min; /* DM_DIG_MIN; */
- rx_gain_range_min = dig_dynamic_min; /* DM_DIG_MIN; */
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Normal Case: At Lower Bound\n",
- __func__);
- } else {
- if (dig_tab->large_fa_hit == 0) {
- dig_tab->forbidden_igi -= 2;
- rx_gain_range_min =
- (dig_tab->forbidden_igi + 2);
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): Normal Case: Approach Lower Bound\n",
- __func__);
- }
- }
- }
-
- return rx_gain_range_min;
-}
-
-static void phydm_set_big_jump_step(void *dm_void, u8 current_igi)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
- u8 i;
-
- if (dig_tab->enable_adjust_big_jump == 0)
- return;
-
- for (i = 0; i <= dig_tab->big_jump_step1; i++) {
- if ((current_igi + step1[i]) >
- dig_tab->big_jump_lmt[dig_tab->agc_table_idx]) {
- if (i != 0)
- i = i - 1;
- break;
- } else if (i == dig_tab->big_jump_step1) {
- break;
- }
- }
- if (dm->support_ic_type & ODM_RTL8822B)
- odm_set_bb_reg(dm, 0x8c8, 0xe, i);
- else if (dm->support_ic_type & ODM_RTL8197F)
- odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): bigjump = %d (ori = 0x%x), LMT=0x%x\n", __func__, i,
- dig_tab->big_jump_step1,
- dig_tab->big_jump_lmt[dig_tab->agc_table_idx]);
-}
-
-void odm_write_dig(void *dm_void, u8 current_igi)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
-
- if (dig_tab->is_stop_dig) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Stop Writing IGI\n",
- __func__);
- return;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): ODM_REG(IGI_A,dm)=0x%x, ODM_BIT(IGI,dm)=0x%x\n",
- __func__, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
-
- /* 1 Check initial gain by upper bound */
- if (!dig_tab->is_psd_in_progress && dm->is_linked) {
- if (current_igi > dig_tab->rx_gain_range_max) {
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): current_igi(0x%02x) is larger than upper bound !!\n",
- __func__, current_igi);
- current_igi = dig_tab->rx_gain_range_max;
- }
- if (dm->support_ability & ODM_BB_ADAPTIVITY &&
- dm->adaptivity_flag) {
- if (current_igi > dm->adaptivity_igi_upper)
- current_igi = dm->adaptivity_igi_upper;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): adaptivity case: Force upper bound to 0x%x !!!!!!\n",
- __func__, current_igi);
- }
- }
-
- if (dig_tab->cur_ig_value != current_igi) {
- /* Modify big jump step for 8822B and 8197F */
- if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F))
- phydm_set_big_jump_step(dm, current_igi);
-
- /* Set IGI value of CCK for new CCK AGC */
- if (dm->cck_new_agc) {
- if (dm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE)
- odm_set_bb_reg(dm, 0xa0c, 0x00003f00,
- (current_igi >> 1));
- }
-
- /*Add by YuChen for USB IO too slow issue*/
- if ((dm->support_ability & ODM_BB_ADAPTIVITY) &&
- current_igi > dig_tab->cur_ig_value) {
- dig_tab->cur_ig_value = current_igi;
- phydm_adaptivity(dm);
- }
-
- /* 1 Set IGI value */
- if (dm->support_platform & (ODM_WIN | ODM_CE)) {
- odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm),
- current_igi);
-
- if (dm->rf_type > ODM_1T1R)
- odm_set_bb_reg(dm, ODM_REG(IGI_B, dm),
- ODM_BIT(IGI, dm), current_igi);
-
- } else if (dm->support_platform & (ODM_AP)) {
- phydm_check_ap_write_dig(dm, current_igi);
- }
-
- dig_tab->cur_ig_value = current_igi;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): current_igi(0x%02x).\n", __func__,
- current_igi);
-}
-
-void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
- enum phydm_pause_level pause_level, u8 igi_value)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- s8 max_level;
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s()=========> level = %d\n", __func__,
- pause_level);
-
- if (dig_tab->pause_dig_level == 0 &&
- (!(dm->support_ability & ODM_BB_DIG) ||
- !(dm->support_ability & ODM_BB_FA_CNT))) {
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): Return: support_ability DIG or FA is disabled !!\n",
- __func__);
- return;
- }
-
- if (pause_level > DM_DIG_MAX_PAUSE_TYPE) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Return: Wrong pause level !!\n", __func__);
- return;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): pause level = 0x%x, Current value = 0x%x\n",
- __func__, dig_tab->pause_dig_level, igi_value);
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
- __func__, dig_tab->pause_dig_value[7],
- dig_tab->pause_dig_value[6], dig_tab->pause_dig_value[5],
- dig_tab->pause_dig_value[4], dig_tab->pause_dig_value[3],
- dig_tab->pause_dig_value[2], dig_tab->pause_dig_value[1],
- dig_tab->pause_dig_value[0]);
-
- switch (pause_type) {
- /* Pause DIG */
- case PHYDM_PAUSE: {
- /* Disable DIG */
- odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY,
- dm->support_ability & (~ODM_BB_DIG));
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Pause DIG !!\n",
- __func__);
-
- /* Backup IGI value */
- if (dig_tab->pause_dig_level == 0) {
- dig_tab->igi_backup = dig_tab->cur_ig_value;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): Backup IGI = 0x%x, new IGI = 0x%x\n",
- __func__, dig_tab->igi_backup, igi_value);
- }
-
- /* Record IGI value */
- dig_tab->pause_dig_value[pause_level] = igi_value;
-
- /* Update pause level */
- dig_tab->pause_dig_level =
- (dig_tab->pause_dig_level | BIT(pause_level));
-
- /* Write new IGI value */
- if (BIT(pause_level + 1) > dig_tab->pause_dig_level) {
- odm_write_dig(dm, igi_value);
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): IGI of higher level = 0x%x\n",
- __func__, igi_value);
- }
- break;
- }
- /* Resume DIG */
- case PHYDM_RESUME: {
- /* check if the level is illegal or not */
- if ((dig_tab->pause_dig_level & (BIT(pause_level))) != 0) {
- dig_tab->pause_dig_level = dig_tab->pause_dig_level &
- (~(BIT(pause_level)));
- dig_tab->pause_dig_value[pause_level] = 0;
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Resume DIG !!\n",
- __func__);
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Wrong resume level !!\n", __func__);
- break;
- }
-
- /* Resume DIG */
- if (dig_tab->pause_dig_level == 0) {
- /* Write backup IGI value */
- odm_write_dig(dm, dig_tab->igi_backup);
- dig_tab->is_ignore_dig = true;
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Write original IGI = 0x%x\n",
- __func__, dig_tab->igi_backup);
-
- /* Enable DIG */
- odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY,
- dm->support_ability | ODM_BB_DIG);
- break;
- }
-
- if (BIT(pause_level) <= dig_tab->pause_dig_level)
- break;
-
- /* Calculate the maximum level now */
- for (max_level = (pause_level - 1); max_level >= 0;
- max_level--) {
- if ((dig_tab->pause_dig_level & BIT(max_level)) > 0)
- break;
- }
-
- /* pin max_level to be >= 0 */
- max_level = max_t(s8, 0, max_level);
- /* write IGI of lower level */
- odm_write_dig(dm, dig_tab->pause_dig_value[max_level]);
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Write IGI (0x%x) of level (%d)\n", __func__,
- dig_tab->pause_dig_value[max_level], max_level);
- break;
- }
- default:
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Wrong type !!\n",
- __func__);
- break;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): pause level = 0x%x, Current value = 0x%x\n",
- __func__, dig_tab->pause_dig_level, igi_value);
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
- __func__, dig_tab->pause_dig_value[7],
- dig_tab->pause_dig_value[6], dig_tab->pause_dig_value[5],
- dig_tab->pause_dig_value[4], dig_tab->pause_dig_value[3],
- dig_tab->pause_dig_value[2], dig_tab->pause_dig_value[1],
- dig_tab->pause_dig_value[0]);
-}
-
-static bool odm_dig_abort(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
-
- /* support_ability */
- if (!(dm->support_ability & ODM_BB_FA_CNT)) {
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): Return: support_ability ODM_BB_FA_CNT is disabled\n",
- __func__);
- return true;
- }
-
- /* support_ability */
- if (!(dm->support_ability & ODM_BB_DIG)) {
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): Return: support_ability ODM_BB_DIG is disabled\n",
- __func__);
- return true;
- }
-
- /* ScanInProcess */
- if (*dm->is_scan_in_process) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Return: In Scan Progress\n", __func__);
- return true;
- }
-
- if (dig_tab->is_ignore_dig) {
- dig_tab->is_ignore_dig = false;
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Return: Ignore DIG\n",
- __func__);
- return true;
- }
-
- /* add by Neil Chen to avoid PSD is processing */
- if (!dm->is_dm_initial_gain_enable) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Return: PSD is Processing\n", __func__);
- return true;
- }
-
- return false;
-}
-
-void odm_dig_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- u32 ret_value;
- u8 i;
-
- dig_tab->is_stop_dig = false;
- dig_tab->is_ignore_dig = false;
- dig_tab->is_psd_in_progress = false;
- dig_tab->cur_ig_value =
- (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
- dig_tab->pre_ig_value = 0;
- dig_tab->rssi_low_thresh = DM_DIG_THRESH_LOW;
- dig_tab->rssi_high_thresh = DM_DIG_THRESH_HIGH;
- dig_tab->fa_low_thresh = DM_FALSEALARM_THRESH_LOW;
- dig_tab->fa_high_thresh = DM_FALSEALARM_THRESH_HIGH;
- dig_tab->backoff_val = DM_DIG_BACKOFF_DEFAULT;
- dig_tab->backoff_val_range_max = DM_DIG_BACKOFF_MAX;
- dig_tab->backoff_val_range_min = DM_DIG_BACKOFF_MIN;
- dig_tab->pre_cck_cca_thres = 0xFF;
- dig_tab->cur_cck_cca_thres = 0x83;
- dig_tab->forbidden_igi = DM_DIG_MIN_NIC;
- dig_tab->large_fa_hit = 0;
- dig_tab->large_fa_timeout = 0;
- dig_tab->recover_cnt = 0;
- dig_tab->is_media_connect_0 = false;
- dig_tab->is_media_connect_1 = false;
-
- /*To initialize dm->is_dm_initial_gain_enable==false to avoid DIG err*/
- dm->is_dm_initial_gain_enable = true;
-
- dig_tab->dig_dynamic_min_0 = DM_DIG_MIN_NIC;
- dig_tab->dig_dynamic_min_1 = DM_DIG_MIN_NIC;
-
- /* To Initi BT30 IGI */
- dig_tab->bt30_cur_igi = 0x32;
-
- odm_memory_set(dm, dig_tab->pause_dig_value, 0,
- (DM_DIG_MAX_PAUSE_TYPE + 1));
- dig_tab->pause_dig_level = 0;
- odm_memory_set(dm, dig_tab->pause_cckpd_value, 0,
- (DM_DIG_MAX_PAUSE_TYPE + 1));
- dig_tab->pause_cckpd_level = 0;
-
- dig_tab->rx_gain_range_max = DM_DIG_MAX_NIC;
- dig_tab->rx_gain_range_min = DM_DIG_MIN_NIC;
-
- dig_tab->enable_adjust_big_jump = 1;
- if (dm->support_ic_type & ODM_RTL8822B) {
- ret_value = odm_get_bb_reg(dm, 0x8c8, MASKLWORD);
- dig_tab->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
- dig_tab->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
- dig_tab->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
-
- } else if (dm->support_ic_type & ODM_RTL8197F) {
- ret_value =
- odm_get_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, MASKLWORD);
- dig_tab->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
- dig_tab->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
- dig_tab->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
- }
- if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) {
- for (i = 0; i < sizeof(dig_tab->big_jump_lmt); i++) {
- if (dig_tab->big_jump_lmt[i] == 0)
- dig_tab->big_jump_lmt[i] =
- 0x64; /* Set -10dBm as default value */
- }
- }
-}
-
-void odm_DIG(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- /* Common parameters */
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- struct false_alarm_stat *fa_cnt =
- (struct false_alarm_stat *)phydm_get_structure(
- dm, PHYDM_FALSEALMCNT);
- bool first_connect, first_dis_connect;
- u8 dig_max_of_min, dig_dynamic_min;
- u8 dm_dig_max, dm_dig_min;
- u8 current_igi = dig_tab->cur_ig_value;
- u8 offset;
- u32 dm_FA_thres[3];
- u32 tx_tp = 0, rx_tp = 0;
- bool is_dfs_band = false;
- bool is_performance = true, is_first_tp_target = false,
- is_first_coverage = false;
-
- if (odm_dig_abort(dm))
- return;
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG Start===>\n");
-
- /* 1 Update status */
- {
- dig_dynamic_min = dig_tab->dig_dynamic_min_0;
- first_connect = (dm->is_linked) && !dig_tab->is_media_connect_0;
- first_dis_connect =
- (!dm->is_linked) && dig_tab->is_media_connect_0;
- }
-
- /* 1 Boundary Decision */
- {
- /* 2 For WIN\CE */
- if (dm->support_ic_type >= ODM_RTL8188E)
- dm_dig_max = 0x5A;
- else
- dm_dig_max = DM_DIG_MAX_NIC;
-
- if (dm->support_ic_type != ODM_RTL8821)
- dm_dig_min = DM_DIG_MIN_NIC;
- else
- dm_dig_min = 0x1C;
-
- dig_max_of_min = DM_DIG_MAX_AP;
-
- /* Modify lower bound for DFS band */
- if ((((*dm->channel >= 52) && (*dm->channel <= 64)) ||
- ((*dm->channel >= 100) && (*dm->channel <= 140))) &&
- phydm_dfs_master_enabled(dm)) {
- is_dfs_band = true;
- if (*dm->band_width == ODM_BW20M)
- dm_dig_min = DM_DIG_MIN_AP_DFS + 2;
- else
- dm_dig_min = DM_DIG_MIN_AP_DFS;
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "DIG: ====== In DFS band ======\n");
- }
- }
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "DIG: Absolutly upper bound = 0x%x, lower bound = 0x%x\n",
- dm_dig_max, dm_dig_min);
-
- if (dm->pu1_forced_igi_lb && (*dm->pu1_forced_igi_lb > 0)) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG: Force IGI lb to: 0x%02x\n",
- *dm->pu1_forced_igi_lb);
- dm_dig_min = *dm->pu1_forced_igi_lb;
- dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) :
- (dm_dig_min + 1);
- }
-
- /* 1 Adjust boundary by RSSI */
- if (dm->is_linked && is_performance) {
- /* 2 Modify DIG upper bound */
- /* 4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT */
- if ((dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8723B |
- ODM_RTL8812 | ODM_RTL8821)) &&
- dm->is_bt_limited_dig == 1) {
- offset = 10;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: Coex. case: Force upper bound to RSSI + %d\n",
- offset);
- } else {
- offset = 15;
- }
-
- if ((dm->rssi_min + offset) > dm_dig_max)
- dig_tab->rx_gain_range_max = dm_dig_max;
- else if ((dm->rssi_min + offset) < dm_dig_min)
- dig_tab->rx_gain_range_max = dm_dig_min;
- else
- dig_tab->rx_gain_range_max = dm->rssi_min + offset;
-
- /* 2 Modify DIG lower bound */
- /* if(dm->is_one_entry_only) */
- {
- if (dm->rssi_min < dm_dig_min)
- dig_dynamic_min = dm_dig_min;
- else if (dm->rssi_min > dig_max_of_min)
- dig_dynamic_min = dig_max_of_min;
- else
- dig_dynamic_min = dm->rssi_min;
-
- if (is_dfs_band) {
- dig_dynamic_min = dm_dig_min;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: DFS band: Force lower bound to 0x%x after link\n",
- dm_dig_min);
- }
- }
- } else {
- if (is_performance && is_dfs_band) {
- dig_tab->rx_gain_range_max = 0x28;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: DFS band: Force upper bound to 0x%x before link\n",
- dig_tab->rx_gain_range_max);
- } else {
- if (is_performance)
- dig_tab->rx_gain_range_max = DM_DIG_MAX_OF_MIN;
- else
- dig_tab->rx_gain_range_max = dm_dig_max;
- }
- dig_dynamic_min = dm_dig_min;
- }
-
- /* 1 Force Lower Bound for AntDiv */
- if (dm->is_linked && !dm->is_one_entry_only &&
- (dm->support_ic_type & ODM_ANTDIV_SUPPORT) &&
- (dm->support_ability & ODM_BB_ANT_DIV)) {
- if (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
- dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
- if (dig_tab->ant_div_rssi_max > dig_max_of_min)
- dig_dynamic_min = dig_max_of_min;
- else
- dig_dynamic_min = (u8)dig_tab->ant_div_rssi_max;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: AntDiv case: Force lower bound to 0x%x\n",
- dig_dynamic_min);
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "DIG: AntDiv case: rssi_max = 0x%x\n",
- dig_tab->ant_div_rssi_max);
- }
- }
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: Adjust boundary by RSSI Upper bound = 0x%x, Lower bound = 0x%x\n",
- dig_tab->rx_gain_range_max, dig_dynamic_min);
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: Link status: is_linked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n",
- dm->is_linked, dm->rssi_min, first_connect, first_dis_connect);
-
- /* 1 Modify DIG lower bound, deal with abnormal case */
- /* 2 Abnormal false alarm case */
- if (is_dfs_band) {
- dig_tab->rx_gain_range_min = dig_dynamic_min;
- } else {
- if (!dm->is_linked) {
- dig_tab->rx_gain_range_min = dig_dynamic_min;
-
- if (first_dis_connect)
- dig_tab->forbidden_igi = dig_dynamic_min;
- } else {
- dig_tab->rx_gain_range_min = odm_forbidden_igi_check(
- dm, dig_dynamic_min, current_igi);
- }
- }
-
- /* 2 Abnormal # beacon case */
- if (dm->is_linked && !first_connect) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "Beacon Num (%d)\n",
- dm->phy_dbg_info.num_qry_beacon_pkt);
- if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
- dm->bsta_state) {
- dig_tab->rx_gain_range_min = 0x1c;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: Abnormal #beacon (%d) case in STA mode: Force lower bound to 0x%x\n",
- dm->phy_dbg_info.num_qry_beacon_pkt,
- dig_tab->rx_gain_range_min);
- }
- }
-
- /* 2 Abnormal lower bound case */
- if (dig_tab->rx_gain_range_min > dig_tab->rx_gain_range_max) {
- dig_tab->rx_gain_range_min = dig_tab->rx_gain_range_max;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: Abnormal lower bound case: Force lower bound to 0x%x\n",
- dig_tab->rx_gain_range_min);
- }
-
- /* 1 False alarm threshold decision */
- odm_fa_threshold_check(dm, is_dfs_band, is_performance, rx_tp, tx_tp,
- dm_FA_thres);
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "DIG: False alarm threshold = %d, %d, %d\n",
- dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2]);
-
- /* 1 Adjust initial gain by false alarm */
- if (dm->is_linked && is_performance) {
- /* 2 After link */
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG: Adjust IGI after link\n");
-
- if (is_first_tp_target || (first_connect && is_performance)) {
- dig_tab->large_fa_hit = 0;
-
- if (is_dfs_band) {
- u8 rssi = dm->rssi_min;
-
- current_igi =
- (dm->rssi_min > 0x28) ? 0x28 : rssi;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: DFS band: One-shot to 0x28 upmost\n");
- } else {
- current_igi = phydm_get_current_igi(
- dig_max_of_min, dm->rssi_min,
- current_igi);
- }
-
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: First connect case: IGI does on-shot to 0x%x\n",
- current_igi);
-
- } else {
- if (fa_cnt->cnt_all > dm_FA_thres[2])
- current_igi = current_igi + 4;
- else if (fa_cnt->cnt_all > dm_FA_thres[1])
- current_igi = current_igi + 2;
- else if (fa_cnt->cnt_all < dm_FA_thres[0])
- current_igi = current_igi - 2;
-
- /* 4 Abnormal # beacon case */
- if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
- fa_cnt->cnt_all < DM_DIG_FA_TH1 &&
- dm->bsta_state) {
- current_igi = dig_tab->rx_gain_range_min;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n",
- dm->phy_dbg_info.num_qry_beacon_pkt,
- current_igi);
- }
- }
- } else {
- /* 2 Before link */
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG: Adjust IGI before link\n");
-
- if (first_dis_connect || is_first_coverage) {
- current_igi = dm_dig_min;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "DIG: First disconnect case: IGI does on-shot to lower bound\n");
- } else {
- if (fa_cnt->cnt_all > dm_FA_thres[2])
- current_igi = current_igi + 4;
- else if (fa_cnt->cnt_all > dm_FA_thres[1])
- current_igi = current_igi + 2;
- else if (fa_cnt->cnt_all < dm_FA_thres[0])
- current_igi = current_igi - 2;
- }
- }
-
- /* 1 Check initial gain by upper/lower bound */
- if (current_igi < dig_tab->rx_gain_range_min)
- current_igi = dig_tab->rx_gain_range_min;
-
- if (current_igi > dig_tab->rx_gain_range_max)
- current_igi = dig_tab->rx_gain_range_max;
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG: cur_ig_value=0x%x, TotalFA = %d\n",
- current_igi, fa_cnt->cnt_all);
-
- /* 1 Update status */
- if (dm->is_bt_hs_operation) {
- if (dm->is_linked) {
- if (dig_tab->bt30_cur_igi > (current_igi))
- odm_write_dig(dm, current_igi);
- else
- odm_write_dig(dm, dig_tab->bt30_cur_igi);
-
- dig_tab->is_media_connect_0 = dm->is_linked;
- dig_tab->dig_dynamic_min_0 = dig_dynamic_min;
- } else {
- if (dm->is_link_in_process)
- odm_write_dig(dm, 0x1c);
- else if (dm->is_bt_connect_process)
- odm_write_dig(dm, 0x28);
- else
- odm_write_dig(dm, dig_tab->bt30_cur_igi);
- }
- } else { /* BT is not using */
- odm_write_dig(dm, current_igi);
- dig_tab->is_media_connect_0 = dm->is_linked;
- dig_tab->dig_dynamic_min_0 = dig_dynamic_min;
- }
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "DIG end\n");
-}
-
-void odm_dig_by_rssi_lps(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct false_alarm_stat *fa_cnt =
- (struct false_alarm_stat *)phydm_get_structure(
- dm, PHYDM_FALSEALMCNT);
-
- u8 rssi_lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */
- u8 current_igi = dm->rssi_min;
-
- if (odm_dig_abort(dm))
- return;
-
- current_igi = current_igi + RSSI_OFFSET_DIG;
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s()==>\n", __func__);
-
- /* Using FW PS mode to make IGI */
- /* Adjust by FA in LPS MODE */
- if (fa_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
- current_igi = current_igi + 4;
- else if (fa_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
- current_igi = current_igi + 2;
- else if (fa_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
- current_igi = current_igi - 2;
-
- /* Lower bound checking */
-
- /* RSSI Lower bound check */
- if ((dm->rssi_min - 10) > DM_DIG_MIN_NIC)
- rssi_lower = (dm->rssi_min - 10);
- else
- rssi_lower = DM_DIG_MIN_NIC;
-
- /* Upper and Lower Bound checking */
- if (current_igi > DM_DIG_MAX_NIC)
- current_igi = DM_DIG_MAX_NIC;
- else if (current_igi < rssi_lower)
- current_igi = rssi_lower;
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): fa_cnt->cnt_all = %d\n", __func__,
- fa_cnt->cnt_all);
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): dm->rssi_min = %d\n", __func__,
- dm->rssi_min);
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): current_igi = 0x%x\n", __func__,
- current_igi);
-
- odm_write_dig(
- dm,
- current_igi); /* odm_write_dig(dm, dig_tab->cur_ig_value); */
-}
-
-/* 3============================================================
- * 3 FASLE ALARM CHECK
- * 3============================================================
- */
-
-void odm_false_alarm_counter_statistics(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct false_alarm_stat *false_alm_cnt =
- (struct false_alarm_stat *)phydm_get_structure(
- dm, PHYDM_FALSEALMCNT);
- struct rt_adcsmp *adc_smp = &dm->adcsmp;
- u32 ret_value;
-
- if (!(dm->support_ability & ODM_BB_FA_CNT))
- return;
-
- ODM_RT_TRACE(dm, ODM_COMP_FA_CNT, "%s()======>\n", __func__);
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES) {
- /* hold ofdm counter */
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31),
- 1); /* hold page C counter */
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31),
- 1); /* hold page D counter */
-
- ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N,
- MASKDWORD);
- false_alm_cnt->cnt_fast_fsync = (ret_value & 0xffff);
- false_alm_cnt->cnt_sb_search_fail =
- ((ret_value & 0xffff0000) >> 16);
-
- ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N,
- MASKDWORD);
- false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff);
- false_alm_cnt->cnt_parity_fail =
- ((ret_value & 0xffff0000) >> 16);
-
- ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N,
- MASKDWORD);
- false_alm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
- false_alm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
-
- ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N,
- MASKDWORD);
- false_alm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
-
- false_alm_cnt->cnt_ofdm_fail =
- false_alm_cnt->cnt_parity_fail +
- false_alm_cnt->cnt_rate_illegal +
- false_alm_cnt->cnt_crc8_fail +
- false_alm_cnt->cnt_mcs_fail +
- false_alm_cnt->cnt_fast_fsync +
- false_alm_cnt->cnt_sb_search_fail;
-
- /* read CCK CRC32 counter */
- false_alm_cnt->cnt_cck_crc32_error = odm_get_bb_reg(
- dm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, MASKDWORD);
- false_alm_cnt->cnt_cck_crc32_ok = odm_get_bb_reg(
- dm, ODM_REG_CCK_CRC32_OK_CNT_11N, MASKDWORD);
-
- /* read OFDM CRC32 counter */
- ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N,
- MASKDWORD);
- false_alm_cnt->cnt_ofdm_crc32_error =
- (ret_value & 0xffff0000) >> 16;
- false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff;
-
- /* read HT CRC32 counter */
- ret_value =
- odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
- false_alm_cnt->cnt_ht_crc32_error =
- (ret_value & 0xffff0000) >> 16;
- false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff;
-
- /* read VHT CRC32 counter */
- false_alm_cnt->cnt_vht_crc32_error = 0;
- false_alm_cnt->cnt_vht_crc32_ok = 0;
-
- {
- /* hold cck counter */
- odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
- odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
-
- ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N,
- MASKBYTE0);
- false_alm_cnt->cnt_cck_fail = ret_value;
-
- ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N,
- MASKBYTE3);
- false_alm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
-
- ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N,
- MASKDWORD);
- false_alm_cnt->cnt_cck_cca =
- ((ret_value & 0xFF) << 8) |
- ((ret_value & 0xFF00) >> 8);
- }
-
- false_alm_cnt->cnt_all_pre = false_alm_cnt->cnt_all;
-
- false_alm_cnt->cnt_all = (false_alm_cnt->cnt_fast_fsync +
- false_alm_cnt->cnt_sb_search_fail +
- false_alm_cnt->cnt_parity_fail +
- false_alm_cnt->cnt_rate_illegal +
- false_alm_cnt->cnt_crc8_fail +
- false_alm_cnt->cnt_mcs_fail +
- false_alm_cnt->cnt_cck_fail);
-
- false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca +
- false_alm_cnt->cnt_cck_cca;
-
- if (dm->support_ic_type >= ODM_RTL8188E) {
- /*reset false alarm counter registers*/
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31),
- 1);
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31),
- 0);
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27),
- 1);
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27),
- 0);
-
- /*update ofdm counter*/
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31),
- 0); /*update page C counter*/
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31),
- 0); /*update page D counter*/
-
- /*reset CCK CCA counter*/
- odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N,
- BIT(13) | BIT(12), 0);
- odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N,
- BIT(13) | BIT(12), 2);
-
- /*reset CCK FA counter*/
- odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N,
- BIT(15) | BIT(14), 0);
- odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11N,
- BIT(15) | BIT(14), 2);
-
- /*reset CRC32 counter*/
- odm_set_bb_reg(dm, ODM_REG_PAGE_F_RST_11N, BIT(16), 1);
- odm_set_bb_reg(dm, ODM_REG_PAGE_F_RST_11N, BIT(16), 0);
- }
-
- /* Get debug port 0 */
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x0);
- false_alm_cnt->dbg_port0 =
- odm_get_bb_reg(dm, ODM_REG_RPT_11N, MASKDWORD);
-
- /* Get EDCCA flag */
- odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x208);
- false_alm_cnt->edcca_flag =
- (bool)odm_get_bb_reg(dm, ODM_REG_RPT_11N, BIT(30));
-
- ODM_RT_TRACE(
- dm, ODM_COMP_FA_CNT,
- "[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n",
- false_alm_cnt->cnt_parity_fail,
- false_alm_cnt->cnt_rate_illegal,
- false_alm_cnt->cnt_crc8_fail,
- false_alm_cnt->cnt_mcs_fail,
- false_alm_cnt->cnt_fast_fsync,
- false_alm_cnt->cnt_sb_search_fail);
- }
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- u32 cck_enable;
-
- /* read OFDM FA counter */
- false_alm_cnt->cnt_ofdm_fail =
- odm_get_bb_reg(dm, ODM_REG_OFDM_FA_11AC, MASKLWORD);
-
- /* Read CCK FA counter */
- false_alm_cnt->cnt_cck_fail =
- odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
-
- /* read CCK/OFDM CCA counter */
- ret_value =
- odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
- false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
- false_alm_cnt->cnt_cck_cca = ret_value & 0xffff;
-
- /* read CCK CRC32 counter */
- ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC,
- MASKDWORD);
- false_alm_cnt->cnt_cck_crc32_error =
- (ret_value & 0xffff0000) >> 16;
- false_alm_cnt->cnt_cck_crc32_ok = ret_value & 0xffff;
-
- /* read OFDM CRC32 counter */
- ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC,
- MASKDWORD);
- false_alm_cnt->cnt_ofdm_crc32_error =
- (ret_value & 0xffff0000) >> 16;
- false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff;
-
- /* read HT CRC32 counter */
- ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC,
- MASKDWORD);
- false_alm_cnt->cnt_ht_crc32_error =
- (ret_value & 0xffff0000) >> 16;
- false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff;
-
- /* read VHT CRC32 counter */
- ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC,
- MASKDWORD);
- false_alm_cnt->cnt_vht_crc32_error =
- (ret_value & 0xffff0000) >> 16;
- false_alm_cnt->cnt_vht_crc32_ok = ret_value & 0xffff;
-
- /* reset OFDM FA counter */
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1);
- odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0);
-
- /* reset CCK FA counter */
- odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0);
- odm_set_bb_reg(dm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1);
-
- /* reset CCA counter */
- odm_set_bb_reg(dm, ODM_REG_RST_RPT_11AC, BIT(0), 1);
- odm_set_bb_reg(dm, ODM_REG_RST_RPT_11AC, BIT(0), 0);
-
- cck_enable =
- odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
- if (cck_enable) { /* if(*dm->band_type == ODM_BAND_2_4G) */
- false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail +
- false_alm_cnt->cnt_cck_fail;
- false_alm_cnt->cnt_cca_all =
- false_alm_cnt->cnt_cck_cca +
- false_alm_cnt->cnt_ofdm_cca;
- } else {
- false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail;
- false_alm_cnt->cnt_cca_all =
- false_alm_cnt->cnt_ofdm_cca;
- }
-
- if (adc_smp->adc_smp_state == ADCSMP_STATE_IDLE) {
- if (phydm_set_bb_dbg_port(
- dm, BB_DBGPORT_PRIORITY_1,
- 0x0)) { /*set debug port to 0x0*/
- false_alm_cnt->dbg_port0 =
- phydm_get_bb_dbg_port_value(dm);
- phydm_release_bb_dbg_port(dm);
- }
-
- if (phydm_set_bb_dbg_port(
- dm, BB_DBGPORT_PRIORITY_1,
- 0x209)) { /*set debug port to 0x0*/
- false_alm_cnt->edcca_flag =
- (bool)((phydm_get_bb_dbg_port_value(
- dm) &
- BIT(30)) >>
- 30);
- phydm_release_bb_dbg_port(dm);
- }
- }
- }
-
- false_alm_cnt->cnt_crc32_error_all =
- false_alm_cnt->cnt_vht_crc32_error +
- false_alm_cnt->cnt_ht_crc32_error +
- false_alm_cnt->cnt_ofdm_crc32_error +
- false_alm_cnt->cnt_cck_crc32_error;
- false_alm_cnt->cnt_crc32_ok_all = false_alm_cnt->cnt_vht_crc32_ok +
- false_alm_cnt->cnt_ht_crc32_ok +
- false_alm_cnt->cnt_ofdm_crc32_ok +
- false_alm_cnt->cnt_cck_crc32_ok;
-
- ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
- "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
- false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca,
- false_alm_cnt->cnt_cca_all);
-
- ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
- "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
- false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail,
- false_alm_cnt->cnt_all);
-
- ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
- "[CCK] CRC32 {error, ok}= {%d, %d}\n",
- false_alm_cnt->cnt_cck_crc32_error,
- false_alm_cnt->cnt_cck_crc32_ok);
- ODM_RT_TRACE(dm, ODM_COMP_FA_CNT, "[OFDM]CRC32 {error, ok}= {%d, %d}\n",
- false_alm_cnt->cnt_ofdm_crc32_error,
- false_alm_cnt->cnt_ofdm_crc32_ok);
- ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
- "[ HT ] CRC32 {error, ok}= {%d, %d}\n",
- false_alm_cnt->cnt_ht_crc32_error,
- false_alm_cnt->cnt_ht_crc32_ok);
- ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
- "[VHT] CRC32 {error, ok}= {%d, %d}\n",
- false_alm_cnt->cnt_vht_crc32_error,
- false_alm_cnt->cnt_vht_crc32_ok);
- ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
- "[VHT] CRC32 {error, ok}= {%d, %d}\n",
- false_alm_cnt->cnt_crc32_error_all,
- false_alm_cnt->cnt_crc32_ok_all);
- ODM_RT_TRACE(dm, ODM_COMP_FA_CNT,
- "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n",
- false_alm_cnt->dbg_port0, false_alm_cnt->edcca_flag);
-}
-
-/* 3============================================================
- * 3 CCK Packet Detect threshold
- * 3============================================================
- */
-
-void odm_pause_cck_packet_detection(void *dm_void,
- enum phydm_pause_type pause_type,
- enum phydm_pause_level pause_level,
- u8 cck_pd_threshold)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- s8 max_level;
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s()=========> level = %d\n", __func__,
- pause_level);
-
- if (dig_tab->pause_cckpd_level == 0 &&
- (!(dm->support_ability & ODM_BB_CCK_PD) ||
- !(dm->support_ability & ODM_BB_FA_CNT))) {
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "Return: support_ability ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n");
- return;
- }
-
- if (pause_level > DM_DIG_MAX_PAUSE_TYPE) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Return: Wrong pause level !!\n", __func__);
- return;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): pause level = 0x%x, Current value = 0x%x\n",
- __func__, dig_tab->pause_cckpd_level, cck_pd_threshold);
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
- __func__, dig_tab->pause_cckpd_value[7],
- dig_tab->pause_cckpd_value[6], dig_tab->pause_cckpd_value[5],
- dig_tab->pause_cckpd_value[4], dig_tab->pause_cckpd_value[3],
- dig_tab->pause_cckpd_value[2], dig_tab->pause_cckpd_value[1],
- dig_tab->pause_cckpd_value[0]);
-
- switch (pause_type) {
- /* Pause CCK Packet Detection threshold */
- case PHYDM_PAUSE: {
- /* Disable CCK PD */
- odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY,
- dm->support_ability & (~ODM_BB_CCK_PD));
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Pause CCK packet detection threshold !!\n",
- __func__);
-
- /*Backup original CCK PD threshold decided by CCK PD mechanism*/
- if (dig_tab->pause_cckpd_level == 0) {
- dig_tab->cck_pd_backup = dig_tab->cur_cck_cca_thres;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n",
- __func__, dig_tab->cck_pd_backup,
- cck_pd_threshold);
- }
-
- /* Update pause level */
- dig_tab->pause_cckpd_level =
- (dig_tab->pause_cckpd_level | BIT(pause_level));
-
- /* Record CCK PD threshold */
- dig_tab->pause_cckpd_value[pause_level] = cck_pd_threshold;
-
- /* Write new CCK PD threshold */
- if (BIT(pause_level + 1) > dig_tab->pause_cckpd_level) {
- odm_write_cck_cca_thres(dm, cck_pd_threshold);
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): CCKPD of higher level = 0x%x\n",
- __func__, cck_pd_threshold);
- }
- break;
- }
- /* Resume CCK Packet Detection threshold */
- case PHYDM_RESUME: {
- /* check if the level is illegal or not */
- if ((dig_tab->pause_cckpd_level & (BIT(pause_level))) != 0) {
- dig_tab->pause_cckpd_level =
- dig_tab->pause_cckpd_level &
- (~(BIT(pause_level)));
- dig_tab->pause_cckpd_value[pause_level] = 0;
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Resume CCK PD !!\n", __func__);
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Wrong resume level !!\n", __func__);
- break;
- }
-
- /* Resume DIG */
- if (dig_tab->pause_cckpd_level == 0) {
- /* Write backup IGI value */
- odm_write_cck_cca_thres(dm, dig_tab->cck_pd_backup);
- /* dig_tab->is_ignore_dig = true; */
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Write original CCKPD = 0x%x\n",
- __func__, dig_tab->cck_pd_backup);
-
- /* Enable DIG */
- odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY,
- dm->support_ability |
- ODM_BB_CCK_PD);
- break;
- }
-
- if (BIT(pause_level) <= dig_tab->pause_cckpd_level)
- break;
-
- /* Calculate the maximum level now */
- for (max_level = (pause_level - 1); max_level >= 0;
- max_level--) {
- if ((dig_tab->pause_cckpd_level & BIT(max_level)) > 0)
- break;
- }
-
- /* write CCKPD of lower level */
- odm_write_cck_cca_thres(dm,
- dig_tab->pause_cckpd_value[max_level]);
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): Write CCKPD (0x%x) of level (%d)\n",
- __func__, dig_tab->pause_cckpd_value[max_level],
- max_level);
- break;
- }
- default:
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "%s(): Wrong type !!\n",
- __func__);
- break;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG,
- "%s(): pause level = 0x%x, Current value = 0x%x\n",
- __func__, dig_tab->pause_cckpd_level, cck_pd_threshold);
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "%s(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
- __func__, dig_tab->pause_cckpd_value[7],
- dig_tab->pause_cckpd_value[6], dig_tab->pause_cckpd_value[5],
- dig_tab->pause_cckpd_value[4], dig_tab->pause_cckpd_value[3],
- dig_tab->pause_cckpd_value[2], dig_tab->pause_cckpd_value[1],
- dig_tab->pause_cckpd_value[0]);
-}
-
-void odm_cck_packet_detection_thresh(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- struct false_alarm_stat *false_alm_cnt =
- (struct false_alarm_stat *)phydm_get_structure(
- dm, PHYDM_FALSEALMCNT);
- u8 cur_cck_cca_thres = dig_tab->cur_cck_cca_thres, rssi_thd = 35;
-
- if ((!(dm->support_ability & ODM_BB_CCK_PD)) ||
- (!(dm->support_ability & ODM_BB_FA_CNT))) {
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "CCK_PD: return==========\n");
- return;
- }
-
- if (dm->ext_lna)
- return;
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "CCK_PD: ==========>\n");
-
- if (dig_tab->cck_fa_ma == 0xffffffff)
- dig_tab->cck_fa_ma = false_alm_cnt->cnt_cck_fail;
- else
- dig_tab->cck_fa_ma =
- ((dig_tab->cck_fa_ma << 1) + dig_tab->cck_fa_ma +
- false_alm_cnt->cnt_cck_fail) >>
- 2;
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "CCK_PD: CCK FA moving average = %d\n",
- dig_tab->cck_fa_ma);
-
- if (dm->is_linked) {
- if (dm->rssi_min > rssi_thd) {
- cur_cck_cca_thres = 0xcd;
- } else if (dm->rssi_min > 20) {
- if (dig_tab->cck_fa_ma >
- ((DM_DIG_FA_TH1 >> 1) + (DM_DIG_FA_TH1 >> 3)))
- cur_cck_cca_thres = 0xcd;
- else if (dig_tab->cck_fa_ma < (DM_DIG_FA_TH0 >> 1))
- cur_cck_cca_thres = 0x83;
- } else if (dm->rssi_min > 7) {
- cur_cck_cca_thres = 0x83;
- } else {
- cur_cck_cca_thres = 0x40;
- }
-
- } else {
- if (dig_tab->cck_fa_ma > 0x400)
- cur_cck_cca_thres = 0x83;
- else if (dig_tab->cck_fa_ma < 0x200)
- cur_cck_cca_thres = 0x40;
- }
-
- {
- odm_write_cck_cca_thres(dm, cur_cck_cca_thres);
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_DIG, "CCK_PD: cck_cca_th=((0x%x))\n\n",
- cur_cck_cca_thres);
-}
-
-void odm_write_cck_cca_thres(void *dm_void, u8 cur_cck_cca_thres)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dig_thres *dig_tab = &dm->dm_dig_table;
-
- if (dig_tab->cur_cck_cca_thres !=
- cur_cck_cca_thres) { /* modify by Guo.Mingzhi 2012-01-03 */
- odm_write_1byte(dm, ODM_REG(CCK_CCA, dm), cur_cck_cca_thres);
- dig_tab->cck_fa_ma = 0xffffffff;
- }
- dig_tab->pre_cck_cca_thres = dig_tab->cur_cck_cca_thres;
- dig_tab->cur_cck_cca_thres = cur_cck_cca_thres;
-}
-
-bool phydm_dig_go_up_check(void *dm_void)
-{
- bool ret = true;
-
- return ret;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMDIG_H__
-#define __PHYDMDIG_H__
-
-#define DIG_VERSION "1.32" /* 2016.09.02 YuChen. add CCK PD for 8197F*/
-
-/* Pause DIG & CCKPD */
-#define DM_DIG_MAX_PAUSE_TYPE 0x7
-
-enum dig_goupcheck_level {
- DIG_GOUPCHECK_LEVEL_0,
- DIG_GOUPCHECK_LEVEL_1,
- DIG_GOUPCHECK_LEVEL_2
-
-};
-
-struct dig_thres {
- bool is_stop_dig; /* for debug */
- bool is_ignore_dig;
- bool is_psd_in_progress;
-
- u8 dig_enable_flag;
- u8 dig_ext_port_stage;
-
- int rssi_low_thresh;
- int rssi_high_thresh;
-
- u32 fa_low_thresh;
- u32 fa_high_thresh;
-
- u8 cur_sta_connect_state;
- u8 pre_sta_connect_state;
- u8 cur_multi_sta_connect_state;
-
- u8 pre_ig_value;
- u8 cur_ig_value;
- u8 backup_ig_value; /* MP DIG */
- u8 bt30_cur_igi;
- u8 igi_backup;
-
- s8 backoff_val;
- s8 backoff_val_range_max;
- s8 backoff_val_range_min;
- u8 rx_gain_range_max;
- u8 rx_gain_range_min;
- u8 rssi_val_min;
-
- u8 pre_cck_cca_thres;
- u8 cur_cck_cca_thres;
- u8 pre_cck_pd_state;
- u8 cur_cck_pd_state;
- u8 cck_pd_backup;
- u8 pause_cckpd_level;
- u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
-
- u8 large_fa_hit;
- u8 large_fa_timeout; /*if (large_fa_hit), monitor "large_fa_timeout"
- *sec, if timeout, large_fa_hit=0
- */
- u8 forbidden_igi;
- u32 recover_cnt;
-
- u8 dig_dynamic_min_0;
- u8 dig_dynamic_min_1;
- bool is_media_connect_0;
- bool is_media_connect_1;
-
- u32 ant_div_rssi_max;
- u32 rssi_max;
-
- u8 *is_p2p_in_process;
-
- u8 pause_dig_level;
- u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
-
- u32 cck_fa_ma;
- enum dig_goupcheck_level dig_go_up_check_level;
- u8 aaa_default;
-
- u8 rf_gain_idx;
- u8 agc_table_idx;
- u8 big_jump_lmt[16];
- u8 enable_adjust_big_jump : 1;
- u8 big_jump_step1 : 3;
- u8 big_jump_step2 : 2;
- u8 big_jump_step3 : 2;
-};
-
-struct false_alarm_stat {
- u32 cnt_parity_fail;
- u32 cnt_rate_illegal;
- u32 cnt_crc8_fail;
- u32 cnt_mcs_fail;
- u32 cnt_ofdm_fail;
- u32 cnt_ofdm_fail_pre; /* For RTL8881A */
- u32 cnt_cck_fail;
- u32 cnt_all;
- u32 cnt_all_pre;
- u32 cnt_fast_fsync;
- u32 cnt_sb_search_fail;
- u32 cnt_ofdm_cca;
- u32 cnt_cck_cca;
- u32 cnt_cca_all;
- u32 cnt_bw_usc; /* Gary */
- u32 cnt_bw_lsc; /* Gary */
- u32 cnt_cck_crc32_error;
- u32 cnt_cck_crc32_ok;
- u32 cnt_ofdm_crc32_error;
- u32 cnt_ofdm_crc32_ok;
- u32 cnt_ht_crc32_error;
- u32 cnt_ht_crc32_ok;
- u32 cnt_vht_crc32_error;
- u32 cnt_vht_crc32_ok;
- u32 cnt_crc32_error_all;
- u32 cnt_crc32_ok_all;
- bool cck_block_enable;
- bool ofdm_block_enable;
- u32 dbg_port0;
- bool edcca_flag;
-};
-
-enum dm_dig_op {
- DIG_TYPE_THRESH_HIGH = 0,
- DIG_TYPE_THRESH_LOW = 1,
- DIG_TYPE_BACKOFF = 2,
- DIG_TYPE_RX_GAIN_MIN = 3,
- DIG_TYPE_RX_GAIN_MAX = 4,
- DIG_TYPE_ENABLE = 5,
- DIG_TYPE_DISABLE = 6,
- DIG_OP_TYPE_MAX
-};
-
-enum phydm_pause_type { PHYDM_PAUSE = BIT(0), PHYDM_RESUME = BIT(1) };
-
-enum phydm_pause_level {
- /* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
- PHYDM_PAUSE_LEVEL_0 = 0,
- PHYDM_PAUSE_LEVEL_1 = 1,
- PHYDM_PAUSE_LEVEL_2 = 2,
- PHYDM_PAUSE_LEVEL_3 = 3,
- PHYDM_PAUSE_LEVEL_4 = 4,
- PHYDM_PAUSE_LEVEL_5 = 5,
- PHYDM_PAUSE_LEVEL_6 = 6,
- PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */
-};
-
-#define DM_DIG_THRESH_HIGH 40
-#define DM_DIG_THRESH_LOW 35
-
-#define DM_FALSEALARM_THRESH_LOW 400
-#define DM_FALSEALARM_THRESH_HIGH 1000
-
-#define DM_DIG_MAX_NIC 0x3e
-#define DM_DIG_MIN_NIC 0x20
-#define DM_DIG_MAX_OF_MIN_NIC 0x3e
-
-#define DM_DIG_MAX_AP 0x3e
-#define DM_DIG_MIN_AP 0x20
-#define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */
-#define DM_DIG_MIN_AP_DFS 0x20
-
-#define DM_DIG_MAX_NIC_HP 0x46
-#define DM_DIG_MIN_NIC_HP 0x2e
-
-#define DM_DIG_MAX_AP_HP 0x42
-#define DM_DIG_MIN_AP_HP 0x30
-
-/* vivi 92c&92d has different definition, 20110504
- * this is for 92c
- */
-#define DM_DIG_FA_TH0 0x200 /* 0x20 */
-
-#define DM_DIG_FA_TH1 0x300
-#define DM_DIG_FA_TH2 0x400
-/* this is for 92d */
-#define DM_DIG_FA_TH0_92D 0x100
-#define DM_DIG_FA_TH1_92D 0x400
-#define DM_DIG_FA_TH2_92D 0x600
-
-#define DM_DIG_BACKOFF_MAX 12
-#define DM_DIG_BACKOFF_MIN -4
-#define DM_DIG_BACKOFF_DEFAULT 10
-
-#define DM_DIG_FA_TH0_LPS 4 /* -> 4 in lps */
-#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */
-#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */
-#define RSSI_OFFSET_DIG 0x05
-#define LARGE_FA_TIMEOUT 60
-
-void odm_change_dynamic_init_gain_thresh(void *dm_void, u32 dm_type,
- u32 dm_value);
-
-void odm_write_dig(void *dm_void, u8 current_igi);
-
-void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
- enum phydm_pause_level pause_level, u8 igi_value);
-
-void odm_dig_init(void *dm_void);
-
-void odm_DIG(void *dm_void);
-
-void odm_dig_by_rssi_lps(void *dm_void);
-
-void odm_false_alarm_counter_statistics(void *dm_void);
-
-void odm_pause_cck_packet_detection(void *dm_void,
- enum phydm_pause_type pause_type,
- enum phydm_pause_level pause_level,
- u8 cck_pd_threshold);
-
-void odm_cck_packet_detection_thresh(void *dm_void);
-
-void odm_write_cck_cca_thres(void *dm_void, u8 cur_cck_cca_thres);
-
-bool phydm_dig_go_up_check(void *dm_void);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMDYMICRXPATH_H__
-#define __PHYDMDYMICRXPATH_H__
-
-#define DYNAMIC_RX_PATH_VERSION "1.0" /*2016.07.15 Dino */
-
-#define DRP_RSSI_TH 35
-
-#define INIT_DRP_TIMMER 0
-#define CANCEL_DRP_TIMMER 1
-#define RELEASE_DRP_TIMMER 2
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-static inline void phydm_update_rf_state(struct phy_dm_struct *dm,
- struct dyn_pwr_saving *dm_ps_table,
- int _rssi_up_bound,
- int _rssi_low_bound,
- int _is_force_in_normal)
-{
- if (_is_force_in_normal) {
- dm_ps_table->cur_rf_state = rf_normal;
- return;
- }
-
- if (dm->rssi_min == 0xFF) {
- dm_ps_table->cur_rf_state = RF_MAX;
- return;
- }
-
- if (dm_ps_table->pre_rf_state == rf_normal) {
- if (dm->rssi_min >= _rssi_up_bound)
- dm_ps_table->cur_rf_state = rf_save;
- else
- dm_ps_table->cur_rf_state = rf_normal;
- } else {
- if (dm->rssi_min <= _rssi_low_bound)
- dm_ps_table->cur_rf_state = rf_normal;
- else
- dm_ps_table->cur_rf_state = rf_save;
- }
-}
-
-void odm_dynamic_bb_power_saving_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dyn_pwr_saving *dm_ps_table = &dm->dm_ps_table;
-
- dm_ps_table->pre_cca_state = CCA_MAX;
- dm_ps_table->cur_cca_state = CCA_MAX;
- dm_ps_table->pre_rf_state = RF_MAX;
- dm_ps_table->cur_rf_state = RF_MAX;
- dm_ps_table->rssi_val_min = 0;
- dm_ps_table->initialize = 0;
-}
-
-void odm_rf_saving(void *dm_void, u8 is_force_in_normal)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dyn_pwr_saving *dm_ps_table = &dm->dm_ps_table;
- u8 rssi_up_bound = 30;
- u8 rssi_low_bound = 25;
-
- if (dm->patch_id == 40) { /* RT_CID_819x_FUNAI_TV */
- rssi_up_bound = 50;
- rssi_low_bound = 45;
- }
- if (dm_ps_table->initialize == 0) {
- dm_ps_table->reg874 =
- (odm_get_bb_reg(dm, 0x874, MASKDWORD) & 0x1CC000) >> 14;
- dm_ps_table->regc70 =
- (odm_get_bb_reg(dm, 0xc70, MASKDWORD) & BIT(3)) >> 3;
- dm_ps_table->reg85c =
- (odm_get_bb_reg(dm, 0x85c, MASKDWORD) & 0xFF000000) >>
- 24;
- dm_ps_table->rega74 =
- (odm_get_bb_reg(dm, 0xa74, MASKDWORD) & 0xF000) >> 12;
- /* Reg818 = phy_query_bb_reg(adapter, 0x818, MASKDWORD); */
- dm_ps_table->initialize = 1;
- }
-
- phydm_update_rf_state(dm, dm_ps_table, rssi_up_bound, rssi_low_bound,
- is_force_in_normal);
-
- if (dm_ps_table->pre_rf_state != dm_ps_table->cur_rf_state) {
- if (dm_ps_table->cur_rf_state == rf_save) {
- odm_set_bb_reg(dm, 0x874, 0x1C0000,
- 0x2); /* reg874[20:18]=3'b010 */
- odm_set_bb_reg(dm, 0xc70, BIT(3),
- 0); /* regc70[3]=1'b0 */
- odm_set_bb_reg(dm, 0x85c, 0xFF000000,
- 0x63); /* reg85c[31:24]=0x63 */
- odm_set_bb_reg(dm, 0x874, 0xC000,
- 0x2); /* reg874[15:14]=2'b10 */
- odm_set_bb_reg(dm, 0xa74, 0xF000,
- 0x3); /* RegA75[7:4]=0x3 */
- odm_set_bb_reg(dm, 0x818, BIT(28),
- 0x0); /* Reg818[28]=1'b0 */
- odm_set_bb_reg(dm, 0x818, BIT(28),
- 0x1); /* Reg818[28]=1'b1 */
- } else {
- odm_set_bb_reg(dm, 0x874, 0x1CC000,
- dm_ps_table->reg874);
- odm_set_bb_reg(dm, 0xc70, BIT(3), dm_ps_table->regc70);
- odm_set_bb_reg(dm, 0x85c, 0xFF000000,
- dm_ps_table->reg85c);
- odm_set_bb_reg(dm, 0xa74, 0xF000, dm_ps_table->rega74);
- odm_set_bb_reg(dm, 0x818, BIT(28), 0x0);
- }
- dm_ps_table->pre_rf_state = dm_ps_table->cur_rf_state;
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__
-#define __PHYDMDYNAMICBBPOWERSAVING_H__
-
-#define DYNAMIC_BBPWRSAV_VERSION "1.1"
-
-struct dyn_pwr_saving {
- u8 pre_cca_state;
- u8 cur_cca_state;
-
- u8 pre_rf_state;
- u8 cur_rf_state;
-
- int rssi_val_min;
-
- u8 initialize;
- u32 reg874, regc70, reg85c, rega74;
-};
-
-#define dm_rf_saving odm_rf_saving
-
-void odm_rf_saving(void *dm_void, u8 is_force_in_normal);
-
-void odm_dynamic_bb_power_saving_init(void *dm_void);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-void odm_dynamic_tx_power_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- dm->last_dtp_lvl = tx_high_pwr_level_normal;
- dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
- dm->tx_agc_ofdm_18_6 =
- odm_get_bb_reg(dm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/
-}
-
-void odm_dynamic_tx_power_save_power_index(void *dm_void) {}
-
-void odm_dynamic_tx_power_restore_power_index(void *dm_void) {}
-
-void odm_dynamic_tx_power_write_power_index(void *dm_void, u8 value)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 index;
- u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
-
- for (index = 0; index < 6; index++)
- odm_write_1byte(dm, power_index_reg[index], value);
-}
-
-static void odm_dynamic_tx_power_nic_ce(void *dm_void) {}
-
-void odm_dynamic_tx_power(void *dm_void)
-{
- /* */
- /* For AP/ADSL use struct rtl8192cd_priv* */
- /* For CE/NIC use struct void* */
- /* */
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
- return;
- /* 2011/09/29 MH In HW integration first stage, we provide 4 different
- * handle to operate at the same time.
- * In the stage2/3, we need to prive universal interface and merge all
- * HW dynamic mechanism.
- */
- switch (dm->support_platform) {
- case ODM_WIN:
- odm_dynamic_tx_power_nic(dm);
- break;
- case ODM_CE:
- odm_dynamic_tx_power_nic_ce(dm);
- break;
- case ODM_AP:
- odm_dynamic_tx_power_ap(dm);
- break;
- default:
- break;
- }
-}
-
-void odm_dynamic_tx_power_nic(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
- return;
-}
-
-void odm_dynamic_tx_power_ap(void *dm_void
-
- )
-{
-}
-
-void odm_dynamic_tx_power_8821(void *dm_void, u8 *desc, u8 mac_id) {}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMDYNAMICTXPOWER_H__
-#define __PHYDMDYNAMICTXPOWER_H__
-
-/*#define DYNAMIC_TXPWR_VERSION "1.0"*/
-/*#define DYNAMIC_TXPWR_VERSION "1.3" */ /*2015.08.26, Add 8814 Dynamic TX pwr*/
-#define DYNAMIC_TXPWR_VERSION "1.4" /*2015.11.06,Add CE 8821A Dynamic TX pwr*/
-
-#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
-#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
-
-#define tx_high_pwr_level_normal 0
-#define tx_high_pwr_level_level1 1
-#define tx_high_pwr_level_level2 2
-
-#define tx_high_pwr_level_bt1 3
-#define tx_high_pwr_level_bt2 4
-#define tx_high_pwr_level_15 5
-#define tx_high_pwr_level_35 6
-#define tx_high_pwr_level_50 7
-#define tx_high_pwr_level_70 8
-#define tx_high_pwr_level_100 9
-
-void odm_dynamic_tx_power_init(void *dm_void);
-
-void odm_dynamic_tx_power_restore_power_index(void *dm_void);
-
-void odm_dynamic_tx_power_nic(void *dm_void);
-
-void odm_dynamic_tx_power_save_power_index(void *dm_void);
-
-void odm_dynamic_tx_power_write_power_index(void *dm_void, u8 value);
-
-void odm_dynamic_tx_power_8821(void *dm_void, u8 *desc, u8 mac_id);
-
-void odm_dynamic_tx_power(void *dm_void);
-
-void odm_dynamic_tx_power_ap(void *dm_void);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-void odm_edca_turbo_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- dm->dm_edca_table.is_current_turbo_edca = false;
- dm->dm_edca_table.is_cur_rdl_state = false;
-
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Original VO PARAM: 0x%x\n",
- odm_read_4byte(dm, ODM_EDCA_VO_PARAM));
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Original VI PARAM: 0x%x\n",
- odm_read_4byte(dm, ODM_EDCA_VI_PARAM));
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Original BE PARAM: 0x%x\n",
- odm_read_4byte(dm, ODM_EDCA_BE_PARAM));
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO, "Original BK PARAM: 0x%x\n",
- odm_read_4byte(dm, ODM_EDCA_BK_PARAM));
-
-} /* ODM_InitEdcaTurbo */
-
-void odm_edca_turbo_check(void *dm_void)
-{
- /* For AP/ADSL use struct rtl8192cd_priv* */
- /* For CE/NIC use struct void* */
-
- /* 2011/09/29 MH In HW integration first stage, we provide 4 different
- * handle to operate at the same time.
- * In the stage2/3, we need to prive universal interface and merge all
- * HW dynamic mechanism.
- */
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO,
- "%s========================>\n", __func__);
-
- if (!(dm->support_ability & ODM_MAC_EDCA_TURBO))
- return;
-
- switch (dm->support_platform) {
- case ODM_WIN:
-
- break;
-
- case ODM_CE:
- odm_edca_turbo_check_ce(dm);
- break;
- }
- ODM_RT_TRACE(dm, ODM_COMP_EDCA_TURBO,
- "<========================%s\n", __func__);
-
-} /* odm_CheckEdcaTurbo */
-
-void odm_edca_turbo_check_ce(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- u64 cur_txok_cnt = 0;
- u64 cur_rxok_cnt = 0;
- u32 edca_be_ul = 0x5ea42b;
- u32 edca_be_dl = 0x5ea42b;
- u32 edca_be = 0x5ea42b;
- bool is_cur_rdlstate;
- bool edca_turbo_on = false;
-
- if (dm->wifi_test)
- return;
-
- if (!dm->is_linked) {
- rtlpriv->dm.is_any_nonbepkts = false;
- return;
- }
-
- if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
- rtlpriv->dm.is_any_nonbepkts = true;
- rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
-
- cur_txok_cnt = rtlpriv->stats.txbytesunicast_inperiod;
- cur_rxok_cnt = rtlpriv->stats.rxbytesunicast_inperiod;
-
- /*b_bias_on_rx = false;*/
- edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
- (!rtlpriv->dm.disable_framebursting)) ?
- true :
- false;
-
- if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
- goto label_exit;
-
- if (edca_turbo_on) {
- is_cur_rdlstate =
- (cur_rxok_cnt > cur_txok_cnt * 4) ? true : false;
-
- edca_be = is_cur_rdlstate ? edca_be_dl : edca_be_ul;
- rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM_8822B, edca_be);
- rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate;
- rtlpriv->dm.current_turbo_edca = true;
- } else {
- if (rtlpriv->dm.current_turbo_edca) {
- u8 tmp = AC0_BE;
-
- rtlpriv->cfg->ops->set_hw_reg(rtlpriv->hw,
- HW_VAR_AC_PARAM,
- (u8 *)(&tmp));
- rtlpriv->dm.current_turbo_edca = false;
- }
- }
-
-label_exit:
- rtlpriv->dm.is_any_nonbepkts = false;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMEDCATURBOCHECK_H__
-#define __PHYDMEDCATURBOCHECK_H__
-
-/*#define EDCATURBO_VERSION "2.1"*/
-#define EDCATURBO_VERSION "2.3" /*2015.07.29 by YuChen*/
-
-struct edca_turbo {
- bool is_current_turbo_edca;
- bool is_cur_rdl_state;
-
- u32 prv_traffic_idx; /* edca turbo */
-};
-
-void odm_edca_turbo_check(void *dm_void);
-void odm_edca_turbo_init(void *dm_void);
-
-void odm_edca_turbo_check_ce(void *dm_void);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDM_FEATURES_H__
-#define __PHYDM_FEATURES_H__
-
-/*phydm debyg report & tools*/
-
-/*Antenna Diversity*/
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(dm))
-#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(dm))
-
-#define READ_AND_CONFIG READ_AND_CONFIG_MP
-
-#define READ_FIRMWARE_MP(ic, txt) \
- (odm_read_firmware_mp_##ic##txt(dm, p_firmware, size))
-#define READ_FIRMWARE_TC(ic, txt) \
- (odm_read_firmware_tc_##ic##txt(dm, p_firmware, size))
-
-#define READ_FIRMWARE READ_FIRMWARE_MP
-
-#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt())
-#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt())
-
-#define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt)
-
-static u32 phydm_process_rssi_pwdb(struct phy_dm_struct *dm,
- struct rtl_sta_info *entry,
- struct dm_per_pkt_info *pktinfo,
- u32 undecorated_smoothed_ofdm,
- u32 undecorated_smoothed_cck)
-{
- u32 weighting = 0, undecorated_smoothed_pwdb;
- /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
-
- if (entry->rssi_stat.ofdm_pkt == 64) {
- /* speed up when all packets are OFDM */
- undecorated_smoothed_pwdb = undecorated_smoothed_ofdm;
- ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
- "PWDB_0[%d] = (( %d ))\n", pktinfo->station_id,
- undecorated_smoothed_cck);
- } else {
- if (entry->rssi_stat.valid_bit < 64)
- entry->rssi_stat.valid_bit++;
-
- if (entry->rssi_stat.valid_bit == 64) {
- weighting = ((entry->rssi_stat.ofdm_pkt) > 4) ?
- 64 :
- (entry->rssi_stat.ofdm_pkt << 4);
- undecorated_smoothed_pwdb =
- (weighting * undecorated_smoothed_ofdm +
- (64 - weighting) * undecorated_smoothed_cck) >>
- 6;
- ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
- "PWDB_1[%d] = (( %d )), W = (( %d ))\n",
- pktinfo->station_id,
- undecorated_smoothed_cck, weighting);
- } else {
- if (entry->rssi_stat.valid_bit != 0)
- undecorated_smoothed_pwdb =
- (entry->rssi_stat.ofdm_pkt *
- undecorated_smoothed_ofdm +
- (entry->rssi_stat.valid_bit -
- entry->rssi_stat.ofdm_pkt) *
- undecorated_smoothed_cck) /
- entry->rssi_stat.valid_bit;
- else
- undecorated_smoothed_pwdb = 0;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_RSSI_MONITOR,
- "PWDB_2[%d] = (( %d )), ofdm_pkt = (( %d )), Valid_Bit = (( %d ))\n",
- pktinfo->station_id, undecorated_smoothed_cck,
- entry->rssi_stat.ofdm_pkt,
- entry->rssi_stat.valid_bit);
- }
- }
-
- return undecorated_smoothed_pwdb;
-}
-
-static u32 phydm_process_rssi_cck(struct phy_dm_struct *dm,
- struct dm_phy_status_info *phy_info,
- struct rtl_sta_info *entry,
- u32 undecorated_smoothed_cck)
-{
- u32 rssi_ave;
- u8 i;
-
- rssi_ave = phy_info->rx_pwdb_all;
- dm->rssi_a = (u8)phy_info->rx_pwdb_all;
- dm->rssi_b = 0xFF;
- dm->rssi_c = 0xFF;
- dm->rssi_d = 0xFF;
-
- if (entry->rssi_stat.cck_pkt <= 63)
- entry->rssi_stat.cck_pkt++;
-
- /* 1 Process CCK RSSI */
- if (undecorated_smoothed_cck <= 0) { /* initialize */
- undecorated_smoothed_cck = phy_info->rx_pwdb_all;
- entry->rssi_stat.cck_sum_power =
- (u16)phy_info->rx_pwdb_all; /*reset*/
- entry->rssi_stat.cck_pkt = 1; /*reset*/
- ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR, "CCK_INIT: (( %d ))\n",
- undecorated_smoothed_cck);
- } else if (entry->rssi_stat.cck_pkt <= CCK_RSSI_INIT_COUNT) {
- entry->rssi_stat.cck_sum_power =
- entry->rssi_stat.cck_sum_power +
- (u16)phy_info->rx_pwdb_all;
- undecorated_smoothed_cck = entry->rssi_stat.cck_sum_power /
- entry->rssi_stat.cck_pkt;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_RSSI_MONITOR,
- "CCK_0: (( %d )), SumPow = (( %d )), cck_pkt = (( %d ))\n",
- undecorated_smoothed_cck,
- entry->rssi_stat.cck_sum_power,
- entry->rssi_stat.cck_pkt);
- } else {
- if (phy_info->rx_pwdb_all > (u32)undecorated_smoothed_cck) {
- undecorated_smoothed_cck =
- (((undecorated_smoothed_cck) *
- (RX_SMOOTH_FACTOR - 1)) +
- (phy_info->rx_pwdb_all)) /
- (RX_SMOOTH_FACTOR);
- undecorated_smoothed_cck = undecorated_smoothed_cck + 1;
- ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
- "CCK_1: (( %d ))\n",
- undecorated_smoothed_cck);
- } else {
- undecorated_smoothed_cck =
- (((undecorated_smoothed_cck) *
- (RX_SMOOTH_FACTOR - 1)) +
- (phy_info->rx_pwdb_all)) /
- (RX_SMOOTH_FACTOR);
- ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
- "CCK_2: (( %d ))\n",
- undecorated_smoothed_cck);
- }
- }
-
- i = 63;
- entry->rssi_stat.ofdm_pkt -=
- (u8)((entry->rssi_stat.packet_map >> i) & BIT(0));
- entry->rssi_stat.packet_map = entry->rssi_stat.packet_map << 1;
- return undecorated_smoothed_cck;
-}
-
-static u32 phydm_process_rssi_ofdm(struct phy_dm_struct *dm,
- struct dm_phy_status_info *phy_info,
- struct rtl_sta_info *entry,
- u32 undecorated_smoothed_ofdm)
-{
- u32 rssi_ave;
- u8 rssi_max, rssi_min, i;
-
- if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) {
- u8 rx_count = 0;
- u32 rssi_linear = 0;
-
- if (dm->rx_ant_status & ODM_RF_A) {
- dm->rssi_a = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_A];
- rx_count++;
- rssi_linear += odm_convert_to_linear(
- phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_A]);
- } else {
- dm->rssi_a = 0;
- }
-
- if (dm->rx_ant_status & ODM_RF_B) {
- dm->rssi_b = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_B];
- rx_count++;
- rssi_linear += odm_convert_to_linear(
- phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_B]);
- } else {
- dm->rssi_b = 0;
- }
-
- if (dm->rx_ant_status & ODM_RF_C) {
- dm->rssi_c = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_C];
- rx_count++;
- rssi_linear += odm_convert_to_linear(
- phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_C]);
- } else {
- dm->rssi_c = 0;
- }
-
- if (dm->rx_ant_status & ODM_RF_D) {
- dm->rssi_d = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_D];
- rx_count++;
- rssi_linear += odm_convert_to_linear(
- phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_D]);
- } else {
- dm->rssi_d = 0;
- }
-
- /* Calculate average RSSI */
- switch (rx_count) {
- case 2:
- rssi_linear = rssi_linear >> 1;
- break;
- case 3:
- /* rssi_linear/3 ~ rssi_linear*11/32 */
- rssi_linear = ((rssi_linear) + (rssi_linear << 1) +
- (rssi_linear << 3)) >>
- 5;
- break;
- case 4:
- rssi_linear = rssi_linear >> 2;
- break;
- }
-
- rssi_ave = odm_convert_to_db(rssi_linear);
- } else {
- if (phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B] == 0) {
- rssi_ave = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_A];
- dm->rssi_a = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_A];
- dm->rssi_b = 0;
- } else {
- dm->rssi_a = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_A];
- dm->rssi_b = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_B];
-
- if (phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A] >
- phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]) {
- rssi_max = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_A];
- rssi_min = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_B];
- } else {
- rssi_max = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_B];
- rssi_min = phy_info->rx_mimo_signal_strength
- [ODM_RF_PATH_A];
- }
- if ((rssi_max - rssi_min) < 3)
- rssi_ave = rssi_max;
- else if ((rssi_max - rssi_min) < 6)
- rssi_ave = rssi_max - 1;
- else if ((rssi_max - rssi_min) < 10)
- rssi_ave = rssi_max - 2;
- else
- rssi_ave = rssi_max - 3;
- }
- }
-
- /* 1 Process OFDM RSSI */
- if (undecorated_smoothed_ofdm <= 0) { /* initialize */
- undecorated_smoothed_ofdm = phy_info->rx_pwdb_all;
- ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR, "OFDM_INIT: (( %d ))\n",
- undecorated_smoothed_ofdm);
- } else {
- if (phy_info->rx_pwdb_all > (u32)undecorated_smoothed_ofdm) {
- undecorated_smoothed_ofdm =
- (((undecorated_smoothed_ofdm) *
- (RX_SMOOTH_FACTOR - 1)) +
- (rssi_ave)) /
- (RX_SMOOTH_FACTOR);
- undecorated_smoothed_ofdm =
- undecorated_smoothed_ofdm + 1;
- ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
- "OFDM_1: (( %d ))\n",
- undecorated_smoothed_ofdm);
- } else {
- undecorated_smoothed_ofdm =
- (((undecorated_smoothed_ofdm) *
- (RX_SMOOTH_FACTOR - 1)) +
- (rssi_ave)) /
- (RX_SMOOTH_FACTOR);
- ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
- "OFDM_2: (( %d ))\n",
- undecorated_smoothed_ofdm);
- }
- }
-
- if (entry->rssi_stat.ofdm_pkt != 64) {
- i = 63;
- entry->rssi_stat.ofdm_pkt -=
- (u8)(((entry->rssi_stat.packet_map >> i) & BIT(0)) - 1);
- }
-
- entry->rssi_stat.packet_map =
- (entry->rssi_stat.packet_map << 1) | BIT(0);
- return undecorated_smoothed_ofdm;
-}
-
-static u8 odm_evm_db_to_percentage(s8);
-static u8 odm_evm_dbm_jaguar_series(s8);
-
-static inline u32 phydm_get_rssi_average(struct phy_dm_struct *dm,
- struct dm_phy_status_info *phy_info)
-{
- u8 rssi_max = 0, rssi_min = 0;
-
- dm->rssi_a = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
- dm->rssi_b = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
-
- if (phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A] >
- phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]) {
- rssi_max = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
- rssi_min = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
- } else {
- rssi_max = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
- rssi_min = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
- }
- if ((rssi_max - rssi_min) < 3)
- return rssi_max;
- else if ((rssi_max - rssi_min) < 6)
- return rssi_max - 1;
- else if ((rssi_max - rssi_min) < 10)
- return rssi_max - 2;
- else
- return rssi_max - 3;
-}
-
-static inline u8 phydm_get_evm_dbm(u8 i, u8 EVM,
- struct phy_status_rpt_8812 *phy_sta_rpt,
- struct dm_phy_status_info *phy_info)
-{
- if (i < ODM_RF_PATH_C)
- return odm_evm_dbm_jaguar_series(phy_sta_rpt->rxevm[i]);
- else
- return odm_evm_dbm_jaguar_series(phy_sta_rpt->rxevm_cd[i - 2]);
- /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/
- /*pktinfo->data_rate, phy_sta_rpt->rxevm[i], "%", EVM));*/
-}
-
-static inline u8 phydm_get_odm_evm(u8 i, struct dm_per_pkt_info *pktinfo,
- struct phy_status_rpt_8812 *phy_sta_rpt)
-{
- u8 evm = 0;
-
- if (pktinfo->data_rate >= ODM_RATE6M &&
- pktinfo->data_rate <= ODM_RATE54M) {
- if (i == ODM_RF_PATH_A) {
- evm = odm_evm_db_to_percentage(
- (phy_sta_rpt->sigevm)); /*dbm*/
- evm += 20;
- if (evm > 100)
- evm = 100;
- }
- } else {
- if (i < ODM_RF_PATH_C) {
- if (phy_sta_rpt->rxevm[i] == -128)
- phy_sta_rpt->rxevm[i] = -25;
- evm = odm_evm_db_to_percentage(
- (phy_sta_rpt->rxevm[i])); /*dbm*/
- } else {
- if (phy_sta_rpt->rxevm_cd[i - 2] == -128)
- phy_sta_rpt->rxevm_cd[i - 2] = -25;
- evm = odm_evm_db_to_percentage(
- (phy_sta_rpt->rxevm_cd[i - 2])); /*dbm*/
- }
- }
-
- return evm;
-}
-
-static inline s8 phydm_get_rx_pwr(u8 LNA_idx, u8 VGA_idx, u8 cck_highpwr)
-{
- switch (LNA_idx) {
- case 7:
- if (VGA_idx <= 27)
- return -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/
- else
- return -100;
- break;
- case 6:
- return -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/
- case 5:
- return -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/
- case 4:
- return -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/
- case 3:
- return -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/
- case 2:
- if (cck_highpwr)
- return -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/
- else
- return -6 + 2 * (5 - VGA_idx);
- break;
- case 1:
- return 8 - 2 * VGA_idx;
- case 0:
- return 14 - 2 * VGA_idx;
- default:
- break;
- }
- return 0;
-}
-
-static inline u8 phydm_adjust_pwdb(u8 cck_highpwr, u8 pwdb_all)
-{
- if (!cck_highpwr) {
- if (pwdb_all >= 80)
- return ((pwdb_all - 80) << 1) + ((pwdb_all - 80) >> 1) +
- 80;
- else if ((pwdb_all <= 78) && (pwdb_all >= 20))
- return pwdb_all + 3;
- if (pwdb_all > 100)
- return 100;
- }
- return pwdb_all;
-}
-
-static inline u8
-phydm_get_signal_quality_8812(struct dm_phy_status_info *phy_info,
- struct phy_dm_struct *dm,
- struct phy_status_rpt_8812 *phy_sta_rpt)
-{
- u8 sq_rpt;
-
- if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test)
- return 100;
-
- sq_rpt = phy_sta_rpt->pwdb_all;
-
- if (sq_rpt > 64)
- return 0;
- else if (sq_rpt < 20)
- return 100;
- else
- return ((64 - sq_rpt) * 100) / 44;
-}
-
-static inline u8
-phydm_get_signal_quality_8192(struct dm_phy_status_info *phy_info,
- struct phy_dm_struct *dm,
- struct phy_status_rpt_8192cd *phy_sta_rpt)
-{
- u8 sq_rpt;
-
- if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test)
- return 100;
-
- sq_rpt = phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all;
-
- if (sq_rpt > 64)
- return 0;
- else if (sq_rpt < 20)
- return 100;
- else
- return ((64 - sq_rpt) * 100) / 44;
-}
-
-static u8 odm_query_rx_pwr_percentage(s8 ant_power)
-{
- if ((ant_power <= -100) || (ant_power >= 20))
- return 0;
- else if (ant_power >= 0)
- return 100;
- else
- return 100 + ant_power;
-}
-
-static u8 odm_evm_db_to_percentage(s8 value)
-{
- /* -33dB~0dB to 0%~99% */
- s8 ret_val;
-
- ret_val = value;
- ret_val /= 2;
-
- if (ret_val >= 0)
- ret_val = 0;
-
- if (ret_val <= -33)
- ret_val = -33;
-
- ret_val = 0 - ret_val;
- ret_val *= 3;
-
- if (ret_val == 99)
- ret_val = 100;
-
- return (u8)ret_val;
-}
-
-static u8 odm_evm_dbm_jaguar_series(s8 value)
-{
- s8 ret_val = value;
-
- /* -33dB~0dB to 33dB ~ 0dB */
- if (ret_val == -128)
- ret_val = 127;
- else if (ret_val < 0)
- ret_val = 0 - ret_val;
-
- ret_val = ret_val >> 1;
- return (u8)ret_val;
-}
-
-static s16 odm_cfo(s8 value)
-{
- s16 ret_val;
-
- if (value < 0) {
- ret_val = 0 - value;
- ret_val = (ret_val << 1) + (ret_val >> 1); /* *2.5~=312.5/2^7 */
- ret_val =
- ret_val | BIT(12); /* set bit12 as 1 for negative cfo */
- } else {
- ret_val = value;
- ret_val = (ret_val << 1) + (ret_val >> 1); /* *2.5~=312.5/2^7 */
- }
- return ret_val;
-}
-
-static u8 phydm_rate_to_num_ss(struct phy_dm_struct *dm, u8 data_rate)
-{
- u8 num_ss = 1;
-
- if (data_rate <= ODM_RATE54M)
- num_ss = 1;
- else if (data_rate <= ODM_RATEMCS31)
- num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;
- else if (data_rate <= ODM_RATEVHTSS1MCS9)
- num_ss = 1;
- else if (data_rate <= ODM_RATEVHTSS2MCS9)
- num_ss = 2;
- else if (data_rate <= ODM_RATEVHTSS3MCS9)
- num_ss = 3;
- else if (data_rate <= ODM_RATEVHTSS4MCS9)
- num_ss = 4;
-
- return num_ss;
-}
-
-static void odm_rx_phy_status92c_series_parsing(
- struct phy_dm_struct *dm, struct dm_phy_status_info *phy_info,
- u8 *phy_status, struct dm_per_pkt_info *pktinfo)
-{
- u8 i, max_spatial_stream;
- s8 rx_pwr[4], rx_pwr_all = 0;
- u8 EVM, pwdb_all = 0, pwdb_all_bt;
- u8 RSSI, total_rssi = 0;
- bool is_cck_rate = false;
- u8 rf_rx_num = 0;
- u8 LNA_idx = 0;
- u8 VGA_idx = 0;
- u8 cck_agc_rpt;
- u8 num_ss;
- struct phy_status_rpt_8192cd *phy_sta_rpt =
- (struct phy_status_rpt_8192cd *)phy_status;
-
- is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false;
-
- if (pktinfo->is_to_self)
- dm->curr_station_id = pktinfo->station_id;
-
- phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1;
- phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
-
- if (is_cck_rate) {
- dm->phy_dbg_info.num_qry_phy_status_cck++;
- cck_agc_rpt = phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a;
-
- if (dm->support_ic_type & (ODM_RTL8703B)) {
- } else { /*3 bit LNA*/
-
- LNA_idx = ((cck_agc_rpt & 0xE0) >> 5);
- VGA_idx = (cck_agc_rpt & 0x1F);
- }
-
- ODM_RT_TRACE(
- dm, ODM_COMP_RSSI_MONITOR,
- "ext_lna_gain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n",
- dm->ext_lna_gain, LNA_idx, VGA_idx, rx_pwr_all);
-
- if (dm->board_type & ODM_BOARD_EXT_LNA)
- rx_pwr_all -= dm->ext_lna_gain;
-
- pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
-
- if (pktinfo->is_to_self) {
- dm->cck_lna_idx = LNA_idx;
- dm->cck_vga_idx = VGA_idx;
- }
- phy_info->rx_pwdb_all = pwdb_all;
-
- phy_info->bt_rx_rssi_percentage = pwdb_all;
- phy_info->recv_signal_power = rx_pwr_all;
- /* (3) Get Signal Quality (EVM) */
- {
- u8 sq;
-
- sq = phydm_get_signal_quality_8192(phy_info, dm,
- phy_sta_rpt);
- phy_info->signal_quality = sq;
- phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = sq;
- phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
- }
-
- for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) {
- if (i == 0)
- phy_info->rx_mimo_signal_strength[0] = pwdb_all;
- else
- phy_info->rx_mimo_signal_strength[1] = 0;
- }
- } else { /* 2 is OFDM rate */
- dm->phy_dbg_info.num_qry_phy_status_ofdm++;
-
- /* */
- /* (1)Get RSSI for HT rate */
- /* */
-
- for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) {
- /* 2008/01/30 MH we will judge RF RX path now. */
- if (dm->rf_path_rx_enable & BIT(i))
- rf_rx_num++;
- /* else */
- /* continue; */
-
- rx_pwr[i] =
- ((phy_sta_rpt->path_agc[i].gain & 0x3F) * 2) -
- 110;
-
- if (pktinfo->is_to_self) {
- dm->ofdm_agc_idx[i] =
- (phy_sta_rpt->path_agc[i].gain & 0x3F);
- /**/
- }
-
- phy_info->rx_pwr[i] = rx_pwr[i];
-
- /* Translate DBM to percentage. */
- RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]);
- total_rssi += RSSI;
-
- phy_info->rx_mimo_signal_strength[i] = (u8)RSSI;
-
- /* Get Rx snr value in DB */
- dm->phy_dbg_info.rx_snr_db[i] =
- (s32)(phy_sta_rpt->path_rxsnr[i] / 2);
- phy_info->rx_snr[i] = dm->phy_dbg_info.rx_snr_db[i];
-
- /* Record Signal Strength for next packet */
- /* if(pktinfo->is_packet_match_bssid) */
- {
- }
- }
-
- /* */
- /* (2)PWDB, Average PWDB calcuated by hardware (for RA) */
- /* */
- rx_pwr_all = (((phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all) >> 1) &
- 0x7f) -
- 110;
-
- pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
- pwdb_all_bt = pwdb_all;
-
- phy_info->rx_pwdb_all = pwdb_all;
- phy_info->bt_rx_rssi_percentage = pwdb_all_bt;
- phy_info->rx_power = rx_pwr_all;
- phy_info->recv_signal_power = rx_pwr_all;
-
- if ((dm->support_platform == ODM_WIN) && (dm->patch_id == 19)) {
- /* do nothing */
- } else if ((dm->support_platform == ODM_WIN) &&
- (dm->patch_id == 25)) {
- /* do nothing */
- } else { /* mgnt_info->customer_id != RT_CID_819X_LENOVO */
- /* */
- /* (3)EVM of HT rate */
- /* */
- if (pktinfo->data_rate >= ODM_RATEMCS8 &&
- pktinfo->data_rate <= ODM_RATEMCS15) {
- /* both spatial stream make sense */
- max_spatial_stream = 2;
- } else {
- /* only spatial stream 1 makes sense */
- max_spatial_stream = 1;
- }
-
- for (i = 0; i < max_spatial_stream; i++) {
- /*Don't use shift operation like "rx_evmX >>= 1"
- *because the compilor of free build environment
- *fill most significant bit to "zero" when doing
- *shifting operation which may change a negative
- *value to positive one, then the dbm value
- *(which is supposed to be negative) is not
- *correct anymore.
- */
- EVM = odm_evm_db_to_percentage(
- (phy_sta_rpt
- ->stream_rxevm[i])); /* dbm */
-
- /* Fill value in RFD, Get the first spatial
- * stream only
- */
- if (i == ODM_RF_PATH_A)
- phy_info->signal_quality =
- (u8)(EVM & 0xff);
- phy_info->rx_mimo_signal_quality[i] =
- (u8)(EVM & 0xff);
- }
- }
-
- num_ss = phydm_rate_to_num_ss(dm, pktinfo->data_rate);
- odm_parsing_cfo(dm, pktinfo, phy_sta_rpt->path_cfotail, num_ss);
- }
- /* UI BSS List signal strength(in percentage), make it good looking,
- * from 0~100.
- */
- /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
- if (is_cck_rate)
- phy_info->signal_strength = pwdb_all;
- else if (rf_rx_num != 0)
- phy_info->signal_strength = (total_rssi /= rf_rx_num);
-
- /* For 92C/92D HW (Hybrid) Antenna Diversity */
-}
-
-static void
-odm_rx_phy_bw_jaguar_series_parsing(struct dm_phy_status_info *phy_info,
- struct dm_per_pkt_info *pktinfo,
- struct phy_status_rpt_8812 *phy_sta_rpt)
-{
- if (pktinfo->data_rate <= ODM_RATE54M) {
- switch (phy_sta_rpt->r_RFMOD) {
- case 1:
- if (phy_sta_rpt->sub_chnl == 0)
- phy_info->band_width = 1;
- else
- phy_info->band_width = 0;
- break;
-
- case 2:
- if (phy_sta_rpt->sub_chnl == 0)
- phy_info->band_width = 2;
- else if (phy_sta_rpt->sub_chnl == 9 ||
- phy_sta_rpt->sub_chnl == 10)
- phy_info->band_width = 1;
- else
- phy_info->band_width = 0;
- break;
-
- default:
- case 0:
- phy_info->band_width = 0;
- break;
- }
- }
-}
-
-static void odm_rx_phy_status_jaguar_series_parsing(
- struct phy_dm_struct *dm, struct dm_phy_status_info *phy_info,
- u8 *phy_status, struct dm_per_pkt_info *pktinfo)
-{
- u8 i, max_spatial_stream;
- s8 rx_pwr[4], rx_pwr_all = 0;
- u8 EVM = 0, evm_dbm, pwdb_all = 0, pwdb_all_bt;
- u8 RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0;
- u8 is_cck_rate = 0;
- u8 rf_rx_num = 0;
- u8 cck_highpwr = 0;
- u8 LNA_idx, VGA_idx;
- struct phy_status_rpt_8812 *phy_sta_rpt =
- (struct phy_status_rpt_8812 *)phy_status;
- struct fast_antenna_training *fat_tab = &dm->dm_fat_table;
- u8 num_ss;
-
- odm_rx_phy_bw_jaguar_series_parsing(phy_info, pktinfo, phy_sta_rpt);
-
- if (pktinfo->data_rate <= ODM_RATE11M)
- is_cck_rate = true;
- else
- is_cck_rate = false;
-
- if (pktinfo->is_to_self)
- dm->curr_station_id = pktinfo->station_id;
- else
- dm->curr_station_id = 0xff;
-
- phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1;
- phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
- phy_info->rx_mimo_signal_quality[ODM_RF_PATH_C] = -1;
- phy_info->rx_mimo_signal_quality[ODM_RF_PATH_D] = -1;
-
- if (is_cck_rate) {
- u8 cck_agc_rpt;
-
- dm->phy_dbg_info.num_qry_phy_status_cck++;
-
- /*(1)Hardware does not provide RSSI for CCK*/
- /*(2)PWDB, Average PWDB calculated by hardware (for RA)*/
-
- cck_highpwr = dm->is_cck_high_power;
-
- cck_agc_rpt = phy_sta_rpt->cfosho[0];
- LNA_idx = (cck_agc_rpt & 0xE0) >> 5;
- VGA_idx = cck_agc_rpt & 0x1F;
-
- if (dm->support_ic_type == ODM_RTL8812) {
- rx_pwr_all =
- phydm_get_rx_pwr(LNA_idx, VGA_idx, cck_highpwr);
- rx_pwr_all += 6;
- pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
- pwdb_all = phydm_adjust_pwdb(cck_highpwr, pwdb_all);
-
- } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
- s8 pout = -6;
-
- switch (LNA_idx) {
- case 5:
- rx_pwr_all = pout - 32 - (2 * VGA_idx);
- break;
- case 4:
- rx_pwr_all = pout - 24 - (2 * VGA_idx);
- break;
- case 2:
- rx_pwr_all = pout - 11 - (2 * VGA_idx);
- break;
- case 1:
- rx_pwr_all = pout + 5 - (2 * VGA_idx);
- break;
- case 0:
- rx_pwr_all = pout + 21 - (2 * VGA_idx);
- break;
- }
- pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
- } else if (dm->support_ic_type == ODM_RTL8814A ||
- dm->support_ic_type == ODM_RTL8822B) {
- s8 pout = -6;
-
- switch (LNA_idx) {
- /*CCK only use LNA: 2, 3, 5, 7*/
- case 7:
- rx_pwr_all = pout - 32 - (2 * VGA_idx);
- break;
- case 5:
- rx_pwr_all = pout - 22 - (2 * VGA_idx);
- break;
- case 3:
- rx_pwr_all = pout - 2 - (2 * VGA_idx);
- break;
- case 2:
- rx_pwr_all = pout + 5 - (2 * VGA_idx);
- break;
- default:
- break;
- }
- pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
- }
-
- dm->cck_lna_idx = LNA_idx;
- dm->cck_vga_idx = VGA_idx;
- phy_info->rx_pwdb_all = pwdb_all;
- phy_info->bt_rx_rssi_percentage = pwdb_all;
- phy_info->recv_signal_power = rx_pwr_all;
- /*(3) Get Signal Quality (EVM)*/
- {
- u8 sq = 0;
-
- if (!(dm->support_platform == ODM_WIN &&
- dm->patch_id == RT_CID_819X_LENOVO))
- sq = phydm_get_signal_quality_8812(phy_info, dm,
- phy_sta_rpt);
-
- phy_info->signal_quality = sq;
- phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = sq;
- }
-
- for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
- if (i == 0)
- phy_info->rx_mimo_signal_strength[0] = pwdb_all;
- else
- phy_info->rx_mimo_signal_strength[i] = 0;
- }
- } else {
- /*is OFDM rate*/
- fat_tab->hw_antsw_occur = phy_sta_rpt->hw_antsw_occur;
-
- dm->phy_dbg_info.num_qry_phy_status_ofdm++;
-
- /*(1)Get RSSI for OFDM rate*/
-
- for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
- /*2008/01/30 MH we will judge RF RX path now.*/
- if (dm->rf_path_rx_enable & BIT(i))
- rf_rx_num++;
- /*2012.05.25 LukeLee: Testchip AGC report is wrong,
- *it should be restored back to old formula in MP chip
- */
- if (i < ODM_RF_PATH_C)
- rx_pwr[i] = (phy_sta_rpt->gain_trsw[i] & 0x7F) -
- 110;
- else
- rx_pwr[i] = (phy_sta_rpt->gain_trsw_cd[i - 2] &
- 0x7F) -
- 110;
-
- phy_info->rx_pwr[i] = rx_pwr[i];
-
- /* Translate DBM to percentage. */
- RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]);
-
- /*total_rssi += RSSI;*/
- /*Get the best two RSSI*/
- if (RSSI > best_rssi && RSSI > second_rssi) {
- second_rssi = best_rssi;
- best_rssi = RSSI;
- } else if (RSSI > second_rssi && RSSI <= best_rssi) {
- second_rssi = RSSI;
- }
-
- phy_info->rx_mimo_signal_strength[i] = (u8)RSSI;
-
- /*Get Rx snr value in DB*/
- if (i < ODM_RF_PATH_C)
- phy_info->rx_snr[i] =
- dm->phy_dbg_info.rx_snr_db[i] =
- phy_sta_rpt->rxsnr[i] / 2;
- else if (dm->support_ic_type &
- (ODM_RTL8814A | ODM_RTL8822B))
- phy_info->rx_snr[i] = dm->phy_dbg_info
- .rx_snr_db[i] =
- phy_sta_rpt->csi_current[i - 2] / 2;
-
- /*(2) CFO_short & CFO_tail*/
- if (i < ODM_RF_PATH_C) {
- phy_info->cfo_short[i] =
- odm_cfo((phy_sta_rpt->cfosho[i]));
- phy_info->cfo_tail[i] =
- odm_cfo((phy_sta_rpt->cfotail[i]));
- }
- }
-
- /*(3)PWDB, Average PWDB calculated by hardware (for RA)*/
-
- /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be
- *restored back to old formula in MP chip
- */
- if ((dm->support_ic_type &
- (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) &&
- (!dm->is_mp_chip))
- rx_pwr_all = (phy_sta_rpt->pwdb_all & 0x7f) - 110;
- else
- rx_pwr_all = (((phy_sta_rpt->pwdb_all) >> 1) & 0x7f) -
- 110; /*OLD FORMULA*/
-
- pwdb_all = odm_query_rx_pwr_percentage(rx_pwr_all);
- pwdb_all_bt = pwdb_all;
-
- phy_info->rx_pwdb_all = pwdb_all;
- phy_info->bt_rx_rssi_percentage = pwdb_all_bt;
- phy_info->rx_power = rx_pwr_all;
- phy_info->recv_signal_power = rx_pwr_all;
-
- if ((dm->support_platform == ODM_WIN) && (dm->patch_id == 19)) {
- /*do nothing*/
- } else {
- /*mgnt_info->customer_id != RT_CID_819X_LENOVO*/
-
- /*(4)EVM of OFDM rate*/
-
- if ((pktinfo->data_rate >= ODM_RATEMCS8) &&
- (pktinfo->data_rate <= ODM_RATEMCS15))
- max_spatial_stream = 2;
- else if ((pktinfo->data_rate >= ODM_RATEVHTSS2MCS0) &&
- (pktinfo->data_rate <= ODM_RATEVHTSS2MCS9))
- max_spatial_stream = 2;
- else if ((pktinfo->data_rate >= ODM_RATEMCS16) &&
- (pktinfo->data_rate <= ODM_RATEMCS23))
- max_spatial_stream = 3;
- else if ((pktinfo->data_rate >= ODM_RATEVHTSS3MCS0) &&
- (pktinfo->data_rate <= ODM_RATEVHTSS3MCS9))
- max_spatial_stream = 3;
- else
- max_spatial_stream = 1;
-
- for (i = 0; i < max_spatial_stream; i++) {
- /*Don't use shift operation like "rx_evmX >>= 1"
- *because the compilor of free build environment
- *fill most significant bit to "zero" when doing
- *shifting operation which may change a negative
- *value to positive one, then the dbm value
- *(which is supposed to be negative) is not
- *correct anymore.
- */
-
- EVM = phydm_get_odm_evm(i, pktinfo,
- phy_sta_rpt);
- evm_dbm = phydm_get_evm_dbm(i, EVM, phy_sta_rpt,
- phy_info);
- phy_info->rx_mimo_signal_quality[i] = EVM;
- phy_info->rx_mimo_evm_dbm[i] = evm_dbm;
- }
- }
-
- num_ss = phydm_rate_to_num_ss(dm, pktinfo->data_rate);
- odm_parsing_cfo(dm, pktinfo, phy_sta_rpt->cfotail, num_ss);
- }
-
- /*UI BSS List signal strength(in percentage), make it good looking,
- *from 0~100.
- */
- /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/
- if (is_cck_rate) {
- phy_info->signal_strength = pwdb_all;
- } else if (rf_rx_num != 0) {
- /* 2015/01 Sean, use the best two RSSI only,
- * suggested by Ynlin and ChenYu.
- */
- if (rf_rx_num == 1)
- avg_rssi = best_rssi;
- else
- avg_rssi = (best_rssi + second_rssi) / 2;
-
- phy_info->signal_strength = avg_rssi;
- }
-
- dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all;
-
- dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->antidx_anta;
- dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->antidx_antb;
- dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antidx_antc;
- dm->dm_fat_table.antsel_rx_keep_3 = phy_sta_rpt->antidx_antd;
-}
-
-void phydm_reset_rssi_for_dm(struct phy_dm_struct *dm, u8 station_id)
-{
- struct rtl_sta_info *entry;
-
- entry = dm->odm_sta_info[station_id];
-
- if (!IS_STA_VALID(entry))
- return;
-
- ODM_RT_TRACE(dm, ODM_COMP_RSSI_MONITOR,
- "Reset RSSI for macid = (( %d ))\n", station_id);
-
- entry->rssi_stat.undecorated_smoothed_cck = -1;
- entry->rssi_stat.undecorated_smoothed_ofdm = -1;
- entry->rssi_stat.undecorated_smoothed_pwdb = -1;
- entry->rssi_stat.ofdm_pkt = 0;
- entry->rssi_stat.cck_pkt = 0;
- entry->rssi_stat.cck_sum_power = 0;
- entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;
- entry->rssi_stat.packet_map = 0;
- entry->rssi_stat.valid_bit = 0;
-}
-
-void odm_init_rssi_for_dm(struct phy_dm_struct *dm) {}
-
-static void odm_process_rssi_for_dm(struct phy_dm_struct *dm,
- struct dm_phy_status_info *phy_info,
- struct dm_per_pkt_info *pktinfo)
-{
- s32 undecorated_smoothed_pwdb, undecorated_smoothed_cck,
- undecorated_smoothed_ofdm;
- u8 is_cck_rate = 0;
- u8 send_rssi_2_fw = 0;
- struct rtl_sta_info *entry;
-
- if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
- return;
-
- /* 2012/05/30 MH/Luke.Lee Add some description */
- /* In windows driver: AP/IBSS mode STA */
- entry = dm->odm_sta_info[pktinfo->station_id];
-
- if (!IS_STA_VALID(entry))
- return;
-
- {
- if ((!pktinfo->is_packet_match_bssid)) /*data frame only*/
- return;
- }
-
- if (pktinfo->is_packet_beacon)
- dm->phy_dbg_info.num_qry_beacon_pkt++;
-
- is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false;
- dm->rx_rate = pktinfo->data_rate;
-
- /* --------------Statistic for antenna/path diversity---------------- */
-
- /* -----------------Smart Antenna Debug Message------------------ */
-
- undecorated_smoothed_cck = entry->rssi_stat.undecorated_smoothed_cck;
- undecorated_smoothed_ofdm = entry->rssi_stat.undecorated_smoothed_ofdm;
- undecorated_smoothed_pwdb = entry->rssi_stat.undecorated_smoothed_pwdb;
-
- if (pktinfo->is_packet_to_self || pktinfo->is_packet_beacon) {
- if (!is_cck_rate) /* ofdm rate */
- undecorated_smoothed_ofdm = phydm_process_rssi_ofdm(
- dm, phy_info, entry, undecorated_smoothed_ofdm);
- else
- undecorated_smoothed_cck = phydm_process_rssi_cck(
- dm, phy_info, entry, undecorated_smoothed_cck);
-
- undecorated_smoothed_pwdb = phydm_process_rssi_pwdb(
- dm, entry, pktinfo, undecorated_smoothed_ofdm,
- undecorated_smoothed_cck);
-
- if ((entry->rssi_stat.ofdm_pkt >= 1 ||
- entry->rssi_stat.cck_pkt >= 5) &&
- (entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) {
- send_rssi_2_fw = 1;
- entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_SEND;
- }
-
- entry->rssi_stat.undecorated_smoothed_cck =
- undecorated_smoothed_cck;
- entry->rssi_stat.undecorated_smoothed_ofdm =
- undecorated_smoothed_ofdm;
- entry->rssi_stat.undecorated_smoothed_pwdb =
- undecorated_smoothed_pwdb;
-
- if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
-
- if (entry->rssi_stat.ofdm_pkt != 0)
- entry->rssi_stat.undecorated_smoothed_pwdb =
- undecorated_smoothed_ofdm;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_RSSI_MONITOR,
- "[Send to FW] PWDB = (( %d )), ofdm_pkt = (( %d )), cck_pkt = (( %d ))\n",
- undecorated_smoothed_pwdb,
- entry->rssi_stat.ofdm_pkt,
- entry->rssi_stat.cck_pkt);
- }
- }
-}
-
-/*
- * Endianness before calling this API
- */
-static void odm_phy_status_query_92c_series(struct phy_dm_struct *dm,
- struct dm_phy_status_info *phy_info,
- u8 *phy_status,
- struct dm_per_pkt_info *pktinfo)
-{
- odm_rx_phy_status92c_series_parsing(dm, phy_info, phy_status, pktinfo);
- odm_process_rssi_for_dm(dm, phy_info, pktinfo);
-}
-
-/*
- * Endianness before calling this API
- */
-
-static void odm_phy_status_query_jaguar_series(
- struct phy_dm_struct *dm, struct dm_phy_status_info *phy_info,
- u8 *phy_status, struct dm_per_pkt_info *pktinfo)
-{
- odm_rx_phy_status_jaguar_series_parsing(dm, phy_info, phy_status,
- pktinfo);
- odm_process_rssi_for_dm(dm, phy_info, pktinfo);
-}
-
-void odm_phy_status_query(struct phy_dm_struct *dm,
- struct dm_phy_status_info *phy_info, u8 *phy_status,
- struct dm_per_pkt_info *pktinfo)
-{
- if (dm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) {
- phydm_rx_phy_status_new_type(dm, phy_status, pktinfo, phy_info);
- return;
- }
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- odm_phy_status_query_jaguar_series(dm, phy_info, phy_status,
- pktinfo);
-
- if (dm->support_ic_type & ODM_IC_11N_SERIES)
- odm_phy_status_query_92c_series(dm, phy_info, phy_status,
- pktinfo);
-}
-
-/* For future use. */
-void odm_mac_status_query(struct phy_dm_struct *dm, u8 *mac_status, u8 mac_id,
- bool is_packet_match_bssid, bool is_packet_to_self,
- bool is_packet_beacon)
-{
- /* 2011/10/19 Driver team will handle in the future. */
-}
-
-/*
- * If you want to add a new IC, Please follow below template and generate
- * a new one.
- */
-
-enum hal_status
-odm_config_rf_with_header_file(struct phy_dm_struct *dm,
- enum odm_rf_config_type config_type,
- enum odm_rf_radio_path e_rf_path)
-{
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===>%s (%s)\n", __func__,
- (dm->is_mp_chip) ? "MPChip" : "TestChip");
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "dm->support_platform: 0x%X, dm->support_interface: 0x%X, dm->board_type: 0x%X\n",
- dm->support_platform, dm->support_interface, dm->board_type);
-
- /* 1 AP doesn't use PHYDM power tracking table in these ICs */
- /* JJ ADD 20161014 */
-
- /* 1 All platforms support */
- if (dm->support_ic_type == ODM_RTL8822B) {
- if (config_type == CONFIG_RF_RADIO) {
- if (e_rf_path == ODM_RF_PATH_A)
- READ_AND_CONFIG_MP(8822b, _radioa);
- else if (e_rf_path == ODM_RF_PATH_B)
- READ_AND_CONFIG_MP(8822b, _radiob);
- } else if (config_type == CONFIG_RF_TXPWR_LMT) {
- if (dm->rfe_type == 5)
- READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5);
- else
- READ_AND_CONFIG_MP(8822b, _txpwr_lmt);
- }
- }
-
- return HAL_STATUS_SUCCESS;
-}
-
-enum hal_status
-odm_config_rf_with_tx_pwr_track_header_file(struct phy_dm_struct *dm)
-{
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===>%s (%s)\n", __func__,
- (dm->is_mp_chip) ? "MPChip" : "TestChip");
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "dm->support_platform: 0x%X, dm->support_interface: 0x%X, dm->board_type: 0x%X\n",
- dm->support_platform, dm->support_interface, dm->board_type);
-
- /* 1 AP doesn't use PHYDM power tracking table in these ICs */
- /* JJ ADD 20161014 */
-
- /* 1 All platforms support */
-
- if (dm->support_ic_type == ODM_RTL8822B) {
- if (dm->rfe_type == 0)
- READ_AND_CONFIG_MP(8822b, _txpowertrack_type0);
- else if (dm->rfe_type == 1)
- READ_AND_CONFIG_MP(8822b, _txpowertrack_type1);
- else if (dm->rfe_type == 2)
- READ_AND_CONFIG_MP(8822b, _txpowertrack_type2);
- else if ((dm->rfe_type == 3) || (dm->rfe_type == 5))
- READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5);
- else if (dm->rfe_type == 4)
- READ_AND_CONFIG_MP(8822b, _txpowertrack_type4);
- else if (dm->rfe_type == 6)
- READ_AND_CONFIG_MP(8822b, _txpowertrack_type6);
- else if (dm->rfe_type == 7)
- READ_AND_CONFIG_MP(8822b, _txpowertrack_type7);
- else if (dm->rfe_type == 8)
- READ_AND_CONFIG_MP(8822b, _txpowertrack_type8);
- else if (dm->rfe_type == 9)
- READ_AND_CONFIG_MP(8822b, _txpowertrack_type9);
- else
- READ_AND_CONFIG_MP(8822b, _txpowertrack);
- }
-
- return HAL_STATUS_SUCCESS;
-}
-
-enum hal_status
-odm_config_bb_with_header_file(struct phy_dm_struct *dm,
- enum odm_bb_config_type config_type)
-{
- /* 1 AP doesn't use PHYDM initialization in these ICs */
- /* JJ ADD 20161014 */
-
- /* 1 All platforms support */
- if (dm->support_ic_type == ODM_RTL8822B) {
- if (config_type == CONFIG_BB_PHY_REG)
- READ_AND_CONFIG_MP(8822b, _phy_reg);
- else if (config_type == CONFIG_BB_AGC_TAB)
- READ_AND_CONFIG_MP(8822b, _agc_tab);
- else if (config_type == CONFIG_BB_PHY_REG_PG)
- READ_AND_CONFIG_MP(8822b, _phy_reg_pg);
- /*else if (config_type == CONFIG_BB_PHY_REG_MP)*/
- /*READ_AND_CONFIG_MP(8822b, _phy_reg_mp);*/
- }
-
- return HAL_STATUS_SUCCESS;
-}
-
-enum hal_status odm_config_mac_with_header_file(struct phy_dm_struct *dm)
-{
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===>%s (%s)\n", __func__,
- (dm->is_mp_chip) ? "MPChip" : "TestChip");
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "dm->support_platform: 0x%X, dm->support_interface: 0x%X, dm->board_type: 0x%X\n",
- dm->support_platform, dm->support_interface, dm->board_type);
-
- /* 1 AP doesn't use PHYDM initialization in these ICs */
- /* JJ ADD 20161014 */
-
- /* 1 All platforms support */
- if (dm->support_ic_type == ODM_RTL8822B)
- READ_AND_CONFIG_MP(8822b, _mac_reg);
-
- return HAL_STATUS_SUCCESS;
-}
-
-enum hal_status
-odm_config_fw_with_header_file(struct phy_dm_struct *dm,
- enum odm_fw_config_type config_type,
- u8 *p_firmware, u32 *size)
-{
- return HAL_STATUS_SUCCESS;
-}
-
-u32 odm_get_hw_img_version(struct phy_dm_struct *dm)
-{
- u32 version = 0;
-
- /* 1 AP doesn't use PHYDM initialization in these ICs */
- /* JJ ADD 20161014 */
-
- /*1 All platforms support*/
- if (dm->support_ic_type == ODM_RTL8822B)
- version = GET_VERSION_MP(8822b, _mac_reg);
-
- return version;
-}
-
-/* For 8822B only!! need to move to FW finally */
-/*==============================================*/
-
-bool phydm_query_is_mu_api(struct phy_dm_struct *phydm, u8 ppdu_idx,
- u8 *p_data_rate, u8 *p_gid)
-{
- u8 data_rate = 0, gid = 0;
- bool is_mu = false;
-
- data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];
- gid = phydm->phy_dbg_info.gid_num[ppdu_idx];
-
- if (data_rate & BIT(7)) {
- is_mu = true;
- data_rate = data_rate & ~(BIT(7));
- } else {
- is_mu = false;
- }
-
- *p_data_rate = data_rate;
- *p_gid = gid;
-
- return is_mu;
-}
-
-static void phydm_rx_statistic_cal(struct phy_dm_struct *phydm, u8 *phy_status,
- struct dm_per_pkt_info *pktinfo)
-{
- struct phy_status_rpt_jaguar2_type1 *phy_sta_rpt =
- (struct phy_status_rpt_jaguar2_type1 *)phy_status;
- u8 date_rate = pktinfo->data_rate & ~(BIT(7));
-
- if ((phy_sta_rpt->gid != 0) && (phy_sta_rpt->gid != 63)) {
- if (date_rate >= ODM_RATEVHTSS1MCS0) {
- phydm->phy_dbg_info
- .num_qry_mu_vht_pkt[date_rate - 0x2C]++;
- phydm->phy_dbg_info.num_of_ppdu[pktinfo->ppdu_cnt] =
- date_rate | BIT(7);
- phydm->phy_dbg_info.gid_num[pktinfo->ppdu_cnt] =
- phy_sta_rpt->gid;
- }
-
- } else {
- if (date_rate >= ODM_RATEVHTSS1MCS0) {
- phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - 0x2C]++;
- phydm->phy_dbg_info.num_of_ppdu[pktinfo->ppdu_cnt] =
- date_rate;
- phydm->phy_dbg_info.gid_num[pktinfo->ppdu_cnt] =
- phy_sta_rpt->gid;
- }
- }
-}
-
-static void phydm_reset_phy_info(struct phy_dm_struct *phydm,
- struct dm_phy_status_info *phy_info)
-{
- phy_info->rx_pwdb_all = 0;
- phy_info->signal_quality = 0;
- phy_info->band_width = 0;
- phy_info->rx_count = 0;
- odm_memory_set(phydm, phy_info->rx_mimo_signal_quality, 0, 4);
- odm_memory_set(phydm, phy_info->rx_mimo_signal_strength, 0, 4);
- odm_memory_set(phydm, phy_info->rx_snr, 0, 4);
-
- phy_info->rx_power = -110;
- phy_info->recv_signal_power = -110;
- phy_info->bt_rx_rssi_percentage = 0;
- phy_info->signal_strength = 0;
- phy_info->bt_coex_pwr_adjust = 0;
- phy_info->channel = 0;
- phy_info->is_mu_packet = 0;
- phy_info->is_beamformed = 0;
- phy_info->rxsc = 0;
- odm_memory_set(phydm, phy_info->rx_pwr, -110, 4);
- odm_memory_set(phydm, phy_info->rx_mimo_evm_dbm, 0, 4);
- odm_memory_set(phydm, phy_info->cfo_short, 0, 8);
- odm_memory_set(phydm, phy_info->cfo_tail, 0, 8);
-}
-
-static void phydm_set_per_path_phy_info(u8 rx_path, s8 rx_pwr, s8 rx_evm,
- s8 cfo_tail, s8 rx_snr,
- struct dm_phy_status_info *phy_info)
-{
- u8 evm_dbm = 0;
- u8 evm_percentage = 0;
-
- /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
-
- if (rx_evm < 0) {
- /* Calculate EVM in dBm */
- evm_dbm = (u8)(0 - rx_evm) >> 1;
-
- /* Calculate EVM in percentage */
- if (evm_dbm >= 33)
- evm_percentage = 100;
- else
- evm_percentage = (evm_dbm << 1) + (evm_dbm);
- }
-
- phy_info->rx_pwr[rx_path] = rx_pwr;
- phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
-
- /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/
- phy_info->cfo_tail[rx_path] = cfo_tail;
- phy_info->cfo_tail[rx_path] = ((phy_info->cfo_tail[rx_path] << 5) +
- (phy_info->cfo_tail[rx_path] << 2) +
- (phy_info->cfo_tail[rx_path] << 1) +
- (phy_info->cfo_tail[rx_path])) >>
- 9;
-
- phy_info->rx_mimo_signal_strength[rx_path] =
- odm_query_rx_pwr_percentage(rx_pwr);
- phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
- phy_info->rx_snr[rx_path] = rx_snr >> 1;
-}
-
-static void phydm_set_common_phy_info(s8 rx_power, u8 channel,
- bool is_beamformed, bool is_mu_packet,
- u8 bandwidth, u8 signal_quality, u8 rxsc,
- struct dm_phy_status_info *phy_info)
-{
- phy_info->rx_power = rx_power; /* RSSI in dB */
- phy_info->recv_signal_power = rx_power; /* RSSI in dB */
- phy_info->channel = channel; /* channel number */
- phy_info->is_beamformed = is_beamformed; /* apply BF */
- phy_info->is_mu_packet = is_mu_packet; /* MU packet */
- phy_info->rxsc = rxsc;
- phy_info->rx_pwdb_all =
- odm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */
- phy_info->signal_quality = signal_quality; /* signal quality */
- phy_info->band_width = bandwidth; /* bandwidth */
-}
-
-static void phydm_get_rx_phy_status_type0(struct phy_dm_struct *dm,
- u8 *phy_status,
- struct dm_per_pkt_info *pktinfo,
- struct dm_phy_status_info *phy_info)
-{
- /* type 0 is used for cck packet */
-
- struct phy_status_rpt_jaguar2_type0 *phy_sta_rpt =
- (struct phy_status_rpt_jaguar2_type0 *)phy_status;
- u8 sq = 0;
- s8 rx_power = phy_sta_rpt->pwdb - 110;
-
- /* JJ ADD 20161014 */
-
- /* Calculate Signal Quality*/
- if (pktinfo->is_packet_match_bssid) {
- if (phy_sta_rpt->signal_quality >= 64) {
- sq = 0;
- } else if (phy_sta_rpt->signal_quality <= 20) {
- sq = 100;
- } else {
- /* mapping to 2~99% */
- sq = 64 - phy_sta_rpt->signal_quality;
- sq = ((sq << 3) + sq) >> 2;
- }
- }
-
- /* Modify CCK PWDB if old AGC */
- if (!dm->cck_new_agc) {
- u8 lna_idx, vga_idx;
-
- lna_idx = (phy_sta_rpt->lna_h << 3) | phy_sta_rpt->lna_l;
- vga_idx = phy_sta_rpt->vga;
-
- /* JJ ADD 20161014 */
-
- /* Need to do !! */
- /*if (dm->support_ic_type & ODM_RTL8822B) */
- /*rx_power = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/
- }
-
- /* Update CCK packet counter */
- dm->phy_dbg_info.num_qry_phy_status_cck++;
-
- /*CCK no STBC and LDPC*/
- dm->phy_dbg_info.is_ldpc_pkt = false;
- dm->phy_dbg_info.is_stbc_pkt = false;
-
- /* Update Common information */
- phydm_set_common_phy_info(rx_power, phy_sta_rpt->channel, false, false,
- ODM_BW20M, sq, phy_sta_rpt->rxsc, phy_info);
-
- /* Update CCK pwdb */
- /* Update per-path information */
- phydm_set_per_path_phy_info(ODM_RF_PATH_A, rx_power, 0, 0, 0, phy_info);
-
- dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->antidx_a;
- dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->antidx_b;
- dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antidx_c;
- dm->dm_fat_table.antsel_rx_keep_3 = phy_sta_rpt->antidx_d;
-}
-
-static void phydm_get_rx_phy_status_type1(struct phy_dm_struct *dm,
- u8 *phy_status,
- struct dm_per_pkt_info *pktinfo,
- struct dm_phy_status_info *phy_info)
-{
- /* type 1 is used for ofdm packet */
-
- struct phy_status_rpt_jaguar2_type1 *phy_sta_rpt =
- (struct phy_status_rpt_jaguar2_type1 *)phy_status;
- s8 rx_pwr_db = -120;
- u8 i, rxsc, bw = ODM_BW20M, rx_count = 0;
- bool is_mu;
- u8 num_ss;
-
- /* Update OFDM packet counter */
- dm->phy_dbg_info.num_qry_phy_status_ofdm++;
-
- /* Update per-path information */
- for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
- if (dm->rx_ant_status & BIT(i)) {
- s8 rx_path_pwr_db;
-
- /* RX path counter */
- rx_count++;
-
- /* Update per-path information
- * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
- */
- /* EVM report is reported by stream, not path */
- rx_path_pwr_db = phy_sta_rpt->pwdb[i] -
- 110; /* per-path pwdb in dB domain */
- phydm_set_per_path_phy_info(
- i, rx_path_pwr_db,
- phy_sta_rpt->rxevm[rx_count - 1],
- phy_sta_rpt->cfo_tail[i], phy_sta_rpt->rxsnr[i],
- phy_info);
-
- /* search maximum pwdb */
- if (rx_path_pwr_db > rx_pwr_db)
- rx_pwr_db = rx_path_pwr_db;
- }
- }
-
- /* mapping RX counter from 1~4 to 0~3 */
- if (rx_count > 0)
- phy_info->rx_count = rx_count - 1;
-
- /* Check if MU packet or not */
- if ((phy_sta_rpt->gid != 0) && (phy_sta_rpt->gid != 63)) {
- is_mu = true;
- dm->phy_dbg_info.num_qry_mu_pkt++;
- } else {
- is_mu = false;
- }
-
- /* count BF packet */
- dm->phy_dbg_info.num_qry_bf_pkt =
- dm->phy_dbg_info.num_qry_bf_pkt + phy_sta_rpt->beamformed;
-
- /*STBC or LDPC pkt*/
- dm->phy_dbg_info.is_ldpc_pkt = phy_sta_rpt->ldpc;
- dm->phy_dbg_info.is_stbc_pkt = phy_sta_rpt->stbc;
-
- /* Check sub-channel */
- if ((pktinfo->data_rate > ODM_RATE11M) &&
- (pktinfo->data_rate < ODM_RATEMCS0))
- rxsc = phy_sta_rpt->l_rxsc;
- else
- rxsc = phy_sta_rpt->ht_rxsc;
-
- /* Check RX bandwidth */
- if (dm->support_ic_type & ODM_RTL8822B) {
- if ((rxsc >= 1) && (rxsc <= 8))
- bw = ODM_BW20M;
- else if ((rxsc >= 9) && (rxsc <= 12))
- bw = ODM_BW40M;
- else if (rxsc >= 13)
- bw = ODM_BW80M;
- else
- bw = phy_sta_rpt->rf_mode;
- } else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D |
- ODM_RTL8710B)) { /* JJ ADD 20161014 */
- if (phy_sta_rpt->rf_mode == 0)
- bw = ODM_BW20M;
- else if ((rxsc == 1) || (rxsc == 2))
- bw = ODM_BW20M;
- else
- bw = ODM_BW40M;
- }
-
- /* Update packet information */
- phydm_set_common_phy_info(
- rx_pwr_db, phy_sta_rpt->channel, (bool)phy_sta_rpt->beamformed,
- is_mu, bw, odm_evm_db_to_percentage(phy_sta_rpt->rxevm[0]),
- rxsc, phy_info);
-
- num_ss = phydm_rate_to_num_ss(dm, pktinfo->data_rate);
-
- odm_parsing_cfo(dm, pktinfo, phy_sta_rpt->cfo_tail, num_ss);
- dm->dm_fat_table.antsel_rx_keep_0 = phy_sta_rpt->antidx_a;
- dm->dm_fat_table.antsel_rx_keep_1 = phy_sta_rpt->antidx_b;
- dm->dm_fat_table.antsel_rx_keep_2 = phy_sta_rpt->antidx_c;
- dm->dm_fat_table.antsel_rx_keep_3 = phy_sta_rpt->antidx_d;
-
- if (pktinfo->is_packet_match_bssid) {
- /* */
- phydm_rx_statistic_cal(dm, phy_status, pktinfo);
- }
-}
-
-static void phydm_get_rx_phy_status_type2(struct phy_dm_struct *dm,
- u8 *phy_status,
- struct dm_per_pkt_info *pktinfo,
- struct dm_phy_status_info *phy_info)
-{
- struct phy_status_rpt_jaguar2_type2 *phy_sta_rpt =
- (struct phy_status_rpt_jaguar2_type2 *)phy_status;
- s8 rx_pwr_db = -120;
- u8 i, rxsc, bw = ODM_BW20M, rx_count = 0;
-
- /* Update OFDM packet counter */
- dm->phy_dbg_info.num_qry_phy_status_ofdm++;
-
- /* Update per-path information */
- for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
- if (dm->rx_ant_status & BIT(i)) {
- s8 rx_path_pwr_db;
-
- /* RX path counter */
- rx_count++;
-
- /* Update per-path information
- * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
- */
- rx_path_pwr_db = phy_sta_rpt->pwdb[i] -
- 110; /* per-path pwdb in dB domain */
-
- phydm_set_per_path_phy_info(i, rx_path_pwr_db, 0, 0, 0,
- phy_info);
-
- /* search maximum pwdb */
- if (rx_path_pwr_db > rx_pwr_db)
- rx_pwr_db = rx_path_pwr_db;
- }
- }
-
- /* mapping RX counter from 1~4 to 0~3 */
- if (rx_count > 0)
- phy_info->rx_count = rx_count - 1;
-
- /* Check RX sub-channel */
- if ((pktinfo->data_rate > ODM_RATE11M) &&
- (pktinfo->data_rate < ODM_RATEMCS0))
- rxsc = phy_sta_rpt->l_rxsc;
- else
- rxsc = phy_sta_rpt->ht_rxsc;
-
- /*STBC or LDPC pkt*/
- dm->phy_dbg_info.is_ldpc_pkt = phy_sta_rpt->ldpc;
- dm->phy_dbg_info.is_stbc_pkt = phy_sta_rpt->stbc;
-
- /* Check RX bandwidth */
- /* the BW information of sc=0 is useless, because there is
- * no information of RF mode
- */
-
- if (dm->support_ic_type & ODM_RTL8822B) {
- if ((rxsc >= 1) && (rxsc <= 8))
- bw = ODM_BW20M;
- else if ((rxsc >= 9) && (rxsc <= 12))
- bw = ODM_BW40M;
- else if (rxsc >= 13)
- bw = ODM_BW80M;
- else
- bw = ODM_BW20M;
- } else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D |
- ODM_RTL8710B)) { /* JJ ADD 20161014 */
- if (rxsc == 3)
- bw = ODM_BW40M;
- else
- bw = ODM_BW20M;
- }
-
- /* Update packet information */
- phydm_set_common_phy_info(rx_pwr_db, phy_sta_rpt->channel,
- (bool)phy_sta_rpt->beamformed, false, bw, 0,
- rxsc, phy_info);
-}
-
-static void
-phydm_process_rssi_for_dm_new_type(struct phy_dm_struct *dm,
- struct dm_phy_status_info *phy_info,
- struct dm_per_pkt_info *pktinfo)
-{
- s32 undecorated_smoothed_pwdb, accumulate_pwdb;
- u32 rssi_ave;
- u8 i;
- struct rtl_sta_info *entry;
- u8 scaling_factor = 4;
-
- if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
- return;
-
- entry = dm->odm_sta_info[pktinfo->station_id];
-
- if (!IS_STA_VALID(entry))
- return;
-
- if ((!pktinfo->is_packet_match_bssid)) /*data frame only*/
- return;
-
- if (pktinfo->is_packet_beacon)
- dm->phy_dbg_info.num_qry_beacon_pkt++;
-
- if (pktinfo->is_packet_to_self || pktinfo->is_packet_beacon) {
- u32 rssi_linear = 0;
-
- dm->rx_rate = pktinfo->data_rate;
- undecorated_smoothed_pwdb =
- entry->rssi_stat.undecorated_smoothed_pwdb;
- accumulate_pwdb = dm->accumulate_pwdb[pktinfo->station_id];
- dm->rssi_a = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A];
- dm->rssi_b = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B];
- dm->rssi_c = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C];
- dm->rssi_d = phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D];
-
- for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) {
- if (phy_info->rx_mimo_signal_strength[i] != 0)
- rssi_linear += odm_convert_to_linear(
- phy_info->rx_mimo_signal_strength[i]);
- }
-
- switch (phy_info->rx_count + 1) {
- case 2:
- rssi_linear = rssi_linear >> 1;
- break;
- case 3:
- /* rssi_linear/3 ~ rssi_linear*11/32 */
- rssi_linear = ((rssi_linear) + (rssi_linear << 1) +
- (rssi_linear << 3)) >>
- 5;
- break;
- case 4:
- rssi_linear = rssi_linear >> 2;
- break;
- }
- rssi_ave = odm_convert_to_db(rssi_linear);
-
- if (undecorated_smoothed_pwdb <= 0) {
- accumulate_pwdb =
- phy_info->rx_pwdb_all << scaling_factor;
- undecorated_smoothed_pwdb = phy_info->rx_pwdb_all;
- } else {
- accumulate_pwdb = accumulate_pwdb -
- (accumulate_pwdb >> scaling_factor) +
- rssi_ave;
- undecorated_smoothed_pwdb =
- (accumulate_pwdb +
- (1 << (scaling_factor - 1))) >>
- scaling_factor;
- }
-
- entry->rssi_stat.undecorated_smoothed_pwdb =
- undecorated_smoothed_pwdb;
- dm->accumulate_pwdb[pktinfo->station_id] = accumulate_pwdb;
- }
-}
-
-void phydm_rx_phy_status_new_type(struct phy_dm_struct *phydm, u8 *phy_status,
- struct dm_per_pkt_info *pktinfo,
- struct dm_phy_status_info *phy_info)
-{
- u8 phy_status_type = (*phy_status & 0xf);
-
- /* Memory reset */
- phydm_reset_phy_info(phydm, phy_info);
-
- /* Phy status parsing */
- switch (phy_status_type) {
- case 0: {
- phydm_get_rx_phy_status_type0(phydm, phy_status, pktinfo,
- phy_info);
- break;
- }
- case 1: {
- phydm_get_rx_phy_status_type1(phydm, phy_status, pktinfo,
- phy_info);
- break;
- }
- case 2: {
- phydm_get_rx_phy_status_type2(phydm, phy_status, pktinfo,
- phy_info);
- break;
- }
- default:
- return;
- }
-
- /* Update signal strength to UI, and phy_info->rx_pwdb_all is the
- * maximum RSSI of all path
- */
- phy_info->signal_strength = phy_info->rx_pwdb_all;
-
- /* Calculate average RSSI and smoothed RSSI */
- phydm_process_rssi_for_dm_new_type(phydm, phy_info, pktinfo);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __HALHWOUTSRC_H__
-#define __HALHWOUTSRC_H__
-
-/*--------------------------Define -------------------------------------------*/
-#define CCK_RSSI_INIT_COUNT 5
-
-#define RA_RSSI_STATE_INIT 0
-#define RA_RSSI_STATE_SEND 1
-#define RA_RSSI_STATE_HOLD 2
-
-#define CFO_HW_RPT_2_MHZ(val) ((val << 1) + (val >> 1))
-/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */
-
-#define AGC_DIFF_CONFIG_MP(ic, band) \
- (odm_read_and_config_mp_##ic##_agc_tab_diff( \
- dm, array_mp_##ic##_agc_tab_diff_##band, \
- sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
-#define AGC_DIFF_CONFIG_TC(ic, band) \
- (odm_read_and_config_tc_##ic##_agc_tab_diff( \
- dm, array_tc_##ic##_agc_tab_diff_##band, \
- sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
-
-#define AGC_DIFF_CONFIG(ic, band) \
- do { \
- if (dm->is_mp_chip) \
- AGC_DIFF_CONFIG_MP(ic, band); \
- else \
- AGC_DIFF_CONFIG_TC(ic, band); \
- } while (0)
-
-/* ************************************************************
- * structure and define
- * *************************************************************/
-
-struct phy_rx_agc_info {
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 gain : 7, trsw : 1;
-#else
- u8 trsw : 1, gain : 7;
-#endif
-};
-
-struct phy_status_rpt_8192cd {
- struct phy_rx_agc_info path_agc[2];
- u8 ch_corr[2];
- u8 cck_sig_qual_ofdm_pwdb_all;
- u8 cck_agc_rpt_ofdm_cfosho_a;
- u8 cck_rpt_b_ofdm_cfosho_b;
- u8 rsvd_1; /*ch_corr_msb;*/
- u8 noise_power_db_msb;
- s8 path_cfotail[2];
- u8 pcts_mask[2];
- s8 stream_rxevm[2];
- u8 path_rxsnr[2];
- u8 noise_power_db_lsb;
- u8 rsvd_2[3];
- u8 stream_csi[2];
- u8 stream_target_csi[2];
- s8 sig_evm;
- u8 rsvd_3;
-
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
- u8 sgi_en : 1;
- u8 rxsc : 2;
- u8 idle_long : 1;
- u8 r_ant_train_en : 1;
- u8 ant_sel_b : 1;
- u8 ant_sel : 1;
-#else /*_BIG_ENDIAN_ */
- u8 ant_sel : 1;
- u8 ant_sel_b : 1;
- u8 r_ant_train_en : 1;
- u8 idle_long : 1;
- u8 rxsc : 2;
- u8 sgi_en : 1;
- u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
-#endif
-};
-
-struct phy_status_rpt_8812 {
- /* DWORD 0*/
- u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
- u8 chl_num_LSB; /*channel number[7:0]*/
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 chl_num_MSB : 2; /*channel number[9:8]*/
- u8 sub_chnl : 4; /*sub-channel location[3:0]*/
- u8 r_RFMOD : 2; /*RF mode[1:0]*/
-#else /*_BIG_ENDIAN_ */
- u8 r_RFMOD : 2;
- u8 sub_chnl : 4;
- u8 chl_num_MSB : 2;
-#endif
-
- /* DWORD 1*/
- u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/
- s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 */
-/*CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- /*this should be checked again
- *because the definition of 8812 and 8814 is different
- */
- u8 resvd_0 : 6;
- u8 bt_RF_ch_MSB : 2; /*8812A:2'b0, 8814A: bt rf channel keep[7:6]*/
-#else /*_BIG_ENDIAN_*/
- u8 bt_RF_ch_MSB : 2;
- u8 resvd_0 : 6;
-#endif
-
-/* DWORD 2*/
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 ant_div_sw_a : 1; /*8812A: ant_div_sw_a, 8814A: 1'b0*/
- u8 ant_div_sw_b : 1; /*8812A: ant_div_sw_b, 8814A: 1'b0*/
- u8 bt_RF_ch_LSB : 6; /*8812A: 6'b0, 8814A: bt rf channel keep[5:0]*/
-#else /*_BIG_ENDIAN_ */
- u8 bt_RF_ch_LSB : 6;
- u8 ant_div_sw_b : 1;
- u8 ant_div_sw_a : 1;
-#endif
- s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/
- u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
- u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
-
- /* DWORD 3*/
- s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/
- s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/
-
- /* DWORD 4*/
- u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/
- u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/
- u8 resvd_1 : 1; /*1'b0*/
-#else /*_BIG_ENDIAN_*/
- u8 resvd_1 : 1;
- u8 pcts_rpt_valid : 1;
- u8 PCTS_MSK_RPT_3 : 6;
-#endif
- s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 */
- /* 8812A: 16'b0, 8814A: stream 3 and stream 4 RX EVM*/
-
- /* DWORD 5*/
- u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 */
- /* 8812A: stream 1 and 2 CSI, 8814A: path-C and path-D RX SNR*/
- u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 */
- /* path-C and path-D {TRSW, gain[6:0] }*/
-
- /* DWORD 6*/
- s8 sigevm; /*signal field EVM*/
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 antidx_antc : 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/
- u8 antidx_antd : 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/
- u8 dpdt_ctrl_keep : 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/
- u8 GNT_BT_keep : 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/
-#else /*_BIG_ENDIAN_*/
- u8 GNT_BT_keep : 1;
- u8 dpdt_ctrl_keep : 1;
- u8 antidx_antd : 3;
- u8 antidx_antc : 3;
-#endif
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 antidx_anta : 3; /*antidx_anta[2:0]*/
- u8 antidx_antb : 3; /*antidx_antb[2:0]*/
- u8 hw_antsw_occur : 2; /*1'b0*/
-#else /*_BIG_ENDIAN_*/
- u8 hw_antsw_occur : 2;
- u8 antidx_antb : 3;
- u8 antidx_anta : 3;
-#endif
-};
-
-void phydm_reset_rssi_for_dm(struct phy_dm_struct *dm, u8 station_id);
-
-void odm_init_rssi_for_dm(struct phy_dm_struct *dm);
-
-void odm_phy_status_query(struct phy_dm_struct *dm,
- struct dm_phy_status_info *phy_info, u8 *phy_status,
- struct dm_per_pkt_info *pktinfo);
-
-void odm_mac_status_query(struct phy_dm_struct *dm, u8 *mac_status, u8 mac_id,
- bool is_packet_match_bssid, bool is_packet_to_self,
- bool is_packet_beacon);
-
-enum hal_status
-odm_config_rf_with_tx_pwr_track_header_file(struct phy_dm_struct *dm);
-
-enum hal_status
-odm_config_rf_with_header_file(struct phy_dm_struct *dm,
- enum odm_rf_config_type config_type,
- enum odm_rf_radio_path e_rf_path);
-
-enum hal_status
-odm_config_bb_with_header_file(struct phy_dm_struct *dm,
- enum odm_bb_config_type config_type);
-
-enum hal_status odm_config_mac_with_header_file(struct phy_dm_struct *dm);
-
-enum hal_status
-odm_config_fw_with_header_file(struct phy_dm_struct *dm,
- enum odm_fw_config_type config_type,
- u8 *p_firmware, u32 *size);
-
-u32 odm_get_hw_img_version(struct phy_dm_struct *dm);
-
-/*For 8822B only!! need to move to FW finally */
-/*==============================================*/
-void phydm_rx_phy_status_new_type(struct phy_dm_struct *phydm, u8 *phy_status,
- struct dm_per_pkt_info *pktinfo,
- struct dm_phy_status_info *phy_info);
-
-bool phydm_query_is_mu_api(struct phy_dm_struct *phydm, u8 ppdu_idx,
- u8 *p_data_rate, u8 *p_gid);
-
-struct phy_status_rpt_jaguar2_type0 {
- /* DW0 */
- u8 page_num;
- u8 pwdb;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 gain : 6;
- u8 rsvd_0 : 1;
- u8 trsw : 1;
-#else
- u8 trsw : 1;
- u8 rsvd_0 : 1;
- u8 gain : 6;
-#endif
- u8 rsvd_1;
-
- /* DW1 */
- u8 rsvd_2;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 rxsc : 4;
- u8 agc_table : 4;
-#else
- u8 agc_table : 4;
- u8 rxsc : 4;
-#endif
- u8 channel;
- u8 band;
-
- /* DW2 */
- u16 length;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 antidx_a : 3;
- u8 antidx_b : 3;
- u8 rsvd_3 : 2;
- u8 antidx_c : 3;
- u8 antidx_d : 3;
- u8 rsvd_4 : 2;
-#else
- u8 rsvd_3 : 2;
- u8 antidx_b : 3;
- u8 antidx_a : 3;
- u8 rsvd_4 : 2;
- u8 antidx_d : 3;
- u8 antidx_c : 3;
-#endif
-
- /* DW3 */
- u8 signal_quality;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 vga : 5;
- u8 lna_l : 3;
- u8 bb_power : 6;
- u8 rsvd_9 : 1;
- u8 lna_h : 1;
-#else
- u8 lna_l : 3;
- u8 vga : 5;
- u8 lna_h : 1;
- u8 rsvd_9 : 1;
- u8 bb_power : 6;
-#endif
- u8 rsvd_5;
-
- /* DW4 */
- u32 rsvd_6;
-
- /* DW5 */
- u32 rsvd_7;
-
- /* DW6 */
- u32 rsvd_8;
-};
-
-struct phy_status_rpt_jaguar2_type1 {
- /* DW0 and DW1 */
- u8 page_num;
- u8 pwdb[4];
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 l_rxsc : 4;
- u8 ht_rxsc : 4;
-#else
- u8 ht_rxsc : 4;
- u8 l_rxsc : 4;
-#endif
- u8 channel;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 band : 2;
- u8 rsvd_0 : 1;
- u8 hw_antsw_occu : 1;
- u8 gnt_bt : 1;
- u8 ldpc : 1;
- u8 stbc : 1;
- u8 beamformed : 1;
-#else
- u8 beamformed : 1;
- u8 stbc : 1;
- u8 ldpc : 1;
- u8 gnt_bt : 1;
- u8 hw_antsw_occu : 1;
- u8 rsvd_0 : 1;
- u8 band : 2;
-#endif
-
- /* DW2 */
- u16 lsig_length;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 antidx_a : 3;
- u8 antidx_b : 3;
- u8 rsvd_1 : 2;
- u8 antidx_c : 3;
- u8 antidx_d : 3;
- u8 rsvd_2 : 2;
-#else
- u8 rsvd_1 : 2;
- u8 antidx_b : 3;
- u8 antidx_a : 3;
- u8 rsvd_2 : 2;
- u8 antidx_d : 3;
- u8 antidx_c : 3;
-#endif
-
- /* DW3 */
- u8 paid;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 paid_msb : 1;
- u8 gid : 6;
- u8 rsvd_3 : 1;
-#else
- u8 rsvd_3 : 1;
- u8 gid : 6;
- u8 paid_msb : 1;
-#endif
- u8 intf_pos;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 intf_pos_msb : 1;
- u8 rsvd_4 : 2;
- u8 nb_intf_flag : 1;
- u8 rf_mode : 2;
- u8 rsvd_5 : 2;
-#else
- u8 rsvd_5 : 2;
- u8 rf_mode : 2;
- u8 nb_intf_flag : 1;
- u8 rsvd_4 : 2;
- u8 intf_pos_msb : 1;
-#endif
-
- /* DW4 */
- s8 rxevm[4]; /* s(8,1) */
-
- /* DW5 */
- s8 cfo_tail[4]; /* s(8,7) */
-
- /* DW6 */
- s8 rxsnr[4]; /* s(8,1) */
-};
-
-struct phy_status_rpt_jaguar2_type2 {
- /* DW0 ane DW1 */
- u8 page_num;
- u8 pwdb[4];
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 l_rxsc : 4;
- u8 ht_rxsc : 4;
-#else
- u8 ht_rxsc : 4;
- u8 l_rxsc : 4;
-#endif
- u8 channel;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 band : 2;
- u8 rsvd_0 : 1;
- u8 hw_antsw_occu : 1;
- u8 gnt_bt : 1;
- u8 ldpc : 1;
- u8 stbc : 1;
- u8 beamformed : 1;
-#else
- u8 beamformed : 1;
- u8 stbc : 1;
- u8 ldpc : 1;
- u8 gnt_bt : 1;
- u8 hw_antsw_occu : 1;
- u8 rsvd_0 : 1;
- u8 band : 2;
-#endif
-
-/* DW2 */
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 shift_l_map : 6;
- u8 rsvd_1 : 2;
-#else
- u8 rsvd_1 : 2;
- u8 shift_l_map : 6;
-#endif
- u8 cnt_pw2cca;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 agc_table_a : 4;
- u8 agc_table_b : 4;
- u8 agc_table_c : 4;
- u8 agc_table_d : 4;
-#else
- u8 agc_table_b : 4;
- u8 agc_table_a : 4;
- u8 agc_table_d : 4;
- u8 agc_table_c : 4;
-#endif
-
- /* DW3 ~ DW6*/
- u8 cnt_cca2agc_rdy;
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 gain_a : 6;
- u8 rsvd_2 : 1;
- u8 trsw_a : 1;
- u8 gain_b : 6;
- u8 rsvd_3 : 1;
- u8 trsw_b : 1;
- u8 gain_c : 6;
- u8 rsvd_4 : 1;
- u8 trsw_c : 1;
- u8 gain_d : 6;
- u8 rsvd_5 : 1;
- u8 trsw_d : 1;
- u8 aagc_step_a : 2;
- u8 aagc_step_b : 2;
- u8 aagc_step_c : 2;
- u8 aagc_step_d : 2;
-#else
- u8 trsw_a : 1;
- u8 rsvd_2 : 1;
- u8 gain_a : 6;
- u8 trsw_b : 1;
- u8 rsvd_3 : 1;
- u8 gain_b : 6;
- u8 trsw_c : 1;
- u8 rsvd_4 : 1;
- u8 gain_c : 6;
- u8 trsw_d : 1;
- u8 rsvd_5 : 1;
- u8 gain_d : 6;
- u8 aagc_step_d : 2;
- u8 aagc_step_c : 2;
- u8 aagc_step_b : 2;
- u8 aagc_step_a : 2;
-#endif
- u8 ht_aagc_gain[4];
- u8 dagc_gain[4];
-#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
- u8 counter : 6;
- u8 rsvd_6 : 2;
- u8 syn_count : 5;
- u8 rsvd_7 : 3;
-#else
- u8 rsvd_6 : 2;
- u8 counter : 6;
- u8 rsvd_7 : 3;
- u8 syn_count : 5;
-#endif
-};
-
-#endif /*#ifndef __HALHWOUTSRC_H__*/
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-/*
- * ODM IO Relative API.
- */
-
-u8 odm_read_1byte(struct phy_dm_struct *dm, u32 reg_addr)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- return rtl_read_byte(rtlpriv, reg_addr);
-}
-
-u16 odm_read_2byte(struct phy_dm_struct *dm, u32 reg_addr)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- return rtl_read_word(rtlpriv, reg_addr);
-}
-
-u32 odm_read_4byte(struct phy_dm_struct *dm, u32 reg_addr)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- return rtl_read_dword(rtlpriv, reg_addr);
-}
-
-void odm_write_1byte(struct phy_dm_struct *dm, u32 reg_addr, u8 data)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- rtl_write_byte(rtlpriv, reg_addr, data);
-}
-
-void odm_write_2byte(struct phy_dm_struct *dm, u32 reg_addr, u16 data)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- rtl_write_word(rtlpriv, reg_addr, data);
-}
-
-void odm_write_4byte(struct phy_dm_struct *dm, u32 reg_addr, u32 data)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- rtl_write_dword(rtlpriv, reg_addr, data);
-}
-
-void odm_set_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
- u32 data)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
-}
-
-u32 odm_get_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
-}
-
-void odm_set_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
- u32 data)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
-}
-
-u32 odm_get_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
-}
-
-void odm_set_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
- u32 reg_addr, u32 bit_mask, u32 data)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- rtl_set_rfreg(rtlpriv->hw, (enum radio_path)e_rf_path, reg_addr,
- bit_mask, data);
-}
-
-u32 odm_get_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
- u32 reg_addr, u32 bit_mask)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-
- return rtl_get_rfreg(rtlpriv->hw, (enum radio_path)e_rf_path, reg_addr,
- bit_mask);
-}
-
-/*
- * ODM Memory relative API.
- */
-void odm_allocate_memory(struct phy_dm_struct *dm, void **ptr, u32 length)
-{
- *ptr = kmalloc(length, GFP_ATOMIC);
-}
-
-/* length could be ignored, used to detect memory leakage. */
-void odm_free_memory(struct phy_dm_struct *dm, void *ptr, u32 length)
-{
- kfree(ptr);
-}
-
-void odm_move_memory(struct phy_dm_struct *dm, void *p_dest, void *src,
- u32 length)
-{
- memcpy(p_dest, src, length);
-}
-
-void odm_memory_set(struct phy_dm_struct *dm, void *pbuf, s8 value, u32 length)
-{
- memset(pbuf, value, length);
-}
-
-s32 odm_compare_memory(struct phy_dm_struct *dm, void *p_buf1, void *buf2,
- u32 length)
-{
- return memcmp(p_buf1, buf2, length);
-}
-
-/*
- * ODM MISC relative API.
- */
-void odm_acquire_spin_lock(struct phy_dm_struct *dm, enum rt_spinlock_type type)
-{
-}
-
-void odm_release_spin_lock(struct phy_dm_struct *dm, enum rt_spinlock_type type)
-{
-}
-
-/*
- * ODM Timer relative API.
- */
-void odm_stall_execution(u32 us_delay) { udelay(us_delay); }
-
-void ODM_delay_ms(u32 ms) { mdelay(ms); }
-
-void ODM_delay_us(u32 us) { udelay(us); }
-
-void ODM_sleep_ms(u32 ms) { msleep(ms); }
-
-void ODM_sleep_us(u32 us) { usleep_range(us, us + 1); }
-
-static u8 phydm_trans_h2c_id(struct phy_dm_struct *dm, u8 phydm_h2c_id)
-{
- u8 platform_h2c_id = phydm_h2c_id;
-
- switch (phydm_h2c_id) {
- /* 1 [0] */
- case ODM_H2C_RSSI_REPORT:
-
- break;
-
- /* 1 [3] */
- case ODM_H2C_WIFI_CALIBRATION:
-
- break;
-
- /* 1 [4] */
- case ODM_H2C_IQ_CALIBRATION:
-
- break;
- /* 1 [5] */
- case ODM_H2C_RA_PARA_ADJUST:
-
- break;
-
- /* 1 [6] */
- case PHYDM_H2C_DYNAMIC_TX_PATH:
-
- break;
-
- /* [7]*/
- case PHYDM_H2C_FW_TRACE_EN:
-
- platform_h2c_id = 0x49;
-
- break;
-
- case PHYDM_H2C_TXBF:
- break;
-
- case PHYDM_H2C_MU:
- platform_h2c_id = 0x4a; /*H2C_MU*/
- break;
-
- default:
- platform_h2c_id = phydm_h2c_id;
- break;
- }
-
- return platform_h2c_id;
-}
-
-/*ODM FW relative API.*/
-
-void odm_fill_h2c_cmd(struct phy_dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len,
- u8 *cmd_buffer)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- u8 platform_h2c_id;
-
- platform_h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id);
-
- ODM_RT_TRACE(dm, PHYDM_COMP_RA_DBG,
- "[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id);
-
- rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, platform_h2c_id, cmd_len,
- cmd_buffer);
-}
-
-u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
- u8 *tmp_buf)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 extend_c2h_sub_id = 0;
- u8 find_c2h_cmd = true;
-
- switch (c2h_cmd_id) {
- case PHYDM_C2H_DBG:
- phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len);
- break;
-
- case PHYDM_C2H_RA_RPT:
- phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len);
- break;
-
- case PHYDM_C2H_RA_PARA_RPT:
- odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len);
- break;
-
- case PHYDM_C2H_DYNAMIC_TX_PATH_RPT:
- break;
-
- case PHYDM_C2H_IQK_FINISH:
- break;
-
- case PHYDM_C2H_DBG_CODE:
- phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len);
- break;
-
- case PHYDM_C2H_EXTEND:
- extend_c2h_sub_id = tmp_buf[0];
- if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT)
- phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len);
-
- break;
-
- default:
- find_c2h_cmd = false;
- break;
- }
-
- return find_c2h_cmd;
-}
-
-u64 odm_get_current_time(struct phy_dm_struct *dm) { return jiffies; }
-
-u64 odm_get_progressing_time(struct phy_dm_struct *dm, u64 start_time)
-{
- return jiffies_to_msecs(jiffies - (u32)start_time);
-}
-
-void odm_set_tx_power_index_by_rate_section(struct phy_dm_struct *dm,
- u8 rf_path, u8 channel,
- u8 rate_section)
-{
- void *adapter = dm->adapter;
-
- phy_set_tx_power_index_by_rs(adapter, channel, rf_path, rate_section);
-}
-
-u8 odm_get_tx_power_index(struct phy_dm_struct *dm, u8 rf_path, u8 tx_rate,
- u8 band_width, u8 channel)
-{
- void *adapter = dm->adapter;
-
- return phy_get_tx_power_index(adapter, (enum odm_rf_radio_path)rf_path,
- tx_rate, band_width, channel);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __ODM_INTERFACE_H__
-#define __ODM_INTERFACE_H__
-
-#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/
-
-/*
- * =========== Constant/Structure/Enum/... Define
- */
-
-/*
- * =========== Macro Define
- */
-
-#define _reg_all(_name) ODM_##_name
-#define _reg_ic(_name, _ic) ODM_##_name##_ic
-#define _bit_all(_name) BIT_##_name
-#define _bit_ic(_name, _ic) BIT_##_name##_ic
-
-/* _cat: implemented by Token-Pasting Operator. */
-
-/*===================================
- *
- * #define ODM_REG_DIG_11N 0xC50
- * #define ODM_REG_DIG_11AC 0xDDD
- *
- * ODM_REG(DIG,_pdm_odm)
- * ===================================
- */
-
-#define _reg_11N(_name) ODM_REG_##_name##_11N
-#define _reg_11AC(_name) ODM_REG_##_name##_11AC
-#define _bit_11N(_name) ODM_BIT_##_name##_11N
-#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
-
-#define _cat(_name, _ic_type, _func) \
- (((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
- _func##_11AC(_name))
-
-/* _name: name of register or bit.
- * Example: "ODM_REG(R_A_AGC_CORE1, dm)"
- * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C",
- * depends on support_ic_type.
- */
-#define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg)
-#define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit)
-enum phydm_h2c_cmd {
- PHYDM_H2C_TXBF = 0x41,
- ODM_H2C_RSSI_REPORT = 0x42,
- ODM_H2C_IQ_CALIBRATION = 0x45,
- ODM_H2C_RA_PARA_ADJUST = 0x47,
- PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
- PHYDM_H2C_FW_TRACE_EN = 0x49,
- ODM_H2C_WIFI_CALIBRATION = 0x6d,
- PHYDM_H2C_MU = 0x4a,
- ODM_MAX_H2CCMD
-};
-
-enum phydm_c2h_evt {
- PHYDM_C2H_DBG = 0,
- PHYDM_C2H_LB = 1,
- PHYDM_C2H_XBF = 2,
- PHYDM_C2H_TX_REPORT = 3,
- PHYDM_C2H_INFO = 9,
- PHYDM_C2H_BT_MP = 11,
- PHYDM_C2H_RA_RPT = 12,
- PHYDM_C2H_RA_PARA_RPT = 14,
- PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
- PHYDM_C2H_IQK_FINISH = 17, /*0x11*/
- PHYDM_C2H_DBG_CODE = 0xFE,
- PHYDM_C2H_EXTEND = 0xFF,
-};
-
-enum phydm_extend_c2h_evt {
- PHYDM_EXTEND_C2H_DBG_PRINT = 0
-
-};
-
-/*
- * =========== Extern Variable ??? It should be forbidden.
- */
-
-/*
- * =========== EXtern Function Prototype
- */
-
-u8 odm_read_1byte(struct phy_dm_struct *dm, u32 reg_addr);
-
-u16 odm_read_2byte(struct phy_dm_struct *dm, u32 reg_addr);
-
-u32 odm_read_4byte(struct phy_dm_struct *dm, u32 reg_addr);
-
-void odm_write_1byte(struct phy_dm_struct *dm, u32 reg_addr, u8 data);
-
-void odm_write_2byte(struct phy_dm_struct *dm, u32 reg_addr, u16 data);
-
-void odm_write_4byte(struct phy_dm_struct *dm, u32 reg_addr, u32 data);
-
-void odm_set_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
- u32 data);
-
-u32 odm_get_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask);
-
-void odm_set_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
- u32 data);
-
-u32 odm_get_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask);
-
-void odm_set_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
- u32 reg_addr, u32 bit_mask, u32 data);
-
-u32 odm_get_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path,
- u32 reg_addr, u32 bit_mask);
-
-/*
- * Memory Relative Function.
- */
-void odm_allocate_memory(struct phy_dm_struct *dm, void **ptr, u32 length);
-void odm_free_memory(struct phy_dm_struct *dm, void *ptr, u32 length);
-
-void odm_move_memory(struct phy_dm_struct *dm, void *p_dest, void *src,
- u32 length);
-
-s32 odm_compare_memory(struct phy_dm_struct *dm, void *p_buf1, void *buf2,
- u32 length);
-
-void odm_memory_set(struct phy_dm_struct *dm, void *pbuf, s8 value, u32 length);
-
-/*
- * ODM MISC-spin lock relative API.
- */
-void odm_acquire_spin_lock(struct phy_dm_struct *dm,
- enum rt_spinlock_type type);
-
-void odm_release_spin_lock(struct phy_dm_struct *dm,
- enum rt_spinlock_type type);
-
-/*
- * ODM Timer relative API.
- */
-void odm_stall_execution(u32 us_delay);
-
-void ODM_delay_ms(u32 ms);
-
-void ODM_delay_us(u32 us);
-
-void ODM_sleep_ms(u32 ms);
-
-void ODM_sleep_us(u32 us);
-
-/*
- * ODM FW relative API.
- */
-void odm_fill_h2c_cmd(struct phy_dm_struct *dm, u8 element_id, u32 cmd_len,
- u8 *cmd_buffer);
-
-u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
- u8 *tmp_buf);
-
-u64 odm_get_current_time(struct phy_dm_struct *dm);
-u64 odm_get_progressing_time(struct phy_dm_struct *dm, u64 start_time);
-
-void odm_set_tx_power_index_by_rate_section(struct phy_dm_struct *dm,
- u8 rf_path, u8 channel,
- u8 rate_section);
-
-u8 odm_get_tx_power_index(struct phy_dm_struct *dm, u8 rf_path, u8 tx_rate,
- u8 band_width, u8 channel);
-
-#endif /* __ODM_INTERFACE_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMIQK_H__
-#define __PHYDMIQK_H__
-
-/*--------------------------Define Parameters-------------------------------*/
-#define LOK_delay 1
-#define WBIQK_delay 10
-#define TX_IQK 0
-#define RX_IQK 1
-#define TXIQK 0
-#define RXIQK1 1
-#define RXIQK2 2
-#define GSRXK1 0
-#define GSRXK2 1
-#define kcount_limit_80m 2
-#define kcount_limit_others 4
-#define rxiqk_gs_limit 4
-
-#define NUM 4
-/*----------------------End Define Parameters-------------------------------*/
-
-struct dm_iqk_info {
- bool lok_fail[NUM];
- bool iqk_fail[2][NUM];
- u32 iqc_matrix[2][NUM];
- u8 iqk_times;
- u32 rf_reg18;
- u32 lna_idx;
- u8 rxiqk_step;
- u8 tmp1bcc;
- u8 kcount;
-
- u32 iqk_channel[2];
- bool iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
- u32 iqk_cfir_real[2][4][2]
- [8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
- u32 iqk_cfir_imag[2][4][2]
- [8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
- u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
- u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
- u8 rxiqk_fail_code[2][4]; /* channel / path
- * 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail
- */
- u32 lok_idac[2][4]; /*channel / path*/
- u16 rxiqk_agc[2][4]; /*channel / path*/
- u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
- u32 tmp_gntwl;
- bool is_btg;
- bool isbnd;
-};
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/*============================================================*/
-/*include files*/
-/*============================================================*/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-/*<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
-/*This is a phydm API*/
-
-static void phydm_set_kfree_to_rf_8814a(void *dm_void, u8 e_rf_path, u8 data)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
- bool is_odd;
-
- if ((data % 2) != 0) { /*odd->positive*/
- data = data - 1;
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19),
- 1);
- is_odd = true;
- } else { /*even->negative*/
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19),
- 0);
- is_odd = false;
- }
- ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): RF_0x55[19]= %d\n", __func__,
- is_odd);
- switch (data) {
- case 0:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 0);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 0);
- cali_info->kfree_offset[e_rf_path] = 0;
- break;
- case 2:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 1);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 0);
- cali_info->kfree_offset[e_rf_path] = 0;
- break;
- case 4:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 0);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 1);
- cali_info->kfree_offset[e_rf_path] = 1;
- break;
- case 6:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 1);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 1);
- cali_info->kfree_offset[e_rf_path] = 1;
- break;
- case 8:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 0);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 2);
- cali_info->kfree_offset[e_rf_path] = 2;
- break;
- case 10:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 1);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 2);
- cali_info->kfree_offset[e_rf_path] = 2;
- break;
- case 12:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 0);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 3);
- cali_info->kfree_offset[e_rf_path] = 3;
- break;
- case 14:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 1);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 3);
- cali_info->kfree_offset[e_rf_path] = 3;
- break;
- case 16:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 0);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 4);
- cali_info->kfree_offset[e_rf_path] = 4;
- break;
- case 18:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 1);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 4);
- cali_info->kfree_offset[e_rf_path] = 4;
- break;
- case 20:
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14),
- 0);
- odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET,
- BIT(17) | BIT(16) | BIT(15), 5);
- cali_info->kfree_offset[e_rf_path] = 5;
- break;
-
- default:
- break;
- }
-
- if (!is_odd) {
- /*that means Kfree offset is negative, we need to record it.*/
- cali_info->kfree_offset[e_rf_path] =
- (-1) * cali_info->kfree_offset[e_rf_path];
- ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): kfree_offset = %d\n",
- __func__, cali_info->kfree_offset[e_rf_path]);
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): kfree_offset = %d\n",
- __func__, cali_info->kfree_offset[e_rf_path]);
- }
-}
-
-static void phydm_set_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_RTL8814A)
- phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data);
-}
-
-void phydm_config_kfree(void *dm_void, u8 channel_to_sw, u8 *kfree_table)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
- u8 rfpath = 0, max_rf_path = 0;
- u8 channel_idx = 0;
-
- if (dm->support_ic_type & ODM_RTL8814A)
- max_rf_path = 4; /*0~3*/
- else if (dm->support_ic_type &
- (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B))
- max_rf_path = 2; /*0~1*/
- else
- max_rf_path = 1;
-
- ODM_RT_TRACE(dm, ODM_COMP_MP, "===>%s()\n", __func__);
-
- if (cali_info->reg_rf_kfree_enable == 2) {
- ODM_RT_TRACE(dm, ODM_COMP_MP,
- "%s(): reg_rf_kfree_enable == 2, Disable\n",
- __func__);
- return;
- }
-
- if (cali_info->reg_rf_kfree_enable != 1 &&
- cali_info->reg_rf_kfree_enable != 0) {
- ODM_RT_TRACE(dm, ODM_COMP_MP, "<===%s()\n", __func__);
- return;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): reg_rf_kfree_enable == true\n",
- __func__);
- /*Make sure the targetval is defined*/
- if (((cali_info->reg_rf_kfree_enable == 1) &&
- (kfree_table[0] != 0xFF)) ||
- cali_info->rf_kfree_enable) {
- /*if kfree_table[0] == 0xff, means no Kfree*/
- if (*dm->band_type == ODM_BAND_2_4G) {
- if (channel_to_sw <= 14 && channel_to_sw >= 1)
- channel_idx = PHYDM_2G;
- } else if (*dm->band_type == ODM_BAND_5G) {
- if (channel_to_sw >= 36 && channel_to_sw <= 48)
- channel_idx = PHYDM_5GLB1;
- if (channel_to_sw >= 52 && channel_to_sw <= 64)
- channel_idx = PHYDM_5GLB2;
- if (channel_to_sw >= 100 && channel_to_sw <= 120)
- channel_idx = PHYDM_5GMB1;
- if (channel_to_sw >= 124 && channel_to_sw <= 144)
- channel_idx = PHYDM_5GMB2;
- if (channel_to_sw >= 149 && channel_to_sw <= 177)
- channel_idx = PHYDM_5GHB;
- }
-
- for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) {
- ODM_RT_TRACE(dm, ODM_COMP_MP, "%s(): PATH_%d: %#x\n",
- __func__, rfpath,
- kfree_table[channel_idx * max_rf_path +
- rfpath]);
- phydm_set_kfree_to_rf(
- dm, rfpath,
- kfree_table[channel_idx * max_rf_path +
- rfpath]);
- }
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_MP,
- "%s(): targetval not defined, Don't execute KFree Process.\n",
- __func__);
- return;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_MP, "<===%s()\n", __func__);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMKFREE_H__
-#define __PHYDMKFREE_H__
-
-#define KFREE_VERSION "1.0"
-
-enum phydm_kfree_channeltosw {
- PHYDM_2G = 0,
- PHYDM_5GLB1 = 1,
- PHYDM_5GLB2 = 2,
- PHYDM_5GMB1 = 3,
- PHYDM_5GMB2 = 4,
- PHYDM_5GHB = 5,
-};
-
-void phydm_config_kfree(void *dm_void, u8 channel_to_sw, u8 *kfree_table);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-#include "phydm_noisemonitor.h"
-
-/* *************************************************
- * This function is for inband noise test utility only
- * To obtain the inband noise level(dbm), do the following.
- * 1. disable DIG and Power Saving
- * 2. Set initial gain = 0x1a
- * 3. Stop updating idle time pwer report (for driver read)
- * - 0x80c[25]
- *
- * **************************************************/
-
-#define VALID_MIN -35
-#define VALID_MAX 10
-#define VALID_CNT 5
-
-static inline void phydm_set_noise_data_sum(struct noise_level *noise_data,
- u8 max_rf_path)
-{
- u8 rf_path;
-
- for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
- if (noise_data->valid_cnt[rf_path])
- noise_data->sum[rf_path] /=
- noise_data->valid_cnt[rf_path];
- else
- noise_data->sum[rf_path] = 0;
- }
-}
-
-static s16 odm_inband_noise_monitor_n_series(struct phy_dm_struct *dm,
- u8 is_pause_dig, u8 igi_value,
- u32 max_time)
-{
- u32 tmp4b;
- u8 max_rf_path = 0, rf_path;
- u8 reg_c50, reg_c58, valid_done = 0;
- struct noise_level noise_data;
- u64 start = 0, func_start = 0, func_end = 0;
-
- func_start = odm_get_current_time(dm);
- dm->noise_level.noise_all = 0;
-
- if ((dm->rf_type == ODM_1T2R) || (dm->rf_type == ODM_2T2R))
- max_rf_path = 2;
- else
- max_rf_path = 1;
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() ==>\n", __func__);
-
- odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
-
- /* */
- /* step 1. Disable DIG && Set initial gain. */
- /* */
-
- if (is_pause_dig)
- odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
- /* */
- /* step 2. Disable all power save for read registers */
- /* */
- /* dcmd_DebugControlPowerSave(adapter, PSDisable); */
-
- /* */
- /* step 3. Get noise power level */
- /* */
- start = odm_get_current_time(dm);
- while (1) {
- /* Stop updating idle time pwer report (for driver read) */
- odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
-
- /* Read Noise Floor Report */
- tmp4b = odm_get_bb_reg(dm, 0x8f8, MASKDWORD);
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b);
-
- /* update idle time pwer report per 5us */
- odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
-
- noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff);
- noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
- noise_data.value[ODM_RF_PATH_A],
- noise_data.value[ODM_RF_PATH_A],
- noise_data.value[ODM_RF_PATH_B],
- noise_data.value[ODM_RF_PATH_B]);
-
- for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path;
- rf_path++) {
- noise_data.sval[rf_path] =
- (s8)noise_data.value[rf_path];
- noise_data.sval[rf_path] /= 2;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "sval_a = %d, sval_b = %d\n",
- noise_data.sval[ODM_RF_PATH_A],
- noise_data.sval[ODM_RF_PATH_B]);
-
- for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path;
- rf_path++) {
- if (!(noise_data.valid_cnt[rf_path] < VALID_CNT) ||
- !(noise_data.sval[rf_path] < VALID_MAX &&
- noise_data.sval[rf_path] >= VALID_MIN)) {
- continue;
- }
-
- noise_data.valid_cnt[rf_path]++;
- noise_data.sum[rf_path] += noise_data.sval[rf_path];
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "rf_path:%d Valid sval = %d\n", rf_path,
- noise_data.sval[rf_path]);
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "Sum of sval = %d,\n",
- noise_data.sum[rf_path]);
- if (noise_data.valid_cnt[rf_path] == VALID_CNT) {
- valid_done++;
- ODM_RT_TRACE(
- dm, ODM_COMP_COMMON,
- "After divided, rf_path:%d,sum = %d\n",
- rf_path, noise_data.sum[rf_path]);
- }
- }
-
- if ((valid_done == max_rf_path) ||
- (odm_get_progressing_time(dm, start) > max_time)) {
- phydm_set_noise_data_sum(&noise_data, max_rf_path);
- break;
- }
- }
- reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
- reg_c50 &= ~BIT(7);
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "0x%x = 0x%02x(%d)\n",
- REG_OFDM_0_XA_AGC_CORE1, reg_c50, reg_c50);
- dm->noise_level.noise[ODM_RF_PATH_A] =
- (u8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]);
- dm->noise_level.noise_all += dm->noise_level.noise[ODM_RF_PATH_A];
-
- if (max_rf_path == 2) {
- reg_c58 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XB_AGC_CORE1,
- MASKBYTE0);
- reg_c58 &= ~BIT(7);
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "0x%x = 0x%02x(%d)\n",
- REG_OFDM_0_XB_AGC_CORE1, reg_c58, reg_c58);
- dm->noise_level.noise[ODM_RF_PATH_B] =
- (u8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]);
- dm->noise_level.noise_all +=
- dm->noise_level.noise[ODM_RF_PATH_B];
- }
- dm->noise_level.noise_all /= max_rf_path;
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "noise_a = %d, noise_b = %d\n",
- dm->noise_level.noise[ODM_RF_PATH_A],
- dm->noise_level.noise[ODM_RF_PATH_B]);
-
- /* */
- /* step 4. Recover the Dig */
- /* */
- if (is_pause_dig)
- odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
- func_end = odm_get_progressing_time(dm, func_start);
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() <==\n", __func__);
- return dm->noise_level.noise_all;
-}
-
-static s16 odm_inband_noise_monitor_ac_series(struct phy_dm_struct *dm,
- u8 is_pause_dig, u8 igi_value,
- u32 max_time)
-{
- s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
- s32 value32, pwdb_A = 0, sval, noise, sum;
- bool pd_flag;
- u8 valid_cnt;
- u64 start = 0, func_start = 0, func_end = 0;
-
- if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
- return 0;
-
- func_start = odm_get_current_time(dm);
- dm->noise_level.noise_all = 0;
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() ==>\n", __func__);
-
- /* step 1. Disable DIG && Set initial gain. */
- if (is_pause_dig)
- odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
-
- /* step 2. Disable all power save for read registers */
- /*dcmd_DebugControlPowerSave(adapter, PSDisable); */
-
- /* step 3. Get noise power level */
- start = odm_get_current_time(dm);
-
- /* reset counters */
- sum = 0;
- valid_cnt = 0;
-
- /* step 3. Get noise power level */
- while (1) {
- /*Set IGI=0x1C */
- odm_write_dig(dm, 0x1C);
- /*stop CK320&CK88 */
- odm_set_bb_reg(dm, 0x8B4, BIT(6), 1);
- /*Read path-A */
- odm_set_bb_reg(dm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/
- value32 = odm_get_bb_reg(dm, 0xFA0,
- MASKDWORD); /*read debug port*/
-
- rxi_buf_anta = (value32 & 0xFFC00) >>
- 10; /*rxi_buf_anta=RegFA0[19:10]*/
- rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
-
- pd_flag = (bool)((value32 & BIT(31)) >> 31);
-
- /*Not in packet detection period or Tx state */
- if ((!pd_flag) || (rxi_buf_anta != 0x200)) {
- /*sign conversion*/
- rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
- rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
-
- pwdb_A = odm_pwdb_conversion(
- rxi_buf_anta * rxi_buf_anta +
- rxq_buf_anta * rxq_buf_anta,
- 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/
-
- ODM_RT_TRACE(
- dm, ODM_COMP_COMMON,
- "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n",
- pwdb_A, rxi_buf_anta & 0x3FF,
- rxq_buf_anta & 0x3FF);
- }
- /*Start CK320&CK88*/
- odm_set_bb_reg(dm, 0x8B4, BIT(6), 0);
- /*BB Reset*/
- odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) & (~BIT(0)));
- odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) | BIT(0));
- /*PMAC Reset*/
- odm_write_1byte(dm, 0xB03,
- odm_read_1byte(dm, 0xB03) & (~BIT(0)));
- odm_write_1byte(dm, 0xB03, odm_read_1byte(dm, 0xB03) | BIT(0));
- /*CCK Reset*/
- if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
- odm_write_1byte(dm, 0x80B,
- odm_read_1byte(dm, 0x80B) & (~BIT(4)));
- odm_write_1byte(dm, 0x80B,
- odm_read_1byte(dm, 0x80B) | BIT(4));
- }
-
- sval = pwdb_A;
-
- if ((sval < 0 && sval >= -27) && (valid_cnt < VALID_CNT)) {
- valid_cnt++;
- sum += sval;
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "Valid sval = %d\n",
- sval);
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "Sum of sval = %d,\n",
- sum);
- if ((valid_cnt >= VALID_CNT) ||
- (odm_get_progressing_time(dm, start) > max_time)) {
- sum /= VALID_CNT;
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "After divided, sum = %d\n", sum);
- break;
- }
- }
- }
-
- /*ADC backoff is 12dB,*/
- /*Ptarget=0x1C-110=-82dBm*/
- noise = sum + 12 + 0x1C - 110;
-
- /*Offset*/
- noise = noise - 3;
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "noise = %d\n", noise);
- dm->noise_level.noise_all = (s16)noise;
-
- /* step 4. Recover the Dig*/
- if (is_pause_dig)
- odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
-
- func_end = odm_get_progressing_time(dm, func_start);
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s() <==\n", __func__);
-
- return dm->noise_level.noise_all;
-}
-
-s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
- u32 max_time)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES)
- return odm_inband_noise_monitor_ac_series(dm, is_pause_dig,
- igi_value, max_time);
- else
- return odm_inband_noise_monitor_n_series(dm, is_pause_dig,
- igi_value, max_time);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __ODMNOISEMONITOR_H__
-#define __ODMNOISEMONITOR_H__
-
-#define ODM_MAX_CHANNEL_NUM 38 /* 14+24 */
-struct noise_level {
- u8 value[MAX_RF_PATH];
- s8 sval[MAX_RF_PATH];
-
- s32 sum[MAX_RF_PATH];
- u8 valid[MAX_RF_PATH];
- u8 valid_cnt[MAX_RF_PATH];
-};
-
-struct odm_noise_monitor {
- s8 noise[MAX_RF_PATH];
- s16 noise_all;
-};
-
-s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
- u32 max_time);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/*============================================================ */
-/* include files */
-/*============================================================ */
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-/* ************************************************************
- * Global var
- * *************************************************************/
-
-u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
- 0x7f8001fe, /* 0, +6.0dB */
- 0x788001e2, /* 1, +5.5dB */
- 0x71c001c7, /* 2, +5.0dB*/
- 0x6b8001ae, /* 3, +4.5dB*/
- 0x65400195, /* 4, +4.0dB*/
- 0x5fc0017f, /* 5, +3.5dB*/
- 0x5a400169, /* 6, +3.0dB*/
- 0x55400155, /* 7, +2.5dB*/
- 0x50800142, /* 8, +2.0dB*/
- 0x4c000130, /* 9, +1.5dB*/
- 0x47c0011f, /* 10, +1.0dB*/
- 0x43c0010f, /* 11, +0.5dB*/
- 0x40000100, /* 12, +0dB*/
- 0x3c8000f2, /* 13, -0.5dB*/
- 0x390000e4, /* 14, -1.0dB*/
- 0x35c000d7, /* 15, -1.5dB*/
- 0x32c000cb, /* 16, -2.0dB*/
- 0x300000c0, /* 17, -2.5dB*/
- 0x2d4000b5, /* 18, -3.0dB*/
- 0x2ac000ab, /* 19, -3.5dB*/
- 0x288000a2, /* 20, -4.0dB*/
- 0x26000098, /* 21, -4.5dB*/
- 0x24000090, /* 22, -5.0dB*/
- 0x22000088, /* 23, -5.5dB*/
- 0x20000080, /* 24, -6.0dB*/
- 0x1e400079, /* 25, -6.5dB*/
- 0x1c800072, /* 26, -7.0dB*/
- 0x1b00006c, /* 27. -7.5dB*/
- 0x19800066, /* 28, -8.0dB*/
- 0x18000060, /* 29, -8.5dB*/
- 0x16c0005b, /* 30, -9.0dB*/
- 0x15800056, /* 31, -9.5dB*/
- 0x14400051, /* 32, -10.0dB*/
- 0x1300004c, /* 33, -10.5dB*/
- 0x12000048, /* 34, -11.0dB*/
- 0x11000044, /* 35, -11.5dB*/
- 0x10000040, /* 36, -12.0dB*/
-};
-
-u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
- {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
- {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
- {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/
- {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/
- {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
- {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/
- {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/
- {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/
- {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
- {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/
- {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
- {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/
- {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04,
- 0x02}, /* 12, -6.0dB <== default */
- {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/
- {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
- {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/
- {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
- {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/
- {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
- {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/
- {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
- {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
- {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
- {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
- {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
- {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
- {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
- {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
- {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
- {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
- {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
- {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
- {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
-};
-
-u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
- {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
- {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
- {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
- {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/
- {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
- {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/
- {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
- {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
- {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
- {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/
- {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
- {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/
- {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00,
- 0x00}, /* 12, -6.0dB <== default*/
- {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
- {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
- {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/
- {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
- {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/
- {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
- {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/
- {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
- {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
- {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
- {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
- {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
- {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
- {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
- {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
- {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
- {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
- {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
- {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
- {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
-};
-
-u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
- 0x0b40002d, /* 0, -15.0dB */
- 0x0c000030, /* 1, -14.5dB*/
- 0x0cc00033, /* 2, -14.0dB*/
- 0x0d800036, /* 3, -13.5dB*/
- 0x0e400039, /* 4, -13.0dB */
- 0x0f00003c, /* 5, -12.5dB*/
- 0x10000040, /* 6, -12.0dB*/
- 0x11000044, /* 7, -11.5dB*/
- 0x12000048, /* 8, -11.0dB*/
- 0x1300004c, /* 9, -10.5dB*/
- 0x14400051, /* 10, -10.0dB*/
- 0x15800056, /* 11, -9.5dB*/
- 0x16c0005b, /* 12, -9.0dB*/
- 0x18000060, /* 13, -8.5dB*/
- 0x19800066, /* 14, -8.0dB*/
- 0x1b00006c, /* 15, -7.5dB*/
- 0x1c800072, /* 16, -7.0dB*/
- 0x1e400079, /* 17, -6.5dB*/
- 0x20000080, /* 18, -6.0dB*/
- 0x22000088, /* 19, -5.5dB*/
- 0x24000090, /* 20, -5.0dB*/
- 0x26000098, /* 21, -4.5dB*/
- 0x288000a2, /* 22, -4.0dB*/
- 0x2ac000ab, /* 23, -3.5dB*/
- 0x2d4000b5, /* 24, -3.0dB*/
- 0x300000c0, /* 25, -2.5dB*/
- 0x32c000cb, /* 26, -2.0dB*/
- 0x35c000d7, /* 27, -1.5dB*/
- 0x390000e4, /* 28, -1.0dB*/
- 0x3c8000f2, /* 29, -0.5dB*/
- 0x40000100, /* 30, +0dB*/
- 0x43c0010f, /* 31, +0.5dB*/
- 0x47c0011f, /* 32, +1.0dB*/
- 0x4c000130, /* 33, +1.5dB*/
- 0x50800142, /* 34, +2.0dB*/
- 0x55400155, /* 35, +2.5dB*/
- 0x5a400169, /* 36, +3.0dB*/
- 0x5fc0017f, /* 37, +3.5dB*/
- 0x65400195, /* 38, +4.0dB*/
- 0x6b8001ae, /* 39, +4.5dB*/
- 0x71c001c7, /* 40, +5.0dB*/
- 0x788001e2, /* 41, +5.5dB*/
- 0x7f8001fe /* 42, +6.0dB*/
-};
-
-u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
- {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
- {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
- {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
- {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
- {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
- {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
- {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
- {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
- {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
- {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
- {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
- {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
- {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
- {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
- {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
- {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
- {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
- {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
- {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
- {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
- {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00} /*-6dB*/
-};
-
-u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
- {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
- {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
- {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
- {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
- {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
- {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
- {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
- {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
- {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
- {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
- {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
- {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
- {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
- {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
- {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
- {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
- {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
- {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
- {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
- {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
- {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00} /*-6dB*/
-};
-
-u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
- {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
- {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
- {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
- {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
- {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
- {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
- {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
- {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
- {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
- {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
- {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
- {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
- {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
- {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
- {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
- {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
- {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
- {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
- {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
- {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
- {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00} /*-6dB*/
-};
-
-u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
- {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/
- {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/
- {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/
- {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/
- {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/
- {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/
- {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/
- {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/
- {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/
- {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/
- {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/
- {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/
- {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/
- {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/
- {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
- {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/
- {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
- {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/
- {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
- {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/
- {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */
- {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/
- {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
- {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/
- {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
- {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/
- {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/
- {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/
- {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
- {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/
- {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/
- {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/
- {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/
-};
-
-u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
- {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/
- {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
- {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/
- {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
- {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/
- {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
- {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
- {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/
- {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
- {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
- {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
- {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
- {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
- {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
- {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
- {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
- {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
- {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
- {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
- {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
- {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
- {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
- {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
- {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
- {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
- {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
- {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
- {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
- {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
- {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
- {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
- {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
- {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
-};
-
-u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
- 0x0CD, /*0 , -20dB*/
- 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158, 0x16C,
- 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263, 0x287,
- 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F, 0x47F,
- 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C, 0x7FF,
-};
-
-/* JJ ADD 20161014 */
-u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
- 0x0CD, /*0 , -20dB*/
- 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158, 0x16C,
- 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263, 0x287,
- 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F, 0x47F,
- 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C, 0x7FF,
-};
-
-u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
- 0x081, /* 0, -12.0dB*/
- 0x088, /* 1, -11.5dB*/
- 0x090, /* 2, -11.0dB*/
- 0x099, /* 3, -10.5dB*/
- 0x0A2, /* 4, -10.0dB*/
- 0x0AC, /* 5, -9.5dB*/
- 0x0B6, /* 6, -9.0dB*/
- 0x0C0, /*7, -8.5dB*/
- 0x0CC, /* 8, -8.0dB*/
- 0x0D8, /* 9, -7.5dB*/
- 0x0E5, /* 10, -7.0dB*/
- 0x0F2, /* 11, -6.5dB*/
- 0x101, /* 12, -6.0dB*/
- 0x110, /* 13, -5.5dB*/
- 0x120, /* 14, -5.0dB*/
- 0x131, /* 15, -4.5dB*/
- 0x143, /* 16, -4.0dB*/
- 0x156, /* 17, -3.5dB*/
- 0x16A, /* 18, -3.0dB*/
- 0x180, /* 19, -2.5dB*/
- 0x197, /* 20, -2.0dB*/
- 0x1AF, /* 21, -1.5dB*/
- 0x1C8, /* 22, -1.0dB*/
- 0x1E3, /* 23, -0.5dB*/
- 0x200, /* 24, +0 dB*/
- 0x21E, /* 25, +0.5dB*/
- 0x23E, /* 26, +1.0dB*/
- 0x261, /* 27, +1.5dB*/
- 0x285, /* 28, +2.0dB*/
- 0x2AB, /* 29, +2.5dB*/
- 0x2D3, /*30, +3.0dB*/
- 0x2FE, /* 31, +3.5dB*/
- 0x32B, /* 32, +4.0dB*/
- 0x35C, /* 33, +4.5dB*/
- 0x38E, /* 34, +5.0dB*/
- 0x3C4, /* 35, +5.5dB*/
- 0x3FE /* 36, +6.0dB */
-};
-
-void odm_txpowertracking_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- odm_txpowertracking_thermal_meter_init(dm);
-}
-
-static u8 get_swing_index(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 i = 0;
- u32 bb_swing;
- u32 swing_table_size;
- u32 *swing_table;
-
- if (dm->support_ic_type == ODM_RTL8188E ||
- dm->support_ic_type == ODM_RTL8723B ||
- dm->support_ic_type == ODM_RTL8192E ||
- dm->support_ic_type == ODM_RTL8188F ||
- dm->support_ic_type == ODM_RTL8703B) {
- bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
- 0xFFC00000);
-
- swing_table = ofdm_swing_table_new;
- swing_table_size = OFDM_TABLE_SIZE;
- } else {
- {
- bb_swing = 0;
- swing_table = ofdm_swing_table;
- swing_table_size = OFDM_TABLE_SIZE;
- }
- }
-
- for (i = 0; i < swing_table_size; ++i) {
- u32 table_value = swing_table[i];
-
- if (table_value >= 0x100000)
- table_value >>= 22;
- if (bb_swing == table_value)
- break;
- }
- return i;
-}
-
-void odm_txpowertracking_thermal_meter_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 default_swing_index = get_swing_index(dm);
- u8 p = 0;
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
-
- cali_info->is_txpowertracking = true;
- cali_info->tx_powercount = 0;
- cali_info->is_txpowertracking_init = false;
-
- if (!dm->mp_mode)
- cali_info->txpowertrack_control = true;
- else
- cali_info->txpowertrack_control = false;
-
- if (!dm->mp_mode)
- cali_info->txpowertrack_control = true;
-
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "dm txpowertrack_control = %d\n",
- cali_info->txpowertrack_control);
-
- /* dm->rf_calibrate_info.txpowertrack_control = true; */
- cali_info->thermal_value = rtlefu->eeprom_thermalmeter;
- cali_info->thermal_value_iqk = rtlefu->eeprom_thermalmeter;
- cali_info->thermal_value_lck = rtlefu->eeprom_thermalmeter;
-
- if (!cali_info->default_bb_swing_index_flag) {
- /*The index of "0 dB" in SwingTable.*/
- if (dm->support_ic_type == ODM_RTL8188E ||
- dm->support_ic_type == ODM_RTL8723B ||
- dm->support_ic_type == ODM_RTL8192E ||
- dm->support_ic_type == ODM_RTL8703B) {
- cali_info->default_ofdm_index =
- (default_swing_index >= OFDM_TABLE_SIZE) ?
- 30 :
- default_swing_index;
- cali_info->default_cck_index = 20;
- } else if (dm->support_ic_type ==
- ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
- cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
- cali_info->default_cck_index = 20; /*CCK:-6dB*/
- } else if (dm->support_ic_type ==
- ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
- cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
- cali_info->default_cck_index = 28; /*CCK: -6dB*/
- } else if (dm->support_ic_type ==
- ODM_RTL8710B) { /* JJ ADD 20161014 */
- cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
- cali_info->default_cck_index = 28; /*CCK: -6dB*/
- } else {
- cali_info->default_ofdm_index =
- (default_swing_index >= TXSCALE_TABLE_SIZE) ?
- 24 :
- default_swing_index;
- cali_info->default_cck_index = 24;
- }
- cali_info->default_bb_swing_index_flag = true;
- }
-
- cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
- cali_info->CCK_index = cali_info->default_cck_index;
-
- for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
- cali_info->bb_swing_idx_ofdm_base[p] =
- cali_info->default_ofdm_index;
- cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
- cali_info->delta_power_index[p] = 0;
- cali_info->delta_power_index_last[p] = 0;
- cali_info->power_index_offset[p] = 0;
- }
- cali_info->modify_tx_agc_value_ofdm = 0;
- cali_info->modify_tx_agc_value_cck = 0;
-}
-
-void odm_txpowertracking_check(void *dm_void)
-{
- /* 2011/09/29 MH In HW integration first stage, we provide 4 different
- * handle to operate at the same time.
- * In the stage2/3, we need to prive universal interface and merge all
- * HW dynamic mechanism.
- */
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- switch (dm->support_platform) {
- case ODM_WIN:
- odm_txpowertracking_check_mp(dm);
- break;
-
- case ODM_CE:
- odm_txpowertracking_check_ce(dm);
- break;
-
- case ODM_AP:
- odm_txpowertracking_check_ap(dm);
- break;
-
- default:
- break;
- }
-}
-
-void odm_txpowertracking_check_ce(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- void *adapter = dm->adapter;
-
- if (!(dm->support_ability & ODM_RF_TX_PWR_TRACK))
- return;
-
- if (!dm->rf_calibrate_info.tm_trigger) {
- if (IS_HARDWARE_TYPE_8188E(adapter) ||
- IS_HARDWARE_TYPE_8188F(adapter) ||
- IS_HARDWARE_TYPE_8192E(adapter) ||
- IS_HARDWARE_TYPE_8723B(adapter) ||
- IS_HARDWARE_TYPE_JAGUAR(adapter) ||
- IS_HARDWARE_TYPE_8814A(adapter) ||
- IS_HARDWARE_TYPE_8703B(adapter) ||
- IS_HARDWARE_TYPE_8723D(adapter) ||
- IS_HARDWARE_TYPE_8822B(adapter) ||
- IS_HARDWARE_TYPE_8821C(adapter) ||
- (dm->support_ic_type == ODM_RTL8710B)) /* JJ ADD 20161014 */
- odm_set_rf_reg(dm, ODM_RF_PATH_A, RF_T_METER_NEW,
- (BIT(17) | BIT(16)), 0x03);
- else
- odm_set_rf_reg(dm, ODM_RF_PATH_A, RF_T_METER_OLD,
- RFREGOFFSETMASK, 0x60);
-
- dm->rf_calibrate_info.tm_trigger = 1;
- return;
- }
-
- odm_txpowertracking_callback_thermal_meter(dm);
- dm->rf_calibrate_info.tm_trigger = 0;
-}
-
-void odm_txpowertracking_check_mp(void *dm_void) {}
-
-void odm_txpowertracking_check_ap(void *dm_void) {}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMPOWERTRACKING_H__
-#define __PHYDMPOWERTRACKING_H__
-
-#define POWRTRACKING_VERSION "1.1"
-
-#define DPK_DELTA_MAPPING_NUM 13
-#define index_mapping_HP_NUM 15
-#define OFDM_TABLE_SIZE 43
-#define CCK_TABLE_SIZE 33
-#define CCK_TABLE_SIZE_88F 21
-#define TXSCALE_TABLE_SIZE 37
-#define CCK_TABLE_SIZE_8723D 41
-/* JJ ADD 20161014 */
-#define CCK_TABLE_SIZE_8710B 41
-
-#define TXPWR_TRACK_TABLE_SIZE 30
-#define DELTA_SWINGIDX_SIZE 30
-#define DELTA_SWINTSSI_SIZE 61
-#define BAND_NUM 4
-
-#define AVG_THERMAL_NUM 8
-#define HP_THERMAL_NUM 8
-#define IQK_MAC_REG_NUM 4
-#define IQK_ADDA_REG_NUM 16
-#define IQK_BB_REG_NUM_MAX 10
-
-#define IQK_BB_REG_NUM 9
-
-#define iqk_matrix_reg_num 8
-
-extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
-extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
-extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
-
-extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
-extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
-extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
-extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
-extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
-extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
-extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
-/* JJ ADD 20161014 */
-extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
-
-extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
-
-/* <20121018, Kordan> In case fail to read TxPowerTrack.txt,
- * we use the table of 88E as the default table.
- */
-
-#define dm_check_txpowertracking odm_txpowertracking_check
-
-struct iqk_matrix_regs_setting {
- bool is_iqk_done;
- s32 value[3][iqk_matrix_reg_num];
- bool is_bw_iqk_result_saved[3];
-};
-
-struct dm_rf_calibration_struct {
- /* for tx power tracking */
-
- u32 rega24; /* for TempCCK */
- s32 rege94;
- s32 rege9c;
- s32 regeb4;
- s32 regebc;
-
- u8 tx_powercount;
- bool is_txpowertracking_init;
- bool is_txpowertracking;
- /* for mp mode, turn off txpwrtracking as default */
- u8 txpowertrack_control;
- u8 tm_trigger;
- u8 internal_pa_5g[2]; /* pathA / pathB */
-
- u8 thermal_meter
- [2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
- u8 thermal_value;
- u8 thermal_value_lck;
- u8 thermal_value_iqk;
- s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
- u8 thermal_value_dpk;
- u8 thermal_value_avg[AVG_THERMAL_NUM];
- u8 thermal_value_avg_index;
- u8 thermal_value_rx_gain;
- u8 thermal_value_crystal;
- u8 thermal_value_dpk_store;
- u8 thermal_value_dpk_track;
- bool txpowertracking_in_progress;
-
- bool is_reloadtxpowerindex;
- u8 is_rf_pi_enable;
- u32 txpowertracking_callback_cnt; /* cosa add for debug */
-
- /* ---------------------- Tx power Tracking ------------------------- */
- u8 is_cck_in_ch14;
- u8 CCK_index;
- u8 OFDM_index[MAX_RF_PATH];
- s8 power_index_offset[MAX_RF_PATH];
- s8 delta_power_index[MAX_RF_PATH];
- s8 delta_power_index_last[MAX_RF_PATH];
- bool is_tx_power_changed;
- s8 xtal_offset;
- s8 xtal_offset_last;
-
- u8 thermal_value_hp[HP_THERMAL_NUM];
- u8 thermal_value_hp_index;
- struct iqk_matrix_regs_setting
- iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
- u8 delta_lck;
- s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
- u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
- u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
- u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
- s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
- s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
- u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
-
- u8 bb_swing_idx_ofdm[MAX_RF_PATH];
- u8 bb_swing_idx_ofdm_current;
- u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
- bool default_bb_swing_index_flag;
- bool bb_swing_flag_ofdm;
- u8 bb_swing_idx_cck;
- u8 bb_swing_idx_cck_current;
- u8 bb_swing_idx_cck_base;
- u8 default_ofdm_index;
- u8 default_cck_index;
- bool bb_swing_flag_cck;
-
- s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
- s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
- s8 absolute_cck_swing_idx[MAX_RF_PATH];
- s8 remnant_cck_swing_idx;
- s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
- bool modify_tx_agc_flag_path_a;
- bool modify_tx_agc_flag_path_b;
- bool modify_tx_agc_flag_path_c;
- bool modify_tx_agc_flag_path_d;
- bool modify_tx_agc_flag_path_a_cck;
-
- s8 kfree_offset[MAX_RF_PATH];
-
- /* ------------------------------------------------------------------ */
-
- /* for IQK */
- u32 regc04;
- u32 reg874;
- u32 regc08;
- u32 regb68;
- u32 regb6c;
- u32 reg870;
- u32 reg860;
- u32 reg864;
-
- bool is_iqk_initialized;
- bool is_lck_in_progress;
- bool is_antenna_detected;
- bool is_need_iqk;
- bool is_iqk_in_progress;
- bool is_iqk_pa_off;
- u8 delta_iqk;
- u32 ADDA_backup[IQK_ADDA_REG_NUM];
- u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
- u32 IQK_BB_backup_recover[9];
- /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
- u32 IQK_BB_backup[IQK_BB_REG_NUM];
- u32 tx_iqc_8723b[2][3][2];
- /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
- u32 rx_iqc_8723b[2][2][2];
- /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
- u32 tx_iqc_8703b[3][2];
- /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
- u32 rx_iqc_8703b[2][2];
- /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
- u32 tx_iqc_8723d[2][3][2];
- /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
- u32 rx_iqc_8723d[2][2][2];
- /* JJ ADD 20161014 */
- /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
- u32 tx_iqc_8710b[2][3][2];
- /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
- u32 rx_iqc_8710b[2][2][2];
-
- u8 iqk_step;
- u8 kcount;
- u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
- bool is_mp_mode;
-
- /* <James> IQK time measurement */
- u64 iqk_start_time;
- u64 iqk_progressing_time;
- u64 iqk_total_progressing_time;
-
- u32 lok_result;
-
- /* for APK */
- u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
- u8 is_ap_kdone;
- u8 is_apk_thermal_meter_ignore;
-
- /* DPK */
- bool is_dpk_fail;
- u8 is_dp_done;
- u8 is_dp_path_aok;
- u8 is_dp_path_bok;
-
- u32 tx_lok[2];
- u32 dpk_tx_agc;
- s32 dpk_gain;
- u32 dpk_thermal[4];
- s8 modify_tx_agc_value_ofdm;
- s8 modify_tx_agc_value_cck;
-
- /*Add by Yuchen for Kfree Phydm*/
- u8 reg_rf_kfree_enable; /*for registry*/
- u8 rf_kfree_enable; /*for efuse enable check*/
-};
-
-void odm_txpowertracking_check(void *dm_void);
-
-void odm_txpowertracking_init(void *dm_void);
-
-void odm_txpowertracking_check_ap(void *dm_void);
-
-void odm_txpowertracking_thermal_meter_init(void *dm_void);
-
-void odm_txpowertracking_init(void *dm_void);
-
-void odm_txpowertracking_check_mp(void *dm_void);
-
-void odm_txpowertracking_check_ce(void *dm_void);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMPREDEFINE_H__
-#define __PHYDMPREDEFINE_H__
-
-/* 1 ============================================================
- * 1 Definition
- * 1 ============================================================
- */
-
-#define PHYDM_CODE_BASE "PHYDM_TRUNK"
-#define PHYDM_RELEASE_DATE "00000000"
-
-/* Max path of IC */
-#define MAX_PATH_NUM_8188E 1
-#define MAX_PATH_NUM_8192E 2
-#define MAX_PATH_NUM_8723B 1
-#define MAX_PATH_NUM_8812A 2
-#define MAX_PATH_NUM_8821A 1
-#define MAX_PATH_NUM_8814A 4
-#define MAX_PATH_NUM_8822B 2
-#define MAX_PATH_NUM_8821B 2
-#define MAX_PATH_NUM_8703B 1
-#define MAX_PATH_NUM_8188F 1
-#define MAX_PATH_NUM_8723D 1
-#define MAX_PATH_NUM_8197F 2
-#define MAX_PATH_NUM_8821C 1
-/* JJ ADD 20161014 */
-#define MAX_PATH_NUM_8710B 1
-
-/* Max RF path */
-#define ODM_RF_PATH_MAX 2
-#define ODM_RF_PATH_MAX_JAGUAR 4
-
-/*Bit define path*/
-#define PHYDM_A BIT(0)
-#define PHYDM_B BIT(1)
-#define PHYDM_C BIT(2)
-#define PHYDM_D BIT(3)
-#define PHYDM_AB (BIT(0) | BIT(1))
-#define PHYDM_AC (BIT(0) | BIT(2))
-#define PHYDM_AD (BIT(0) | BIT(3))
-#define PHYDM_BC (BIT(1) | BIT(2))
-#define PHYDM_BD (BIT(1) | BIT(3))
-#define PHYDM_CD (BIT(2) | BIT(3))
-#define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2))
-#define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3))
-#define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3))
-#define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3))
-#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-
-/* number of entry */
-/* defined in wifi.h (32+1) */
-#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
-
-#define RX_SMOOTH_FACTOR 20
-
-/* -----MGN rate--------------------------------- */
-
-enum ODM_MGN_RATE {
- ODM_MGN_1M = 0x02,
- ODM_MGN_2M = 0x04,
- ODM_MGN_5_5M = 0x0B,
- ODM_MGN_6M = 0x0C,
- ODM_MGN_9M = 0x12,
- ODM_MGN_11M = 0x16,
- ODM_MGN_12M = 0x18,
- ODM_MGN_18M = 0x24,
- ODM_MGN_24M = 0x30,
- ODM_MGN_36M = 0x48,
- ODM_MGN_48M = 0x60,
- ODM_MGN_54M = 0x6C,
- ODM_MGN_MCS32 = 0x7F,
- ODM_MGN_MCS0,
- ODM_MGN_MCS1,
- ODM_MGN_MCS2,
- ODM_MGN_MCS3,
- ODM_MGN_MCS4,
- ODM_MGN_MCS5,
- ODM_MGN_MCS6,
- ODM_MGN_MCS7,
- ODM_MGN_MCS8,
- ODM_MGN_MCS9,
- ODM_MGN_MCS10,
- ODM_MGN_MCS11,
- ODM_MGN_MCS12,
- ODM_MGN_MCS13,
- ODM_MGN_MCS14,
- ODM_MGN_MCS15,
- ODM_MGN_MCS16,
- ODM_MGN_MCS17,
- ODM_MGN_MCS18,
- ODM_MGN_MCS19,
- ODM_MGN_MCS20,
- ODM_MGN_MCS21,
- ODM_MGN_MCS22,
- ODM_MGN_MCS23,
- ODM_MGN_MCS24,
- ODM_MGN_MCS25,
- ODM_MGN_MCS26,
- ODM_MGN_MCS27,
- ODM_MGN_MCS28,
- ODM_MGN_MCS29,
- ODM_MGN_MCS30,
- ODM_MGN_MCS31,
- ODM_MGN_VHT1SS_MCS0,
- ODM_MGN_VHT1SS_MCS1,
- ODM_MGN_VHT1SS_MCS2,
- ODM_MGN_VHT1SS_MCS3,
- ODM_MGN_VHT1SS_MCS4,
- ODM_MGN_VHT1SS_MCS5,
- ODM_MGN_VHT1SS_MCS6,
- ODM_MGN_VHT1SS_MCS7,
- ODM_MGN_VHT1SS_MCS8,
- ODM_MGN_VHT1SS_MCS9,
- ODM_MGN_VHT2SS_MCS0,
- ODM_MGN_VHT2SS_MCS1,
- ODM_MGN_VHT2SS_MCS2,
- ODM_MGN_VHT2SS_MCS3,
- ODM_MGN_VHT2SS_MCS4,
- ODM_MGN_VHT2SS_MCS5,
- ODM_MGN_VHT2SS_MCS6,
- ODM_MGN_VHT2SS_MCS7,
- ODM_MGN_VHT2SS_MCS8,
- ODM_MGN_VHT2SS_MCS9,
- ODM_MGN_VHT3SS_MCS0,
- ODM_MGN_VHT3SS_MCS1,
- ODM_MGN_VHT3SS_MCS2,
- ODM_MGN_VHT3SS_MCS3,
- ODM_MGN_VHT3SS_MCS4,
- ODM_MGN_VHT3SS_MCS5,
- ODM_MGN_VHT3SS_MCS6,
- ODM_MGN_VHT3SS_MCS7,
- ODM_MGN_VHT3SS_MCS8,
- ODM_MGN_VHT3SS_MCS9,
- ODM_MGN_VHT4SS_MCS0,
- ODM_MGN_VHT4SS_MCS1,
- ODM_MGN_VHT4SS_MCS2,
- ODM_MGN_VHT4SS_MCS3,
- ODM_MGN_VHT4SS_MCS4,
- ODM_MGN_VHT4SS_MCS5,
- ODM_MGN_VHT4SS_MCS6,
- ODM_MGN_VHT4SS_MCS7,
- ODM_MGN_VHT4SS_MCS8,
- ODM_MGN_VHT4SS_MCS9,
- ODM_MGN_UNKNOWN
-};
-
-#define ODM_MGN_MCS0_SG 0xc0
-#define ODM_MGN_MCS1_SG 0xc1
-#define ODM_MGN_MCS2_SG 0xc2
-#define ODM_MGN_MCS3_SG 0xc3
-#define ODM_MGN_MCS4_SG 0xc4
-#define ODM_MGN_MCS5_SG 0xc5
-#define ODM_MGN_MCS6_SG 0xc6
-#define ODM_MGN_MCS7_SG 0xc7
-#define ODM_MGN_MCS8_SG 0xc8
-#define ODM_MGN_MCS9_SG 0xc9
-#define ODM_MGN_MCS10_SG 0xca
-#define ODM_MGN_MCS11_SG 0xcb
-#define ODM_MGN_MCS12_SG 0xcc
-#define ODM_MGN_MCS13_SG 0xcd
-#define ODM_MGN_MCS14_SG 0xce
-#define ODM_MGN_MCS15_SG 0xcf
-
-/* -----DESC rate--------------------------------- */
-
-#define ODM_RATEMCS15_SG 0x1c
-#define ODM_RATEMCS32 0x20
-
-/* CCK Rates, TxHT = 0 */
-#define ODM_RATE1M 0x00
-#define ODM_RATE2M 0x01
-#define ODM_RATE5_5M 0x02
-#define ODM_RATE11M 0x03
-/* OFDM Rates, TxHT = 0 */
-#define ODM_RATE6M 0x04
-#define ODM_RATE9M 0x05
-#define ODM_RATE12M 0x06
-#define ODM_RATE18M 0x07
-#define ODM_RATE24M 0x08
-#define ODM_RATE36M 0x09
-#define ODM_RATE48M 0x0A
-#define ODM_RATE54M 0x0B
-/* MCS Rates, TxHT = 1 */
-#define ODM_RATEMCS0 0x0C
-#define ODM_RATEMCS1 0x0D
-#define ODM_RATEMCS2 0x0E
-#define ODM_RATEMCS3 0x0F
-#define ODM_RATEMCS4 0x10
-#define ODM_RATEMCS5 0x11
-#define ODM_RATEMCS6 0x12
-#define ODM_RATEMCS7 0x13
-#define ODM_RATEMCS8 0x14
-#define ODM_RATEMCS9 0x15
-#define ODM_RATEMCS10 0x16
-#define ODM_RATEMCS11 0x17
-#define ODM_RATEMCS12 0x18
-#define ODM_RATEMCS13 0x19
-#define ODM_RATEMCS14 0x1A
-#define ODM_RATEMCS15 0x1B
-#define ODM_RATEMCS16 0x1C
-#define ODM_RATEMCS17 0x1D
-#define ODM_RATEMCS18 0x1E
-#define ODM_RATEMCS19 0x1F
-#define ODM_RATEMCS20 0x20
-#define ODM_RATEMCS21 0x21
-#define ODM_RATEMCS22 0x22
-#define ODM_RATEMCS23 0x23
-#define ODM_RATEMCS24 0x24
-#define ODM_RATEMCS25 0x25
-#define ODM_RATEMCS26 0x26
-#define ODM_RATEMCS27 0x27
-#define ODM_RATEMCS28 0x28
-#define ODM_RATEMCS29 0x29
-#define ODM_RATEMCS30 0x2A
-#define ODM_RATEMCS31 0x2B
-#define ODM_RATEVHTSS1MCS0 0x2C
-#define ODM_RATEVHTSS1MCS1 0x2D
-#define ODM_RATEVHTSS1MCS2 0x2E
-#define ODM_RATEVHTSS1MCS3 0x2F
-#define ODM_RATEVHTSS1MCS4 0x30
-#define ODM_RATEVHTSS1MCS5 0x31
-#define ODM_RATEVHTSS1MCS6 0x32
-#define ODM_RATEVHTSS1MCS7 0x33
-#define ODM_RATEVHTSS1MCS8 0x34
-#define ODM_RATEVHTSS1MCS9 0x35
-#define ODM_RATEVHTSS2MCS0 0x36
-#define ODM_RATEVHTSS2MCS1 0x37
-#define ODM_RATEVHTSS2MCS2 0x38
-#define ODM_RATEVHTSS2MCS3 0x39
-#define ODM_RATEVHTSS2MCS4 0x3A
-#define ODM_RATEVHTSS2MCS5 0x3B
-#define ODM_RATEVHTSS2MCS6 0x3C
-#define ODM_RATEVHTSS2MCS7 0x3D
-#define ODM_RATEVHTSS2MCS8 0x3E
-#define ODM_RATEVHTSS2MCS9 0x3F
-#define ODM_RATEVHTSS3MCS0 0x40
-#define ODM_RATEVHTSS3MCS1 0x41
-#define ODM_RATEVHTSS3MCS2 0x42
-#define ODM_RATEVHTSS3MCS3 0x43
-#define ODM_RATEVHTSS3MCS4 0x44
-#define ODM_RATEVHTSS3MCS5 0x45
-#define ODM_RATEVHTSS3MCS6 0x46
-#define ODM_RATEVHTSS3MCS7 0x47
-#define ODM_RATEVHTSS3MCS8 0x48
-#define ODM_RATEVHTSS3MCS9 0x49
-#define ODM_RATEVHTSS4MCS0 0x4A
-#define ODM_RATEVHTSS4MCS1 0x4B
-#define ODM_RATEVHTSS4MCS2 0x4C
-#define ODM_RATEVHTSS4MCS3 0x4D
-#define ODM_RATEVHTSS4MCS4 0x4E
-#define ODM_RATEVHTSS4MCS5 0x4F
-#define ODM_RATEVHTSS4MCS6 0x50
-#define ODM_RATEVHTSS4MCS7 0x51
-#define ODM_RATEVHTSS4MCS8 0x52
-#define ODM_RATEVHTSS4MCS9 0x53
-
-#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
-
-/* 1 ============================================================
- * 1 enumeration
- * 1 ============================================================
- */
-
-/* ODM_CMNINFO_INTERFACE */
-enum odm_interface {
- ODM_ITRF_PCIE = 0x1,
- ODM_ITRF_USB = 0x2,
- ODM_ITRF_SDIO = 0x4,
- ODM_ITRF_ALL = 0x7,
-};
-
-/* ODM_CMNINFO_IC_TYPE */
-enum odm_ic_type {
- ODM_RTL8188E = BIT(0),
- ODM_RTL8812 = BIT(1),
- ODM_RTL8821 = BIT(2),
- ODM_RTL8192E = BIT(3),
- ODM_RTL8723B = BIT(4),
- ODM_RTL8814A = BIT(5),
- ODM_RTL8881A = BIT(6),
- ODM_RTL8822B = BIT(7),
- ODM_RTL8703B = BIT(8),
- ODM_RTL8195A = BIT(9),
- ODM_RTL8188F = BIT(10),
- ODM_RTL8723D = BIT(11),
- ODM_RTL8197F = BIT(12),
- ODM_RTL8821C = BIT(13),
- ODM_RTL8814B = BIT(14),
- ODM_RTL8198F = BIT(15),
- /* JJ ADD 20161014 */
- ODM_RTL8710B = BIT(16),
-};
-
-/* JJ ADD 20161014 */
-#define ODM_IC_1SS \
- (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | \
- ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | \
- ODM_RTL8195A | ODM_RTL8710B)
-#define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B)
-#define ODM_IC_3SS (ODM_RTL8814A)
-#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F)
-
-/* JJ ADD 20161014 */
-#define ODM_IC_11N_SERIES \
- (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | \
- ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B)
-#define ODM_IC_11AC_SERIES \
- (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | \
- ODM_RTL8822B | ODM_RTL8821C)
-#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
-#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
-#define ODM_IC_TXBF_SUPPORT \
- (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | \
- ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
-#define ODM_IC_11N_GAIN_IDX_EDCCA \
- (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | \
- ODM_RTL8197F | ODM_RTL8710B)
-#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
-#define ODM_IC_PHY_STATUE_NEW_TYPE \
- (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | \
- ODM_RTL8710B)
-
-#define PHYDM_IC_8051_SERIES \
- (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E | \
- ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F)
-#define PHYDM_IC_3081_SERIES \
- (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
-
-#define PHYDM_IC_SUPPORT_LA_MODE \
- (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
-
-/* JJ ADD 20161014 */
-
-/* ODM_CMNINFO_CUT_VER */
-enum odm_cut_version {
- ODM_CUT_A = 0,
- ODM_CUT_B = 1,
- ODM_CUT_C = 2,
- ODM_CUT_D = 3,
- ODM_CUT_E = 4,
- ODM_CUT_F = 5,
-
- ODM_CUT_I = 8,
- ODM_CUT_J = 9,
- ODM_CUT_K = 10,
- ODM_CUT_TEST = 15,
-};
-
-/* ODM_CMNINFO_FAB_VER */
-enum odm_fab {
- ODM_TSMC = 0,
- ODM_UMC = 1,
-};
-
-/* ODM_CMNINFO_RF_TYPE
- *
- * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5))
- */
-enum odm_rf_path {
- ODM_RF_A = BIT(0),
- ODM_RF_B = BIT(1),
- ODM_RF_C = BIT(2),
- ODM_RF_D = BIT(3),
-};
-
-enum odm_rf_tx_num {
- ODM_1T = 1,
- ODM_2T = 2,
- ODM_3T = 3,
- ODM_4T = 4,
-};
-
-enum odm_rf_type {
- ODM_1T1R,
- ODM_1T2R,
- ODM_2T2R,
- ODM_2T2R_GREEN,
- ODM_2T3R,
- ODM_2T4R,
- ODM_3T3R,
- ODM_3T4R,
- ODM_4T4R,
- ODM_XTXR
-};
-
-enum odm_mac_phy_mode {
- ODM_SMSP = 0,
- ODM_DMSP = 1,
- ODM_DMDP = 2,
-};
-
-enum odm_bt_coexist {
- ODM_BT_BUSY = 1,
- ODM_BT_ON = 2,
- ODM_BT_OFF = 3,
- ODM_BT_NONE = 4,
-};
-
-/* ODM_CMNINFO_OP_MODE */
-enum odm_operation_mode {
- ODM_NO_LINK = BIT(0),
- ODM_LINK = BIT(1),
- ODM_SCAN = BIT(2),
- ODM_POWERSAVE = BIT(3),
- ODM_AP_MODE = BIT(4),
- ODM_CLIENT_MODE = BIT(5),
- ODM_AD_HOC = BIT(6),
- ODM_WIFI_DIRECT = BIT(7),
- ODM_WIFI_DISPLAY = BIT(8),
-};
-
-/* ODM_CMNINFO_WM_MODE */
-enum odm_wireless_mode {
- ODM_WM_UNKNOWN = 0x0,
- ODM_WM_B = BIT(0),
- ODM_WM_G = BIT(1),
- ODM_WM_A = BIT(2),
- ODM_WM_N24G = BIT(3),
- ODM_WM_N5G = BIT(4),
- ODM_WM_AUTO = BIT(5),
- ODM_WM_AC = BIT(6),
-};
-
-/* ODM_CMNINFO_BAND */
-enum odm_band_type {
- ODM_BAND_2_4G = 0,
- ODM_BAND_5G,
- ODM_BAND_ON_BOTH,
- ODM_BANDMAX
-};
-
-/* ODM_CMNINFO_SEC_CHNL_OFFSET */
-enum phydm_sec_chnl_offset {
- PHYDM_DONT_CARE = 0,
- PHYDM_BELOW = 1,
- PHYDM_ABOVE = 2
-};
-
-/* ODM_CMNINFO_SEC_MODE */
-enum odm_security {
- ODM_SEC_OPEN = 0,
- ODM_SEC_WEP40 = 1,
- ODM_SEC_TKIP = 2,
- ODM_SEC_RESERVE = 3,
- ODM_SEC_AESCCMP = 4,
- ODM_SEC_WEP104 = 5,
- ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
- ODM_SEC_SMS4 = 7,
-};
-
-/* ODM_CMNINFO_BW */
-enum odm_bw {
- ODM_BW20M = 0,
- ODM_BW40M = 1,
- ODM_BW80M = 2,
- ODM_BW160M = 3,
- ODM_BW5M = 4,
- ODM_BW10M = 5,
- ODM_BW_MAX = 6
-};
-
-/* ODM_CMNINFO_CHNL */
-
-/* ODM_CMNINFO_BOARD_TYPE */
-enum odm_board_type {
- ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
- ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */
- ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
- ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
- ODM_BOARD_EXT_PA =
- BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */
- ODM_BOARD_EXT_LNA =
- BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
- ODM_BOARD_EXT_TRSW =
- BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */
- ODM_BOARD_EXT_PA_5G =
- BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */
- ODM_BOARD_EXT_LNA_5G =
- BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
-};
-
-enum odm_package_type {
- ODM_PACKAGE_DEFAULT = 0,
- ODM_PACKAGE_QFN68 = BIT(0),
- ODM_PACKAGE_TFBGA90 = BIT(1),
- ODM_PACKAGE_TFBGA79 = BIT(2),
-};
-
-enum odm_type_gpa {
- TYPE_GPA0 = 0x0000,
- TYPE_GPA1 = 0x0055,
- TYPE_GPA2 = 0x00AA,
- TYPE_GPA3 = 0x00FF,
- TYPE_GPA4 = 0x5500,
- TYPE_GPA5 = 0x5555,
- TYPE_GPA6 = 0x55AA,
- TYPE_GPA7 = 0x55FF,
- TYPE_GPA8 = 0xAA00,
- TYPE_GPA9 = 0xAA55,
- TYPE_GPA10 = 0xAAAA,
- TYPE_GPA11 = 0xAAFF,
- TYPE_GPA12 = 0xFF00,
- TYPE_GPA13 = 0xFF55,
- TYPE_GPA14 = 0xFFAA,
- TYPE_GPA15 = 0xFFFF,
-};
-
-enum odm_type_apa {
- TYPE_APA0 = 0x0000,
- TYPE_APA1 = 0x0055,
- TYPE_APA2 = 0x00AA,
- TYPE_APA3 = 0x00FF,
- TYPE_APA4 = 0x5500,
- TYPE_APA5 = 0x5555,
- TYPE_APA6 = 0x55AA,
- TYPE_APA7 = 0x55FF,
- TYPE_APA8 = 0xAA00,
- TYPE_APA9 = 0xAA55,
- TYPE_APA10 = 0xAAAA,
- TYPE_APA11 = 0xAAFF,
- TYPE_APA12 = 0xFF00,
- TYPE_APA13 = 0xFF55,
- TYPE_APA14 = 0xFFAA,
- TYPE_APA15 = 0xFFFF,
-};
-
-enum odm_type_glna {
- TYPE_GLNA0 = 0x0000,
- TYPE_GLNA1 = 0x0055,
- TYPE_GLNA2 = 0x00AA,
- TYPE_GLNA3 = 0x00FF,
- TYPE_GLNA4 = 0x5500,
- TYPE_GLNA5 = 0x5555,
- TYPE_GLNA6 = 0x55AA,
- TYPE_GLNA7 = 0x55FF,
- TYPE_GLNA8 = 0xAA00,
- TYPE_GLNA9 = 0xAA55,
- TYPE_GLNA10 = 0xAAAA,
- TYPE_GLNA11 = 0xAAFF,
- TYPE_GLNA12 = 0xFF00,
- TYPE_GLNA13 = 0xFF55,
- TYPE_GLNA14 = 0xFFAA,
- TYPE_GLNA15 = 0xFFFF,
-};
-
-enum odm_type_alna {
- TYPE_ALNA0 = 0x0000,
- TYPE_ALNA1 = 0x0055,
- TYPE_ALNA2 = 0x00AA,
- TYPE_ALNA3 = 0x00FF,
- TYPE_ALNA4 = 0x5500,
- TYPE_ALNA5 = 0x5555,
- TYPE_ALNA6 = 0x55AA,
- TYPE_ALNA7 = 0x55FF,
- TYPE_ALNA8 = 0xAA00,
- TYPE_ALNA9 = 0xAA55,
- TYPE_ALNA10 = 0xAAAA,
- TYPE_ALNA11 = 0xAAFF,
- TYPE_ALNA12 = 0xFF00,
- TYPE_ALNA13 = 0xFF55,
- TYPE_ALNA14 = 0xFFAA,
- TYPE_ALNA15 = 0xFFFF,
-};
-
-enum odm_rf_radio_path {
- ODM_RF_PATH_A = 0, /* Radio path A */
- ODM_RF_PATH_B = 1, /* Radio path B */
- ODM_RF_PATH_C = 2, /* Radio path C */
- ODM_RF_PATH_D = 3, /* Radio path D */
- ODM_RF_PATH_AB,
- ODM_RF_PATH_AC,
- ODM_RF_PATH_AD,
- ODM_RF_PATH_BC,
- ODM_RF_PATH_BD,
- ODM_RF_PATH_CD,
- ODM_RF_PATH_ABC,
- ODM_RF_PATH_ACD,
- ODM_RF_PATH_BCD,
- ODM_RF_PATH_ABCD,
- /* ODM_RF_PATH_MAX, */ /* Max RF number 90 support */
-};
-
-enum odm_parameter_init {
- ODM_PRE_SETTING = 0,
- ODM_POST_SETTING = 1,
-};
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __ODM_PRECOMP_H__
-#define __ODM_PRECOMP_H__
-
-#include "phydm_types.h"
-
-/* 2 Config Flags and Structs - defined by each ODM type */
-
-#include "../wifi.h"
-#include "rtl_phydm.h"
-
-/* 2 OutSrc Header Files */
-
-#include "phydm.h"
-#include "phydm_hwconfig.h"
-#include "phydm_debug.h"
-#include "phydm_regdefine11ac.h"
-#include "phydm_regdefine11n.h"
-#include "phydm_interface.h"
-#include "phydm_reg.h"
-
-#include "phydm_adc_sampling.h"
-
-/* JJ ADD 20161014 */
-
-#include "../halmac/halmac_reg2.h"
-
-#define LDPC_HT_ENABLE_RX BIT(0)
-#define LDPC_HT_ENABLE_TX BIT(1)
-#define LDPC_HT_TEST_TX_ENABLE BIT(2)
-#define LDPC_HT_CAP_TX BIT(3)
-
-#define STBC_HT_ENABLE_RX BIT(0)
-#define STBC_HT_ENABLE_TX BIT(1)
-#define STBC_HT_TEST_TX_ENABLE BIT(2)
-#define STBC_HT_CAP_TX BIT(3)
-
-#define LDPC_VHT_ENABLE_RX BIT(0)
-#define LDPC_VHT_ENABLE_TX BIT(1)
-#define LDPC_VHT_TEST_TX_ENABLE BIT(2)
-#define LDPC_VHT_CAP_TX BIT(3)
-
-#define STBC_VHT_ENABLE_RX BIT(0)
-#define STBC_VHT_ENABLE_TX BIT(1)
-#define STBC_VHT_TEST_TX_ENABLE BIT(2)
-#define STBC_VHT_CAP_TX BIT(3)
-
-#include "rtl8822b/halhwimg8822b_mac.h"
-#include "rtl8822b/halhwimg8822b_rf.h"
-#include "rtl8822b/halhwimg8822b_bb.h"
-#include "rtl8822b/phydm_regconfig8822b.h"
-#include "rtl8822b/halphyrf_8822b.h"
-#include "rtl8822b/phydm_rtl8822b.h"
-#include "rtl8822b/phydm_hal_api8822b.h"
-#include "rtl8822b/version_rtl8822b.h"
-
-#include "../halmac/halmac_reg_8822b.h"
-
-/* JJ ADD 20161014 */
-
-#endif /* __ODM_PRECOMP_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/*============================================================
- * include files
- *============================================================
- */
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct psd_info *dm_psd_table = &dm->dm_psd_table;
- u32 psd_report = 0;
-
- odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
-
- odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22),
- 1); /*PSD trigger start*/
- ODM_delay_us(10);
- odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22),
- 0); /*PSD trigger stop*/
-
- psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, 0xffff);
- psd_report = odm_convert_to_db(psd_report) + igi;
-
- return psd_report;
-}
-
-static u8 phydm_psd_stop_trx(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u32 i;
- u8 trx_idle_success = false;
- u32 dbg_port_value = 0;
-
- /*[Stop TRX]----------------------------------------------------------*/
- if (!phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3,
- 0x0)) /*set debug port to 0x0*/
- return STOP_TRX_FAIL;
-
- for (i = 0; i < 10000; i++) {
- dbg_port_value = phydm_get_bb_dbg_port_value(dm);
- if ((dbg_port_value & (BIT(17) | BIT(3))) ==
- 0) /* PHYTXON && CCA_all */ {
- ODM_RT_TRACE(dm, ODM_COMP_API,
- "PSD wait for ((%d)) times\n", i);
-
- trx_idle_success = true;
- break;
- }
- }
-
- if (trx_idle_success) {
- /*pause all TX queue*/
- odm_set_bb_reg(dm, 0x520, 0xff0000, 0xff);
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- /*disable CCK block*/
- odm_set_bb_reg(dm, 0x808, BIT(28), 0);
- /*disable OFDM RX CCA*/
- odm_set_bb_reg(dm, 0x838, BIT(1), 1);
- } else {
- /*TBD*/
- /* disable whole CCK block */
- odm_set_bb_reg(dm, 0x800, BIT(24), 0);
- /*[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA]*/
- odm_set_bb_reg(dm, 0xC14, MASKDWORD, 0x0);
- }
-
- } else {
- return STOP_TRX_FAIL;
- }
-
- phydm_release_bb_dbg_port(dm);
-
- return STOP_TRX_SUCCESS;
-}
-
-static u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
-static u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
-
-void phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct psd_info *dm_psd_table = &dm->dm_psd_table;
- u32 i = 0, mod_tone_idx;
- u32 t = 0;
- u16 fft_max_half_bw;
- u32 psd_igi_a_reg;
- u32 psd_igi_b_reg;
- u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
- u8 ag_rf_mode_reg = 0;
- u8 rf_reg18_9_8 = 0;
- u32 psd_result_tmp = 0;
- u8 psd_result = 0;
- u8 psd_result_cali_tone[7] = {0};
- u8 psd_result_cali_val[7] = {0};
- u8 noise_table_idx = 0;
-
- if (dm->support_ic_type == ODM_RTL8821) {
- odm_move_memory(dm, psd_result_cali_tone,
- psd_result_cali_tone_8821, 7);
- odm_move_memory(dm, psd_result_cali_val,
- psd_result_cali_val_8821, 7);
- }
-
- dm_psd_table->psd_in_progress = 1;
-
- /*[Stop DIG]*/
- dm->support_ability &= ~(ODM_BB_DIG);
- dm->support_ability &= ~(ODM_BB_FA_CNT);
-
- ODM_RT_TRACE(dm, ODM_COMP_API, "PSD Start =>\n");
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- psd_igi_a_reg = 0xc50;
- psd_igi_b_reg = 0xe50;
- } else {
- psd_igi_a_reg = 0xc50;
- psd_igi_b_reg = 0xc58;
- }
-
- /*[back up IGI]*/
- dm_psd_table->initial_gain_backup =
- odm_get_bb_reg(dm, psd_igi_a_reg, 0xff);
- odm_set_bb_reg(dm, psd_igi_a_reg, 0xff,
- 0x6e); /*IGI target at 0dBm & make it can't CCA*/
- odm_set_bb_reg(dm, psd_igi_b_reg, 0xff,
- 0x6e); /*IGI target at 0dBm & make it can't CCA*/
- ODM_delay_us(10);
-
- if (phydm_psd_stop_trx(dm) == STOP_TRX_FAIL) {
- ODM_RT_TRACE(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
- return;
- }
-
- /*[Set IGI]*/
- odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, igi);
- odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, igi);
-
- /*[Backup RF Reg]*/
- dm_psd_table->rf_0x18_bkp =
- odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK);
-
- if (psd_fc_channel > 14) {
- rf_reg18_9_8 = 1;
-
- if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
- ag_rf_mode_reg = 0x1;
- else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
- ag_rf_mode_reg = 0x3;
- else if (psd_fc_channel > 140)
- ag_rf_mode_reg = 0x5;
- }
-
- /* Set RF fc*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xff, psd_fc_channel);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0x300, rf_reg18_9_8);
- /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xc00,
- dm_psd_table->psd_bw_rf_reg);
- /* Set RF ag fc mode*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg);
-
- ODM_RT_TRACE(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
- odm_get_bb_reg(dm, 0xc50, MASKDWORD));
- ODM_RT_TRACE(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
- odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK));
-
- /*[Stop 3-wires]*/
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, 0xc00, 0xf, 0x4); /* hardware 3-wire off */
- odm_set_bb_reg(dm, 0xe00, 0xf, 0x4); /* hardware 3-wire off */
- } else {
- odm_set_bb_reg(dm, 0x88c, 0xf00000,
- 0xf); /* 3 wire Disable 88c[23:20]=0xf */
- }
- ODM_delay_us(10);
-
- if (stop_point > (dm_psd_table->fft_smp_point - 1))
- stop_point = (dm_psd_table->fft_smp_point - 1);
-
- if (start_point > (dm_psd_table->fft_smp_point - 1))
- start_point = (dm_psd_table->fft_smp_point - 1);
-
- if (start_point > stop_point)
- stop_point = start_point;
-
- if (stop_point > 127) /* limit of psd_result[128] */
- stop_point = 127;
-
- for (i = start_point; i <= stop_point; i++) {
- fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
-
- if (i < fft_max_half_bw)
- mod_tone_idx = i + fft_max_half_bw;
- else
- mod_tone_idx = i - fft_max_half_bw;
-
- psd_result_tmp = 0;
- for (t = 0; t < dm_psd_table->sw_avg_time; t++)
- psd_result_tmp +=
- phydm_get_psd_data(dm, mod_tone_idx, igi);
- psd_result =
- (u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
- dm_psd_table->psd_pwr_common_offset;
-
- if (dm_psd_table->fft_smp_point == 128 &&
- (dm_psd_table->noise_k_en)) {
- if (i > psd_result_cali_tone[noise_table_idx])
- noise_table_idx++;
-
- if (noise_table_idx > 6)
- noise_table_idx = 6;
-
- if (psd_result >= psd_result_cali_val[noise_table_idx])
- psd_result =
- psd_result -
- psd_result_cali_val[noise_table_idx];
- else
- psd_result = 0;
-
- dm_psd_table->psd_result[i] = psd_result;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
- mod_tone_idx, psd_result_cali_val[noise_table_idx],
- psd_result);
- }
-
- /*[Start 3-wires]*/
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, 0xc00, 0xf, 0x7); /* hardware 3-wire on */
- odm_set_bb_reg(dm, 0xe00, 0xf, 0x7); /* hardware 3-wire on */
- } else {
- odm_set_bb_reg(dm, 0x88c, 0xf00000,
- 0x0); /* 3 wire enable 88c[23:20]=0x0 */
- }
- ODM_delay_us(10);
-
- /*[Revert Reg]*/
- odm_set_bb_reg(dm, 0x520, 0xff0000, 0x0); /*start all TX queue*/
- odm_set_bb_reg(dm, 0x808, BIT(28), 1); /*enable CCK block*/
- odm_set_bb_reg(dm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/
-
- odm_set_bb_reg(dm, psd_igi_a_reg, 0xff,
- dm_psd_table->initial_gain_backup);
- odm_set_bb_reg(dm, psd_igi_b_reg, 0xff,
- dm_psd_table->initial_gain_backup);
-
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK,
- dm_psd_table->rf_0x18_bkp);
-
- ODM_RT_TRACE(dm, ODM_COMP_API, "PSD finished\n\n");
-
- dm->support_ability |= ODM_BB_DIG;
- dm->support_ability |= ODM_BB_FA_CNT;
- dm_psd_table->psd_in_progress = 0;
-}
-
-void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
- u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
- u8 psd_input, u8 channel, u8 noise_k_en)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct psd_info *dm_psd_table = &dm->dm_psd_table;
- u8 fft_smp_point_idx = 0;
-
- dm_psd_table->fft_smp_point = fft_smp_point;
-
- if (sw_avg_time == 0)
- sw_avg_time = 1;
-
- dm_psd_table->sw_avg_time = sw_avg_time;
- dm_psd_table->psd_fc_channel = channel;
- dm_psd_table->noise_k_en = noise_k_en;
-
- if (fft_smp_point == 128)
- fft_smp_point_idx = 0;
- else if (fft_smp_point == 256)
- fft_smp_point_idx = 1;
- else if (fft_smp_point == 512)
- fft_smp_point_idx = 2;
- else if (fft_smp_point == 1024)
- fft_smp_point_idx = 3;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- odm_set_bb_reg(dm, 0x910, BIT(11) | BIT(10), i_q_setting);
- odm_set_bb_reg(dm, 0x910, BIT(13) | BIT(12), hw_avg_time);
- odm_set_bb_reg(dm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx);
- odm_set_bb_reg(dm, 0x910, BIT(17) | BIT(16), ant_sel);
- odm_set_bb_reg(dm, 0x910, BIT(23), psd_input);
- }
-
- /*bw = (*dm->band_width); //ODM_BW20M */
- /*channel = *(dm->channel);*/
-}
-
-void phydm_psd_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct psd_info *dm_psd_table = &dm->dm_psd_table;
-
- ODM_RT_TRACE(dm, ODM_COMP_API, "PSD para init\n");
-
- dm_psd_table->psd_in_progress = false;
-
- if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
- dm_psd_table->psd_reg = 0x910;
- dm_psd_table->psd_report_reg = 0xF44;
-
- if (ODM_IC_11AC_2_SERIES)
- dm_psd_table->psd_bw_rf_reg =
- 1; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
- else
- dm_psd_table->psd_bw_rf_reg =
- 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
-
- } else {
- dm_psd_table->psd_reg = 0x808;
- dm_psd_table->psd_report_reg = 0x8B4;
- dm_psd_table->psd_bw_rf_reg =
- 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
- }
-
- dm_psd_table->psd_pwr_common_offset = 0;
-
- phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
- /*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
-}
-
-void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used, char *output,
- u32 *_out_len, u32 input_num)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- char help[] = "-h";
- u32 var1[10] = {0};
- u32 used = *_used;
- u32 out_len = *_out_len;
- u8 i;
-
- if ((strcmp(input[1], help) == 0)) {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
- PHYDM_SNPRINTF(output + used, out_len - used,
- "{1} {IGI(hex)} {start_point} {stop_point}\n");
- return;
- }
-
- PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-
- if (var1[0] == 0) {
- for (i = 1; i < 10; i++) {
- if (input[i + 1])
- PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
- &var1[i]);
- }
-
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
- var1[1], var1[2], var1[3], var1[4], var1[5], var1[6],
- (u8)var1[7], (u8)var1[8]);
- phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
- (u8)var1[3], (u16)var1[4], (u8)var1[5],
- (u8)var1[6], (u8)var1[7], (u8)var1[8]);
-
- } else if (var1[0] == 1) {
- PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
- PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
- PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
- var1[1], var1[2], var1[3]);
- dm->debug_components |= ODM_COMP_API;
- phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]);
- dm->debug_components &= (~ODM_COMP_API);
- }
-}
-
-u8 phydm_get_psd_result_table(void *dm_void, int index)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct psd_info *dm_psd_table = &dm->dm_psd_table;
- u8 temp_result = 0;
-
- if (index < 128)
- temp_result = dm_psd_table->psd_result[index];
-
- return temp_result;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMPSD_H__
-#define __PHYDMPSD_H__
-
-/*#define PSD_VERSION "1.0"*/ /*2016.09.22 Dino*/
-#define PSD_VERSION "1.1" /*2016.10.07 Dino, Add Option for PSD Tone index
- *Selection
- */
-
-#define STOP_TRX_SUCCESS 1
-#define STOP_TRX_FAIL 0
-
-struct psd_info {
- u8 psd_in_progress;
- u32 psd_reg;
- u32 psd_report_reg;
- u8 psd_pwr_common_offset;
- u16 sw_avg_time;
- u16 fft_smp_point;
- u32 initial_gain_backup;
- u32 rf_0x18_bkp;
- u16 psd_fc_channel;
- u32 psd_bw_rf_reg;
- u8 psd_result[128];
- u8 noise_k_en;
-};
-
-u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi);
-
-void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used, char *output,
- u32 *_out_len, u32 input_num);
-
-void phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point);
-
-void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
- u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
- u8 psd_input, u8 channel, u8 noise_k_en);
-
-void phydm_psd_init(void *dm_void);
-
-u8 phydm_get_psd_result_table(void *dm_void, int index);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/* ************************************************************
- * include files
- * *************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-void phydm_h2C_debug(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
- u8 phydm_h2c_id = (u8)dm_value[0];
- u8 i;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- PHYDM_SNPRINTF(output + used, out_len - used,
- "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id);
- for (i = 0; i < H2C_MAX_LENGTH; i++) {
- h2c_parameter[i] = (u8)dm_value[i + 1];
- PHYDM_SNPRINTF(output + used, out_len - used,
- "H2C: Byte[%d] = ((0x%x))\n", i,
- h2c_parameter[i]);
- }
-
- odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
-}
-
-void phydm_RA_debug_PCR(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ra_table *ra_tab = &dm->dm_ra_table;
- u32 used = *_used;
- u32 out_len = *_out_len;
-
- if (dm_value[0] == 100) {
- PHYDM_SNPRINTF(
- output + used, out_len - used,
- "[Get] PCR RA_threshold_offset = (( %s%d ))\n",
- ((ra_tab->RA_threshold_offset == 0) ?
- " " :
- ((ra_tab->RA_offset_direction) ? "+" : "-")),
- ra_tab->RA_threshold_offset);
- /**/
- } else if (dm_value[0] == 0) {
- ra_tab->RA_offset_direction = 0;
- ra_tab->RA_threshold_offset = (u8)dm_value[1];
- PHYDM_SNPRINTF(output + used, out_len - used,
- "[Set] PCR RA_threshold_offset = (( -%d ))\n",
- ra_tab->RA_threshold_offset);
- } else if (dm_value[0] == 1) {
- ra_tab->RA_offset_direction = 1;
- ra_tab->RA_threshold_offset = (u8)dm_value[1];
- PHYDM_SNPRINTF(output + used, out_len - used,
- "[Set] PCR RA_threshold_offset = (( +%d ))\n",
- ra_tab->RA_threshold_offset);
- } else {
- PHYDM_SNPRINTF(output + used, out_len - used, "[Set] Error\n");
- /**/
- }
-}
-
-void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- u8 para_idx = cmd_buf[0]; /*Retry Penalty, NH, NL*/
- u8 i;
-
- ODM_RT_TRACE(dm, PHYDM_COMP_RA_DBG,
- "[ From FW C2H RA Para ] cmd_buf[0]= (( %d ))\n",
- cmd_buf[0]);
-
- if (para_idx == RADBG_DEBUG_MONITOR1) {
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "-------------------------------\n");
- if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "RSSI =", cmd_buf[1]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "rate =", cmd_buf[2] & 0x7f);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "SGI =", (cmd_buf[2] & 0x80) >> 7);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "BW =", cmd_buf[3]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "BW_max =", cmd_buf[4]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "multi_rate0 =", cmd_buf[5]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "multi_rate1 =", cmd_buf[6]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "DISRA =", cmd_buf[7]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "VHT_EN =", cmd_buf[8]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "SGI_support =", cmd_buf[9]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "try_ness =", cmd_buf[10]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "pre_rate =", cmd_buf[11]);
- } else {
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "RSSI =", cmd_buf[1]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %x\n",
- "BW =", cmd_buf[2]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "DISRA =", cmd_buf[3]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "VHT_EN =", cmd_buf[4]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "Highest rate =", cmd_buf[5]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "Lowest rate =", cmd_buf[6]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "SGI_support =", cmd_buf[7]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "Rate_ID =", cmd_buf[8]);
- }
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "-------------------------------\n");
- } else if (para_idx == RADBG_DEBUG_MONITOR2) {
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "-------------------------------\n");
- if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "rate_id =", cmd_buf[1]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "highest_rate =", cmd_buf[2]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "lowest_rate =", cmd_buf[3]);
-
- for (i = 4; i <= 11; i++)
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "RAMASK = 0x%x\n", cmd_buf[i]);
- } else {
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "%5s %x%x %x%x %x%x %x%x\n",
- "RA Mask:", cmd_buf[8], cmd_buf[7],
- cmd_buf[6], cmd_buf[5], cmd_buf[4],
- cmd_buf[3], cmd_buf[2], cmd_buf[1]);
- }
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "-------------------------------\n");
- } else if (para_idx == RADBG_DEBUG_MONITOR3) {
- for (i = 0; i < (cmd_len - 1); i++)
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
- "content[%d] = %d\n", i, cmd_buf[1 + i]);
- } else if (para_idx == RADBG_DEBUG_MONITOR4) {
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s {%d.%d}\n",
- "RA version =", cmd_buf[1], cmd_buf[2]);
- } else if (para_idx == RADBG_DEBUG_MONITOR5) {
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "Current rate =", cmd_buf[1]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "Retry ratio =", cmd_buf[2]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s %d\n",
- "rate down ratio =", cmd_buf[3]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x\n",
- "highest rate =", cmd_buf[4]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s {0x%x 0x%x}\n",
- "Muti-try =", cmd_buf[5], cmd_buf[6]);
- ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s 0x%x%x%x%x%x\n",
- "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9],
- cmd_buf[8], cmd_buf[7]);
- }
-}
-
-void phydm_ra_dynamic_retry_count(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
- return;
-
- if (dm->pre_b_noisy != dm->noisy_decision) {
- if (dm->noisy_decision) {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
- "->Noisy Env. RA fallback value\n");
- odm_set_mac_reg(dm, 0x430, MASKDWORD, 0x0);
- odm_set_mac_reg(dm, 0x434, MASKDWORD, 0x04030201);
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
- "->Clean Env. RA fallback value\n");
- odm_set_mac_reg(dm, 0x430, MASKDWORD, 0x01000000);
- odm_set_mac_reg(dm, 0x434, MASKDWORD, 0x06050402);
- }
- dm->pre_b_noisy = dm->noisy_decision;
- }
-}
-
-void phydm_ra_dynamic_retry_limit(void *dm_void) {}
-
-void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
- u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
- u8 vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0;
- u8 b_sgi = (rate & 0x80) >> 7;
-
- ODM_RT_TRACE(dm, dbg_component, "( %s%s%s%s%d%s%s)\n",
- ((rate_idx >= ODM_RATEVHTSS1MCS0) &&
- (rate_idx <= ODM_RATEVHTSS1MCS9)) ?
- "VHT 1ss " :
- "",
- ((rate_idx >= ODM_RATEVHTSS2MCS0) &&
- (rate_idx <= ODM_RATEVHTSS2MCS9)) ?
- "VHT 2ss " :
- "",
- ((rate_idx >= ODM_RATEVHTSS3MCS0) &&
- (rate_idx <= ODM_RATEVHTSS3MCS9)) ?
- "VHT 3ss " :
- "",
- (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
- (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) :
- ((rate_idx >= ODM_RATEMCS0) ?
- (rate_idx - ODM_RATEMCS0) :
- ((rate_idx <= ODM_RATE54M) ?
- legacy_table[rate_idx] :
- 0)),
- (b_sgi) ? "-S" : " ",
- (rate_idx >= ODM_RATEMCS0) ? "" : "M");
-}
-
-void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ra_table *ra_tab = &dm->dm_ra_table;
- u8 macid = cmd_buf[1];
- u8 rate = cmd_buf[0];
- u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
- u8 rate_order;
-
- if (cmd_len >= 4) {
- if (cmd_buf[3] == 0) {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
- "TX Init-rate Update[%d]:", macid);
- /**/
- } else if (cmd_buf[3] == 0xff) {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
- "FW Level: Fix rate[%d]:", macid);
- /**/
- } else if (cmd_buf[3] == 1) {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
- "Try Success[%d]:", macid);
- /**/
- } else if (cmd_buf[3] == 2) {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
- "Try Fail & Try Again[%d]:", macid);
- /**/
- } else if (cmd_buf[3] == 3) {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
- "rate Back[%d]:", macid);
- /**/
- } else if (cmd_buf[3] == 4) {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
- "start rate by RSSI[%d]:", macid);
- /**/
- } else if (cmd_buf[3] == 5) {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
- "Try rate[%d]:", macid);
- /**/
- }
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE, "Tx rate Update[%d]:",
- macid);
- /**/
- }
-
- phydm_print_rate(dm, rate, ODM_COMP_RATE_ADAPTIVE);
-
- ra_tab->link_tx_rate[macid] = rate;
-
- /*trigger power training*/
-
- rate_order = phydm_rate_order_compute(dm, rate_idx);
-
- if ((dm->is_one_entry_only) ||
- ((rate_order > ra_tab->highest_client_tx_order) &&
- (ra_tab->power_tracking_flag == 1))) {
- phydm_update_pwr_track(dm, rate_idx);
- ra_tab->power_tracking_flag = 0;
- }
-
- /*trigger dynamic rate ID*/
-}
-
-void odm_rssi_monitor_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ra_table *ra_tab = &dm->dm_ra_table;
-
- ra_tab->firstconnect = false;
-}
-
-void odm_ra_post_action_on_assoc(void *dm_void) {}
-
-void phydm_init_ra_info(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (dm->support_ic_type == ODM_RTL8822B) {
- u32 ret_value;
-
- ret_value = odm_get_bb_reg(dm, 0x4c8, MASKBYTE2);
- odm_set_bb_reg(dm, 0x4cc, MASKBYTE3, (ret_value - 1));
- }
-}
-
-void phydm_modify_RA_PCR_threshold(void *dm_void, u8 RA_offset_direction,
- u8 RA_threshold_offset
-
- )
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ra_table *ra_tab = &dm->dm_ra_table;
-
- ra_tab->RA_offset_direction = RA_offset_direction;
- ra_tab->RA_threshold_offset = RA_threshold_offset;
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "Set RA_threshold_offset = (( %s%d ))\n",
- ((RA_threshold_offset == 0) ?
- " " :
- ((RA_offset_direction) ? "+" : "-")),
- RA_threshold_offset);
-}
-
-static void odm_rssi_monitor_check_mp(void *dm_void) {}
-
-static void odm_rssi_monitor_check_ce(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ra_table *ra_tab = &dm->dm_ra_table;
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- struct rtl_sta_info *entry;
- int i;
- int tmp_entry_min_pwdb = 0xff;
- unsigned long cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0;
- u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0;
- u8 h2c_parameter[H2C_0X42_LENGTH] = {0};
- u8 cmdlen = H2C_0X42_LENGTH;
- u8 macid = 0;
-
- if (!dm->is_linked)
- return;
-
- for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
- entry = (struct rtl_sta_info *)dm->odm_sta_info[i];
- if (!IS_STA_VALID(entry))
- continue;
-
- if (is_multicast_ether_addr(entry->mac_addr) ||
- is_broadcast_ether_addr(entry->mac_addr))
- continue;
-
- if (entry->rssi_stat.undecorated_smoothed_pwdb == (-1))
- continue;
-
- /* calculate min_pwdb */
- if (entry->rssi_stat.undecorated_smoothed_pwdb <
- tmp_entry_min_pwdb)
- tmp_entry_min_pwdb =
- entry->rssi_stat.undecorated_smoothed_pwdb;
-
- /* report RSSI */
- cur_tx_ok_cnt = rtlpriv->stats.txbytesunicast_inperiod;
- cur_rx_ok_cnt = rtlpriv->stats.rxbytesunicast_inperiod;
-
- if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6))
- UL_DL_STATE = 1;
- else
- UL_DL_STATE = 0;
-
- if (mac->opmode == NL80211_IFTYPE_AP ||
- mac->opmode == NL80211_IFTYPE_ADHOC) {
- struct ieee80211_sta *sta = container_of(
- (void *)entry, struct ieee80211_sta, drv_priv);
- macid = sta->aid + 1;
- }
-
- h2c_parameter[0] = macid;
- h2c_parameter[2] =
- entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F;
-
- if (UL_DL_STATE)
- h2c_parameter[3] |= RAINFO_BE_RX_STATE;
-
- if (tx_bf_en)
- h2c_parameter[3] |= RAINFO_BF_STATE;
- if (STBC_TX)
- h2c_parameter[3] |= RAINFO_STBC_STATE;
- if (dm->noisy_decision)
- h2c_parameter[3] |= RAINFO_NOISY_STATE;
-
- if (entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND) {
- h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
- entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD;
- }
-
- h2c_parameter[4] = (ra_tab->RA_threshold_offset & 0x7f) |
- (ra_tab->RA_offset_direction << 7);
-
- odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, cmdlen,
- h2c_parameter);
- }
-
- if (tmp_entry_min_pwdb != 0xff)
- dm->rssi_min = tmp_entry_min_pwdb;
-}
-
-static void odm_rssi_monitor_check_ap(void *dm_void) {}
-
-void odm_rssi_monitor_check(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- if (!(dm->support_ability & ODM_BB_RSSI_MONITOR))
- return;
-
- switch (dm->support_platform) {
- case ODM_WIN:
- odm_rssi_monitor_check_mp(dm);
- break;
-
- case ODM_CE:
- odm_rssi_monitor_check_ce(dm);
- break;
-
- case ODM_AP:
- odm_rssi_monitor_check_ap(dm);
- break;
-
- default:
- break;
- }
-}
-
-void odm_rate_adaptive_mask_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct odm_rate_adaptive *odm_ra = &dm->rate_adaptive;
-
- odm_ra->type = dm_type_by_driver;
- if (odm_ra->type == dm_type_by_driver)
- dm->is_use_ra_mask = true;
- else
- dm->is_use_ra_mask = false;
-
- odm_ra->ratr_state = DM_RATR_STA_INIT;
-
- odm_ra->ldpc_thres = 35;
- odm_ra->is_use_ldpc = false;
-
- odm_ra->high_rssi_thresh = 50;
- odm_ra->low_rssi_thresh = 20;
-}
-
-/*-----------------------------------------------------------------------------
- * Function: odm_refresh_rate_adaptive_mask()
- *
- * Overview: Update rate table mask according to rssi
- *
- * Input: NONE
- *
- * Output: NONE
- *
- * Return: NONE
- *
- * Revised History:
- * When Who Remark
- * 05/27/2009 hpfan Create version 0.
- *
- *---------------------------------------------------------------------------
- */
-void odm_refresh_rate_adaptive_mask(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ra_table *ra_tab = &dm->dm_ra_table;
-
- if (!dm->is_linked)
- return;
-
- if (!(dm->support_ability & ODM_BB_RA_MASK)) {
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "%s(): Return cos not supported\n", __func__);
- return;
- }
-
- ra_tab->force_update_ra_mask_count++;
- /* 2011/09/29 MH In HW integration first stage, we provide 4 different
- * handle to operate at the same time.
- * In the stage2/3, we need to prive universal interface and merge all
- * HW dynamic mechanism.
- */
- switch (dm->support_platform) {
- case ODM_WIN:
- odm_refresh_rate_adaptive_mask_mp(dm);
- break;
-
- case ODM_CE:
- odm_refresh_rate_adaptive_mask_ce(dm);
- break;
-
- case ODM_AP:
- odm_refresh_rate_adaptive_mask_apadsl(dm);
- break;
- }
-}
-
-static u8 phydm_trans_platform_bw(void *dm_void, u8 BW)
-{
- if (BW == HT_CHANNEL_WIDTH_20)
- BW = PHYDM_BW_20;
-
- else if (BW == HT_CHANNEL_WIDTH_20_40)
- BW = PHYDM_BW_40;
-
- else if (BW == HT_CHANNEL_WIDTH_80)
- BW = PHYDM_BW_80;
-
- return BW;
-}
-
-static u8 phydm_trans_platform_rf_type(void *dm_void, u8 rf_type)
-{
- if (rf_type == RF_1T2R)
- rf_type = PHYDM_RF_1T2R;
-
- else if (rf_type == RF_2T4R)
- rf_type = PHYDM_RF_2T4R;
-
- else if (rf_type == RF_2T2R)
- rf_type = PHYDM_RF_2T2R;
-
- else if (rf_type == RF_1T1R)
- rf_type = PHYDM_RF_1T1R;
-
- else if (rf_type == RF_2T2R_GREEN)
- rf_type = PHYDM_RF_2T2R_GREEN;
-
- else if (rf_type == RF_3T3R)
- rf_type = PHYDM_RF_3T3R;
-
- else if (rf_type == RF_4T4R)
- rf_type = PHYDM_RF_4T4R;
-
- else if (rf_type == RF_2T3R)
- rf_type = PHYDM_RF_1T2R;
-
- else if (rf_type == RF_3T4R)
- rf_type = PHYDM_RF_3T4R;
-
- return rf_type;
-}
-
-static u32 phydm_trans_platform_wireless_mode(void *dm_void, u32 wireless_mode)
-{
- return wireless_mode;
-}
-
-u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 vht_en_out = 0;
-
- if ((wireless_mode == PHYDM_WIRELESS_MODE_AC_5G) ||
- (wireless_mode == PHYDM_WIRELESS_MODE_AC_24G) ||
- (wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)) {
- vht_en_out = 1;
- /**/
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n",
- wireless_mode, vht_en_out);
- return vht_en_out;
-}
-
-u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 rate_id_idx = 0;
- u8 phydm_BW;
- u8 phydm_rf_type;
-
- phydm_BW = phydm_trans_platform_bw(dm, bw);
- phydm_rf_type = phydm_trans_platform_rf_type(dm, rf_type);
- wireless_mode = phydm_trans_platform_wireless_mode(dm, wireless_mode);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_RA_MASK,
- "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
- wireless_mode, phydm_rf_type, phydm_BW);
-
- switch (wireless_mode) {
- case PHYDM_WIRELESS_MODE_N_24G: {
- if (phydm_BW == PHYDM_BW_40) {
- if (phydm_rf_type == PHYDM_RF_1T1R)
- rate_id_idx = PHYDM_BGN_40M_1SS;
- else if (phydm_rf_type == PHYDM_RF_2T2R)
- rate_id_idx = PHYDM_BGN_40M_2SS;
- else
- rate_id_idx = PHYDM_ARFR5_N_3SS;
-
- } else {
- if (phydm_rf_type == PHYDM_RF_1T1R)
- rate_id_idx = PHYDM_BGN_20M_1SS;
- else if (phydm_rf_type == PHYDM_RF_2T2R)
- rate_id_idx = PHYDM_BGN_20M_2SS;
- else
- rate_id_idx = PHYDM_ARFR5_N_3SS;
- }
- } break;
-
- case PHYDM_WIRELESS_MODE_N_5G: {
- if (phydm_rf_type == PHYDM_RF_1T1R)
- rate_id_idx = PHYDM_GN_N1SS;
- else if (phydm_rf_type == PHYDM_RF_2T2R)
- rate_id_idx = PHYDM_GN_N2SS;
- else
- rate_id_idx = PHYDM_ARFR5_N_3SS;
- }
-
- break;
-
- case PHYDM_WIRELESS_MODE_G:
- rate_id_idx = PHYDM_BG;
- break;
-
- case PHYDM_WIRELESS_MODE_A:
- rate_id_idx = PHYDM_G;
- break;
-
- case PHYDM_WIRELESS_MODE_B:
- rate_id_idx = PHYDM_B_20M;
- break;
-
- case PHYDM_WIRELESS_MODE_AC_5G:
- case PHYDM_WIRELESS_MODE_AC_ONLY: {
- if (phydm_rf_type == PHYDM_RF_1T1R)
- rate_id_idx = PHYDM_ARFR1_AC_1SS;
- else if (phydm_rf_type == PHYDM_RF_2T2R)
- rate_id_idx = PHYDM_ARFR0_AC_2SS;
- else
- rate_id_idx = PHYDM_ARFR4_AC_3SS;
- } break;
-
- case PHYDM_WIRELESS_MODE_AC_24G: {
- /*Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS
- *in 2.4G/5G
- */
- if (phydm_BW >= PHYDM_BW_80) {
- if (phydm_rf_type == PHYDM_RF_1T1R)
- rate_id_idx = PHYDM_ARFR1_AC_1SS;
- else if (phydm_rf_type == PHYDM_RF_2T2R)
- rate_id_idx = PHYDM_ARFR0_AC_2SS;
- else
- rate_id_idx = PHYDM_ARFR4_AC_3SS;
- } else {
- if (phydm_rf_type == PHYDM_RF_1T1R)
- rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
- else if (phydm_rf_type == PHYDM_RF_2T2R)
- rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
- else
- rate_id_idx = PHYDM_ARFR4_AC_3SS;
- }
- } break;
-
- default:
- rate_id_idx = 0;
- break;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "RA rate ID = (( 0x%x ))\n",
- rate_id_idx);
-
- return rate_id_idx;
-}
-
-void phydm_update_hal_ra_mask(void *dm_void, u32 wireless_mode, u8 rf_type,
- u8 BW, u8 mimo_ps_enable, u8 disable_cck_rate,
- u32 *ratr_bitmap_msb_in, u32 *ratr_bitmap_lsb_in,
- u8 tx_rate_level)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 phydm_rf_type;
- u8 phydm_BW;
- u32 ratr_bitmap = *ratr_bitmap_lsb_in,
- ratr_bitmap_msb = *ratr_bitmap_msb_in;
-
- wireless_mode = phydm_trans_platform_wireless_mode(dm, wireless_mode);
-
- phydm_rf_type = phydm_trans_platform_rf_type(dm, rf_type);
- phydm_BW = phydm_trans_platform_bw(dm, BW);
-
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "Platform original RA Mask = (( 0x %x | %x ))\n",
- ratr_bitmap_msb, ratr_bitmap);
-
- switch (wireless_mode) {
- case PHYDM_WIRELESS_MODE_B: {
- ratr_bitmap &= 0x0000000f;
- } break;
-
- case PHYDM_WIRELESS_MODE_G: {
- ratr_bitmap &= 0x00000ff5;
- } break;
-
- case PHYDM_WIRELESS_MODE_A: {
- ratr_bitmap &= 0x00000ff0;
- } break;
-
- case PHYDM_WIRELESS_MODE_N_24G:
- case PHYDM_WIRELESS_MODE_N_5G: {
- if (mimo_ps_enable)
- phydm_rf_type = PHYDM_RF_1T1R;
-
- if (phydm_rf_type == PHYDM_RF_1T1R) {
- if (phydm_BW == PHYDM_BW_40)
- ratr_bitmap &= 0x000ff015;
- else
- ratr_bitmap &= 0x000ff005;
- } else if (phydm_rf_type == PHYDM_RF_2T2R ||
- phydm_rf_type == PHYDM_RF_2T4R ||
- phydm_rf_type == PHYDM_RF_2T3R) {
- if (phydm_BW == PHYDM_BW_40)
- ratr_bitmap &= 0x0ffff015;
- else
- ratr_bitmap &= 0x0ffff005;
- } else { /*3T*/
-
- ratr_bitmap &= 0xfffff015;
- ratr_bitmap_msb &= 0xf;
- }
- } break;
-
- case PHYDM_WIRELESS_MODE_AC_24G: {
- if (phydm_rf_type == PHYDM_RF_1T1R) {
- ratr_bitmap &= 0x003ff015;
- } else if (phydm_rf_type == PHYDM_RF_2T2R ||
- phydm_rf_type == PHYDM_RF_2T4R ||
- phydm_rf_type == PHYDM_RF_2T3R) {
- ratr_bitmap &= 0xfffff015;
- } else { /*3T*/
-
- ratr_bitmap &= 0xfffff010;
- ratr_bitmap_msb &= 0x3ff;
- }
-
- if (phydm_BW ==
- PHYDM_BW_20) { /* AC 20MHz doesn't support MCS9 */
- ratr_bitmap &= 0x7fdfffff;
- ratr_bitmap_msb &= 0x1ff;
- }
- } break;
-
- case PHYDM_WIRELESS_MODE_AC_5G: {
- if (phydm_rf_type == PHYDM_RF_1T1R) {
- ratr_bitmap &= 0x003ff010;
- } else if (phydm_rf_type == PHYDM_RF_2T2R ||
- phydm_rf_type == PHYDM_RF_2T4R ||
- phydm_rf_type == PHYDM_RF_2T3R) {
- ratr_bitmap &= 0xfffff010;
- } else { /*3T*/
-
- ratr_bitmap &= 0xfffff010;
- ratr_bitmap_msb &= 0x3ff;
- }
-
- if (phydm_BW ==
- PHYDM_BW_20) { /* AC 20MHz doesn't support MCS9 */
- ratr_bitmap &= 0x7fdfffff;
- ratr_bitmap_msb &= 0x1ff;
- }
- } break;
-
- default:
- break;
- }
-
- if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
- if (tx_rate_level == 0)
- ratr_bitmap &= 0xffffffff;
- else if (tx_rate_level == 1)
- ratr_bitmap &= 0xfffffff0;
- else if (tx_rate_level == 2)
- ratr_bitmap &= 0xffffefe0;
- else if (tx_rate_level == 3)
- ratr_bitmap &= 0xffffcfc0;
- else if (tx_rate_level == 4)
- ratr_bitmap &= 0xffff8f80;
- else if (tx_rate_level >= 5)
- ratr_bitmap &= 0xffff0f00;
- }
-
- if (disable_cck_rate)
- ratr_bitmap &= 0xfffffff0;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_RA_MASK,
- "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
- wireless_mode, phydm_rf_type, phydm_BW, mimo_ps_enable,
- tx_rate_level);
-
- *ratr_bitmap_lsb_in = ratr_bitmap;
- *ratr_bitmap_msb_in = ratr_bitmap_msb;
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "Phydm modified RA Mask = (( 0x %x | %x ))\n",
- *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);
-}
-
-u8 phydm_RA_level_decision(void *dm_void, u32 rssi, u8 ratr_state)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {
- 20, 34, 38, 42,
- 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
- u8 new_ratr_state = 0;
- u8 i;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_RA_MASK,
- "curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n",
- ratr_state, ra_rate_floor_table[0], ra_rate_floor_table[1],
- ra_rate_floor_table[2], ra_rate_floor_table[3],
- ra_rate_floor_table[4], ra_rate_floor_table[5]);
-
- for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
- if (i >= (ratr_state))
- ra_rate_floor_table[i] += RA_FLOOR_UP_GAP;
- }
-
- ODM_RT_TRACE(
- dm, ODM_COMP_RA_MASK,
- "RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n",
- rssi, ra_rate_floor_table[0], ra_rate_floor_table[1],
- ra_rate_floor_table[2], ra_rate_floor_table[3],
- ra_rate_floor_table[4], ra_rate_floor_table[5]);
-
- for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
- if (rssi < ra_rate_floor_table[i]) {
- new_ratr_state = i;
- break;
- }
- }
-
- return new_ratr_state;
-}
-
-void odm_refresh_rate_adaptive_mask_mp(void *dm_void) {}
-
-void odm_refresh_rate_adaptive_mask_ce(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ra_table *ra_tab = &dm->dm_ra_table;
- void *adapter = dm->adapter;
- u32 i;
- struct rtl_sta_info *entry;
- u8 ratr_state_new;
-
- if (!dm->is_use_ra_mask) {
- ODM_RT_TRACE(
- dm, ODM_COMP_RA_MASK,
- "<---- %s(): driver does not control rate adaptive mask\n",
- __func__);
- return;
- }
-
- for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
- entry = dm->odm_sta_info[i];
-
- if (!IS_STA_VALID(entry))
- continue;
-
- if (is_multicast_ether_addr(entry->mac_addr))
- continue;
- else if (is_broadcast_ether_addr(entry->mac_addr))
- continue;
-
- ratr_state_new = phydm_RA_level_decision(
- dm, entry->rssi_stat.undecorated_smoothed_pwdb,
- entry->rssi_level);
-
- if ((entry->rssi_level != ratr_state_new) ||
- (ra_tab->force_update_ra_mask_count >=
- FORCED_UPDATE_RAMASK_PERIOD)) {
- ra_tab->force_update_ra_mask_count = 0;
- ODM_RT_TRACE(
- dm, ODM_COMP_RA_MASK,
- "Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n",
- entry->rssi_level, ratr_state_new,
- entry->rssi_stat.undecorated_smoothed_pwdb);
-
- entry->rssi_level = ratr_state_new;
- rtl_hal_update_ra_mask(adapter, entry,
- entry->rssi_level);
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "Stay in RA level = (( %d ))\n\n",
- ratr_state_new);
- /**/
- }
- }
-}
-
-void odm_refresh_rate_adaptive_mask_apadsl(void *dm_void) {}
-
-void odm_refresh_basic_rate_mask(void *dm_void) {}
-
-u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
-{
- if (rate_idx >= ODM_RATEVHTSS4MCS0) {
- rate_idx -= ODM_RATEVHTSS4MCS0;
- /**/
- } else if (rate_idx >= ODM_RATEVHTSS3MCS0) {
- rate_idx -= ODM_RATEVHTSS3MCS0;
- /**/
- } else if (rate_idx >= ODM_RATEVHTSS2MCS0) {
- rate_idx -= ODM_RATEVHTSS2MCS0;
- /**/
- } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
- rate_idx -= ODM_RATEVHTSS1MCS0;
- /**/
- } else if (rate_idx >= ODM_RATEMCS24) {
- rate_idx -= ODM_RATEMCS24;
- /**/
- } else if (rate_idx >= ODM_RATEMCS16) {
- rate_idx -= ODM_RATEMCS16;
- /**/
- } else if (rate_idx >= ODM_RATEMCS8) {
- rate_idx -= ODM_RATEMCS8;
- /**/
- }
-
- return rate_idx;
-}
-
-static void phydm_ra_common_info_update(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ra_table *ra_tab = &dm->dm_ra_table;
- u16 macid;
- u8 rate_order_tmp;
- u8 cnt = 0;
-
- ra_tab->highest_client_tx_order = 0;
- ra_tab->power_tracking_flag = 1;
-
- if (dm->number_linked_client != 0) {
- for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
- rate_order_tmp = phydm_rate_order_compute(
- dm, ((ra_tab->link_tx_rate[macid]) & 0x7f));
-
- if (rate_order_tmp >=
- (ra_tab->highest_client_tx_order)) {
- ra_tab->highest_client_tx_order =
- rate_order_tmp;
- ra_tab->highest_client_tx_rate_order = macid;
- }
-
- cnt++;
-
- if (cnt == dm->number_linked_client)
- break;
- }
- ODM_RT_TRACE(
- dm, ODM_COMP_RATE_ADAPTIVE,
- "MACID[%d], Highest Tx order Update for power tracking: %d\n",
- (ra_tab->highest_client_tx_rate_order),
- (ra_tab->highest_client_tx_order));
- }
-}
-
-void phydm_ra_info_watchdog(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- phydm_ra_common_info_update(dm);
- phydm_ra_dynamic_retry_limit(dm);
- phydm_ra_dynamic_retry_count(dm);
- odm_refresh_rate_adaptive_mask(dm);
- odm_refresh_basic_rate_mask(dm);
-}
-
-void phydm_ra_info_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct ra_table *ra_tab = &dm->dm_ra_table;
-
- ra_tab->highest_client_tx_rate_order = 0;
- ra_tab->highest_client_tx_order = 0;
- ra_tab->RA_threshold_offset = 0;
- ra_tab->RA_offset_direction = 0;
-}
-
-u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, bool is_erp_protect)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- u8 rts_ini_rate = ODM_RATE6M;
-
- if (is_erp_protect) { /* use CCK rate as RTS*/
- rts_ini_rate = ODM_RATE1M;
- } else {
- switch (tx_rate) {
- case ODM_RATEVHTSS3MCS9:
- case ODM_RATEVHTSS3MCS8:
- case ODM_RATEVHTSS3MCS7:
- case ODM_RATEVHTSS3MCS6:
- case ODM_RATEVHTSS3MCS5:
- case ODM_RATEVHTSS3MCS4:
- case ODM_RATEVHTSS3MCS3:
- case ODM_RATEVHTSS2MCS9:
- case ODM_RATEVHTSS2MCS8:
- case ODM_RATEVHTSS2MCS7:
- case ODM_RATEVHTSS2MCS6:
- case ODM_RATEVHTSS2MCS5:
- case ODM_RATEVHTSS2MCS4:
- case ODM_RATEVHTSS2MCS3:
- case ODM_RATEVHTSS1MCS9:
- case ODM_RATEVHTSS1MCS8:
- case ODM_RATEVHTSS1MCS7:
- case ODM_RATEVHTSS1MCS6:
- case ODM_RATEVHTSS1MCS5:
- case ODM_RATEVHTSS1MCS4:
- case ODM_RATEVHTSS1MCS3:
- case ODM_RATEMCS15:
- case ODM_RATEMCS14:
- case ODM_RATEMCS13:
- case ODM_RATEMCS12:
- case ODM_RATEMCS11:
- case ODM_RATEMCS7:
- case ODM_RATEMCS6:
- case ODM_RATEMCS5:
- case ODM_RATEMCS4:
- case ODM_RATEMCS3:
- case ODM_RATE54M:
- case ODM_RATE48M:
- case ODM_RATE36M:
- case ODM_RATE24M:
- rts_ini_rate = ODM_RATE24M;
- break;
- case ODM_RATEVHTSS3MCS2:
- case ODM_RATEVHTSS3MCS1:
- case ODM_RATEVHTSS2MCS2:
- case ODM_RATEVHTSS2MCS1:
- case ODM_RATEVHTSS1MCS2:
- case ODM_RATEVHTSS1MCS1:
- case ODM_RATEMCS10:
- case ODM_RATEMCS9:
- case ODM_RATEMCS2:
- case ODM_RATEMCS1:
- case ODM_RATE18M:
- case ODM_RATE12M:
- rts_ini_rate = ODM_RATE12M;
- break;
- case ODM_RATEVHTSS3MCS0:
- case ODM_RATEVHTSS2MCS0:
- case ODM_RATEVHTSS1MCS0:
- case ODM_RATEMCS8:
- case ODM_RATEMCS0:
- case ODM_RATE9M:
- case ODM_RATE6M:
- rts_ini_rate = ODM_RATE6M;
- break;
- case ODM_RATE11M:
- case ODM_RATE5_5M:
- case ODM_RATE2M:
- case ODM_RATE1M:
- rts_ini_rate = ODM_RATE1M;
- break;
- default:
- rts_ini_rate = ODM_RATE6M;
- break;
- }
- }
-
- if (*dm->band_type == 1) {
- if (rts_ini_rate < ODM_RATE6M)
- rts_ini_rate = ODM_RATE6M;
- }
- return rts_ini_rate;
-}
-
-static void odm_set_ra_dm_arfb_by_noisy(struct phy_dm_struct *dm) {}
-
-void odm_update_noisy_state(void *dm_void, bool is_noisy_state_from_c2h)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- /* JJ ADD 20161014 */
- if (dm->support_ic_type == ODM_RTL8821 ||
- dm->support_ic_type == ODM_RTL8812 ||
- dm->support_ic_type == ODM_RTL8723B ||
- dm->support_ic_type == ODM_RTL8192E ||
- dm->support_ic_type == ODM_RTL8188E ||
- dm->support_ic_type == ODM_RTL8723D ||
- dm->support_ic_type == ODM_RTL8710B)
- dm->is_noisy_state = is_noisy_state_from_c2h;
- odm_set_ra_dm_arfb_by_noisy(dm);
-};
-
-void phydm_update_pwr_track(void *dm_void, u8 rate)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n",
- rate);
-
- dm->tx_rate = rate;
-}
-
-/* RA_MASK_PHYDMLIZE, will delete it later*/
-
-bool odm_ra_state_check(void *dm_void, s32 rssi, bool is_force_update,
- u8 *ra_tr_state)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct odm_rate_adaptive *ra = &dm->rate_adaptive;
- const u8 go_up_gap = 5;
- u8 high_rssi_thresh_for_ra = ra->high_rssi_thresh;
- u8 low_rssi_thresh_for_ra = ra->low_rssi_thresh;
- u8 ratr_state;
-
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", rssi,
- *ra_tr_state);
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n",
- high_rssi_thresh_for_ra, low_rssi_thresh_for_ra);
- /* threshold Adjustment:
- * when RSSI state trends to go up one or two levels, make sure RSSI is
- * high enough. Here go_up_gap is added to solve the boundary's level
- * alternation issue.
- */
-
- switch (*ra_tr_state) {
- case DM_RATR_STA_INIT:
- case DM_RATR_STA_HIGH:
- break;
-
- case DM_RATR_STA_MIDDLE:
- high_rssi_thresh_for_ra += go_up_gap;
- break;
-
- case DM_RATR_STA_LOW:
- high_rssi_thresh_for_ra += go_up_gap;
- low_rssi_thresh_for_ra += go_up_gap;
- break;
-
- default:
- WARN_ONCE(true, "wrong rssi level setting %d !", *ra_tr_state);
- break;
- }
-
- /* Decide ratr_state by RSSI.*/
- if (rssi > high_rssi_thresh_for_ra)
- ratr_state = DM_RATR_STA_HIGH;
- else if (rssi > low_rssi_thresh_for_ra)
- ratr_state = DM_RATR_STA_MIDDLE;
-
- else
- ratr_state = DM_RATR_STA_LOW;
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n",
- high_rssi_thresh_for_ra, low_rssi_thresh_for_ra);
-
- if (*ra_tr_state != ratr_state || is_force_update) {
- ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
- "[RSSI Level Update] %d->%d\n", *ra_tr_state,
- ratr_state);
- *ra_tr_state = ratr_state;
- return true;
- }
-
- return false;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __PHYDMRAINFO_H__
-#define __PHYDMRAINFO_H__
-
-/*#define RAINFO_VERSION "2.0"*/ /*2014.11.04*/
-/*#define RAINFO_VERSION "3.0"*/ /*2015.01.13 Dino*/
-/*#define RAINFO_VERSION "3.1"*/ /*2015.01.14 Dino*/
-/*#define RAINFO_VERSION "3.3"*/ /*2015.07.29 YuChen*/
-/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
-/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask
- *state and Phydm-lize partial ra mask
- *function
- */
-/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to
- *adjust PCR RA threshold
- */
-/*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */
-#define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem*/
-
-#define FORCED_UPDATE_RAMASK_PERIOD 5
-
-#define H2C_0X42_LENGTH 5
-#define H2C_MAX_LENGTH 7
-
-#define RA_FLOOR_UP_GAP 3
-#define RA_FLOOR_TABLE_SIZE 7
-
-#define ACTIVE_TP_THRESHOLD 150
-#define RA_RETRY_DESCEND_NUM 2
-#define RA_RETRY_LIMIT_LOW 4
-#define RA_RETRY_LIMIT_HIGH 32
-
-#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */
-#define RAINFO_STBC_STATE BIT(1)
-/* #define RAINFO_LDPC_STATE BIT2 */
-#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */
-#define RAINFO_SHURTCUT_STATE BIT(3)
-#define RAINFO_SHURTCUT_FLAG BIT(4)
-#define RAINFO_INIT_RSSI_RATE_STATE BIT(5)
-#define RAINFO_BF_STATE BIT(6)
-#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */
-
-#define RA_MASK_CCK 0xf
-#define RA_MASK_OFDM 0xff0
-#define RA_MASK_HT1SS 0xff000
-#define RA_MASK_HT2SS 0xff00000
-/*#define RA_MASK_MCS3SS */
-#define RA_MASK_HT4SS 0xff0
-#define RA_MASK_VHT1SS 0x3ff000
-#define RA_MASK_VHT2SS 0xffc00000
-
-#define RA_FIRST_MACID 0
-
-#define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init
-
-#define DM_RATR_STA_INIT 0
-#define DM_RATR_STA_HIGH 1
-#define DM_RATR_STA_MIDDLE 2
-#define DM_RATR_STA_LOW 3
-#define DM_RATR_STA_ULTRA_LOW 4
-
-enum phydm_ra_arfr_num {
- ARFR_0_RATE_ID = 0x9,
- ARFR_1_RATE_ID = 0xa,
- ARFR_2_RATE_ID = 0xb,
- ARFR_3_RATE_ID = 0xc,
- ARFR_4_RATE_ID = 0xd,
- ARFR_5_RATE_ID = 0xe
-};
-
-enum phydm_ra_dbg_para {
- RADBG_PCR_TH_OFFSET = 0,
- RADBG_RTY_PENALTY = 1,
- RADBG_N_HIGH = 2,
- RADBG_N_LOW = 3,
- RADBG_TRATE_UP_TABLE = 4,
- RADBG_TRATE_DOWN_TABLE = 5,
- RADBG_TRYING_NECESSARY = 6,
- RADBG_TDROPING_NECESSARY = 7,
- RADBG_RATE_UP_RTY_RATIO = 8,
- RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
-
- RADBG_DEBUG_MONITOR1 = 0xc,
- RADBG_DEBUG_MONITOR2 = 0xd,
- RADBG_DEBUG_MONITOR3 = 0xe,
- RADBG_DEBUG_MONITOR4 = 0xf,
- RADBG_DEBUG_MONITOR5 = 0x10,
- NUM_RA_PARA
-};
-
-enum phydm_wireless_mode {
- PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
- PHYDM_WIRELESS_MODE_A = 0x01,
- PHYDM_WIRELESS_MODE_B = 0x02,
- PHYDM_WIRELESS_MODE_G = 0x04,
- PHYDM_WIRELESS_MODE_AUTO = 0x08,
- PHYDM_WIRELESS_MODE_N_24G = 0x10,
- PHYDM_WIRELESS_MODE_N_5G = 0x20,
- PHYDM_WIRELESS_MODE_AC_5G = 0x40,
- PHYDM_WIRELESS_MODE_AC_24G = 0x80,
- PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
- PHYDM_WIRELESS_MODE_MAX = 0x800,
- PHYDM_WIRELESS_MODE_ALL = 0xFFFF
-};
-
-enum phydm_rateid_idx {
- PHYDM_BGN_40M_2SS = 0,
- PHYDM_BGN_40M_1SS = 1,
- PHYDM_BGN_20M_2SS = 2,
- PHYDM_BGN_20M_1SS = 3,
- PHYDM_GN_N2SS = 4,
- PHYDM_GN_N1SS = 5,
- PHYDM_BG = 6,
- PHYDM_G = 7,
- PHYDM_B_20M = 8,
- PHYDM_ARFR0_AC_2SS = 9,
- PHYDM_ARFR1_AC_1SS = 10,
- PHYDM_ARFR2_AC_2G_1SS = 11,
- PHYDM_ARFR3_AC_2G_2SS = 12,
- PHYDM_ARFR4_AC_3SS = 13,
- PHYDM_ARFR5_N_3SS = 14
-};
-
-enum phydm_rf_type_def {
- PHYDM_RF_1T1R = 0,
- PHYDM_RF_1T2R,
- PHYDM_RF_2T2R,
- PHYDM_RF_2T2R_GREEN,
- PHYDM_RF_2T3R,
- PHYDM_RF_2T4R,
- PHYDM_RF_3T3R,
- PHYDM_RF_3T4R,
- PHYDM_RF_4T4R,
- PHYDM_RF_MAX_TYPE
-};
-
-enum phydm_bw {
- PHYDM_BW_20 = 0,
- PHYDM_BW_40,
- PHYDM_BW_80,
- PHYDM_BW_80_80,
- PHYDM_BW_160,
- PHYDM_BW_10,
- PHYDM_BW_5
-};
-
-struct ra_table {
- u8 firstconnect;
-
- u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
- u8 highest_client_tx_order;
- u16 highest_client_tx_rate_order;
- u8 power_tracking_flag;
- u8 RA_threshold_offset;
- u8 RA_offset_direction;
- u8 force_update_ra_mask_count;
-};
-
-struct odm_rate_adaptive {
- /* dm_type_by_fw/dm_type_by_driver */
- u8 type;
- /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */
- u8 high_rssi_thresh;
- /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */
- u8 low_rssi_thresh;
- /* Cur RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW*/
- u8 ratr_state;
-
- /* if RSSI > ldpc_thres => switch from LPDC to BCC */
- u8 ldpc_thres;
- bool is_lower_rts_rate;
-
- bool is_use_ldpc;
-};
-
-void phydm_h2C_debug(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len);
-
-void phydm_RA_debug_PCR(void *dm_void, u32 *const dm_value, u32 *_used,
- char *output, u32 *_out_len);
-
-void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-
-void odm_ra_para_adjust(void *dm_void);
-
-void phydm_ra_dynamic_retry_count(void *dm_void);
-
-void phydm_ra_dynamic_retry_limit(void *dm_void);
-
-void phydm_ra_dynamic_rate_id_on_assoc(void *dm_void, u8 wireless_mode,
- u8 init_rate_id);
-
-void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
-
-void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-
-u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
-
-void phydm_ra_info_watchdog(void *dm_void);
-
-void phydm_ra_info_init(void *dm_void);
-
-void odm_rssi_monitor_init(void *dm_void);
-
-void phydm_modify_RA_PCR_threshold(void *dm_void, u8 RA_offset_direction,
- u8 RA_threshold_offset);
-
-void odm_rssi_monitor_check(void *dm_void);
-
-void phydm_init_ra_info(void *dm_void);
-
-u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);
-
-u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);
-
-void phydm_update_hal_ra_mask(void *dm_void, u32 wireless_mode, u8 rf_type,
- u8 BW, u8 mimo_ps_enable, u8 disable_cck_rate,
- u32 *ratr_bitmap_msb_in, u32 *ratr_bitmap_in,
- u8 tx_rate_level);
-
-void odm_rate_adaptive_mask_init(void *dm_void);
-
-void odm_refresh_rate_adaptive_mask(void *dm_void);
-
-void odm_refresh_rate_adaptive_mask_mp(void *dm_void);
-
-void odm_refresh_rate_adaptive_mask_ce(void *dm_void);
-
-void odm_refresh_rate_adaptive_mask_apadsl(void *dm_void);
-
-u8 phydm_RA_level_decision(void *dm_void, u32 rssi, u8 ratr_state);
-
-bool odm_ra_state_check(void *dm_void, s32 RSSI, bool is_force_update,
- u8 *ra_tr_state);
-
-void odm_refresh_basic_rate_mask(void *dm_void);
-void odm_ra_post_action_on_assoc(void *dm);
-
-u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, bool is_erp_protect);
-
-void odm_update_noisy_state(void *dm_void, bool is_noisy_state_from_c2h);
-
-void phydm_update_pwr_track(void *dm_void, u8 rate);
-
-#endif /*#ifndef __ODMRAINFO_H__*/
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __ODM_REGDEFINE11AC_H__
-#define __ODM_REGDEFINE11AC_H__
-
-/* 2 RF REG LIST */
-
-/* 2 BB REG LIST */
-/* PAGE 8 */
-#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
-#define ODM_REG_BB_RX_PATH_11AC 0x808
-#define ODM_REG_BB_TX_PATH_11AC 0x80c
-#define ODM_REG_BB_ATC_11AC 0x860
-#define ODM_REG_EDCCA_POWER_CAL 0x8dc
-#define ODM_REG_DBG_RPT_11AC 0x8fc
-/* PAGE 9 */
-#define ODM_REG_EDCCA_DOWN_OPT 0x900
-#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
-#define odm_adc_trigger_jaguar2 0x95C /*ADC sample mode*/
-#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
-#define ODM_REG_CCX_PERIOD_11AC 0x990
-#define ODM_REG_NHM_TH9_TH10_11AC 0x994
-#define ODM_REG_CLM_11AC 0x994
-#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
-#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
-#define ODM_REG_NHM_TH8_11AC 0x9a0
-#define ODM_REG_NHM_9E8_11AC 0x9e8
-#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
-/* PAGE A */
-#define ODM_REG_CCK_CCA_11AC 0xA0A
-#define ODM_REG_CCK_FA_RST_11AC 0xA2C
-#define ODM_REG_CCK_FA_11AC 0xA5C
-/* PAGE B */
-#define ODM_REG_RST_RPT_11AC 0xB58
-/* PAGE C */
-#define ODM_REG_TRMUX_11AC 0xC08
-#define ODM_REG_IGI_A_11AC 0xC50
-/* PAGE E */
-#define ODM_REG_IGI_B_11AC 0xE50
-#define ODM_REG_TRMUX_11AC_B 0xE08
-/* PAGE F */
-#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04
-#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
-#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c
-#define ODM_REG_HT_CRC32_CNT_11AC 0xF10
-#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14
-#define ODM_REG_OFDM_FA_11AC 0xF48
-#define ODM_REG_RPT_11AC 0xfa0
-#define ODM_REG_CLM_RESULT_11AC 0xfa4
-#define ODM_REG_NHM_CNT_11AC 0xfa8
-#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
-
-#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
-#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
-#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
-/* PAGE 18 */
-#define ODM_REG_IGI_C_11AC 0x1850
-/* PAGE 1A */
-#define ODM_REG_IGI_D_11AC 0x1A50
-
-/* 2 MAC REG LIST */
-#define ODM_REG_RESP_TX_11AC 0x6D8
-
-/* DIG Related */
-#define ODM_BIT_IGI_11AC 0xFFFFFFFF
-#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16)
-#define ODM_BIT_BB_RX_PATH_11AC 0xF
-#define ODM_BIT_BB_TX_PATH_11AC 0xF
-#define ODM_BIT_BB_ATC_11AC BIT(14)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __ODM_TYPES_H__
-#define __ODM_TYPES_H__
-
-/*Define Different SW team support*/
-#define ODM_AP 0x01 /*BIT0*/
-#define ODM_CE 0x04 /*BIT2*/
-#define ODM_WIN 0x08 /*BIT3*/
-#define ODM_ADSL 0x10 /*BIT4*/
-#define ODM_IOT 0x20 /*BIT5*/
-
-/*Deifne HW endian support*/
-#define ODM_ENDIAN_BIG 0
-#define ODM_ENDIAN_LITTLE 1
-
-#define GET_PDM_ODM(__padapter) \
- ((struct phy_dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv))
-
-enum hal_status {
- HAL_STATUS_SUCCESS,
- HAL_STATUS_FAILURE,
-};
-
-/*
- * Declare for ODM spin lock definition temporarily fro compile pass.
- */
-enum rt_spinlock_type {
- RT_TX_SPINLOCK = 1,
- RT_RX_SPINLOCK = 2,
- RT_RM_SPINLOCK = 3,
- RT_CAM_SPINLOCK = 4,
- RT_SCAN_SPINLOCK = 5,
- RT_LOG_SPINLOCK = 7,
- RT_BW_SPINLOCK = 8,
- RT_CHNLOP_SPINLOCK = 9,
- RT_RF_OPERATE_SPINLOCK = 10,
- RT_INITIAL_SPINLOCK = 11,
- RT_RF_STATE_SPINLOCK =
- 12, /* For RF state. Added by Bruce, 2007-10-30. */
- /* Shall we define Ndis 6.2 SpinLock Here ? */
- RT_PORT_SPINLOCK = 16,
- RT_VNIC_SPINLOCK = 17,
- RT_HVL_SPINLOCK = 18,
- RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */
-
- rt_bt_data_spinlock = 25,
-
- RT_WAPI_OPTION_SPINLOCK = 26,
- RT_WAPI_RX_SPINLOCK = 27,
-
- /* add for 92D CCK control issue */
- RT_CCK_PAGEA_SPINLOCK = 28,
- RT_BUFFER_SPINLOCK = 29,
- RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
- RT_GEN_TEMP_BUF_SPINLOCK = 31,
- RT_AWB_SPINLOCK = 32,
- RT_FW_PS_SPINLOCK = 33,
- RT_HW_TIMER_SPIN_LOCK = 34,
- RT_MPT_WI_SPINLOCK = 35,
- RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */
- RT_DBG_SPIN_LOCK = 37,
- RT_IQK_SPINLOCK = 38,
- RT_PENDED_OID_SPINLOCK = 39,
- RT_CHNLLIST_SPINLOCK = 40,
- RT_INDIC_SPINLOCK = 41, /* protect indication */
- RT_RFD_SPINLOCK = 42,
- RT_SYNC_IO_CNT_SPINLOCK = 43,
- RT_LAST_SPINLOCK,
-};
-
-#include <asm/byteorder.h>
-
-#if defined(__LITTLE_ENDIAN)
-#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
-#elif defined(__BIG_ENDIAN)
-#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
-#else
-#error
-#endif
-
-#define COND_ELSE 2
-#define COND_ENDIF 3
-
-#define MASKBYTE0 0xff
-#define MASKBYTE1 0xff00
-#define MASKBYTE2 0xff0000
-#define MASKBYTE3 0xff000000
-#define MASKHWORD 0xffff0000
-#define MASKLWORD 0x0000ffff
-#define MASKDWORD 0xffffffff
-#define MASK7BITS 0x7f
-#define MASK12BITS 0xfff
-#define MASKH4BITS 0xf0000000
-#define MASK20BITS 0xfffff
-#define MASKOFDM_D 0xffc00000
-#define MASKCCK 0x3f3f3f3f
-#define RFREGOFFSETMASK 0xfffff
-#define MASKH3BYTES 0xffffff00
-#define MASKL3BYTES 0x00ffffff
-#define MASKBYTE2HIGHNIBBLE 0x00f00000
-#define MASKBYTE3LOWNIBBLE 0x0f000000
-#define MASKL3BYTES 0x00ffffff
-#define RFREGOFFSETMASK 0xfffff
-
-#include "phydm_features.h"
-
-#endif /* __ODM_TYPES_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/*Image2HeaderVersion: 3.2*/
-#include "../mp_precomp.h"
-#include "../phydm_precomp.h"
-#include <linux/kernel.h>
-
-static bool check_positive(struct phy_dm_struct *dm, const u32 condition1,
- const u32 condition2, const u32 condition3,
- const u32 condition4)
-{
- u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
- ((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
- ((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
- ((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
- ((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
-
- u32 cond1 = condition1, cond2 = condition2, cond3 = condition3,
- cond4 = condition4;
-
- u8 cut_version_for_para =
- (dm->cut_version == ODM_CUT_A) ? 14 : dm->cut_version;
- u8 pkg_type_for_para = (dm->package_type == 0) ? 14 : dm->package_type;
-
- u32 driver1 = cut_version_for_para << 24 |
- (dm->support_interface & 0xF0) << 16 |
- dm->support_platform << 16 | pkg_type_for_para << 12 |
- (dm->support_interface & 0x0F) << 8 | _board_type;
-
- u32 driver2 = (dm->type_glna & 0xFF) << 0 | (dm->type_gpa & 0xFF) << 8 |
- (dm->type_alna & 0xFF) << 16 |
- (dm->type_apa & 0xFF) << 24;
-
- u32 driver3 = 0;
-
- u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | (dm->type_gpa & 0xFF00) |
- (dm->type_alna & 0xFF00) << 8 |
- (dm->type_apa & 0xFF00) << 16;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
- __func__, cond1, cond2, cond3, cond4);
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
- __func__, driver1, driver2, driver3, driver4);
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- " (Platform, Interface) = (0x%X, 0x%X)\n",
- dm->support_platform, dm->support_interface);
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- " (Board, Package) = (0x%X, 0x%X)\n",
- dm->board_type, dm->package_type);
-
- /*============== value Defined Check ===============*/
- /*QFN type [15:12] and cut version [27:24] need to do value check*/
-
- if (((cond1 & 0x0000F000) != 0) &&
- ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
- return false;
- if (((cond1 & 0x0F000000) != 0) &&
- ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
- return false;
-
- /*=============== Bit Defined Check ================*/
- /* We don't care [31:28] */
-
- cond1 &= 0x00FF0FFF;
- driver1 &= 0x00FF0FFF;
-
- if ((cond1 & driver1) == cond1) {
- u32 bit_mask = 0;
-
- if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
- return true;
-
- if ((cond1 & BIT(0)) != 0) /*GLNA*/
- bit_mask |= 0x000000FF;
- if ((cond1 & BIT(1)) != 0) /*GPA*/
- bit_mask |= 0x0000FF00;
- if ((cond1 & BIT(2)) != 0) /*ALNA*/
- bit_mask |= 0x00FF0000;
- if ((cond1 & BIT(3)) != 0) /*APA*/
- bit_mask |= 0xFF000000;
-
- if (((cond2 & bit_mask) == (driver2 & bit_mask)) &&
- ((cond4 & bit_mask) ==
- (driver4 &
- bit_mask))) /* board_type of each RF path is matched*/
- return true;
- else
- return false;
- } else {
- return false;
- }
-}
-
-/******************************************************************************
- * agc_tab.TXT
- ******************************************************************************/
-
-static u32 array_mp_8822b_agc_tab[] = {
- 0x8000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x81C, 0xFF000003,
- 0x81C, 0xF5000003, 0x81C, 0xF4020003, 0x81C, 0xF3040003,
- 0x81C, 0xF2060003, 0x81C, 0xF1080003, 0x81C, 0xF00A0003,
- 0x81C, 0xEF0C0003, 0x81C, 0xEE0E0003, 0x81C, 0xED100003,
- 0x81C, 0xEC120003, 0x81C, 0xEB140003, 0x81C, 0xEA160003,
- 0x81C, 0xE9180003, 0x81C, 0xE81A0003, 0x81C, 0xE71C0003,
- 0x81C, 0xE61E0003, 0x81C, 0xE5200003, 0x81C, 0xE4220003,
- 0x81C, 0xE3240003, 0x81C, 0xE2260003, 0x81C, 0xE1280003,
- 0x81C, 0xE02A0003, 0x81C, 0xC32C0003, 0x81C, 0xC22E0003,
- 0x81C, 0xC1300003, 0x81C, 0xC0320003, 0x81C, 0xA4340003,
- 0x81C, 0xA3360003, 0x81C, 0xA2380003, 0x81C, 0xA13A0003,
- 0x81C, 0xA03C0003, 0x81C, 0x823E0003, 0x81C, 0x81400003,
- 0x81C, 0x80420003, 0x81C, 0x64440003, 0x81C, 0x63460003,
- 0x81C, 0x62480003, 0x81C, 0x614A0003, 0x81C, 0x604C0003,
- 0x81C, 0x454E0003, 0x81C, 0x44500003, 0x81C, 0x43520003,
- 0x81C, 0x42540003, 0x81C, 0x41560003, 0x81C, 0x40580003,
- 0x81C, 0x055A0003, 0x81C, 0x045C0003, 0x81C, 0x035E0003,
- 0x81C, 0x02600003, 0x81C, 0x01620003, 0x81C, 0x00640003,
- 0x81C, 0x00660003, 0x81C, 0x00680003, 0x81C, 0x006A0003,
- 0x81C, 0x006C0003, 0x81C, 0x006E0003, 0x81C, 0x00700003,
- 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
- 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
- 0x81C, 0x007E0003, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x81C, 0xFF000003, 0x81C, 0xF5000003, 0x81C, 0xF4020003,
- 0x81C, 0xF3040003, 0x81C, 0xF2060003, 0x81C, 0xF1080003,
- 0x81C, 0xF00A0003, 0x81C, 0xEF0C0003, 0x81C, 0xEE0E0003,
- 0x81C, 0xED100003, 0x81C, 0xEC120003, 0x81C, 0xEB140003,
- 0x81C, 0xEA160003, 0x81C, 0xE9180003, 0x81C, 0xE81A0003,
- 0x81C, 0xE71C0003, 0x81C, 0xE61E0003, 0x81C, 0xE5200003,
- 0x81C, 0xE4220003, 0x81C, 0xE3240003, 0x81C, 0xE2260003,
- 0x81C, 0xE1280003, 0x81C, 0xE02A0003, 0x81C, 0xC32C0003,
- 0x81C, 0xC22E0003, 0x81C, 0xC1300003, 0x81C, 0xC0320003,
- 0x81C, 0xA4340003, 0x81C, 0xA3360003, 0x81C, 0xA2380003,
- 0x81C, 0xA13A0003, 0x81C, 0xA03C0003, 0x81C, 0x823E0003,
- 0x81C, 0x81400003, 0x81C, 0x80420003, 0x81C, 0x64440003,
- 0x81C, 0x63460003, 0x81C, 0x62480003, 0x81C, 0x614A0003,
- 0x81C, 0x604C0003, 0x81C, 0x454E0003, 0x81C, 0x44500003,
- 0x81C, 0x43520003, 0x81C, 0x42540003, 0x81C, 0x41560003,
- 0x81C, 0x40580003, 0x81C, 0x055A0003, 0x81C, 0x045C0003,
- 0x81C, 0x035E0003, 0x81C, 0x02600003, 0x81C, 0x01620003,
- 0x81C, 0x00640003, 0x81C, 0x00660003, 0x81C, 0x00680003,
- 0x81C, 0x006A0003, 0x81C, 0x006C0003, 0x81C, 0x006E0003,
- 0x81C, 0x00700003, 0x81C, 0x00720003, 0x81C, 0x00740003,
- 0x81C, 0x00760003, 0x81C, 0x00780003, 0x81C, 0x007A0003,
- 0x81C, 0x007C0003, 0x81C, 0x007E0003, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xF5000003,
- 0x81C, 0xF4020003, 0x81C, 0xF3040003, 0x81C, 0xF2060003,
- 0x81C, 0xF1080003, 0x81C, 0xF00A0003, 0x81C, 0xEF0C0003,
- 0x81C, 0xEE0E0003, 0x81C, 0xED100003, 0x81C, 0xEC120003,
- 0x81C, 0xEB140003, 0x81C, 0xEA160003, 0x81C, 0xE9180003,
- 0x81C, 0xE81A0003, 0x81C, 0xE71C0003, 0x81C, 0xE61E0003,
- 0x81C, 0xE5200003, 0x81C, 0xE4220003, 0x81C, 0xE3240003,
- 0x81C, 0xE2260003, 0x81C, 0xE1280003, 0x81C, 0xE02A0003,
- 0x81C, 0xC32C0003, 0x81C, 0xC22E0003, 0x81C, 0xC1300003,
- 0x81C, 0xC0320003, 0x81C, 0xA4340003, 0x81C, 0xA3360003,
- 0x81C, 0xA2380003, 0x81C, 0xA13A0003, 0x81C, 0xA03C0003,
- 0x81C, 0x823E0003, 0x81C, 0x81400003, 0x81C, 0x80420003,
- 0x81C, 0x64440003, 0x81C, 0x63460003, 0x81C, 0x62480003,
- 0x81C, 0x614A0003, 0x81C, 0x604C0003, 0x81C, 0x454E0003,
- 0x81C, 0x44500003, 0x81C, 0x43520003, 0x81C, 0x42540003,
- 0x81C, 0x41560003, 0x81C, 0x40580003, 0x81C, 0x055A0003,
- 0x81C, 0x045C0003, 0x81C, 0x035E0003, 0x81C, 0x02600003,
- 0x81C, 0x01620003, 0x81C, 0x00640003, 0x81C, 0x00660003,
- 0x81C, 0x00680003, 0x81C, 0x006A0003, 0x81C, 0x006C0003,
- 0x81C, 0x006E0003, 0x81C, 0x00700003, 0x81C, 0x00720003,
- 0x81C, 0x00740003, 0x81C, 0x00760003, 0x81C, 0x00780003,
- 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003,
- 0x81C, 0xF5000003, 0x81C, 0xF4020003, 0x81C, 0xF3040003,
- 0x81C, 0xF2060003, 0x81C, 0xF1080003, 0x81C, 0xF00A0003,
- 0x81C, 0xEF0C0003, 0x81C, 0xEE0E0003, 0x81C, 0xED100003,
- 0x81C, 0xEC120003, 0x81C, 0xEB140003, 0x81C, 0xEA160003,
- 0x81C, 0xE9180003, 0x81C, 0xE81A0003, 0x81C, 0xE71C0003,
- 0x81C, 0xE61E0003, 0x81C, 0xE5200003, 0x81C, 0xE4220003,
- 0x81C, 0xE3240003, 0x81C, 0xE2260003, 0x81C, 0xE1280003,
- 0x81C, 0xE02A0003, 0x81C, 0xC32C0003, 0x81C, 0xC22E0003,
- 0x81C, 0xC1300003, 0x81C, 0xC0320003, 0x81C, 0xA4340003,
- 0x81C, 0xA3360003, 0x81C, 0xA2380003, 0x81C, 0xA13A0003,
- 0x81C, 0xA03C0003, 0x81C, 0x823E0003, 0x81C, 0x81400003,
- 0x81C, 0x80420003, 0x81C, 0x64440003, 0x81C, 0x63460003,
- 0x81C, 0x62480003, 0x81C, 0x614A0003, 0x81C, 0x604C0003,
- 0x81C, 0x454E0003, 0x81C, 0x44500003, 0x81C, 0x43520003,
- 0x81C, 0x42540003, 0x81C, 0x41560003, 0x81C, 0x40580003,
- 0x81C, 0x055A0003, 0x81C, 0x045C0003, 0x81C, 0x035E0003,
- 0x81C, 0x02600003, 0x81C, 0x01620003, 0x81C, 0x00640003,
- 0x81C, 0x00660003, 0x81C, 0x00680003, 0x81C, 0x006A0003,
- 0x81C, 0x006C0003, 0x81C, 0x006E0003, 0x81C, 0x00700003,
- 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
- 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
- 0x81C, 0x007E0003, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
- 0x81C, 0xFF000003, 0x81C, 0xFD000003, 0x81C, 0xFC020003,
- 0x81C, 0xFB040003, 0x81C, 0xFA060003, 0x81C, 0xF9080003,
- 0x81C, 0xF80A0003, 0x81C, 0xF70C0003, 0x81C, 0xF60E0003,
- 0x81C, 0xF5100003, 0x81C, 0xF4120003, 0x81C, 0xF3140003,
- 0x81C, 0xF2160003, 0x81C, 0xF1180003, 0x81C, 0xF01A0003,
- 0x81C, 0xEF1C0003, 0x81C, 0xEE1E0003, 0x81C, 0xED200003,
- 0x81C, 0xEC220003, 0x81C, 0xEB240003, 0x81C, 0xEA260003,
- 0x81C, 0xE9280003, 0x81C, 0xE82A0003, 0x81C, 0xE72C0003,
- 0x81C, 0xE62E0003, 0x81C, 0xE5300003, 0x81C, 0xC8320003,
- 0x81C, 0xC7340003, 0x81C, 0xC6360003, 0x81C, 0xC5380003,
- 0x81C, 0xC43A0003, 0x81C, 0xC33C0003, 0x81C, 0xC23E0003,
- 0x81C, 0xC1400003, 0x81C, 0xC0420003, 0x81C, 0xA5440003,
- 0x81C, 0xA4460003, 0x81C, 0xA3480003, 0x81C, 0xA24A0003,
- 0x81C, 0xA14C0003, 0x81C, 0x834E0003, 0x81C, 0x82500003,
- 0x81C, 0x81520003, 0x81C, 0x80540003, 0x81C, 0x65560003,
- 0x81C, 0x64580003, 0x81C, 0x635A0003, 0x81C, 0x625C0003,
- 0x81C, 0x435E0003, 0x81C, 0x42600003, 0x81C, 0x41620003,
- 0x81C, 0x40640003, 0x81C, 0x06660003, 0x81C, 0x05680003,
- 0x81C, 0x046A0003, 0x81C, 0x036C0003, 0x81C, 0x026E0003,
- 0x81C, 0x01700003, 0x81C, 0x00720003, 0x81C, 0x00740003,
- 0x81C, 0x00760003, 0x81C, 0x00780003, 0x81C, 0x007A0003,
- 0x81C, 0x007C0003, 0x81C, 0x007E0003, 0x90012100, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xFE000003,
- 0x81C, 0xFD020003, 0x81C, 0xFC040003, 0x81C, 0xFB060003,
- 0x81C, 0xFA080003, 0x81C, 0xF90A0003, 0x81C, 0xF80C0003,
- 0x81C, 0xF70E0003, 0x81C, 0xF6100003, 0x81C, 0xF5120003,
- 0x81C, 0xF4140003, 0x81C, 0xF3160003, 0x81C, 0xF2180003,
- 0x81C, 0xF11A0003, 0x81C, 0xF01C0003, 0x81C, 0xEF1E0003,
- 0x81C, 0xEE200003, 0x81C, 0xED220003, 0x81C, 0xEC240003,
- 0x81C, 0xEB260003, 0x81C, 0xEA280003, 0x81C, 0xE92A0003,
- 0x81C, 0xE82C0003, 0x81C, 0xE72E0003, 0x81C, 0xE6300003,
- 0x81C, 0xE5320003, 0x81C, 0xC8340003, 0x81C, 0xC7360003,
- 0x81C, 0xC6380003, 0x81C, 0xC53A0003, 0x81C, 0xC43C0003,
- 0x81C, 0xC33E0003, 0x81C, 0xC2400003, 0x81C, 0xC1420003,
- 0x81C, 0xC0440003, 0x81C, 0xA3460003, 0x81C, 0xA2480003,
- 0x81C, 0xA14A0003, 0x81C, 0xA04C0003, 0x81C, 0x824E0003,
- 0x81C, 0x81500003, 0x81C, 0x80520003, 0x81C, 0x64540003,
- 0x81C, 0x63560003, 0x81C, 0x62580003, 0x81C, 0x445A0003,
- 0x81C, 0x435C0003, 0x81C, 0x425E0003, 0x81C, 0x41600003,
- 0x81C, 0x40620003, 0x81C, 0x05640003, 0x81C, 0x04660003,
- 0x81C, 0x03680003, 0x81C, 0x026A0003, 0x81C, 0x016C0003,
- 0x81C, 0x006E0003, 0x81C, 0x00700003, 0x81C, 0x00720003,
- 0x81C, 0x00740003, 0x81C, 0x00760003, 0x81C, 0x00780003,
- 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003,
- 0x81C, 0xF5000003, 0x81C, 0xF4020003, 0x81C, 0xF3040003,
- 0x81C, 0xF2060003, 0x81C, 0xF1080003, 0x81C, 0xF00A0003,
- 0x81C, 0xEF0C0003, 0x81C, 0xEE0E0003, 0x81C, 0xED100003,
- 0x81C, 0xEC120003, 0x81C, 0xEB140003, 0x81C, 0xEA160003,
- 0x81C, 0xE9180003, 0x81C, 0xE81A0003, 0x81C, 0xE71C0003,
- 0x81C, 0xE61E0003, 0x81C, 0xE5200003, 0x81C, 0xE4220003,
- 0x81C, 0xE3240003, 0x81C, 0xE2260003, 0x81C, 0xE1280003,
- 0x81C, 0xE02A0003, 0x81C, 0xC32C0003, 0x81C, 0xC22E0003,
- 0x81C, 0xC1300003, 0x81C, 0xC0320003, 0x81C, 0xA4340003,
- 0x81C, 0xA3360003, 0x81C, 0xA2380003, 0x81C, 0xA13A0003,
- 0x81C, 0xA03C0003, 0x81C, 0x823E0003, 0x81C, 0x81400003,
- 0x81C, 0x80420003, 0x81C, 0x64440003, 0x81C, 0x63460003,
- 0x81C, 0x62480003, 0x81C, 0x614A0003, 0x81C, 0x604C0003,
- 0x81C, 0x454E0003, 0x81C, 0x44500003, 0x81C, 0x43520003,
- 0x81C, 0x42540003, 0x81C, 0x41560003, 0x81C, 0x40580003,
- 0x81C, 0x055A0003, 0x81C, 0x045C0003, 0x81C, 0x035E0003,
- 0x81C, 0x02600003, 0x81C, 0x01620003, 0x81C, 0x00640003,
- 0x81C, 0x00660003, 0x81C, 0x00680003, 0x81C, 0x006A0003,
- 0x81C, 0x006C0003, 0x81C, 0x006E0003, 0x81C, 0x00700003,
- 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
- 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
- 0x81C, 0x007E0003, 0x90011000, 0x00000000, 0x40000000, 0x00000000,
- 0x81C, 0xFF000003, 0x81C, 0xFE000003, 0x81C, 0xFD020003,
- 0x81C, 0xFC040003, 0x81C, 0xFB060003, 0x81C, 0xFA080003,
- 0x81C, 0xF90A0003, 0x81C, 0xF80C0003, 0x81C, 0xF70E0003,
- 0x81C, 0xF6100003, 0x81C, 0xF5120003, 0x81C, 0xF4140003,
- 0x81C, 0xF3160003, 0x81C, 0xF2180003, 0x81C, 0xF11A0003,
- 0x81C, 0xF01C0003, 0x81C, 0xEF1E0003, 0x81C, 0xEE200003,
- 0x81C, 0xED220003, 0x81C, 0xEC240003, 0x81C, 0xEB260003,
- 0x81C, 0xEA280003, 0x81C, 0xE92A0003, 0x81C, 0xE82C0003,
- 0x81C, 0xE72E0003, 0x81C, 0xE6300003, 0x81C, 0xE5320003,
- 0x81C, 0xC8340003, 0x81C, 0xC7360003, 0x81C, 0xC6380003,
- 0x81C, 0xC53A0003, 0x81C, 0xC43C0003, 0x81C, 0xC33E0003,
- 0x81C, 0xC2400003, 0x81C, 0xC1420003, 0x81C, 0xC0440003,
- 0x81C, 0xA3460003, 0x81C, 0xA2480003, 0x81C, 0xA14A0003,
- 0x81C, 0xA04C0003, 0x81C, 0x824E0003, 0x81C, 0x81500003,
- 0x81C, 0x80520003, 0x81C, 0x64540003, 0x81C, 0x63560003,
- 0x81C, 0x62580003, 0x81C, 0x445A0003, 0x81C, 0x435C0003,
- 0x81C, 0x425E0003, 0x81C, 0x41600003, 0x81C, 0x40620003,
- 0x81C, 0x05640003, 0x81C, 0x04660003, 0x81C, 0x03680003,
- 0x81C, 0x026A0003, 0x81C, 0x016C0003, 0x81C, 0x006E0003,
- 0x81C, 0x00700003, 0x81C, 0x00720003, 0x81C, 0x00740003,
- 0x81C, 0x00760003, 0x81C, 0x00780003, 0x81C, 0x007A0003,
- 0x81C, 0x007C0003, 0x81C, 0x007E0003, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFF000003, 0x81C, 0xFD000003,
- 0x81C, 0xFC020003, 0x81C, 0xFB040003, 0x81C, 0xFA060003,
- 0x81C, 0xF9080003, 0x81C, 0xF80A0003, 0x81C, 0xF70C0003,
- 0x81C, 0xF60E0003, 0x81C, 0xF5100003, 0x81C, 0xF4120003,
- 0x81C, 0xF3140003, 0x81C, 0xF2160003, 0x81C, 0xF1180003,
- 0x81C, 0xF01A0003, 0x81C, 0xEF1C0003, 0x81C, 0xEE1E0003,
- 0x81C, 0xED200003, 0x81C, 0xEC220003, 0x81C, 0xEB240003,
- 0x81C, 0xEA260003, 0x81C, 0xE9280003, 0x81C, 0xE82A0003,
- 0x81C, 0xE72C0003, 0x81C, 0xE62E0003, 0x81C, 0xE5300003,
- 0x81C, 0xC8320003, 0x81C, 0xC7340003, 0x81C, 0xC6360003,
- 0x81C, 0xC5380003, 0x81C, 0xC43A0003, 0x81C, 0xC33C0003,
- 0x81C, 0xC23E0003, 0x81C, 0xC1400003, 0x81C, 0xC0420003,
- 0x81C, 0xA5440003, 0x81C, 0xA4460003, 0x81C, 0xA3480003,
- 0x81C, 0xA24A0003, 0x81C, 0xA14C0003, 0x81C, 0x834E0003,
- 0x81C, 0x82500003, 0x81C, 0x81520003, 0x81C, 0x80540003,
- 0x81C, 0x65560003, 0x81C, 0x64580003, 0x81C, 0x635A0003,
- 0x81C, 0x625C0003, 0x81C, 0x435E0003, 0x81C, 0x42600003,
- 0x81C, 0x41620003, 0x81C, 0x40640003, 0x81C, 0x06660003,
- 0x81C, 0x05680003, 0x81C, 0x046A0003, 0x81C, 0x036C0003,
- 0x81C, 0x026E0003, 0x81C, 0x01700003, 0x81C, 0x00720003,
- 0x81C, 0x00740003, 0x81C, 0x00760003, 0x81C, 0x00780003,
- 0x81C, 0x007A0003, 0x81C, 0x007C0003, 0x81C, 0x007E0003,
- 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000003,
- 0x81C, 0xFD000003, 0x81C, 0xFC020003, 0x81C, 0xFB040003,
- 0x81C, 0xFA060003, 0x81C, 0xF9080003, 0x81C, 0xF80A0003,
- 0x81C, 0xF70C0003, 0x81C, 0xF60E0003, 0x81C, 0xF5100003,
- 0x81C, 0xF4120003, 0x81C, 0xF3140003, 0x81C, 0xF2160003,
- 0x81C, 0xF1180003, 0x81C, 0xF01A0003, 0x81C, 0xEF1C0003,
- 0x81C, 0xEE1E0003, 0x81C, 0xED200003, 0x81C, 0xEC220003,
- 0x81C, 0xEB240003, 0x81C, 0xEA260003, 0x81C, 0xE9280003,
- 0x81C, 0xE82A0003, 0x81C, 0xE72C0003, 0x81C, 0xE62E0003,
- 0x81C, 0xE5300003, 0x81C, 0xC8320003, 0x81C, 0xC7340003,
- 0x81C, 0xC6360003, 0x81C, 0xC5380003, 0x81C, 0xC43A0003,
- 0x81C, 0xC33C0003, 0x81C, 0xC23E0003, 0x81C, 0xC1400003,
- 0x81C, 0xC0420003, 0x81C, 0xA5440003, 0x81C, 0xA4460003,
- 0x81C, 0xA3480003, 0x81C, 0xA24A0003, 0x81C, 0xA14C0003,
- 0x81C, 0x834E0003, 0x81C, 0x82500003, 0x81C, 0x81520003,
- 0x81C, 0x80540003, 0x81C, 0x65560003, 0x81C, 0x64580003,
- 0x81C, 0x635A0003, 0x81C, 0x625C0003, 0x81C, 0x435E0003,
- 0x81C, 0x42600003, 0x81C, 0x41620003, 0x81C, 0x40640003,
- 0x81C, 0x06660003, 0x81C, 0x05680003, 0x81C, 0x046A0003,
- 0x81C, 0x036C0003, 0x81C, 0x026E0003, 0x81C, 0x01700003,
- 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
- 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
- 0x81C, 0x007E0003, 0xA0000000, 0x00000000, 0x81C, 0xFF000003,
- 0x81C, 0xFE000003, 0x81C, 0xFD020003, 0x81C, 0xFC040003,
- 0x81C, 0xFB060003, 0x81C, 0xFA080003, 0x81C, 0xF90A0003,
- 0x81C, 0xF80C0003, 0x81C, 0xF70E0003, 0x81C, 0xF6100003,
- 0x81C, 0xF5120003, 0x81C, 0xF4140003, 0x81C, 0xF3160003,
- 0x81C, 0xF2180003, 0x81C, 0xF11A0003, 0x81C, 0xF01C0003,
- 0x81C, 0xEF1E0003, 0x81C, 0xEE200003, 0x81C, 0xED220003,
- 0x81C, 0xEC240003, 0x81C, 0xEB260003, 0x81C, 0xEA280003,
- 0x81C, 0xE92A0003, 0x81C, 0xE82C0003, 0x81C, 0xE72E0003,
- 0x81C, 0xE6300003, 0x81C, 0xE5320003, 0x81C, 0xC8340003,
- 0x81C, 0xC7360003, 0x81C, 0xC6380003, 0x81C, 0xC53A0003,
- 0x81C, 0xC43C0003, 0x81C, 0xC33E0003, 0x81C, 0xC2400003,
- 0x81C, 0xC1420003, 0x81C, 0xC0440003, 0x81C, 0xA3460003,
- 0x81C, 0xA2480003, 0x81C, 0xA14A0003, 0x81C, 0xA04C0003,
- 0x81C, 0x824E0003, 0x81C, 0x81500003, 0x81C, 0x80520003,
- 0x81C, 0x64540003, 0x81C, 0x63560003, 0x81C, 0x62580003,
- 0x81C, 0x445A0003, 0x81C, 0x435C0003, 0x81C, 0x425E0003,
- 0x81C, 0x41600003, 0x81C, 0x40620003, 0x81C, 0x05640003,
- 0x81C, 0x04660003, 0x81C, 0x03680003, 0x81C, 0x026A0003,
- 0x81C, 0x016C0003, 0x81C, 0x006E0003, 0x81C, 0x00700003,
- 0x81C, 0x00720003, 0x81C, 0x00740003, 0x81C, 0x00760003,
- 0x81C, 0x00780003, 0x81C, 0x007A0003, 0x81C, 0x007C0003,
- 0x81C, 0x007E0003, 0xB0000000, 0x00000000, 0x8000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
- 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
- 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
- 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
- 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
- 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
- 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
- 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xE22C0103,
- 0x81C, 0xC32E0103, 0x81C, 0xC2300103, 0x81C, 0xC1320103,
- 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
- 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
- 0x81C, 0x80400103, 0x81C, 0x64420103, 0x81C, 0x63440103,
- 0x81C, 0x62460103, 0x81C, 0x61480103, 0x81C, 0x434A0103,
- 0x81C, 0x424C0103, 0x81C, 0x414E0103, 0x81C, 0x40500103,
- 0x81C, 0x22520103, 0x81C, 0x21540103, 0x81C, 0x20560103,
- 0x81C, 0x04580103, 0x81C, 0x035A0103, 0x81C, 0x025C0103,
- 0x81C, 0x015E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
- 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x81C, 0xFA000103, 0x81C, 0xF9020103,
- 0x81C, 0xF8040103, 0x81C, 0xF7060103, 0x81C, 0xF6080103,
- 0x81C, 0xF50A0103, 0x81C, 0xF40C0103, 0x81C, 0xF30E0103,
- 0x81C, 0xF2100103, 0x81C, 0xF1120103, 0x81C, 0xF0140103,
- 0x81C, 0xEF160103, 0x81C, 0xEE180103, 0x81C, 0xED1A0103,
- 0x81C, 0xEC1C0103, 0x81C, 0xEB1E0103, 0x81C, 0xEA200103,
- 0x81C, 0xE9220103, 0x81C, 0xE8240103, 0x81C, 0xE7260103,
- 0x81C, 0xE6280103, 0x81C, 0xE52A0103, 0x81C, 0xC42C0103,
- 0x81C, 0xC32E0103, 0x81C, 0xC2300103, 0x81C, 0xC1320103,
- 0x81C, 0xA4340103, 0x81C, 0xA3360103, 0x81C, 0xA2380103,
- 0x81C, 0xA13A0103, 0x81C, 0x833C0103, 0x81C, 0x823E0103,
- 0x81C, 0x81400103, 0x81C, 0x63420103, 0x81C, 0x62440103,
- 0x81C, 0x61460103, 0x81C, 0x60480103, 0x81C, 0x424A0103,
- 0x81C, 0x414C0103, 0x81C, 0x404E0103, 0x81C, 0x22500103,
- 0x81C, 0x21520103, 0x81C, 0x20540103, 0x81C, 0x03560103,
- 0x81C, 0x02580103, 0x81C, 0x015A0103, 0x81C, 0x005C0103,
- 0x81C, 0x005E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
- 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
- 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
- 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
- 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
- 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
- 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
- 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
- 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xC32C0103,
- 0x81C, 0xC22E0103, 0x81C, 0xC1300103, 0x81C, 0xC0320103,
- 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
- 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
- 0x81C, 0x80400103, 0x81C, 0x63420103, 0x81C, 0x62440103,
- 0x81C, 0x61460103, 0x81C, 0x60480103, 0x81C, 0x424A0103,
- 0x81C, 0x414C0103, 0x81C, 0x404E0103, 0x81C, 0x06500103,
- 0x81C, 0x05520103, 0x81C, 0x04540103, 0x81C, 0x03560103,
- 0x81C, 0x02580103, 0x81C, 0x015A0103, 0x81C, 0x005C0103,
- 0x81C, 0x005E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
- 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
- 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
- 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
- 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
- 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
- 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
- 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
- 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xC32C0103,
- 0x81C, 0xC22E0103, 0x81C, 0xC1300103, 0x81C, 0xC0320103,
- 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
- 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
- 0x81C, 0x80400103, 0x81C, 0x63420103, 0x81C, 0x62440103,
- 0x81C, 0x61460103, 0x81C, 0x60480103, 0x81C, 0x424A0103,
- 0x81C, 0x414C0103, 0x81C, 0x404E0103, 0x81C, 0x22500103,
- 0x81C, 0x21520103, 0x81C, 0x20540103, 0x81C, 0x03560103,
- 0x81C, 0x02580103, 0x81C, 0x015A0103, 0x81C, 0x005C0103,
- 0x81C, 0x005E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
- 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
- 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
- 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
- 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
- 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
- 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
- 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
- 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xC32C0103,
- 0x81C, 0xC22E0103, 0x81C, 0xC1300103, 0x81C, 0xC0320103,
- 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
- 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
- 0x81C, 0x80400103, 0x81C, 0x63420103, 0x81C, 0x62440103,
- 0x81C, 0x61460103, 0x81C, 0x60480103, 0x81C, 0x424A0103,
- 0x81C, 0x414C0103, 0x81C, 0x404E0103, 0x81C, 0x22500103,
- 0x81C, 0x21520103, 0x81C, 0x20540103, 0x81C, 0x03560103,
- 0x81C, 0x02580103, 0x81C, 0x015A0103, 0x81C, 0x005C0103,
- 0x81C, 0x005E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
- 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90012100, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFD000103, 0x81C, 0xFC020103,
- 0x81C, 0xFB040103, 0x81C, 0xFA060103, 0x81C, 0xF9080103,
- 0x81C, 0xF80A0103, 0x81C, 0xF70C0103, 0x81C, 0xF60E0103,
- 0x81C, 0xF5100103, 0x81C, 0xF4120103, 0x81C, 0xF3140103,
- 0x81C, 0xF2160103, 0x81C, 0xF1180103, 0x81C, 0xF01A0103,
- 0x81C, 0xEF1C0103, 0x81C, 0xEE1E0103, 0x81C, 0xED200103,
- 0x81C, 0xEC220103, 0x81C, 0xEB240103, 0x81C, 0xEA260103,
- 0x81C, 0xE9280103, 0x81C, 0xE82A0103, 0x81C, 0xE72C0103,
- 0x81C, 0xE62E0103, 0x81C, 0xE5300103, 0x81C, 0xE4320103,
- 0x81C, 0xE3340103, 0x81C, 0xC6360103, 0x81C, 0xC5380103,
- 0x81C, 0xC43A0103, 0x81C, 0xC33C0103, 0x81C, 0xC23E0103,
- 0x81C, 0xA5400103, 0x81C, 0xA4420103, 0x81C, 0xA3440103,
- 0x81C, 0xA2460103, 0x81C, 0xA1480103, 0x81C, 0x834A0103,
- 0x81C, 0x824C0103, 0x81C, 0x814E0103, 0x81C, 0x63500103,
- 0x81C, 0x62520103, 0x81C, 0x61540103, 0x81C, 0x43560103,
- 0x81C, 0x42580103, 0x81C, 0x245A0103, 0x81C, 0x235C0103,
- 0x81C, 0x225E0103, 0x81C, 0x21600103, 0x81C, 0x04620103,
- 0x81C, 0x03640103, 0x81C, 0x02660103, 0x81C, 0x01680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF8000103, 0x81C, 0xF7020103,
- 0x81C, 0xF6040103, 0x81C, 0xF5060103, 0x81C, 0xF4080103,
- 0x81C, 0xF30A0103, 0x81C, 0xF20C0103, 0x81C, 0xF10E0103,
- 0x81C, 0xF0100103, 0x81C, 0xEF120103, 0x81C, 0xEE140103,
- 0x81C, 0xED160103, 0x81C, 0xEC180103, 0x81C, 0xEB1A0103,
- 0x81C, 0xEA1C0103, 0x81C, 0xE91E0103, 0x81C, 0xE8200103,
- 0x81C, 0xE7220103, 0x81C, 0xE6240103, 0x81C, 0xE5260103,
- 0x81C, 0xE4280103, 0x81C, 0xE32A0103, 0x81C, 0xE22C0103,
- 0x81C, 0xC32E0103, 0x81C, 0xC2300103, 0x81C, 0xC1320103,
- 0x81C, 0xA3340103, 0x81C, 0xA2360103, 0x81C, 0xA1380103,
- 0x81C, 0xA03A0103, 0x81C, 0x823C0103, 0x81C, 0x813E0103,
- 0x81C, 0x80400103, 0x81C, 0x64420103, 0x81C, 0x63440103,
- 0x81C, 0x62460103, 0x81C, 0x61480103, 0x81C, 0x434A0103,
- 0x81C, 0x424C0103, 0x81C, 0x414E0103, 0x81C, 0x40500103,
- 0x81C, 0x22520103, 0x81C, 0x21540103, 0x81C, 0x20560103,
- 0x81C, 0x04580103, 0x81C, 0x035A0103, 0x81C, 0x025C0103,
- 0x81C, 0x015E0103, 0x81C, 0x00600103, 0x81C, 0x00620103,
- 0x81C, 0x00640103, 0x81C, 0x00660103, 0x81C, 0x00680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90011000, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFD000103, 0x81C, 0xFC020103,
- 0x81C, 0xFB040103, 0x81C, 0xFA060103, 0x81C, 0xF9080103,
- 0x81C, 0xF80A0103, 0x81C, 0xF70C0103, 0x81C, 0xF60E0103,
- 0x81C, 0xF5100103, 0x81C, 0xF4120103, 0x81C, 0xF3140103,
- 0x81C, 0xF2160103, 0x81C, 0xF1180103, 0x81C, 0xF01A0103,
- 0x81C, 0xEE1C0103, 0x81C, 0xED1E0103, 0x81C, 0xEC200103,
- 0x81C, 0xEB220103, 0x81C, 0xEA240103, 0x81C, 0xE9260103,
- 0x81C, 0xE8280103, 0x81C, 0xE72A0103, 0x81C, 0xE62C0103,
- 0x81C, 0xE52E0103, 0x81C, 0xE4300103, 0x81C, 0xE3320103,
- 0x81C, 0xE2340103, 0x81C, 0xC5360103, 0x81C, 0xC4380103,
- 0x81C, 0xC33A0103, 0x81C, 0xC23C0103, 0x81C, 0xA53E0103,
- 0x81C, 0xA4400103, 0x81C, 0xA3420103, 0x81C, 0xA2440103,
- 0x81C, 0xA1460103, 0x81C, 0x83480103, 0x81C, 0x824A0103,
- 0x81C, 0x814C0103, 0x81C, 0x804E0103, 0x81C, 0x63500103,
- 0x81C, 0x62520103, 0x81C, 0x61540103, 0x81C, 0x43560103,
- 0x81C, 0x42580103, 0x81C, 0x415A0103, 0x81C, 0x405C0103,
- 0x81C, 0x225E0103, 0x81C, 0x21600103, 0x81C, 0x20620103,
- 0x81C, 0x03640103, 0x81C, 0x02660103, 0x81C, 0x01680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFD000103, 0x81C, 0xFC020103,
- 0x81C, 0xFB040103, 0x81C, 0xFA060103, 0x81C, 0xF9080103,
- 0x81C, 0xF80A0103, 0x81C, 0xF70C0103, 0x81C, 0xF60E0103,
- 0x81C, 0xF5100103, 0x81C, 0xF4120103, 0x81C, 0xF3140103,
- 0x81C, 0xF2160103, 0x81C, 0xF1180103, 0x81C, 0xF01A0103,
- 0x81C, 0xEF1C0103, 0x81C, 0xEE1E0103, 0x81C, 0xED200103,
- 0x81C, 0xEC220103, 0x81C, 0xEB240103, 0x81C, 0xEA260103,
- 0x81C, 0xE9280103, 0x81C, 0xE82A0103, 0x81C, 0xE72C0103,
- 0x81C, 0xE62E0103, 0x81C, 0xE5300103, 0x81C, 0xE4320103,
- 0x81C, 0xE3340103, 0x81C, 0xE2360103, 0x81C, 0xC5380103,
- 0x81C, 0xC43A0103, 0x81C, 0xC33C0103, 0x81C, 0xC23E0103,
- 0x81C, 0xA5400103, 0x81C, 0xA4420103, 0x81C, 0xA3440103,
- 0x81C, 0xA2460103, 0x81C, 0xA1480103, 0x81C, 0x834A0103,
- 0x81C, 0x824C0103, 0x81C, 0x814E0103, 0x81C, 0x64500103,
- 0x81C, 0x63520103, 0x81C, 0x62540103, 0x81C, 0x61560103,
- 0x81C, 0x42580103, 0x81C, 0x415A0103, 0x81C, 0x405C0103,
- 0x81C, 0x065E0103, 0x81C, 0x05600103, 0x81C, 0x04620103,
- 0x81C, 0x03640103, 0x81C, 0x02660103, 0x81C, 0x01680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFE000103, 0x81C, 0xFD020103,
- 0x81C, 0xFC040103, 0x81C, 0xFB060103, 0x81C, 0xFA080103,
- 0x81C, 0xF90A0103, 0x81C, 0xF80C0103, 0x81C, 0xF70E0103,
- 0x81C, 0xF6100103, 0x81C, 0xF5120103, 0x81C, 0xF4140103,
- 0x81C, 0xF3160103, 0x81C, 0xF2180103, 0x81C, 0xF11A0103,
- 0x81C, 0xF01C0103, 0x81C, 0xEF1E0103, 0x81C, 0xEE200103,
- 0x81C, 0xED220103, 0x81C, 0xEC240103, 0x81C, 0xEB260103,
- 0x81C, 0xEA280103, 0x81C, 0xE92A0103, 0x81C, 0xE82C0103,
- 0x81C, 0xE72E0103, 0x81C, 0xE6300103, 0x81C, 0xE5320103,
- 0x81C, 0xE4340103, 0x81C, 0xE3360103, 0x81C, 0xC6380103,
- 0x81C, 0xC53A0103, 0x81C, 0xC43C0103, 0x81C, 0xC33E0103,
- 0x81C, 0xA5400103, 0x81C, 0xA4420103, 0x81C, 0xA3440103,
- 0x81C, 0xA2460103, 0x81C, 0xA1480103, 0x81C, 0xA04A0103,
- 0x81C, 0x824C0103, 0x81C, 0x814E0103, 0x81C, 0x80500103,
- 0x81C, 0x64520103, 0x81C, 0x63540103, 0x81C, 0x62560103,
- 0x81C, 0x61580103, 0x81C, 0x605A0103, 0x81C, 0x235C0103,
- 0x81C, 0x225E0103, 0x81C, 0x21600103, 0x81C, 0x20620103,
- 0x81C, 0x03640103, 0x81C, 0x02660103, 0x81C, 0x01680103,
- 0x81C, 0x006A0103, 0x81C, 0x006C0103, 0x81C, 0x006E0103,
- 0x81C, 0x00700103, 0x81C, 0x00720103, 0x81C, 0x00740103,
- 0x81C, 0x00760103, 0x81C, 0x00780103, 0x81C, 0x007A0103,
- 0x81C, 0x007C0103, 0x81C, 0x007E0103, 0xA0000000, 0x00000000,
- 0x81C, 0xFE000103, 0x81C, 0xFD020103, 0x81C, 0xFC040103,
- 0x81C, 0xFB060103, 0x81C, 0xFA080103, 0x81C, 0xF90A0103,
- 0x81C, 0xF80C0103, 0x81C, 0xF70E0103, 0x81C, 0xF6100103,
- 0x81C, 0xF5120103, 0x81C, 0xF4140103, 0x81C, 0xF3160103,
- 0x81C, 0xF2180103, 0x81C, 0xF11A0103, 0x81C, 0xF01C0103,
- 0x81C, 0xEF1E0103, 0x81C, 0xEE200103, 0x81C, 0xED220103,
- 0x81C, 0xEC240103, 0x81C, 0xEB260103, 0x81C, 0xEA280103,
- 0x81C, 0xE92A0103, 0x81C, 0xE82C0103, 0x81C, 0xE72E0103,
- 0x81C, 0xE6300103, 0x81C, 0xE5320103, 0x81C, 0xE4340103,
- 0x81C, 0xE3360103, 0x81C, 0xC6380103, 0x81C, 0xC53A0103,
- 0x81C, 0xC43C0103, 0x81C, 0xC33E0103, 0x81C, 0xA5400103,
- 0x81C, 0xA4420103, 0x81C, 0xA3440103, 0x81C, 0xA2460103,
- 0x81C, 0xA1480103, 0x81C, 0xA04A0103, 0x81C, 0x824C0103,
- 0x81C, 0x814E0103, 0x81C, 0x80500103, 0x81C, 0x64520103,
- 0x81C, 0x63540103, 0x81C, 0x62560103, 0x81C, 0x61580103,
- 0x81C, 0x605A0103, 0x81C, 0x235C0103, 0x81C, 0x225E0103,
- 0x81C, 0x21600103, 0x81C, 0x20620103, 0x81C, 0x03640103,
- 0x81C, 0x02660103, 0x81C, 0x01680103, 0x81C, 0x006A0103,
- 0x81C, 0x006C0103, 0x81C, 0x006E0103, 0x81C, 0x00700103,
- 0x81C, 0x00720103, 0x81C, 0x00740103, 0x81C, 0x00760103,
- 0x81C, 0x00780103, 0x81C, 0x007A0103, 0x81C, 0x007C0103,
- 0x81C, 0x007E0103, 0xB0000000, 0x00000000, 0x8000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x81C, 0xF8000203, 0x81C, 0xF7020203,
- 0x81C, 0xF6040203, 0x81C, 0xF5060203, 0x81C, 0xF4080203,
- 0x81C, 0xF30A0203, 0x81C, 0xF20C0203, 0x81C, 0xF10E0203,
- 0x81C, 0xF0100203, 0x81C, 0xEF120203, 0x81C, 0xEE140203,
- 0x81C, 0xED160203, 0x81C, 0xEC180203, 0x81C, 0xEB1A0203,
- 0x81C, 0xEA1C0203, 0x81C, 0xE91E0203, 0x81C, 0xE8200203,
- 0x81C, 0xE7220203, 0x81C, 0xE6240203, 0x81C, 0xE5260203,
- 0x81C, 0xE4280203, 0x81C, 0xE32A0203, 0x81C, 0xC42C0203,
- 0x81C, 0xC32E0203, 0x81C, 0xC2300203, 0x81C, 0xC1320203,
- 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
- 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
- 0x81C, 0x80400203, 0x81C, 0x65420203, 0x81C, 0x64440203,
- 0x81C, 0x63460203, 0x81C, 0x62480203, 0x81C, 0x614A0203,
- 0x81C, 0x424C0203, 0x81C, 0x414E0203, 0x81C, 0x40500203,
- 0x81C, 0x22520203, 0x81C, 0x21540203, 0x81C, 0x20560203,
- 0x81C, 0x04580203, 0x81C, 0x035A0203, 0x81C, 0x025C0203,
- 0x81C, 0x015E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
- 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x81C, 0xF9000203, 0x81C, 0xF8020203,
- 0x81C, 0xF7040203, 0x81C, 0xF6060203, 0x81C, 0xF5080203,
- 0x81C, 0xF40A0203, 0x81C, 0xF30C0203, 0x81C, 0xF20E0203,
- 0x81C, 0xF1100203, 0x81C, 0xF0120203, 0x81C, 0xEF140203,
- 0x81C, 0xEE160203, 0x81C, 0xED180203, 0x81C, 0xEC1A0203,
- 0x81C, 0xEB1C0203, 0x81C, 0xEA1E0203, 0x81C, 0xE9200203,
- 0x81C, 0xE8220203, 0x81C, 0xE7240203, 0x81C, 0xE6260203,
- 0x81C, 0xE5280203, 0x81C, 0xC42A0203, 0x81C, 0xC32C0203,
- 0x81C, 0xC22E0203, 0x81C, 0xC1300203, 0x81C, 0xC0320203,
- 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
- 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
- 0x81C, 0x80400203, 0x81C, 0x64420203, 0x81C, 0x63440203,
- 0x81C, 0x62460203, 0x81C, 0x61480203, 0x81C, 0x604A0203,
- 0x81C, 0x414C0203, 0x81C, 0x404E0203, 0x81C, 0x22500203,
- 0x81C, 0x21520203, 0x81C, 0x20540203, 0x81C, 0x03560203,
- 0x81C, 0x02580203, 0x81C, 0x015A0203, 0x81C, 0x005C0203,
- 0x81C, 0x005E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
- 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF7000203, 0x81C, 0xF6020203,
- 0x81C, 0xF5040203, 0x81C, 0xF4060203, 0x81C, 0xF3080203,
- 0x81C, 0xF20A0203, 0x81C, 0xF10C0203, 0x81C, 0xF00E0203,
- 0x81C, 0xEF100203, 0x81C, 0xEE120203, 0x81C, 0xED140203,
- 0x81C, 0xEC160203, 0x81C, 0xEB180203, 0x81C, 0xEA1A0203,
- 0x81C, 0xE91C0203, 0x81C, 0xE81E0203, 0x81C, 0xE7200203,
- 0x81C, 0xE6220203, 0x81C, 0xE5240203, 0x81C, 0xE4260203,
- 0x81C, 0xE3280203, 0x81C, 0xC42A0203, 0x81C, 0xC32C0203,
- 0x81C, 0xC22E0203, 0x81C, 0xC1300203, 0x81C, 0xC0320203,
- 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
- 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
- 0x81C, 0x80400203, 0x81C, 0x63420203, 0x81C, 0x62440203,
- 0x81C, 0x61460203, 0x81C, 0x60480203, 0x81C, 0x424A0203,
- 0x81C, 0x414C0203, 0x81C, 0x404E0203, 0x81C, 0x06500203,
- 0x81C, 0x05520203, 0x81C, 0x04540203, 0x81C, 0x03560203,
- 0x81C, 0x02580203, 0x81C, 0x015A0203, 0x81C, 0x005C0203,
- 0x81C, 0x005E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
- 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF7000203, 0x81C, 0xF6020203,
- 0x81C, 0xF5040203, 0x81C, 0xF4060203, 0x81C, 0xF3080203,
- 0x81C, 0xF20A0203, 0x81C, 0xF10C0203, 0x81C, 0xF00E0203,
- 0x81C, 0xEF100203, 0x81C, 0xEE120203, 0x81C, 0xED140203,
- 0x81C, 0xEC160203, 0x81C, 0xEB180203, 0x81C, 0xEA1A0203,
- 0x81C, 0xE91C0203, 0x81C, 0xE81E0203, 0x81C, 0xE7200203,
- 0x81C, 0xE6220203, 0x81C, 0xE5240203, 0x81C, 0xE4260203,
- 0x81C, 0xE3280203, 0x81C, 0xC42A0203, 0x81C, 0xC32C0203,
- 0x81C, 0xC22E0203, 0x81C, 0xC1300203, 0x81C, 0xC0320203,
- 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
- 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
- 0x81C, 0x80400203, 0x81C, 0x64420203, 0x81C, 0x63440203,
- 0x81C, 0x62460203, 0x81C, 0x61480203, 0x81C, 0x604A0203,
- 0x81C, 0x414C0203, 0x81C, 0x404E0203, 0x81C, 0x22500203,
- 0x81C, 0x21520203, 0x81C, 0x20540203, 0x81C, 0x03560203,
- 0x81C, 0x02580203, 0x81C, 0x015A0203, 0x81C, 0x005C0203,
- 0x81C, 0x005E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
- 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF7000203, 0x81C, 0xF6020203,
- 0x81C, 0xF5040203, 0x81C, 0xF4060203, 0x81C, 0xF3080203,
- 0x81C, 0xF20A0203, 0x81C, 0xF10C0203, 0x81C, 0xF00E0203,
- 0x81C, 0xEF100203, 0x81C, 0xEE120203, 0x81C, 0xED140203,
- 0x81C, 0xEC160203, 0x81C, 0xEB180203, 0x81C, 0xEA1A0203,
- 0x81C, 0xE91C0203, 0x81C, 0xE81E0203, 0x81C, 0xE7200203,
- 0x81C, 0xE6220203, 0x81C, 0xE5240203, 0x81C, 0xE4260203,
- 0x81C, 0xE3280203, 0x81C, 0xC42A0203, 0x81C, 0xC32C0203,
- 0x81C, 0xC22E0203, 0x81C, 0xC1300203, 0x81C, 0xC0320203,
- 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
- 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
- 0x81C, 0x80400203, 0x81C, 0x64420203, 0x81C, 0x63440203,
- 0x81C, 0x62460203, 0x81C, 0x61480203, 0x81C, 0x604A0203,
- 0x81C, 0x414C0203, 0x81C, 0x404E0203, 0x81C, 0x22500203,
- 0x81C, 0x21520203, 0x81C, 0x20540203, 0x81C, 0x03560203,
- 0x81C, 0x02580203, 0x81C, 0x015A0203, 0x81C, 0x005C0203,
- 0x81C, 0x005E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
- 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90012100, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFB000203, 0x81C, 0xFA020203,
- 0x81C, 0xF9040203, 0x81C, 0xF8060203, 0x81C, 0xF7080203,
- 0x81C, 0xF60A0203, 0x81C, 0xF50C0203, 0x81C, 0xF40E0203,
- 0x81C, 0xF3100203, 0x81C, 0xF2120203, 0x81C, 0xF1140203,
- 0x81C, 0xF0160203, 0x81C, 0xEF180203, 0x81C, 0xEE1A0203,
- 0x81C, 0xED1C0203, 0x81C, 0xEC1E0203, 0x81C, 0xEB200203,
- 0x81C, 0xEA220203, 0x81C, 0xE9240203, 0x81C, 0xE8260203,
- 0x81C, 0xE7280203, 0x81C, 0xE62A0203, 0x81C, 0xE52C0203,
- 0x81C, 0xE42E0203, 0x81C, 0xE3300203, 0x81C, 0xE2320203,
- 0x81C, 0xC6340203, 0x81C, 0xC5360203, 0x81C, 0xC4380203,
- 0x81C, 0xC33A0203, 0x81C, 0xC23C0203, 0x81C, 0xC13E0203,
- 0x81C, 0xC0400203, 0x81C, 0xA3420203, 0x81C, 0xA2440203,
- 0x81C, 0xA1460203, 0x81C, 0xA0480203, 0x81C, 0x824A0203,
- 0x81C, 0x814C0203, 0x81C, 0x804E0203, 0x81C, 0x63500203,
- 0x81C, 0x62520203, 0x81C, 0x61540203, 0x81C, 0x60560203,
- 0x81C, 0x24580203, 0x81C, 0x235A0203, 0x81C, 0x225C0203,
- 0x81C, 0x215E0203, 0x81C, 0x20600203, 0x81C, 0x03620203,
- 0x81C, 0x02640203, 0x81C, 0x01660203, 0x81C, 0x00680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF8000203, 0x81C, 0xF7020203,
- 0x81C, 0xF6040203, 0x81C, 0xF5060203, 0x81C, 0xF4080203,
- 0x81C, 0xF30A0203, 0x81C, 0xF20C0203, 0x81C, 0xF10E0203,
- 0x81C, 0xF0100203, 0x81C, 0xEF120203, 0x81C, 0xEE140203,
- 0x81C, 0xED160203, 0x81C, 0xEC180203, 0x81C, 0xEB1A0203,
- 0x81C, 0xEA1C0203, 0x81C, 0xE91E0203, 0x81C, 0xE8200203,
- 0x81C, 0xE7220203, 0x81C, 0xE6240203, 0x81C, 0xE5260203,
- 0x81C, 0xE4280203, 0x81C, 0xE32A0203, 0x81C, 0xC42C0203,
- 0x81C, 0xC32E0203, 0x81C, 0xC2300203, 0x81C, 0xC1320203,
- 0x81C, 0xA3340203, 0x81C, 0xA2360203, 0x81C, 0xA1380203,
- 0x81C, 0xA03A0203, 0x81C, 0x823C0203, 0x81C, 0x813E0203,
- 0x81C, 0x80400203, 0x81C, 0x65420203, 0x81C, 0x64440203,
- 0x81C, 0x63460203, 0x81C, 0x62480203, 0x81C, 0x614A0203,
- 0x81C, 0x424C0203, 0x81C, 0x414E0203, 0x81C, 0x40500203,
- 0x81C, 0x22520203, 0x81C, 0x21540203, 0x81C, 0x20560203,
- 0x81C, 0x04580203, 0x81C, 0x035A0203, 0x81C, 0x025C0203,
- 0x81C, 0x015E0203, 0x81C, 0x00600203, 0x81C, 0x00620203,
- 0x81C, 0x00640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90011000, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203,
- 0x81C, 0xFA040203, 0x81C, 0xF9060203, 0x81C, 0xF8080203,
- 0x81C, 0xF70A0203, 0x81C, 0xF60C0203, 0x81C, 0xF50E0203,
- 0x81C, 0xF4100203, 0x81C, 0xF3120203, 0x81C, 0xF2140203,
- 0x81C, 0xF1160203, 0x81C, 0xF0180203, 0x81C, 0xEE1A0203,
- 0x81C, 0xED1C0203, 0x81C, 0xEC1E0203, 0x81C, 0xEB200203,
- 0x81C, 0xEA220203, 0x81C, 0xE9240203, 0x81C, 0xE8260203,
- 0x81C, 0xE7280203, 0x81C, 0xE62A0203, 0x81C, 0xE52C0203,
- 0x81C, 0xE42E0203, 0x81C, 0xE3300203, 0x81C, 0xE2320203,
- 0x81C, 0xC6340203, 0x81C, 0xC5360203, 0x81C, 0xC4380203,
- 0x81C, 0xC33A0203, 0x81C, 0xA63C0203, 0x81C, 0xA53E0203,
- 0x81C, 0xA4400203, 0x81C, 0xA3420203, 0x81C, 0xA2440203,
- 0x81C, 0xA1460203, 0x81C, 0x83480203, 0x81C, 0x824A0203,
- 0x81C, 0x814C0203, 0x81C, 0x804E0203, 0x81C, 0x63500203,
- 0x81C, 0x62520203, 0x81C, 0x61540203, 0x81C, 0x42560203,
- 0x81C, 0x41580203, 0x81C, 0x405A0203, 0x81C, 0x225C0203,
- 0x81C, 0x215E0203, 0x81C, 0x20600203, 0x81C, 0x04620203,
- 0x81C, 0x03640203, 0x81C, 0x02660203, 0x81C, 0x01680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203,
- 0x81C, 0xFA040203, 0x81C, 0xF9060203, 0x81C, 0xF8080203,
- 0x81C, 0xF70A0203, 0x81C, 0xF60C0203, 0x81C, 0xF50E0203,
- 0x81C, 0xF4100203, 0x81C, 0xF3120203, 0x81C, 0xF2140203,
- 0x81C, 0xF1160203, 0x81C, 0xF0180203, 0x81C, 0xEF1A0203,
- 0x81C, 0xEE1C0203, 0x81C, 0xED1E0203, 0x81C, 0xEC200203,
- 0x81C, 0xEB220203, 0x81C, 0xEA240203, 0x81C, 0xE9260203,
- 0x81C, 0xE8280203, 0x81C, 0xE72A0203, 0x81C, 0xE62C0203,
- 0x81C, 0xE52E0203, 0x81C, 0xE4300203, 0x81C, 0xE3320203,
- 0x81C, 0xE2340203, 0x81C, 0xE1360203, 0x81C, 0xC5380203,
- 0x81C, 0xC43A0203, 0x81C, 0xC33C0203, 0x81C, 0xC23E0203,
- 0x81C, 0xC1400203, 0x81C, 0xA3420203, 0x81C, 0xA2440203,
- 0x81C, 0xA1460203, 0x81C, 0xA0480203, 0x81C, 0x834A0203,
- 0x81C, 0x824C0203, 0x81C, 0x814E0203, 0x81C, 0x64500203,
- 0x81C, 0x63520203, 0x81C, 0x62540203, 0x81C, 0x61560203,
- 0x81C, 0x25580203, 0x81C, 0x245A0203, 0x81C, 0x235C0203,
- 0x81C, 0x225E0203, 0x81C, 0x21600203, 0x81C, 0x04620203,
- 0x81C, 0x03640203, 0x81C, 0x02660203, 0x81C, 0x01680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203,
- 0x81C, 0xFA040203, 0x81C, 0xF9060203, 0x81C, 0xF8080203,
- 0x81C, 0xF70A0203, 0x81C, 0xF60C0203, 0x81C, 0xF50E0203,
- 0x81C, 0xF4100203, 0x81C, 0xF3120203, 0x81C, 0xF2140203,
- 0x81C, 0xF1160203, 0x81C, 0xF0180203, 0x81C, 0xEF1A0203,
- 0x81C, 0xEE1C0203, 0x81C, 0xED1E0203, 0x81C, 0xEC200203,
- 0x81C, 0xEB220203, 0x81C, 0xEA240203, 0x81C, 0xE9260203,
- 0x81C, 0xE8280203, 0x81C, 0xE72A0203, 0x81C, 0xE62C0203,
- 0x81C, 0xE52E0203, 0x81C, 0xE4300203, 0x81C, 0xE3320203,
- 0x81C, 0xE2340203, 0x81C, 0xC6360203, 0x81C, 0xC5380203,
- 0x81C, 0xC43A0203, 0x81C, 0xC33C0203, 0x81C, 0xA63E0203,
- 0x81C, 0xA5400203, 0x81C, 0xA4420203, 0x81C, 0xA3440203,
- 0x81C, 0xA2460203, 0x81C, 0xA1480203, 0x81C, 0x834A0203,
- 0x81C, 0x824C0203, 0x81C, 0x814E0203, 0x81C, 0x64500203,
- 0x81C, 0x63520203, 0x81C, 0x62540203, 0x81C, 0x61560203,
- 0x81C, 0x60580203, 0x81C, 0x405A0203, 0x81C, 0x215C0203,
- 0x81C, 0x205E0203, 0x81C, 0x03600203, 0x81C, 0x02620203,
- 0x81C, 0x01640203, 0x81C, 0x00660203, 0x81C, 0x00680203,
- 0x81C, 0x006A0203, 0x81C, 0x006C0203, 0x81C, 0x006E0203,
- 0x81C, 0x00700203, 0x81C, 0x00720203, 0x81C, 0x00740203,
- 0x81C, 0x00760203, 0x81C, 0x00780203, 0x81C, 0x007A0203,
- 0x81C, 0x007C0203, 0x81C, 0x007E0203, 0xA0000000, 0x00000000,
- 0x81C, 0xFD000203, 0x81C, 0xFC020203, 0x81C, 0xFB040203,
- 0x81C, 0xFA060203, 0x81C, 0xF9080203, 0x81C, 0xF80A0203,
- 0x81C, 0xF70C0203, 0x81C, 0xF60E0203, 0x81C, 0xF5100203,
- 0x81C, 0xF4120203, 0x81C, 0xF3140203, 0x81C, 0xF2160203,
- 0x81C, 0xF1180203, 0x81C, 0xF01A0203, 0x81C, 0xEF1C0203,
- 0x81C, 0xEE1E0203, 0x81C, 0xED200203, 0x81C, 0xEC220203,
- 0x81C, 0xEB240203, 0x81C, 0xEA260203, 0x81C, 0xE9280203,
- 0x81C, 0xE82A0203, 0x81C, 0xE72C0203, 0x81C, 0xE62E0203,
- 0x81C, 0xE5300203, 0x81C, 0xE4320203, 0x81C, 0xE3340203,
- 0x81C, 0xC6360203, 0x81C, 0xC5380203, 0x81C, 0xC43A0203,
- 0x81C, 0xC33C0203, 0x81C, 0xA63E0203, 0x81C, 0xA5400203,
- 0x81C, 0xA4420203, 0x81C, 0xA3440203, 0x81C, 0xA2460203,
- 0x81C, 0xA1480203, 0x81C, 0x834A0203, 0x81C, 0x824C0203,
- 0x81C, 0x814E0203, 0x81C, 0x64500203, 0x81C, 0x63520203,
- 0x81C, 0x62540203, 0x81C, 0x61560203, 0x81C, 0x60580203,
- 0x81C, 0x235A0203, 0x81C, 0x225C0203, 0x81C, 0x215E0203,
- 0x81C, 0x20600203, 0x81C, 0x03620203, 0x81C, 0x02640203,
- 0x81C, 0x01660203, 0x81C, 0x00680203, 0x81C, 0x006A0203,
- 0x81C, 0x006C0203, 0x81C, 0x006E0203, 0x81C, 0x00700203,
- 0x81C, 0x00720203, 0x81C, 0x00740203, 0x81C, 0x00760203,
- 0x81C, 0x00780203, 0x81C, 0x007A0203, 0x81C, 0x007C0203,
- 0x81C, 0x007E0203, 0xB0000000, 0x00000000, 0x8000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x81C, 0xF8000303, 0x81C, 0xF7020303,
- 0x81C, 0xF6040303, 0x81C, 0xF5060303, 0x81C, 0xF4080303,
- 0x81C, 0xF30A0303, 0x81C, 0xF20C0303, 0x81C, 0xF10E0303,
- 0x81C, 0xF0100303, 0x81C, 0xEF120303, 0x81C, 0xEE140303,
- 0x81C, 0xED160303, 0x81C, 0xEC180303, 0x81C, 0xEB1A0303,
- 0x81C, 0xEA1C0303, 0x81C, 0xE91E0303, 0x81C, 0xCA200303,
- 0x81C, 0xC9220303, 0x81C, 0xC8240303, 0x81C, 0xC7260303,
- 0x81C, 0xC6280303, 0x81C, 0xC52A0303, 0x81C, 0xC42C0303,
- 0x81C, 0xC32E0303, 0x81C, 0xC2300303, 0x81C, 0xC1320303,
- 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
- 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
- 0x81C, 0x80400303, 0x81C, 0x65420303, 0x81C, 0x64440303,
- 0x81C, 0x63460303, 0x81C, 0x62480303, 0x81C, 0x614A0303,
- 0x81C, 0x424C0303, 0x81C, 0x414E0303, 0x81C, 0x40500303,
- 0x81C, 0x22520303, 0x81C, 0x21540303, 0x81C, 0x20560303,
- 0x81C, 0x04580303, 0x81C, 0x035A0303, 0x81C, 0x025C0303,
- 0x81C, 0x015E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
- 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x81C, 0xF9000303, 0x81C, 0xF8020303,
- 0x81C, 0xF7040303, 0x81C, 0xF6060303, 0x81C, 0xF5080303,
- 0x81C, 0xF40A0303, 0x81C, 0xF30C0303, 0x81C, 0xF20E0303,
- 0x81C, 0xF1100303, 0x81C, 0xF0120303, 0x81C, 0xEF140303,
- 0x81C, 0xEE160303, 0x81C, 0xED180303, 0x81C, 0xEC1A0303,
- 0x81C, 0xEB1C0303, 0x81C, 0xEA1E0303, 0x81C, 0xC9200303,
- 0x81C, 0xC8220303, 0x81C, 0xC7240303, 0x81C, 0xC6260303,
- 0x81C, 0xC5280303, 0x81C, 0xC42A0303, 0x81C, 0xC32C0303,
- 0x81C, 0xC22E0303, 0x81C, 0xC1300303, 0x81C, 0xC0320303,
- 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
- 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
- 0x81C, 0x80400303, 0x81C, 0x64420303, 0x81C, 0x63440303,
- 0x81C, 0x62460303, 0x81C, 0x61480303, 0x81C, 0x604A0303,
- 0x81C, 0x414C0303, 0x81C, 0x404E0303, 0x81C, 0x22500303,
- 0x81C, 0x21520303, 0x81C, 0x20540303, 0x81C, 0x03560303,
- 0x81C, 0x02580303, 0x81C, 0x015A0303, 0x81C, 0x005C0303,
- 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
- 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF7000303, 0x81C, 0xF6020303,
- 0x81C, 0xF5040303, 0x81C, 0xF4060303, 0x81C, 0xF3080303,
- 0x81C, 0xF20A0303, 0x81C, 0xF10C0303, 0x81C, 0xF00E0303,
- 0x81C, 0xEF100303, 0x81C, 0xEE120303, 0x81C, 0xED140303,
- 0x81C, 0xEC160303, 0x81C, 0xEB180303, 0x81C, 0xEA1A0303,
- 0x81C, 0xE91C0303, 0x81C, 0xCA1E0303, 0x81C, 0xC9200303,
- 0x81C, 0xC8220303, 0x81C, 0xC7240303, 0x81C, 0xC6260303,
- 0x81C, 0xC5280303, 0x81C, 0xC42A0303, 0x81C, 0xC32C0303,
- 0x81C, 0xC22E0303, 0x81C, 0xC1300303, 0x81C, 0xA4320303,
- 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
- 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
- 0x81C, 0x80400303, 0x81C, 0x64420303, 0x81C, 0x63440303,
- 0x81C, 0x62460303, 0x81C, 0x61480303, 0x81C, 0x604A0303,
- 0x81C, 0x414C0303, 0x81C, 0x404E0303, 0x81C, 0x06500303,
- 0x81C, 0x05520303, 0x81C, 0x04540303, 0x81C, 0x03560303,
- 0x81C, 0x02580303, 0x81C, 0x015A0303, 0x81C, 0x005C0303,
- 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
- 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF7000303, 0x81C, 0xF6020303,
- 0x81C, 0xF5040303, 0x81C, 0xF4060303, 0x81C, 0xF3080303,
- 0x81C, 0xF20A0303, 0x81C, 0xF10C0303, 0x81C, 0xF00E0303,
- 0x81C, 0xEF100303, 0x81C, 0xEE120303, 0x81C, 0xED140303,
- 0x81C, 0xEC160303, 0x81C, 0xEB180303, 0x81C, 0xEA1A0303,
- 0x81C, 0xE91C0303, 0x81C, 0xCA1E0303, 0x81C, 0xC9200303,
- 0x81C, 0xC8220303, 0x81C, 0xC7240303, 0x81C, 0xC6260303,
- 0x81C, 0xC5280303, 0x81C, 0xC42A0303, 0x81C, 0xC32C0303,
- 0x81C, 0xC22E0303, 0x81C, 0xC1300303, 0x81C, 0xA4320303,
- 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
- 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
- 0x81C, 0x80400303, 0x81C, 0x64420303, 0x81C, 0x63440303,
- 0x81C, 0x62460303, 0x81C, 0x61480303, 0x81C, 0x604A0303,
- 0x81C, 0x414C0303, 0x81C, 0x404E0303, 0x81C, 0x22500303,
- 0x81C, 0x21520303, 0x81C, 0x20540303, 0x81C, 0x03560303,
- 0x81C, 0x02580303, 0x81C, 0x015A0303, 0x81C, 0x005C0303,
- 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
- 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF7000303, 0x81C, 0xF6020303,
- 0x81C, 0xF5040303, 0x81C, 0xF4060303, 0x81C, 0xF3080303,
- 0x81C, 0xF20A0303, 0x81C, 0xF10C0303, 0x81C, 0xF00E0303,
- 0x81C, 0xEF100303, 0x81C, 0xEE120303, 0x81C, 0xED140303,
- 0x81C, 0xEC160303, 0x81C, 0xEB180303, 0x81C, 0xEA1A0303,
- 0x81C, 0xE91C0303, 0x81C, 0xCA1E0303, 0x81C, 0xC9200303,
- 0x81C, 0xC8220303, 0x81C, 0xC7240303, 0x81C, 0xC6260303,
- 0x81C, 0xC5280303, 0x81C, 0xC42A0303, 0x81C, 0xC32C0303,
- 0x81C, 0xC22E0303, 0x81C, 0xC1300303, 0x81C, 0xA4320303,
- 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
- 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
- 0x81C, 0x80400303, 0x81C, 0x64420303, 0x81C, 0x63440303,
- 0x81C, 0x62460303, 0x81C, 0x61480303, 0x81C, 0x604A0303,
- 0x81C, 0x414C0303, 0x81C, 0x404E0303, 0x81C, 0x22500303,
- 0x81C, 0x21520303, 0x81C, 0x20540303, 0x81C, 0x03560303,
- 0x81C, 0x02580303, 0x81C, 0x015A0303, 0x81C, 0x005C0303,
- 0x81C, 0x005E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
- 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90012100, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFB000303, 0x81C, 0xFA020303,
- 0x81C, 0xF9040303, 0x81C, 0xF8060303, 0x81C, 0xF7080303,
- 0x81C, 0xF60A0303, 0x81C, 0xF50C0303, 0x81C, 0xF40E0303,
- 0x81C, 0xF3100303, 0x81C, 0xF2120303, 0x81C, 0xF1140303,
- 0x81C, 0xF0160303, 0x81C, 0xEF180303, 0x81C, 0xEE1A0303,
- 0x81C, 0xED1C0303, 0x81C, 0xEC1E0303, 0x81C, 0xEB200303,
- 0x81C, 0xEA220303, 0x81C, 0xE9240303, 0x81C, 0xE8260303,
- 0x81C, 0xE7280303, 0x81C, 0xE62A0303, 0x81C, 0xE52C0303,
- 0x81C, 0xE42E0303, 0x81C, 0xE3300303, 0x81C, 0xE2320303,
- 0x81C, 0xC6340303, 0x81C, 0xC5360303, 0x81C, 0xC4380303,
- 0x81C, 0xC33A0303, 0x81C, 0xC23C0303, 0x81C, 0xC13E0303,
- 0x81C, 0xA4400303, 0x81C, 0xA3420303, 0x81C, 0xA2440303,
- 0x81C, 0xA1460303, 0x81C, 0x83480303, 0x81C, 0x824A0303,
- 0x81C, 0x814C0303, 0x81C, 0x804E0303, 0x81C, 0x63500303,
- 0x81C, 0x62520303, 0x81C, 0x43540303, 0x81C, 0x42560303,
- 0x81C, 0x41580303, 0x81C, 0x235A0303, 0x81C, 0x225C0303,
- 0x81C, 0x215E0303, 0x81C, 0x20600303, 0x81C, 0x04620303,
- 0x81C, 0x03640303, 0x81C, 0x02660303, 0x81C, 0x01680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xF8000303, 0x81C, 0xF7020303,
- 0x81C, 0xF6040303, 0x81C, 0xF5060303, 0x81C, 0xF4080303,
- 0x81C, 0xF30A0303, 0x81C, 0xF20C0303, 0x81C, 0xF10E0303,
- 0x81C, 0xF0100303, 0x81C, 0xEF120303, 0x81C, 0xEE140303,
- 0x81C, 0xED160303, 0x81C, 0xEC180303, 0x81C, 0xEB1A0303,
- 0x81C, 0xEA1C0303, 0x81C, 0xE91E0303, 0x81C, 0xCA200303,
- 0x81C, 0xC9220303, 0x81C, 0xC8240303, 0x81C, 0xC7260303,
- 0x81C, 0xC6280303, 0x81C, 0xC52A0303, 0x81C, 0xC42C0303,
- 0x81C, 0xC32E0303, 0x81C, 0xC2300303, 0x81C, 0xC1320303,
- 0x81C, 0xA3340303, 0x81C, 0xA2360303, 0x81C, 0xA1380303,
- 0x81C, 0xA03A0303, 0x81C, 0x823C0303, 0x81C, 0x813E0303,
- 0x81C, 0x80400303, 0x81C, 0x65420303, 0x81C, 0x64440303,
- 0x81C, 0x63460303, 0x81C, 0x62480303, 0x81C, 0x614A0303,
- 0x81C, 0x424C0303, 0x81C, 0x414E0303, 0x81C, 0x40500303,
- 0x81C, 0x22520303, 0x81C, 0x21540303, 0x81C, 0x20560303,
- 0x81C, 0x04580303, 0x81C, 0x035A0303, 0x81C, 0x025C0303,
- 0x81C, 0x015E0303, 0x81C, 0x00600303, 0x81C, 0x00620303,
- 0x81C, 0x00640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90011000, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFB000303, 0x81C, 0xFA020303,
- 0x81C, 0xF9040303, 0x81C, 0xF8060303, 0x81C, 0xF7080303,
- 0x81C, 0xF60A0303, 0x81C, 0xF50C0303, 0x81C, 0xF40E0303,
- 0x81C, 0xF3100303, 0x81C, 0xF2120303, 0x81C, 0xF1140303,
- 0x81C, 0xF0160303, 0x81C, 0xEE180303, 0x81C, 0xED1A0303,
- 0x81C, 0xEC1C0303, 0x81C, 0xEB1E0303, 0x81C, 0xEA200303,
- 0x81C, 0xE9220303, 0x81C, 0xE8240303, 0x81C, 0xE7260303,
- 0x81C, 0xE6280303, 0x81C, 0xE52A0303, 0x81C, 0xE42C0303,
- 0x81C, 0xE32E0303, 0x81C, 0xE2300303, 0x81C, 0xE1320303,
- 0x81C, 0xC6340303, 0x81C, 0xC5360303, 0x81C, 0xC4380303,
- 0x81C, 0xC33A0303, 0x81C, 0xA63C0303, 0x81C, 0xA53E0303,
- 0x81C, 0xA4400303, 0x81C, 0xA3420303, 0x81C, 0xA2440303,
- 0x81C, 0xA1460303, 0x81C, 0x83480303, 0x81C, 0x824A0303,
- 0x81C, 0x814C0303, 0x81C, 0x804E0303, 0x81C, 0x63500303,
- 0x81C, 0x62520303, 0x81C, 0x61540303, 0x81C, 0x42560303,
- 0x81C, 0x41580303, 0x81C, 0x405A0303, 0x81C, 0x225C0303,
- 0x81C, 0x215E0303, 0x81C, 0x20600303, 0x81C, 0x04620303,
- 0x81C, 0x03640303, 0x81C, 0x02660303, 0x81C, 0x01680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFB000303, 0x81C, 0xFA020303,
- 0x81C, 0xF9040303, 0x81C, 0xF8060303, 0x81C, 0xF7080303,
- 0x81C, 0xF60A0303, 0x81C, 0xF50C0303, 0x81C, 0xF40E0303,
- 0x81C, 0xF3100303, 0x81C, 0xF2120303, 0x81C, 0xF1140303,
- 0x81C, 0xF0160303, 0x81C, 0xEF180303, 0x81C, 0xEE1A0303,
- 0x81C, 0xED1C0303, 0x81C, 0xEC1E0303, 0x81C, 0xEB200303,
- 0x81C, 0xEA220303, 0x81C, 0xE9240303, 0x81C, 0xE8260303,
- 0x81C, 0xE7280303, 0x81C, 0xE62A0303, 0x81C, 0xE52C0303,
- 0x81C, 0xE42E0303, 0x81C, 0xE3300303, 0x81C, 0xE2320303,
- 0x81C, 0xE1340303, 0x81C, 0xC5360303, 0x81C, 0xC4380303,
- 0x81C, 0xC33A0303, 0x81C, 0xC23C0303, 0x81C, 0xC13E0303,
- 0x81C, 0xA4400303, 0x81C, 0xA3420303, 0x81C, 0xA2440303,
- 0x81C, 0xA1460303, 0x81C, 0x83480303, 0x81C, 0x824A0303,
- 0x81C, 0x814C0303, 0x81C, 0x804E0303, 0x81C, 0x64500303,
- 0x81C, 0x63520303, 0x81C, 0x62540303, 0x81C, 0x61560303,
- 0x81C, 0x60580303, 0x81C, 0x235A0303, 0x81C, 0x225C0303,
- 0x81C, 0x215E0303, 0x81C, 0x20600303, 0x81C, 0x04620303,
- 0x81C, 0x03640303, 0x81C, 0x02660303, 0x81C, 0x01680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFC000303, 0x81C, 0xFB020303,
- 0x81C, 0xFA040303, 0x81C, 0xF9060303, 0x81C, 0xF8080303,
- 0x81C, 0xF70A0303, 0x81C, 0xF60C0303, 0x81C, 0xF50E0303,
- 0x81C, 0xF4100303, 0x81C, 0xF3120303, 0x81C, 0xF2140303,
- 0x81C, 0xF1160303, 0x81C, 0xF0180303, 0x81C, 0xEF1A0303,
- 0x81C, 0xEE1C0303, 0x81C, 0xED1E0303, 0x81C, 0xEC200303,
- 0x81C, 0xEB220303, 0x81C, 0xEA240303, 0x81C, 0xE9260303,
- 0x81C, 0xE8280303, 0x81C, 0xE72A0303, 0x81C, 0xE62C0303,
- 0x81C, 0xE52E0303, 0x81C, 0xE4300303, 0x81C, 0xE3320303,
- 0x81C, 0xE2340303, 0x81C, 0xC6360303, 0x81C, 0xC5380303,
- 0x81C, 0xC43A0303, 0x81C, 0xC33C0303, 0x81C, 0xA63E0303,
- 0x81C, 0xA5400303, 0x81C, 0xA4420303, 0x81C, 0xA3440303,
- 0x81C, 0xA2460303, 0x81C, 0x84480303, 0x81C, 0x834A0303,
- 0x81C, 0x824C0303, 0x81C, 0x814E0303, 0x81C, 0x80500303,
- 0x81C, 0x63520303, 0x81C, 0x62540303, 0x81C, 0x61560303,
- 0x81C, 0x60580303, 0x81C, 0x225A0303, 0x81C, 0x055C0303,
- 0x81C, 0x045E0303, 0x81C, 0x03600303, 0x81C, 0x02620303,
- 0x81C, 0x01640303, 0x81C, 0x00660303, 0x81C, 0x00680303,
- 0x81C, 0x006A0303, 0x81C, 0x006C0303, 0x81C, 0x006E0303,
- 0x81C, 0x00700303, 0x81C, 0x00720303, 0x81C, 0x00740303,
- 0x81C, 0x00760303, 0x81C, 0x00780303, 0x81C, 0x007A0303,
- 0x81C, 0x007C0303, 0x81C, 0x007E0303, 0xA0000000, 0x00000000,
- 0x81C, 0xFC000303, 0x81C, 0xFB020303, 0x81C, 0xFA040303,
- 0x81C, 0xF9060303, 0x81C, 0xF8080303, 0x81C, 0xF70A0303,
- 0x81C, 0xF60C0303, 0x81C, 0xF50E0303, 0x81C, 0xF4100303,
- 0x81C, 0xF3120303, 0x81C, 0xF2140303, 0x81C, 0xF1160303,
- 0x81C, 0xF0180303, 0x81C, 0xEF1A0303, 0x81C, 0xEE1C0303,
- 0x81C, 0xED1E0303, 0x81C, 0xEC200303, 0x81C, 0xEB220303,
- 0x81C, 0xEA240303, 0x81C, 0xE9260303, 0x81C, 0xE8280303,
- 0x81C, 0xE72A0303, 0x81C, 0xE62C0303, 0x81C, 0xE52E0303,
- 0x81C, 0xE4300303, 0x81C, 0xE3320303, 0x81C, 0xE2340303,
- 0x81C, 0xC6360303, 0x81C, 0xC5380303, 0x81C, 0xC43A0303,
- 0x81C, 0xC33C0303, 0x81C, 0xA63E0303, 0x81C, 0xA5400303,
- 0x81C, 0xA4420303, 0x81C, 0xA3440303, 0x81C, 0xA2460303,
- 0x81C, 0x84480303, 0x81C, 0x834A0303, 0x81C, 0x824C0303,
- 0x81C, 0x814E0303, 0x81C, 0x80500303, 0x81C, 0x63520303,
- 0x81C, 0x62540303, 0x81C, 0x61560303, 0x81C, 0x60580303,
- 0x81C, 0x235A0303, 0x81C, 0x225C0303, 0x81C, 0x215E0303,
- 0x81C, 0x20600303, 0x81C, 0x03620303, 0x81C, 0x02640303,
- 0x81C, 0x01660303, 0x81C, 0x00680303, 0x81C, 0x006A0303,
- 0x81C, 0x006C0303, 0x81C, 0x006E0303, 0x81C, 0x00700303,
- 0x81C, 0x00720303, 0x81C, 0x00740303, 0x81C, 0x00760303,
- 0x81C, 0x00780303, 0x81C, 0x007A0303, 0x81C, 0x007C0303,
- 0x81C, 0x007E0303, 0xB0000000, 0x00000000, 0x8000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403,
- 0x81C, 0xF4020403, 0x81C, 0xF3040403, 0x81C, 0xF2060403,
- 0x81C, 0xF1080403, 0x81C, 0xF00A0403, 0x81C, 0xEF0C0403,
- 0x81C, 0xEE0E0403, 0x81C, 0xED100403, 0x81C, 0xEC120403,
- 0x81C, 0xEB140403, 0x81C, 0xEA160403, 0x81C, 0xE9180403,
- 0x81C, 0xE81A0403, 0x81C, 0xE71C0403, 0x81C, 0xE61E0403,
- 0x81C, 0xE5200403, 0x81C, 0xE4220403, 0x81C, 0xE3240403,
- 0x81C, 0xE2260403, 0x81C, 0xE1280403, 0x81C, 0xE02A0403,
- 0x81C, 0xC32C0403, 0x81C, 0xC22E0403, 0x81C, 0xC1300403,
- 0x81C, 0xC0320403, 0x81C, 0xA4340403, 0x81C, 0xA3360403,
- 0x81C, 0xA2380403, 0x81C, 0xA13A0403, 0x81C, 0xA03C0403,
- 0x81C, 0x823E0403, 0x81C, 0x81400403, 0x81C, 0x80420403,
- 0x81C, 0x64440403, 0x81C, 0x63460403, 0x81C, 0x62480403,
- 0x81C, 0x614A0403, 0x81C, 0x604C0403, 0x81C, 0x454E0403,
- 0x81C, 0x44500403, 0x81C, 0x43520403, 0x81C, 0x42540403,
- 0x81C, 0x41560403, 0x81C, 0x40580403, 0x81C, 0x055A0403,
- 0x81C, 0x045C0403, 0x81C, 0x035E0403, 0x81C, 0x02600403,
- 0x81C, 0x01620403, 0x81C, 0x00640403, 0x81C, 0x00660403,
- 0x81C, 0x00680403, 0x81C, 0x006A0403, 0x81C, 0x006C0403,
- 0x81C, 0x006E0403, 0x81C, 0x00700403, 0x81C, 0x00720403,
- 0x81C, 0x00740403, 0x81C, 0x00760403, 0x81C, 0x00780403,
- 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x81C, 0xFF000403,
- 0x81C, 0xF5000403, 0x81C, 0xF4020403, 0x81C, 0xF3040403,
- 0x81C, 0xF2060403, 0x81C, 0xF1080403, 0x81C, 0xF00A0403,
- 0x81C, 0xEF0C0403, 0x81C, 0xEE0E0403, 0x81C, 0xED100403,
- 0x81C, 0xEC120403, 0x81C, 0xEB140403, 0x81C, 0xEA160403,
- 0x81C, 0xE9180403, 0x81C, 0xE81A0403, 0x81C, 0xE71C0403,
- 0x81C, 0xE61E0403, 0x81C, 0xE5200403, 0x81C, 0xE4220403,
- 0x81C, 0xE3240403, 0x81C, 0xE2260403, 0x81C, 0xE1280403,
- 0x81C, 0xE02A0403, 0x81C, 0xC32C0403, 0x81C, 0xC22E0403,
- 0x81C, 0xC1300403, 0x81C, 0xC0320403, 0x81C, 0xA4340403,
- 0x81C, 0xA3360403, 0x81C, 0xA2380403, 0x81C, 0xA13A0403,
- 0x81C, 0xA03C0403, 0x81C, 0x823E0403, 0x81C, 0x81400403,
- 0x81C, 0x80420403, 0x81C, 0x64440403, 0x81C, 0x63460403,
- 0x81C, 0x62480403, 0x81C, 0x614A0403, 0x81C, 0x604C0403,
- 0x81C, 0x454E0403, 0x81C, 0x44500403, 0x81C, 0x43520403,
- 0x81C, 0x42540403, 0x81C, 0x41560403, 0x81C, 0x40580403,
- 0x81C, 0x055A0403, 0x81C, 0x045C0403, 0x81C, 0x035E0403,
- 0x81C, 0x02600403, 0x81C, 0x01620403, 0x81C, 0x00640403,
- 0x81C, 0x00660403, 0x81C, 0x00680403, 0x81C, 0x006A0403,
- 0x81C, 0x006C0403, 0x81C, 0x006E0403, 0x81C, 0x00700403,
- 0x81C, 0x00720403, 0x81C, 0x00740403, 0x81C, 0x00760403,
- 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403,
- 0x81C, 0x007E0403, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x81C, 0xFF000403, 0x81C, 0xF5000403, 0x81C, 0xF4020403,
- 0x81C, 0xF3040403, 0x81C, 0xF2060403, 0x81C, 0xF1080403,
- 0x81C, 0xF00A0403, 0x81C, 0xEF0C0403, 0x81C, 0xEE0E0403,
- 0x81C, 0xED100403, 0x81C, 0xEC120403, 0x81C, 0xEB140403,
- 0x81C, 0xEA160403, 0x81C, 0xE9180403, 0x81C, 0xE81A0403,
- 0x81C, 0xE71C0403, 0x81C, 0xE61E0403, 0x81C, 0xE5200403,
- 0x81C, 0xE4220403, 0x81C, 0xE3240403, 0x81C, 0xE2260403,
- 0x81C, 0xE1280403, 0x81C, 0xE02A0403, 0x81C, 0xC32C0403,
- 0x81C, 0xC22E0403, 0x81C, 0xC1300403, 0x81C, 0xC0320403,
- 0x81C, 0xA4340403, 0x81C, 0xA3360403, 0x81C, 0xA2380403,
- 0x81C, 0xA13A0403, 0x81C, 0xA03C0403, 0x81C, 0x823E0403,
- 0x81C, 0x81400403, 0x81C, 0x80420403, 0x81C, 0x64440403,
- 0x81C, 0x63460403, 0x81C, 0x62480403, 0x81C, 0x614A0403,
- 0x81C, 0x604C0403, 0x81C, 0x454E0403, 0x81C, 0x44500403,
- 0x81C, 0x43520403, 0x81C, 0x42540403, 0x81C, 0x41560403,
- 0x81C, 0x40580403, 0x81C, 0x055A0403, 0x81C, 0x045C0403,
- 0x81C, 0x035E0403, 0x81C, 0x02600403, 0x81C, 0x01620403,
- 0x81C, 0x00640403, 0x81C, 0x00660403, 0x81C, 0x00680403,
- 0x81C, 0x006A0403, 0x81C, 0x006C0403, 0x81C, 0x006E0403,
- 0x81C, 0x00700403, 0x81C, 0x00720403, 0x81C, 0x00740403,
- 0x81C, 0x00760403, 0x81C, 0x00780403, 0x81C, 0x007A0403,
- 0x81C, 0x007C0403, 0x81C, 0x007E0403, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403,
- 0x81C, 0xF4020403, 0x81C, 0xF3040403, 0x81C, 0xF2060403,
- 0x81C, 0xF1080403, 0x81C, 0xF00A0403, 0x81C, 0xEF0C0403,
- 0x81C, 0xEE0E0403, 0x81C, 0xED100403, 0x81C, 0xEC120403,
- 0x81C, 0xEB140403, 0x81C, 0xEA160403, 0x81C, 0xE9180403,
- 0x81C, 0xE81A0403, 0x81C, 0xE71C0403, 0x81C, 0xE61E0403,
- 0x81C, 0xE5200403, 0x81C, 0xE4220403, 0x81C, 0xE3240403,
- 0x81C, 0xE2260403, 0x81C, 0xE1280403, 0x81C, 0xE02A0403,
- 0x81C, 0xC32C0403, 0x81C, 0xC22E0403, 0x81C, 0xC1300403,
- 0x81C, 0xC0320403, 0x81C, 0xA4340403, 0x81C, 0xA3360403,
- 0x81C, 0xA2380403, 0x81C, 0xA13A0403, 0x81C, 0xA03C0403,
- 0x81C, 0x823E0403, 0x81C, 0x81400403, 0x81C, 0x80420403,
- 0x81C, 0x64440403, 0x81C, 0x63460403, 0x81C, 0x62480403,
- 0x81C, 0x614A0403, 0x81C, 0x604C0403, 0x81C, 0x454E0403,
- 0x81C, 0x44500403, 0x81C, 0x43520403, 0x81C, 0x42540403,
- 0x81C, 0x41560403, 0x81C, 0x40580403, 0x81C, 0x055A0403,
- 0x81C, 0x045C0403, 0x81C, 0x035E0403, 0x81C, 0x02600403,
- 0x81C, 0x01620403, 0x81C, 0x00640403, 0x81C, 0x00660403,
- 0x81C, 0x00680403, 0x81C, 0x006A0403, 0x81C, 0x006C0403,
- 0x81C, 0x006E0403, 0x81C, 0x00700403, 0x81C, 0x00720403,
- 0x81C, 0x00740403, 0x81C, 0x00760403, 0x81C, 0x00780403,
- 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403,
- 0x81C, 0xFF000403, 0x81C, 0xFF020403, 0x81C, 0xFE040403,
- 0x81C, 0xFD060403, 0x81C, 0xFC080403, 0x81C, 0xFB0A0403,
- 0x81C, 0xFA0C0403, 0x81C, 0xF90E0403, 0x81C, 0xF8100403,
- 0x81C, 0xF7120403, 0x81C, 0xF6140403, 0x81C, 0xF5160403,
- 0x81C, 0xF4180403, 0x81C, 0xF31A0403, 0x81C, 0xF21C0403,
- 0x81C, 0xD51E0403, 0x81C, 0xD4200403, 0x81C, 0xD3220403,
- 0x81C, 0xD2240403, 0x81C, 0xB6260403, 0x81C, 0xB5280403,
- 0x81C, 0xB42A0403, 0x81C, 0xB32C0403, 0x81C, 0xB22E0403,
- 0x81C, 0xB1300403, 0x81C, 0xB0320403, 0x81C, 0xAF340403,
- 0x81C, 0xAE360403, 0x81C, 0xAD380403, 0x81C, 0xAC3A0403,
- 0x81C, 0xAB3C0403, 0x81C, 0xAA3E0403, 0x81C, 0xA9400403,
- 0x81C, 0xA8420403, 0x81C, 0xA7440403, 0x81C, 0xA6460403,
- 0x81C, 0xA5480403, 0x81C, 0xA44A0403, 0x81C, 0xA34C0403,
- 0x81C, 0x854E0403, 0x81C, 0x84500403, 0x81C, 0x83520403,
- 0x81C, 0x82540403, 0x81C, 0x81560403, 0x81C, 0x80580403,
- 0x81C, 0x485A0403, 0x81C, 0x475C0403, 0x81C, 0x465E0403,
- 0x81C, 0x45600403, 0x81C, 0x44620403, 0x81C, 0x0A640403,
- 0x81C, 0x09660403, 0x81C, 0x08680403, 0x81C, 0x076A0403,
- 0x81C, 0x066C0403, 0x81C, 0x056E0403, 0x81C, 0x04700403,
- 0x81C, 0x03720403, 0x81C, 0x02740403, 0x81C, 0x01760403,
- 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403,
- 0x81C, 0x007E0403, 0x90012100, 0x00000000, 0x40000000, 0x00000000,
- 0x81C, 0xFF000403, 0x81C, 0xFF000403, 0x81C, 0xFF020403,
- 0x81C, 0xFE040403, 0x81C, 0xFD060403, 0x81C, 0xFC080403,
- 0x81C, 0xFB0A0403, 0x81C, 0xFA0C0403, 0x81C, 0xF90E0403,
- 0x81C, 0xF8100403, 0x81C, 0xF7120403, 0x81C, 0xF6140403,
- 0x81C, 0xF5160403, 0x81C, 0xF4180403, 0x81C, 0xF31A0403,
- 0x81C, 0xF21C0403, 0x81C, 0xD51E0403, 0x81C, 0xD4200403,
- 0x81C, 0xD3220403, 0x81C, 0xD2240403, 0x81C, 0xB6260403,
- 0x81C, 0xB5280403, 0x81C, 0xB42A0403, 0x81C, 0xB32C0403,
- 0x81C, 0xB22E0403, 0x81C, 0xB1300403, 0x81C, 0xB0320403,
- 0x81C, 0xAF340403, 0x81C, 0xAE360403, 0x81C, 0xAD380403,
- 0x81C, 0xAC3A0403, 0x81C, 0xAB3C0403, 0x81C, 0xAA3E0403,
- 0x81C, 0xA9400403, 0x81C, 0xA8420403, 0x81C, 0xA7440403,
- 0x81C, 0xA6460403, 0x81C, 0xA5480403, 0x81C, 0xA44A0403,
- 0x81C, 0xA34C0403, 0x81C, 0x854E0403, 0x81C, 0x84500403,
- 0x81C, 0x83520403, 0x81C, 0x82540403, 0x81C, 0x81560403,
- 0x81C, 0x80580403, 0x81C, 0x485A0403, 0x81C, 0x475C0403,
- 0x81C, 0x465E0403, 0x81C, 0x45600403, 0x81C, 0x44620403,
- 0x81C, 0x0A640403, 0x81C, 0x09660403, 0x81C, 0x08680403,
- 0x81C, 0x076A0403, 0x81C, 0x066C0403, 0x81C, 0x056E0403,
- 0x81C, 0x04700403, 0x81C, 0x03720403, 0x81C, 0x02740403,
- 0x81C, 0x01760403, 0x81C, 0x00780403, 0x81C, 0x007A0403,
- 0x81C, 0x007C0403, 0x81C, 0x007E0403, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xF5000403,
- 0x81C, 0xF4020403, 0x81C, 0xF3040403, 0x81C, 0xF2060403,
- 0x81C, 0xF1080403, 0x81C, 0xF00A0403, 0x81C, 0xEF0C0403,
- 0x81C, 0xEE0E0403, 0x81C, 0xED100403, 0x81C, 0xEC120403,
- 0x81C, 0xEB140403, 0x81C, 0xEA160403, 0x81C, 0xE9180403,
- 0x81C, 0xE81A0403, 0x81C, 0xE71C0403, 0x81C, 0xE61E0403,
- 0x81C, 0xE5200403, 0x81C, 0xE4220403, 0x81C, 0xE3240403,
- 0x81C, 0xE2260403, 0x81C, 0xE1280403, 0x81C, 0xE02A0403,
- 0x81C, 0xC32C0403, 0x81C, 0xC22E0403, 0x81C, 0xC1300403,
- 0x81C, 0xC0320403, 0x81C, 0xA4340403, 0x81C, 0xA3360403,
- 0x81C, 0xA2380403, 0x81C, 0xA13A0403, 0x81C, 0xA03C0403,
- 0x81C, 0x823E0403, 0x81C, 0x81400403, 0x81C, 0x80420403,
- 0x81C, 0x64440403, 0x81C, 0x63460403, 0x81C, 0x62480403,
- 0x81C, 0x614A0403, 0x81C, 0x604C0403, 0x81C, 0x454E0403,
- 0x81C, 0x44500403, 0x81C, 0x43520403, 0x81C, 0x42540403,
- 0x81C, 0x41560403, 0x81C, 0x40580403, 0x81C, 0x055A0403,
- 0x81C, 0x045C0403, 0x81C, 0x035E0403, 0x81C, 0x02600403,
- 0x81C, 0x01620403, 0x81C, 0x00640403, 0x81C, 0x00660403,
- 0x81C, 0x00680403, 0x81C, 0x006A0403, 0x81C, 0x006C0403,
- 0x81C, 0x006E0403, 0x81C, 0x00700403, 0x81C, 0x00720403,
- 0x81C, 0x00740403, 0x81C, 0x00760403, 0x81C, 0x00780403,
- 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
- 0x90011000, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000403,
- 0x81C, 0xFF000403, 0x81C, 0xFF020403, 0x81C, 0xFE040403,
- 0x81C, 0xFD060403, 0x81C, 0xFC080403, 0x81C, 0xFB0A0403,
- 0x81C, 0xFA0C0403, 0x81C, 0xF90E0403, 0x81C, 0xF8100403,
- 0x81C, 0xF7120403, 0x81C, 0xF6140403, 0x81C, 0xF5160403,
- 0x81C, 0xF4180403, 0x81C, 0xF31A0403, 0x81C, 0xF21C0403,
- 0x81C, 0xD51E0403, 0x81C, 0xD4200403, 0x81C, 0xD3220403,
- 0x81C, 0xD2240403, 0x81C, 0xB6260403, 0x81C, 0xB5280403,
- 0x81C, 0xB42A0403, 0x81C, 0xB32C0403, 0x81C, 0xB22E0403,
- 0x81C, 0xB1300403, 0x81C, 0xB0320403, 0x81C, 0xAF340403,
- 0x81C, 0xAE360403, 0x81C, 0xAD380403, 0x81C, 0xAC3A0403,
- 0x81C, 0xAB3C0403, 0x81C, 0xAA3E0403, 0x81C, 0xA9400403,
- 0x81C, 0xA8420403, 0x81C, 0xA7440403, 0x81C, 0xA6460403,
- 0x81C, 0xA5480403, 0x81C, 0xA44A0403, 0x81C, 0xA34C0403,
- 0x81C, 0x854E0403, 0x81C, 0x84500403, 0x81C, 0x83520403,
- 0x81C, 0x82540403, 0x81C, 0x81560403, 0x81C, 0x80580403,
- 0x81C, 0x485A0403, 0x81C, 0x475C0403, 0x81C, 0x465E0403,
- 0x81C, 0x45600403, 0x81C, 0x44620403, 0x81C, 0x0A640403,
- 0x81C, 0x09660403, 0x81C, 0x08680403, 0x81C, 0x076A0403,
- 0x81C, 0x066C0403, 0x81C, 0x056E0403, 0x81C, 0x04700403,
- 0x81C, 0x03720403, 0x81C, 0x02740403, 0x81C, 0x01760403,
- 0x81C, 0x00780403, 0x81C, 0x007A0403, 0x81C, 0x007C0403,
- 0x81C, 0x007E0403, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
- 0x81C, 0xFF000403, 0x81C, 0xFF000403, 0x81C, 0xFF020403,
- 0x81C, 0xFE040403, 0x81C, 0xFD060403, 0x81C, 0xFC080403,
- 0x81C, 0xFB0A0403, 0x81C, 0xFA0C0403, 0x81C, 0xF90E0403,
- 0x81C, 0xF8100403, 0x81C, 0xF7120403, 0x81C, 0xF6140403,
- 0x81C, 0xF5160403, 0x81C, 0xF4180403, 0x81C, 0xF31A0403,
- 0x81C, 0xF21C0403, 0x81C, 0xD51E0403, 0x81C, 0xD4200403,
- 0x81C, 0xD3220403, 0x81C, 0xD2240403, 0x81C, 0xB6260403,
- 0x81C, 0xB5280403, 0x81C, 0xB42A0403, 0x81C, 0xB32C0403,
- 0x81C, 0xB22E0403, 0x81C, 0xB1300403, 0x81C, 0xB0320403,
- 0x81C, 0xAF340403, 0x81C, 0xAE360403, 0x81C, 0xAD380403,
- 0x81C, 0xAC3A0403, 0x81C, 0xAB3C0403, 0x81C, 0xAA3E0403,
- 0x81C, 0xA9400403, 0x81C, 0xA8420403, 0x81C, 0xA7440403,
- 0x81C, 0xA6460403, 0x81C, 0xA5480403, 0x81C, 0xA44A0403,
- 0x81C, 0xA34C0403, 0x81C, 0x854E0403, 0x81C, 0x84500403,
- 0x81C, 0x83520403, 0x81C, 0x82540403, 0x81C, 0x81560403,
- 0x81C, 0x80580403, 0x81C, 0x485A0403, 0x81C, 0x475C0403,
- 0x81C, 0x465E0403, 0x81C, 0x45600403, 0x81C, 0x44620403,
- 0x81C, 0x0A640403, 0x81C, 0x09660403, 0x81C, 0x08680403,
- 0x81C, 0x076A0403, 0x81C, 0x066C0403, 0x81C, 0x056E0403,
- 0x81C, 0x04700403, 0x81C, 0x03720403, 0x81C, 0x02740403,
- 0x81C, 0x01760403, 0x81C, 0x00780403, 0x81C, 0x007A0403,
- 0x81C, 0x007C0403, 0x81C, 0x007E0403, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xFF000403,
- 0x81C, 0xFF020403, 0x81C, 0xFE040403, 0x81C, 0xFD060403,
- 0x81C, 0xFC080403, 0x81C, 0xFB0A0403, 0x81C, 0xFA0C0403,
- 0x81C, 0xF90E0403, 0x81C, 0xF8100403, 0x81C, 0xF7120403,
- 0x81C, 0xF6140403, 0x81C, 0xF5160403, 0x81C, 0xF4180403,
- 0x81C, 0xF31A0403, 0x81C, 0xF21C0403, 0x81C, 0xD51E0403,
- 0x81C, 0xD4200403, 0x81C, 0xD3220403, 0x81C, 0xD2240403,
- 0x81C, 0xB6260403, 0x81C, 0xB5280403, 0x81C, 0xB42A0403,
- 0x81C, 0xB32C0403, 0x81C, 0xB22E0403, 0x81C, 0xB1300403,
- 0x81C, 0xB0320403, 0x81C, 0xAF340403, 0x81C, 0xAE360403,
- 0x81C, 0xAD380403, 0x81C, 0xAC3A0403, 0x81C, 0xAB3C0403,
- 0x81C, 0xAA3E0403, 0x81C, 0xA9400403, 0x81C, 0xA8420403,
- 0x81C, 0xA7440403, 0x81C, 0xA6460403, 0x81C, 0xA5480403,
- 0x81C, 0xA44A0403, 0x81C, 0xA34C0403, 0x81C, 0x854E0403,
- 0x81C, 0x84500403, 0x81C, 0x83520403, 0x81C, 0x82540403,
- 0x81C, 0x81560403, 0x81C, 0x80580403, 0x81C, 0x485A0403,
- 0x81C, 0x475C0403, 0x81C, 0x465E0403, 0x81C, 0x45600403,
- 0x81C, 0x44620403, 0x81C, 0x0A640403, 0x81C, 0x09660403,
- 0x81C, 0x08680403, 0x81C, 0x076A0403, 0x81C, 0x066C0403,
- 0x81C, 0x056E0403, 0x81C, 0x04700403, 0x81C, 0x03720403,
- 0x81C, 0x02740403, 0x81C, 0x01760403, 0x81C, 0x00780403,
- 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
- 0xA0000000, 0x00000000, 0x81C, 0xFF000403, 0x81C, 0xFF000403,
- 0x81C, 0xFF020403, 0x81C, 0xFE040403, 0x81C, 0xFD060403,
- 0x81C, 0xFC080403, 0x81C, 0xFB0A0403, 0x81C, 0xFA0C0403,
- 0x81C, 0xF90E0403, 0x81C, 0xF8100403, 0x81C, 0xF7120403,
- 0x81C, 0xF6140403, 0x81C, 0xF5160403, 0x81C, 0xF4180403,
- 0x81C, 0xF31A0403, 0x81C, 0xF21C0403, 0x81C, 0xD51E0403,
- 0x81C, 0xD4200403, 0x81C, 0xD3220403, 0x81C, 0xD2240403,
- 0x81C, 0xB6260403, 0x81C, 0xB5280403, 0x81C, 0xB42A0403,
- 0x81C, 0xB32C0403, 0x81C, 0xB22E0403, 0x81C, 0xB1300403,
- 0x81C, 0xB0320403, 0x81C, 0xAF340403, 0x81C, 0xAE360403,
- 0x81C, 0xAD380403, 0x81C, 0xAC3A0403, 0x81C, 0xAB3C0403,
- 0x81C, 0xAA3E0403, 0x81C, 0xA9400403, 0x81C, 0xA8420403,
- 0x81C, 0xA7440403, 0x81C, 0xA6460403, 0x81C, 0xA5480403,
- 0x81C, 0xA44A0403, 0x81C, 0xA34C0403, 0x81C, 0x854E0403,
- 0x81C, 0x84500403, 0x81C, 0x83520403, 0x81C, 0x82540403,
- 0x81C, 0x81560403, 0x81C, 0x80580403, 0x81C, 0x485A0403,
- 0x81C, 0x475C0403, 0x81C, 0x465E0403, 0x81C, 0x45600403,
- 0x81C, 0x44620403, 0x81C, 0x0A640403, 0x81C, 0x09660403,
- 0x81C, 0x08680403, 0x81C, 0x076A0403, 0x81C, 0x066C0403,
- 0x81C, 0x056E0403, 0x81C, 0x04700403, 0x81C, 0x03720403,
- 0x81C, 0x02740403, 0x81C, 0x01760403, 0x81C, 0x00780403,
- 0x81C, 0x007A0403, 0x81C, 0x007C0403, 0x81C, 0x007E0403,
- 0xB0000000, 0x00000000, 0xC50, 0x00000022, 0xC50, 0x00000020,
- 0xE50, 0x00000022, 0xE50, 0x00000020,
-
-};
-
-void odm_read_and_config_mp_8822b_agc_tab(struct phy_dm_struct *dm)
-{
- u32 i = 0;
- u8 c_cond;
- bool is_matched = true, is_skipped = false;
- u32 *array = array_mp_8822b_agc_tab;
-
- u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===> %s\n", __func__);
-
- for (; (i + 1) < ARRAY_SIZE(array_mp_8822b_agc_tab); i = i + 2) {
- v1 = array[i];
- v2 = array[i + 1];
-
- if (v1 & BIT(31)) { /* positive condition*/
- c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
- if (c_cond == COND_ENDIF) { /*end*/
- is_matched = true;
- is_skipped = false;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
- } else if (c_cond == COND_ELSE) { /*else*/
- is_matched = is_skipped ? false : true;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
- } else { /*if , else if*/
- pre_v1 = v1;
- pre_v2 = v2;
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "IF or ELSE IF\n");
- }
- } else if (v1 & BIT(30)) { /*negative condition*/
- if (is_skipped) {
- is_matched = false;
- continue;
- }
-
- if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
- is_matched = true;
- is_skipped = true;
- } else {
- is_matched = false;
- is_skipped = false;
- }
- } else if (is_matched) {
- odm_config_bb_agc_8822b(dm, v1, MASKDWORD, v2);
- }
- }
-}
-
-u32 odm_get_version_mp_8822b_agc_tab(void) { return 67; }
-
-/******************************************************************************
- * phy_reg.TXT
- ******************************************************************************/
-
-static u32 array_mp_8822b_phy_reg[] = {
- 0x800, 0x9020D010, 0x804, 0x800181A0, 0x808, 0x0E028233,
- 0x80C, 0x10000013, 0x810, 0x21101263, 0x814, 0x020C3D10,
- 0x818, 0x84A10385, 0x81C, 0x1E1E081F, 0x820, 0x0001AAAA,
- 0x824, 0x00030FE0, 0x828, 0x0000CCCC, 0x82C, 0x75CB7010,
- 0x830, 0x79A0EA2A, 0x834, 0x072E6986, 0x838, 0x87766441,
- 0x83C, 0x9194B2B6, 0x840, 0x171740E0, 0x844, 0x4D3D7CDB,
- 0x848, 0x4AD0408B, 0x84C, 0x6AFBF7A5, 0x850, 0x28A74706,
- 0x854, 0x0001520C, 0x858, 0x4060C000, 0x85C, 0x74010160,
- 0x860, 0x68A7C321, 0x864, 0x79F27432, 0x868, 0x8CA7A314,
- 0x86C, 0x778C2878, 0x870, 0x77777777, 0x874, 0x27612C2E,
- 0x878, 0xC0003152, 0x87C, 0x5C8FC000, 0x880, 0x00000000,
- 0x884, 0x00000000, 0x888, 0x00000000, 0x88C, 0x00000000,
- 0x890, 0x00000000, 0x894, 0x00000000, 0x898, 0x00000000,
- 0x89C, 0x00000000, 0x8A0, 0x00000013, 0x8A4, 0x7F7F7F7F,
- 0x8A8, 0x2202033E, 0x8AC, 0xF00F000A, 0x8B0, 0x00000600,
- 0x8B4, 0x000FC080, 0x8B8, 0xEC0057F7, 0x8BC, 0xACB520A3,
- 0x8C0, 0xFFE04020, 0x8C4, 0x47C00000, 0x8C8, 0x000251A5,
- 0x8CC, 0x08108000, 0x8D0, 0x0000B800, 0x8D4, 0x860308A0,
- 0x8D8, 0x21095612, 0x8DC, 0x00000000, 0x8E0, 0x32D16777,
- 0x8E4, 0x4C098935, 0x8E8, 0xFFFFC42C, 0x8EC, 0x99999999,
- 0x8F0, 0x00009999, 0x8F4, 0x00D80FA1, 0x8F8, 0x40000080,
- 0x8FC, 0x00000130, 0x900, 0x00800000, 0x904, 0x00000000,
- 0x908, 0x00000000, 0x90C, 0xD3000000, 0x910, 0x0000FC00,
- 0x914, 0xC6380000, 0x918, 0x1C1028C0, 0x91C, 0x64B11A1C,
- 0x920, 0xE0767233, 0x924, 0x855A2500, 0x928, 0x4AB0E4E4,
- 0x92C, 0xFFFEB200, 0x930, 0xFFFFFFFE, 0x934, 0x001FFFFF,
- 0x938, 0x00008480, 0x93C, 0xE41C0642, 0x940, 0x0E470430,
- 0x944, 0x00000000, 0x948, 0xAC000000, 0x94C, 0x10000083,
- 0x950, 0x32010080, 0x954, 0x84510080, 0x958, 0x00000001,
- 0x95C, 0x04248000, 0x960, 0x00000000, 0x964, 0x00000000,
- 0x968, 0x00000000, 0x96C, 0x00000000, 0x970, 0x00001FFF,
- 0x974, 0x44000FFF, 0x978, 0x00000000, 0x97C, 0x00000000,
- 0x980, 0x00000000, 0x984, 0x00000000, 0x988, 0x00000000,
- 0x98C, 0x23440000, 0x990, 0x27100000, 0x994, 0xFFFF0100,
- 0x998, 0xFFFFFF5C, 0x99C, 0xFFFFFFFF, 0x9A0, 0x000000FF,
- 0x9A4, 0x80000088, 0x9A8, 0x0C2F0000, 0x9AC, 0x01560000,
- 0x9B0, 0x70000000, 0x9B4, 0x00000000, 0x9B8, 0x00000000,
- 0x9BC, 0x00000000, 0x9C0, 0x00000000, 0x9C4, 0x00000000,
- 0x9C8, 0x00000000, 0x9CC, 0x00000000, 0x9D0, 0x00000000,
- 0x9D4, 0x00000000, 0x9D8, 0x00000000, 0x9DC, 0x00000000,
- 0x9E0, 0x00000000, 0x9E4, 0x02000402, 0x9E8, 0x000022D4,
- 0x9EC, 0x00000000, 0x9F0, 0x00010080, 0x9F4, 0x00000000,
- 0x9F8, 0x00000000, 0x9FC, 0xEFFFF7F7, 0xA00, 0x00D047C8,
- 0xA04, 0x81FF800C, 0xA08, 0x8C838300, 0xA0C, 0x2E20100F,
- 0xA10, 0x9500BB78, 0xA14, 0x1114D028, 0xA18, 0x00881117,
- 0xA1C, 0x89140F00, 0xA20, 0x84880000, 0xA24, 0x384F6577,
- 0xA28, 0x00001525, 0xA2C, 0x00920000, 0xA70, 0x101FFF00,
- 0xA74, 0x00000148, 0xA78, 0x00000900, 0xA7C, 0x225B0606,
- 0xA80, 0x218675B2, 0xA84, 0x80208C00, 0xA88, 0x040C0000,
- 0xA8C, 0x12345678, 0xA90, 0xABCDEF00, 0xA94, 0x001B1B89,
- 0xA98, 0x030A0000, 0xA9C, 0x00060000, 0xAA0, 0x00000000,
- 0xAA4, 0x0004000F, 0xAA8, 0x00000200, 0xB00, 0xE1000440,
- 0xB04, 0x00800000, 0xB08, 0xFF02030B, 0xB0C, 0x01EAA406,
- 0xB10, 0x00030690, 0xB14, 0x006000FA, 0xB18, 0x00000002,
- 0xB1C, 0x00000002, 0xB20, 0x4B00001F, 0xB24, 0x4E8E3E40,
- 0xB28, 0x03020100, 0xB2C, 0x07060504, 0xB30, 0x0B0A0908,
- 0xB34, 0x0F0E0D0C, 0xB38, 0x13121110, 0xB3C, 0x0000003A,
- 0xB40, 0x00000000, 0xB44, 0x80000000, 0xB48, 0x3F0000FA,
- 0xB4C, 0x88C80020, 0xB50, 0x00000000, 0xB54, 0x00004241,
- 0xB58, 0xE0008208, 0xB5C, 0x41EFFFF9, 0xB60, 0x00000000,
- 0xB64, 0x00200063, 0xB68, 0x0000003A, 0xB6C, 0x00000102,
- 0xB70, 0x4E6D1870, 0xB74, 0x03020100, 0xB78, 0x07060504,
- 0xB7C, 0x0B0A0908, 0xB80, 0x0F0E0D0C, 0xB84, 0x13121110,
- 0xB88, 0x00000000, 0xB8C, 0x00000000, 0xC00, 0x00000007,
- 0xC04, 0x00000020, 0xC08, 0x60403231, 0xC0C, 0x00012345,
- 0xC10, 0x00000100, 0xC14, 0x01000000, 0xC18, 0x00000000,
- 0xC1C, 0x40040053, 0xC20, 0x40020103, 0xC24, 0x00000000,
- 0xC28, 0x00000000, 0xC2C, 0x00000000, 0xC30, 0x00000000,
- 0xC34, 0x00000000, 0xC38, 0x00000000, 0xC3C, 0x00000000,
- 0xC40, 0x00000000, 0xC44, 0x00000000, 0xC48, 0x00000000,
- 0xC4C, 0x00000000, 0xC50, 0x00000020, 0xC54, 0x00000000,
- 0xC58, 0xD8020402, 0xC5C, 0xDE000120, 0xC68, 0x5979993F,
- 0xC6C, 0x0000122A, 0xC70, 0x99795979, 0xC74, 0x99795979,
- 0xC78, 0x99799979, 0xC7C, 0x99791979, 0xC80, 0x19791979,
- 0xC84, 0x19791979, 0xC88, 0x00000000, 0xC8C, 0x07000000,
- 0xC94, 0x01000100, 0xC98, 0x201C8000, 0xC9C, 0x00000000,
- 0xCA0, 0x0000A555, 0xCA4, 0x08040201, 0xCA8, 0x80402010,
- 0xCAC, 0x00000000, 0xCB0, 0x77777777, 0xCB4, 0x00007777,
- 0xCB8, 0x00000000, 0xCBC, 0x00000000, 0xCC0, 0x00000000,
- 0xCC4, 0x00000000, 0xCC8, 0x00000000, 0xCCC, 0x00000000,
- 0xCD0, 0x00000000, 0xCD4, 0x00000000, 0xCD8, 0x00000000,
- 0xCDC, 0x00000000, 0xCE0, 0x00000000, 0xCE4, 0x00000000,
- 0xCE8, 0x00000000, 0xCEC, 0x00000000, 0xE00, 0x00000007,
- 0xE04, 0x00000020, 0xE08, 0x60403231, 0xE0C, 0x00012345,
- 0xE10, 0x00000100, 0xE14, 0x01000000, 0xE18, 0x00000000,
- 0xE1C, 0x40040053, 0xE20, 0x40020103, 0xE24, 0x00000000,
- 0xE28, 0x00000000, 0xE2C, 0x00000000, 0xE30, 0x00000000,
- 0xE34, 0x00000000, 0xE38, 0x00000000, 0xE3C, 0x00000000,
- 0xE40, 0x00000000, 0xE44, 0x00000000, 0xE48, 0x00000000,
- 0xE4C, 0x00000000, 0xE50, 0x00000020, 0xE54, 0x00000000,
- 0xE58, 0xD8020402, 0xE5C, 0xDE000120, 0xE68, 0x5979993F,
- 0xE6C, 0x0000122A, 0xE70, 0x99795979, 0xE74, 0x99795979,
- 0xE78, 0x99799979, 0xE7C, 0x99791979, 0xE80, 0x19791979,
- 0xE84, 0x19791979, 0xE88, 0x00000000, 0xE8C, 0x07000000,
- 0xE94, 0x01000100, 0xE98, 0x201C8000, 0xE9C, 0x00000000,
- 0xEA0, 0x0000A555, 0xEA4, 0x08040201, 0xEA8, 0x80402010,
- 0xEAC, 0x00000000, 0xEB0, 0x77777777, 0xEB4, 0x00007777,
- 0xEB8, 0x00000000, 0xEBC, 0x00000000, 0xEC0, 0x00000000,
- 0xEC4, 0x00000000, 0xEC8, 0x00000000, 0xECC, 0x00000000,
- 0xED0, 0x00000000, 0xED4, 0x00000000, 0xED8, 0x00000000,
- 0xEDC, 0x00000000, 0xEE0, 0x00000000, 0xEE4, 0x00000000,
- 0xEE8, 0x00000000, 0xEEC, 0x00000000, 0x1900, 0x00000000,
- 0x1904, 0x00238000, 0x1908, 0x00000000, 0x190C, 0x00000000,
- 0x1910, 0x00000000, 0x1914, 0x00000000, 0x1918, 0x00000000,
- 0x191C, 0x00000000, 0x1920, 0x00000000, 0x1924, 0x00000000,
- 0x1928, 0x00000000, 0x192C, 0x00000000, 0x1930, 0x00000000,
- 0x1934, 0x00000000, 0x1938, 0x00000000, 0x193C, 0x00000000,
- 0x1940, 0x00000000, 0x1944, 0x00000000, 0x1948, 0x00000000,
- 0x194C, 0x00000000, 0x1950, 0x00000000, 0x1954, 0x00000000,
- 0x1958, 0x00000000, 0x195C, 0x00000000, 0x1960, 0x00000000,
- 0x1964, 0x00000000, 0x1968, 0x00000000, 0x196C, 0x00000000,
- 0x1970, 0x00000000, 0x1974, 0x00000000, 0x1978, 0x00000000,
- 0x197C, 0x00000000, 0x1980, 0x00000000, 0x1984, 0x03000000,
- 0x1988, 0x21401E88, 0x198C, 0x00004000, 0x1990, 0x00000000,
- 0x1994, 0x00000000, 0x1998, 0x00000053, 0x199C, 0x00000000,
- 0x19A0, 0x00000000, 0x19A4, 0x00000000, 0x19A8, 0x00000000,
- 0x19AC, 0x0E47E47F, 0x19B0, 0x00000000, 0x19B4, 0x0E47E47F,
- 0x19B8, 0x00000000, 0x19BC, 0x00000000, 0x19C0, 0x00000000,
- 0x19C4, 0x00000000, 0x19C8, 0x00000000, 0x19CC, 0x00000000,
- 0x19D0, 0x00000000, 0x19D4, 0xAAAAAAAA, 0x19D8, 0x00000AAA,
- 0x19DC, 0x133E0F37, 0x19E0, 0x00000000, 0x19E4, 0x00000000,
- 0x19E8, 0x00000000, 0x19EC, 0x00000000, 0x19F0, 0x00000000,
- 0x19F4, 0x00000000, 0x19F8, 0x01A00000, 0x19FC, 0x00000000,
- 0x1C00, 0x00000100, 0x1C04, 0x01000000, 0x1C08, 0x00000100,
- 0x1C0C, 0x01000000, 0x1C10, 0x00000100, 0x1C14, 0x01000000,
- 0x1C18, 0x00000100, 0x1C1C, 0x01000000, 0x1C20, 0x00000100,
- 0x1C24, 0x01000000, 0x1C28, 0x00000100, 0x1C2C, 0x01000000,
- 0x1C30, 0x00000100, 0x1C34, 0x01000000, 0x1C38, 0x00000000,
- 0x1C3C, 0x00000000, 0x1C40, 0x000C0100, 0x1C44, 0x000000F3,
- 0x1C48, 0x1A8249A8, 0x1C4C, 0x1461C826, 0x1C50, 0x0001469E,
- 0x1C54, 0x58D158D1, 0x1C58, 0x04490088, 0x1C5C, 0x04004400,
- 0x1C60, 0x00000000, 0x1C64, 0x04004400, 0x1C68, 0x00000100,
- 0x1C6C, 0x01000000, 0x1C70, 0x00000100, 0x1C74, 0x01000000,
- 0x1C78, 0x00000000, 0x1C7C, 0x00000010, 0x1C80, 0x5FFF5FFF,
- 0x1C84, 0x5FFF5FFF, 0x1C88, 0x5FFF5FFF, 0x1C8C, 0x5FFF5FFF,
- 0x1C90, 0x5FFF5FFF, 0x1C94, 0x5FFF5FFF, 0x1C98, 0x5FFF5FFF,
- 0x1C9C, 0x5FFF5FFF, 0x1CA0, 0x00000100, 0x1CA4, 0x01000000,
- 0x1CA8, 0x00000100, 0x1CAC, 0x5FFF5FFF, 0x1CB0, 0x00000100,
- 0x1CB4, 0x01000000, 0x1CB8, 0x00000000, 0x1CBC, 0x00000000,
- 0x1CC0, 0x00000100, 0x1CC4, 0x01000000, 0x1CC8, 0x00000100,
- 0x1CCC, 0x01000000, 0x1CD0, 0x00000100, 0x1CD4, 0x01000000,
- 0x1CD8, 0x00000100, 0x1CDC, 0x01000000, 0x1CE0, 0x00000100,
- 0x1CE4, 0x01000000, 0x1CE8, 0x00000100, 0x1CEC, 0x01000000,
- 0x1CF0, 0x00000100, 0x1CF4, 0x01000000, 0x1CF8, 0x00000000,
- 0x1CFC, 0x00000000, 0xC60, 0x70038040, 0xC60, 0x70038040,
- 0xC60, 0x70146040, 0xC60, 0x70246040, 0xC60, 0x70346040,
- 0xC60, 0x70446040, 0xC60, 0x70532040, 0xC60, 0x70646040,
- 0xC60, 0x70738040, 0xC60, 0x70838040, 0xC60, 0x70938040,
- 0xC60, 0x70A38040, 0xC60, 0x70B36040, 0xC60, 0x70C06040,
- 0xC60, 0x70D06040, 0xC60, 0x70E76040, 0xC60, 0x70F06040,
- 0xE60, 0x70038040, 0xE60, 0x70038040, 0xE60, 0x70146040,
- 0xE60, 0x70246040, 0xE60, 0x70346040, 0xE60, 0x70446040,
- 0xE60, 0x70532040, 0xE60, 0x70646040, 0xE60, 0x70738040,
- 0xE60, 0x70838040, 0xE60, 0x70938040, 0xE60, 0x70A38040,
- 0xE60, 0x70B36040, 0xE60, 0x70C06040, 0xE60, 0x70D06040,
- 0xE60, 0x70E76040, 0xE60, 0x70F06040, 0xC64, 0x00800000,
- 0xC64, 0x08800001, 0xC64, 0x00800002, 0xC64, 0x00800003,
- 0xC64, 0x00800004, 0xC64, 0x00800005, 0xC64, 0x00800006,
- 0xC64, 0x08800007, 0xC64, 0x00004000, 0xE64, 0x00800000,
- 0xE64, 0x08800001, 0xE64, 0x00800002, 0xE64, 0x00800003,
- 0xE64, 0x00800004, 0xE64, 0x00800005, 0xE64, 0x00800006,
- 0xE64, 0x08800007, 0xE64, 0x00004000, 0x1B00, 0xF8000008,
- 0x1B00, 0xF80A7008, 0x1B00, 0xF8015008, 0x1B00, 0xF8000008,
- 0x1B04, 0xE24629D2, 0x1B08, 0x00000080, 0x1B0C, 0x00000000,
- 0x1B10, 0x00010C00, 0x1B14, 0x00000000, 0x1B18, 0x00292903,
- 0x1B1C, 0xA2193C32, 0x1B20, 0x01840008, 0x1B24, 0x01860008,
- 0x1B28, 0x80060300, 0x1B2C, 0x00000003, 0x1B30, 0x20000000,
- 0x1B34, 0x00000800, 0x1B3C, 0x20000000, 0x1BC0, 0x01000000,
- 0x1BCC, 0x00000000, 0x1B00, 0xF800000A, 0x1B1C, 0xA2193C32,
- 0x1B20, 0x01840008, 0x1B24, 0x01860008, 0x1B28, 0x80060300,
- 0x1B2C, 0x00000003, 0x1B30, 0x20000000, 0x1B34, 0x00000800,
- 0x1B3C, 0x20000000, 0x1BC0, 0x01000000, 0x1BCC, 0x00000000,
- 0x1B00, 0xF8000000, 0x1B80, 0x00000007, 0x1B80, 0x090A0005,
- 0x1B80, 0x090A0007, 0x1B80, 0x0FFE0015, 0x1B80, 0x0FFE0017,
- 0x1B80, 0x00220025, 0x1B80, 0x00220027, 0x1B80, 0x00040035,
- 0x1B80, 0x00040037, 0x1B80, 0x05C00045, 0x1B80, 0x05C00047,
- 0x1B80, 0x00070055, 0x1B80, 0x00070057, 0x1B80, 0x64000065,
- 0x1B80, 0x64000067, 0x1B80, 0x00020075, 0x1B80, 0x00020077,
- 0x1B80, 0x00080085, 0x1B80, 0x00080087, 0x1B80, 0x80000095,
- 0x1B80, 0x80000097, 0x1B80, 0x090800A5, 0x1B80, 0x090800A7,
- 0x1B80, 0x0F0200B5, 0x1B80, 0x0F0200B7, 0x1B80, 0x002200C5,
- 0x1B80, 0x002200C7, 0x1B80, 0x000400D5, 0x1B80, 0x000400D7,
- 0x1B80, 0x05C000E5, 0x1B80, 0x05C000E7, 0x1B80, 0x000700F5,
- 0x1B80, 0x000700F7, 0x1B80, 0x64020105, 0x1B80, 0x64020107,
- 0x1B80, 0x00020115, 0x1B80, 0x00020117, 0x1B80, 0x00040125,
- 0x1B80, 0x00040127, 0x1B80, 0x4A000135, 0x1B80, 0x4A000137,
- 0x1B80, 0x4B040145, 0x1B80, 0x4B040147, 0x1B80, 0x85030155,
- 0x1B80, 0x85030157, 0x1B80, 0x40090165, 0x1B80, 0x40090167,
- 0x1B80, 0xE0210175, 0x1B80, 0xE0210177, 0x1B80, 0x4B050185,
- 0x1B80, 0x4B050187, 0x1B80, 0x86030195, 0x1B80, 0x86030197,
- 0x1B80, 0x400B01A5, 0x1B80, 0x400B01A7, 0x1B80, 0xE02101B5,
- 0x1B80, 0xE02101B7, 0x1B80, 0x4B0001C5, 0x1B80, 0x4B0001C7,
- 0x1B80, 0x000701D5, 0x1B80, 0x000701D7, 0x1B80, 0x4C0001E5,
- 0x1B80, 0x4C0001E7, 0x1B80, 0x000401F5, 0x1B80, 0x000401F7,
- 0x1B80, 0x30000205, 0x1B80, 0x30000207, 0x1B80, 0xFE000215,
- 0x1B80, 0xFE000217, 0x1B80, 0xFF000225, 0x1B80, 0xFF000227,
- 0x1B80, 0xE1750235, 0x1B80, 0xE1750237, 0x1B80, 0xF00D0245,
- 0x1B80, 0xF00D0247, 0x1B80, 0xF10D0255, 0x1B80, 0xF10D0257,
- 0x1B80, 0xF20D0265, 0x1B80, 0xF20D0267, 0x1B80, 0xF30D0275,
- 0x1B80, 0xF30D0277, 0x1B80, 0xF40D0285, 0x1B80, 0xF40D0287,
- 0x1B80, 0xF50D0295, 0x1B80, 0xF50D0297, 0x1B80, 0xF60D02A5,
- 0x1B80, 0xF60D02A7, 0x1B80, 0xF70D02B5, 0x1B80, 0xF70D02B7,
- 0x1B80, 0xF80D02C5, 0x1B80, 0xF80D02C7, 0x1B80, 0xF90D02D5,
- 0x1B80, 0xF90D02D7, 0x1B80, 0xFA0D02E5, 0x1B80, 0xFA0D02E7,
- 0x1B80, 0xFB0D02F5, 0x1B80, 0xFB0D02F7, 0x1B80, 0x00010305,
- 0x1B80, 0x00010307, 0x1B80, 0x303D0315, 0x1B80, 0x303D0317,
- 0x1B80, 0x30550325, 0x1B80, 0x30550327, 0x1B80, 0x30A00335,
- 0x1B80, 0x30A00337, 0x1B80, 0x30A30345, 0x1B80, 0x30A30347,
- 0x1B80, 0x30570355, 0x1B80, 0x30570357, 0x1B80, 0x30620365,
- 0x1B80, 0x30620367, 0x1B80, 0x306D0375, 0x1B80, 0x306D0377,
- 0x1B80, 0x30AD0385, 0x1B80, 0x30AD0387, 0x1B80, 0x30A70395,
- 0x1B80, 0x30A70397, 0x1B80, 0x30BB03A5, 0x1B80, 0x30BB03A7,
- 0x1B80, 0x30C603B5, 0x1B80, 0x30C603B7, 0x1B80, 0x30D103C5,
- 0x1B80, 0x30D103C7, 0x1B80, 0xE11403D5, 0x1B80, 0xE11403D7,
- 0x1B80, 0x4D0403E5, 0x1B80, 0x4D0403E7, 0x1B80, 0x208003F5,
- 0x1B80, 0x208003F7, 0x1B80, 0x00000405, 0x1B80, 0x00000407,
- 0x1B80, 0x4D000415, 0x1B80, 0x4D000417, 0x1B80, 0x55070425,
- 0x1B80, 0x55070427, 0x1B80, 0xE10C0435, 0x1B80, 0xE10C0437,
- 0x1B80, 0xE10C0445, 0x1B80, 0xE10C0447, 0x1B80, 0x4D040455,
- 0x1B80, 0x4D040457, 0x1B80, 0x20880465, 0x1B80, 0x20880467,
- 0x1B80, 0x02000475, 0x1B80, 0x02000477, 0x1B80, 0x4D000485,
- 0x1B80, 0x4D000487, 0x1B80, 0x550F0495, 0x1B80, 0x550F0497,
- 0x1B80, 0xE10C04A5, 0x1B80, 0xE10C04A7, 0x1B80, 0x4F0204B5,
- 0x1B80, 0x4F0204B7, 0x1B80, 0x4E0004C5, 0x1B80, 0x4E0004C7,
- 0x1B80, 0x530204D5, 0x1B80, 0x530204D7, 0x1B80, 0x520104E5,
- 0x1B80, 0x520104E7, 0x1B80, 0xE11004F5, 0x1B80, 0xE11004F7,
- 0x1B80, 0x4D080505, 0x1B80, 0x4D080507, 0x1B80, 0x57100515,
- 0x1B80, 0x57100517, 0x1B80, 0x57000525, 0x1B80, 0x57000527,
- 0x1B80, 0x4D000535, 0x1B80, 0x4D000537, 0x1B80, 0x00010545,
- 0x1B80, 0x00010547, 0x1B80, 0xE1140555, 0x1B80, 0xE1140557,
- 0x1B80, 0x00010565, 0x1B80, 0x00010567, 0x1B80, 0x30770575,
- 0x1B80, 0x30770577, 0x1B80, 0x00230585, 0x1B80, 0x00230587,
- 0x1B80, 0xE1680595, 0x1B80, 0xE1680597, 0x1B80, 0x000205A5,
- 0x1B80, 0x000205A7, 0x1B80, 0x54E905B5, 0x1B80, 0x54E905B7,
- 0x1B80, 0x0BA605C5, 0x1B80, 0x0BA605C7, 0x1B80, 0x002305D5,
- 0x1B80, 0x002305D7, 0x1B80, 0xE16805E5, 0x1B80, 0xE16805E7,
- 0x1B80, 0x000205F5, 0x1B80, 0x000205F7, 0x1B80, 0x4D300605,
- 0x1B80, 0x4D300607, 0x1B80, 0x30900615, 0x1B80, 0x30900617,
- 0x1B80, 0x30730625, 0x1B80, 0x30730627, 0x1B80, 0x00220635,
- 0x1B80, 0x00220637, 0x1B80, 0xE1680645, 0x1B80, 0xE1680647,
- 0x1B80, 0x00020655, 0x1B80, 0x00020657, 0x1B80, 0x54E80665,
- 0x1B80, 0x54E80667, 0x1B80, 0x0BA60675, 0x1B80, 0x0BA60677,
- 0x1B80, 0x00220685, 0x1B80, 0x00220687, 0x1B80, 0xE1680695,
- 0x1B80, 0xE1680697, 0x1B80, 0x000206A5, 0x1B80, 0x000206A7,
- 0x1B80, 0x4D3006B5, 0x1B80, 0x4D3006B7, 0x1B80, 0x309006C5,
- 0x1B80, 0x309006C7, 0x1B80, 0x63F106D5, 0x1B80, 0x63F106D7,
- 0x1B80, 0xE11406E5, 0x1B80, 0xE11406E7, 0x1B80, 0xE16806F5,
- 0x1B80, 0xE16806F7, 0x1B80, 0x63F40705, 0x1B80, 0x63F40707,
- 0x1B80, 0xE1140715, 0x1B80, 0xE1140717, 0x1B80, 0xE1680725,
- 0x1B80, 0xE1680727, 0x1B80, 0x0BA80735, 0x1B80, 0x0BA80737,
- 0x1B80, 0x63F80745, 0x1B80, 0x63F80747, 0x1B80, 0xE1140755,
- 0x1B80, 0xE1140757, 0x1B80, 0xE1680765, 0x1B80, 0xE1680767,
- 0x1B80, 0x0BA90775, 0x1B80, 0x0BA90777, 0x1B80, 0x63FC0785,
- 0x1B80, 0x63FC0787, 0x1B80, 0xE1140795, 0x1B80, 0xE1140797,
- 0x1B80, 0xE16807A5, 0x1B80, 0xE16807A7, 0x1B80, 0x63FF07B5,
- 0x1B80, 0x63FF07B7, 0x1B80, 0xE11407C5, 0x1B80, 0xE11407C7,
- 0x1B80, 0xE16807D5, 0x1B80, 0xE16807D7, 0x1B80, 0x630007E5,
- 0x1B80, 0x630007E7, 0x1B80, 0xE11407F5, 0x1B80, 0xE11407F7,
- 0x1B80, 0xE1680805, 0x1B80, 0xE1680807, 0x1B80, 0x63030815,
- 0x1B80, 0x63030817, 0x1B80, 0xE1140825, 0x1B80, 0xE1140827,
- 0x1B80, 0xE1680835, 0x1B80, 0xE1680837, 0x1B80, 0xF4D40845,
- 0x1B80, 0xF4D40847, 0x1B80, 0x63070855, 0x1B80, 0x63070857,
- 0x1B80, 0xE1140865, 0x1B80, 0xE1140867, 0x1B80, 0xE1680875,
- 0x1B80, 0xE1680877, 0x1B80, 0xF5DB0885, 0x1B80, 0xF5DB0887,
- 0x1B80, 0x630B0895, 0x1B80, 0x630B0897, 0x1B80, 0xE11408A5,
- 0x1B80, 0xE11408A7, 0x1B80, 0xE16808B5, 0x1B80, 0xE16808B7,
- 0x1B80, 0x630E08C5, 0x1B80, 0x630E08C7, 0x1B80, 0xE11408D5,
- 0x1B80, 0xE11408D7, 0x1B80, 0xE16808E5, 0x1B80, 0xE16808E7,
- 0x1B80, 0x4D3008F5, 0x1B80, 0x4D3008F7, 0x1B80, 0x55010905,
- 0x1B80, 0x55010907, 0x1B80, 0x57040915, 0x1B80, 0x57040917,
- 0x1B80, 0x57000925, 0x1B80, 0x57000927, 0x1B80, 0x96000935,
- 0x1B80, 0x96000937, 0x1B80, 0x57080945, 0x1B80, 0x57080947,
- 0x1B80, 0x57000955, 0x1B80, 0x57000957, 0x1B80, 0x95000965,
- 0x1B80, 0x95000967, 0x1B80, 0x4D000975, 0x1B80, 0x4D000977,
- 0x1B80, 0x6C070985, 0x1B80, 0x6C070987, 0x1B80, 0x7B200995,
- 0x1B80, 0x7B200997, 0x1B80, 0x7A0009A5, 0x1B80, 0x7A0009A7,
- 0x1B80, 0x790009B5, 0x1B80, 0x790009B7, 0x1B80, 0x7F2009C5,
- 0x1B80, 0x7F2009C7, 0x1B80, 0x7E0009D5, 0x1B80, 0x7E0009D7,
- 0x1B80, 0x7D0009E5, 0x1B80, 0x7D0009E7, 0x1B80, 0x000109F5,
- 0x1B80, 0x000109F7, 0x1B80, 0x62850A05, 0x1B80, 0x62850A07,
- 0x1B80, 0xE1140A15, 0x1B80, 0xE1140A17, 0x1B80, 0x00010A25,
- 0x1B80, 0x00010A27, 0x1B80, 0x5C320A35, 0x1B80, 0x5C320A37,
- 0x1B80, 0xE1640A45, 0x1B80, 0xE1640A47, 0x1B80, 0xE1420A55,
- 0x1B80, 0xE1420A57, 0x1B80, 0x00010A65, 0x1B80, 0x00010A67,
- 0x1B80, 0x5C320A75, 0x1B80, 0x5C320A77, 0x1B80, 0x63F40A85,
- 0x1B80, 0x63F40A87, 0x1B80, 0x62850A95, 0x1B80, 0x62850A97,
- 0x1B80, 0x0BB00AA5, 0x1B80, 0x0BB00AA7, 0x1B80, 0xE1140AB5,
- 0x1B80, 0xE1140AB7, 0x1B80, 0xE1680AC5, 0x1B80, 0xE1680AC7,
- 0x1B80, 0x5C320AD5, 0x1B80, 0x5C320AD7, 0x1B80, 0x63FC0AE5,
- 0x1B80, 0x63FC0AE7, 0x1B80, 0x62850AF5, 0x1B80, 0x62850AF7,
- 0x1B80, 0x0BB10B05, 0x1B80, 0x0BB10B07, 0x1B80, 0xE1140B15,
- 0x1B80, 0xE1140B17, 0x1B80, 0xE1680B25, 0x1B80, 0xE1680B27,
- 0x1B80, 0x63030B35, 0x1B80, 0x63030B37, 0x1B80, 0xE1140B45,
- 0x1B80, 0xE1140B47, 0x1B80, 0xE1680B55, 0x1B80, 0xE1680B57,
- 0x1B80, 0xF7040B65, 0x1B80, 0xF7040B67, 0x1B80, 0x630B0B75,
- 0x1B80, 0x630B0B77, 0x1B80, 0xE1140B85, 0x1B80, 0xE1140B87,
- 0x1B80, 0xE1680B95, 0x1B80, 0xE1680B97, 0x1B80, 0x00010BA5,
- 0x1B80, 0x00010BA7, 0x1B80, 0x30DF0BB5, 0x1B80, 0x30DF0BB7,
- 0x1B80, 0x00230BC5, 0x1B80, 0x00230BC7, 0x1B80, 0xE16D0BD5,
- 0x1B80, 0xE16D0BD7, 0x1B80, 0x00020BE5, 0x1B80, 0x00020BE7,
- 0x1B80, 0x54E90BF5, 0x1B80, 0x54E90BF7, 0x1B80, 0x0BA60C05,
- 0x1B80, 0x0BA60C07, 0x1B80, 0x00230C15, 0x1B80, 0x00230C17,
- 0x1B80, 0xE16D0C25, 0x1B80, 0xE16D0C27, 0x1B80, 0x00020C35,
- 0x1B80, 0x00020C37, 0x1B80, 0x4D100C45, 0x1B80, 0x4D100C47,
- 0x1B80, 0x30900C55, 0x1B80, 0x30900C57, 0x1B80, 0x30D90C65,
- 0x1B80, 0x30D90C67, 0x1B80, 0x00220C75, 0x1B80, 0x00220C77,
- 0x1B80, 0xE16D0C85, 0x1B80, 0xE16D0C87, 0x1B80, 0x00020C95,
- 0x1B80, 0x00020C97, 0x1B80, 0x54E80CA5, 0x1B80, 0x54E80CA7,
- 0x1B80, 0x0BA60CB5, 0x1B80, 0x0BA60CB7, 0x1B80, 0x00220CC5,
- 0x1B80, 0x00220CC7, 0x1B80, 0xE16D0CD5, 0x1B80, 0xE16D0CD7,
- 0x1B80, 0x00020CE5, 0x1B80, 0x00020CE7, 0x1B80, 0x4D100CF5,
- 0x1B80, 0x4D100CF7, 0x1B80, 0x30900D05, 0x1B80, 0x30900D07,
- 0x1B80, 0x5C320D15, 0x1B80, 0x5C320D17, 0x1B80, 0x54F00D25,
- 0x1B80, 0x54F00D27, 0x1B80, 0x67F10D35, 0x1B80, 0x67F10D37,
- 0x1B80, 0xE1420D45, 0x1B80, 0xE1420D47, 0x1B80, 0xE16D0D55,
- 0x1B80, 0xE16D0D57, 0x1B80, 0x67F40D65, 0x1B80, 0x67F40D67,
- 0x1B80, 0xE1420D75, 0x1B80, 0xE1420D77, 0x1B80, 0xE16D0D85,
- 0x1B80, 0xE16D0D87, 0x1B80, 0x5C320D95, 0x1B80, 0x5C320D97,
- 0x1B80, 0x54F10DA5, 0x1B80, 0x54F10DA7, 0x1B80, 0x0BA80DB5,
- 0x1B80, 0x0BA80DB7, 0x1B80, 0x67F80DC5, 0x1B80, 0x67F80DC7,
- 0x1B80, 0xE1420DD5, 0x1B80, 0xE1420DD7, 0x1B80, 0xE16D0DE5,
- 0x1B80, 0xE16D0DE7, 0x1B80, 0x5C320DF5, 0x1B80, 0x5C320DF7,
- 0x1B80, 0x54F10E05, 0x1B80, 0x54F10E07, 0x1B80, 0x0BA90E15,
- 0x1B80, 0x0BA90E17, 0x1B80, 0x67FC0E25, 0x1B80, 0x67FC0E27,
- 0x1B80, 0xE1420E35, 0x1B80, 0xE1420E37, 0x1B80, 0xE16D0E45,
- 0x1B80, 0xE16D0E47, 0x1B80, 0x67FF0E55, 0x1B80, 0x67FF0E57,
- 0x1B80, 0xE1420E65, 0x1B80, 0xE1420E67, 0x1B80, 0xE16D0E75,
- 0x1B80, 0xE16D0E77, 0x1B80, 0x5C320E85, 0x1B80, 0x5C320E87,
- 0x1B80, 0x54F20E95, 0x1B80, 0x54F20E97, 0x1B80, 0x67000EA5,
- 0x1B80, 0x67000EA7, 0x1B80, 0xE1420EB5, 0x1B80, 0xE1420EB7,
- 0x1B80, 0xE16D0EC5, 0x1B80, 0xE16D0EC7, 0x1B80, 0x67030ED5,
- 0x1B80, 0x67030ED7, 0x1B80, 0xE1420EE5, 0x1B80, 0xE1420EE7,
- 0x1B80, 0xE16D0EF5, 0x1B80, 0xE16D0EF7, 0x1B80, 0xF9CC0F05,
- 0x1B80, 0xF9CC0F07, 0x1B80, 0x67070F15, 0x1B80, 0x67070F17,
- 0x1B80, 0xE1420F25, 0x1B80, 0xE1420F27, 0x1B80, 0xE16D0F35,
- 0x1B80, 0xE16D0F37, 0x1B80, 0xFAD30F45, 0x1B80, 0xFAD30F47,
- 0x1B80, 0x5C320F55, 0x1B80, 0x5C320F57, 0x1B80, 0x54F30F65,
- 0x1B80, 0x54F30F67, 0x1B80, 0x670B0F75, 0x1B80, 0x670B0F77,
- 0x1B80, 0xE1420F85, 0x1B80, 0xE1420F87, 0x1B80, 0xE16D0F95,
- 0x1B80, 0xE16D0F97, 0x1B80, 0x670E0FA5, 0x1B80, 0x670E0FA7,
- 0x1B80, 0xE1420FB5, 0x1B80, 0xE1420FB7, 0x1B80, 0xE16D0FC5,
- 0x1B80, 0xE16D0FC7, 0x1B80, 0x4D100FD5, 0x1B80, 0x4D100FD7,
- 0x1B80, 0x30900FE5, 0x1B80, 0x30900FE7, 0x1B80, 0x00010FF5,
- 0x1B80, 0x00010FF7, 0x1B80, 0x7B241005, 0x1B80, 0x7B241007,
- 0x1B80, 0x7A401015, 0x1B80, 0x7A401017, 0x1B80, 0x79001025,
- 0x1B80, 0x79001027, 0x1B80, 0x55031035, 0x1B80, 0x55031037,
- 0x1B80, 0x310C1045, 0x1B80, 0x310C1047, 0x1B80, 0x7B1C1055,
- 0x1B80, 0x7B1C1057, 0x1B80, 0x7A401065, 0x1B80, 0x7A401067,
- 0x1B80, 0x550B1075, 0x1B80, 0x550B1077, 0x1B80, 0x310C1085,
- 0x1B80, 0x310C1087, 0x1B80, 0x7B201095, 0x1B80, 0x7B201097,
- 0x1B80, 0x7A0010A5, 0x1B80, 0x7A0010A7, 0x1B80, 0x551310B5,
- 0x1B80, 0x551310B7, 0x1B80, 0x740110C5, 0x1B80, 0x740110C7,
- 0x1B80, 0x740010D5, 0x1B80, 0x740010D7, 0x1B80, 0x8E0010E5,
- 0x1B80, 0x8E0010E7, 0x1B80, 0x000110F5, 0x1B80, 0x000110F7,
- 0x1B80, 0x57021105, 0x1B80, 0x57021107, 0x1B80, 0x57001115,
- 0x1B80, 0x57001117, 0x1B80, 0x97001125, 0x1B80, 0x97001127,
- 0x1B80, 0x00011135, 0x1B80, 0x00011137, 0x1B80, 0x4F781145,
- 0x1B80, 0x4F781147, 0x1B80, 0x53881155, 0x1B80, 0x53881157,
- 0x1B80, 0xE1221165, 0x1B80, 0xE1221167, 0x1B80, 0x54801175,
- 0x1B80, 0x54801177, 0x1B80, 0x54001185, 0x1B80, 0x54001187,
- 0x1B80, 0xE1221195, 0x1B80, 0xE1221197, 0x1B80, 0x548111A5,
- 0x1B80, 0x548111A7, 0x1B80, 0x540011B5, 0x1B80, 0x540011B7,
- 0x1B80, 0xE12211C5, 0x1B80, 0xE12211C7, 0x1B80, 0x548211D5,
- 0x1B80, 0x548211D7, 0x1B80, 0x540011E5, 0x1B80, 0x540011E7,
- 0x1B80, 0xE12D11F5, 0x1B80, 0xE12D11F7, 0x1B80, 0xBF1D1205,
- 0x1B80, 0xBF1D1207, 0x1B80, 0x301D1215, 0x1B80, 0x301D1217,
- 0x1B80, 0xE1001225, 0x1B80, 0xE1001227, 0x1B80, 0xE1051235,
- 0x1B80, 0xE1051237, 0x1B80, 0xE1091245, 0x1B80, 0xE1091247,
- 0x1B80, 0xE1101255, 0x1B80, 0xE1101257, 0x1B80, 0xE1641265,
- 0x1B80, 0xE1641267, 0x1B80, 0x55131275, 0x1B80, 0x55131277,
- 0x1B80, 0xE10C1285, 0x1B80, 0xE10C1287, 0x1B80, 0x55151295,
- 0x1B80, 0x55151297, 0x1B80, 0xE11012A5, 0x1B80, 0xE11012A7,
- 0x1B80, 0xE16412B5, 0x1B80, 0xE16412B7, 0x1B80, 0x000112C5,
- 0x1B80, 0x000112C7, 0x1B80, 0x54BF12D5, 0x1B80, 0x54BF12D7,
- 0x1B80, 0x54C012E5, 0x1B80, 0x54C012E7, 0x1B80, 0x54A312F5,
- 0x1B80, 0x54A312F7, 0x1B80, 0x54C11305, 0x1B80, 0x54C11307,
- 0x1B80, 0x54A41315, 0x1B80, 0x54A41317, 0x1B80, 0x4C181325,
- 0x1B80, 0x4C181327, 0x1B80, 0xBF071335, 0x1B80, 0xBF071337,
- 0x1B80, 0x54C21345, 0x1B80, 0x54C21347, 0x1B80, 0x54A41355,
- 0x1B80, 0x54A41357, 0x1B80, 0xBF041365, 0x1B80, 0xBF041367,
- 0x1B80, 0x54C11375, 0x1B80, 0x54C11377, 0x1B80, 0x54A31385,
- 0x1B80, 0x54A31387, 0x1B80, 0xBF011395, 0x1B80, 0xBF011397,
- 0x1B80, 0xE17213A5, 0x1B80, 0xE17213A7, 0x1B80, 0x54DF13B5,
- 0x1B80, 0x54DF13B7, 0x1B80, 0x000113C5, 0x1B80, 0x000113C7,
- 0x1B80, 0x54BF13D5, 0x1B80, 0x54BF13D7, 0x1B80, 0x54E513E5,
- 0x1B80, 0x54E513E7, 0x1B80, 0x050A13F5, 0x1B80, 0x050A13F7,
- 0x1B80, 0x54DF1405, 0x1B80, 0x54DF1407, 0x1B80, 0x00011415,
- 0x1B80, 0x00011417, 0x1B80, 0x7F201425, 0x1B80, 0x7F201427,
- 0x1B80, 0x7E001435, 0x1B80, 0x7E001437, 0x1B80, 0x7D001445,
- 0x1B80, 0x7D001447, 0x1B80, 0x55011455, 0x1B80, 0x55011457,
- 0x1B80, 0x5C311465, 0x1B80, 0x5C311467, 0x1B80, 0xE10C1475,
- 0x1B80, 0xE10C1477, 0x1B80, 0xE1101485, 0x1B80, 0xE1101487,
- 0x1B80, 0x54801495, 0x1B80, 0x54801497, 0x1B80, 0x540014A5,
- 0x1B80, 0x540014A7, 0x1B80, 0xE10C14B5, 0x1B80, 0xE10C14B7,
- 0x1B80, 0xE11014C5, 0x1B80, 0xE11014C7, 0x1B80, 0x548114D5,
- 0x1B80, 0x548114D7, 0x1B80, 0x540014E5, 0x1B80, 0x540014E7,
- 0x1B80, 0xE10C14F5, 0x1B80, 0xE10C14F7, 0x1B80, 0xE1101505,
- 0x1B80, 0xE1101507, 0x1B80, 0x54821515, 0x1B80, 0x54821517,
- 0x1B80, 0x54001525, 0x1B80, 0x54001527, 0x1B80, 0xE12D1535,
- 0x1B80, 0xE12D1537, 0x1B80, 0xBFE91545, 0x1B80, 0xBFE91547,
- 0x1B80, 0x301D1555, 0x1B80, 0x301D1557, 0x1B80, 0x00231565,
- 0x1B80, 0x00231567, 0x1B80, 0x7B201575, 0x1B80, 0x7B201577,
- 0x1B80, 0x7A001585, 0x1B80, 0x7A001587, 0x1B80, 0x79001595,
- 0x1B80, 0x79001597, 0x1B80, 0xE16815A5, 0x1B80, 0xE16815A7,
- 0x1B80, 0x000215B5, 0x1B80, 0x000215B7, 0x1B80, 0x000115C5,
- 0x1B80, 0x000115C7, 0x1B80, 0x002215D5, 0x1B80, 0x002215D7,
- 0x1B80, 0x7B2015E5, 0x1B80, 0x7B2015E7, 0x1B80, 0x7A0015F5,
- 0x1B80, 0x7A0015F7, 0x1B80, 0x79001605, 0x1B80, 0x79001607,
- 0x1B80, 0xE1681615, 0x1B80, 0xE1681617, 0x1B80, 0x00021625,
- 0x1B80, 0x00021627, 0x1B80, 0x00011635, 0x1B80, 0x00011637,
- 0x1B80, 0x549F1645, 0x1B80, 0x549F1647, 0x1B80, 0x54FF1655,
- 0x1B80, 0x54FF1657, 0x1B80, 0x54001665, 0x1B80, 0x54001667,
- 0x1B80, 0x00011675, 0x1B80, 0x00011677, 0x1B80, 0x5C311685,
- 0x1B80, 0x5C311687, 0x1B80, 0x07141695, 0x1B80, 0x07141697,
- 0x1B80, 0x540016A5, 0x1B80, 0x540016A7, 0x1B80, 0x5C3216B5,
- 0x1B80, 0x5C3216B7, 0x1B80, 0x000116C5, 0x1B80, 0x000116C7,
- 0x1B80, 0x5C3216D5, 0x1B80, 0x5C3216D7, 0x1B80, 0x071416E5,
- 0x1B80, 0x071416E7, 0x1B80, 0x540016F5, 0x1B80, 0x540016F7,
- 0x1B80, 0x5C311705, 0x1B80, 0x5C311707, 0x1B80, 0x00011715,
- 0x1B80, 0x00011717, 0x1B80, 0x4C981725, 0x1B80, 0x4C981727,
- 0x1B80, 0x4C181735, 0x1B80, 0x4C181737, 0x1B80, 0x00011745,
- 0x1B80, 0x00011747, 0x1B80, 0x5C321755, 0x1B80, 0x5C321757,
- 0x1B80, 0x62841765, 0x1B80, 0x62841767, 0x1B80, 0x66861775,
- 0x1B80, 0x66861777, 0x1B80, 0x6C031785, 0x1B80, 0x6C031787,
- 0x1B80, 0x7B201795, 0x1B80, 0x7B201797, 0x1B80, 0x7A0017A5,
- 0x1B80, 0x7A0017A7, 0x1B80, 0x790017B5, 0x1B80, 0x790017B7,
- 0x1B80, 0x7F2017C5, 0x1B80, 0x7F2017C7, 0x1B80, 0x7E0017D5,
- 0x1B80, 0x7E0017D7, 0x1B80, 0x7D0017E5, 0x1B80, 0x7D0017E7,
- 0x1B80, 0x090117F5, 0x1B80, 0x090117F7, 0x1B80, 0x0C011805,
- 0x1B80, 0x0C011807, 0x1B80, 0x0BA61815, 0x1B80, 0x0BA61817,
- 0x1B80, 0x00011825, 0x1B80, 0x00011827, 0x1B80, 0x00000006,
- 0x1B80, 0x00000002,
-
-};
-
-void odm_read_and_config_mp_8822b_phy_reg(struct phy_dm_struct *dm)
-{
- u32 i = 0;
- u8 c_cond;
- bool is_matched = true, is_skipped = false;
- u32 *array = array_mp_8822b_phy_reg;
-
- u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===> %s\n", __func__);
-
- for (; (i + 1) < ARRAY_SIZE(array_mp_8822b_phy_reg); i = i + 2) {
- v1 = array[i];
- v2 = array[i + 1];
-
- if (v1 & BIT(31)) { /* positive condition*/
- c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
- if (c_cond == COND_ENDIF) { /*end*/
- is_matched = true;
- is_skipped = false;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
- } else if (c_cond == COND_ELSE) { /*else*/
- is_matched = is_skipped ? false : true;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
- } else { /*if , else if*/
- pre_v1 = v1;
- pre_v2 = v2;
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "IF or ELSE IF\n");
- }
- } else if (v1 & BIT(30)) { /*negative condition*/
- if (is_skipped) {
- is_matched = false;
- continue;
- }
-
- if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
- is_matched = true;
- is_skipped = true;
- } else {
- is_matched = false;
- is_skipped = false;
- }
- } else if (is_matched) {
- odm_config_bb_phy_8822b(dm, v1, MASKDWORD, v2);
- }
- }
-}
-
-u32 odm_get_version_mp_8822b_phy_reg(void) { return 67; }
-
-/******************************************************************************
- * phy_reg_pg.TXT
- ******************************************************************************/
-
-static u32 array_mp_8822b_phy_reg_pg[] = {
- 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638,
- 0, 0, 0, 0x00000c24, 0xffffffff, 0x36384042,
- 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234,
- 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363840,
- 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032,
- 0, 0, 1, 0x00000c34, 0xffffffff, 0x34363840,
- 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283032,
- 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363840,
- 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032,
- 0, 0, 0, 0x00000c44, 0xffffffff, 0x38402224,
- 0, 0, 1, 0x00000c48, 0xffffffff, 0x30323436,
- 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
- 0, 1, 0, 0x00000e20, 0xffffffff, 0x32343638,
- 0, 1, 0, 0x00000e24, 0xffffffff, 0x36384042,
- 0, 1, 0, 0x00000e28, 0xffffffff, 0x28303234,
- 0, 1, 0, 0x00000e2c, 0xffffffff, 0x34363840,
- 0, 1, 0, 0x00000e30, 0xffffffff, 0x26283032,
- 0, 1, 1, 0x00000e34, 0xffffffff, 0x34363840,
- 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283032,
- 0, 1, 0, 0x00000e3c, 0xffffffff, 0x34363840,
- 0, 1, 0, 0x00000e40, 0xffffffff, 0x26283032,
- 0, 1, 0, 0x00000e44, 0xffffffff, 0x38402224,
- 0, 1, 1, 0x00000e48, 0xffffffff, 0x30323436,
- 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628,
- 1, 0, 0, 0x00000c24, 0xffffffff, 0x34363840,
- 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032,
- 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343638,
- 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830,
- 1, 0, 1, 0x00000c34, 0xffffffff, 0x32343638,
- 1, 0, 1, 0x00000c38, 0xffffffff, 0x24262830,
- 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343638,
- 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
- 1, 0, 0, 0x00000c44, 0xffffffff, 0x36382022,
- 1, 0, 1, 0x00000c48, 0xffffffff, 0x28303234,
- 1, 0, 1, 0x00000c4c, 0xffffffff, 0x20222426,
- 1, 1, 0, 0x00000e24, 0xffffffff, 0x34363840,
- 1, 1, 0, 0x00000e28, 0xffffffff, 0x26283032,
- 1, 1, 0, 0x00000e2c, 0xffffffff, 0x32343638,
- 1, 1, 0, 0x00000e30, 0xffffffff, 0x24262830,
- 1, 1, 1, 0x00000e34, 0xffffffff, 0x32343638,
- 1, 1, 1, 0x00000e38, 0xffffffff, 0x24262830,
- 1, 1, 0, 0x00000e3c, 0xffffffff, 0x32343638,
- 1, 1, 0, 0x00000e40, 0xffffffff, 0x24262830,
- 1, 1, 0, 0x00000e44, 0xffffffff, 0x36382022,
- 1, 1, 1, 0x00000e48, 0xffffffff, 0x28303234,
- 1, 1, 1, 0x00000e4c, 0xffffffff, 0x20222426,
-};
-
-void odm_read_and_config_mp_8822b_phy_reg_pg(struct phy_dm_struct *dm)
-{
- u32 i = 0;
- u32 *array = array_mp_8822b_phy_reg_pg;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===> %s\n", __func__);
-
- dm->phy_reg_pg_version = 1;
- dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
-
- for (i = 0; i < ARRAY_SIZE(array_mp_8822b_phy_reg_pg); i += 6) {
- u32 v1 = array[i];
- u32 v2 = array[i + 1];
- u32 v3 = array[i + 2];
- u32 v4 = array[i + 3];
- u32 v5 = array[i + 4];
- u32 v6 = array[i + 5];
-
- odm_config_bb_phy_reg_pg_8822b(dm, v1, v2, v3, v4, v5, v6);
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/*Image2HeaderVersion: 3.2*/
-#ifndef __INC_MP_BB_HW_IMG_8822B_H
-#define __INC_MP_BB_HW_IMG_8822B_H
-
-/******************************************************************************
- * agc_tab.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_agc_tab(/* tc: Test Chip, mp: mp Chip*/
- struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_agc_tab(void);
-
-/******************************************************************************
- * phy_reg.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_phy_reg(/* tc: Test Chip, mp: mp Chip*/
- struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_phy_reg(void);
-
-/******************************************************************************
- * phy_reg_pg.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_phy_reg_pg(/* tc: Test Chip, mp: mp Chip*/
- struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_phy_reg_pg(void);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/*Image2HeaderVersion: 3.2*/
-#include "../mp_precomp.h"
-#include "../phydm_precomp.h"
-#include <linux/kernel.h>
-
-static bool check_positive(struct phy_dm_struct *dm, const u32 condition1,
- const u32 condition2, const u32 condition3,
- const u32 condition4)
-{
- u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
- ((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
- ((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
- ((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
- ((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
-
- u32 cond1 = condition1, cond2 = condition2, cond3 = condition3,
- cond4 = condition4;
-
- u8 cut_version_for_para =
- (dm->cut_version == ODM_CUT_A) ? 14 : dm->cut_version;
- u8 pkg_type_for_para = (dm->package_type == 0) ? 14 : dm->package_type;
-
- u32 driver1 = cut_version_for_para << 24 |
- (dm->support_interface & 0xF0) << 16 |
- dm->support_platform << 16 | pkg_type_for_para << 12 |
- (dm->support_interface & 0x0F) << 8 | _board_type;
-
- u32 driver2 = (dm->type_glna & 0xFF) << 0 | (dm->type_gpa & 0xFF) << 8 |
- (dm->type_alna & 0xFF) << 16 |
- (dm->type_apa & 0xFF) << 24;
-
- u32 driver3 = 0;
-
- u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | (dm->type_gpa & 0xFF00) |
- (dm->type_alna & 0xFF00) << 8 |
- (dm->type_apa & 0xFF00) << 16;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
- __func__, cond1, cond2, cond3, cond4);
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
- __func__, driver1, driver2, driver3, driver4);
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- " (Platform, Interface) = (0x%X, 0x%X)\n",
- dm->support_platform, dm->support_interface);
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- " (Board, Package) = (0x%X, 0x%X)\n",
- dm->board_type, dm->package_type);
-
- /*============== value Defined Check ===============*/
- /*QFN type [15:12] and cut version [27:24] need to do value check*/
-
- if (((cond1 & 0x0000F000) != 0) &&
- ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
- return false;
- if (((cond1 & 0x0F000000) != 0) &&
- ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
- return false;
-
- /*=============== Bit Defined Check ================*/
- /* We don't care [31:28] */
-
- cond1 &= 0x00FF0FFF;
- driver1 &= 0x00FF0FFF;
-
- if ((cond1 & driver1) == cond1) {
- u32 bit_mask = 0;
-
- if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
- return true;
-
- if ((cond1 & BIT(0)) != 0) /*GLNA*/
- bit_mask |= 0x000000FF;
- if ((cond1 & BIT(1)) != 0) /*GPA*/
- bit_mask |= 0x0000FF00;
- if ((cond1 & BIT(2)) != 0) /*ALNA*/
- bit_mask |= 0x00FF0000;
- if ((cond1 & BIT(3)) != 0) /*APA*/
- bit_mask |= 0xFF000000;
-
- if (((cond2 & bit_mask) == (driver2 & bit_mask)) &&
- ((cond4 & bit_mask) ==
- (driver4 &
- bit_mask))) /* board_type of each RF path is matched*/
- return true;
- else
- return false;
- } else {
- return false;
- }
-}
-
-/******************************************************************************
- * mac_reg.TXT
- ******************************************************************************/
-
-static u32 array_mp_8822b_mac_reg[] = {
- 0x029, 0x000000F9, 0x420, 0x00000080, 0x421, 0x0000000F,
- 0x428, 0x0000000A, 0x429, 0x00000010, 0x430, 0x00000000,
- 0x431, 0x00000000, 0x432, 0x00000000, 0x433, 0x00000001,
- 0x434, 0x00000004, 0x435, 0x00000005, 0x436, 0x00000007,
- 0x437, 0x00000008, 0x43C, 0x00000004, 0x43D, 0x00000005,
- 0x43E, 0x00000007, 0x43F, 0x00000008, 0x440, 0x0000005D,
- 0x441, 0x00000001, 0x442, 0x00000000, 0x444, 0x00000010,
- 0x445, 0x000000F0, 0x446, 0x00000001, 0x447, 0x000000FE,
- 0x448, 0x00000000, 0x449, 0x00000000, 0x44A, 0x00000000,
- 0x44B, 0x00000040, 0x44C, 0x00000010, 0x44D, 0x000000F0,
- 0x44E, 0x0000003F, 0x44F, 0x00000000, 0x450, 0x00000000,
- 0x451, 0x00000000, 0x452, 0x00000000, 0x453, 0x00000040,
- 0x455, 0x00000070, 0x45E, 0x00000004, 0x49C, 0x00000010,
- 0x49D, 0x000000F0, 0x49E, 0x00000000, 0x49F, 0x00000006,
- 0x4A0, 0x000000E0, 0x4A1, 0x00000003, 0x4A2, 0x00000000,
- 0x4A3, 0x00000040, 0x4A4, 0x00000015, 0x4A5, 0x000000F0,
- 0x4A6, 0x00000000, 0x4A7, 0x00000006, 0x4A8, 0x000000E0,
- 0x4A9, 0x00000000, 0x4AA, 0x00000000, 0x4AB, 0x00000000,
- 0x7DA, 0x00000008, 0x1448, 0x00000006, 0x144A, 0x00000006,
- 0x144C, 0x00000006, 0x144E, 0x00000006, 0x4C8, 0x000000FF,
- 0x4C9, 0x00000008, 0x4CA, 0x00000020, 0x4CB, 0x00000020,
- 0x4CC, 0x000000FF, 0x4CD, 0x000000FF, 0x4CE, 0x00000001,
- 0x4CF, 0x00000008, 0x500, 0x00000026, 0x501, 0x000000A2,
- 0x502, 0x0000002F, 0x503, 0x00000000, 0x504, 0x00000028,
- 0x505, 0x000000A3, 0x506, 0x0000005E, 0x507, 0x00000000,
- 0x508, 0x0000002B, 0x509, 0x000000A4, 0x50A, 0x0000005E,
- 0x50B, 0x00000000, 0x50C, 0x0000004F, 0x50D, 0x000000A4,
- 0x50E, 0x00000000, 0x50F, 0x00000000, 0x512, 0x0000001C,
- 0x514, 0x0000000A, 0x516, 0x0000000A, 0x521, 0x0000002F,
- 0x525, 0x0000004F, 0x551, 0x00000010, 0x559, 0x00000002,
- 0x55C, 0x00000050, 0x55D, 0x000000FF, 0x577, 0x0000000B,
- 0x5BE, 0x00000064, 0x605, 0x00000030, 0x608, 0x0000000E,
- 0x609, 0x00000022, 0x60C, 0x00000018, 0x6A0, 0x000000FF,
- 0x6A1, 0x000000FF, 0x6A2, 0x000000FF, 0x6A3, 0x000000FF,
- 0x6A4, 0x000000FF, 0x6A5, 0x000000FF, 0x6DE, 0x00000084,
- 0x620, 0x000000FF, 0x621, 0x000000FF, 0x622, 0x000000FF,
- 0x623, 0x000000FF, 0x624, 0x000000FF, 0x625, 0x000000FF,
- 0x626, 0x000000FF, 0x627, 0x000000FF, 0x638, 0x00000050,
- 0x63C, 0x0000000A, 0x63D, 0x0000000A, 0x63E, 0x0000000E,
- 0x63F, 0x0000000E, 0x640, 0x00000040, 0x642, 0x00000040,
- 0x643, 0x00000000, 0x652, 0x000000C8, 0x66E, 0x00000005,
- 0x718, 0x00000040, 0x7D4, 0x00000098,
-
-};
-
-void odm_read_and_config_mp_8822b_mac_reg(struct phy_dm_struct *dm)
-{
- u32 i = 0;
- u8 c_cond;
- bool is_matched = true, is_skipped = false;
- u32 *array = array_mp_8822b_mac_reg;
-
- u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===> %s\n", __func__);
-
- for (; (i + 1) < ARRAY_SIZE(array_mp_8822b_mac_reg); i = i + 2) {
- v1 = array[i];
- v2 = array[i + 1];
-
- if (v1 & BIT(31)) { /* positive condition*/
- c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
- if (c_cond == COND_ENDIF) { /*end*/
- is_matched = true;
- is_skipped = false;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
- } else if (c_cond == COND_ELSE) { /*else*/
- is_matched = is_skipped ? false : true;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
- } else { /*if , else if*/
- pre_v1 = v1;
- pre_v2 = v2;
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "IF or ELSE IF\n");
- }
- } else if (v1 & BIT(30)) { /*negative condition*/
- if (is_skipped) {
- is_matched = false;
- continue;
- }
-
- if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
- is_matched = true;
- is_skipped = true;
- } else {
- is_matched = false;
- is_skipped = false;
- }
- } else if (is_matched) {
- odm_config_mac_8822b(dm, v1, (u8)v2);
- }
- }
-}
-
-u32 odm_get_version_mp_8822b_mac_reg(void) { return 67; }
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/*Image2HeaderVersion: 3.2*/
-#ifndef __INC_MP_MAC_HW_IMG_8822B_H
-#define __INC_MP_MAC_HW_IMG_8822B_H
-
-/******************************************************************************
- * mac_reg.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_mac_reg(/* tc: Test Chip, mp: mp Chip*/
- struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_mac_reg(void);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/*Image2HeaderVersion: 3.2*/
-#include "../mp_precomp.h"
-#include "../phydm_precomp.h"
-#include <linux/kernel.h>
-
-static bool check_positive(struct phy_dm_struct *dm, const u32 condition1,
- const u32 condition2, const u32 condition3,
- const u32 condition4)
-{
- u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
- ((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
- ((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
- ((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
- ((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
-
- u32 cond1 = condition1, cond2 = condition2, cond3 = condition3,
- cond4 = condition4;
-
- u8 cut_version_for_para =
- (dm->cut_version == ODM_CUT_A) ? 14 : dm->cut_version;
- u8 pkg_type_for_para = (dm->package_type == 0) ? 14 : dm->package_type;
-
- u32 driver1 = cut_version_for_para << 24 |
- (dm->support_interface & 0xF0) << 16 |
- dm->support_platform << 16 | pkg_type_for_para << 12 |
- (dm->support_interface & 0x0F) << 8 | _board_type;
-
- u32 driver2 = (dm->type_glna & 0xFF) << 0 | (dm->type_gpa & 0xFF) << 8 |
- (dm->type_alna & 0xFF) << 16 |
- (dm->type_apa & 0xFF) << 24;
-
- u32 driver3 = 0;
-
- u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | (dm->type_gpa & 0xFF00) |
- (dm->type_alna & 0xFF00) << 8 |
- (dm->type_apa & 0xFF00) << 16;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
- __func__, cond1, cond2, cond3, cond4);
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
- __func__, driver1, driver2, driver3, driver4);
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- " (Platform, Interface) = (0x%X, 0x%X)\n",
- dm->support_platform, dm->support_interface);
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- " (Board, Package) = (0x%X, 0x%X)\n",
- dm->board_type, dm->package_type);
-
- /*============== value Defined Check ===============*/
- /*QFN type [15:12] and cut version [27:24] need to do value check*/
-
- if (((cond1 & 0x0000F000) != 0) &&
- ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
- return false;
- if (((cond1 & 0x0F000000) != 0) &&
- ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
- return false;
-
- /*=============== Bit Defined Check ================*/
- /* We don't care [31:28] */
-
- cond1 &= 0x00FF0FFF;
- driver1 &= 0x00FF0FFF;
-
- if ((cond1 & driver1) == cond1) {
- u32 bit_mask = 0;
-
- if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
- return true;
-
- if ((cond1 & BIT(0)) != 0) /*GLNA*/
- bit_mask |= 0x000000FF;
- if ((cond1 & BIT(1)) != 0) /*GPA*/
- bit_mask |= 0x0000FF00;
- if ((cond1 & BIT(2)) != 0) /*ALNA*/
- bit_mask |= 0x00FF0000;
- if ((cond1 & BIT(3)) != 0) /*APA*/
- bit_mask |= 0xFF000000;
-
- if (((cond2 & bit_mask) == (driver2 & bit_mask)) &&
- ((cond4 & bit_mask) ==
- (driver4 &
- bit_mask))) /* board_type of each RF path is matched*/
- return true;
- else
- return false;
- } else {
- return false;
- }
-}
-
-/******************************************************************************
- * radioa.TXT
- ******************************************************************************/
-
-static u32 array_mp_8822b_radioa[] = {
- 0x000, 0x00030000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0xA0000000, 0x00000000, 0x001, 0x00040029,
- 0xB0000000, 0x00000000, 0x018, 0x00010D24, 0x0EF, 0x00080000,
- 0x033, 0x00000002, 0x03E, 0x0000003F, 0x03F, 0x000C0F4E,
- 0x033, 0x00000001, 0x03E, 0x00000034, 0x03F, 0x0004080E,
- 0x0EF, 0x00080000, 0x0DF, 0x00002449, 0x033, 0x00000024,
- 0x03E, 0x0000003F, 0x03F, 0x00060FDE, 0x0EF, 0x00000000,
- 0x0EF, 0x00080000, 0x033, 0x00000025, 0x03E, 0x00000037,
- 0x03F, 0x0007EFCE, 0x0EF, 0x00000000, 0x0EF, 0x00080000,
- 0x033, 0x00000026, 0x03E, 0x00000037, 0x03F, 0x000DEFCE,
- 0x0EF, 0x00000000, 0x07F, 0x00000000, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x93001000, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x0B0, 0x000FB0F8, 0xA0000000, 0x00000000,
- 0x0B0, 0x000FF0F8, 0xB0000000, 0x00000000, 0x0B1, 0x0007DBE4,
- 0x0B2, 0x000225D1, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
- 0x0B3, 0x000FC760, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
- 0x0B3, 0x0007C330, 0xA0000000, 0x00000000, 0x0B3, 0x000FC760,
- 0xB0000000, 0x00000000, 0x0B4, 0x00099DD0, 0x0B5, 0x000400FC,
- 0x0B6, 0x000187F0, 0x0B7, 0x00030018, 0x0B8, 0x00080800,
- 0x0B9, 0x00000000, 0x0BA, 0x00008000, 0x0BB, 0x00000000,
- 0x0BC, 0x00040030, 0x0BD, 0x00000000, 0x0BE, 0x00000000,
- 0x0BF, 0x00000000, 0x0C0, 0x00000000, 0x0C1, 0x00000000,
- 0x0C2, 0x00000000, 0x0C3, 0x00000000, 0x0C4, 0x00002402,
- 0x0C5, 0x00000009, 0x0C6, 0x00040299, 0x0C7, 0x00055555,
- 0x0C8, 0x0000C16C, 0x0C9, 0x0001C140, 0x0CA, 0x00000000,
- 0x0CB, 0x00000000, 0x0CC, 0x00000000, 0x0CD, 0x00000000,
- 0x0CE, 0x00090C00, 0x0CF, 0x0006D200, 0x0DF, 0x00000009,
- 0x018, 0x00010524, 0x089, 0x00000207, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x08A, 0x000FE186, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x08A, 0x000FE186, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x08A, 0x000FF186, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x08A, 0x000FE186, 0xA0000000, 0x00000000,
- 0x08A, 0x000FF186, 0xB0000000, 0x00000000, 0x08B, 0x00061E3C,
- 0x08C, 0x000112C7, 0x08D, 0x000F4988, 0x08E, 0x00064D40,
- 0x0EF, 0x00020000, 0x033, 0x00000007, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0xA0000000, 0x00000000,
- 0x03E, 0x00004000, 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000DFF86, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C0006, 0x93001000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0xA0000000, 0x00000000,
- 0x03F, 0x000C3186, 0xB0000000, 0x00000000, 0x033, 0x00000006,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004080,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004080,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004080,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004080,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0xA0000000, 0x00000000, 0x03E, 0x00004080, 0xB0000000, 0x00000000,
- 0x03F, 0x000C3186, 0x033, 0x00000005, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x000040C8, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x00004084, 0xA0000000, 0x00000000,
- 0x03E, 0x000040C8, 0xB0000000, 0x00000000, 0x03F, 0x000C3186,
- 0x033, 0x00000004, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x03E, 0x00004190, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x03E, 0x00004190, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004190, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004190, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x03E, 0x00004190, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x03E, 0x00004108, 0xA0000000, 0x00000000, 0x03E, 0x00004190,
- 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000003,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004998,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004998,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004998,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004998,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004998,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x0000490C,
- 0xA0000000, 0x00000000, 0x03E, 0x00004998, 0xB0000000, 0x00000000,
- 0x03F, 0x000C3186, 0x033, 0x00000002, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x00005840, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x00005E00, 0xA0000000, 0x00000000,
- 0x03E, 0x00005840, 0xB0000000, 0x00000000, 0x03F, 0x000C3186,
- 0x033, 0x00000001, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x03E, 0x000058C2, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x03E, 0x000058C2, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x000058C2, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x000058C2, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x03E, 0x000058C2, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x03E, 0x00005862, 0xA0000000, 0x00000000, 0x03E, 0x000058C2,
- 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000000,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00005930,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00005930,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00005930,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00005930,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00005930,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00005948,
- 0xA0000000, 0x00000000, 0x03E, 0x00005930, 0xB0000000, 0x00000000,
- 0x03F, 0x000C3186, 0x033, 0x0000000F, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0xA0000000, 0x00000000,
- 0x03E, 0x00004000, 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000DFF86, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000DFF86, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C0006, 0x93001000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0xA0000000, 0x00000000,
- 0x03F, 0x000C3186, 0xB0000000, 0x00000000, 0x033, 0x0000000E,
- 0x03E, 0x00004080, 0x03F, 0x000C3186, 0x033, 0x0000000D,
- 0x03E, 0x000040C8, 0x03F, 0x000C3186, 0x033, 0x0000000C,
- 0x03E, 0x00004190, 0x03F, 0x000C3186, 0x033, 0x0000000B,
- 0x03E, 0x00004998, 0x03F, 0x000C3186, 0x033, 0x0000000A,
- 0x03E, 0x00005840, 0x03F, 0x000C3186, 0x033, 0x00000009,
- 0x03E, 0x000058C2, 0x03F, 0x000C3186, 0x033, 0x00000008,
- 0x03E, 0x00005930, 0x03F, 0x000C3186, 0x033, 0x00000017,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
- 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
- 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0xA0000000, 0x00000000, 0x03E, 0x00004000, 0xB0000000, 0x00000000,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C0006,
- 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0xA0000000, 0x00000000, 0x03F, 0x000C3186, 0xB0000000, 0x00000000,
- 0x033, 0x00000016, 0x03E, 0x00004080, 0x03F, 0x000C3186,
- 0x033, 0x00000015, 0x03E, 0x000040C8, 0x03F, 0x000C3186,
- 0x033, 0x00000014, 0x03E, 0x00004190, 0x03F, 0x000C3186,
- 0x033, 0x00000013, 0x03E, 0x00004998, 0x03F, 0x000C3186,
- 0x033, 0x00000012, 0x03E, 0x00005840, 0x03F, 0x000C3186,
- 0x033, 0x00000011, 0x03E, 0x000058C2, 0x03F, 0x000C3186,
- 0x033, 0x00000010, 0x03E, 0x00005930, 0x03F, 0x000C3186,
- 0x0EF, 0x00000000, 0x0EF, 0x00004000, 0x033, 0x00000000,
- 0x03F, 0x0000000A, 0x033, 0x00000001, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000006, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93001000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0xA0000000, 0x00000000,
- 0x03F, 0x00000005, 0xB0000000, 0x00000000, 0x033, 0x00000002,
- 0x03F, 0x00000000, 0x0EF, 0x00000000, 0x018, 0x00000401,
- 0x084, 0x00001209, 0x086, 0x000001A0, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0xA0000000, 0x00000000,
- 0x087, 0x000E8180, 0xB0000000, 0x00000000, 0x088, 0x00070020,
- 0x0DE, 0x00000010, 0x0EF, 0x00008000, 0x033, 0x0000000F,
- 0x03F, 0x0000003C, 0x033, 0x0000000E, 0x03F, 0x00000038,
- 0x033, 0x0000000D, 0x03F, 0x00000030, 0x033, 0x0000000C,
- 0x03F, 0x00000028, 0x033, 0x0000000B, 0x03F, 0x00000020,
- 0x033, 0x0000000A, 0x03F, 0x00000018, 0x033, 0x00000009,
- 0x03F, 0x00000010, 0x033, 0x00000008, 0x03F, 0x00000008,
- 0x033, 0x00000007, 0x03F, 0x0000003C, 0x033, 0x00000006,
- 0x03F, 0x00000038, 0x033, 0x00000005, 0x03F, 0x00000030,
- 0x033, 0x00000004, 0x03F, 0x00000028, 0x033, 0x00000003,
- 0x03F, 0x00000020, 0x033, 0x00000002, 0x03F, 0x00000018,
- 0x033, 0x00000001, 0x03F, 0x00000010, 0x033, 0x00000000,
- 0x03F, 0x00000008, 0x0EF, 0x00000000, 0x0B8, 0x00080A00,
- 0x0B0, 0x000FF0FA, 0x0FE, 0x00000000, 0x0CA, 0x00080000,
- 0x0C9, 0x0001C141, 0x0FE, 0x00000000, 0x0B0, 0x000FF0F8,
- 0x018, 0x00018D24, 0xFFE, 0x00000000, 0xFFE, 0x00000000,
- 0xFFE, 0x00000000, 0xFFE, 0x00000000, 0x018, 0x00010D24,
- 0x01B, 0x00075A40, 0x0EE, 0x00000002, 0x033, 0x00000000,
- 0x03F, 0x00000004, 0x033, 0x00000001, 0x03F, 0x00000004,
- 0x033, 0x00000002, 0x03F, 0x00000004, 0x033, 0x00000003,
- 0x03F, 0x00000004, 0x033, 0x00000004, 0x03F, 0x00000004,
- 0x033, 0x00000005, 0x03F, 0x00000006, 0x033, 0x00000006,
- 0x03F, 0x00000002, 0x033, 0x00000007, 0x03F, 0x00000000,
- 0x0EE, 0x00000000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x061, 0x0005D4A0,
- 0x062, 0x0000D203, 0x063, 0x00000062, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203,
- 0x063, 0x00000062, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000062,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x061, 0x0005D4A0,
- 0x062, 0x0000D203, 0x063, 0x00000062, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203,
- 0x063, 0x00000062, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1,
- 0x062, 0x0000D3A2, 0x063, 0x00000062, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2,
- 0x063, 0x00000062, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D301, 0x062, 0x0000D303, 0x063, 0x00000002,
- 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D301,
- 0x062, 0x0000D303, 0x063, 0x00000002, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x061, 0x0005D3D1, 0x062, 0x0000D3A2,
- 0x063, 0x00000002, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000062,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D3D1,
- 0x062, 0x0000D3A2, 0x063, 0x00000002, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x061, 0x0005D301, 0x062, 0x0000D303,
- 0x063, 0x00000002, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D3D1, 0x062, 0x0000D3A2, 0x063, 0x00000002,
- 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D301,
- 0x062, 0x0000D303, 0x063, 0x00000002, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x061, 0x0005D301, 0x062, 0x0000D303,
- 0x063, 0x00000002, 0xA0000000, 0x00000000, 0x061, 0x0005D3D0,
- 0x062, 0x0000D303, 0x063, 0x00000002, 0xB0000000, 0x00000000,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
- 0x030, 0x000004A3, 0x030, 0x000014A3, 0x030, 0x000024A3,
- 0x030, 0x000034A3, 0x030, 0x000044A3, 0x030, 0x000054A3,
- 0x030, 0x000064A3, 0x030, 0x000074A3, 0x030, 0x000084A3,
- 0x030, 0x000094A3, 0x030, 0x0000A4A3, 0x030, 0x0000B4A3,
- 0x0EF, 0x00000000, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x0EF, 0x00000200, 0x030, 0x000004A3, 0x030, 0x000014A3,
- 0x030, 0x000024A3, 0x030, 0x000034A3, 0x030, 0x000044A3,
- 0x030, 0x000054A3, 0x030, 0x000064A3, 0x030, 0x000074A3,
- 0x030, 0x000084A3, 0x030, 0x000094A3, 0x030, 0x0000A4A3,
- 0x030, 0x0000B4A3, 0x0EF, 0x00000000, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000004A3,
- 0x030, 0x000014A3, 0x030, 0x000024A3, 0x030, 0x000034A3,
- 0x030, 0x000044A3, 0x030, 0x000054A3, 0x030, 0x000064A3,
- 0x030, 0x000074A3, 0x030, 0x000084A3, 0x030, 0x000094A3,
- 0x030, 0x0000A4A3, 0x030, 0x0000B4A3, 0x0EF, 0x00000000,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
- 0x030, 0x000002A6, 0x030, 0x000012A6, 0x030, 0x000022A6,
- 0x030, 0x000032A6, 0x030, 0x000042A6, 0x030, 0x000052A6,
- 0x030, 0x000062A6, 0x030, 0x000072A6, 0x030, 0x000082A6,
- 0x030, 0x000092A6, 0x030, 0x0000A2A6, 0x030, 0x0000B2A6,
- 0x0EF, 0x00000000, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x0EF, 0x00000200, 0x030, 0x000004A0, 0x030, 0x000014A0,
- 0x030, 0x000024A0, 0x030, 0x000034A0, 0x030, 0x000044A0,
- 0x030, 0x000054A0, 0x030, 0x000064A0, 0x030, 0x000074A0,
- 0x030, 0x000084A0, 0x030, 0x000094A0, 0x030, 0x0000A4A0,
- 0x030, 0x0000B4A0, 0x0EF, 0x00000000, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000004A0,
- 0x030, 0x000014A0, 0x030, 0x000024A0, 0x030, 0x000034A0,
- 0x030, 0x000044A0, 0x030, 0x000054A0, 0x030, 0x000064A0,
- 0x030, 0x000074A0, 0x030, 0x000084A0, 0x030, 0x000094A0,
- 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, 0x0EF, 0x00000000,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
- 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0,
- 0x030, 0x000034A0, 0x030, 0x000044A0, 0x030, 0x000054A0,
- 0x030, 0x000064A0, 0x030, 0x000074A0, 0x030, 0x000084A0,
- 0x030, 0x000094A0, 0x030, 0x0000A4A0, 0x030, 0x0000B4A0,
- 0x0EF, 0x00000000, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000200, 0x030, 0x000002A1, 0x030, 0x000012A1,
- 0x030, 0x000022A1, 0x030, 0x000032A1, 0x030, 0x000042A1,
- 0x030, 0x000052A1, 0x030, 0x000062A1, 0x030, 0x000072A1,
- 0x030, 0x000082A1, 0x030, 0x000092A1, 0x030, 0x0000A2A1,
- 0x030, 0x0000B2A1, 0x0EF, 0x00000000, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000002A6,
- 0x030, 0x000012A6, 0x030, 0x000022A6, 0x030, 0x000032A6,
- 0x030, 0x000042A6, 0x030, 0x000052A6, 0x030, 0x000062A6,
- 0x030, 0x000072A6, 0x030, 0x000082A6, 0x030, 0x000092A6,
- 0x030, 0x0000A2A6, 0x030, 0x0000B2A6, 0x0EF, 0x00000000,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
- 0x030, 0x00000384, 0x030, 0x00001384, 0x030, 0x00002384,
- 0x030, 0x00003384, 0x030, 0x00004425, 0x030, 0x00005425,
- 0x030, 0x00006425, 0x030, 0x00007425, 0x030, 0x000083A4,
- 0x030, 0x000093A4, 0x030, 0x0000A3A4, 0x030, 0x0000B3A4,
- 0x0EF, 0x00000000, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000200, 0x030, 0x000003A3, 0x030, 0x000013A3,
- 0x030, 0x000023A3, 0x030, 0x000033A3, 0x030, 0x00004355,
- 0x030, 0x00005355, 0x030, 0x00006355, 0x030, 0x00007355,
- 0x030, 0x00008314, 0x030, 0x00009314, 0x030, 0x0000A314,
- 0x030, 0x0000B314, 0x0EF, 0x00000000, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000003A1,
- 0x030, 0x000013A1, 0x030, 0x000023A1, 0x030, 0x000033A1,
- 0x030, 0x000043A3, 0x030, 0x000053A3, 0x030, 0x000063A3,
- 0x030, 0x000073A3, 0x030, 0x000083A5, 0x030, 0x000093A5,
- 0x030, 0x0000A3A5, 0x030, 0x0000B3A5, 0x0EF, 0x00000000,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
- 0x030, 0x000002A1, 0x030, 0x000012A1, 0x030, 0x000022A1,
- 0x030, 0x000032A1, 0x030, 0x000042A1, 0x030, 0x000052A1,
- 0x030, 0x000062A1, 0x030, 0x000072A1, 0x030, 0x000082A1,
- 0x030, 0x000092A1, 0x030, 0x0000A2A1, 0x030, 0x0000B2A1,
- 0x0EF, 0x00000000, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000200, 0x030, 0x00000463, 0x030, 0x00001463,
- 0x030, 0x00002463, 0x030, 0x00003463, 0x030, 0x00004545,
- 0x030, 0x00005545, 0x030, 0x00006545, 0x030, 0x00007545,
- 0x030, 0x00008565, 0x030, 0x00009565, 0x030, 0x0000A565,
- 0x030, 0x0000B565, 0x0EF, 0x00000000, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x00000303,
- 0x030, 0x00001303, 0x030, 0x00002303, 0x030, 0x00003303,
- 0x030, 0x000043A4, 0x030, 0x000053A4, 0x030, 0x000063A4,
- 0x030, 0x000073A4, 0x030, 0x00008365, 0x030, 0x00009365,
- 0x030, 0x0000A365, 0x030, 0x0000B365, 0x0EF, 0x00000000,
- 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000200,
- 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
- 0x030, 0x000033A2, 0x030, 0x00004343, 0x030, 0x00005343,
- 0x030, 0x00006343, 0x030, 0x00007343, 0x030, 0x00008364,
- 0x030, 0x00009364, 0x030, 0x0000A364, 0x030, 0x0000B364,
- 0x0EF, 0x00000000, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000200, 0x030, 0x000003A0, 0x030, 0x000013A0,
- 0x030, 0x000023A0, 0x030, 0x000033A0, 0x030, 0x00004430,
- 0x030, 0x00005430, 0x030, 0x00006430, 0x030, 0x00007430,
- 0x030, 0x00008372, 0x030, 0x00009372, 0x030, 0x0000A372,
- 0x030, 0x0000B372, 0x0EF, 0x00000000, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000003A0,
- 0x030, 0x000013A0, 0x030, 0x000023A0, 0x030, 0x000033A0,
- 0x030, 0x000043A1, 0x030, 0x000053A1, 0x030, 0x000063A1,
- 0x030, 0x000073A1, 0x030, 0x000083A2, 0x030, 0x000093A2,
- 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x0EF, 0x00000000,
- 0xA0000000, 0x00000000, 0x0EF, 0x00000200, 0x030, 0x000003D0,
- 0x030, 0x000013D0, 0x030, 0x000023D0, 0x030, 0x000033D0,
- 0x030, 0x000043D0, 0x030, 0x000053D0, 0x030, 0x000063D0,
- 0x030, 0x000073D0, 0x030, 0x000083D0, 0x030, 0x000093D0,
- 0x030, 0x0000A3D0, 0x030, 0x0000B3D0, 0x0EF, 0x00000000,
- 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
- 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
- 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
- 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
- 0x030, 0x0000B203, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
- 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
- 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
- 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
- 0x030, 0x0000B203, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
- 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
- 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
- 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
- 0x030, 0x0000B203, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
- 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
- 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
- 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
- 0x030, 0x0000B203, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
- 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
- 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
- 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
- 0x030, 0x0000B203, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x00000203, 0x030, 0x00001203,
- 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
- 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
- 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
- 0x030, 0x0000B203, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A3, 0x030, 0x000013A3,
- 0x030, 0x000023A3, 0x030, 0x000033A3, 0x030, 0x000043A3,
- 0x030, 0x000053A3, 0x030, 0x000063A3, 0x030, 0x000073A3,
- 0x030, 0x000083A3, 0x030, 0x000093A3, 0x030, 0x0000A3A3,
- 0x030, 0x0000B3A3, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
- 0x0EF, 0x00000080, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0xA0000000, 0x00000000, 0x0EF, 0x00000080,
- 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
- 0x030, 0x000033A2, 0x030, 0x000043A2, 0x030, 0x000053A2,
- 0x030, 0x000063A2, 0x030, 0x000073A2, 0x030, 0x000083A2,
- 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
- 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004777,
- 0x030, 0x00005777, 0x030, 0x00006777, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004777,
- 0x030, 0x00005777, 0x030, 0x00006777, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000660,
- 0x030, 0x00001443, 0x030, 0x00002221, 0x030, 0x00004777,
- 0x030, 0x00005777, 0x030, 0x00006777, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000776,
- 0x030, 0x00001455, 0x030, 0x00002325, 0x030, 0x00004777,
- 0x030, 0x00005777, 0x030, 0x00006777, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000764,
- 0x030, 0x00001632, 0x030, 0x00002421, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000764,
- 0x030, 0x00001632, 0x030, 0x00002421, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000777,
- 0x030, 0x00001442, 0x030, 0x00002222, 0x030, 0x00004777,
- 0x030, 0x00005777, 0x030, 0x00006777, 0x93001000, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000764,
- 0x030, 0x00001632, 0x030, 0x00002421, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000775,
- 0x030, 0x00001343, 0x030, 0x00002210, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x0EF, 0x00000040, 0x030, 0x00000775,
- 0x030, 0x00001422, 0x030, 0x00002210, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0xA0000000, 0x00000000,
- 0x0EF, 0x00000040, 0x030, 0x00000764, 0x030, 0x00001632,
- 0x030, 0x00002421, 0x030, 0x00004000, 0x030, 0x00005000,
- 0x030, 0x00006000, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
- 0x0EF, 0x00000800, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
- 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
- 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
- 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
- 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
- 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
- 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
- 0x03F, 0x000000F3, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
- 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
- 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
- 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
- 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
- 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
- 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
- 0x03F, 0x000000F3, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
- 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
- 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
- 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
- 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
- 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
- 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
- 0x03F, 0x000000F3, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000005, 0x033, 0x00000021,
- 0x03F, 0x00000008, 0x033, 0x00000022, 0x03F, 0x0000000B,
- 0x033, 0x00000023, 0x03F, 0x0000000E, 0x033, 0x00000024,
- 0x03F, 0x0000002B, 0x033, 0x00000025, 0x03F, 0x00000068,
- 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027,
- 0x03F, 0x0000006E, 0x033, 0x00000028, 0x03F, 0x00000071,
- 0x033, 0x00000029, 0x03F, 0x00000074, 0x033, 0x0000002A,
- 0x03F, 0x00000077, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
- 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
- 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
- 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
- 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
- 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
- 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
- 0x03F, 0x000000F3, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
- 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
- 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
- 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
- 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
- 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
- 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
- 0x03F, 0x000000F3, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000007, 0x033, 0x00000021,
- 0x03F, 0x0000000A, 0x033, 0x00000022, 0x03F, 0x0000000D,
- 0x033, 0x00000023, 0x03F, 0x0000002A, 0x033, 0x00000024,
- 0x03F, 0x0000002D, 0x033, 0x00000025, 0x03F, 0x00000030,
- 0x033, 0x00000026, 0x03F, 0x0000006D, 0x033, 0x00000027,
- 0x03F, 0x00000070, 0x033, 0x00000028, 0x03F, 0x000000ED,
- 0x033, 0x00000029, 0x03F, 0x000000F0, 0x033, 0x0000002A,
- 0x03F, 0x000000F3, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000005, 0x033, 0x00000021,
- 0x03F, 0x00000008, 0x033, 0x00000022, 0x03F, 0x0000000B,
- 0x033, 0x00000023, 0x03F, 0x0000000E, 0x033, 0x00000024,
- 0x03F, 0x0000002B, 0x033, 0x00000025, 0x03F, 0x00000068,
- 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027,
- 0x03F, 0x0000006E, 0x033, 0x00000028, 0x03F, 0x00000071,
- 0x033, 0x00000029, 0x03F, 0x00000074, 0x033, 0x0000002A,
- 0x03F, 0x00000077, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000005, 0x033, 0x00000021,
- 0x03F, 0x00000008, 0x033, 0x00000022, 0x03F, 0x0000000B,
- 0x033, 0x00000023, 0x03F, 0x0000000E, 0x033, 0x00000024,
- 0x03F, 0x0000002B, 0x033, 0x00000025, 0x03F, 0x00000068,
- 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027,
- 0x03F, 0x0000006E, 0x033, 0x00000028, 0x03F, 0x00000071,
- 0x033, 0x00000029, 0x03F, 0x00000074, 0x033, 0x0000002A,
- 0x03F, 0x00000077, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000C0C, 0x033, 0x00000021,
- 0x03F, 0x00000C29, 0x033, 0x00000022, 0x03F, 0x00000C2C,
- 0x033, 0x00000023, 0x03F, 0x00000C69, 0x033, 0x00000024,
- 0x03F, 0x00000CA8, 0x033, 0x00000025, 0x03F, 0x00000CE8,
- 0x033, 0x00000026, 0x03F, 0x00000CEB, 0x033, 0x00000027,
- 0x03F, 0x00000CEE, 0x033, 0x00000028, 0x03F, 0x00000CF1,
- 0x033, 0x00000029, 0x03F, 0x00000CF4, 0x033, 0x0000002A,
- 0x03F, 0x00000CF7, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x0000042B, 0x033, 0x00000021,
- 0x03F, 0x0000082A, 0x033, 0x00000022, 0x03F, 0x00000849,
- 0x033, 0x00000023, 0x03F, 0x0000084C, 0x033, 0x00000024,
- 0x03F, 0x00000C4C, 0x033, 0x00000025, 0x03F, 0x00000CA9,
- 0x033, 0x00000026, 0x03F, 0x00000CEA, 0x033, 0x00000027,
- 0x03F, 0x00000CED, 0x033, 0x00000028, 0x03F, 0x00000CF0,
- 0x033, 0x00000029, 0x03F, 0x00000CF3, 0x033, 0x0000002A,
- 0x03F, 0x00000CF6, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000C09, 0x033, 0x00000021,
- 0x03F, 0x00000C0C, 0x033, 0x00000022, 0x03F, 0x00000C0F,
- 0x033, 0x00000023, 0x03F, 0x00000C2C, 0x033, 0x00000024,
- 0x03F, 0x00000C2F, 0x033, 0x00000025, 0x03F, 0x00000C8A,
- 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
- 0x03F, 0x00000C90, 0x033, 0x00000028, 0x03F, 0x00000CD0,
- 0x033, 0x00000029, 0x03F, 0x00000CF2, 0x033, 0x0000002A,
- 0x03F, 0x00000CF5, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000005, 0x033, 0x00000021,
- 0x03F, 0x00000008, 0x033, 0x00000022, 0x03F, 0x0000000B,
- 0x033, 0x00000023, 0x03F, 0x0000000E, 0x033, 0x00000024,
- 0x03F, 0x0000002B, 0x033, 0x00000025, 0x03F, 0x00000068,
- 0x033, 0x00000026, 0x03F, 0x0000006B, 0x033, 0x00000027,
- 0x03F, 0x0000006E, 0x033, 0x00000028, 0x03F, 0x00000071,
- 0x033, 0x00000029, 0x03F, 0x00000074, 0x033, 0x0000002A,
- 0x03F, 0x00000077, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000C09, 0x033, 0x00000021,
- 0x03F, 0x00000C0C, 0x033, 0x00000022, 0x03F, 0x00000C0F,
- 0x033, 0x00000023, 0x03F, 0x00000C2C, 0x033, 0x00000024,
- 0x03F, 0x00000C2F, 0x033, 0x00000025, 0x03F, 0x00000C8A,
- 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
- 0x03F, 0x00000C90, 0x033, 0x00000028, 0x03F, 0x00000CD0,
- 0x033, 0x00000029, 0x03F, 0x00000CF2, 0x033, 0x0000002A,
- 0x03F, 0x00000CF5, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000429, 0x033, 0x00000021,
- 0x03F, 0x00000828, 0x033, 0x00000022, 0x03F, 0x00000847,
- 0x033, 0x00000023, 0x03F, 0x0000084A, 0x033, 0x00000024,
- 0x03F, 0x00000C4B, 0x033, 0x00000025, 0x03F, 0x00000C8A,
- 0x033, 0x00000026, 0x03F, 0x00000CEA, 0x033, 0x00000027,
- 0x03F, 0x00000CED, 0x033, 0x00000028, 0x03F, 0x00000CF0,
- 0x033, 0x00000029, 0x03F, 0x00000CF3, 0x033, 0x0000002A,
- 0x03F, 0x00000CF6, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x00000C09, 0x033, 0x00000021,
- 0x03F, 0x00000C0C, 0x033, 0x00000022, 0x03F, 0x00000C0F,
- 0x033, 0x00000023, 0x03F, 0x00000C2C, 0x033, 0x00000024,
- 0x03F, 0x00000C2F, 0x033, 0x00000025, 0x03F, 0x00000C8A,
- 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
- 0x03F, 0x00000C90, 0x033, 0x00000028, 0x03F, 0x00000CD0,
- 0x033, 0x00000029, 0x03F, 0x00000CF2, 0x033, 0x0000002A,
- 0x03F, 0x00000CF5, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x0000042B, 0x033, 0x00000021,
- 0x03F, 0x0000082A, 0x033, 0x00000022, 0x03F, 0x00000849,
- 0x033, 0x00000023, 0x03F, 0x0000084C, 0x033, 0x00000024,
- 0x03F, 0x00000C4C, 0x033, 0x00000025, 0x03F, 0x00000C8A,
- 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
- 0x03F, 0x00000CEB, 0x033, 0x00000028, 0x03F, 0x00000CEE,
- 0x033, 0x00000029, 0x03F, 0x00000CF1, 0x033, 0x0000002A,
- 0x03F, 0x00000CF4, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000020, 0x03F, 0x0000042B, 0x033, 0x00000021,
- 0x03F, 0x0000082A, 0x033, 0x00000022, 0x03F, 0x00000849,
- 0x033, 0x00000023, 0x03F, 0x0000084C, 0x033, 0x00000024,
- 0x03F, 0x00000C4C, 0x033, 0x00000025, 0x03F, 0x00000C8A,
- 0x033, 0x00000026, 0x03F, 0x00000C8D, 0x033, 0x00000027,
- 0x03F, 0x00000CEB, 0x033, 0x00000028, 0x03F, 0x00000CEE,
- 0x033, 0x00000029, 0x03F, 0x00000CF1, 0x033, 0x0000002A,
- 0x03F, 0x00000CF4, 0xA0000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000C09, 0x033, 0x00000021, 0x03F, 0x00000C0C,
- 0x033, 0x00000022, 0x03F, 0x00000C0F, 0x033, 0x00000023,
- 0x03F, 0x00000C2C, 0x033, 0x00000024, 0x03F, 0x00000C2F,
- 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
- 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000C90,
- 0x033, 0x00000028, 0x03F, 0x00000CD0, 0x033, 0x00000029,
- 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5,
- 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
- 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
- 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
- 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
- 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
- 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
- 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
- 0x03F, 0x000000F3, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
- 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
- 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
- 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
- 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
- 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
- 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
- 0x03F, 0x000000F3, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
- 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
- 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
- 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
- 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
- 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
- 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
- 0x03F, 0x000000F3, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000060, 0x03F, 0x00000005, 0x033, 0x00000061,
- 0x03F, 0x00000008, 0x033, 0x00000062, 0x03F, 0x0000000B,
- 0x033, 0x00000063, 0x03F, 0x0000000E, 0x033, 0x00000064,
- 0x03F, 0x0000002B, 0x033, 0x00000065, 0x03F, 0x00000068,
- 0x033, 0x00000066, 0x03F, 0x0000006B, 0x033, 0x00000067,
- 0x03F, 0x0000006E, 0x033, 0x00000068, 0x03F, 0x00000071,
- 0x033, 0x00000069, 0x03F, 0x00000074, 0x033, 0x0000006A,
- 0x03F, 0x00000077, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
- 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
- 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
- 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
- 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
- 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
- 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
- 0x03F, 0x000000F3, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
- 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
- 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
- 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
- 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
- 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
- 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
- 0x03F, 0x000000F3, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000060, 0x03F, 0x00000007, 0x033, 0x00000061,
- 0x03F, 0x0000000A, 0x033, 0x00000062, 0x03F, 0x0000000D,
- 0x033, 0x00000063, 0x03F, 0x0000002A, 0x033, 0x00000064,
- 0x03F, 0x0000002D, 0x033, 0x00000065, 0x03F, 0x00000030,
- 0x033, 0x00000066, 0x03F, 0x0000006D, 0x033, 0x00000067,
- 0x03F, 0x00000070, 0x033, 0x00000068, 0x03F, 0x000000ED,
- 0x033, 0x00000069, 0x03F, 0x000000F0, 0x033, 0x0000006A,
- 0x03F, 0x000000F3, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000060, 0x03F, 0x00000005, 0x033, 0x00000061,
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- 0x03F, 0x00000C09, 0x033, 0x000000A1, 0x03F, 0x00000C0C,
- 0x033, 0x000000A2, 0x03F, 0x00000C0F, 0x033, 0x000000A3,
- 0x03F, 0x00000C2C, 0x033, 0x000000A4, 0x03F, 0x00000C2F,
- 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
- 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000C90,
- 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
- 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
- 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x0EF, 0x00000400,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x0000047C, 0x033, 0x00000001, 0x03F, 0x0000047C,
- 0x033, 0x00000002, 0x03F, 0x0000047C, 0x033, 0x00000003,
- 0x03F, 0x0000047C, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001,
- 0x03F, 0x0000047C, 0x033, 0x00000002, 0x03F, 0x0000047C,
- 0x033, 0x00000003, 0x03F, 0x0000047C, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000047C,
- 0x033, 0x00000001, 0x03F, 0x0000047C, 0x033, 0x00000002,
- 0x03F, 0x0000047C, 0x033, 0x00000003, 0x03F, 0x0000047C,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x0000047C, 0x033, 0x00000001, 0x03F, 0x0000047C,
- 0x033, 0x00000002, 0x03F, 0x0000047C, 0x033, 0x00000003,
- 0x03F, 0x0000047C, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001,
- 0x03F, 0x0000047C, 0x033, 0x00000002, 0x03F, 0x0000047C,
- 0x033, 0x00000003, 0x03F, 0x0000047C, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000047C,
- 0x033, 0x00000001, 0x03F, 0x0000047C, 0x033, 0x00000002,
- 0x03F, 0x0000047C, 0x033, 0x00000003, 0x03F, 0x0000047C,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x0000047C, 0x033, 0x00000001, 0x03F, 0x0000047C,
- 0x033, 0x00000002, 0x03F, 0x0000047C, 0x033, 0x00000003,
- 0x03F, 0x0000047C, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x0000047C, 0x033, 0x00000001,
- 0x03F, 0x0000047C, 0x033, 0x00000002, 0x03F, 0x0000047C,
- 0x033, 0x00000003, 0x03F, 0x0000047C, 0xA0000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x000004BB, 0x033, 0x00000001,
- 0x03F, 0x000004BB, 0x033, 0x00000002, 0x03F, 0x000004BB,
- 0x033, 0x00000003, 0x03F, 0x000004BB, 0xB0000000, 0x00000000,
- 0x0EF, 0x00000000, 0x0EF, 0x00000100, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726,
- 0x033, 0x00000001, 0x03F, 0x00001726, 0x033, 0x00000002,
- 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00001726, 0x033, 0x00000001, 0x03F, 0x00001726,
- 0x033, 0x00000002, 0x03F, 0x00001726, 0x033, 0x00000003,
- 0x03F, 0x00001726, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x00001726, 0x033, 0x00000001,
- 0x03F, 0x00001726, 0x033, 0x00000002, 0x03F, 0x00001726,
- 0x033, 0x00000003, 0x03F, 0x00001726, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726,
- 0x033, 0x00000001, 0x03F, 0x00001726, 0x033, 0x00000002,
- 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00001726, 0x033, 0x00000001, 0x03F, 0x00001726,
- 0x033, 0x00000002, 0x03F, 0x00001726, 0x033, 0x00000003,
- 0x03F, 0x00001726, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x00001726, 0x033, 0x00000001,
- 0x03F, 0x00001726, 0x033, 0x00000002, 0x03F, 0x00001726,
- 0x033, 0x00000003, 0x03F, 0x00001726, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00001726,
- 0x033, 0x00000001, 0x03F, 0x00001726, 0x033, 0x00000002,
- 0x03F, 0x00001726, 0x033, 0x00000003, 0x03F, 0x00001726,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00001726, 0x033, 0x00000001, 0x03F, 0x00001726,
- 0x033, 0x00000002, 0x03F, 0x00001726, 0x033, 0x00000003,
- 0x03F, 0x00001726, 0xA0000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000F34, 0x033, 0x00000001, 0x03F, 0x00000F34,
- 0x033, 0x00000002, 0x03F, 0x00000F34, 0x033, 0x00000003,
- 0x03F, 0x00000F34, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x081, 0x0000F400,
- 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
- 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
- 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
- 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
- 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
- 0x058, 0x00082030, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
- 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
- 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400,
- 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
- 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
- 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
- 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
- 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
- 0x058, 0x00082030, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
- 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
- 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400,
- 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
- 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
- 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
- 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
- 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
- 0x058, 0x00082030, 0xA0000000, 0x00000000, 0x081, 0x0000F000,
- 0x087, 0x00016040, 0x051, 0x00000C00, 0x052, 0x0007C241,
- 0x053, 0x0001C069, 0x054, 0x00078032, 0x057, 0x0000CE0A,
- 0x058, 0x00058750, 0xB0000000, 0x00000000, 0x0EF, 0x00000800,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
- 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
- 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
- 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
- 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
- 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
- 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
- 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
- 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
- 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
- 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
- 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
- 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
- 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
- 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
- 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
- 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
- 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
- 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
- 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
- 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
- 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
- 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
- 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
- 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
- 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
- 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
- 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
- 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
- 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
- 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
- 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
- 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
- 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
- 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
- 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
- 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
- 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
- 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
- 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
- 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
- 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
- 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000003, 0x033, 0x00000001, 0x03F, 0x00000006,
- 0x033, 0x00000002, 0x03F, 0x00000009, 0x033, 0x00000003,
- 0x03F, 0x00000026, 0x033, 0x00000004, 0x03F, 0x00000029,
- 0x033, 0x00000005, 0x03F, 0x0000002C, 0x033, 0x00000006,
- 0x03F, 0x0000002F, 0x033, 0x00000007, 0x03F, 0x00000033,
- 0x033, 0x00000008, 0x03F, 0x00000036, 0x033, 0x00000009,
- 0x03F, 0x00000039, 0x033, 0x0000000A, 0x03F, 0x0000003C,
- 0xA0000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0005142C,
- 0x033, 0x00000001, 0x03F, 0x0005144B, 0x033, 0x00000002,
- 0x03F, 0x0005144E, 0x033, 0x00000003, 0x03F, 0x00051C69,
- 0x033, 0x00000004, 0x03F, 0x00051C6C, 0x033, 0x00000005,
- 0x03F, 0x00051C6F, 0x033, 0x00000006, 0x03F, 0x00051CEB,
- 0x033, 0x00000007, 0x03F, 0x00051CEE, 0x033, 0x00000008,
- 0x03F, 0x00051CF1, 0x033, 0x00000009, 0x03F, 0x00051CF4,
- 0x033, 0x0000000A, 0x03F, 0x00051CF7, 0xB0000000, 0x00000000,
- 0x0EF, 0x00000000, 0x0EF, 0x00000010, 0x033, 0x00000000,
- 0x008, 0x0009C060, 0x033, 0x00000001, 0x008, 0x0009C060,
- 0x0EF, 0x00000000, 0x033, 0x000000A2, 0x0EF, 0x00080000,
- 0x03E, 0x0000593F, 0x03F, 0x000C0F4F, 0x0EF, 0x00000000,
- 0x033, 0x000000A3, 0x0EF, 0x00080000, 0x03E, 0x00005934,
- 0x03F, 0x0005AFCF, 0x0EF, 0x00000000,
-
-};
-
-void odm_read_and_config_mp_8822b_radioa(struct phy_dm_struct *dm)
-{
- u32 i = 0;
- u8 c_cond;
- bool is_matched = true, is_skipped = false;
- u32 *array = array_mp_8822b_radioa;
-
- u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===> %s\n", __func__);
-
- for (; (i + 1) < ARRAY_SIZE(array_mp_8822b_radioa); i = i + 2) {
- v1 = array[i];
- v2 = array[i + 1];
-
- if (v1 & BIT(31)) { /* positive condition*/
- c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
- if (c_cond == COND_ENDIF) { /*end*/
- is_matched = true;
- is_skipped = false;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
- } else if (c_cond == COND_ELSE) { /*else*/
- is_matched = is_skipped ? false : true;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
- } else { /*if , else if*/
- pre_v1 = v1;
- pre_v2 = v2;
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "IF or ELSE IF\n");
- }
- } else if (v1 & BIT(30)) { /*negative condition*/
- if (is_skipped) {
- is_matched = false;
- continue;
- }
-
- if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
- is_matched = true;
- is_skipped = true;
- } else {
- is_matched = false;
- is_skipped = false;
- }
- } else if (is_matched) {
- odm_config_rf_radio_a_8822b(dm, v1, v2);
- }
- }
-}
-
-u32 odm_get_version_mp_8822b_radioa(void) { return 67; }
-
-/******************************************************************************
- * radiob.TXT
- ******************************************************************************/
-
-static u32 array_mp_8822b_radiob[] = {
- 0x000, 0x00030000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x0004002D, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
- 0x001, 0x00040029, 0xA0000000, 0x00000000, 0x001, 0x00040029,
- 0xB0000000, 0x00000000, 0x018, 0x00010D24, 0x0EF, 0x00080000,
- 0x033, 0x00000002, 0x03E, 0x0000003F, 0x03F, 0x000C0F4E,
- 0x033, 0x00000001, 0x03E, 0x00000034, 0x03F, 0x0004080E,
- 0x0EF, 0x00080000, 0x0DF, 0x00002449, 0x033, 0x00000024,
- 0x03E, 0x0000003F, 0x03F, 0x00060FDE, 0x0EF, 0x00000000,
- 0x0EF, 0x00080000, 0x033, 0x00000025, 0x03E, 0x00000037,
- 0x03F, 0x0007EFCE, 0x0EF, 0x00000000, 0x0EF, 0x00080000,
- 0x033, 0x00000026, 0x03E, 0x00000037, 0x03F, 0x000DEFCE,
- 0x0EF, 0x00000000, 0x0DF, 0x00000009, 0x018, 0x00010524,
- 0x089, 0x00000207, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x08A, 0x000FF186, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x08A, 0x000FE186, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x08A, 0x000FF186, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x08A, 0x000FF186, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x08A, 0x000FF186, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x08A, 0x000FE186, 0xA0000000, 0x00000000, 0x08A, 0x000FF186,
- 0xB0000000, 0x00000000, 0x08B, 0x00061E3C, 0x08C, 0x000112C7,
- 0x08D, 0x000F4988, 0x08E, 0x00064D40, 0x0EF, 0x00020000,
- 0x033, 0x00000007, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x03E, 0x00004040, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x03E, 0x00004080, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004040, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004040, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x03E, 0x00004040, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x03E, 0x00004080, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004040, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004040, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004040, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004000, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004000, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004000, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004040, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004040, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
- 0x03E, 0x00004000, 0xA0000000, 0x00000000, 0x03E, 0x00004000,
- 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C0006, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C0006, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
- 0x03F, 0x000C3186, 0xA0000000, 0x00000000, 0x03F, 0x000C3186,
- 0xB0000000, 0x00000000, 0x033, 0x00000006, 0x03E, 0x00004080,
- 0x03F, 0x000C3186, 0x033, 0x00000005, 0x03E, 0x000040C8,
- 0x03F, 0x000C3186, 0x033, 0x00000004, 0x03E, 0x00004190,
- 0x03F, 0x000C3186, 0x033, 0x00000003, 0x03E, 0x00004998,
- 0x03F, 0x000C3186, 0x033, 0x00000002, 0x03E, 0x00005840,
- 0x03F, 0x000C3186, 0x033, 0x00000001, 0x03E, 0x000058C2,
- 0x03F, 0x000C3186, 0x033, 0x00000000, 0x03E, 0x00005930,
- 0x03F, 0x000C3186, 0x033, 0x0000000F, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03E, 0x00004080, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004040, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x03E, 0x00004000, 0xA0000000, 0x00000000,
- 0x03E, 0x00004000, 0xB0000000, 0x00000000, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C0006, 0x93001000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x000C3186, 0xA0000000, 0x00000000,
- 0x03F, 0x000C3186, 0xB0000000, 0x00000000, 0x033, 0x0000000E,
- 0x03E, 0x00004080, 0x03F, 0x000C3186, 0x033, 0x0000000D,
- 0x03E, 0x000040C8, 0x03F, 0x000C3186, 0x033, 0x0000000C,
- 0x03E, 0x00004190, 0x03F, 0x000C3186, 0x033, 0x0000000B,
- 0x03E, 0x00004998, 0x03F, 0x000C3186, 0x033, 0x0000000A,
- 0x03E, 0x00005840, 0x03F, 0x000C3186, 0x033, 0x00000009,
- 0x03E, 0x000058C2, 0x03F, 0x000C3186, 0x033, 0x00000008,
- 0x03E, 0x00005930, 0x03F, 0x000C3186, 0x033, 0x00000017,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03E, 0x00004080,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
- 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
- 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004040,
- 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00004000,
- 0xA0000000, 0x00000000, 0x03E, 0x00004000, 0xB0000000, 0x00000000,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000DFF86,
- 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C0006,
- 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000C3186,
- 0xA0000000, 0x00000000, 0x03F, 0x000C3186, 0xB0000000, 0x00000000,
- 0x033, 0x00000016, 0x03E, 0x00004080, 0x03F, 0x000C3186,
- 0x033, 0x00000015, 0x03E, 0x000040C8, 0x03F, 0x000C3186,
- 0x033, 0x00000014, 0x03E, 0x00004190, 0x03F, 0x000C3186,
- 0x033, 0x00000013, 0x03E, 0x00004998, 0x03F, 0x000C3186,
- 0x033, 0x00000012, 0x03E, 0x00005840, 0x03F, 0x000C3186,
- 0x033, 0x00000011, 0x03E, 0x000058C2, 0x03F, 0x000C3186,
- 0x033, 0x00000010, 0x03E, 0x00005930, 0x03F, 0x000C3186,
- 0x0EF, 0x00000000, 0x0EF, 0x00004000, 0x033, 0x00000000,
- 0x03F, 0x0000000A, 0x033, 0x00000001, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000002, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x93001000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000005, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x03F, 0x00000000, 0xA0000000, 0x00000000,
- 0x03F, 0x00000005, 0xB0000000, 0x00000000, 0x033, 0x00000002,
- 0x03F, 0x00000000, 0x0EF, 0x00000000, 0x018, 0x00000401,
- 0x084, 0x00001209, 0x086, 0x000001A0, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x087, 0x00068080, 0xA0000000, 0x00000000,
- 0x087, 0x000E8180, 0xB0000000, 0x00000000, 0x088, 0x00070020,
- 0x0DE, 0x00000010, 0x0EF, 0x00008000, 0x033, 0x0000000F,
- 0x03F, 0x0000003C, 0x033, 0x0000000E, 0x03F, 0x00000038,
- 0x033, 0x0000000D, 0x03F, 0x00000030, 0x033, 0x0000000C,
- 0x03F, 0x00000028, 0x033, 0x0000000B, 0x03F, 0x00000020,
- 0x033, 0x0000000A, 0x03F, 0x00000018, 0x033, 0x00000009,
- 0x03F, 0x00000010, 0x033, 0x00000008, 0x03F, 0x00000008,
- 0x033, 0x00000007, 0x03F, 0x0000003C, 0x033, 0x00000006,
- 0x03F, 0x00000038, 0x033, 0x00000005, 0x03F, 0x00000030,
- 0x033, 0x00000004, 0x03F, 0x00000028, 0x033, 0x00000003,
- 0x03F, 0x00000020, 0x033, 0x00000002, 0x03F, 0x00000018,
- 0x033, 0x00000001, 0x03F, 0x00000010, 0x033, 0x00000000,
- 0x03F, 0x00000008, 0x0EF, 0x00000000, 0x018, 0x00018D24,
- 0xFFE, 0x00000000, 0xFFE, 0x00000000, 0xFFE, 0x00000000,
- 0xFFE, 0x00000000, 0x018, 0x00010D24, 0x01B, 0x00075A40,
- 0x0EE, 0x00000002, 0x033, 0x00000000, 0x03F, 0x00000004,
- 0x033, 0x00000001, 0x03F, 0x00000004, 0x033, 0x00000002,
- 0x03F, 0x00000004, 0x033, 0x00000003, 0x03F, 0x00000004,
- 0x033, 0x00000004, 0x03F, 0x00000004, 0x033, 0x00000005,
- 0x03F, 0x00000006, 0x033, 0x00000006, 0x03F, 0x00000002,
- 0x033, 0x00000007, 0x03F, 0x00000000, 0x0EE, 0x00000000,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x061, 0x0005D4A0,
- 0x062, 0x0000D203, 0x063, 0x00000062, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203,
- 0x063, 0x00000062, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1,
- 0x062, 0x0000D3A2, 0x063, 0x00000062, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x061, 0x0005D4A0, 0x062, 0x0000D203,
- 0x063, 0x00000062, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x061, 0x0005D4A0, 0x062, 0x0000D203, 0x063, 0x00000062,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D4A0,
- 0x062, 0x0000D203, 0x063, 0x00000062, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2,
- 0x063, 0x00000062, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000062,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1,
- 0x062, 0x0000D3A2, 0x063, 0x00000002, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2,
- 0x063, 0x00000002, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D3D1, 0x062, 0x0000D3A2, 0x063, 0x00000002,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D2A1,
- 0x062, 0x0000D3A2, 0x063, 0x00000062, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x061, 0x0005D3D1, 0x062, 0x0000D3A2,
- 0x063, 0x00000002, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000002,
- 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x061, 0x0005D3D1,
- 0x062, 0x0000D3A2, 0x063, 0x00000002, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x061, 0x0005D2A1, 0x062, 0x0000D3A2,
- 0x063, 0x00000002, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
- 0x061, 0x0005D2A1, 0x062, 0x0000D3A2, 0x063, 0x00000002,
- 0xA0000000, 0x00000000, 0x061, 0x0005D3D0, 0x062, 0x0000D303,
- 0x063, 0x00000002, 0xB0000000, 0x00000000, 0x0EF, 0x00000200,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x030, 0x000004A3,
- 0x030, 0x000014A3, 0x030, 0x000024A3, 0x030, 0x000034A3,
- 0x030, 0x000044A3, 0x030, 0x000054A3, 0x030, 0x000064A3,
- 0x030, 0x000074A3, 0x030, 0x000084A3, 0x030, 0x000094A3,
- 0x030, 0x0000A4A3, 0x030, 0x0000B4A3, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x030, 0x000004A3, 0x030, 0x000014A3,
- 0x030, 0x000024A3, 0x030, 0x000034A3, 0x030, 0x000044A3,
- 0x030, 0x000054A3, 0x030, 0x000064A3, 0x030, 0x000074A3,
- 0x030, 0x000084A3, 0x030, 0x000094A3, 0x030, 0x0000A4A3,
- 0x030, 0x0000B4A3, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x000004A3, 0x030, 0x000014A3, 0x030, 0x000024A3,
- 0x030, 0x000034A3, 0x030, 0x000044A3, 0x030, 0x000054A3,
- 0x030, 0x000064A3, 0x030, 0x000074A3, 0x030, 0x000084A3,
- 0x030, 0x000094A3, 0x030, 0x0000A4A3, 0x030, 0x0000B4A3,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000002A6,
- 0x030, 0x000012A6, 0x030, 0x000022A6, 0x030, 0x000032A6,
- 0x030, 0x000042A6, 0x030, 0x000052A6, 0x030, 0x000062A6,
- 0x030, 0x000072A6, 0x030, 0x000082A6, 0x030, 0x000092A6,
- 0x030, 0x0000A2A6, 0x030, 0x0000B2A6, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x030, 0x000004A0, 0x030, 0x000014A0,
- 0x030, 0x000024A0, 0x030, 0x000034A0, 0x030, 0x000044A0,
- 0x030, 0x000054A0, 0x030, 0x000064A0, 0x030, 0x000074A0,
- 0x030, 0x000084A0, 0x030, 0x000094A0, 0x030, 0x0000A4A0,
- 0x030, 0x0000B4A0, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0,
- 0x030, 0x000034A0, 0x030, 0x000044A0, 0x030, 0x000054A0,
- 0x030, 0x000064A0, 0x030, 0x000074A0, 0x030, 0x000084A0,
- 0x030, 0x000094A0, 0x030, 0x0000A4A0, 0x030, 0x0000B4A0,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000004A0,
- 0x030, 0x000014A0, 0x030, 0x000024A0, 0x030, 0x000034A0,
- 0x030, 0x000044A0, 0x030, 0x000054A0, 0x030, 0x000064A0,
- 0x030, 0x000074A0, 0x030, 0x000084A0, 0x030, 0x000094A0,
- 0x030, 0x0000A4A0, 0x030, 0x0000B4A0, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x000002A1, 0x030, 0x000012A1,
- 0x030, 0x000022A1, 0x030, 0x000032A1, 0x030, 0x000042A1,
- 0x030, 0x000052A1, 0x030, 0x000062A1, 0x030, 0x000072A1,
- 0x030, 0x000082A1, 0x030, 0x000092A1, 0x030, 0x0000A2A1,
- 0x030, 0x0000B2A1, 0x9300200c, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x000002A6, 0x030, 0x000012A6, 0x030, 0x000022A6,
- 0x030, 0x000032A6, 0x030, 0x000042A6, 0x030, 0x000052A6,
- 0x030, 0x000062A6, 0x030, 0x000072A6, 0x030, 0x000082A6,
- 0x030, 0x000092A6, 0x030, 0x0000A2A6, 0x030, 0x0000B2A6,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000002F4,
- 0x030, 0x000012F4, 0x030, 0x000022F4, 0x030, 0x000032F4,
- 0x030, 0x00004365, 0x030, 0x00005365, 0x030, 0x00006365,
- 0x030, 0x00007365, 0x030, 0x000082A4, 0x030, 0x000092A4,
- 0x030, 0x0000A2A4, 0x030, 0x0000B2A4, 0x93002100, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x000004A4, 0x030, 0x000014A4,
- 0x030, 0x000024A4, 0x030, 0x000034A4, 0x030, 0x000043A4,
- 0x030, 0x000053A4, 0x030, 0x000063A4, 0x030, 0x000073A4,
- 0x030, 0x000083A5, 0x030, 0x000093A5, 0x030, 0x0000A3A5,
- 0x030, 0x0000B3A5, 0x93011000, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x000003A1, 0x030, 0x000013A1, 0x030, 0x000023A1,
- 0x030, 0x000033A1, 0x030, 0x000043A4, 0x030, 0x000053A4,
- 0x030, 0x000063A4, 0x030, 0x000073A4, 0x030, 0x000083A6,
- 0x030, 0x000093A6, 0x030, 0x0000A3A6, 0x030, 0x0000B3A6,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000002A1,
- 0x030, 0x000012A1, 0x030, 0x000022A1, 0x030, 0x000032A1,
- 0x030, 0x000042A1, 0x030, 0x000052A1, 0x030, 0x000062A1,
- 0x030, 0x000072A1, 0x030, 0x000082A1, 0x030, 0x000092A1,
- 0x030, 0x0000A2A1, 0x030, 0x0000B2A1, 0x90001004, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x00000382, 0x030, 0x00001382,
- 0x030, 0x00002382, 0x030, 0x00003382, 0x030, 0x00004445,
- 0x030, 0x00005445, 0x030, 0x00006445, 0x030, 0x00007445,
- 0x030, 0x00008425, 0x030, 0x00009425, 0x030, 0x0000A425,
- 0x030, 0x0000B425, 0x93002000, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x00000303, 0x030, 0x00001303, 0x030, 0x00002303,
- 0x030, 0x00003303, 0x030, 0x000043A4, 0x030, 0x000053A4,
- 0x030, 0x000063A4, 0x030, 0x000073A4, 0x030, 0x00008365,
- 0x030, 0x00009365, 0x030, 0x0000A365, 0x030, 0x0000B365,
- 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A1,
- 0x030, 0x000013A1, 0x030, 0x000023A1, 0x030, 0x000033A1,
- 0x030, 0x00004364, 0x030, 0x00005364, 0x030, 0x00006364,
- 0x030, 0x00007364, 0x030, 0x00008564, 0x030, 0x00009564,
- 0x030, 0x0000A564, 0x030, 0x0000B564, 0x90002100, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x000004A1, 0x030, 0x000014A1,
- 0x030, 0x000024A1, 0x030, 0x000034A1, 0x030, 0x000043A1,
- 0x030, 0x000053A1, 0x030, 0x000063A1, 0x030, 0x000073A1,
- 0x030, 0x000083A1, 0x030, 0x000093A1, 0x030, 0x0000A3A1,
- 0x030, 0x0000B3A1, 0x90002000, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x000004A0, 0x030, 0x000014A0, 0x030, 0x000024A0,
- 0x030, 0x000034A0, 0x030, 0x000043A1, 0x030, 0x000053A1,
- 0x030, 0x000063A1, 0x030, 0x000073A1, 0x030, 0x000083A2,
- 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
- 0xA0000000, 0x00000000, 0x030, 0x000002D0, 0x030, 0x000012D0,
- 0x030, 0x000022D0, 0x030, 0x000032D0, 0x030, 0x000042D0,
- 0x030, 0x000052D0, 0x030, 0x000062D0, 0x030, 0x000072D0,
- 0x030, 0x000082D0, 0x030, 0x000092D0, 0x030, 0x0000A2D0,
- 0x030, 0x0000B2D0, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
- 0x0EF, 0x00000080, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x030, 0x00000203, 0x030, 0x00001203, 0x030, 0x00002203,
- 0x030, 0x00003203, 0x030, 0x00004203, 0x030, 0x00005203,
- 0x030, 0x00006203, 0x030, 0x00007203, 0x030, 0x00008203,
- 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x030, 0x00000203,
- 0x030, 0x00001203, 0x030, 0x00002203, 0x030, 0x00003203,
- 0x030, 0x00004203, 0x030, 0x00005203, 0x030, 0x00006203,
- 0x030, 0x00007203, 0x030, 0x00008203, 0x030, 0x00009203,
- 0x030, 0x0000A203, 0x030, 0x0000B203, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203,
- 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
- 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
- 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
- 0x030, 0x0000B203, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
- 0x030, 0x000033A2, 0x030, 0x000043A2, 0x030, 0x000053A2,
- 0x030, 0x000063A2, 0x030, 0x000073A2, 0x030, 0x000083A2,
- 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x030, 0x00000203,
- 0x030, 0x00001203, 0x030, 0x00002203, 0x030, 0x00003203,
- 0x030, 0x00004203, 0x030, 0x00005203, 0x030, 0x00006203,
- 0x030, 0x00007203, 0x030, 0x00008203, 0x030, 0x00009203,
- 0x030, 0x0000A203, 0x030, 0x0000B203, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x030, 0x00000203, 0x030, 0x00001203,
- 0x030, 0x00002203, 0x030, 0x00003203, 0x030, 0x00004203,
- 0x030, 0x00005203, 0x030, 0x00006203, 0x030, 0x00007203,
- 0x030, 0x00008203, 0x030, 0x00009203, 0x030, 0x0000A203,
- 0x030, 0x0000B203, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x00000203, 0x030, 0x00001203, 0x030, 0x00002203,
- 0x030, 0x00003203, 0x030, 0x00004203, 0x030, 0x00005203,
- 0x030, 0x00006203, 0x030, 0x00007203, 0x030, 0x00008203,
- 0x030, 0x00009203, 0x030, 0x0000A203, 0x030, 0x0000B203,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2,
- 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
- 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
- 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
- 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x9300200c, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x93012100, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x000003A3, 0x030, 0x000013A3, 0x030, 0x000023A3,
- 0x030, 0x000033A3, 0x030, 0x000043A4, 0x030, 0x000053A4,
- 0x030, 0x000063A4, 0x030, 0x000073A4, 0x030, 0x000083A3,
- 0x030, 0x000093A3, 0x030, 0x0000A3A3, 0x030, 0x0000B3A3,
- 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2,
- 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
- 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
- 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
- 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x93011000, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x9000200c, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
- 0x030, 0x000033A2, 0x030, 0x000043A2, 0x030, 0x000053A2,
- 0x030, 0x000063A2, 0x030, 0x000073A2, 0x030, 0x000083A2,
- 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2,
- 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
- 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
- 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
- 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x93002000, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0x93001000, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x000003A2, 0x030, 0x000013A2, 0x030, 0x000023A2,
- 0x030, 0x000033A2, 0x030, 0x000043A2, 0x030, 0x000053A2,
- 0x030, 0x000063A2, 0x030, 0x000073A2, 0x030, 0x000083A2,
- 0x030, 0x000093A2, 0x030, 0x0000A3A2, 0x030, 0x0000B3A2,
- 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x000003A2,
- 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
- 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
- 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
- 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0x90002000, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x000003A2, 0x030, 0x000013A2,
- 0x030, 0x000023A2, 0x030, 0x000033A2, 0x030, 0x000043A2,
- 0x030, 0x000053A2, 0x030, 0x000063A2, 0x030, 0x000073A2,
- 0x030, 0x000083A2, 0x030, 0x000093A2, 0x030, 0x0000A3A2,
- 0x030, 0x0000B3A2, 0xA0000000, 0x00000000, 0x030, 0x000003A2,
- 0x030, 0x000013A2, 0x030, 0x000023A2, 0x030, 0x000033A2,
- 0x030, 0x000043A2, 0x030, 0x000053A2, 0x030, 0x000063A2,
- 0x030, 0x000073A2, 0x030, 0x000083A2, 0x030, 0x000093A2,
- 0x030, 0x0000A3A2, 0x030, 0x0000B3A2, 0xB0000000, 0x00000000,
- 0x0EF, 0x00000000, 0x0EF, 0x00000040, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333,
- 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000,
- 0x030, 0x00006000, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011,
- 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333,
- 0x030, 0x00002011, 0x030, 0x00004777, 0x030, 0x00005777,
- 0x030, 0x00006777, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011,
- 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333,
- 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000,
- 0x030, 0x00006000, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x00000645, 0x030, 0x00001333, 0x030, 0x00002011,
- 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
- 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000645,
- 0x030, 0x00001333, 0x030, 0x00002011, 0x030, 0x00004777,
- 0x030, 0x00005777, 0x030, 0x00006777, 0x93012100, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x00000660, 0x030, 0x00001341,
- 0x030, 0x00002220, 0x030, 0x00004777, 0x030, 0x00005777,
- 0x030, 0x00006777, 0x93002100, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x00000764, 0x030, 0x00001452, 0x030, 0x00002220,
- 0x030, 0x00004777, 0x030, 0x00005777, 0x030, 0x00006777,
- 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000764,
- 0x030, 0x00001632, 0x030, 0x00002421, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0x9000200c, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x00000645, 0x030, 0x00001333,
- 0x030, 0x00002011, 0x030, 0x00004000, 0x030, 0x00005000,
- 0x030, 0x00006000, 0x90001004, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x00000764, 0x030, 0x00001632, 0x030, 0x00002421,
- 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
- 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000777,
- 0x030, 0x00001442, 0x030, 0x00002222, 0x030, 0x00004777,
- 0x030, 0x00005777, 0x030, 0x00006777, 0x93001000, 0x00000000,
- 0x40000000, 0x00000000, 0x030, 0x00000764, 0x030, 0x00001632,
- 0x030, 0x00002421, 0x030, 0x00004000, 0x030, 0x00005000,
- 0x030, 0x00006000, 0x90002100, 0x00000000, 0x40000000, 0x00000000,
- 0x030, 0x00000775, 0x030, 0x00001222, 0x030, 0x00002210,
- 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
- 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x030, 0x00000775,
- 0x030, 0x00001422, 0x030, 0x00002210, 0x030, 0x00004000,
- 0x030, 0x00005000, 0x030, 0x00006000, 0xA0000000, 0x00000000,
- 0x030, 0x00000764, 0x030, 0x00001632, 0x030, 0x00002421,
- 0x030, 0x00004000, 0x030, 0x00005000, 0x030, 0x00006000,
- 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x0EF, 0x00000800,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
- 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
- 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
- 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
- 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
- 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
- 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
- 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
- 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
- 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
- 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
- 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
- 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
- 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
- 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
- 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
- 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
- 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
- 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000005, 0x033, 0x00000021, 0x03F, 0x00000008,
- 0x033, 0x00000022, 0x03F, 0x0000000B, 0x033, 0x00000023,
- 0x03F, 0x0000000E, 0x033, 0x00000024, 0x03F, 0x0000002B,
- 0x033, 0x00000025, 0x03F, 0x00000068, 0x033, 0x00000026,
- 0x03F, 0x0000006B, 0x033, 0x00000027, 0x03F, 0x0000006E,
- 0x033, 0x00000028, 0x03F, 0x00000071, 0x033, 0x00000029,
- 0x03F, 0x00000074, 0x033, 0x0000002A, 0x03F, 0x00000077,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
- 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
- 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
- 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
- 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
- 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
- 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
- 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
- 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
- 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
- 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
- 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
- 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000007, 0x033, 0x00000021, 0x03F, 0x0000000A,
- 0x033, 0x00000022, 0x03F, 0x0000000D, 0x033, 0x00000023,
- 0x03F, 0x0000002A, 0x033, 0x00000024, 0x03F, 0x0000002D,
- 0x033, 0x00000025, 0x03F, 0x00000030, 0x033, 0x00000026,
- 0x03F, 0x0000006D, 0x033, 0x00000027, 0x03F, 0x00000070,
- 0x033, 0x00000028, 0x03F, 0x000000ED, 0x033, 0x00000029,
- 0x03F, 0x000000F0, 0x033, 0x0000002A, 0x03F, 0x000000F3,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000005, 0x033, 0x00000021, 0x03F, 0x00000008,
- 0x033, 0x00000022, 0x03F, 0x0000000B, 0x033, 0x00000023,
- 0x03F, 0x0000000E, 0x033, 0x00000024, 0x03F, 0x0000002B,
- 0x033, 0x00000025, 0x03F, 0x00000068, 0x033, 0x00000026,
- 0x03F, 0x0000006B, 0x033, 0x00000027, 0x03F, 0x0000006E,
- 0x033, 0x00000028, 0x03F, 0x00000071, 0x033, 0x00000029,
- 0x03F, 0x00000074, 0x033, 0x0000002A, 0x03F, 0x00000077,
- 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000005, 0x033, 0x00000021, 0x03F, 0x00000008,
- 0x033, 0x00000022, 0x03F, 0x0000000B, 0x033, 0x00000023,
- 0x03F, 0x0000000E, 0x033, 0x00000024, 0x03F, 0x0000002B,
- 0x033, 0x00000025, 0x03F, 0x00000068, 0x033, 0x00000026,
- 0x03F, 0x0000006B, 0x033, 0x00000027, 0x03F, 0x0000006E,
- 0x033, 0x00000028, 0x03F, 0x00000071, 0x033, 0x00000029,
- 0x03F, 0x00000074, 0x033, 0x0000002A, 0x03F, 0x00000077,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000828, 0x033, 0x00000021, 0x03F, 0x0000082B,
- 0x033, 0x00000022, 0x03F, 0x00000868, 0x033, 0x00000023,
- 0x03F, 0x00000889, 0x033, 0x00000024, 0x03F, 0x000008AA,
- 0x033, 0x00000025, 0x03F, 0x00000CE8, 0x033, 0x00000026,
- 0x03F, 0x00000CEB, 0x033, 0x00000027, 0x03F, 0x00000CEE,
- 0x033, 0x00000028, 0x03F, 0x00000CF1, 0x033, 0x00000029,
- 0x03F, 0x00000CF4, 0x033, 0x0000002A, 0x03F, 0x00000CF7,
- 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x0000042A, 0x033, 0x00000021, 0x03F, 0x00000829,
- 0x033, 0x00000022, 0x03F, 0x00000848, 0x033, 0x00000023,
- 0x03F, 0x0000084B, 0x033, 0x00000024, 0x03F, 0x00000C4C,
- 0x033, 0x00000025, 0x03F, 0x00000C8B, 0x033, 0x00000026,
- 0x03F, 0x00000CEA, 0x033, 0x00000027, 0x03F, 0x00000CED,
- 0x033, 0x00000028, 0x03F, 0x00000CF0, 0x033, 0x00000029,
- 0x03F, 0x00000CF3, 0x033, 0x0000002A, 0x03F, 0x00000CF6,
- 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000C09, 0x033, 0x00000021, 0x03F, 0x00000C0C,
- 0x033, 0x00000022, 0x03F, 0x00000C0F, 0x033, 0x00000023,
- 0x03F, 0x00000C2C, 0x033, 0x00000024, 0x03F, 0x00000C2F,
- 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
- 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000C90,
- 0x033, 0x00000028, 0x03F, 0x00000CD0, 0x033, 0x00000029,
- 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000005, 0x033, 0x00000021, 0x03F, 0x00000008,
- 0x033, 0x00000022, 0x03F, 0x0000000B, 0x033, 0x00000023,
- 0x03F, 0x0000000E, 0x033, 0x00000024, 0x03F, 0x0000002B,
- 0x033, 0x00000025, 0x03F, 0x00000068, 0x033, 0x00000026,
- 0x03F, 0x0000006B, 0x033, 0x00000027, 0x03F, 0x0000006E,
- 0x033, 0x00000028, 0x03F, 0x00000071, 0x033, 0x00000029,
- 0x03F, 0x00000074, 0x033, 0x0000002A, 0x03F, 0x00000077,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000C09, 0x033, 0x00000021, 0x03F, 0x00000C0C,
- 0x033, 0x00000022, 0x03F, 0x00000C0F, 0x033, 0x00000023,
- 0x03F, 0x00000C2C, 0x033, 0x00000024, 0x03F, 0x00000C2F,
- 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
- 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000C90,
- 0x033, 0x00000028, 0x03F, 0x00000CD0, 0x033, 0x00000029,
- 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5,
- 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000429, 0x033, 0x00000021, 0x03F, 0x00000828,
- 0x033, 0x00000022, 0x03F, 0x00000847, 0x033, 0x00000023,
- 0x03F, 0x0000084A, 0x033, 0x00000024, 0x03F, 0x00000C4B,
- 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
- 0x03F, 0x00000CEA, 0x033, 0x00000027, 0x03F, 0x00000CED,
- 0x033, 0x00000028, 0x03F, 0x00000CF0, 0x033, 0x00000029,
- 0x03F, 0x00000CF3, 0x033, 0x0000002A, 0x03F, 0x00000CF6,
- 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x00000C09, 0x033, 0x00000021, 0x03F, 0x00000C0C,
- 0x033, 0x00000022, 0x03F, 0x00000C0F, 0x033, 0x00000023,
- 0x03F, 0x00000C2C, 0x033, 0x00000024, 0x03F, 0x00000C2F,
- 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
- 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000C90,
- 0x033, 0x00000028, 0x03F, 0x00000CD0, 0x033, 0x00000029,
- 0x03F, 0x00000CF2, 0x033, 0x0000002A, 0x03F, 0x00000CF5,
- 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x0000042B, 0x033, 0x00000021, 0x03F, 0x0000082A,
- 0x033, 0x00000022, 0x03F, 0x00000849, 0x033, 0x00000023,
- 0x03F, 0x0000084C, 0x033, 0x00000024, 0x03F, 0x00000C4C,
- 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
- 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000CEB,
- 0x033, 0x00000028, 0x03F, 0x00000CEE, 0x033, 0x00000029,
- 0x03F, 0x00000CF1, 0x033, 0x0000002A, 0x03F, 0x00000CF4,
- 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000020,
- 0x03F, 0x0000042B, 0x033, 0x00000021, 0x03F, 0x0000082A,
- 0x033, 0x00000022, 0x03F, 0x00000849, 0x033, 0x00000023,
- 0x03F, 0x0000084C, 0x033, 0x00000024, 0x03F, 0x00000C4C,
- 0x033, 0x00000025, 0x03F, 0x00000C8A, 0x033, 0x00000026,
- 0x03F, 0x00000C8D, 0x033, 0x00000027, 0x03F, 0x00000CEB,
- 0x033, 0x00000028, 0x03F, 0x00000CEE, 0x033, 0x00000029,
- 0x03F, 0x00000CF1, 0x033, 0x0000002A, 0x03F, 0x00000CF4,
- 0xA0000000, 0x00000000, 0x033, 0x00000020, 0x03F, 0x00000C09,
- 0x033, 0x00000021, 0x03F, 0x00000C0C, 0x033, 0x00000022,
- 0x03F, 0x00000C0F, 0x033, 0x00000023, 0x03F, 0x00000C2C,
- 0x033, 0x00000024, 0x03F, 0x00000C2F, 0x033, 0x00000025,
- 0x03F, 0x00000C8A, 0x033, 0x00000026, 0x03F, 0x00000C8D,
- 0x033, 0x00000027, 0x03F, 0x00000C90, 0x033, 0x00000028,
- 0x03F, 0x00000CD0, 0x033, 0x00000029, 0x03F, 0x00000CF2,
- 0x033, 0x0000002A, 0x03F, 0x00000CF5, 0xB0000000, 0x00000000,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
- 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
- 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
- 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
- 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
- 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
- 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
- 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
- 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
- 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
- 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
- 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
- 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
- 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
- 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
- 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
- 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
- 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
- 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000005, 0x033, 0x00000061, 0x03F, 0x00000008,
- 0x033, 0x00000062, 0x03F, 0x0000000B, 0x033, 0x00000063,
- 0x03F, 0x0000000E, 0x033, 0x00000064, 0x03F, 0x0000002B,
- 0x033, 0x00000065, 0x03F, 0x00000068, 0x033, 0x00000066,
- 0x03F, 0x0000006B, 0x033, 0x00000067, 0x03F, 0x0000006E,
- 0x033, 0x00000068, 0x03F, 0x00000071, 0x033, 0x00000069,
- 0x03F, 0x00000074, 0x033, 0x0000006A, 0x03F, 0x00000077,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
- 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
- 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
- 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
- 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
- 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
- 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
- 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
- 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
- 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
- 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
- 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
- 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000007, 0x033, 0x00000061, 0x03F, 0x0000000A,
- 0x033, 0x00000062, 0x03F, 0x0000000D, 0x033, 0x00000063,
- 0x03F, 0x0000002A, 0x033, 0x00000064, 0x03F, 0x0000002D,
- 0x033, 0x00000065, 0x03F, 0x00000030, 0x033, 0x00000066,
- 0x03F, 0x0000006D, 0x033, 0x00000067, 0x03F, 0x00000070,
- 0x033, 0x00000068, 0x03F, 0x000000ED, 0x033, 0x00000069,
- 0x03F, 0x000000F0, 0x033, 0x0000006A, 0x03F, 0x000000F3,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000005, 0x033, 0x00000061, 0x03F, 0x00000008,
- 0x033, 0x00000062, 0x03F, 0x0000000B, 0x033, 0x00000063,
- 0x03F, 0x0000000E, 0x033, 0x00000064, 0x03F, 0x0000002B,
- 0x033, 0x00000065, 0x03F, 0x00000068, 0x033, 0x00000066,
- 0x03F, 0x0000006B, 0x033, 0x00000067, 0x03F, 0x0000006E,
- 0x033, 0x00000068, 0x03F, 0x00000071, 0x033, 0x00000069,
- 0x03F, 0x00000074, 0x033, 0x0000006A, 0x03F, 0x00000077,
- 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000005, 0x033, 0x00000061, 0x03F, 0x00000008,
- 0x033, 0x00000062, 0x03F, 0x0000000B, 0x033, 0x00000063,
- 0x03F, 0x0000000E, 0x033, 0x00000064, 0x03F, 0x0000002B,
- 0x033, 0x00000065, 0x03F, 0x00000068, 0x033, 0x00000066,
- 0x03F, 0x0000006B, 0x033, 0x00000067, 0x03F, 0x0000006E,
- 0x033, 0x00000068, 0x03F, 0x00000071, 0x033, 0x00000069,
- 0x03F, 0x00000074, 0x033, 0x0000006A, 0x03F, 0x00000077,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000842, 0x033, 0x00000061, 0x03F, 0x00000845,
- 0x033, 0x00000062, 0x03F, 0x00000866, 0x033, 0x00000063,
- 0x03F, 0x000008A6, 0x033, 0x00000064, 0x03F, 0x000008C8,
- 0x033, 0x00000065, 0x03F, 0x00000CE8, 0x033, 0x00000066,
- 0x03F, 0x00000CEB, 0x033, 0x00000067, 0x03F, 0x00000CEE,
- 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069,
- 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7,
- 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x0000042A, 0x033, 0x00000061, 0x03F, 0x00000829,
- 0x033, 0x00000062, 0x03F, 0x00000848, 0x033, 0x00000063,
- 0x03F, 0x0000084B, 0x033, 0x00000064, 0x03F, 0x00000C69,
- 0x033, 0x00000065, 0x03F, 0x00000CA9, 0x033, 0x00000066,
- 0x03F, 0x00000CEA, 0x033, 0x00000067, 0x03F, 0x00000CED,
- 0x033, 0x00000068, 0x03F, 0x00000CF0, 0x033, 0x00000069,
- 0x03F, 0x00000CF3, 0x033, 0x0000006A, 0x03F, 0x00000CF6,
- 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000C0A, 0x033, 0x00000061, 0x03F, 0x00000C0D,
- 0x033, 0x00000062, 0x03F, 0x00000C2A, 0x033, 0x00000063,
- 0x03F, 0x00000C2D, 0x033, 0x00000064, 0x03F, 0x00000C6A,
- 0x033, 0x00000065, 0x03F, 0x00000CAA, 0x033, 0x00000066,
- 0x03F, 0x00000CAD, 0x033, 0x00000067, 0x03F, 0x00000CB0,
- 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069,
- 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000005, 0x033, 0x00000061, 0x03F, 0x00000008,
- 0x033, 0x00000062, 0x03F, 0x0000000B, 0x033, 0x00000063,
- 0x03F, 0x0000000E, 0x033, 0x00000064, 0x03F, 0x0000002B,
- 0x033, 0x00000065, 0x03F, 0x00000068, 0x033, 0x00000066,
- 0x03F, 0x0000006B, 0x033, 0x00000067, 0x03F, 0x0000006E,
- 0x033, 0x00000068, 0x03F, 0x00000071, 0x033, 0x00000069,
- 0x03F, 0x00000074, 0x033, 0x0000006A, 0x03F, 0x00000077,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000C0A, 0x033, 0x00000061, 0x03F, 0x00000C0D,
- 0x033, 0x00000062, 0x03F, 0x00000C2A, 0x033, 0x00000063,
- 0x03F, 0x00000C2D, 0x033, 0x00000064, 0x03F, 0x00000C6A,
- 0x033, 0x00000065, 0x03F, 0x00000CAA, 0x033, 0x00000066,
- 0x03F, 0x00000CAD, 0x033, 0x00000067, 0x03F, 0x00000CB0,
- 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069,
- 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7,
- 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000429, 0x033, 0x00000061, 0x03F, 0x00000828,
- 0x033, 0x00000062, 0x03F, 0x00000847, 0x033, 0x00000063,
- 0x03F, 0x0000084A, 0x033, 0x00000064, 0x03F, 0x00000C4B,
- 0x033, 0x00000065, 0x03F, 0x00000C8A, 0x033, 0x00000066,
- 0x03F, 0x00000CEA, 0x033, 0x00000067, 0x03F, 0x00000CED,
- 0x033, 0x00000068, 0x03F, 0x00000CF0, 0x033, 0x00000069,
- 0x03F, 0x00000CF3, 0x033, 0x0000006A, 0x03F, 0x00000CF6,
- 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x00000C0A, 0x033, 0x00000061, 0x03F, 0x00000C0D,
- 0x033, 0x00000062, 0x03F, 0x00000C2A, 0x033, 0x00000063,
- 0x03F, 0x00000C2D, 0x033, 0x00000064, 0x03F, 0x00000C6A,
- 0x033, 0x00000065, 0x03F, 0x00000CAA, 0x033, 0x00000066,
- 0x03F, 0x00000CAD, 0x033, 0x00000067, 0x03F, 0x00000CB0,
- 0x033, 0x00000068, 0x03F, 0x00000CF1, 0x033, 0x00000069,
- 0x03F, 0x00000CF4, 0x033, 0x0000006A, 0x03F, 0x00000CF7,
- 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x0000042C, 0x033, 0x00000061, 0x03F, 0x0000082B,
- 0x033, 0x00000062, 0x03F, 0x0000084A, 0x033, 0x00000063,
- 0x03F, 0x0000084D, 0x033, 0x00000064, 0x03F, 0x00000C4E,
- 0x033, 0x00000065, 0x03F, 0x00000C8C, 0x033, 0x00000066,
- 0x03F, 0x00000C8F, 0x033, 0x00000067, 0x03F, 0x00000CEC,
- 0x033, 0x00000068, 0x03F, 0x00000CEF, 0x033, 0x00000069,
- 0x03F, 0x00000CF2, 0x033, 0x0000006A, 0x03F, 0x00000CF5,
- 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000060,
- 0x03F, 0x0000042C, 0x033, 0x00000061, 0x03F, 0x0000082B,
- 0x033, 0x00000062, 0x03F, 0x0000084A, 0x033, 0x00000063,
- 0x03F, 0x0000084D, 0x033, 0x00000064, 0x03F, 0x00000C4E,
- 0x033, 0x00000065, 0x03F, 0x00000C8C, 0x033, 0x00000066,
- 0x03F, 0x00000C8F, 0x033, 0x00000067, 0x03F, 0x00000CEC,
- 0x033, 0x00000068, 0x03F, 0x00000CEF, 0x033, 0x00000069,
- 0x03F, 0x00000CF2, 0x033, 0x0000006A, 0x03F, 0x00000CF5,
- 0xA0000000, 0x00000000, 0x033, 0x00000060, 0x03F, 0x00000C0A,
- 0x033, 0x00000061, 0x03F, 0x00000C0D, 0x033, 0x00000062,
- 0x03F, 0x00000C2A, 0x033, 0x00000063, 0x03F, 0x00000C2D,
- 0x033, 0x00000064, 0x03F, 0x00000C6A, 0x033, 0x00000065,
- 0x03F, 0x00000CAA, 0x033, 0x00000066, 0x03F, 0x00000CAD,
- 0x033, 0x00000067, 0x03F, 0x00000CB0, 0x033, 0x00000068,
- 0x03F, 0x00000CF1, 0x033, 0x00000069, 0x03F, 0x00000CF4,
- 0x033, 0x0000006A, 0x03F, 0x00000CF7, 0xB0000000, 0x00000000,
- 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
- 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
- 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
- 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
- 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
- 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
- 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
- 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
- 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
- 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
- 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
- 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
- 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
- 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
- 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
- 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
- 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
- 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
- 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
- 0x9300200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000005, 0x033, 0x000000A1, 0x03F, 0x00000008,
- 0x033, 0x000000A2, 0x03F, 0x0000000B, 0x033, 0x000000A3,
- 0x03F, 0x0000000E, 0x033, 0x000000A4, 0x03F, 0x00000047,
- 0x033, 0x000000A5, 0x03F, 0x0000004A, 0x033, 0x000000A6,
- 0x03F, 0x0000004D, 0x033, 0x000000A7, 0x03F, 0x00000050,
- 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9,
- 0x03F, 0x00000056, 0x033, 0x000000AA, 0x03F, 0x00000094,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
- 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
- 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
- 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
- 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
- 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
- 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
- 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
- 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
- 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
- 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
- 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
- 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
- 0x9000100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000007, 0x033, 0x000000A1, 0x03F, 0x0000000A,
- 0x033, 0x000000A2, 0x03F, 0x0000000D, 0x033, 0x000000A3,
- 0x03F, 0x0000002A, 0x033, 0x000000A4, 0x03F, 0x0000002D,
- 0x033, 0x000000A5, 0x03F, 0x00000030, 0x033, 0x000000A6,
- 0x03F, 0x0000006D, 0x033, 0x000000A7, 0x03F, 0x00000070,
- 0x033, 0x000000A8, 0x03F, 0x000000ED, 0x033, 0x000000A9,
- 0x03F, 0x000000F0, 0x033, 0x000000AA, 0x03F, 0x000000F3,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000005, 0x033, 0x000000A1, 0x03F, 0x00000008,
- 0x033, 0x000000A2, 0x03F, 0x0000000B, 0x033, 0x000000A3,
- 0x03F, 0x0000000E, 0x033, 0x000000A4, 0x03F, 0x00000047,
- 0x033, 0x000000A5, 0x03F, 0x0000004A, 0x033, 0x000000A6,
- 0x03F, 0x0000004D, 0x033, 0x000000A7, 0x03F, 0x00000050,
- 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9,
- 0x03F, 0x00000056, 0x033, 0x000000AA, 0x03F, 0x00000094,
- 0x9300200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000005, 0x033, 0x000000A1, 0x03F, 0x00000008,
- 0x033, 0x000000A2, 0x03F, 0x0000000B, 0x033, 0x000000A3,
- 0x03F, 0x0000000E, 0x033, 0x000000A4, 0x03F, 0x00000047,
- 0x033, 0x000000A5, 0x03F, 0x0000004A, 0x033, 0x000000A6,
- 0x03F, 0x0000004D, 0x033, 0x000000A7, 0x03F, 0x00000050,
- 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9,
- 0x03F, 0x00000056, 0x033, 0x000000AA, 0x03F, 0x00000094,
- 0x93012100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000826, 0x033, 0x000000A1, 0x03F, 0x00000829,
- 0x033, 0x000000A2, 0x03F, 0x0000082C, 0x033, 0x000000A3,
- 0x03F, 0x0000082F, 0x033, 0x000000A4, 0x03F, 0x0000086C,
- 0x033, 0x000000A5, 0x03F, 0x00000CE8, 0x033, 0x000000A6,
- 0x03F, 0x00000CEB, 0x033, 0x000000A7, 0x03F, 0x00000CEE,
- 0x033, 0x000000A8, 0x03F, 0x00000CF1, 0x033, 0x000000A9,
- 0x03F, 0x00000CF4, 0x033, 0x000000AA, 0x03F, 0x00000CF7,
- 0x93002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x0000042A, 0x033, 0x000000A1, 0x03F, 0x00000829,
- 0x033, 0x000000A2, 0x03F, 0x00000848, 0x033, 0x000000A3,
- 0x03F, 0x0000084B, 0x033, 0x000000A4, 0x03F, 0x00000C4C,
- 0x033, 0x000000A5, 0x03F, 0x00000CA9, 0x033, 0x000000A6,
- 0x03F, 0x00000CEA, 0x033, 0x000000A7, 0x03F, 0x00000CED,
- 0x033, 0x000000A8, 0x03F, 0x00000CF0, 0x033, 0x000000A9,
- 0x03F, 0x00000CF3, 0x033, 0x000000AA, 0x03F, 0x00000CF6,
- 0x93011000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000C09, 0x033, 0x000000A1, 0x03F, 0x00000C0C,
- 0x033, 0x000000A2, 0x03F, 0x00000C0F, 0x033, 0x000000A3,
- 0x03F, 0x00000C2C, 0x033, 0x000000A4, 0x03F, 0x00000C2F,
- 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
- 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000C90,
- 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
- 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
- 0x9000200c, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000005, 0x033, 0x000000A1, 0x03F, 0x00000008,
- 0x033, 0x000000A2, 0x03F, 0x0000000B, 0x033, 0x000000A3,
- 0x03F, 0x0000000E, 0x033, 0x000000A4, 0x03F, 0x00000047,
- 0x033, 0x000000A5, 0x03F, 0x0000004A, 0x033, 0x000000A6,
- 0x03F, 0x0000004D, 0x033, 0x000000A7, 0x03F, 0x00000050,
- 0x033, 0x000000A8, 0x03F, 0x00000053, 0x033, 0x000000A9,
- 0x03F, 0x00000056, 0x033, 0x000000AA, 0x03F, 0x00000094,
- 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000C09, 0x033, 0x000000A1, 0x03F, 0x00000C0C,
- 0x033, 0x000000A2, 0x03F, 0x00000C0F, 0x033, 0x000000A3,
- 0x03F, 0x00000C2C, 0x033, 0x000000A4, 0x03F, 0x00000C2F,
- 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
- 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000C90,
- 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
- 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
- 0x93002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000429, 0x033, 0x000000A1, 0x03F, 0x00000828,
- 0x033, 0x000000A2, 0x03F, 0x00000847, 0x033, 0x000000A3,
- 0x03F, 0x0000084A, 0x033, 0x000000A4, 0x03F, 0x00000C4B,
- 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
- 0x03F, 0x00000CEA, 0x033, 0x000000A7, 0x03F, 0x00000CED,
- 0x033, 0x000000A8, 0x03F, 0x00000CF0, 0x033, 0x000000A9,
- 0x03F, 0x00000CF3, 0x033, 0x000000AA, 0x03F, 0x00000CF6,
- 0x93001000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x00000C09, 0x033, 0x000000A1, 0x03F, 0x00000C0C,
- 0x033, 0x000000A2, 0x03F, 0x00000C0F, 0x033, 0x000000A3,
- 0x03F, 0x00000C2C, 0x033, 0x000000A4, 0x03F, 0x00000C2F,
- 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
- 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000C90,
- 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
- 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
- 0x90002100, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x0000042A, 0x033, 0x000000A1, 0x03F, 0x00000829,
- 0x033, 0x000000A2, 0x03F, 0x00000848, 0x033, 0x000000A3,
- 0x03F, 0x0000084B, 0x033, 0x000000A4, 0x03F, 0x00000C4C,
- 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
- 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000CEC,
- 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
- 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
- 0x90002000, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0,
- 0x03F, 0x0000042A, 0x033, 0x000000A1, 0x03F, 0x00000829,
- 0x033, 0x000000A2, 0x03F, 0x00000848, 0x033, 0x000000A3,
- 0x03F, 0x0000084B, 0x033, 0x000000A4, 0x03F, 0x00000C4C,
- 0x033, 0x000000A5, 0x03F, 0x00000C8A, 0x033, 0x000000A6,
- 0x03F, 0x00000C8D, 0x033, 0x000000A7, 0x03F, 0x00000CEC,
- 0x033, 0x000000A8, 0x03F, 0x00000CEF, 0x033, 0x000000A9,
- 0x03F, 0x00000CF2, 0x033, 0x000000AA, 0x03F, 0x00000CF5,
- 0xA0000000, 0x00000000, 0x033, 0x000000A0, 0x03F, 0x00000C09,
- 0x033, 0x000000A1, 0x03F, 0x00000C0C, 0x033, 0x000000A2,
- 0x03F, 0x00000C0F, 0x033, 0x000000A3, 0x03F, 0x00000C2C,
- 0x033, 0x000000A4, 0x03F, 0x00000C2F, 0x033, 0x000000A5,
- 0x03F, 0x00000C8A, 0x033, 0x000000A6, 0x03F, 0x00000C8D,
- 0x033, 0x000000A7, 0x03F, 0x00000C90, 0x033, 0x000000A8,
- 0x03F, 0x00000CEF, 0x033, 0x000000A9, 0x03F, 0x00000CF2,
- 0x033, 0x000000AA, 0x03F, 0x00000CF5, 0xB0000000, 0x00000000,
- 0x0EF, 0x00000000, 0x0EF, 0x00000400, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A,
- 0x033, 0x00000001, 0x03F, 0x0000265A, 0x033, 0x00000002,
- 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A,
- 0x9300100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x0000265A, 0x033, 0x00000001, 0x03F, 0x0000265A,
- 0x033, 0x00000002, 0x03F, 0x0000265A, 0x033, 0x00000003,
- 0x03F, 0x0000265A, 0x9300100f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x0000265A, 0x033, 0x00000001,
- 0x03F, 0x0000265A, 0x033, 0x00000002, 0x03F, 0x0000265A,
- 0x033, 0x00000003, 0x03F, 0x0000265A, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A,
- 0x033, 0x00000001, 0x03F, 0x0000265A, 0x033, 0x00000002,
- 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A,
- 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x0000265A, 0x033, 0x00000001, 0x03F, 0x0000265A,
- 0x033, 0x00000002, 0x03F, 0x0000265A, 0x033, 0x00000003,
- 0x03F, 0x0000265A, 0x9000100f, 0x05050505, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x0000265A, 0x033, 0x00000001,
- 0x03F, 0x0000265A, 0x033, 0x00000002, 0x03F, 0x0000265A,
- 0x033, 0x00000003, 0x03F, 0x0000265A, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x0000265A,
- 0x033, 0x00000001, 0x03F, 0x0000265A, 0x033, 0x00000002,
- 0x03F, 0x0000265A, 0x033, 0x00000003, 0x03F, 0x0000265A,
- 0x9000200f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x0000265A, 0x033, 0x00000001, 0x03F, 0x0000265A,
- 0x033, 0x00000002, 0x03F, 0x0000265A, 0x033, 0x00000003,
- 0x03F, 0x0000265A, 0xA0000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x000004BB, 0x033, 0x00000001, 0x03F, 0x000004BB,
- 0x033, 0x00000002, 0x03F, 0x000004BB, 0x033, 0x00000003,
- 0x03F, 0x000004BB, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
- 0x0EF, 0x00000100, 0x8300100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001,
- 0x03F, 0x00000745, 0x033, 0x00000002, 0x03F, 0x00000745,
- 0x033, 0x00000003, 0x03F, 0x00000745, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745,
- 0x033, 0x00000001, 0x03F, 0x00000745, 0x033, 0x00000002,
- 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000745, 0x033, 0x00000001, 0x03F, 0x00000745,
- 0x033, 0x00000002, 0x03F, 0x00000745, 0x033, 0x00000003,
- 0x03F, 0x00000745, 0x9300200f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001,
- 0x03F, 0x00000745, 0x033, 0x00000002, 0x03F, 0x00000745,
- 0x033, 0x00000003, 0x03F, 0x00000745, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745,
- 0x033, 0x00000001, 0x03F, 0x00000745, 0x033, 0x00000002,
- 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x033, 0x00000000,
- 0x03F, 0x00000745, 0x033, 0x00000001, 0x03F, 0x00000745,
- 0x033, 0x00000002, 0x03F, 0x00000745, 0x033, 0x00000003,
- 0x03F, 0x00000745, 0x9000100f, 0x00000000, 0x40000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x00000745, 0x033, 0x00000001,
- 0x03F, 0x00000745, 0x033, 0x00000002, 0x03F, 0x00000745,
- 0x033, 0x00000003, 0x03F, 0x00000745, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000745,
- 0x033, 0x00000001, 0x03F, 0x00000745, 0x033, 0x00000002,
- 0x03F, 0x00000745, 0x033, 0x00000003, 0x03F, 0x00000745,
- 0xA0000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000F34,
- 0x033, 0x00000001, 0x03F, 0x00000F34, 0x033, 0x00000002,
- 0x03F, 0x00000F34, 0x033, 0x00000003, 0x03F, 0x00000F34,
- 0xB0000000, 0x00000000, 0x0EF, 0x00000000, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
- 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
- 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
- 0x058, 0x00082030, 0x9300100f, 0x05050505, 0x40000000, 0x00000000,
- 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
- 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
- 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
- 0x9300100f, 0x00000000, 0x40000000, 0x00000000, 0x081, 0x0000F400,
- 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
- 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
- 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
- 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
- 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
- 0x058, 0x00082030, 0x9000100f, 0x0a0a0a0a, 0x40000000, 0x00000000,
- 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
- 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
- 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
- 0x9000100f, 0x05050505, 0x40000000, 0x00000000, 0x081, 0x0000F400,
- 0x087, 0x00016040, 0x051, 0x00000808, 0x052, 0x00098002,
- 0x053, 0x0000FA47, 0x054, 0x00058032, 0x056, 0x00051000,
- 0x057, 0x0000CE0A, 0x058, 0x00082030, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x081, 0x0000F400, 0x087, 0x00016040,
- 0x051, 0x00000808, 0x052, 0x00098002, 0x053, 0x0000FA47,
- 0x054, 0x00058032, 0x056, 0x00051000, 0x057, 0x0000CE0A,
- 0x058, 0x00082030, 0x9000200f, 0x00000000, 0x40000000, 0x00000000,
- 0x081, 0x0000F400, 0x087, 0x00016040, 0x051, 0x00000808,
- 0x052, 0x00098002, 0x053, 0x0000FA47, 0x054, 0x00058032,
- 0x056, 0x00051000, 0x057, 0x0000CE0A, 0x058, 0x00082030,
- 0xA0000000, 0x00000000, 0x081, 0x0000F000, 0x087, 0x00016040,
- 0x051, 0x00000C00, 0x052, 0x0007C241, 0x053, 0x0001C069,
- 0x054, 0x00078032, 0x057, 0x0000CE0A, 0x058, 0x00058750,
- 0xB0000000, 0x00000000, 0x0EF, 0x00000800, 0x8300100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
- 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
- 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
- 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
- 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
- 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
- 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
- 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9300100f, 0x05050505,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
- 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
- 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
- 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
- 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
- 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
- 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
- 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9300100f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
- 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
- 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
- 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
- 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
- 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
- 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
- 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9300200f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
- 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
- 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
- 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
- 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
- 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
- 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
- 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9000100f, 0x0a0a0a0a,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
- 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
- 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
- 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
- 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
- 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
- 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
- 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9000100f, 0x05050505,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
- 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
- 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
- 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
- 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
- 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
- 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
- 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9000100f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
- 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
- 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
- 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
- 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
- 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
- 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
- 0x033, 0x0000000A, 0x03F, 0x0000003C, 0x9000200f, 0x00000000,
- 0x40000000, 0x00000000, 0x033, 0x00000000, 0x03F, 0x00000003,
- 0x033, 0x00000001, 0x03F, 0x00000006, 0x033, 0x00000002,
- 0x03F, 0x00000009, 0x033, 0x00000003, 0x03F, 0x00000026,
- 0x033, 0x00000004, 0x03F, 0x00000029, 0x033, 0x00000005,
- 0x03F, 0x0000002C, 0x033, 0x00000006, 0x03F, 0x0000002F,
- 0x033, 0x00000007, 0x03F, 0x00000033, 0x033, 0x00000008,
- 0x03F, 0x00000036, 0x033, 0x00000009, 0x03F, 0x00000039,
- 0x033, 0x0000000A, 0x03F, 0x0000003C, 0xA0000000, 0x00000000,
- 0x033, 0x00000000, 0x03F, 0x0005142C, 0x033, 0x00000001,
- 0x03F, 0x0005142F, 0x033, 0x00000002, 0x03F, 0x00051432,
- 0x033, 0x00000003, 0x03F, 0x00051C87, 0x033, 0x00000004,
- 0x03F, 0x00051C8A, 0x033, 0x00000005, 0x03F, 0x00051C8D,
- 0x033, 0x00000006, 0x03F, 0x00051CEB, 0x033, 0x00000007,
- 0x03F, 0x00051CEE, 0x033, 0x00000008, 0x03F, 0x00051CF1,
- 0x033, 0x00000009, 0x03F, 0x00051CF4, 0x033, 0x0000000A,
- 0x03F, 0x00051CF7, 0xB0000000, 0x00000000, 0x0EF, 0x00000000,
- 0x0EF, 0x00000010, 0x033, 0x00000000, 0x008, 0x0009C060,
- 0x033, 0x00000001, 0x008, 0x0009C060, 0x0EF, 0x00000000,
- 0x033, 0x000000A2, 0x0EF, 0x00080000, 0x03E, 0x0000593F,
- 0x03F, 0x000C0F4F, 0x0EF, 0x00000000, 0x033, 0x000000A3,
- 0x0EF, 0x00080000, 0x03E, 0x00005934, 0x03F, 0x0005AFCF,
- 0x0EF, 0x00000000,
-
-};
-
-void odm_read_and_config_mp_8822b_radiob(struct phy_dm_struct *dm)
-{
- u32 i = 0;
- u8 c_cond;
- bool is_matched = true, is_skipped = false;
- u32 *array = array_mp_8822b_radiob;
-
- u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===> %s\n", __func__);
-
- for (; (i + 1) < ARRAY_SIZE(array_mp_8822b_radiob); i = i + 2) {
- v1 = array[i];
- v2 = array[i + 1];
-
- if (v1 & BIT(31)) { /* positive condition*/
- c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
- if (c_cond == COND_ENDIF) { /*end*/
- is_matched = true;
- is_skipped = false;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ENDIF\n");
- } else if (c_cond == COND_ELSE) { /*else*/
- is_matched = is_skipped ? false : true;
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "ELSE\n");
- } else { /*if , else if*/
- pre_v1 = v1;
- pre_v2 = v2;
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "IF or ELSE IF\n");
- }
- } else if (v1 & BIT(30)) { /*negative condition*/
- if (is_skipped) {
- is_matched = false;
- continue;
- }
-
- if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
- is_matched = true;
- is_skipped = true;
- } else {
- is_matched = false;
- is_skipped = false;
- }
- } else if (is_matched) {
- odm_config_rf_radio_b_8822b(dm, v1, v2);
- }
- }
-}
-
-u32 odm_get_version_mp_8822b_radiob(void) { return 67; }
-
-/******************************************************************************
- * txpowertrack.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_8822b[][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10,
- 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8,
- 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
- {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9,
- 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_8822b[][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11,
- 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19},
- {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10,
- 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10,
- 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_8822b[][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10,
- 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9,
- 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
- {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9,
- 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_8822b[][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20},
- {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9,
- 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18},
- {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10,
- 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-void odm_read_and_config_mp_8822b_txpowertrack(struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpowertrack_type0.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type0_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8,
- 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type0_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type0_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type0_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type0_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type0_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type0_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type0_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type0_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type0_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type0_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type0_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-void odm_read_and_config_mp_8822b_txpowertrack_type0(struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_type0_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpowertrack_type1.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type1_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10,
- 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8,
- 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
- {0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9,
- 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type1_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11,
- 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19},
- {0, 1, 2, 2, 3, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10,
- 11, 12, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10,
- 10, 11, 12, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type1_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 9, 10,
- 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9,
- 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
- {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9,
- 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type1_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 20, 20},
- {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9,
- 10, 11, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 18, 18},
- {0, 1, 2, 3, 3, 4, 5, 5, 6, 6, 7, 8, 8, 9, 10,
- 11, 12, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 18, 18, 18},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type1_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type1_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type1_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type1_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type1_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type1_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type1_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type1_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-void odm_read_and_config_mp_8822b_txpowertrack_type1(struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_type1_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpowertrack_type2.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type2_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type2_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type2_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type2_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type2_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type2_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type2_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type2_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type2_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type2_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type2_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type2_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-void odm_read_and_config_mp_8822b_txpowertrack_type2(struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_type2_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpowertrack_type3_type5.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type3_type5_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type3_type5_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type3_type5_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type3_type5_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type3_type5_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type3_type5_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type3_type5_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type3_type5_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type3_type5_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type3_type5_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type3_type5_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type3_type5_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-void odm_read_and_config_mp_8822b_txpowertrack_type3_type5(
- struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(
- dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(
- dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(
- dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(
- dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_type3_type5_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpowertrack_type4.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type4_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type4_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type4_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 11,
- 11, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type4_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 13, 14, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type4_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type4_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type4_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type4_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type4_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type4_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type4_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type4_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-void odm_read_and_config_mp_8822b_txpowertrack_type4(struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_type4_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpowertrack_type6.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type6_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10,
- 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
- {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10,
- 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16},
- {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12,
- 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type6_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11,
- 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19},
- {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21},
- {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12,
- 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type6_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11,
- 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10,
- 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15},
- {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10,
- 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type6_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12,
- 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21},
- {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11,
- 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21},
- {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type6_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type6_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type6_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type6_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type6_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type6_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type6_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type6_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-void odm_read_and_config_mp_8822b_txpowertrack_type6(struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_type6_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpowertrack_type7.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type7_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10,
- 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 15, 15, 15},
- {0, 1, 2, 3, 4, 5, 5, 6, 7, 7, 8, 9, 9, 10, 10,
- 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16},
- {0, 1, 2, 3, 4, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12,
- 12, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type7_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 11,
- 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 19, 19, 19, 19},
- {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 9, 11, 11, 12,
- 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21, 21},
- {0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12,
- 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 20, 20, 21, 21, 21},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type7_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11,
- 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 17, 17},
- {0, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10,
- 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15},
- {0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10,
- 11, 12, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type7_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12,
- 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 21, 21, 21, 21},
- {0, 1, 2, 2, 3, 4, 4, 5, 7, 7, 8, 9, 10, 11, 11,
- 12, 13, 13, 14, 15, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21},
- {0, 1, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 20, 20, 20, 20},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type7_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type7_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type7_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type7_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type7_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type7_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type7_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type7_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-void odm_read_and_config_mp_8822b_txpowertrack_type7(struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_type7_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpowertrack_type8.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type8_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type8_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type8_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type8_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8,
- 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 16, 17},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type8_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type8_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type8_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type8_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type8_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type8_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type8_8822b[] = {
- 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6,
- 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type8_8822b[] = {
- 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15};
-
-void odm_read_and_config_mp_8822b_txpowertrack_type8(struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_type8_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpowertrack_type9.TXT
- ******************************************************************************/
-
-static u8 delta_swing_index_mp_5gb_n_txpwrtrack_type9_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8,
- 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14},
- {0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 8,
- 9, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 15, 15},
-};
-
-static u8 delta_swing_index_mp_5gb_p_txpwrtrack_type9_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16},
-};
-
-static u8 delta_swing_index_mp_5ga_n_txpwrtrack_type9_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14},
-};
-
-static u8 delta_swing_index_mp_5ga_p_txpwrtrack_type9_8822b
- [][DELTA_SWINGIDX_SIZE] = {
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 12, 13, 13, 14, 14, 15, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 8, 9, 9, 10, 10, 11, 12, 12, 13, 13, 14, 14, 15, 15},
- {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
- 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15},
-};
-
-static u8 delta_swing_index_mp_2gb_n_txpwrtrack_type9_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2gb_p_txpwrtrack_type9_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 17, 18, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2ga_n_txpwrtrack_type9_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2ga_p_txpwrtrack_type9_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type9_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17, 17};
-
-static u8 delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type9_8822b[] = {
- 0, 1, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-static u8 delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type9_8822b[] = {
- 0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12,
- 13, 13, 14, 15, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18};
-
-static u8 delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type9_8822b[] = {
- 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11,
- 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 22, 22};
-
-void odm_read_and_config_mp_8822b_txpowertrack_type9(struct phy_dm_struct *dm)
-{
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8822b\n");
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p,
- delta_swing_index_mp_2ga_p_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n,
- delta_swing_index_mp_2ga_n_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p,
- delta_swing_index_mp_2gb_p_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n,
- delta_swing_index_mp_2gb_n_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p,
- delta_swing_index_mp_2g_cck_a_p_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n,
- delta_swing_index_mp_2g_cck_a_n_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p,
- delta_swing_index_mp_2g_cck_b_p_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n,
- delta_swing_index_mp_2g_cck_b_n_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE);
-
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p,
- delta_swing_index_mp_5ga_p_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n,
- delta_swing_index_mp_5ga_n_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p,
- delta_swing_index_mp_5gb_p_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE * 3);
- odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n,
- delta_swing_index_mp_5gb_n_txpwrtrack_type9_8822b,
- DELTA_SWINGIDX_SIZE * 3);
-}
-
-/******************************************************************************
- * txpwr_lmt.TXT
- ******************************************************************************/
-
-static const char *const array_mp_8822b_txpwr_lmt[] = {
- "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", "ETSI", "2.4G",
- "20M", "CCK", "1T", "01", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "01", "30", "FCC", "2.4G", "20M", "CCK", "1T", "02",
- "32", "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", "MKK",
- "2.4G", "20M", "CCK", "1T", "02", "30", "FCC", "2.4G", "20M",
- "CCK", "1T", "03", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
- "03", "28", "MKK", "2.4G", "20M", "CCK", "1T", "03", "30",
- "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", "ETSI", "2.4G",
- "20M", "CCK", "1T", "04", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "04", "30", "FCC", "2.4G", "20M", "CCK", "1T", "05",
- "32", "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", "MKK",
- "2.4G", "20M", "CCK", "1T", "05", "30", "FCC", "2.4G", "20M",
- "CCK", "1T", "06", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
- "06", "28", "MKK", "2.4G", "20M", "CCK", "1T", "06", "30",
- "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", "ETSI", "2.4G",
- "20M", "CCK", "1T", "07", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "07", "30", "FCC", "2.4G", "20M", "CCK", "1T", "08",
- "32", "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", "MKK",
- "2.4G", "20M", "CCK", "1T", "08", "30", "FCC", "2.4G", "20M",
- "CCK", "1T", "09", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
- "09", "28", "MKK", "2.4G", "20M", "CCK", "1T", "09", "30",
- "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", "ETSI", "2.4G",
- "20M", "CCK", "1T", "10", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "10", "30", "FCC", "2.4G", "20M", "CCK", "1T", "11",
- "32", "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", "MKK",
- "2.4G", "20M", "CCK", "1T", "11", "30", "FCC", "2.4G", "20M",
- "CCK", "1T", "12", "26", "ETSI", "2.4G", "20M", "CCK", "1T",
- "12", "28", "MKK", "2.4G", "20M", "CCK", "1T", "12", "30",
- "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", "ETSI", "2.4G",
- "20M", "CCK", "1T", "13", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "13", "28", "FCC", "2.4G", "20M", "CCK", "1T", "14",
- "63", "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", "MKK",
- "2.4G", "20M", "CCK", "1T", "14", "32", "FCC", "2.4G", "20M",
- "OFDM", "1T", "01", "26", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "01", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "02", "30", "MKK", "2.4G", "20M", "OFDM",
- "1T", "02", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "03",
- "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", "MKK",
- "2.4G", "20M", "OFDM", "1T", "03", "34", "FCC", "2.4G", "20M",
- "OFDM", "1T", "04", "34", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "04", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "05", "30", "MKK", "2.4G", "20M", "OFDM",
- "1T", "05", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "06",
- "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", "MKK",
- "2.4G", "20M", "OFDM", "1T", "06", "34", "FCC", "2.4G", "20M",
- "OFDM", "1T", "07", "34", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "07", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "08", "30", "MKK", "2.4G", "20M", "OFDM",
- "1T", "08", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "09",
- "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", "MKK",
- "2.4G", "20M", "OFDM", "1T", "09", "34", "FCC", "2.4G", "20M",
- "OFDM", "1T", "10", "30", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "10", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "11", "30", "MKK", "2.4G", "20M", "OFDM",
- "1T", "11", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "12",
- "22", "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", "MKK",
- "2.4G", "20M", "OFDM", "1T", "12", "34", "FCC", "2.4G", "20M",
- "OFDM", "1T", "13", "14", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "13", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "14", "63", "MKK", "2.4G", "20M", "OFDM",
- "1T", "14", "63", "FCC", "2.4G", "20M", "HT", "1T", "01",
- "26", "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "01", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "02", "30", "ETSI", "2.4G", "20M", "HT", "1T",
- "02", "30", "MKK", "2.4G", "20M", "HT", "1T", "02", "34",
- "FCC", "2.4G", "20M", "HT", "1T", "03", "32", "ETSI", "2.4G",
- "20M", "HT", "1T", "03", "30", "MKK", "2.4G", "20M", "HT",
- "1T", "03", "34", "FCC", "2.4G", "20M", "HT", "1T", "04",
- "34", "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "04", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "05", "34", "ETSI", "2.4G", "20M", "HT", "1T",
- "05", "30", "MKK", "2.4G", "20M", "HT", "1T", "05", "34",
- "FCC", "2.4G", "20M", "HT", "1T", "06", "34", "ETSI", "2.4G",
- "20M", "HT", "1T", "06", "30", "MKK", "2.4G", "20M", "HT",
- "1T", "06", "34", "FCC", "2.4G", "20M", "HT", "1T", "07",
- "34", "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "07", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "08", "34", "ETSI", "2.4G", "20M", "HT", "1T",
- "08", "30", "MKK", "2.4G", "20M", "HT", "1T", "08", "34",
- "FCC", "2.4G", "20M", "HT", "1T", "09", "32", "ETSI", "2.4G",
- "20M", "HT", "1T", "09", "30", "MKK", "2.4G", "20M", "HT",
- "1T", "09", "34", "FCC", "2.4G", "20M", "HT", "1T", "10",
- "30", "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "10", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "11", "26", "ETSI", "2.4G", "20M", "HT", "1T",
- "11", "30", "MKK", "2.4G", "20M", "HT", "1T", "11", "34",
- "FCC", "2.4G", "20M", "HT", "1T", "12", "20", "ETSI", "2.4G",
- "20M", "HT", "1T", "12", "30", "MKK", "2.4G", "20M", "HT",
- "1T", "12", "34", "FCC", "2.4G", "20M", "HT", "1T", "13",
- "14", "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "13", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "14", "63", "ETSI", "2.4G", "20M", "HT", "1T",
- "14", "63", "MKK", "2.4G", "20M", "HT", "1T", "14", "63",
- "FCC", "2.4G", "20M", "HT", "2T", "01", "26", "ETSI", "2.4G",
- "20M", "HT", "2T", "01", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "01", "30", "FCC", "2.4G", "20M", "HT", "2T", "02",
- "28", "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", "MKK",
- "2.4G", "20M", "HT", "2T", "02", "30", "FCC", "2.4G", "20M",
- "HT", "2T", "03", "30", "ETSI", "2.4G", "20M", "HT", "2T",
- "03", "18", "MKK", "2.4G", "20M", "HT", "2T", "03", "30",
- "FCC", "2.4G", "20M", "HT", "2T", "04", "30", "ETSI", "2.4G",
- "20M", "HT", "2T", "04", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "04", "30", "FCC", "2.4G", "20M", "HT", "2T", "05",
- "32", "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", "MKK",
- "2.4G", "20M", "HT", "2T", "05", "30", "FCC", "2.4G", "20M",
- "HT", "2T", "06", "32", "ETSI", "2.4G", "20M", "HT", "2T",
- "06", "18", "MKK", "2.4G", "20M", "HT", "2T", "06", "30",
- "FCC", "2.4G", "20M", "HT", "2T", "07", "32", "ETSI", "2.4G",
- "20M", "HT", "2T", "07", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "07", "30", "FCC", "2.4G", "20M", "HT", "2T", "08",
- "30", "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", "MKK",
- "2.4G", "20M", "HT", "2T", "08", "30", "FCC", "2.4G", "20M",
- "HT", "2T", "09", "30", "ETSI", "2.4G", "20M", "HT", "2T",
- "09", "18", "MKK", "2.4G", "20M", "HT", "2T", "09", "30",
- "FCC", "2.4G", "20M", "HT", "2T", "10", "28", "ETSI", "2.4G",
- "20M", "HT", "2T", "10", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "10", "30", "FCC", "2.4G", "20M", "HT", "2T", "11",
- "26", "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", "MKK",
- "2.4G", "20M", "HT", "2T", "11", "30", "FCC", "2.4G", "20M",
- "HT", "2T", "12", "20", "ETSI", "2.4G", "20M", "HT", "2T",
- "12", "18", "MKK", "2.4G", "20M", "HT", "2T", "12", "30",
- "FCC", "2.4G", "20M", "HT", "2T", "13", "14", "ETSI", "2.4G",
- "20M", "HT", "2T", "13", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "13", "30", "FCC", "2.4G", "20M", "HT", "2T", "14",
- "63", "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", "MKK",
- "2.4G", "20M", "HT", "2T", "14", "63", "FCC", "2.4G", "40M",
- "HT", "1T", "01", "63", "ETSI", "2.4G", "40M", "HT", "1T",
- "01", "63", "MKK", "2.4G", "40M", "HT", "1T", "01", "63",
- "FCC", "2.4G", "40M", "HT", "1T", "02", "63", "ETSI", "2.4G",
- "40M", "HT", "1T", "02", "63", "MKK", "2.4G", "40M", "HT",
- "1T", "02", "63", "FCC", "2.4G", "40M", "HT", "1T", "03",
- "26", "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", "MKK",
- "2.4G", "40M", "HT", "1T", "03", "34", "FCC", "2.4G", "40M",
- "HT", "1T", "04", "26", "ETSI", "2.4G", "40M", "HT", "1T",
- "04", "30", "MKK", "2.4G", "40M", "HT", "1T", "04", "34",
- "FCC", "2.4G", "40M", "HT", "1T", "05", "30", "ETSI", "2.4G",
- "40M", "HT", "1T", "05", "30", "MKK", "2.4G", "40M", "HT",
- "1T", "05", "34", "FCC", "2.4G", "40M", "HT", "1T", "06",
- "32", "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", "MKK",
- "2.4G", "40M", "HT", "1T", "06", "34", "FCC", "2.4G", "40M",
- "HT", "1T", "07", "30", "ETSI", "2.4G", "40M", "HT", "1T",
- "07", "30", "MKK", "2.4G", "40M", "HT", "1T", "07", "34",
- "FCC", "2.4G", "40M", "HT", "1T", "08", "26", "ETSI", "2.4G",
- "40M", "HT", "1T", "08", "30", "MKK", "2.4G", "40M", "HT",
- "1T", "08", "34", "FCC", "2.4G", "40M", "HT", "1T", "09",
- "26", "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", "MKK",
- "2.4G", "40M", "HT", "1T", "09", "34", "FCC", "2.4G", "40M",
- "HT", "1T", "10", "20", "ETSI", "2.4G", "40M", "HT", "1T",
- "10", "30", "MKK", "2.4G", "40M", "HT", "1T", "10", "34",
- "FCC", "2.4G", "40M", "HT", "1T", "11", "14", "ETSI", "2.4G",
- "40M", "HT", "1T", "11", "30", "MKK", "2.4G", "40M", "HT",
- "1T", "11", "34", "FCC", "2.4G", "40M", "HT", "1T", "12",
- "63", "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", "MKK",
- "2.4G", "40M", "HT", "1T", "12", "63", "FCC", "2.4G", "40M",
- "HT", "1T", "13", "63", "ETSI", "2.4G", "40M", "HT", "1T",
- "13", "63", "MKK", "2.4G", "40M", "HT", "1T", "13", "63",
- "FCC", "2.4G", "40M", "HT", "1T", "14", "63", "ETSI", "2.4G",
- "40M", "HT", "1T", "14", "63", "MKK", "2.4G", "40M", "HT",
- "1T", "14", "63", "FCC", "2.4G", "40M", "HT", "2T", "01",
- "63", "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", "MKK",
- "2.4G", "40M", "HT", "2T", "01", "63", "FCC", "2.4G", "40M",
- "HT", "2T", "02", "63", "ETSI", "2.4G", "40M", "HT", "2T",
- "02", "63", "MKK", "2.4G", "40M", "HT", "2T", "02", "63",
- "FCC", "2.4G", "40M", "HT", "2T", "03", "24", "ETSI", "2.4G",
- "40M", "HT", "2T", "03", "18", "MKK", "2.4G", "40M", "HT",
- "2T", "03", "30", "FCC", "2.4G", "40M", "HT", "2T", "04",
- "24", "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", "MKK",
- "2.4G", "40M", "HT", "2T", "04", "30", "FCC", "2.4G", "40M",
- "HT", "2T", "05", "26", "ETSI", "2.4G", "40M", "HT", "2T",
- "05", "18", "MKK", "2.4G", "40M", "HT", "2T", "05", "30",
- "FCC", "2.4G", "40M", "HT", "2T", "06", "28", "ETSI", "2.4G",
- "40M", "HT", "2T", "06", "18", "MKK", "2.4G", "40M", "HT",
- "2T", "06", "30", "FCC", "2.4G", "40M", "HT", "2T", "07",
- "26", "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", "MKK",
- "2.4G", "40M", "HT", "2T", "07", "30", "FCC", "2.4G", "40M",
- "HT", "2T", "08", "26", "ETSI", "2.4G", "40M", "HT", "2T",
- "08", "18", "MKK", "2.4G", "40M", "HT", "2T", "08", "30",
- "FCC", "2.4G", "40M", "HT", "2T", "09", "26", "ETSI", "2.4G",
- "40M", "HT", "2T", "09", "18", "MKK", "2.4G", "40M", "HT",
- "2T", "09", "30", "FCC", "2.4G", "40M", "HT", "2T", "10",
- "20", "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", "MKK",
- "2.4G", "40M", "HT", "2T", "10", "30", "FCC", "2.4G", "40M",
- "HT", "2T", "11", "14", "ETSI", "2.4G", "40M", "HT", "2T",
- "11", "18", "MKK", "2.4G", "40M", "HT", "2T", "11", "30",
- "FCC", "2.4G", "40M", "HT", "2T", "12", "63", "ETSI", "2.4G",
- "40M", "HT", "2T", "12", "63", "MKK", "2.4G", "40M", "HT",
- "2T", "12", "63", "FCC", "2.4G", "40M", "HT", "2T", "13",
- "63", "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", "MKK",
- "2.4G", "40M", "HT", "2T", "13", "63", "FCC", "2.4G", "40M",
- "HT", "2T", "14", "63", "ETSI", "2.4G", "40M", "HT", "2T",
- "14", "63", "MKK", "2.4G", "40M", "HT", "2T", "14", "63",
- "FCC", "5G", "20M", "OFDM", "1T", "36", "30", "ETSI", "5G",
- "20M", "OFDM", "1T", "36", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "36", "30", "FCC", "5G", "20M", "OFDM", "1T", "40",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "40", "30", "FCC", "5G", "20M",
- "OFDM", "1T", "44", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "44", "32", "MKK", "5G", "20M", "OFDM", "1T", "44", "30",
- "FCC", "5G", "20M", "OFDM", "1T", "48", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "48", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "48", "30", "FCC", "5G", "20M", "OFDM", "1T", "52",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "52", "28", "FCC", "5G", "20M",
- "OFDM", "1T", "56", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "56", "32", "MKK", "5G", "20M", "OFDM", "1T", "56", "28",
- "FCC", "5G", "20M", "OFDM", "1T", "60", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "60", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "60", "28", "FCC", "5G", "20M", "OFDM", "1T", "64",
- "28", "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "64", "28", "FCC", "5G", "20M",
- "OFDM", "1T", "100", "26", "ETSI", "5G", "20M", "OFDM", "1T",
- "100", "32", "MKK", "5G", "20M", "OFDM", "1T", "100", "32",
- "FCC", "5G", "20M", "OFDM", "1T", "104", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "104", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "104", "32", "FCC", "5G", "20M", "OFDM", "1T", "108",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "108", "32", "FCC", "5G", "20M",
- "OFDM", "1T", "112", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "112", "32", "MKK", "5G", "20M", "OFDM", "1T", "112", "32",
- "FCC", "5G", "20M", "OFDM", "1T", "116", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "116", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "116", "32", "FCC", "5G", "20M", "OFDM", "1T", "120",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "120", "32", "FCC", "5G", "20M",
- "OFDM", "1T", "124", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "124", "32", "MKK", "5G", "20M", "OFDM", "1T", "124", "32",
- "FCC", "5G", "20M", "OFDM", "1T", "128", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "128", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "128", "32", "FCC", "5G", "20M", "OFDM", "1T", "132",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "132", "32", "FCC", "5G", "20M",
- "OFDM", "1T", "136", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "136", "32", "MKK", "5G", "20M", "OFDM", "1T", "136", "32",
- "FCC", "5G", "20M", "OFDM", "1T", "140", "28", "ETSI", "5G",
- "20M", "OFDM", "1T", "140", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "140", "32", "FCC", "5G", "20M", "OFDM", "1T", "144",
- "28", "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "144", "63", "FCC", "5G", "20M",
- "OFDM", "1T", "149", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "149", "63", "MKK", "5G", "20M", "OFDM", "1T", "149", "63",
- "FCC", "5G", "20M", "OFDM", "1T", "153", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "153", "63", "MKK", "5G", "20M", "OFDM",
- "1T", "153", "63", "FCC", "5G", "20M", "OFDM", "1T", "157",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", "MKK",
- "5G", "20M", "OFDM", "1T", "157", "63", "FCC", "5G", "20M",
- "OFDM", "1T", "161", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "161", "63", "MKK", "5G", "20M", "OFDM", "1T", "161", "63",
- "FCC", "5G", "20M", "OFDM", "1T", "165", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "165", "63", "MKK", "5G", "20M", "OFDM",
- "1T", "165", "63", "FCC", "5G", "20M", "HT", "1T", "36",
- "30", "ETSI", "5G", "20M", "HT", "1T", "36", "32", "MKK",
- "5G", "20M", "HT", "1T", "36", "28", "FCC", "5G", "20M",
- "HT", "1T", "40", "32", "ETSI", "5G", "20M", "HT", "1T",
- "40", "32", "MKK", "5G", "20M", "HT", "1T", "40", "28",
- "FCC", "5G", "20M", "HT", "1T", "44", "32", "ETSI", "5G",
- "20M", "HT", "1T", "44", "32", "MKK", "5G", "20M", "HT",
- "1T", "44", "28", "FCC", "5G", "20M", "HT", "1T", "48",
- "32", "ETSI", "5G", "20M", "HT", "1T", "48", "32", "MKK",
- "5G", "20M", "HT", "1T", "48", "28", "FCC", "5G", "20M",
- "HT", "1T", "52", "32", "ETSI", "5G", "20M", "HT", "1T",
- "52", "32", "MKK", "5G", "20M", "HT", "1T", "52", "28",
- "FCC", "5G", "20M", "HT", "1T", "56", "32", "ETSI", "5G",
- "20M", "HT", "1T", "56", "32", "MKK", "5G", "20M", "HT",
- "1T", "56", "28", "FCC", "5G", "20M", "HT", "1T", "60",
- "32", "ETSI", "5G", "20M", "HT", "1T", "60", "32", "MKK",
- "5G", "20M", "HT", "1T", "60", "28", "FCC", "5G", "20M",
- "HT", "1T", "64", "28", "ETSI", "5G", "20M", "HT", "1T",
- "64", "32", "MKK", "5G", "20M", "HT", "1T", "64", "28",
- "FCC", "5G", "20M", "HT", "1T", "100", "26", "ETSI", "5G",
- "20M", "HT", "1T", "100", "32", "MKK", "5G", "20M", "HT",
- "1T", "100", "32", "FCC", "5G", "20M", "HT", "1T", "104",
- "32", "ETSI", "5G", "20M", "HT", "1T", "104", "32", "MKK",
- "5G", "20M", "HT", "1T", "104", "32", "FCC", "5G", "20M",
- "HT", "1T", "108", "32", "ETSI", "5G", "20M", "HT", "1T",
- "108", "32", "MKK", "5G", "20M", "HT", "1T", "108", "32",
- "FCC", "5G", "20M", "HT", "1T", "112", "32", "ETSI", "5G",
- "20M", "HT", "1T", "112", "32", "MKK", "5G", "20M", "HT",
- "1T", "112", "32", "FCC", "5G", "20M", "HT", "1T", "116",
- "32", "ETSI", "5G", "20M", "HT", "1T", "116", "32", "MKK",
- "5G", "20M", "HT", "1T", "116", "32", "FCC", "5G", "20M",
- "HT", "1T", "120", "32", "ETSI", "5G", "20M", "HT", "1T",
- "120", "32", "MKK", "5G", "20M", "HT", "1T", "120", "32",
- "FCC", "5G", "20M", "HT", "1T", "124", "32", "ETSI", "5G",
- "20M", "HT", "1T", "124", "32", "MKK", "5G", "20M", "HT",
- "1T", "124", "32", "FCC", "5G", "20M", "HT", "1T", "128",
- "32", "ETSI", "5G", "20M", "HT", "1T", "128", "32", "MKK",
- "5G", "20M", "HT", "1T", "128", "32", "FCC", "5G", "20M",
- "HT", "1T", "132", "32", "ETSI", "5G", "20M", "HT", "1T",
- "132", "32", "MKK", "5G", "20M", "HT", "1T", "132", "32",
- "FCC", "5G", "20M", "HT", "1T", "136", "32", "ETSI", "5G",
- "20M", "HT", "1T", "136", "32", "MKK", "5G", "20M", "HT",
- "1T", "136", "32", "FCC", "5G", "20M", "HT", "1T", "140",
- "26", "ETSI", "5G", "20M", "HT", "1T", "140", "32", "MKK",
- "5G", "20M", "HT", "1T", "140", "32", "FCC", "5G", "20M",
- "HT", "1T", "144", "26", "ETSI", "5G", "20M", "HT", "1T",
- "144", "63", "MKK", "5G", "20M", "HT", "1T", "144", "63",
- "FCC", "5G", "20M", "HT", "1T", "149", "32", "ETSI", "5G",
- "20M", "HT", "1T", "149", "63", "MKK", "5G", "20M", "HT",
- "1T", "149", "63", "FCC", "5G", "20M", "HT", "1T", "153",
- "32", "ETSI", "5G", "20M", "HT", "1T", "153", "63", "MKK",
- "5G", "20M", "HT", "1T", "153", "63", "FCC", "5G", "20M",
- "HT", "1T", "157", "32", "ETSI", "5G", "20M", "HT", "1T",
- "157", "63", "MKK", "5G", "20M", "HT", "1T", "157", "63",
- "FCC", "5G", "20M", "HT", "1T", "161", "32", "ETSI", "5G",
- "20M", "HT", "1T", "161", "63", "MKK", "5G", "20M", "HT",
- "1T", "161", "63", "FCC", "5G", "20M", "HT", "1T", "165",
- "32", "ETSI", "5G", "20M", "HT", "1T", "165", "63", "MKK",
- "5G", "20M", "HT", "1T", "165", "63", "FCC", "5G", "20M",
- "HT", "2T", "36", "28", "ETSI", "5G", "20M", "HT", "2T",
- "36", "20", "MKK", "5G", "20M", "HT", "2T", "36", "22",
- "FCC", "5G", "20M", "HT", "2T", "40", "30", "ETSI", "5G",
- "20M", "HT", "2T", "40", "20", "MKK", "5G", "20M", "HT",
- "2T", "40", "22", "FCC", "5G", "20M", "HT", "2T", "44",
- "30", "ETSI", "5G", "20M", "HT", "2T", "44", "20", "MKK",
- "5G", "20M", "HT", "2T", "44", "22", "FCC", "5G", "20M",
- "HT", "2T", "48", "30", "ETSI", "5G", "20M", "HT", "2T",
- "48", "20", "MKK", "5G", "20M", "HT", "2T", "48", "22",
- "FCC", "5G", "20M", "HT", "2T", "52", "30", "ETSI", "5G",
- "20M", "HT", "2T", "52", "20", "MKK", "5G", "20M", "HT",
- "2T", "52", "22", "FCC", "5G", "20M", "HT", "2T", "56",
- "30", "ETSI", "5G", "20M", "HT", "2T", "56", "20", "MKK",
- "5G", "20M", "HT", "2T", "56", "22", "FCC", "5G", "20M",
- "HT", "2T", "60", "30", "ETSI", "5G", "20M", "HT", "2T",
- "60", "20", "MKK", "5G", "20M", "HT", "2T", "60", "22",
- "FCC", "5G", "20M", "HT", "2T", "64", "28", "ETSI", "5G",
- "20M", "HT", "2T", "64", "20", "MKK", "5G", "20M", "HT",
- "2T", "64", "22", "FCC", "5G", "20M", "HT", "2T", "100",
- "26", "ETSI", "5G", "20M", "HT", "2T", "100", "20", "MKK",
- "5G", "20M", "HT", "2T", "100", "30", "FCC", "5G", "20M",
- "HT", "2T", "104", "30", "ETSI", "5G", "20M", "HT", "2T",
- "104", "20", "MKK", "5G", "20M", "HT", "2T", "104", "30",
- "FCC", "5G", "20M", "HT", "2T", "108", "32", "ETSI", "5G",
- "20M", "HT", "2T", "108", "20", "MKK", "5G", "20M", "HT",
- "2T", "108", "30", "FCC", "5G", "20M", "HT", "2T", "112",
- "32", "ETSI", "5G", "20M", "HT", "2T", "112", "20", "MKK",
- "5G", "20M", "HT", "2T", "112", "30", "FCC", "5G", "20M",
- "HT", "2T", "116", "32", "ETSI", "5G", "20M", "HT", "2T",
- "116", "20", "MKK", "5G", "20M", "HT", "2T", "116", "30",
- "FCC", "5G", "20M", "HT", "2T", "120", "32", "ETSI", "5G",
- "20M", "HT", "2T", "120", "20", "MKK", "5G", "20M", "HT",
- "2T", "120", "30", "FCC", "5G", "20M", "HT", "2T", "124",
- "32", "ETSI", "5G", "20M", "HT", "2T", "124", "20", "MKK",
- "5G", "20M", "HT", "2T", "124", "30", "FCC", "5G", "20M",
- "HT", "2T", "128", "32", "ETSI", "5G", "20M", "HT", "2T",
- "128", "20", "MKK", "5G", "20M", "HT", "2T", "128", "30",
- "FCC", "5G", "20M", "HT", "2T", "132", "32", "ETSI", "5G",
- "20M", "HT", "2T", "132", "20", "MKK", "5G", "20M", "HT",
- "2T", "132", "30", "FCC", "5G", "20M", "HT", "2T", "136",
- "30", "ETSI", "5G", "20M", "HT", "2T", "136", "20", "MKK",
- "5G", "20M", "HT", "2T", "136", "30", "FCC", "5G", "20M",
- "HT", "2T", "140", "26", "ETSI", "5G", "20M", "HT", "2T",
- "140", "20", "MKK", "5G", "20M", "HT", "2T", "140", "30",
- "FCC", "5G", "20M", "HT", "2T", "144", "26", "ETSI", "5G",
- "20M", "HT", "2T", "144", "63", "MKK", "5G", "20M", "HT",
- "2T", "144", "63", "FCC", "5G", "20M", "HT", "2T", "149",
- "32", "ETSI", "5G", "20M", "HT", "2T", "149", "63", "MKK",
- "5G", "20M", "HT", "2T", "149", "63", "FCC", "5G", "20M",
- "HT", "2T", "153", "32", "ETSI", "5G", "20M", "HT", "2T",
- "153", "63", "MKK", "5G", "20M", "HT", "2T", "153", "63",
- "FCC", "5G", "20M", "HT", "2T", "157", "32", "ETSI", "5G",
- "20M", "HT", "2T", "157", "63", "MKK", "5G", "20M", "HT",
- "2T", "157", "63", "FCC", "5G", "20M", "HT", "2T", "161",
- "32", "ETSI", "5G", "20M", "HT", "2T", "161", "63", "MKK",
- "5G", "20M", "HT", "2T", "161", "63", "FCC", "5G", "20M",
- "HT", "2T", "165", "32", "ETSI", "5G", "20M", "HT", "2T",
- "165", "63", "MKK", "5G", "20M", "HT", "2T", "165", "63",
- "FCC", "5G", "40M", "HT", "1T", "38", "22", "ETSI", "5G",
- "40M", "HT", "1T", "38", "30", "MKK", "5G", "40M", "HT",
- "1T", "38", "30", "FCC", "5G", "40M", "HT", "1T", "46",
- "30", "ETSI", "5G", "40M", "HT", "1T", "46", "30", "MKK",
- "5G", "40M", "HT", "1T", "46", "30", "FCC", "5G", "40M",
- "HT", "1T", "54", "30", "ETSI", "5G", "40M", "HT", "1T",
- "54", "30", "MKK", "5G", "40M", "HT", "1T", "54", "30",
- "FCC", "5G", "40M", "HT", "1T", "62", "24", "ETSI", "5G",
- "40M", "HT", "1T", "62", "30", "MKK", "5G", "40M", "HT",
- "1T", "62", "30", "FCC", "5G", "40M", "HT", "1T", "102",
- "24", "ETSI", "5G", "40M", "HT", "1T", "102", "30", "MKK",
- "5G", "40M", "HT", "1T", "102", "30", "FCC", "5G", "40M",
- "HT", "1T", "110", "30", "ETSI", "5G", "40M", "HT", "1T",
- "110", "30", "MKK", "5G", "40M", "HT", "1T", "110", "30",
- "FCC", "5G", "40M", "HT", "1T", "118", "30", "ETSI", "5G",
- "40M", "HT", "1T", "118", "30", "MKK", "5G", "40M", "HT",
- "1T", "118", "30", "FCC", "5G", "40M", "HT", "1T", "126",
- "30", "ETSI", "5G", "40M", "HT", "1T", "126", "30", "MKK",
- "5G", "40M", "HT", "1T", "126", "30", "FCC", "5G", "40M",
- "HT", "1T", "134", "30", "ETSI", "5G", "40M", "HT", "1T",
- "134", "30", "MKK", "5G", "40M", "HT", "1T", "134", "30",
- "FCC", "5G", "40M", "HT", "1T", "142", "30", "ETSI", "5G",
- "40M", "HT", "1T", "142", "63", "MKK", "5G", "40M", "HT",
- "1T", "142", "63", "FCC", "5G", "40M", "HT", "1T", "151",
- "30", "ETSI", "5G", "40M", "HT", "1T", "151", "63", "MKK",
- "5G", "40M", "HT", "1T", "151", "63", "FCC", "5G", "40M",
- "HT", "1T", "159", "30", "ETSI", "5G", "40M", "HT", "1T",
- "159", "63", "MKK", "5G", "40M", "HT", "1T", "159", "63",
- "FCC", "5G", "40M", "HT", "2T", "38", "20", "ETSI", "5G",
- "40M", "HT", "2T", "38", "20", "MKK", "5G", "40M", "HT",
- "2T", "38", "22", "FCC", "5G", "40M", "HT", "2T", "46",
- "30", "ETSI", "5G", "40M", "HT", "2T", "46", "20", "MKK",
- "5G", "40M", "HT", "2T", "46", "22", "FCC", "5G", "40M",
- "HT", "2T", "54", "30", "ETSI", "5G", "40M", "HT", "2T",
- "54", "20", "MKK", "5G", "40M", "HT", "2T", "54", "22",
- "FCC", "5G", "40M", "HT", "2T", "62", "22", "ETSI", "5G",
- "40M", "HT", "2T", "62", "20", "MKK", "5G", "40M", "HT",
- "2T", "62", "22", "FCC", "5G", "40M", "HT", "2T", "102",
- "22", "ETSI", "5G", "40M", "HT", "2T", "102", "20", "MKK",
- "5G", "40M", "HT", "2T", "102", "30", "FCC", "5G", "40M",
- "HT", "2T", "110", "30", "ETSI", "5G", "40M", "HT", "2T",
- "110", "20", "MKK", "5G", "40M", "HT", "2T", "110", "30",
- "FCC", "5G", "40M", "HT", "2T", "118", "30", "ETSI", "5G",
- "40M", "HT", "2T", "118", "20", "MKK", "5G", "40M", "HT",
- "2T", "118", "30", "FCC", "5G", "40M", "HT", "2T", "126",
- "30", "ETSI", "5G", "40M", "HT", "2T", "126", "20", "MKK",
- "5G", "40M", "HT", "2T", "126", "30", "FCC", "5G", "40M",
- "HT", "2T", "134", "30", "ETSI", "5G", "40M", "HT", "2T",
- "134", "20", "MKK", "5G", "40M", "HT", "2T", "134", "30",
- "FCC", "5G", "40M", "HT", "2T", "142", "30", "ETSI", "5G",
- "40M", "HT", "2T", "142", "63", "MKK", "5G", "40M", "HT",
- "2T", "142", "63", "FCC", "5G", "40M", "HT", "2T", "151",
- "30", "ETSI", "5G", "40M", "HT", "2T", "151", "63", "MKK",
- "5G", "40M", "HT", "2T", "151", "63", "FCC", "5G", "40M",
- "HT", "2T", "159", "30", "ETSI", "5G", "40M", "HT", "2T",
- "159", "63", "MKK", "5G", "40M", "HT", "2T", "159", "63",
- "FCC", "5G", "80M", "VHT", "1T", "42", "20", "ETSI", "5G",
- "80M", "VHT", "1T", "42", "30", "MKK", "5G", "80M", "VHT",
- "1T", "42", "28", "FCC", "5G", "80M", "VHT", "1T", "58",
- "20", "ETSI", "5G", "80M", "VHT", "1T", "58", "30", "MKK",
- "5G", "80M", "VHT", "1T", "58", "28", "FCC", "5G", "80M",
- "VHT", "1T", "106", "20", "ETSI", "5G", "80M", "VHT", "1T",
- "106", "30", "MKK", "5G", "80M", "VHT", "1T", "106", "30",
- "FCC", "5G", "80M", "VHT", "1T", "122", "30", "ETSI", "5G",
- "80M", "VHT", "1T", "122", "30", "MKK", "5G", "80M", "VHT",
- "1T", "122", "30", "FCC", "5G", "80M", "VHT", "1T", "138",
- "30", "ETSI", "5G", "80M", "VHT", "1T", "138", "63", "MKK",
- "5G", "80M", "VHT", "1T", "138", "63", "FCC", "5G", "80M",
- "VHT", "1T", "155", "30", "ETSI", "5G", "80M", "VHT", "1T",
- "155", "63", "MKK", "5G", "80M", "VHT", "1T", "155", "63",
- "FCC", "5G", "80M", "VHT", "2T", "42", "18", "ETSI", "5G",
- "80M", "VHT", "2T", "42", "20", "MKK", "5G", "80M", "VHT",
- "2T", "42", "22", "FCC", "5G", "80M", "VHT", "2T", "58",
- "18", "ETSI", "5G", "80M", "VHT", "2T", "58", "20", "MKK",
- "5G", "80M", "VHT", "2T", "58", "22", "FCC", "5G", "80M",
- "VHT", "2T", "106", "20", "ETSI", "5G", "80M", "VHT", "2T",
- "106", "20", "MKK", "5G", "80M", "VHT", "2T", "106", "30",
- "FCC", "5G", "80M", "VHT", "2T", "122", "30", "ETSI", "5G",
- "80M", "VHT", "2T", "122", "20", "MKK", "5G", "80M", "VHT",
- "2T", "122", "30", "FCC", "5G", "80M", "VHT", "2T", "138",
- "30", "ETSI", "5G", "80M", "VHT", "2T", "138", "63", "MKK",
- "5G", "80M", "VHT", "2T", "138", "63", "FCC", "5G", "80M",
- "VHT", "2T", "155", "30", "ETSI", "5G", "80M", "VHT", "2T",
- "155", "63", "MKK", "5G", "80M", "VHT", "2T", "155", "63"};
-
-void odm_read_and_config_mp_8822b_txpwr_lmt(struct phy_dm_struct *dm)
-{
- u32 i = 0;
- u8 **array = (u8 **)array_mp_8822b_txpwr_lmt;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===> %s\n", __func__);
-
- for (i = 0; i < ARRAY_SIZE(array_mp_8822b_txpwr_lmt); i += 7) {
- u8 *regulation = array[i];
- u8 *band = array[i + 1];
- u8 *bandwidth = array[i + 2];
- u8 *rate = array[i + 3];
- u8 *rf_path = array[i + 4];
- u8 *chnl = array[i + 5];
- u8 *val = array[i + 6];
-
- odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth,
- rate, rf_path, chnl, val);
- }
-}
-
-/******************************************************************************
-* txpwr_lmt_type5.TXT
-******************************************************************************/
-
-static const char *const array_mp_8822b_txpwr_lmt_type5[] = {
- "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", "ETSI", "2.4G",
- "20M", "CCK", "1T", "01", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "01", "30", "FCC", "2.4G", "20M", "CCK", "1T", "02",
- "32", "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", "MKK",
- "2.4G", "20M", "CCK", "1T", "02", "30", "FCC", "2.4G", "20M",
- "CCK", "1T", "03", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
- "03", "28", "MKK", "2.4G", "20M", "CCK", "1T", "03", "30",
- "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", "ETSI", "2.4G",
- "20M", "CCK", "1T", "04", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "04", "30", "FCC", "2.4G", "20M", "CCK", "1T", "05",
- "32", "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", "MKK",
- "2.4G", "20M", "CCK", "1T", "05", "30", "FCC", "2.4G", "20M",
- "CCK", "1T", "06", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
- "06", "28", "MKK", "2.4G", "20M", "CCK", "1T", "06", "30",
- "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", "ETSI", "2.4G",
- "20M", "CCK", "1T", "07", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "07", "30", "FCC", "2.4G", "20M", "CCK", "1T", "08",
- "32", "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", "MKK",
- "2.4G", "20M", "CCK", "1T", "08", "30", "FCC", "2.4G", "20M",
- "CCK", "1T", "09", "32", "ETSI", "2.4G", "20M", "CCK", "1T",
- "09", "28", "MKK", "2.4G", "20M", "CCK", "1T", "09", "30",
- "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", "ETSI", "2.4G",
- "20M", "CCK", "1T", "10", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "10", "30", "FCC", "2.4G", "20M", "CCK", "1T", "11",
- "32", "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", "MKK",
- "2.4G", "20M", "CCK", "1T", "11", "30", "FCC", "2.4G", "20M",
- "CCK", "1T", "12", "26", "ETSI", "2.4G", "20M", "CCK", "1T",
- "12", "28", "MKK", "2.4G", "20M", "CCK", "1T", "12", "30",
- "FCC", "2.4G", "20M", "CCK", "1T", "13", "20", "ETSI", "2.4G",
- "20M", "CCK", "1T", "13", "28", "MKK", "2.4G", "20M", "CCK",
- "1T", "13", "28", "FCC", "2.4G", "20M", "CCK", "1T", "14",
- "63", "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", "MKK",
- "2.4G", "20M", "CCK", "1T", "14", "32", "FCC", "2.4G", "20M",
- "OFDM", "1T", "01", "26", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "01", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "02", "30", "MKK", "2.4G", "20M", "OFDM",
- "1T", "02", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "03",
- "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", "MKK",
- "2.4G", "20M", "OFDM", "1T", "03", "34", "FCC", "2.4G", "20M",
- "OFDM", "1T", "04", "34", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "04", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "05", "30", "MKK", "2.4G", "20M", "OFDM",
- "1T", "05", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "06",
- "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", "MKK",
- "2.4G", "20M", "OFDM", "1T", "06", "34", "FCC", "2.4G", "20M",
- "OFDM", "1T", "07", "34", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "07", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "08", "30", "MKK", "2.4G", "20M", "OFDM",
- "1T", "08", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "09",
- "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", "MKK",
- "2.4G", "20M", "OFDM", "1T", "09", "34", "FCC", "2.4G", "20M",
- "OFDM", "1T", "10", "30", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "10", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "11", "30", "MKK", "2.4G", "20M", "OFDM",
- "1T", "11", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "12",
- "22", "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", "MKK",
- "2.4G", "20M", "OFDM", "1T", "12", "34", "FCC", "2.4G", "20M",
- "OFDM", "1T", "13", "14", "ETSI", "2.4G", "20M", "OFDM", "1T",
- "13", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34",
- "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", "ETSI", "2.4G",
- "20M", "OFDM", "1T", "14", "63", "MKK", "2.4G", "20M", "OFDM",
- "1T", "14", "63", "FCC", "2.4G", "20M", "HT", "1T", "01",
- "26", "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "01", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "02", "30", "ETSI", "2.4G", "20M", "HT", "1T",
- "02", "30", "MKK", "2.4G", "20M", "HT", "1T", "02", "34",
- "FCC", "2.4G", "20M", "HT", "1T", "03", "32", "ETSI", "2.4G",
- "20M", "HT", "1T", "03", "30", "MKK", "2.4G", "20M", "HT",
- "1T", "03", "34", "FCC", "2.4G", "20M", "HT", "1T", "04",
- "34", "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "04", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "05", "34", "ETSI", "2.4G", "20M", "HT", "1T",
- "05", "30", "MKK", "2.4G", "20M", "HT", "1T", "05", "34",
- "FCC", "2.4G", "20M", "HT", "1T", "06", "34", "ETSI", "2.4G",
- "20M", "HT", "1T", "06", "30", "MKK", "2.4G", "20M", "HT",
- "1T", "06", "34", "FCC", "2.4G", "20M", "HT", "1T", "07",
- "34", "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "07", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "08", "34", "ETSI", "2.4G", "20M", "HT", "1T",
- "08", "30", "MKK", "2.4G", "20M", "HT", "1T", "08", "34",
- "FCC", "2.4G", "20M", "HT", "1T", "09", "32", "ETSI", "2.4G",
- "20M", "HT", "1T", "09", "30", "MKK", "2.4G", "20M", "HT",
- "1T", "09", "34", "FCC", "2.4G", "20M", "HT", "1T", "10",
- "30", "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "10", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "11", "26", "ETSI", "2.4G", "20M", "HT", "1T",
- "11", "30", "MKK", "2.4G", "20M", "HT", "1T", "11", "34",
- "FCC", "2.4G", "20M", "HT", "1T", "12", "20", "ETSI", "2.4G",
- "20M", "HT", "1T", "12", "30", "MKK", "2.4G", "20M", "HT",
- "1T", "12", "34", "FCC", "2.4G", "20M", "HT", "1T", "13",
- "14", "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", "MKK",
- "2.4G", "20M", "HT", "1T", "13", "34", "FCC", "2.4G", "20M",
- "HT", "1T", "14", "63", "ETSI", "2.4G", "20M", "HT", "1T",
- "14", "63", "MKK", "2.4G", "20M", "HT", "1T", "14", "63",
- "FCC", "2.4G", "20M", "HT", "2T", "01", "26", "ETSI", "2.4G",
- "20M", "HT", "2T", "01", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "01", "30", "FCC", "2.4G", "20M", "HT", "2T", "02",
- "28", "ETSI", "2.4G", "20M", "HT", "2T", "02", "18", "MKK",
- "2.4G", "20M", "HT", "2T", "02", "30", "FCC", "2.4G", "20M",
- "HT", "2T", "03", "30", "ETSI", "2.4G", "20M", "HT", "2T",
- "03", "18", "MKK", "2.4G", "20M", "HT", "2T", "03", "30",
- "FCC", "2.4G", "20M", "HT", "2T", "04", "30", "ETSI", "2.4G",
- "20M", "HT", "2T", "04", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "04", "30", "FCC", "2.4G", "20M", "HT", "2T", "05",
- "32", "ETSI", "2.4G", "20M", "HT", "2T", "05", "18", "MKK",
- "2.4G", "20M", "HT", "2T", "05", "30", "FCC", "2.4G", "20M",
- "HT", "2T", "06", "32", "ETSI", "2.4G", "20M", "HT", "2T",
- "06", "18", "MKK", "2.4G", "20M", "HT", "2T", "06", "30",
- "FCC", "2.4G", "20M", "HT", "2T", "07", "32", "ETSI", "2.4G",
- "20M", "HT", "2T", "07", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "07", "30", "FCC", "2.4G", "20M", "HT", "2T", "08",
- "30", "ETSI", "2.4G", "20M", "HT", "2T", "08", "18", "MKK",
- "2.4G", "20M", "HT", "2T", "08", "30", "FCC", "2.4G", "20M",
- "HT", "2T", "09", "30", "ETSI", "2.4G", "20M", "HT", "2T",
- "09", "18", "MKK", "2.4G", "20M", "HT", "2T", "09", "30",
- "FCC", "2.4G", "20M", "HT", "2T", "10", "28", "ETSI", "2.4G",
- "20M", "HT", "2T", "10", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "10", "30", "FCC", "2.4G", "20M", "HT", "2T", "11",
- "26", "ETSI", "2.4G", "20M", "HT", "2T", "11", "18", "MKK",
- "2.4G", "20M", "HT", "2T", "11", "30", "FCC", "2.4G", "20M",
- "HT", "2T", "12", "20", "ETSI", "2.4G", "20M", "HT", "2T",
- "12", "18", "MKK", "2.4G", "20M", "HT", "2T", "12", "30",
- "FCC", "2.4G", "20M", "HT", "2T", "13", "14", "ETSI", "2.4G",
- "20M", "HT", "2T", "13", "18", "MKK", "2.4G", "20M", "HT",
- "2T", "13", "30", "FCC", "2.4G", "20M", "HT", "2T", "14",
- "63", "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", "MKK",
- "2.4G", "20M", "HT", "2T", "14", "63", "FCC", "2.4G", "40M",
- "HT", "1T", "01", "63", "ETSI", "2.4G", "40M", "HT", "1T",
- "01", "63", "MKK", "2.4G", "40M", "HT", "1T", "01", "63",
- "FCC", "2.4G", "40M", "HT", "1T", "02", "63", "ETSI", "2.4G",
- "40M", "HT", "1T", "02", "63", "MKK", "2.4G", "40M", "HT",
- "1T", "02", "63", "FCC", "2.4G", "40M", "HT", "1T", "03",
- "26", "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", "MKK",
- "2.4G", "40M", "HT", "1T", "03", "34", "FCC", "2.4G", "40M",
- "HT", "1T", "04", "26", "ETSI", "2.4G", "40M", "HT", "1T",
- "04", "30", "MKK", "2.4G", "40M", "HT", "1T", "04", "34",
- "FCC", "2.4G", "40M", "HT", "1T", "05", "30", "ETSI", "2.4G",
- "40M", "HT", "1T", "05", "30", "MKK", "2.4G", "40M", "HT",
- "1T", "05", "34", "FCC", "2.4G", "40M", "HT", "1T", "06",
- "32", "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", "MKK",
- "2.4G", "40M", "HT", "1T", "06", "34", "FCC", "2.4G", "40M",
- "HT", "1T", "07", "30", "ETSI", "2.4G", "40M", "HT", "1T",
- "07", "30", "MKK", "2.4G", "40M", "HT", "1T", "07", "34",
- "FCC", "2.4G", "40M", "HT", "1T", "08", "26", "ETSI", "2.4G",
- "40M", "HT", "1T", "08", "30", "MKK", "2.4G", "40M", "HT",
- "1T", "08", "34", "FCC", "2.4G", "40M", "HT", "1T", "09",
- "26", "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", "MKK",
- "2.4G", "40M", "HT", "1T", "09", "34", "FCC", "2.4G", "40M",
- "HT", "1T", "10", "20", "ETSI", "2.4G", "40M", "HT", "1T",
- "10", "30", "MKK", "2.4G", "40M", "HT", "1T", "10", "34",
- "FCC", "2.4G", "40M", "HT", "1T", "11", "14", "ETSI", "2.4G",
- "40M", "HT", "1T", "11", "30", "MKK", "2.4G", "40M", "HT",
- "1T", "11", "34", "FCC", "2.4G", "40M", "HT", "1T", "12",
- "63", "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", "MKK",
- "2.4G", "40M", "HT", "1T", "12", "63", "FCC", "2.4G", "40M",
- "HT", "1T", "13", "63", "ETSI", "2.4G", "40M", "HT", "1T",
- "13", "63", "MKK", "2.4G", "40M", "HT", "1T", "13", "63",
- "FCC", "2.4G", "40M", "HT", "1T", "14", "63", "ETSI", "2.4G",
- "40M", "HT", "1T", "14", "63", "MKK", "2.4G", "40M", "HT",
- "1T", "14", "63", "FCC", "2.4G", "40M", "HT", "2T", "01",
- "63", "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", "MKK",
- "2.4G", "40M", "HT", "2T", "01", "63", "FCC", "2.4G", "40M",
- "HT", "2T", "02", "63", "ETSI", "2.4G", "40M", "HT", "2T",
- "02", "63", "MKK", "2.4G", "40M", "HT", "2T", "02", "63",
- "FCC", "2.4G", "40M", "HT", "2T", "03", "24", "ETSI", "2.4G",
- "40M", "HT", "2T", "03", "18", "MKK", "2.4G", "40M", "HT",
- "2T", "03", "30", "FCC", "2.4G", "40M", "HT", "2T", "04",
- "24", "ETSI", "2.4G", "40M", "HT", "2T", "04", "18", "MKK",
- "2.4G", "40M", "HT", "2T", "04", "30", "FCC", "2.4G", "40M",
- "HT", "2T", "05", "26", "ETSI", "2.4G", "40M", "HT", "2T",
- "05", "18", "MKK", "2.4G", "40M", "HT", "2T", "05", "30",
- "FCC", "2.4G", "40M", "HT", "2T", "06", "28", "ETSI", "2.4G",
- "40M", "HT", "2T", "06", "18", "MKK", "2.4G", "40M", "HT",
- "2T", "06", "30", "FCC", "2.4G", "40M", "HT", "2T", "07",
- "26", "ETSI", "2.4G", "40M", "HT", "2T", "07", "18", "MKK",
- "2.4G", "40M", "HT", "2T", "07", "30", "FCC", "2.4G", "40M",
- "HT", "2T", "08", "26", "ETSI", "2.4G", "40M", "HT", "2T",
- "08", "18", "MKK", "2.4G", "40M", "HT", "2T", "08", "30",
- "FCC", "2.4G", "40M", "HT", "2T", "09", "26", "ETSI", "2.4G",
- "40M", "HT", "2T", "09", "18", "MKK", "2.4G", "40M", "HT",
- "2T", "09", "30", "FCC", "2.4G", "40M", "HT", "2T", "10",
- "20", "ETSI", "2.4G", "40M", "HT", "2T", "10", "18", "MKK",
- "2.4G", "40M", "HT", "2T", "10", "30", "FCC", "2.4G", "40M",
- "HT", "2T", "11", "14", "ETSI", "2.4G", "40M", "HT", "2T",
- "11", "18", "MKK", "2.4G", "40M", "HT", "2T", "11", "30",
- "FCC", "2.4G", "40M", "HT", "2T", "12", "63", "ETSI", "2.4G",
- "40M", "HT", "2T", "12", "63", "MKK", "2.4G", "40M", "HT",
- "2T", "12", "63", "FCC", "2.4G", "40M", "HT", "2T", "13",
- "63", "ETSI", "2.4G", "40M", "HT", "2T", "13", "63", "MKK",
- "2.4G", "40M", "HT", "2T", "13", "63", "FCC", "2.4G", "40M",
- "HT", "2T", "14", "63", "ETSI", "2.4G", "40M", "HT", "2T",
- "14", "63", "MKK", "2.4G", "40M", "HT", "2T", "14", "63",
- "FCC", "5G", "20M", "OFDM", "1T", "36", "30", "ETSI", "5G",
- "20M", "OFDM", "1T", "36", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "36", "30", "FCC", "5G", "20M", "OFDM", "1T", "40",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "40", "30", "FCC", "5G", "20M",
- "OFDM", "1T", "44", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "44", "32", "MKK", "5G", "20M", "OFDM", "1T", "44", "30",
- "FCC", "5G", "20M", "OFDM", "1T", "48", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "48", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "48", "30", "FCC", "5G", "20M", "OFDM", "1T", "52",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "52", "28", "FCC", "5G", "20M",
- "OFDM", "1T", "56", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "56", "32", "MKK", "5G", "20M", "OFDM", "1T", "56", "28",
- "FCC", "5G", "20M", "OFDM", "1T", "60", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "60", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "60", "28", "FCC", "5G", "20M", "OFDM", "1T", "64",
- "28", "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "64", "28", "FCC", "5G", "20M",
- "OFDM", "1T", "100", "26", "ETSI", "5G", "20M", "OFDM", "1T",
- "100", "32", "MKK", "5G", "20M", "OFDM", "1T", "100", "32",
- "FCC", "5G", "20M", "OFDM", "1T", "104", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "104", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "104", "32", "FCC", "5G", "20M", "OFDM", "1T", "108",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "108", "32", "FCC", "5G", "20M",
- "OFDM", "1T", "112", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "112", "32", "MKK", "5G", "20M", "OFDM", "1T", "112", "32",
- "FCC", "5G", "20M", "OFDM", "1T", "116", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "116", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "116", "32", "FCC", "5G", "20M", "OFDM", "1T", "120",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "120", "32", "FCC", "5G", "20M",
- "OFDM", "1T", "124", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "124", "32", "MKK", "5G", "20M", "OFDM", "1T", "124", "32",
- "FCC", "5G", "20M", "OFDM", "1T", "128", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "128", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "128", "32", "FCC", "5G", "20M", "OFDM", "1T", "132",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "132", "32", "FCC", "5G", "20M",
- "OFDM", "1T", "136", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "136", "32", "MKK", "5G", "20M", "OFDM", "1T", "136", "32",
- "FCC", "5G", "20M", "OFDM", "1T", "140", "28", "ETSI", "5G",
- "20M", "OFDM", "1T", "140", "32", "MKK", "5G", "20M", "OFDM",
- "1T", "140", "32", "FCC", "5G", "20M", "OFDM", "1T", "144",
- "28", "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", "MKK",
- "5G", "20M", "OFDM", "1T", "144", "63", "FCC", "5G", "20M",
- "OFDM", "1T", "149", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "149", "63", "MKK", "5G", "20M", "OFDM", "1T", "149", "63",
- "FCC", "5G", "20M", "OFDM", "1T", "153", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "153", "63", "MKK", "5G", "20M", "OFDM",
- "1T", "153", "63", "FCC", "5G", "20M", "OFDM", "1T", "157",
- "32", "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", "MKK",
- "5G", "20M", "OFDM", "1T", "157", "63", "FCC", "5G", "20M",
- "OFDM", "1T", "161", "32", "ETSI", "5G", "20M", "OFDM", "1T",
- "161", "63", "MKK", "5G", "20M", "OFDM", "1T", "161", "63",
- "FCC", "5G", "20M", "OFDM", "1T", "165", "32", "ETSI", "5G",
- "20M", "OFDM", "1T", "165", "63", "MKK", "5G", "20M", "OFDM",
- "1T", "165", "63", "FCC", "5G", "20M", "HT", "1T", "36",
- "30", "ETSI", "5G", "20M", "HT", "1T", "36", "32", "MKK",
- "5G", "20M", "HT", "1T", "36", "28", "FCC", "5G", "20M",
- "HT", "1T", "40", "32", "ETSI", "5G", "20M", "HT", "1T",
- "40", "32", "MKK", "5G", "20M", "HT", "1T", "40", "28",
- "FCC", "5G", "20M", "HT", "1T", "44", "32", "ETSI", "5G",
- "20M", "HT", "1T", "44", "32", "MKK", "5G", "20M", "HT",
- "1T", "44", "28", "FCC", "5G", "20M", "HT", "1T", "48",
- "32", "ETSI", "5G", "20M", "HT", "1T", "48", "32", "MKK",
- "5G", "20M", "HT", "1T", "48", "28", "FCC", "5G", "20M",
- "HT", "1T", "52", "32", "ETSI", "5G", "20M", "HT", "1T",
- "52", "32", "MKK", "5G", "20M", "HT", "1T", "52", "28",
- "FCC", "5G", "20M", "HT", "1T", "56", "32", "ETSI", "5G",
- "20M", "HT", "1T", "56", "32", "MKK", "5G", "20M", "HT",
- "1T", "56", "28", "FCC", "5G", "20M", "HT", "1T", "60",
- "32", "ETSI", "5G", "20M", "HT", "1T", "60", "32", "MKK",
- "5G", "20M", "HT", "1T", "60", "28", "FCC", "5G", "20M",
- "HT", "1T", "64", "28", "ETSI", "5G", "20M", "HT", "1T",
- "64", "32", "MKK", "5G", "20M", "HT", "1T", "64", "28",
- "FCC", "5G", "20M", "HT", "1T", "100", "26", "ETSI", "5G",
- "20M", "HT", "1T", "100", "32", "MKK", "5G", "20M", "HT",
- "1T", "100", "32", "FCC", "5G", "20M", "HT", "1T", "104",
- "32", "ETSI", "5G", "20M", "HT", "1T", "104", "32", "MKK",
- "5G", "20M", "HT", "1T", "104", "32", "FCC", "5G", "20M",
- "HT", "1T", "108", "32", "ETSI", "5G", "20M", "HT", "1T",
- "108", "32", "MKK", "5G", "20M", "HT", "1T", "108", "32",
- "FCC", "5G", "20M", "HT", "1T", "112", "32", "ETSI", "5G",
- "20M", "HT", "1T", "112", "32", "MKK", "5G", "20M", "HT",
- "1T", "112", "32", "FCC", "5G", "20M", "HT", "1T", "116",
- "32", "ETSI", "5G", "20M", "HT", "1T", "116", "32", "MKK",
- "5G", "20M", "HT", "1T", "116", "32", "FCC", "5G", "20M",
- "HT", "1T", "120", "32", "ETSI", "5G", "20M", "HT", "1T",
- "120", "32", "MKK", "5G", "20M", "HT", "1T", "120", "32",
- "FCC", "5G", "20M", "HT", "1T", "124", "32", "ETSI", "5G",
- "20M", "HT", "1T", "124", "32", "MKK", "5G", "20M", "HT",
- "1T", "124", "32", "FCC", "5G", "20M", "HT", "1T", "128",
- "32", "ETSI", "5G", "20M", "HT", "1T", "128", "32", "MKK",
- "5G", "20M", "HT", "1T", "128", "32", "FCC", "5G", "20M",
- "HT", "1T", "132", "32", "ETSI", "5G", "20M", "HT", "1T",
- "132", "32", "MKK", "5G", "20M", "HT", "1T", "132", "32",
- "FCC", "5G", "20M", "HT", "1T", "136", "32", "ETSI", "5G",
- "20M", "HT", "1T", "136", "32", "MKK", "5G", "20M", "HT",
- "1T", "136", "32", "FCC", "5G", "20M", "HT", "1T", "140",
- "26", "ETSI", "5G", "20M", "HT", "1T", "140", "32", "MKK",
- "5G", "20M", "HT", "1T", "140", "32", "FCC", "5G", "20M",
- "HT", "1T", "144", "26", "ETSI", "5G", "20M", "HT", "1T",
- "144", "63", "MKK", "5G", "20M", "HT", "1T", "144", "63",
- "FCC", "5G", "20M", "HT", "1T", "149", "32", "ETSI", "5G",
- "20M", "HT", "1T", "149", "63", "MKK", "5G", "20M", "HT",
- "1T", "149", "63", "FCC", "5G", "20M", "HT", "1T", "153",
- "32", "ETSI", "5G", "20M", "HT", "1T", "153", "63", "MKK",
- "5G", "20M", "HT", "1T", "153", "63", "FCC", "5G", "20M",
- "HT", "1T", "157", "32", "ETSI", "5G", "20M", "HT", "1T",
- "157", "63", "MKK", "5G", "20M", "HT", "1T", "157", "63",
- "FCC", "5G", "20M", "HT", "1T", "161", "32", "ETSI", "5G",
- "20M", "HT", "1T", "161", "63", "MKK", "5G", "20M", "HT",
- "1T", "161", "63", "FCC", "5G", "20M", "HT", "1T", "165",
- "32", "ETSI", "5G", "20M", "HT", "1T", "165", "63", "MKK",
- "5G", "20M", "HT", "1T", "165", "63", "FCC", "5G", "20M",
- "HT", "2T", "36", "28", "ETSI", "5G", "20M", "HT", "2T",
- "36", "20", "MKK", "5G", "20M", "HT", "2T", "36", "22",
- "FCC", "5G", "20M", "HT", "2T", "40", "30", "ETSI", "5G",
- "20M", "HT", "2T", "40", "20", "MKK", "5G", "20M", "HT",
- "2T", "40", "22", "FCC", "5G", "20M", "HT", "2T", "44",
- "30", "ETSI", "5G", "20M", "HT", "2T", "44", "20", "MKK",
- "5G", "20M", "HT", "2T", "44", "22", "FCC", "5G", "20M",
- "HT", "2T", "48", "30", "ETSI", "5G", "20M", "HT", "2T",
- "48", "20", "MKK", "5G", "20M", "HT", "2T", "48", "22",
- "FCC", "5G", "20M", "HT", "2T", "52", "30", "ETSI", "5G",
- "20M", "HT", "2T", "52", "20", "MKK", "5G", "20M", "HT",
- "2T", "52", "22", "FCC", "5G", "20M", "HT", "2T", "56",
- "30", "ETSI", "5G", "20M", "HT", "2T", "56", "20", "MKK",
- "5G", "20M", "HT", "2T", "56", "22", "FCC", "5G", "20M",
- "HT", "2T", "60", "30", "ETSI", "5G", "20M", "HT", "2T",
- "60", "20", "MKK", "5G", "20M", "HT", "2T", "60", "22",
- "FCC", "5G", "20M", "HT", "2T", "64", "28", "ETSI", "5G",
- "20M", "HT", "2T", "64", "20", "MKK", "5G", "20M", "HT",
- "2T", "64", "22", "FCC", "5G", "20M", "HT", "2T", "100",
- "26", "ETSI", "5G", "20M", "HT", "2T", "100", "20", "MKK",
- "5G", "20M", "HT", "2T", "100", "30", "FCC", "5G", "20M",
- "HT", "2T", "104", "30", "ETSI", "5G", "20M", "HT", "2T",
- "104", "20", "MKK", "5G", "20M", "HT", "2T", "104", "30",
- "FCC", "5G", "20M", "HT", "2T", "108", "32", "ETSI", "5G",
- "20M", "HT", "2T", "108", "20", "MKK", "5G", "20M", "HT",
- "2T", "108", "30", "FCC", "5G", "20M", "HT", "2T", "112",
- "32", "ETSI", "5G", "20M", "HT", "2T", "112", "20", "MKK",
- "5G", "20M", "HT", "2T", "112", "30", "FCC", "5G", "20M",
- "HT", "2T", "116", "32", "ETSI", "5G", "20M", "HT", "2T",
- "116", "20", "MKK", "5G", "20M", "HT", "2T", "116", "30",
- "FCC", "5G", "20M", "HT", "2T", "120", "32", "ETSI", "5G",
- "20M", "HT", "2T", "120", "20", "MKK", "5G", "20M", "HT",
- "2T", "120", "30", "FCC", "5G", "20M", "HT", "2T", "124",
- "32", "ETSI", "5G", "20M", "HT", "2T", "124", "20", "MKK",
- "5G", "20M", "HT", "2T", "124", "30", "FCC", "5G", "20M",
- "HT", "2T", "128", "32", "ETSI", "5G", "20M", "HT", "2T",
- "128", "20", "MKK", "5G", "20M", "HT", "2T", "128", "30",
- "FCC", "5G", "20M", "HT", "2T", "132", "32", "ETSI", "5G",
- "20M", "HT", "2T", "132", "20", "MKK", "5G", "20M", "HT",
- "2T", "132", "30", "FCC", "5G", "20M", "HT", "2T", "136",
- "30", "ETSI", "5G", "20M", "HT", "2T", "136", "20", "MKK",
- "5G", "20M", "HT", "2T", "136", "30", "FCC", "5G", "20M",
- "HT", "2T", "140", "26", "ETSI", "5G", "20M", "HT", "2T",
- "140", "20", "MKK", "5G", "20M", "HT", "2T", "140", "30",
- "FCC", "5G", "20M", "HT", "2T", "144", "26", "ETSI", "5G",
- "20M", "HT", "2T", "144", "63", "MKK", "5G", "20M", "HT",
- "2T", "144", "63", "FCC", "5G", "20M", "HT", "2T", "149",
- "32", "ETSI", "5G", "20M", "HT", "2T", "149", "63", "MKK",
- "5G", "20M", "HT", "2T", "149", "63", "FCC", "5G", "20M",
- "HT", "2T", "153", "32", "ETSI", "5G", "20M", "HT", "2T",
- "153", "63", "MKK", "5G", "20M", "HT", "2T", "153", "63",
- "FCC", "5G", "20M", "HT", "2T", "157", "32", "ETSI", "5G",
- "20M", "HT", "2T", "157", "63", "MKK", "5G", "20M", "HT",
- "2T", "157", "63", "FCC", "5G", "20M", "HT", "2T", "161",
- "32", "ETSI", "5G", "20M", "HT", "2T", "161", "63", "MKK",
- "5G", "20M", "HT", "2T", "161", "63", "FCC", "5G", "20M",
- "HT", "2T", "165", "32", "ETSI", "5G", "20M", "HT", "2T",
- "165", "63", "MKK", "5G", "20M", "HT", "2T", "165", "63",
- "FCC", "5G", "40M", "HT", "1T", "38", "22", "ETSI", "5G",
- "40M", "HT", "1T", "38", "30", "MKK", "5G", "40M", "HT",
- "1T", "38", "30", "FCC", "5G", "40M", "HT", "1T", "46",
- "30", "ETSI", "5G", "40M", "HT", "1T", "46", "30", "MKK",
- "5G", "40M", "HT", "1T", "46", "30", "FCC", "5G", "40M",
- "HT", "1T", "54", "30", "ETSI", "5G", "40M", "HT", "1T",
- "54", "30", "MKK", "5G", "40M", "HT", "1T", "54", "30",
- "FCC", "5G", "40M", "HT", "1T", "62", "24", "ETSI", "5G",
- "40M", "HT", "1T", "62", "30", "MKK", "5G", "40M", "HT",
- "1T", "62", "30", "FCC", "5G", "40M", "HT", "1T", "102",
- "24", "ETSI", "5G", "40M", "HT", "1T", "102", "30", "MKK",
- "5G", "40M", "HT", "1T", "102", "30", "FCC", "5G", "40M",
- "HT", "1T", "110", "30", "ETSI", "5G", "40M", "HT", "1T",
- "110", "30", "MKK", "5G", "40M", "HT", "1T", "110", "30",
- "FCC", "5G", "40M", "HT", "1T", "118", "30", "ETSI", "5G",
- "40M", "HT", "1T", "118", "30", "MKK", "5G", "40M", "HT",
- "1T", "118", "30", "FCC", "5G", "40M", "HT", "1T", "126",
- "30", "ETSI", "5G", "40M", "HT", "1T", "126", "30", "MKK",
- "5G", "40M", "HT", "1T", "126", "30", "FCC", "5G", "40M",
- "HT", "1T", "134", "30", "ETSI", "5G", "40M", "HT", "1T",
- "134", "30", "MKK", "5G", "40M", "HT", "1T", "134", "30",
- "FCC", "5G", "40M", "HT", "1T", "142", "30", "ETSI", "5G",
- "40M", "HT", "1T", "142", "63", "MKK", "5G", "40M", "HT",
- "1T", "142", "63", "FCC", "5G", "40M", "HT", "1T", "151",
- "30", "ETSI", "5G", "40M", "HT", "1T", "151", "63", "MKK",
- "5G", "40M", "HT", "1T", "151", "63", "FCC", "5G", "40M",
- "HT", "1T", "159", "30", "ETSI", "5G", "40M", "HT", "1T",
- "159", "63", "MKK", "5G", "40M", "HT", "1T", "159", "63",
- "FCC", "5G", "40M", "HT", "2T", "38", "20", "ETSI", "5G",
- "40M", "HT", "2T", "38", "20", "MKK", "5G", "40M", "HT",
- "2T", "38", "22", "FCC", "5G", "40M", "HT", "2T", "46",
- "30", "ETSI", "5G", "40M", "HT", "2T", "46", "20", "MKK",
- "5G", "40M", "HT", "2T", "46", "22", "FCC", "5G", "40M",
- "HT", "2T", "54", "30", "ETSI", "5G", "40M", "HT", "2T",
- "54", "20", "MKK", "5G", "40M", "HT", "2T", "54", "22",
- "FCC", "5G", "40M", "HT", "2T", "62", "22", "ETSI", "5G",
- "40M", "HT", "2T", "62", "20", "MKK", "5G", "40M", "HT",
- "2T", "62", "22", "FCC", "5G", "40M", "HT", "2T", "102",
- "22", "ETSI", "5G", "40M", "HT", "2T", "102", "20", "MKK",
- "5G", "40M", "HT", "2T", "102", "30", "FCC", "5G", "40M",
- "HT", "2T", "110", "30", "ETSI", "5G", "40M", "HT", "2T",
- "110", "20", "MKK", "5G", "40M", "HT", "2T", "110", "30",
- "FCC", "5G", "40M", "HT", "2T", "118", "30", "ETSI", "5G",
- "40M", "HT", "2T", "118", "20", "MKK", "5G", "40M", "HT",
- "2T", "118", "30", "FCC", "5G", "40M", "HT", "2T", "126",
- "30", "ETSI", "5G", "40M", "HT", "2T", "126", "20", "MKK",
- "5G", "40M", "HT", "2T", "126", "30", "FCC", "5G", "40M",
- "HT", "2T", "134", "30", "ETSI", "5G", "40M", "HT", "2T",
- "134", "20", "MKK", "5G", "40M", "HT", "2T", "134", "30",
- "FCC", "5G", "40M", "HT", "2T", "142", "30", "ETSI", "5G",
- "40M", "HT", "2T", "142", "63", "MKK", "5G", "40M", "HT",
- "2T", "142", "63", "FCC", "5G", "40M", "HT", "2T", "151",
- "30", "ETSI", "5G", "40M", "HT", "2T", "151", "63", "MKK",
- "5G", "40M", "HT", "2T", "151", "63", "FCC", "5G", "40M",
- "HT", "2T", "159", "30", "ETSI", "5G", "40M", "HT", "2T",
- "159", "63", "MKK", "5G", "40M", "HT", "2T", "159", "63",
- "FCC", "5G", "80M", "VHT", "1T", "42", "20", "ETSI", "5G",
- "80M", "VHT", "1T", "42", "30", "MKK", "5G", "80M", "VHT",
- "1T", "42", "28", "FCC", "5G", "80M", "VHT", "1T", "58",
- "20", "ETSI", "5G", "80M", "VHT", "1T", "58", "30", "MKK",
- "5G", "80M", "VHT", "1T", "58", "28", "FCC", "5G", "80M",
- "VHT", "1T", "106", "20", "ETSI", "5G", "80M", "VHT", "1T",
- "106", "30", "MKK", "5G", "80M", "VHT", "1T", "106", "30",
- "FCC", "5G", "80M", "VHT", "1T", "122", "30", "ETSI", "5G",
- "80M", "VHT", "1T", "122", "30", "MKK", "5G", "80M", "VHT",
- "1T", "122", "30", "FCC", "5G", "80M", "VHT", "1T", "138",
- "30", "ETSI", "5G", "80M", "VHT", "1T", "138", "63", "MKK",
- "5G", "80M", "VHT", "1T", "138", "63", "FCC", "5G", "80M",
- "VHT", "1T", "155", "30", "ETSI", "5G", "80M", "VHT", "1T",
- "155", "63", "MKK", "5G", "80M", "VHT", "1T", "155", "63",
- "FCC", "5G", "80M", "VHT", "2T", "42", "18", "ETSI", "5G",
- "80M", "VHT", "2T", "42", "20", "MKK", "5G", "80M", "VHT",
- "2T", "42", "22", "FCC", "5G", "80M", "VHT", "2T", "58",
- "18", "ETSI", "5G", "80M", "VHT", "2T", "58", "20", "MKK",
- "5G", "80M", "VHT", "2T", "58", "22", "FCC", "5G", "80M",
- "VHT", "2T", "106", "20", "ETSI", "5G", "80M", "VHT", "2T",
- "106", "20", "MKK", "5G", "80M", "VHT", "2T", "106", "30",
- "FCC", "5G", "80M", "VHT", "2T", "122", "30", "ETSI", "5G",
- "80M", "VHT", "2T", "122", "20", "MKK", "5G", "80M", "VHT",
- "2T", "122", "30", "FCC", "5G", "80M", "VHT", "2T", "138",
- "30", "ETSI", "5G", "80M", "VHT", "2T", "138", "63", "MKK",
- "5G", "80M", "VHT", "2T", "138", "63", "FCC", "5G", "80M",
- "VHT", "2T", "155", "30", "ETSI", "5G", "80M", "VHT", "2T",
- "155", "63", "MKK", "5G", "80M", "VHT", "2T", "155", "63"};
-
-void odm_read_and_config_mp_8822b_txpwr_lmt_type5(struct phy_dm_struct *dm)
-{
- u32 i = 0;
- u8 **array = (u8 **)array_mp_8822b_txpwr_lmt_type5;
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT,
- "===> odm_read_and_config_mp_8822b_txpwr_lmt_type5\n");
-
- for (i = 0; i < ARRAY_SIZE(array_mp_8822b_txpwr_lmt_type5); i += 7) {
- u8 *regulation = array[i];
- u8 *band = array[i + 1];
- u8 *bandwidth = array[i + 2];
- u8 *rate = array[i + 3];
- u8 *rf_path = array[i + 4];
- u8 *chnl = array[i + 5];
- u8 *val = array[i + 6];
-
- odm_config_bb_txpwr_lmt_8822b(dm, regulation, band, bandwidth,
- rate, rf_path, chnl, val);
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-/*Image2HeaderVersion: 3.2*/
-#ifndef __INC_MP_RF_HW_IMG_8822B_H
-#define __INC_MP_RF_HW_IMG_8822B_H
-
-/******************************************************************************
- * radioa.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_radioa(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_radioa(void);
-
-/******************************************************************************
- * radiob.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_radiob(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_radiob(void);
-
-/******************************************************************************
- * txpowertrack.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack(void);
-
-/******************************************************************************
- * txpowertrack_type0.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack_type0(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack_type0(void);
-
-/******************************************************************************
- * txpowertrack_type1.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack_type1(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack_type1(void);
-
-/******************************************************************************
- * txpowertrack_type2.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack_type2(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack_type2(void);
-
-/******************************************************************************
- * txpowertrack_type3_type5.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack_type3_type5(
- struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack_type3_type5(void);
-
-/******************************************************************************
- * txpowertrack_type4.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack_type4(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack_type4(void);
-
-/******************************************************************************
- * txpowertrack_type6.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack_type6(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack_type6(void);
-
-/******************************************************************************
- * txpowertrack_type7.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack_type7(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack_type7(void);
-
-/******************************************************************************
- * txpowertrack_type8.TXT
- *****************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack_type8(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack_type8(void);
-
-/******************************************************************************
- * txpowertrack_type9.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpowertrack_type9(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpowertrack_type9(void);
-
-/******************************************************************************
- * txpwr_lmt.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpwr_lmt(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpwr_lmt(void);
-
-/******************************************************************************
- * txpwr_lmt_type5.TXT
- ******************************************************************************/
-
-void odm_read_and_config_mp_8822b_txpwr_lmt_type5(struct phy_dm_struct *dm);
-u32 odm_get_version_mp_8822b_txpwr_lmt_type5(void);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../mp_precomp.h"
-#include "../phydm_precomp.h"
-
-static bool
-get_mix_mode_tx_agc_bb_swing_offset_8822b(void *dm_void,
- enum pwrtrack_method method,
- u8 rf_path, u8 tx_power_index_offset)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
- u8 bb_swing_lower_bound = 0;
-
- s8 tx_agc_index = 0;
- u8 tx_bb_swing_index = cali_info->default_ofdm_index;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offset=%d\n",
- rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
- tx_power_index_offset);
-
- if (tx_power_index_offset > 0XF)
- tx_power_index_offset = 0XF;
-
- if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 &&
- cali_info->absolute_ofdm_swing_idx[rf_path] <=
- tx_power_index_offset) {
- tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
- tx_bb_swing_index = cali_info->default_ofdm_index;
- } else if (cali_info->absolute_ofdm_swing_idx[rf_path] >
- tx_power_index_offset) {
- tx_agc_index = tx_power_index_offset;
- cali_info->remnant_ofdm_swing_idx[rf_path] =
- cali_info->absolute_ofdm_swing_idx[rf_path] -
- tx_power_index_offset;
- tx_bb_swing_index = cali_info->default_ofdm_index +
- cali_info->remnant_ofdm_swing_idx[rf_path];
-
- if (tx_bb_swing_index > bb_swing_upper_bound)
- tx_bb_swing_index = bb_swing_upper_bound;
- } else {
- tx_agc_index = 0;
-
- if (cali_info->default_ofdm_index >
- (cali_info->absolute_ofdm_swing_idx[rf_path] * (-1)))
- tx_bb_swing_index =
- cali_info->default_ofdm_index +
- cali_info->absolute_ofdm_swing_idx[rf_path];
- else
- tx_bb_swing_index = bb_swing_lower_bound;
-
- if (tx_bb_swing_index < bb_swing_lower_bound)
- tx_bb_swing_index = bb_swing_lower_bound;
- }
-
- cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
- cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "MixMode Offset Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d cali_info->bb_swing_idx_ofdm[rf_path]=%d tx_power_index_offset=%d\n",
- rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
- cali_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offset);
-
- return true;
-}
-
-void odm_tx_pwr_track_set_pwr8822b(void *dm_void, enum pwrtrack_method method,
- u8 rf_path, u8 channel_mapped_index)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
- u8 tx_power_index_offset = 0;
- u8 tx_power_index = 0;
-
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 channel = rtlphy->current_channel;
- u8 band_width = rtlphy->current_chan_bw;
- u8 tx_rate = 0xFF;
-
- if (!dm->mp_mode) {
- u16 rate = *dm->forced_data_rate;
-
- if (!rate) /*auto rate*/
- tx_rate = dm->tx_rate;
- else /*force rate*/
- tx_rate = (u8)rate;
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n",
- __func__, tx_rate);
-
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n",
- cali_info->default_ofdm_index,
- cali_info->default_cck_index);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n",
- cali_info->absolute_ofdm_swing_idx[rf_path],
- cali_info->remnant_ofdm_swing_idx[rf_path],
- cali_info->absolute_cck_swing_idx[rf_path],
- cali_info->remnant_cck_swing_idx, rf_path);
-
- if (dm->number_linked_client != 0)
- tx_power_index = odm_get_tx_power_index(
- dm, (enum odm_rf_radio_path)rf_path, tx_rate,
- band_width, channel);
-
- if (tx_power_index >= 63)
- tx_power_index = 63;
-
- tx_power_index_offset = 63 - tx_power_index;
-
- ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
- "tx_power_index=%d tx_power_index_offset=%d rf_path=%d\n",
- tx_power_index, tx_power_index_offset, rf_path);
-
- if (method ==
- BBSWING) { /*use for mp driver clean power tracking status*/
- switch (rf_path) {
- case ODM_RF_PATH_A:
- odm_set_bb_reg(
- dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) |
- BIT(26) | BIT(25)),
- cali_info->absolute_ofdm_swing_idx[rf_path]);
- odm_set_bb_reg(
- dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000,
- tx_scaling_table_jaguar
- [cali_info
- ->bb_swing_idx_ofdm[rf_path]]);
- break;
- case ODM_RF_PATH_B:
- odm_set_bb_reg(
- dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) |
- BIT(26) | BIT(25)),
- cali_info->absolute_ofdm_swing_idx[rf_path]);
- odm_set_bb_reg(
- dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000,
- tx_scaling_table_jaguar
- [cali_info
- ->bb_swing_idx_ofdm[rf_path]]);
- break;
-
- default:
- break;
- }
- } else if (method == MIX_MODE) {
- switch (rf_path) {
- case ODM_RF_PATH_A:
- get_mix_mode_tx_agc_bb_swing_offset_8822b(
- dm, method, rf_path, tx_power_index_offset);
- odm_set_bb_reg(
- dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) |
- BIT(26) | BIT(25)),
- cali_info->absolute_ofdm_swing_idx[rf_path]);
- odm_set_bb_reg(
- dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000,
- tx_scaling_table_jaguar
- [cali_info
- ->bb_swing_idx_ofdm[rf_path]]);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
- odm_get_bb_reg(dm, 0xC94,
- (BIT(29) | BIT(28) | BIT(27) |
- BIT(26) | BIT(25))),
- odm_get_bb_reg(dm, 0xc1c, 0xFFE00000),
- cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
- break;
-
- case ODM_RF_PATH_B:
- get_mix_mode_tx_agc_bb_swing_offset_8822b(
- dm, method, rf_path, tx_power_index_offset);
- odm_set_bb_reg(
- dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) |
- BIT(26) | BIT(25)),
- cali_info->absolute_ofdm_swing_idx[rf_path]);
- odm_set_bb_reg(
- dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000,
- tx_scaling_table_jaguar
- [cali_info
- ->bb_swing_idx_ofdm[rf_path]]);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_TX_PWR_TRACK,
- "TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
- odm_get_bb_reg(dm, 0xE94,
- (BIT(29) | BIT(28) | BIT(27) |
- BIT(26) | BIT(25))),
- odm_get_bb_reg(dm, 0xe1c, 0xFFE00000),
- cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
- break;
-
- default:
- break;
- }
- }
-}
-
-void get_delta_swing_table_8822b(void *dm_void, u8 **temperature_up_a,
- u8 **temperature_down_a, u8 **temperature_up_b,
- u8 **temperature_down_b)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-
- struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 channel = rtlphy->current_channel;
-
- *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
- *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
- *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
- *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
-
- if (channel >= 36 && channel <= 64) {
- *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
- *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
- *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
- *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
- } else if (channel >= 100 && channel <= 144) {
- *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
- *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
- *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
- *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
- } else if (channel >= 149 && channel <= 177) {
- *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
- *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
- *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
- *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
- }
-}
-
-static void _phy_lc_calibrate_8822b(struct phy_dm_struct *dm)
-{
- u32 lc_cal = 0, cnt = 0;
-
- /*backup RF0x18*/
- lc_cal = odm_get_rf_reg(dm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
-
- /*Start LCK*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK,
- lc_cal | 0x08000);
-
- ODM_delay_ms(100);
-
- for (cnt = 0; cnt < 100; cnt++) {
- if (odm_get_rf_reg(dm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
- break;
- ODM_delay_ms(10);
- }
-
- /*Recover channel number*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
-}
-
-void phy_lc_calibrate_8822b(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- bool is_start_cont_tx = false, is_single_tone = false,
- is_carrier_suppression = false;
- u64 start_time;
- u64 progressing_time;
-
- if (is_start_cont_tx || is_single_tone || is_carrier_suppression) {
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[LCK]continues TX ing !!! LCK return\n");
- return;
- }
-
- start_time = odm_get_current_time(dm);
- _phy_lc_calibrate_8822b(dm);
- progressing_time = odm_get_progressing_time(dm, start_time);
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[LCK]LCK progressing_time = %lld\n", progressing_time);
-}
-
-void configure_txpower_track_8822b(struct txpwrtrack_cfg *config)
-{
- config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
- config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
- config->threshold_iqk = IQK_THRESHOLD;
- config->threshold_dpk = DPK_THRESHOLD;
- config->average_thermal_num = AVG_THERMAL_NUM_8822B;
- config->rf_path_count = MAX_PATH_NUM_8822B;
- config->thermal_reg_addr = RF_T_METER_8822B;
-
- config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8822b;
- config->do_iqk = do_iqk_8822b;
- config->phy_lc_calibrate = phy_lc_calibrate_8822b;
-
- config->get_delta_swing_table = get_delta_swing_table_8822b;
-}
-
-void phy_set_rf_path_switch_8822b(struct phy_dm_struct *dm, bool is_main)
-{
- /*BY SY Request */
- odm_set_bb_reg(dm, 0x4C, (BIT(24) | BIT(23)), 0x2);
- odm_set_bb_reg(dm, 0x974, 0xff, 0xff);
-
- /*odm_set_bb_reg(dm, 0x1991, 0x3, 0x0);*/
- odm_set_bb_reg(dm, 0x1990, (BIT(9) | BIT(8)), 0x0);
-
- /*odm_set_bb_reg(dm, 0xCBE, 0x8, 0x0);*/
- odm_set_bb_reg(dm, 0xCBC, BIT(19), 0x0);
-
- odm_set_bb_reg(dm, 0xCB4, 0xff, 0x77);
-
- odm_set_bb_reg(dm, 0x70, MASKBYTE3, 0x0e);
- odm_set_bb_reg(dm, 0x1704, MASKDWORD, 0x0000ff00);
- odm_set_bb_reg(dm, 0x1700, MASKDWORD, 0xc00f0038);
-
- if (is_main) {
- /*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x2); WiFi */
- odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x2); /*WiFi */
- } else {
- /*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x1); BT*/
- odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x1); /*BT*/
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __HAL_PHY_RF_8822B_H__
-#define __HAL_PHY_RF_8822B_H__
-
-#define AVG_THERMAL_NUM_8822B 4
-#define RF_T_METER_8822B 0x42
-
-void configure_txpower_track_8822b(struct txpwrtrack_cfg *config);
-
-void odm_tx_pwr_track_set_pwr8822b(void *dm_void, enum pwrtrack_method method,
- u8 rf_path, u8 channel_mapped_index);
-
-void get_delta_swing_table_8822b(void *dm_void, u8 **temperature_up_a,
- u8 **temperature_down_a, u8 **temperature_up_b,
- u8 **temperature_down_b);
-
-void phy_lc_calibrate_8822b(void *dm_void);
-
-void phy_set_rf_path_switch_8822b(struct phy_dm_struct *dm, bool is_main);
-
-#endif /* #ifndef __HAL_PHY_RF_8822B_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../mp_precomp.h"
-#include "../phydm_precomp.h"
-
-/* ======================================================================== */
-/* These following functions can be used for PHY DM only*/
-
-static u32 reg82c_8822b;
-static u32 reg838_8822b;
-static u32 reg830_8822b;
-static u32 reg83c_8822b;
-static u32 rega20_8822b;
-static u32 rega24_8822b;
-static u32 rega28_8822b;
-static enum odm_bw bw_8822b;
-static u8 central_ch_8822b;
-
-static u32 cca_ifem_ccut[12][4] = {
- /*20M*/
- {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
- {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
- /*40M*/
- {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
- {0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
- {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
- /*80M*/
- {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
- {0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000},
-}; /*Reg83C*/
-static u32 cca_efem_ccut[12][4] = {
- /*20M*/
- {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/
- {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
- {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
- {0x9194b2b9, 0x9194b2b9, 0x9194b2b9, 0x9194b2b9}, /*Reg83C*/
- /*40M*/
- {0x75A85010, 0x75A75010, 0x75A85010, 0x75A75010}, /*Reg82C*/
- {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
- {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
- /*80M*/
- {0x76BA7010, 0x75BA7010, 0x76BA7010, 0x75BA7010}, /*Reg82C*/
- {0x79a0ea28, 0x00000000, 0x79a0ea28, 0x00000000}, /*Reg830*/
- {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000},
-}; /*Reg83C*/
-static u32 cca_ifem_ccut_rfetype5[12][4] = {
- /*20M*/
- {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
- {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
- {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
- /*40M*/
- {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
- {0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
- {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
- /*80M*/
- {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
- {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000},
-}; /*Reg83C*/
-static u32 cca_ifem_ccut_rfetype3[12][4] = {
- /*20M*/
- {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
- {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
- {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
- /*40M*/
- {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
- {0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
- {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
- /*80M*/
- {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
- {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
- {0x00000000, 0x00000000, 0x00000000, 0x00000000},
-}; /*Reg83C*/
-
-static inline u32 phydm_check_bit_mask(u32 bit_mask, u32 data_original,
- u32 data)
-{
- u8 bit_shift;
-
- if (bit_mask != 0xfffff) {
- for (bit_shift = 0; bit_shift <= 19; bit_shift++) {
- if (((bit_mask >> bit_shift) & 0x1) == 1)
- break;
- }
- return ((data_original) & (~bit_mask)) | (data << bit_shift);
- }
- return data;
-}
-
-static bool phydm_rfe_8822b(struct phy_dm_struct *dm, u8 channel)
-{
- if (dm->rfe_type == 4) {
- /* Default setting is in PHY parameters */
-
- if (channel <= 14) {
- /* signal source */
- odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
- 0x745774);
- odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
- 0x745774);
- odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
- odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
-
- /* inverse or not */
- odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
- BIT(2) | BIT(1) | BIT(0)),
- 0x8);
- odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x2);
- odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
- BIT(2) | BIT(1) | BIT(0)),
- 0x8);
- odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x2);
-
- /* antenna switch table */
- if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
- (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
- /* 2TX or 2RX */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf050);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf050);
- } else if (dm->rx_ant_status == dm->tx_ant_status) {
- /* TXA+RXA or TXB+RXB */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf055);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf055);
- } else {
- /* TXB+RXA or TXA+RXB */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf550);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf550);
- }
-
- } else if (channel > 35) {
- /* signal source */
- odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
- 0x477547);
- odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
- 0x477547);
- odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
- odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
-
- /* inverse or not */
- odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
- BIT(2) | BIT(1) | BIT(0)),
- 0x0);
- odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
- odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
- BIT(2) | BIT(1) | BIT(0)),
- 0x0);
- odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
-
- /* antenna switch table */
- if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
- (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
- /* 2TX or 2RX */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
- } else if (dm->rx_ant_status == dm->tx_ant_status) {
- /* TXA+RXA or TXB+RXB */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
- } else {
- /* TXB+RXA or TXA+RXB */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
- }
- } else {
- return false;
- }
-
- } else if ((dm->rfe_type == 1) || (dm->rfe_type == 2) ||
- (dm->rfe_type == 7) || (dm->rfe_type == 9)) {
- /* eFem */
- if (((dm->cut_version == ODM_CUT_A) ||
- (dm->cut_version == ODM_CUT_B)) &&
- (dm->rfe_type < 2)) {
- if (channel <= 14) {
- /* signal source */
- odm_set_bb_reg(dm, 0xcb0,
- (MASKBYTE2 | MASKLWORD),
- 0x704570);
- odm_set_bb_reg(dm, 0xeb0,
- (MASKBYTE2 | MASKLWORD),
- 0x704570);
- odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45);
- odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45);
- } else if (channel > 35) {
- odm_set_bb_reg(dm, 0xcb0,
- (MASKBYTE2 | MASKLWORD),
- 0x174517);
- odm_set_bb_reg(dm, 0xeb0,
- (MASKBYTE2 | MASKLWORD),
- 0x174517);
- odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45);
- odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45);
- } else {
- return false;
- }
-
- /* delay 400ns for PAPE */
- odm_set_bb_reg(dm, 0x810,
- MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) |
- BIT(23),
- 0x211);
-
- /* antenna switch table */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa555);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa555);
-
- /* inverse or not */
- odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
- BIT(2) | BIT(1) | BIT(0)),
- 0x0);
- odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
- odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
- BIT(2) | BIT(1) | BIT(0)),
- 0x0);
- odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
-
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s: Using old RFE control pin setting for A-cut and B-cut\n",
- __func__);
- } else {
- if (channel <= 14) {
- /* signal source */
- odm_set_bb_reg(dm, 0xcb0,
- (MASKBYTE2 | MASKLWORD),
- 0x705770);
- odm_set_bb_reg(dm, 0xeb0,
- (MASKBYTE2 | MASKLWORD),
- 0x705770);
- odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
- odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
- odm_set_bb_reg(dm, 0xcb8, BIT(4), 0);
- odm_set_bb_reg(dm, 0xeb8, BIT(4), 0);
- } else if (channel > 35) {
- /* signal source */
- odm_set_bb_reg(dm, 0xcb0,
- (MASKBYTE2 | MASKLWORD),
- 0x177517);
- odm_set_bb_reg(dm, 0xeb0,
- (MASKBYTE2 | MASKLWORD),
- 0x177517);
- odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
- odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
- odm_set_bb_reg(dm, 0xcb8, BIT(5), 0);
- odm_set_bb_reg(dm, 0xeb8, BIT(5), 0);
- } else {
- return false;
- }
-
- /* inverse or not */
- odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
- BIT(2) | BIT(1) | BIT(0)),
- 0x0);
- odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
- odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
- BIT(2) | BIT(1) | BIT(0)),
- 0x0);
- odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
-
- /* antenna switch table */
- if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
- (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
- /* 2TX or 2RX */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
- } else if (dm->rx_ant_status == dm->tx_ant_status) {
- /* TXA+RXA or TXB+RXB */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
- } else {
- /* TXB+RXA or TXA+RXB */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
- }
- }
- } else if ((dm->rfe_type == 0) || (dm->rfe_type == 3) ||
- (dm->rfe_type == 5) || (dm->rfe_type == 6) ||
- (dm->rfe_type == 8) || (dm->rfe_type == 10)) {
- /* iFEM */
- if (channel <= 14) {
- /* signal source */
-
- odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
- 0x745774);
- odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
- 0x745774);
- odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
- odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
-
- } else if (channel > 35) {
- /* signal source */
-
- odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
- 0x477547);
- odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
- 0x477547);
- odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
- odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
-
- } else {
- return false;
- }
-
- /* inverse or not */
- odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) |
- BIT(1) | BIT(0)),
- 0x0);
- odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
- odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) |
- BIT(1) | BIT(0)),
- 0x0);
- odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
-
- /* antenna switch table */
- if (channel <= 14) {
- if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
- (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
- /* 2TX or 2RX */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
- } else if (dm->rx_ant_status == dm->tx_ant_status) {
- /* TXA+RXA or TXB+RXB */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
- } else {
- /* TXB+RXA or TXA+RXB */
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
- }
- } else if (channel > 35) {
- odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa5a5);
- odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa5a5);
- }
- }
-
- /* chip top mux */
- odm_set_bb_reg(dm, 0x64, BIT(29) | BIT(28), 0x3);
- odm_set_bb_reg(dm, 0x4c, BIT(26) | BIT(25), 0x0);
- odm_set_bb_reg(dm, 0x40, BIT(2), 0x1);
-
- /* from s0 or s1 */
- odm_set_bb_reg(dm, 0x1990,
- (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
- 0x30);
- odm_set_bb_reg(dm, 0x1990, (BIT(11) | BIT(10)), 0x3);
-
- /* input or output */
- odm_set_bb_reg(dm, 0x974,
- (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
- 0x3f);
- odm_set_bb_reg(dm, 0x974, (BIT(11) | BIT(10)), 0x3);
-
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s: Update RFE control pin setting (ch%d, tx_path 0x%x, rx_path 0x%x)\n",
- __func__, channel, dm->tx_ant_status, dm->rx_ant_status);
-
- return true;
-}
-
-static void phydm_ccapar_by_rfe_8822b(struct phy_dm_struct *dm)
-{
- u32 cca_ifem[12][4], cca_efem[12][4];
- u8 row, col;
- u32 reg82c, reg830, reg838, reg83c;
-
- if (dm->cut_version == ODM_CUT_A)
- return;
- {
- odm_move_memory(dm, cca_efem, cca_efem_ccut, 48 * 4);
- if (dm->rfe_type == 5)
- odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfetype5,
- 48 * 4);
- else if (dm->rfe_type == 3)
- odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfetype3,
- 48 * 4);
- else
- odm_move_memory(dm, cca_ifem, cca_ifem_ccut, 48 * 4);
-
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s: Update CCA parameters for Ccut\n", __func__);
- }
-
- if (bw_8822b == ODM_BW20M)
- row = 0;
- else if (bw_8822b == ODM_BW40M)
- row = 4;
- else
- row = 8;
-
- if (central_ch_8822b <= 14) {
- if ((dm->rx_ant_status == ODM_RF_A) ||
- (dm->rx_ant_status == ODM_RF_B))
- col = 0;
- else
- col = 1;
- } else {
- if ((dm->rx_ant_status == ODM_RF_A) ||
- (dm->rx_ant_status == ODM_RF_B))
- col = 2;
- else
- col = 3;
- }
-
- if ((dm->rfe_type == 1) || (dm->rfe_type == 4) || (dm->rfe_type == 6) ||
- (dm->rfe_type == 7)) {
- /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7*/
- reg82c = (cca_efem[row][col] != 0) ? cca_efem[row][col] :
- reg82c_8822b;
- reg830 = (cca_efem[row + 1][col] != 0) ?
- cca_efem[row + 1][col] :
- reg830_8822b;
- reg838 = (cca_efem[row + 2][col] != 0) ?
- cca_efem[row + 2][col] :
- reg838_8822b;
- reg83c = (cca_efem[row + 3][col] != 0) ?
- cca_efem[row + 3][col] :
- reg83c_8822b;
- } else if ((dm->rfe_type == 2) || (dm->rfe_type == 9)) {
- /*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */
- if (central_ch_8822b <= 14) {
- reg82c = (cca_ifem[row][col] != 0) ?
- cca_ifem[row][col] :
- reg82c_8822b;
- reg830 = (cca_ifem[row + 1][col] != 0) ?
- cca_ifem[row + 1][col] :
- reg830_8822b;
- reg838 = (cca_ifem[row + 2][col] != 0) ?
- cca_ifem[row + 2][col] :
- reg838_8822b;
- reg83c = (cca_ifem[row + 3][col] != 0) ?
- cca_ifem[row + 3][col] :
- reg83c_8822b;
- } else {
- reg82c = (cca_efem[row][col] != 0) ?
- cca_efem[row][col] :
- reg82c_8822b;
- reg830 = (cca_efem[row + 1][col] != 0) ?
- cca_efem[row + 1][col] :
- reg830_8822b;
- reg838 = (cca_efem[row + 2][col] != 0) ?
- cca_efem[row + 2][col] :
- reg838_8822b;
- reg83c = (cca_efem[row + 3][col] != 0) ?
- cca_efem[row + 3][col] :
- reg83c_8822b;
- }
- } else {
- /* iFEM =>RFE type 3 & RFE type 5 & RFE type 0 & RFE type 8 &
- * RFE type 10
- */
- reg82c = (cca_ifem[row][col] != 0) ? cca_ifem[row][col] :
- reg82c_8822b;
- reg830 = (cca_ifem[row + 1][col] != 0) ?
- cca_ifem[row + 1][col] :
- reg830_8822b;
- reg838 = (cca_ifem[row + 2][col] != 0) ?
- cca_ifem[row + 2][col] :
- reg838_8822b;
- reg83c = (cca_ifem[row + 3][col] != 0) ?
- cca_ifem[row + 3][col] :
- reg83c_8822b;
- }
-
- odm_set_bb_reg(dm, 0x82c, MASKDWORD, reg82c);
- odm_set_bb_reg(dm, 0x830, MASKDWORD, reg830);
- odm_set_bb_reg(dm, 0x838, MASKDWORD, reg838);
- odm_set_bb_reg(dm, 0x83c, MASKDWORD, reg83c);
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s: (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n",
- __func__, dm->package_type, dm->support_interface,
- dm->rfe_type, row, col);
-}
-
-static void phydm_ccapar_by_bw_8822b(struct phy_dm_struct *dm,
- enum odm_bw bandwidth)
-{
- u32 reg82c;
-
- if (dm->cut_version != ODM_CUT_A)
- return;
-
- /* A-cut */
- reg82c = odm_get_bb_reg(dm, 0x82c, MASKDWORD);
-
- if (bandwidth == ODM_BW20M) {
- /* 82c[15:12] = 4 */
- /* 82c[27:24] = 6 */
-
- reg82c &= (~(0x0f00f000));
- reg82c |= ((0x4) << 12);
- reg82c |= ((0x6) << 24);
- } else if (bandwidth == ODM_BW40M) {
- /* 82c[19:16] = 9 */
- /* 82c[27:24] = 6 */
-
- reg82c &= (~(0x0f0f0000));
- reg82c |= ((0x9) << 16);
- reg82c |= ((0x6) << 24);
- } else if (bandwidth == ODM_BW80M) {
- /* 82c[15:12] 7 */
- /* 82c[19:16] b */
- /* 82c[23:20] d */
- /* 82c[27:24] 3 */
-
- reg82c &= (~(0x0ffff000));
- reg82c |= ((0xdb7) << 12);
- reg82c |= ((0x3) << 24);
- }
-
- odm_set_bb_reg(dm, 0x82c, MASKDWORD, reg82c);
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Update CCA parameters for Acut\n", __func__);
-}
-
-static void phydm_ccapar_by_rxpath_8822b(struct phy_dm_struct *dm)
-{
- if (dm->cut_version != ODM_CUT_A)
- return;
-
- if ((dm->rx_ant_status == ODM_RF_A) ||
- (dm->rx_ant_status == ODM_RF_B)) {
- /* 838[7:4] = 8 */
- /* 838[11:8] = 7 */
- /* 838[15:12] = 6 */
- /* 838[19:16] = 7 */
- /* 838[23:20] = 7 */
- /* 838[27:24] = 7 */
- odm_set_bb_reg(dm, 0x838, 0x0ffffff0, 0x777678);
- } else {
- /* 838[7:4] = 3 */
- /* 838[11:8] = 3 */
- /* 838[15:12] = 6 */
- /* 838[19:16] = 6 */
- /* 838[23:20] = 7 */
- /* 838[27:24] = 7 */
- odm_set_bb_reg(dm, 0x838, 0x0ffffff0, 0x776633);
- }
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Update CCA parameters for Acut\n", __func__);
-}
-
-static void phydm_rxdfirpar_by_bw_8822b(struct phy_dm_struct *dm,
- enum odm_bw bandwidth)
-{
- if (bandwidth == ODM_BW40M) {
- /* RX DFIR for BW40 */
- odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x1);
- odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x0);
- odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0);
- odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0);
- } else if (bandwidth == ODM_BW80M) {
- /* RX DFIR for BW80 */
- odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2);
- odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x1);
- odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0);
- odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0);
- } else {
- /* RX DFIR for BW20, BW10 and BW5*/
- odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2);
- odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x2);
- odm_set_bb_reg(dm, 0xc20, BIT(31), 0x1);
- odm_set_bb_reg(dm, 0xe20, BIT(31), 0x1);
- }
-}
-
-bool phydm_write_txagc_1byte_8822b(struct phy_dm_struct *dm, u32 power_index,
- enum odm_rf_radio_path path, u8 hw_rate)
-{
- u32 offset_txagc[2] = {0x1d00, 0x1d80};
- u8 rate_idx = (hw_rate & 0xfc), i;
- u8 rate_offset = (hw_rate & 0x3);
- u32 txagc_content = 0x0;
-
- /* For debug command only!!!! */
-
- /* Error handling */
- if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): unsupported path (%d)\n", __func__, path);
- return false;
- }
-
- /* For HW limitation, We can't write TXAGC once a byte. */
- for (i = 0; i < 4; i++) {
- if (i != rate_offset)
- txagc_content =
- txagc_content | (config_phydm_read_txagc_8822b(
- dm, path, rate_idx + i)
- << (i << 3));
- else
- txagc_content = txagc_content |
- ((power_index & 0x3f) << (i << 3));
- }
- odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD,
- txagc_content);
-
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
- path, hw_rate, (offset_txagc[path] + hw_rate),
- power_index);
- return true;
-}
-
-void phydm_init_hw_info_by_rfe_type_8822b(struct phy_dm_struct *dm)
-{
- u16 mask_path_a = 0x0303;
- u16 mask_path_b = 0x0c0c;
- /*u16 mask_path_c = 0x3030;*/
- /*u16 mask_path_d = 0xc0c0;*/
-
- dm->is_init_hw_info_by_rfe = false;
-
- if ((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7)) {
- odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
- (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G |
- ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G));
-
- if (dm->rfe_type == 6) {
- odm_cmn_info_init(
- dm, ODM_CMNINFO_GPA,
- (TYPE_GPA1 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(
- dm, ODM_CMNINFO_APA,
- (TYPE_APA1 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(
- dm, ODM_CMNINFO_GLNA,
- (TYPE_GLNA1 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(
- dm, ODM_CMNINFO_ALNA,
- (TYPE_ALNA1 & (mask_path_a | mask_path_b)));
- } else if (dm->rfe_type == 7) {
- odm_cmn_info_init(
- dm, ODM_CMNINFO_GPA,
- (TYPE_GPA2 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(
- dm, ODM_CMNINFO_APA,
- (TYPE_APA2 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(
- dm, ODM_CMNINFO_GLNA,
- (TYPE_GLNA2 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(
- dm, ODM_CMNINFO_ALNA,
- (TYPE_ALNA2 & (mask_path_a | mask_path_b)));
- } else {
- odm_cmn_info_init(
- dm, ODM_CMNINFO_GPA,
- (TYPE_GPA0 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(
- dm, ODM_CMNINFO_APA,
- (TYPE_APA0 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(
- dm, ODM_CMNINFO_GLNA,
- (TYPE_GLNA0 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(
- dm, ODM_CMNINFO_ALNA,
- (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
- }
-
- odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
- } else if (dm->rfe_type == 2) {
- odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
- (ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA_5G));
- odm_cmn_info_init(dm, ODM_CMNINFO_APA,
- (TYPE_APA0 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
- (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
-
- odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
- } else if (dm->rfe_type == 9) {
- odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
- (ODM_BOARD_EXT_LNA_5G));
- odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
- (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
-
- odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
- } else if ((dm->rfe_type == 3) || (dm->rfe_type == 5)) {
- /* RFE type 3: 8822BS\8822BU TFBGA iFEM */
- /* RFE type 5: 8822BE TFBGA iFEM */
- odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
- } else if (dm->rfe_type == 4) {
- odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
- (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G |
- ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G));
- odm_cmn_info_init(dm, ODM_CMNINFO_GPA,
- (TYPE_GPA0 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(dm, ODM_CMNINFO_APA,
- (TYPE_APA0 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(dm, ODM_CMNINFO_GLNA,
- (TYPE_GLNA0 & (mask_path_a | mask_path_b)));
- odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
- (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
-
- odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
- } else if (dm->rfe_type == 8) {
- /* RFE type 8: TFBGA iFEM AP */
- odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
- } else {
- /* RFE Type 0 & 9 & 10: QFN iFEM */
- odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
- }
-
- dm->is_init_hw_info_by_rfe = true;
-
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): RFE type (%d), Board type (0x%x), Package type (%d)\n",
- __func__, dm->rfe_type, dm->board_type, dm->package_type);
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n",
- __func__, dm->ext_pa_5g, dm->ext_lna_5g, dm->ext_pa,
- dm->ext_lna);
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n",
- __func__, dm->type_apa, dm->type_alna, dm->type_gpa,
- dm->type_glna);
-}
-
-s32 phydm_get_condition_number_8822B(struct phy_dm_struct *dm)
-{
- s32 ret_val;
-
- odm_set_bb_reg(dm, 0x1988, BIT(22), 0x1);
- ret_val =
- (s32)odm_get_bb_reg(dm, 0xf84, (BIT(17) | BIT(16) | MASKLWORD));
-
- if (bw_8822b == 0) {
- ret_val = ret_val << (8 - 4);
- ret_val = ret_val / 234;
- } else if (bw_8822b == 1) {
- ret_val = ret_val << (7 - 4);
- ret_val = ret_val / 108;
- } else if (bw_8822b == 2) {
- ret_val = ret_val << (6 - 4);
- ret_val = ret_val / 52;
- }
-
- return ret_val;
-}
-
-/* ======================================================================== */
-
-/* ======================================================================== */
-/* These following functions can be used by driver*/
-
-u32 config_phydm_read_rf_reg_8822b(struct phy_dm_struct *dm,
- enum odm_rf_radio_path rf_path, u32 reg_addr,
- u32 bit_mask)
-{
- u32 readback_value, direct_addr;
- u32 offset_read_rf[2] = {0x2800, 0x2c00};
- u32 power_RF[2] = {0x1c, 0xec};
-
- /* Error handling.*/
- if (rf_path > ODM_RF_PATH_B) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): unsupported path (%d)\n", __func__,
- rf_path);
- return INVALID_RF_DATA;
- }
-
- /* Error handling. Check if RF power is enable or not */
- /* 0xffffffff means RF power is disable */
- if (odm_get_mac_reg(dm, power_RF[rf_path], MASKBYTE3) != 0x7) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Read fail, RF is disabled\n", __func__);
- return INVALID_RF_DATA;
- }
-
- /* Calculate offset */
- reg_addr &= 0xff;
- direct_addr = offset_read_rf[rf_path] + (reg_addr << 2);
-
- /* RF register only has 20bits */
- bit_mask &= RFREGOFFSETMASK;
-
- /* Read RF register directly */
- readback_value = odm_get_bb_reg(dm, direct_addr, bit_mask);
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", __func__,
- rf_path, reg_addr, readback_value, bit_mask);
- return readback_value;
-}
-
-bool config_phydm_write_rf_reg_8822b(struct phy_dm_struct *dm,
- enum odm_rf_radio_path rf_path,
- u32 reg_addr, u32 bit_mask, u32 data)
-{
- u32 data_and_addr = 0, data_original = 0;
- u32 offset_write_rf[2] = {0xc90, 0xe90};
- u32 power_RF[2] = {0x1c, 0xec};
-
- /* Error handling.*/
- if (rf_path > ODM_RF_PATH_B) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): unsupported path (%d)\n", __func__,
- rf_path);
- return false;
- }
-
- /* Read RF register content first */
- reg_addr &= 0xff;
- bit_mask = bit_mask & RFREGOFFSETMASK;
-
- if (bit_mask != RFREGOFFSETMASK) {
- data_original = config_phydm_read_rf_reg_8822b(
- dm, rf_path, reg_addr, RFREGOFFSETMASK);
-
- /* Error handling. RF is disabled */
- if (!config_phydm_read_rf_check_8822b(data_original)) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Write fail, RF is disable\n",
- __func__);
- return false;
- }
-
- /* check bit mask */
- data = phydm_check_bit_mask(bit_mask, data_original, data);
- } else if (odm_get_mac_reg(dm, power_RF[rf_path], MASKBYTE3) != 0x7) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Write fail, RF is disabled\n", __func__);
- return false;
- }
-
- /* Put write addr in [27:20] and write data in [19:00] */
- data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
-
- /* Write operation */
- odm_set_bb_reg(dm, offset_write_rf[rf_path], MASKDWORD, data_and_addr);
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n",
- __func__, rf_path, reg_addr, data, data_original, bit_mask);
- return true;
-}
-
-bool config_phydm_write_txagc_8822b(struct phy_dm_struct *dm, u32 power_index,
- enum odm_rf_radio_path path, u8 hw_rate)
-{
- u32 offset_txagc[2] = {0x1d00, 0x1d80};
- u8 rate_idx = (hw_rate & 0xfc);
-
- /* Input need to be HW rate index, not driver rate index!!!! */
-
- if (dm->is_disable_phy_api) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): disable PHY API for debug!!\n", __func__);
- return true;
- }
-
- /* Error handling */
- if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): unsupported path (%d)\n", __func__, path);
- return false;
- }
-
- /* driver need to construct a 4-byte power index */
- odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD,
- power_index);
-
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
- path, hw_rate, (offset_txagc[path] + hw_rate),
- power_index);
- return true;
-}
-
-u8 config_phydm_read_txagc_8822b(struct phy_dm_struct *dm,
- enum odm_rf_radio_path path, u8 hw_rate)
-{
- u8 read_back_data;
-
- /* Input need to be HW rate index, not driver rate index!!!! */
-
- /* Error handling */
- if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): unsupported path (%d)\n", __func__, path);
- return INVALID_TXAGC_DATA;
- }
-
- /* Disable TX AGC report */
- odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0); /* need to check */
-
- /* Set data rate index (bit0~6) and path index (bit7) */
- odm_set_bb_reg(dm, 0x1998, MASKBYTE0, (hw_rate | (path << 7)));
-
- /* Enable TXAGC report */
- odm_set_bb_reg(dm, 0x1998, BIT(16), 0x1);
-
- /* Read TX AGC report */
- read_back_data = (u8)odm_get_bb_reg(dm, 0xd30, 0x7f0000);
-
- /* Driver have to disable TXAGC report after reading TXAGC
- * (ref. user guide v11)
- */
- odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0);
-
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): path-%d rate index 0x%x = 0x%x\n", __func__, path,
- hw_rate, read_back_data);
- return read_back_data;
-}
-
-bool config_phydm_switch_band_8822b(struct phy_dm_struct *dm, u8 central_ch)
-{
- u32 rf_reg18;
- bool rf_reg_status = true;
-
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()======================>\n",
- __func__);
-
- if (dm->is_disable_phy_api) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): disable PHY API for debug!!\n", __func__);
- return true;
- }
-
- rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
- RFREGOFFSETMASK);
- rf_reg_status =
- rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
-
- if (central_ch <= 14) {
- /* 2.4G */
-
- /* Enable CCK block */
- odm_set_bb_reg(dm, 0x808, BIT(28), 0x1);
-
- /* Disable MAC CCK check */
- odm_set_bb_reg(dm, 0x454, BIT(7), 0x0);
-
- /* Disable BB CCK check */
- odm_set_bb_reg(dm, 0xa80, BIT(18), 0x0);
-
- /*CCA Mask*/
- odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/
-
- /* RF band */
- rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
-
- /* RxHP dynamic control */
- if ((dm->rfe_type == 2) || (dm->rfe_type == 3) ||
- (dm->rfe_type == 5)) {
- odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492);
- odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x29095612);
- }
-
- } else if (central_ch > 35) {
- /* 5G */
-
- /* Enable BB CCK check */
- odm_set_bb_reg(dm, 0xa80, BIT(18), 0x1);
-
- /* Enable CCK check */
- odm_set_bb_reg(dm, 0x454, BIT(7), 0x1);
-
- /* Disable CCK block */
- odm_set_bb_reg(dm, 0x808, BIT(28), 0x0);
-
- /*CCA Mask*/
- odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/
-
- /* RF band */
- rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
- rf_reg18 = (rf_reg18 | BIT(8) | BIT(16));
-
- /* RxHP dynamic control */
- if ((dm->rfe_type == 2) || (dm->rfe_type == 3) ||
- (dm->rfe_type == 5)) {
- odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08100000);
- odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x21095612);
- }
-
- } else {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch band (ch: %d)\n", __func__,
- central_ch);
- return false;
- }
-
- rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x18,
- RFREGOFFSETMASK, rf_reg18);
-
- if (dm->rf_type > ODM_1T1R)
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_B, 0x18,
- RFREGOFFSETMASK, rf_reg18);
-
- if (!phydm_rfe_8822b(dm, central_ch))
- return false;
-
- if (!rf_reg_status) {
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch band (ch: %d), because writing RF register is fail\n",
- __func__, central_ch);
- return false;
- }
-
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Success to switch band (ch: %d)\n", __func__,
- central_ch);
- return true;
-}
-
-bool config_phydm_switch_channel_8822b(struct phy_dm_struct *dm, u8 central_ch)
-{
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- u32 rf_reg18 = 0, rf_reg_b8 = 0, rf_reg_be = 0xff;
- bool rf_reg_status = true;
- u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff,
- 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
- u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff,
- 0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff,
- 0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7};
- u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff,
- 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
-
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()====================>\n",
- __func__);
-
- if (dm->is_disable_phy_api) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): disable PHY API for debug!!\n", __func__);
- return true;
- }
-
- central_ch_8822b = central_ch;
- rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
- RFREGOFFSETMASK);
- rf_reg_status =
- rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
- rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0)));
-
- if (dm->cut_version == ODM_CUT_A) {
- rf_reg_b8 = config_phydm_read_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xb8, RFREGOFFSETMASK);
- rf_reg_status = rf_reg_status &
- config_phydm_read_rf_check_8822b(rf_reg_b8);
- }
-
- /* Switch band and channel */
- if (central_ch <= 14) {
- /* 2.4G */
-
- /* 1. RF band and channel*/
- rf_reg18 = (rf_reg18 | central_ch);
-
- /* 2. AGC table selection */
- odm_set_bb_reg(dm, 0x958, 0x1f, 0x0);
- dig_tab->agc_table_idx = 0x0;
-
- /* 3. Set central frequency for clock offset tracking */
- odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x96a);
-
- /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
- if (dm->cut_version == ODM_CUT_A)
- rf_reg_b8 = rf_reg_b8 | BIT(19);
-
- /* CCK TX filter parameters */
- if (central_ch == 14) {
- odm_set_bb_reg(dm, 0xa20, MASKHWORD, 0x8488);
- odm_set_bb_reg(dm, 0xa24, MASKDWORD, 0x00006577);
- odm_set_bb_reg(dm, 0xa28, MASKLWORD, 0x0000);
- } else {
- odm_set_bb_reg(dm, 0xa20, MASKHWORD,
- (rega20_8822b >> 16));
- odm_set_bb_reg(dm, 0xa24, MASKDWORD, rega24_8822b);
- odm_set_bb_reg(dm, 0xa28, MASKLWORD,
- (rega28_8822b & MASKLWORD));
- }
-
- } else if (central_ch > 35) {
- /* 5G */
-
- /* 1. RF band and channel*/
- rf_reg18 = (rf_reg18 | central_ch);
-
- /* 2. AGC table selection */
- if ((central_ch >= 36) && (central_ch <= 64)) {
- odm_set_bb_reg(dm, 0x958, 0x1f, 0x1);
- dig_tab->agc_table_idx = 0x1;
- } else if ((central_ch >= 100) && (central_ch <= 144)) {
- odm_set_bb_reg(dm, 0x958, 0x1f, 0x2);
- dig_tab->agc_table_idx = 0x2;
- } else if (central_ch >= 149) {
- odm_set_bb_reg(dm, 0x958, 0x1f, 0x3);
- dig_tab->agc_table_idx = 0x3;
- } else {
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch channel (AGC) (ch: %d)\n",
- __func__, central_ch);
- return false;
- }
-
- /* 3. Set central frequency for clock offset tracking */
- if ((central_ch >= 36) && (central_ch <= 48)) {
- odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x494);
- } else if ((central_ch >= 52) && (central_ch <= 64)) {
- odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x453);
- } else if ((central_ch >= 100) && (central_ch <= 116)) {
- odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x452);
- } else if ((central_ch >= 118) && (central_ch <= 177)) {
- odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x412);
- } else {
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch channel (fc_area) (ch: %d)\n",
- __func__, central_ch);
- return false;
- }
-
- /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
- if (dm->cut_version == ODM_CUT_A) {
- if ((central_ch >= 57) && (central_ch <= 75))
- rf_reg_b8 = rf_reg_b8 & (~BIT(19));
- else
- rf_reg_b8 = rf_reg_b8 | BIT(19);
- }
- } else {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch channel (ch: %d)\n",
- __func__, central_ch);
- return false;
- }
-
- /* Modify IGI for MP driver to aviod PCIE interference */
- if (dm->mp_mode && ((dm->rfe_type == 3) || (dm->rfe_type == 5))) {
- if (central_ch == 14)
- odm_write_dig(dm, 0x26);
- else
- odm_write_dig(dm, 0x20);
- }
-
- /* Modify the setting of register 0xBE to reduce phase noise */
- if (central_ch <= 14)
- rf_reg_be = 0x0;
- else if ((central_ch >= 36) && (central_ch <= 64))
- rf_reg_be = low_band[(central_ch - 36) >> 1];
- else if ((central_ch >= 100) && (central_ch <= 144))
- rf_reg_be = middle_band[(central_ch - 100) >> 1];
- else if ((central_ch >= 149) && (central_ch <= 177))
- rf_reg_be = high_band[(central_ch - 149) >> 1];
- else
- rf_reg_be = 0xff;
-
- if (rf_reg_be != 0xff) {
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xbe,
- (BIT(17) | BIT(16) | BIT(15)),
- rf_reg_be);
- } else {
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch channel (ch: %d, Phase noise)\n",
- __func__, central_ch);
- return false;
- }
-
- /* Fix channel 144 issue, ask by RFSI Alvin*/
- /* 00 when freq < 5400; 01 when 5400<=freq<=5720; 10 when freq > 5720;
- * 2G don't care
- */
- /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
- if (central_ch == 144) {
- rf_reg_status = rf_reg_status &
- config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x1);
- rf_reg18 = (rf_reg18 | BIT(17));
- } else {
- rf_reg_status = rf_reg_status &
- config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x0);
-
- if (central_ch > 144)
- rf_reg18 = (rf_reg18 | BIT(18));
- else if (central_ch >= 80)
- rf_reg18 = (rf_reg18 | BIT(17));
- }
-
- rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x18,
- RFREGOFFSETMASK, rf_reg18);
-
- if (dm->cut_version == ODM_CUT_A)
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xb8,
- RFREGOFFSETMASK, rf_reg_b8);
-
- if (dm->rf_type > ODM_1T1R) {
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_B, 0x18,
- RFREGOFFSETMASK, rf_reg18);
-
- if (dm->cut_version == ODM_CUT_A)
- rf_reg_status = rf_reg_status &
- config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_B, 0xb8,
- RFREGOFFSETMASK, rf_reg_b8);
- }
-
- if (!rf_reg_status) {
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch channel (ch: %d), because writing RF register is fail\n",
- __func__, central_ch);
- return false;
- }
-
- phydm_ccapar_by_rfe_8822b(dm);
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Success to switch channel (ch: %d)\n", __func__,
- central_ch);
- return true;
-}
-
-bool config_phydm_switch_bandwidth_8822b(struct phy_dm_struct *dm,
- u8 primary_ch_idx,
- enum odm_bw bandwidth)
-{
- u32 rf_reg18;
- bool rf_reg_status = true;
- u8 IGI = 0;
-
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()===================>\n",
- __func__);
-
- if (dm->is_disable_phy_api) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): disable PHY API for debug!!\n", __func__);
- return true;
- }
-
- /* Error handling */
- if ((bandwidth >= ODM_BW_MAX) ||
- ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) ||
- ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) {
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
- __func__, bandwidth, primary_ch_idx);
- return false;
- }
-
- bw_8822b = bandwidth;
- rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
- RFREGOFFSETMASK);
- rf_reg_status =
- rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
-
- /* Switch bandwidth */
- switch (bandwidth) {
- case ODM_BW20M: {
- /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0,
- * rf mode([1:0]) = 20M
- */
- odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, ODM_BW20M);
-
- /* ADC clock = 160M clock for BW20 */
- odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x0);
- odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x1);
-
- /* DAC clock = 160M clock for BW20 */
- odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x0);
- odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x1);
-
- /* ADC buffer clock */
- odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
-
- /* RF bandwidth */
- rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
-
- break;
- }
- case ODM_BW40M: {
- /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel,
- * rf mode([1:0]) = 40M
- */
- odm_set_bb_reg(dm, 0x8ac, MASKBYTE0,
- (((primary_ch_idx & 0xf) << 2) | ODM_BW40M));
-
- /* CCK primary channel */
- if (primary_ch_idx == 1)
- odm_set_bb_reg(dm, 0xa00, BIT(4), primary_ch_idx);
- else
- odm_set_bb_reg(dm, 0xa00, BIT(4), 0);
-
- /* ADC clock = 160M clock for BW40 */
- odm_set_bb_reg(dm, 0x8ac, (BIT(11) | BIT(10)), 0x0);
- odm_set_bb_reg(dm, 0x8ac, BIT(17), 0x1);
-
- /* DAC clock = 160M clock for BW20 */
- odm_set_bb_reg(dm, 0x8ac, (BIT(23) | BIT(22)), 0x0);
- odm_set_bb_reg(dm, 0x8ac, BIT(29), 0x1);
-
- /* ADC buffer clock */
- odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
-
- /* RF bandwidth */
- rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
- rf_reg18 = (rf_reg18 | BIT(11));
-
- break;
- }
- case ODM_BW80M: {
- /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel,
- * rf mode([1:0]) = 80M
- */
- odm_set_bb_reg(dm, 0x8ac, MASKBYTE0,
- (((primary_ch_idx & 0xf) << 2) | ODM_BW80M));
-
- /* ADC clock = 160M clock for BW80 */
- odm_set_bb_reg(dm, 0x8ac, (BIT(13) | BIT(12)), 0x0);
- odm_set_bb_reg(dm, 0x8ac, BIT(18), 0x1);
-
- /* DAC clock = 160M clock for BW20 */
- odm_set_bb_reg(dm, 0x8ac, (BIT(25) | BIT(24)), 0x0);
- odm_set_bb_reg(dm, 0x8ac, BIT(30), 0x1);
-
- /* ADC buffer clock */
- odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
-
- /* RF bandwidth */
- rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
- rf_reg18 = (rf_reg18 | BIT(10));
-
- break;
- }
- case ODM_BW5M: {
- /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0,
- * rf mode([1:0]) = 20M
- */
- odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(6) | ODM_BW20M));
-
- /* ADC clock = 40M clock */
- odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x2);
- odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);
-
- /* DAC clock = 160M clock for BW20 */
- odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x2);
- odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);
-
- /* ADC buffer clock */
- odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0);
- odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1);
-
- /* RF bandwidth */
- rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
-
- break;
- }
- case ODM_BW10M: {
- /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0,
- * rf mode([1:0]) = 20M
- */
- odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(7) | ODM_BW20M));
-
- /* ADC clock = 80M clock */
- odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x3);
- odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);
-
- /* DAC clock = 160M clock for BW20 */
- odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x3);
- odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);
-
- /* ADC buffer clock */
- odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0);
- odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1);
-
- /* RF bandwidth */
- rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
-
- break;
- }
- default:
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
- __func__, bandwidth, primary_ch_idx);
- }
-
- /* Write RF register */
- rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x18,
- RFREGOFFSETMASK, rf_reg18);
-
- if (dm->rf_type > ODM_1T1R)
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_B, 0x18,
- RFREGOFFSETMASK, rf_reg18);
-
- if (!rf_reg_status) {
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n",
- __func__, bandwidth, primary_ch_idx);
- return false;
- }
-
- /* Modify RX DFIR parameters */
- phydm_rxdfirpar_by_bw_8822b(dm, bandwidth);
-
- /* Modify CCA parameters */
- phydm_ccapar_by_bw_8822b(dm, bandwidth);
- phydm_ccapar_by_rfe_8822b(dm);
-
- /* Toggle RX path to avoid RX dead zone issue */
- odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x0);
- odm_set_bb_reg(dm, 0x808, MASKBYTE0,
- (dm->rx_ant_status | (dm->rx_ant_status << 4)));
-
- /* Toggle IGI to let RF enter RX mode */
- IGI = (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
- odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), IGI - 2);
- odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), IGI - 2);
- odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), IGI);
- odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), IGI);
-
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Success to switch bandwidth (bw: %d, primary ch: %d)\n",
- __func__, bandwidth, primary_ch_idx);
- return true;
-}
-
-bool config_phydm_switch_channel_bw_8822b(struct phy_dm_struct *dm,
- u8 central_ch, u8 primary_ch_idx,
- enum odm_bw bandwidth)
-{
- /* Switch band */
- if (!config_phydm_switch_band_8822b(dm, central_ch))
- return false;
-
- /* Switch channel */
- if (!config_phydm_switch_channel_8822b(dm, central_ch))
- return false;
-
- /* Switch bandwidth */
- if (!config_phydm_switch_bandwidth_8822b(dm, primary_ch_idx, bandwidth))
- return false;
-
- return true;
-}
-
-bool config_phydm_trx_mode_8822b(struct phy_dm_struct *dm,
- enum odm_rf_path tx_path,
- enum odm_rf_path rx_path, bool is_tx2_path)
-{
- bool rf_reg_status = true;
- u8 IGI;
- u32 rf_reg33 = 0;
- u16 counter = 0;
-
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()=====================>\n",
- __func__);
-
- if (dm->is_disable_phy_api) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): disable PHY API for debug!!\n", __func__);
- return true;
- }
-
- if ((tx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Wrong TX setting (TX: 0x%x)\n", __func__,
- tx_path);
- return false;
- }
-
- if ((rx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Wrong RX setting (RX: 0x%x)\n", __func__,
- rx_path);
- return false;
- }
-
- /* RF mode of path-A and path-B */
- /* Cannot shut down path-A, beacause synthesizer will be shut down when
- * path-A is in shut down mode
- */
- if ((tx_path | rx_path) & ODM_RF_A)
- odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x3231);
- else
- odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x1111);
-
- if ((tx_path | rx_path) & ODM_RF_B)
- odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x3231);
- else
- odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x1111);
-
- /* Set TX antenna by Nsts */
- odm_set_bb_reg(dm, 0x93c, (BIT(19) | BIT(18)), 0x3);
- odm_set_bb_reg(dm, 0x80c, (BIT(29) | BIT(28)), 0x1);
-
- /* Control CCK TX path by 0xa07[7] */
- odm_set_bb_reg(dm, 0x80c, BIT(30), 0x1);
-
- /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/
- if (tx_path & ODM_RF_A) {
- odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x001);
- odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8);
- } else if (tx_path & ODM_RF_B) {
- odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x002);
- odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4);
- }
-
- /* TX logic map and TX path en for Nsts = 2*/
- if ((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))
- odm_set_bb_reg(dm, 0x940, 0xfff0, 0x01);
- else
- odm_set_bb_reg(dm, 0x940, 0xfff0, 0x43);
-
- /* TX path enable */
- odm_set_bb_reg(dm, 0x80c, MASKBYTE0, ((tx_path << 4) | tx_path));
-
- /* Tx2path for 1ss */
- if (!((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))) {
- if (is_tx2_path || dm->mp_mode) {
- /* 2Tx for OFDM */
- odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x043);
-
- /* 2Tx for CCK */
- odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc);
- }
- }
-
- /* Always disable MRC for CCK CCA */
- odm_set_bb_reg(dm, 0xa2c, BIT(22), 0x0);
-
- /* Always disable MRC for CCK barker */
- odm_set_bb_reg(dm, 0xa2c, BIT(18), 0x0);
-
- /* CCK RX 1st and 2nd path setting*/
- if (rx_path & ODM_RF_A)
- odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0);
- else if (rx_path & ODM_RF_B)
- odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x5);
-
- /* RX path enable */
- odm_set_bb_reg(dm, 0x808, MASKBYTE0, ((rx_path << 4) | rx_path));
-
- if ((rx_path == ODM_RF_A) || (rx_path == ODM_RF_B)) {
- /* 1R */
-
- /* Disable MRC for CCA */
- /* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x0); */
-
- /* Disable MRC for barker */
- /* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x0); */
-
- /* Disable CCK antenna diversity */
- /* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */
-
- /* Disable Antenna weighting */
- odm_set_bb_reg(dm, 0x1904, BIT(16), 0x0);
- odm_set_bb_reg(dm, 0x800, BIT(28), 0x0);
- odm_set_bb_reg(dm, 0x850, BIT(23), 0x0);
- } else {
- /* 2R */
-
- /* Enable MRC for CCA */
- /* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x1); */
-
- /* Enable MRC for barker */
- /* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x1); */
-
- /* Disable CCK antenna diversity */
- /* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */
-
- /* Enable Antenna weighting */
- odm_set_bb_reg(dm, 0x1904, BIT(16), 0x1);
- odm_set_bb_reg(dm, 0x800, BIT(28), 0x1);
- odm_set_bb_reg(dm, 0x850, BIT(23), 0x1);
- }
-
- /* Update TXRX antenna status for PHYDM */
- dm->tx_ant_status = (tx_path & 0x3);
- dm->rx_ant_status = (rx_path & 0x3);
-
- /* MP driver need to support path-B TX\RX */
-
- while (1) {
- counter++;
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xef,
- RFREGOFFSETMASK, 0x80000);
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x33,
- RFREGOFFSETMASK, 0x00001);
-
- ODM_delay_us(2);
- rf_reg33 = config_phydm_read_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK);
-
- if ((rf_reg33 == 0x00001) &&
- (config_phydm_read_rf_check_8822b(rf_reg33)))
- break;
- else if (counter == 100) {
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to set TRx mode setting, because writing RF mode table is fail\n",
- __func__);
- return false;
- }
- }
-
- if ((dm->mp_mode) || *dm->antenna_test || (dm->normal_rx_path)) {
- /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e
- * 0xef 0x00000 suggested by Lucas
- */
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xef,
- RFREGOFFSETMASK, 0x80000);
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x33,
- RFREGOFFSETMASK, 0x00001);
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x3e,
- RFREGOFFSETMASK, 0x00034);
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x3f,
- RFREGOFFSETMASK, 0x4080e);
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xef,
- RFREGOFFSETMASK, 0x00000);
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): MP mode or Antenna test mode!! support path-B TX and RX\n",
- __func__);
- } else {
- /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080c
- * 0xef 0x00000
- */
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xef,
- RFREGOFFSETMASK, 0x80000);
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x33,
- RFREGOFFSETMASK, 0x00001);
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x3e,
- RFREGOFFSETMASK, 0x00034);
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0x3f,
- RFREGOFFSETMASK, 0x4080c);
- rf_reg_status =
- rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xef,
- RFREGOFFSETMASK, 0x00000);
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Normal mode!! Do not support path-B TX and RX\n",
- __func__);
- }
-
- rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
- dm, ODM_RF_PATH_A, 0xef,
- RFREGOFFSETMASK, 0x00000);
-
- if (!rf_reg_status) {
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n",
- __func__, tx_path, rx_path);
- return false;
- }
-
- /* Toggle IGI to let RF enter RX mode,
- * because BB doesn't send 3-wire command when RX path is enable
- */
- IGI = (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
- odm_write_dig(dm, IGI - 2);
- odm_write_dig(dm, IGI);
-
- /* Modify CCA parameters */
- phydm_ccapar_by_rxpath_8822b(dm);
- phydm_ccapar_by_rfe_8822b(dm);
- phydm_rfe_8822b(dm, central_ch_8822b);
-
- ODM_RT_TRACE(
- dm, ODM_PHY_CONFIG,
- "%s(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n",
- __func__, tx_path, rx_path);
- return true;
-}
-
-bool config_phydm_parameter_init(struct phy_dm_struct *dm,
- enum odm_parameter_init type)
-{
- if (type == ODM_PRE_SETTING) {
- odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x0);
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Pre setting: disable OFDM and CCK block\n",
- __func__);
- } else if (type == ODM_POST_SETTING) {
- odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x3);
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
- "%s(): Post setting: enable OFDM and CCK block\n",
- __func__);
- reg82c_8822b = odm_get_bb_reg(dm, 0x82c, MASKDWORD);
- reg838_8822b = odm_get_bb_reg(dm, 0x838, MASKDWORD);
- reg830_8822b = odm_get_bb_reg(dm, 0x830, MASKDWORD);
- reg83c_8822b = odm_get_bb_reg(dm, 0x83c, MASKDWORD);
- rega20_8822b = odm_get_bb_reg(dm, 0xa20, MASKDWORD);
- rega24_8822b = odm_get_bb_reg(dm, 0xa24, MASKDWORD);
- rega28_8822b = odm_get_bb_reg(dm, 0xa28, MASKDWORD);
- } else {
- ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s(): Wrong type!!\n",
- __func__);
- return false;
- }
-
- return true;
-}
-
-/* ======================================================================== */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __INC_PHYDM_API_H_8822B__
-#define __INC_PHYDM_API_H_8822B__
-
-/*2016.08.01 (HW user guide version: R27, SW user guide version: R05,
- * Modification: R31)
- */
-#define PHY_CONFIG_VERSION_8822B "27.5.31"
-
-#define INVALID_RF_DATA 0xffffffff
-#define INVALID_TXAGC_DATA 0xff
-
-#define config_phydm_read_rf_check_8822b(data) (data != INVALID_RF_DATA)
-#define config_phydm_read_txagc_check_8822b(data) (data != INVALID_TXAGC_DATA)
-
-u32 config_phydm_read_rf_reg_8822b(struct phy_dm_struct *dm,
- enum odm_rf_radio_path rf_path, u32 reg_addr,
- u32 bit_mask);
-
-bool config_phydm_write_rf_reg_8822b(struct phy_dm_struct *dm,
- enum odm_rf_radio_path rf_path,
- u32 reg_addr, u32 bit_mask, u32 data);
-
-bool config_phydm_write_txagc_8822b(struct phy_dm_struct *dm, u32 power_index,
- enum odm_rf_radio_path path, u8 hw_rate);
-
-u8 config_phydm_read_txagc_8822b(struct phy_dm_struct *dm,
- enum odm_rf_radio_path path, u8 hw_rate);
-
-bool config_phydm_switch_band_8822b(struct phy_dm_struct *dm, u8 central_ch);
-
-bool config_phydm_switch_channel_8822b(struct phy_dm_struct *dm, u8 central_ch);
-
-bool config_phydm_switch_bandwidth_8822b(struct phy_dm_struct *dm,
- u8 primary_ch_idx,
- enum odm_bw bandwidth);
-
-bool config_phydm_switch_channel_bw_8822b(struct phy_dm_struct *dm,
- u8 central_ch, u8 primary_ch_idx,
- enum odm_bw bandwidth);
-
-bool config_phydm_trx_mode_8822b(struct phy_dm_struct *dm,
- enum odm_rf_path tx_path,
- enum odm_rf_path rx_path, bool is_tx2_path);
-
-bool config_phydm_parameter_init(struct phy_dm_struct *dm,
- enum odm_parameter_init type);
-
-/* ======================================================================== */
-/* These following functions can be used for PHY DM only*/
-
-bool phydm_write_txagc_1byte_8822b(struct phy_dm_struct *dm, u32 power_index,
- enum odm_rf_radio_path path, u8 hw_rate);
-
-void phydm_init_hw_info_by_rfe_type_8822b(struct phy_dm_struct *dm);
-
-s32 phydm_get_condition_number_8822B(struct phy_dm_struct *dm);
-
-/* ======================================================================== */
-
-#endif /* __INC_PHYDM_API_H_8822B__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../mp_precomp.h"
-#include "../phydm_precomp.h"
-
-/*---------------------------Define Local Constant---------------------------*/
-
-static bool _iqk_rx_iqk_by_path_8822b(void *, u8);
-
-static inline void phydm_set_iqk_info(struct phy_dm_struct *dm,
- struct dm_iqk_info *iqk_info, u8 status)
-{
- bool KFAIL = true;
-
- while (1) {
- KFAIL = _iqk_rx_iqk_by_path_8822b(dm, ODM_RF_PATH_A);
- if (status == 0)
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S0RXK KFail = 0x%x\n", KFAIL);
- else if (status == 1)
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S1RXK KFail = 0x%x\n", KFAIL);
- if (iqk_info->rxiqk_step == 5) {
- dm->rf_calibrate_info.iqk_step++;
- iqk_info->rxiqk_step = 1;
- if (KFAIL && status == 0)
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S0RXK fail code: %d!!!\n",
- iqk_info->rxiqk_fail_code
- [0][ODM_RF_PATH_A]);
- else if (KFAIL && status == 1)
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S1RXK fail code: %d!!!\n",
- iqk_info->rxiqk_fail_code
- [0][ODM_RF_PATH_A]);
- break;
- }
- }
-
- iqk_info->kcount++;
-}
-
-static inline void phydm_init_iqk_information(struct dm_iqk_info *iqk_info)
-{
- u8 i, j, k, m;
-
- for (i = 0; i < 2; i++) {
- iqk_info->iqk_channel[i] = 0x0;
-
- for (j = 0; j < SS_8822B; j++) {
- iqk_info->lok_idac[i][j] = 0x0;
- iqk_info->rxiqk_agc[i][j] = 0x0;
- iqk_info->bypass_iqk[i][j] = 0x0;
-
- for (k = 0; k < 2; k++) {
- iqk_info->iqk_fail_report[i][j][k] = true;
- for (m = 0; m < 8; m++) {
- iqk_info->iqk_cfir_real[i][j][k][m] =
- 0x0;
- iqk_info->iqk_cfir_imag[i][j][k][m] =
- 0x0;
- }
- }
-
- for (k = 0; k < 3; k++)
- iqk_info->retry_count[i][j][k] = 0x0;
- }
- }
-}
-
-static inline void phydm_backup_iqk_information(struct dm_iqk_info *iqk_info)
-{
- u8 i, j, k;
-
- iqk_info->iqk_channel[1] = iqk_info->iqk_channel[0];
- for (i = 0; i < 2; i++) {
- iqk_info->lok_idac[1][i] = iqk_info->lok_idac[0][i];
- iqk_info->rxiqk_agc[1][i] = iqk_info->rxiqk_agc[0][i];
- iqk_info->bypass_iqk[1][i] = iqk_info->bypass_iqk[0][i];
- iqk_info->rxiqk_fail_code[1][i] =
- iqk_info->rxiqk_fail_code[0][i];
- for (j = 0; j < 2; j++) {
- iqk_info->iqk_fail_report[1][i][j] =
- iqk_info->iqk_fail_report[0][i][j];
- for (k = 0; k < 8; k++) {
- iqk_info->iqk_cfir_real[1][i][j][k] =
- iqk_info->iqk_cfir_real[0][i][j][k];
- iqk_info->iqk_cfir_imag[1][i][j][k] =
- iqk_info->iqk_cfir_imag[0][i][j][k];
- }
- }
- }
-
- for (i = 0; i < 4; i++) {
- iqk_info->rxiqk_fail_code[0][i] = 0x0;
- iqk_info->rxiqk_agc[0][i] = 0x0;
- for (j = 0; j < 2; j++) {
- iqk_info->iqk_fail_report[0][i][j] = true;
- iqk_info->gs_retry_count[0][i][j] = 0x0;
- }
- for (j = 0; j < 3; j++)
- iqk_info->retry_count[0][i][j] = 0x0;
- }
-}
-
-static inline void phydm_set_iqk_cfir(struct phy_dm_struct *dm,
- struct dm_iqk_info *iqk_info, u8 path)
-{
- u8 idx, i;
- u32 tmp;
-
- for (idx = 0; idx < 2; idx++) {
- odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1);
-
- if (idx == 0)
- odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3);
- else
- odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1);
-
- odm_set_bb_reg(dm, 0x1bd4,
- BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16),
- 0x10);
-
- for (i = 0; i < 8; i++) {
- odm_set_bb_reg(dm, 0x1bd8, MASKDWORD,
- 0xe0000001 + (i * 4));
- tmp = odm_get_bb_reg(dm, 0x1bfc, MASKDWORD);
- iqk_info->iqk_cfir_real[0][path][idx][i] =
- (tmp & 0x0fff0000) >> 16;
- iqk_info->iqk_cfir_imag[0][path][idx][i] = tmp & 0xfff;
- }
- }
-}
-
-static inline void phydm_get_read_counter(struct phy_dm_struct *dm)
-{
- u32 counter = 0x0;
-
- while (1) {
- if (((odm_read_4byte(dm, 0x1bf0) >> 24) == 0x7f) ||
- (counter > 300))
- break;
-
- counter++;
- ODM_delay_ms(1);
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]counter = %d\n", counter);
-}
-
-/*---------------------------Define Local Constant---------------------------*/
-
-void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
- u8 threshold)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- odm_reset_iqk_result(dm);
-
- dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
-
- phy_iq_calibrate_8822b(dm, true);
-}
-
-static void _iqk_fill_iqk_report_8822b(void *dm_void, u8 channel)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0;
- u8 i;
-
- for (i = 0; i < SS_8822B; i++) {
- tmp1 = tmp1 +
- ((iqk_info->iqk_fail_report[channel][i][TX_IQK] & 0x1)
- << i);
- tmp2 = tmp2 +
- ((iqk_info->iqk_fail_report[channel][i][RX_IQK] & 0x1)
- << (i + 4));
- tmp3 = tmp3 + ((iqk_info->rxiqk_fail_code[channel][i] & 0x3)
- << (i * 2 + 8));
- }
- odm_write_4byte(dm, 0x1b00, 0xf8000008);
- odm_set_bb_reg(dm, 0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3);
-
- for (i = 0; i < 2; i++)
- odm_write_4byte(
- dm, 0x1be8 + (i * 4),
- (iqk_info->rxiqk_agc[channel][(i * 2) + 1] << 16) |
- iqk_info->rxiqk_agc[channel][i * 2]);
-}
-
-static void _iqk_backup_mac_bb_8822b(struct phy_dm_struct *dm, u32 *MAC_backup,
- u32 *BB_backup, u32 *backup_mac_reg,
- u32 *backup_bb_reg)
-{
- u32 i;
-
- for (i = 0; i < MAC_REG_NUM_8822B; i++)
- MAC_backup[i] = odm_read_4byte(dm, backup_mac_reg[i]);
-
- for (i = 0; i < BB_REG_NUM_8822B; i++)
- BB_backup[i] = odm_read_4byte(dm, backup_bb_reg[i]);
-}
-
-static void _iqk_backup_rf_8822b(struct phy_dm_struct *dm, u32 RF_backup[][2],
- u32 *backup_rf_reg)
-{
- u32 i;
-
- for (i = 0; i < RF_REG_NUM_8822B; i++) {
- RF_backup[i][ODM_RF_PATH_A] = odm_get_rf_reg(
- dm, ODM_RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK);
- RF_backup[i][ODM_RF_PATH_B] = odm_get_rf_reg(
- dm, ODM_RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK);
- }
-}
-
-static void _iqk_agc_bnd_int_8822b(struct phy_dm_struct *dm)
-{
- /*initialize RX AGC bnd, it must do after bbreset*/
- odm_write_4byte(dm, 0x1b00, 0xf8000008);
- odm_write_4byte(dm, 0x1b00, 0xf80a7008);
- odm_write_4byte(dm, 0x1b00, 0xf8015008);
- odm_write_4byte(dm, 0x1b00, 0xf8000008);
-}
-
-static void _iqk_bb_reset_8822b(struct phy_dm_struct *dm)
-{
- bool cca_ing = false;
- u32 count = 0;
-
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);
-
- while (1) {
- odm_write_4byte(dm, 0x8fc, 0x0);
- odm_set_bb_reg(dm, 0x198c, 0x7, 0x7);
- cca_ing = (bool)odm_get_bb_reg(dm, 0xfa0, BIT(3));
-
- if (count > 30)
- cca_ing = false;
-
- if (cca_ing) {
- ODM_delay_ms(1);
- count++;
- } else {
- odm_write_1byte(dm, 0x808, 0x0); /*RX ant off*/
- odm_set_bb_reg(dm, 0xa04,
- BIT(27) | BIT(26) | BIT(25) | BIT(24),
- 0x0); /*CCK RX path off*/
-
- /*BBreset*/
- odm_set_bb_reg(dm, 0x0, BIT(16), 0x0);
- odm_set_bb_reg(dm, 0x0, BIT(16), 0x1);
-
- if (odm_get_bb_reg(dm, 0x660, BIT(16)))
- odm_write_4byte(dm, 0x6b4, 0x89000006);
- break;
- }
- }
-}
-
-static void _iqk_afe_setting_8822b(struct phy_dm_struct *dm, bool do_iqk)
-{
- if (do_iqk) {
- odm_write_4byte(dm, 0xc60, 0x50000000);
- odm_write_4byte(dm, 0xc60, 0x70070040);
- odm_write_4byte(dm, 0xe60, 0x50000000);
- odm_write_4byte(dm, 0xe60, 0x70070040);
-
- odm_write_4byte(dm, 0xc58, 0xd8000402);
- odm_write_4byte(dm, 0xc5c, 0xd1000120);
- odm_write_4byte(dm, 0xc6c, 0x00000a15);
- odm_write_4byte(dm, 0xe58, 0xd8000402);
- odm_write_4byte(dm, 0xe5c, 0xd1000120);
- odm_write_4byte(dm, 0xe6c, 0x00000a15);
- _iqk_bb_reset_8822b(dm);
- } else {
- odm_write_4byte(dm, 0xc60, 0x50000000);
- odm_write_4byte(dm, 0xc60, 0x70038040);
- odm_write_4byte(dm, 0xe60, 0x50000000);
- odm_write_4byte(dm, 0xe60, 0x70038040);
-
- odm_write_4byte(dm, 0xc58, 0xd8020402);
- odm_write_4byte(dm, 0xc5c, 0xde000120);
- odm_write_4byte(dm, 0xc6c, 0x0000122a);
- odm_write_4byte(dm, 0xe58, 0xd8020402);
- odm_write_4byte(dm, 0xe5c, 0xde000120);
- odm_write_4byte(dm, 0xe6c, 0x0000122a);
- }
-}
-
-static void _iqk_restore_mac_bb_8822b(struct phy_dm_struct *dm, u32 *MAC_backup,
- u32 *BB_backup, u32 *backup_mac_reg,
- u32 *backup_bb_reg)
-{
- u32 i;
-
- for (i = 0; i < MAC_REG_NUM_8822B; i++)
- odm_write_4byte(dm, backup_mac_reg[i], MAC_backup[i]);
- for (i = 0; i < BB_REG_NUM_8822B; i++)
- odm_write_4byte(dm, backup_bb_reg[i], BB_backup[i]);
-}
-
-static void _iqk_restore_rf_8822b(struct phy_dm_struct *dm, u32 *backup_rf_reg,
- u32 RF_backup[][2])
-{
- u32 i;
-
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x0);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, RFREGOFFSETMASK, 0x0);
- /*0xdf[4]=0*/
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK,
- RF_backup[0][ODM_RF_PATH_A] & (~BIT(4)));
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xdf, RFREGOFFSETMASK,
- RF_backup[0][ODM_RF_PATH_B] & (~BIT(4)));
-
- for (i = 1; i < RF_REG_NUM_8822B; i++) {
- odm_set_rf_reg(dm, ODM_RF_PATH_A, backup_rf_reg[i],
- RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_A]);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, backup_rf_reg[i],
- RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_B]);
- }
-}
-
-static void _iqk_backup_iqk_8822b(struct phy_dm_struct *dm, u8 step)
-{
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- u8 path;
- u16 iqk_apply[2] = {0xc94, 0xe94};
-
- if (step == 0x0) {
- phydm_backup_iqk_information(iqk_info);
- } else {
- iqk_info->iqk_channel[0] = iqk_info->rf_reg18;
- for (path = 0; path < 2; path++) {
- iqk_info->lok_idac[0][path] =
- odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
- 0x58, RFREGOFFSETMASK);
- iqk_info->bypass_iqk[0][path] =
- odm_get_bb_reg(dm, iqk_apply[path], MASKDWORD);
-
- phydm_set_iqk_cfir(dm, iqk_info, path);
- odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);
- odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0);
- }
- }
-}
-
-static void _iqk_reload_iqk_setting_8822b(
- struct phy_dm_struct *dm, u8 channel,
- u8 reload_idx /*1: reload TX, 2: reload LO, TX, RX*/
- )
-{
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- u8 i, path, idx;
- u16 iqk_apply[2] = {0xc94, 0xe94};
-
- for (path = 0; path < 2; path++) {
- if (reload_idx == 2) {
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xdf,
- BIT(4), 0x1);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x58,
- RFREGOFFSETMASK,
- iqk_info->lok_idac[channel][path]);
- }
-
- for (idx = 0; idx < reload_idx; idx++) {
- odm_set_bb_reg(dm, 0x1b00, MASKDWORD,
- 0xf8000008 | path << 1);
- odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x7);
- odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000);
- odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000);
- odm_set_bb_reg(dm, 0x1bcc, MASKDWORD, 0x00000000);
-
- if (idx == 0)
- odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12),
- 0x3);
- else
- odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12),
- 0x1);
-
- odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) |
- BIT(17) | BIT(16),
- 0x10);
-
- for (i = 0; i < 8; i++) {
- odm_write_4byte(
- dm, 0x1bd8,
- ((0xc0000000 >> idx) + 0x3) + (i * 4) +
- (iqk_info->iqk_cfir_real
- [channel][path][idx][i]
- << 9));
- odm_write_4byte(
- dm, 0x1bd8,
- ((0xc0000000 >> idx) + 0x1) + (i * 4) +
- (iqk_info->iqk_cfir_imag
- [channel][path][idx][i]
- << 9));
- }
- }
- odm_set_bb_reg(dm, iqk_apply[path], MASKDWORD,
- iqk_info->bypass_iqk[channel][path]);
-
- odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);
- odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0);
- }
-}
-
-static bool _iqk_reload_iqk_8822b(struct phy_dm_struct *dm, bool reset)
-{
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- u8 i;
- bool reload = false;
-
- if (reset) {
- for (i = 0; i < 2; i++)
- iqk_info->iqk_channel[i] = 0x0;
- } else {
- iqk_info->rf_reg18 = odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18,
- RFREGOFFSETMASK);
-
- for (i = 0; i < 2; i++) {
- if (iqk_info->rf_reg18 == iqk_info->iqk_channel[i]) {
- _iqk_reload_iqk_setting_8822b(dm, i, 2);
- _iqk_fill_iqk_report_8822b(dm, i);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]reload IQK result before!!!!\n");
- reload = true;
- }
- }
- }
- return reload;
-}
-
-static void _iqk_rfe_setting_8822b(struct phy_dm_struct *dm, bool ext_pa_on)
-{
- if (ext_pa_on) {
- /*RFE setting*/
- odm_write_4byte(dm, 0xcb0, 0x77777777);
- odm_write_4byte(dm, 0xcb4, 0x00007777);
- odm_write_4byte(dm, 0xcbc, 0x0000083B);
- odm_write_4byte(dm, 0xeb0, 0x77777777);
- odm_write_4byte(dm, 0xeb4, 0x00007777);
- odm_write_4byte(dm, 0xebc, 0x0000083B);
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]external PA on!!!!\n");
- } else {
- /*RFE setting*/
- odm_write_4byte(dm, 0xcb0, 0x77777777);
- odm_write_4byte(dm, 0xcb4, 0x00007777);
- odm_write_4byte(dm, 0xcbc, 0x00000100);
- odm_write_4byte(dm, 0xeb0, 0x77777777);
- odm_write_4byte(dm, 0xeb4, 0x00007777);
- odm_write_4byte(dm, 0xebc, 0x00000100);
- }
-}
-
-static void _iqk_rf_setting_8822b(struct phy_dm_struct *dm)
-{
- u8 path;
- u32 tmp;
-
- odm_write_4byte(dm, 0x1b00, 0xf8000008);
- odm_write_4byte(dm, 0x1bb8, 0x00000000);
-
- for (path = 0; path < 2; path++) {
- /*0xdf:B11 = 1,B4 = 0, B1 = 1*/
- tmp = odm_get_rf_reg(dm, (enum odm_rf_radio_path)path, 0xdf,
- RFREGOFFSETMASK);
- tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xdf,
- RFREGOFFSETMASK, tmp);
-
- /*release 0x56 TXBB*/
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x65,
- RFREGOFFSETMASK, 0x09000);
-
- if (*dm->band_type == ODM_BAND_5G) {
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef,
- BIT(19), 0x1);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x33,
- RFREGOFFSETMASK, 0x00026);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x3e,
- RFREGOFFSETMASK, 0x00037);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x3f,
- RFREGOFFSETMASK, 0xdefce);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef,
- BIT(19), 0x0);
- } else {
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef,
- BIT(19), 0x1);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x33,
- RFREGOFFSETMASK, 0x00026);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x3e,
- RFREGOFFSETMASK, 0x00037);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x3f,
- RFREGOFFSETMASK, 0x5efce);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef,
- BIT(19), 0x0);
- }
- }
-}
-
-static void _iqk_configure_macbb_8822b(struct phy_dm_struct *dm)
-{
- /*MACBB register setting*/
- odm_write_1byte(dm, 0x522, 0x7f);
- odm_set_bb_reg(dm, 0x550, BIT(11) | BIT(3), 0x0);
- odm_set_bb_reg(dm, 0x90c, BIT(15),
- 0x1); /*0x90c[15]=1: dac_buf reset selection*/
- odm_set_bb_reg(dm, 0x9a4, BIT(31),
- 0x0); /*0x9a4[31]=0: Select da clock*/
- /*0xc94[0]=1, 0xe94[0]=1: let tx through iqk*/
- odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1);
- odm_set_bb_reg(dm, 0xe94, BIT(0), 0x1);
- /* 3-wire off*/
- odm_write_4byte(dm, 0xc00, 0x00000004);
- odm_write_4byte(dm, 0xe00, 0x00000004);
-}
-
-static void _iqk_lok_setting_8822b(struct phy_dm_struct *dm, u8 path)
-{
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
- odm_write_4byte(dm, 0x1bcc, 0x9);
- odm_write_1byte(dm, 0x1b23, 0x00);
-
- switch (*dm->band_type) {
- case ODM_BAND_2_4G:
- odm_write_1byte(dm, 0x1b2b, 0x00);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
- RFREGOFFSETMASK, 0x50df2);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
- RFREGOFFSETMASK, 0xadc00);
- /* WE_LUT_TX_LOK*/
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef, BIT(4),
- 0x1);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x33,
- BIT(1) | BIT(0), 0x0);
- break;
- case ODM_BAND_5G:
- odm_write_1byte(dm, 0x1b2b, 0x80);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
- RFREGOFFSETMASK, 0x5086c);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
- RFREGOFFSETMASK, 0xa9c00);
- /* WE_LUT_TX_LOK*/
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0xef, BIT(4),
- 0x1);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x33,
- BIT(1) | BIT(0), 0x1);
- break;
- }
-}
-
-static void _iqk_txk_setting_8822b(struct phy_dm_struct *dm, u8 path)
-{
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
- odm_write_4byte(dm, 0x1bcc, 0x9);
- odm_write_4byte(dm, 0x1b20, 0x01440008);
-
- if (path == 0x0)
- odm_write_4byte(dm, 0x1b00, 0xf800000a);
- else
- odm_write_4byte(dm, 0x1b00, 0xf8000008);
- odm_write_4byte(dm, 0x1bcc, 0x3f);
-
- switch (*dm->band_type) {
- case ODM_BAND_2_4G:
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
- RFREGOFFSETMASK, 0x50df2);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
- RFREGOFFSETMASK, 0xadc00);
- odm_write_1byte(dm, 0x1b2b, 0x00);
- break;
- case ODM_BAND_5G:
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
- RFREGOFFSETMASK, 0x500ef);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
- RFREGOFFSETMASK, 0xa9c00);
- odm_write_1byte(dm, 0x1b2b, 0x80);
- break;
- }
-}
-
-static void _iqk_rxk1_setting_8822b(struct phy_dm_struct *dm, u8 path)
-{
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
-
- switch (*dm->band_type) {
- case ODM_BAND_2_4G:
- odm_write_1byte(dm, 0x1bcc, 0x9);
- odm_write_1byte(dm, 0x1b2b, 0x00);
- odm_write_4byte(dm, 0x1b20, 0x01450008);
- odm_write_4byte(dm, 0x1b24, 0x01460c88);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
- RFREGOFFSETMASK, 0x510e0);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
- RFREGOFFSETMASK, 0xacc00);
- break;
- case ODM_BAND_5G:
- odm_write_1byte(dm, 0x1bcc, 0x09);
- odm_write_1byte(dm, 0x1b2b, 0x80);
- odm_write_4byte(dm, 0x1b20, 0x00850008);
- odm_write_4byte(dm, 0x1b24, 0x00460048);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
- RFREGOFFSETMASK, 0x510e0);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
- RFREGOFFSETMASK, 0xadc00);
- break;
- }
-}
-
-static void _iqk_rxk2_setting_8822b(struct phy_dm_struct *dm, u8 path,
- bool is_gs)
-{
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
-
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
-
- switch (*dm->band_type) {
- case ODM_BAND_2_4G:
- if (is_gs)
- iqk_info->tmp1bcc = 0x12;
- odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
- odm_write_1byte(dm, 0x1b2b, 0x00);
- odm_write_4byte(dm, 0x1b20, 0x01450008);
- odm_write_4byte(dm, 0x1b24, 0x01460848);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
- RFREGOFFSETMASK, 0x510e0);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
- RFREGOFFSETMASK, 0xa9c00);
- break;
- case ODM_BAND_5G:
- if (is_gs) {
- if (path == ODM_RF_PATH_A)
- iqk_info->tmp1bcc = 0x12;
- else
- iqk_info->tmp1bcc = 0x09;
- }
- odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
- odm_write_1byte(dm, 0x1b2b, 0x80);
- odm_write_4byte(dm, 0x1b20, 0x00850008);
- odm_write_4byte(dm, 0x1b24, 0x00460848);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x56,
- RFREGOFFSETMASK, 0x51060);
- odm_set_rf_reg(dm, (enum odm_rf_radio_path)path, 0x8f,
- RFREGOFFSETMASK, 0xa9c00);
- break;
- }
-}
-
-static bool _iqk_check_cal_8822b(struct phy_dm_struct *dm, u32 IQK_CMD)
-{
- bool notready = true, fail = true;
- u32 delay_count = 0x0;
-
- while (notready) {
- if (odm_read_4byte(dm, 0x1b00) == (IQK_CMD & 0xffffff0f)) {
- fail = (bool)odm_get_bb_reg(dm, 0x1b08, BIT(26));
- notready = false;
- } else {
- ODM_delay_ms(1);
- delay_count++;
- }
-
- if (delay_count >= 50) {
- fail = true;
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]IQK timeout!!!\n");
- break;
- }
- }
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]delay count = 0x%x!!!\n",
- delay_count);
- return fail;
-}
-
-static bool _iqk_rx_iqk_gain_search_fail_8822b(struct phy_dm_struct *dm,
- u8 path, u8 step)
-{
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- bool fail = true;
- u32 IQK_CMD = 0x0, rf_reg0, tmp, bb_idx;
- u8 IQMUX[4] = {0x9, 0x12, 0x1b, 0x24};
- u8 idx;
-
- for (idx = 0; idx < 4; idx++)
- if (iqk_info->tmp1bcc == IQMUX[idx])
- break;
-
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
- odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc);
-
- if (step == RXIQK1)
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]============ S%d RXIQK GainSearch ============\n",
- path);
-
- if (step == RXIQK1)
- IQK_CMD = 0xf8000208 | (1 << (path + 4));
- else
- IQK_CMD = 0xf8000308 | (1 << (path + 4));
-
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]S%d GS%d_Trigger = 0x%x\n",
- path, step, IQK_CMD);
-
- odm_write_4byte(dm, 0x1b00, IQK_CMD);
- odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
- ODM_delay_ms(GS_delay_8822B);
- fail = _iqk_check_cal_8822b(dm, IQK_CMD);
-
- if (step == RXIQK2) {
- rf_reg0 = odm_get_rf_reg(dm, (enum odm_rf_radio_path)path, 0x0,
- RFREGOFFSETMASK);
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n",
- path, rf_reg0, iqk_info->tmp1bcc, idx,
- odm_read_4byte(dm, 0x1b3c));
- tmp = (rf_reg0 & 0x1fe0) >> 5;
- iqk_info->lna_idx = tmp >> 5;
- bb_idx = tmp & 0x1f;
- if (bb_idx == 0x1) {
- if (iqk_info->lna_idx != 0x0)
- iqk_info->lna_idx--;
- else if (idx != 3)
- idx++;
- else
- iqk_info->isbnd = true;
- fail = true;
- } else if (bb_idx == 0xa) {
- if (idx != 0)
- idx--;
- else if (iqk_info->lna_idx != 0x7)
- iqk_info->lna_idx++;
- else
- iqk_info->isbnd = true;
- fail = true;
- } else {
- fail = false;
- }
-
- if (iqk_info->isbnd)
- fail = false;
-
- iqk_info->tmp1bcc = IQMUX[idx];
-
- if (fail) {
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
- odm_write_4byte(
- dm, 0x1b24,
- (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) |
- (iqk_info->lna_idx << 10));
- }
- }
-
- return fail;
-}
-
-static bool _lok_one_shot_8822b(void *dm_void, u8 path)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- u8 delay_count = 0;
- bool LOK_notready = false;
- u32 LOK_temp = 0;
- u32 IQK_CMD = 0x0;
-
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]==========S%d LOK ==========\n", path);
-
- IQK_CMD = 0xf8000008 | (1 << (4 + path));
-
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]LOK_Trigger = 0x%x\n",
- IQK_CMD);
-
- odm_write_4byte(dm, 0x1b00, IQK_CMD);
- odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
- /*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/
- /*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/
- ODM_delay_ms(LOK_delay_8822B);
-
- delay_count = 0;
- LOK_notready = true;
-
- while (LOK_notready) {
- if (odm_read_4byte(dm, 0x1b00) == (IQK_CMD & 0xffffff0f))
- LOK_notready = false;
- else
- LOK_notready = true;
-
- if (LOK_notready) {
- ODM_delay_ms(1);
- delay_count++;
- }
-
- if (delay_count >= 50) {
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S%d LOK timeout!!!\n", path);
- break;
- }
- }
-
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count);
- if (ODM_COMP_CALIBRATION) {
- if (!LOK_notready) {
- LOK_temp =
- odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
- 0x58, RFREGOFFSETMASK);
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]0x58 = 0x%x\n", LOK_temp);
- } else {
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]==>S%d LOK Fail!!!\n", path);
- }
- }
- iqk_info->lok_fail[path] = LOK_notready;
- return LOK_notready;
-}
-
-static bool _iqk_one_shot_8822b(void *dm_void, u8 path, u8 idx)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- u8 delay_count = 0;
- bool notready = true, fail = true;
- u32 IQK_CMD = 0x0;
- u16 iqk_apply[2] = {0xc94, 0xe94};
-
- if (idx == TXIQK)
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]============ S%d WBTXIQK ============\n",
- path);
- else if (idx == RXIQK1)
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]============ S%d WBRXIQK STEP1============\n",
- path);
- else
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]============ S%d WBRXIQK STEP2============\n",
- path);
-
- if (idx == TXIQK) {
- IQK_CMD = 0xf8000008 | ((*dm->band_width + 4) << 8) |
- (1 << (path + 4));
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]TXK_Trigger = 0x%x\n", IQK_CMD);
- /*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/
- /*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/
- /*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/
- } else if (idx == RXIQK1) {
- if (*dm->band_width == 2)
- IQK_CMD = 0xf8000808 | (1 << (path + 4));
- else
- IQK_CMD = 0xf8000708 | (1 << (path + 4));
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD);
- /*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/
- /*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/
- /*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/
- } else if (idx == RXIQK2) {
- IQK_CMD = 0xf8000008 | ((*dm->band_width + 9) << 8) |
- (1 << (path + 4));
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD);
- /*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/
- /*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/
- /*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
- odm_write_4byte(dm, 0x1b24,
- (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) |
- ((iqk_info->lna_idx & 0x7) << 10));
- }
- odm_write_4byte(dm, 0x1b00, IQK_CMD);
- odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
- ODM_delay_ms(WBIQK_delay_8822B);
-
- while (notready) {
- if (odm_read_4byte(dm, 0x1b00) == (IQK_CMD & 0xffffff0f))
- notready = false;
- else
- notready = true;
-
- if (notready) {
- ODM_delay_ms(1);
- delay_count++;
- } else {
- fail = (bool)odm_get_bb_reg(dm, 0x1b08, BIT(26));
- break;
- }
-
- if (delay_count >= 50) {
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S%d IQK timeout!!!\n", path);
- break;
- }
- }
-
- if (dm->debug_components & ODM_COMP_CALIBRATION) {
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n",
- path, odm_read_4byte(dm, 0x1b00),
- odm_read_4byte(dm, 0x1b08));
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S%d ==> delay_count = 0x%x\n", path,
- delay_count);
- if (idx != TXIQK)
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]S%d ==> RF0x0 = 0x%x, RF0x56 = 0x%x\n",
- path,
- odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
- 0x0, RFREGOFFSETMASK),
- odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
- 0x56, RFREGOFFSETMASK));
- }
-
- odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
-
- if (idx == TXIQK)
- if (fail)
- odm_set_bb_reg(dm, iqk_apply[path], BIT(0), 0x0);
-
- if (idx == RXIQK2) {
- iqk_info->rxiqk_agc[0][path] =
- (u16)(((odm_get_rf_reg(dm, (enum odm_rf_radio_path)path,
- 0x0, RFREGOFFSETMASK) >>
- 5) &
- 0xff) |
- (iqk_info->tmp1bcc << 8));
-
- odm_write_4byte(dm, 0x1b38, 0x20000000);
-
- if (!fail)
- odm_set_bb_reg(dm, iqk_apply[path], (BIT(11) | BIT(10)),
- 0x1);
- else
- odm_set_bb_reg(dm, iqk_apply[path], (BIT(11) | BIT(10)),
- 0x0);
- }
-
- if (idx == TXIQK)
- iqk_info->iqk_fail_report[0][path][TXIQK] = fail;
- else
- iqk_info->iqk_fail_report[0][path][RXIQK] = fail;
-
- return fail;
-}
-
-static bool _iqk_rx_iqk_by_path_8822b(void *dm_void, u8 path)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- bool KFAIL = true, gonext;
-
- switch (iqk_info->rxiqk_step) {
- case 1: /*gain search_RXK1*/
- _iqk_rxk1_setting_8822b(dm, path);
- gonext = false;
- while (1) {
- KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(dm, path,
- RXIQK1);
- if (KFAIL &&
- (iqk_info->gs_retry_count[0][path][GSRXK1] < 2))
- iqk_info->gs_retry_count[0][path][GSRXK1]++;
- else if (KFAIL) {
- iqk_info->rxiqk_fail_code[0][path] = 0;
- iqk_info->rxiqk_step = 5;
- gonext = true;
- } else {
- iqk_info->rxiqk_step++;
- gonext = true;
- }
- if (gonext)
- break;
- }
- break;
- case 2: /*gain search_RXK2*/
- _iqk_rxk2_setting_8822b(dm, path, true);
- iqk_info->isbnd = false;
- while (1) {
- KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(dm, path,
- RXIQK2);
- if (KFAIL &&
- (iqk_info->gs_retry_count[0][path][GSRXK2] <
- rxiqk_gs_limit)) {
- iqk_info->gs_retry_count[0][path][GSRXK2]++;
- } else {
- iqk_info->rxiqk_step++;
- break;
- }
- }
- break;
- case 3: /*RXK1*/
- _iqk_rxk1_setting_8822b(dm, path);
- gonext = false;
- while (1) {
- KFAIL = _iqk_one_shot_8822b(dm, path, RXIQK1);
- if (KFAIL &&
- (iqk_info->retry_count[0][path][RXIQK1] < 2))
- iqk_info->retry_count[0][path][RXIQK1]++;
- else if (KFAIL) {
- iqk_info->rxiqk_fail_code[0][path] = 1;
- iqk_info->rxiqk_step = 5;
- gonext = true;
- } else {
- iqk_info->rxiqk_step++;
- gonext = true;
- }
- if (gonext)
- break;
- }
- break;
- case 4: /*RXK2*/
- _iqk_rxk2_setting_8822b(dm, path, false);
- gonext = false;
- while (1) {
- KFAIL = _iqk_one_shot_8822b(dm, path, RXIQK2);
- if (KFAIL &&
- (iqk_info->retry_count[0][path][RXIQK2] < 2))
- iqk_info->retry_count[0][path][RXIQK2]++;
- else if (KFAIL) {
- iqk_info->rxiqk_fail_code[0][path] = 2;
- iqk_info->rxiqk_step = 5;
- gonext = true;
- } else {
- iqk_info->rxiqk_step++;
- gonext = true;
- }
- if (gonext)
- break;
- }
- break;
- }
- return KFAIL;
-}
-
-static void _iqk_iqk_by_path_8822b(void *dm_void, bool segment_iqk)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- bool KFAIL = true;
- u8 i, kcount_limit;
-
- if (*dm->band_width == 2)
- kcount_limit = kcount_limit_80m;
- else
- kcount_limit = kcount_limit_others;
-
- while (1) {
- switch (dm->rf_calibrate_info.iqk_step) {
- case 1: /*S0 LOK*/
- _iqk_lok_setting_8822b(dm, ODM_RF_PATH_A);
- _lok_one_shot_8822b(dm, ODM_RF_PATH_A);
- dm->rf_calibrate_info.iqk_step++;
- break;
- case 2: /*S1 LOK*/
- _iqk_lok_setting_8822b(dm, ODM_RF_PATH_B);
- _lok_one_shot_8822b(dm, ODM_RF_PATH_B);
- dm->rf_calibrate_info.iqk_step++;
- break;
- case 3: /*S0 TXIQK*/
- _iqk_txk_setting_8822b(dm, ODM_RF_PATH_A);
- KFAIL = _iqk_one_shot_8822b(dm, ODM_RF_PATH_A, TXIQK);
- iqk_info->kcount++;
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S0TXK KFail = 0x%x\n", KFAIL);
-
- if (KFAIL &&
- (iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK] <
- 3))
- iqk_info->retry_count[0][ODM_RF_PATH_A]
- [TXIQK]++;
- else
- dm->rf_calibrate_info.iqk_step++;
- break;
- case 4: /*S1 TXIQK*/
- _iqk_txk_setting_8822b(dm, ODM_RF_PATH_B);
- KFAIL = _iqk_one_shot_8822b(dm, ODM_RF_PATH_B, TXIQK);
- iqk_info->kcount++;
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]S1TXK KFail = 0x%x\n", KFAIL);
- if (KFAIL &&
- iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK] < 3)
- iqk_info->retry_count[0][ODM_RF_PATH_B]
- [TXIQK]++;
- else
- dm->rf_calibrate_info.iqk_step++;
- break;
- case 5: /*S0 RXIQK*/
- phydm_set_iqk_info(dm, iqk_info, 0);
- break;
- case 6: /*S1 RXIQK*/
- phydm_set_iqk_info(dm, iqk_info, 1);
- break;
- }
-
- if (dm->rf_calibrate_info.iqk_step == 7) {
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]==========LOK summary ==========\n");
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]PathA_LOK_notready = %d, PathB_LOK1_notready = %d\n",
- iqk_info->lok_fail[ODM_RF_PATH_A],
- iqk_info->lok_fail[ODM_RF_PATH_B]);
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]==========IQK summary ==========\n");
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]PathA_TXIQK_fail = %d, PathB_TXIQK_fail = %d\n",
- iqk_info->iqk_fail_report[0][ODM_RF_PATH_A]
- [TXIQK],
- iqk_info->iqk_fail_report[0][ODM_RF_PATH_B]
- [TXIQK]);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]PathA_RXIQK_fail = %d, PathB_RXIQK_fail = %d\n",
- iqk_info->iqk_fail_report[0][ODM_RF_PATH_A]
- [RXIQK],
- iqk_info->iqk_fail_report[0][ODM_RF_PATH_B]
- [RXIQK]);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]PathA_TXIQK_retry = %d, PathB_TXIQK_retry = %d\n",
- iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK],
- iqk_info->retry_count[0][ODM_RF_PATH_B][TXIQK]);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d, PathB_RXK1_retry = %d, PathB_RXK2_retry = %d\n",
- iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK1],
- iqk_info->retry_count[0][ODM_RF_PATH_A][RXIQK2],
- iqk_info->retry_count[0][ODM_RF_PATH_B][RXIQK1],
- iqk_info->retry_count[0][ODM_RF_PATH_B]
- [RXIQK2]);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d, PathB_GS1_retry = %d, PathB_GS2_retry = %d\n",
- iqk_info->gs_retry_count[0][ODM_RF_PATH_A]
- [GSRXK1],
- iqk_info->gs_retry_count[0][ODM_RF_PATH_A]
- [GSRXK2],
- iqk_info->gs_retry_count[0][ODM_RF_PATH_B]
- [GSRXK1],
- iqk_info->gs_retry_count[0][ODM_RF_PATH_B]
- [GSRXK2]);
- for (i = 0; i < 2; i++) {
- odm_write_4byte(dm, 0x1b00,
- 0xf8000008 | i << 1);
- odm_write_4byte(dm, 0x1b2c, 0x7);
- odm_write_4byte(dm, 0x1bcc, 0x0);
- }
- break;
- }
-
- if (segment_iqk && (iqk_info->kcount == kcount_limit))
- break;
- }
-}
-
-static void _iqk_start_iqk_8822b(struct phy_dm_struct *dm, bool segment_iqk)
-{
- u32 tmp;
-
- /*GNT_WL = 1*/
- tmp = odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK);
- tmp = tmp | BIT(5) | BIT(0);
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK, tmp);
-
- tmp = odm_get_rf_reg(dm, ODM_RF_PATH_B, 0x1, RFREGOFFSETMASK);
- tmp = tmp | BIT(5) | BIT(0);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x1, RFREGOFFSETMASK, tmp);
-
- _iqk_iqk_by_path_8822b(dm, segment_iqk);
-}
-
-static void _iq_calibrate_8822b_init(void *dm_void)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
- u8 i, j;
-
- if (iqk_info->iqk_times == 0) {
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]=====>PHY_IQCalibrate_8822B_Init\n");
-
- for (i = 0; i < SS_8822B; i++) {
- for (j = 0; j < 2; j++) {
- iqk_info->lok_fail[i] = true;
- iqk_info->iqk_fail[j][i] = true;
- iqk_info->iqc_matrix[j][i] = 0x20000000;
- }
- }
-
- phydm_init_iqk_information(iqk_info);
- }
-}
-
-static void _phy_iq_calibrate_8822b(struct phy_dm_struct *dm, bool reset)
-{
- u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B],
- RF_backup[RF_REG_NUM_8822B][SS_8822B];
- u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550};
- u32 backup_bb_reg[BB_REG_NUM_8822B] = {
- 0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00,
- 0xeb0, 0xeb4, 0xebc, 0x1990, 0x9a4, 0xa04};
- u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1};
- bool segment_iqk = false, is_mp = false;
-
- struct dm_iqk_info *iqk_info = &dm->IQK_info;
-
- if (dm->mp_mode)
- is_mp = true;
- else if (dm->is_linked)
- segment_iqk = true;
-
- if (!is_mp)
- if (_iqk_reload_iqk_8822b(dm, reset))
- return;
-
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]==========IQK strat!!!!!==========\n");
-
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n",
- (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width,
- dm->ext_pa, dm->ext_pa_5g);
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]Interface = %d, cut_version = %x\n",
- dm->support_interface, dm->cut_version);
-
- iqk_info->iqk_times++;
-
- iqk_info->kcount = 0;
- dm->rf_calibrate_info.iqk_total_progressing_time = 0;
- dm->rf_calibrate_info.iqk_step = 1;
- iqk_info->rxiqk_step = 1;
-
- _iqk_backup_iqk_8822b(dm, 0);
- _iqk_backup_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg,
- backup_bb_reg);
- _iqk_backup_rf_8822b(dm, RF_backup, backup_rf_reg);
-
- while (1) {
- if (!is_mp)
- dm->rf_calibrate_info.iqk_start_time =
- odm_get_current_time(dm);
-
- _iqk_configure_macbb_8822b(dm);
- _iqk_afe_setting_8822b(dm, true);
- _iqk_rfe_setting_8822b(dm, false);
- _iqk_agc_bnd_int_8822b(dm);
- _iqk_rf_setting_8822b(dm);
-
- _iqk_start_iqk_8822b(dm, segment_iqk);
-
- _iqk_afe_setting_8822b(dm, false);
- _iqk_restore_mac_bb_8822b(dm, MAC_backup, BB_backup,
- backup_mac_reg, backup_bb_reg);
- _iqk_restore_rf_8822b(dm, backup_rf_reg, RF_backup);
-
- if (!is_mp) {
- dm->rf_calibrate_info.iqk_progressing_time =
- odm_get_progressing_time(
- dm,
- dm->rf_calibrate_info.iqk_start_time);
- dm->rf_calibrate_info.iqk_total_progressing_time +=
- odm_get_progressing_time(
- dm,
- dm->rf_calibrate_info.iqk_start_time);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]IQK progressing_time = %lld ms\n",
- dm->rf_calibrate_info.iqk_progressing_time);
- }
-
- if (dm->rf_calibrate_info.iqk_step == 7)
- break;
-
- iqk_info->kcount = 0;
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION, "[IQK]delay 50ms!!!\n");
- ODM_delay_ms(50);
- }
-
- _iqk_backup_iqk_8822b(dm, 1);
- _iqk_fill_iqk_report_8822b(dm, 0);
-
- if (!is_mp)
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]Total IQK progressing_time = %lld ms\n",
- dm->rf_calibrate_info.iqk_total_progressing_time);
-
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]==========IQK end!!!!!==========\n");
-}
-
-static void _phy_iq_calibrate_by_fw_8822b(void *dm_void, u8 clear) {}
-
-/*IQK version:v3.3, NCTL v0.6*/
-/*1.The new gainsearch method for RXIQK*/
-/*2.The new format of IQK report register: 0x1be8/0x1bec*/
-/*3. add the option of segment IQK*/
-void phy_iq_calibrate_8822b(void *dm_void, bool clear)
-{
- struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
-
- dm->iqk_fw_offload = 0;
-
- /*FW IQK*/
- if (dm->iqk_fw_offload) {
- if (!dm->rf_calibrate_info.is_iqk_in_progress) {
- odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
- dm->rf_calibrate_info.is_iqk_in_progress = true;
- odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-
- dm->rf_calibrate_info.iqk_start_time =
- odm_get_current_time(dm);
-
- odm_write_4byte(dm, 0x1b00, 0xf8000008);
- odm_set_bb_reg(dm, 0x1bf0, 0xff000000, 0xff);
- ODM_RT_TRACE(dm, ODM_COMP_CALIBRATION,
- "[IQK]0x1bf0 = 0x%x\n",
- odm_read_4byte(dm, 0x1bf0));
-
- _phy_iq_calibrate_by_fw_8822b(dm, clear);
- phydm_get_read_counter(dm);
-
- dm->rf_calibrate_info.iqk_progressing_time =
- odm_get_progressing_time(
- dm,
- dm->rf_calibrate_info.iqk_start_time);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]IQK progressing_time = %lld ms\n",
- dm->rf_calibrate_info.iqk_progressing_time);
-
- odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
- dm->rf_calibrate_info.is_iqk_in_progress = false;
- odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "== Return the IQK CMD, because the IQK in Progress ==\n");
- }
-
- } else {
- _iq_calibrate_8822b_init(dm_void);
-
- if (!dm->rf_calibrate_info.is_iqk_in_progress) {
- odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
- dm->rf_calibrate_info.is_iqk_in_progress = true;
- odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
- if (dm->mp_mode)
- dm->rf_calibrate_info.iqk_start_time =
- odm_get_current_time(dm);
-
- _phy_iq_calibrate_8822b(dm, clear);
- if (dm->mp_mode) {
- dm->rf_calibrate_info.iqk_progressing_time =
- odm_get_progressing_time(
- dm, dm->rf_calibrate_info
- .iqk_start_time);
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]IQK progressing_time = %lld ms\n",
- dm->rf_calibrate_info
- .iqk_progressing_time);
- }
- odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
- dm->rf_calibrate_info.is_iqk_in_progress = false;
- odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
- } else {
- ODM_RT_TRACE(
- dm, ODM_COMP_CALIBRATION,
- "[IQK]== Return the IQK CMD, because the IQK in Progress ==\n");
- }
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __PHYDM_IQK_8822B_H__
-#define __PHYDM_IQK_8822B_H__
-
-/*--------------------------Define Parameters-------------------------------*/
-#define MAC_REG_NUM_8822B 2
-#define BB_REG_NUM_8822B 13
-#define RF_REG_NUM_8822B 5
-
-#define LOK_delay_8822B 2
-#define GS_delay_8822B 2
-#define WBIQK_delay_8822B 2
-
-#define TXIQK 0
-#define RXIQK 1
-#define SS_8822B 2
-
-/*------------------------End Define Parameters-------------------------------*/
-
-void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
- u8 threshold);
-
-void phy_iq_calibrate_8822b(void *dm_void, bool clear);
-
-#endif /* #ifndef __PHYDM_IQK_8822B_H__*/
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../mp_precomp.h"
-#include "../phydm_precomp.h"
-
-void odm_config_rf_reg_8822b(struct phy_dm_struct *dm, u32 addr, u32 data,
- enum odm_rf_radio_path RF_PATH, u32 reg_addr)
-{
- if (addr == 0xffe) {
- ODM_sleep_ms(50);
- } else if (addr == 0xfe) {
- ODM_delay_us(100);
- } else {
- odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
-
- /* Add 1us delay between BB/RF register setting. */
- ODM_delay_us(1);
- }
-}
-
-void odm_config_rf_radio_a_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
-{
- u32 content = 0x1000; /* RF_Content: radioa_txt */
- u32 maskfor_phy_set = (u32)(content & 0xE000);
-
- odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_A,
- addr | maskfor_phy_set);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
- addr, data);
-}
-
-void odm_config_rf_radio_b_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
-{
- u32 content = 0x1001; /* RF_Content: radiob_txt */
- u32 maskfor_phy_set = (u32)(content & 0xE000);
-
- odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_B,
- addr | maskfor_phy_set);
-
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
- addr, data);
-}
-
-void odm_config_mac_8822b(struct phy_dm_struct *dm, u32 addr, u8 data)
-{
- odm_write_1byte(dm, addr, data);
- ODM_RT_TRACE(
- dm, ODM_COMP_INIT,
- "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
- addr, data);
-}
-
-void odm_update_agc_big_jump_lmt_8822b(struct phy_dm_struct *dm, u32 addr,
- u32 data)
-{
- struct dig_thres *dig_tab = &dm->dm_dig_table;
- u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);
- u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);
- u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);
- static bool is_limit;
-
- if (addr != 0x81c)
- return;
-
- if (bb_gain_idx > 0x3c) {
- if ((rf_gain_idx == dig_tab->rf_gain_idx) && !is_limit) {
- is_limit = true;
- dig_tab->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;
- ODM_RT_TRACE(
- dm, ODM_COMP_DIG,
- "===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n",
- agc_table_idx,
- dig_tab->big_jump_lmt[agc_table_idx]);
- }
- } else {
- is_limit = false;
- }
-
- dig_tab->rf_gain_idx = rf_gain_idx;
-}
-
-void odm_config_bb_agc_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
- u32 data)
-{
- odm_update_agc_big_jump_lmt_8822b(dm, addr, data);
-
- odm_set_bb_reg(dm, addr, bitmask, data);
-
- /* Add 1us delay between BB/RF register setting. */
- ODM_delay_us(1);
-
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [AGC_TAB] %08X %08X\n",
- __func__, addr, data);
-}
-
-void odm_config_bb_phy_reg_pg_8822b(struct phy_dm_struct *dm, u32 band,
- u32 rf_path, u32 tx_num, u32 addr,
- u32 bitmask, u32 data)
-{
- if (addr == 0xfe || addr == 0xffe) {
- ODM_sleep_ms(50);
- } else {
- phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num,
- addr, bitmask, data);
- }
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X %08X\n",
- __func__, addr, bitmask, data);
-}
-
-void odm_config_bb_phy_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
- u32 data)
-{
- if (addr == 0xfe)
- ODM_sleep_ms(50);
- else if (addr == 0xfd)
- ODM_delay_ms(5);
- else if (addr == 0xfc)
- ODM_delay_ms(1);
- else if (addr == 0xfb)
- ODM_delay_us(50);
- else if (addr == 0xfa)
- ODM_delay_us(5);
- else if (addr == 0xf9)
- ODM_delay_us(1);
- else
- odm_set_bb_reg(dm, addr, bitmask, data);
-
- /* Add 1us delay between BB/RF register setting. */
- ODM_delay_us(1);
- ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X\n",
- __func__, addr, data);
-}
-
-void odm_config_bb_txpwr_lmt_8822b(struct phy_dm_struct *dm, u8 *regulation,
- u8 *band, u8 *bandwidth, u8 *rate_section,
- u8 *rf_path, u8 *channel, u8 *power_limit)
-{
- phy_set_tx_power_limit(dm, regulation, band, bandwidth, rate_section,
- rf_path, channel, power_limit);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __INC_ODM_REGCONFIG_H_8822B
-#define __INC_ODM_REGCONFIG_H_8822B
-
-void odm_config_rf_reg_8822b(struct phy_dm_struct *dm, u32 addr, u32 data,
- enum odm_rf_radio_path RF_PATH, u32 reg_addr);
-
-void odm_config_rf_radio_a_8822b(struct phy_dm_struct *dm, u32 addr, u32 data);
-
-void odm_config_rf_radio_b_8822b(struct phy_dm_struct *dm, u32 addr, u32 data);
-
-void odm_config_mac_8822b(struct phy_dm_struct *dm, u32 addr, u8 data);
-
-void odm_update_agc_big_jump_lmt_8822b(struct phy_dm_struct *dm, u32 addr,
- u32 data);
-
-void odm_config_bb_agc_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
- u32 data);
-
-void odm_config_bb_phy_reg_pg_8822b(struct phy_dm_struct *dm, u32 band,
- u32 rf_path, u32 tx_num, u32 addr,
- u32 bitmask, u32 data);
-
-void odm_config_bb_phy_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
- u32 data);
-
-void odm_config_bb_txpwr_lmt_8822b(struct phy_dm_struct *dm, u8 *regulation,
- u8 *band, u8 *bandwidth, u8 *rate_section,
- u8 *rf_path, u8 *channel, u8 *power_limit);
-
-#endif /* RTL8822B_SUPPORT == 1*/
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../mp_precomp.h"
-#include "../phydm_precomp.h"
-
-static void phydm_dynamic_switch_htstf_mumimo_8822b(struct phy_dm_struct *dm)
-{
- /*if rssi > 40dBm, enable HT-STF gain controller,
- *otherwise, if rssi < 40dBm, disable the controller
- */
- /*add by Chun-Hung Ho 20160711 */
- if (dm->rssi_min >= 40)
- odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x1);
- else if (dm->rssi_min < 35)
- odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0);
-
- ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s, rssi_min = %d\n", __func__,
- dm->rssi_min);
-}
-
-static void _set_tx_a_cali_value(struct phy_dm_struct *dm, u8 rf_path,
- u8 offset, u8 tx_a_bias_offset)
-{
- u32 modi_tx_a_value = 0;
- u8 tmp1_byte = 0;
- bool is_minus = false;
- u8 comp_value = 0;
-
- switch (offset) {
- case 0x0:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10124);
- break;
- case 0x1:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10524);
- break;
- case 0x2:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10924);
- break;
- case 0x3:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10D24);
- break;
- case 0x4:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30164);
- break;
- case 0x5:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30564);
- break;
- case 0x6:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30964);
- break;
- case 0x7:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30D64);
- break;
- case 0x8:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50195);
- break;
- case 0x9:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50595);
- break;
- case 0xa:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50995);
- break;
- case 0xb:
- odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50D95);
- break;
- default:
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "Invalid TxA band offset...\n");
- return;
- }
-
- /* Get TxA value */
- modi_tx_a_value = odm_get_rf_reg(dm, rf_path, 0x61, 0xFFFFF);
- tmp1_byte = (u8)modi_tx_a_value & (BIT(3) | BIT(2) | BIT(1) | BIT(0));
-
- /* check how much need to calibration */
- switch (tx_a_bias_offset) {
- case 0xF6:
- is_minus = true;
- comp_value = 3;
- break;
-
- case 0xF4:
- is_minus = true;
- comp_value = 2;
- break;
-
- case 0xF2:
- is_minus = true;
- comp_value = 1;
- break;
-
- case 0xF3:
- is_minus = false;
- comp_value = 1;
- break;
-
- case 0xF5:
- is_minus = false;
- comp_value = 2;
- break;
-
- case 0xF7:
- is_minus = false;
- comp_value = 3;
- break;
-
- case 0xF9:
- is_minus = false;
- comp_value = 4;
- break;
-
- /* do nothing case */
- case 0xF0:
- default:
- ODM_RT_TRACE(dm, ODM_COMP_COMMON,
- "No need to do TxA bias current calibration\n");
- return;
- }
-
- /* calc correct value to calibrate */
- if (is_minus) {
- if (tmp1_byte >= comp_value) {
- tmp1_byte -= comp_value;
- /*modi_tx_a_value += tmp1_byte;*/
- } else {
- tmp1_byte = 0;
- }
- } else {
- tmp1_byte += comp_value;
- if (tmp1_byte >= 7)
- tmp1_byte = 7;
- }
-
- /* Write back to RF reg */
- odm_set_rf_reg(dm, rf_path, 0x30, 0xFFFF,
- (offset << 12 | (modi_tx_a_value & 0xFF0) | tmp1_byte));
-}
-
-static void _txa_bias_cali_4_each_path(struct phy_dm_struct *dm, u8 rf_path,
- u8 efuse_value)
-{
- /* switch on set TxA bias */
- odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x200);
-
- /* Set 12 sets of TxA value */
- _set_tx_a_cali_value(dm, rf_path, 0x0, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0x1, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0x2, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0x3, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0x4, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0x5, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0x6, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0x7, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0x8, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0x9, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0xa, efuse_value);
- _set_tx_a_cali_value(dm, rf_path, 0xb, efuse_value);
-
- /* switch off set TxA bias */
- odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x0);
-}
-
-/*
- * for 8822B PCIE D-cut patch only
- * Normal driver and MP driver need this patch
- */
-
-void phydm_txcurrentcalibration(struct phy_dm_struct *dm)
-{
- u8 efuse0x3D8, efuse0x3D7;
- u32 orig_rf0x18_path_a = 0, orig_rf0x18_path_b = 0;
-
- /* save original 0x18 value */
- orig_rf0x18_path_a = odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xFFFFF);
- orig_rf0x18_path_b = odm_get_rf_reg(dm, ODM_RF_PATH_B, 0x18, 0xFFFFF);
-
- /* define efuse content */
- efuse0x3D8 = dm->efuse0x3d8;
- efuse0x3D7 = dm->efuse0x3d7;
-
- /* check efuse content to judge whether need to calibration or not */
- if (efuse0x3D7 == 0xFF) {
- ODM_RT_TRACE(
- dm, ODM_COMP_COMMON,
- "efuse content 0x3D7 == 0xFF, No need to do TxA cali\n");
- return;
- }
-
- /* write RF register for calibration */
- _txa_bias_cali_4_each_path(dm, ODM_RF_PATH_A, efuse0x3D7);
- _txa_bias_cali_4_each_path(dm, ODM_RF_PATH_B, efuse0x3D8);
-
- /* restore original 0x18 value */
- odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xFFFFF, orig_rf0x18_path_a);
- odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x18, 0xFFFFF, orig_rf0x18_path_b);
-}
-
-void phydm_hwsetting_8822b(struct phy_dm_struct *dm)
-{
- phydm_dynamic_switch_htstf_mumimo_8822b(dm);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __ODM_RTL8822B_H__
-#define __ODM_RTL8822B_H__
-
-void phydm_hwsetting_8822b(struct phy_dm_struct *dm);
-
-#endif /* #define __ODM_RTL8822B_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-/*RTL8822B PHY Parameters*/
-/*
- * [Caution]
- * Since 01/Aug/2015, the commit rules will be simplified.
- * You do not need to fill up the version.h anymore,
- * only the maintenance supervisor fills it before formal release.
- */
-#define RELEASE_DATE_8822B 20161103
-#define COMMIT_BY_8822B "BB_JOE"
-#define RELEASE_VERSION_8822B 67
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-#include <linux/module.h>
-
-static int _rtl_phydm_init_com_info(struct rtl_priv *rtlpriv,
- enum odm_ic_type ic_type,
- struct rtl_phydm_params *params)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
- u8 odm_board_type = ODM_BOARD_DEFAULT;
- u32 support_ability;
- int i;
-
- dm->adapter = (void *)rtlpriv;
-
- odm_cmn_info_init(dm, ODM_CMNINFO_PLATFORM, ODM_CE);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_IC_TYPE, ic_type);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_INTERFACE, ODM_ITRF_PCIE);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_MP_TEST_CHIP, params->mp_chip);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_PATCH_ID, rtlhal->oem_id);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_BWIFI_TEST, 1);
-
- if (rtlphy->rf_type == RF_1T1R)
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_1T1R);
- else if (rtlphy->rf_type == RF_1T2R)
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_1T2R);
- else if (rtlphy->rf_type == RF_2T2R)
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_2T2R);
- else if (rtlphy->rf_type == RF_2T2R_GREEN)
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_2T2R_GREEN);
- else if (rtlphy->rf_type == RF_2T3R)
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_2T3R);
- else if (rtlphy->rf_type == RF_2T4R)
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_2T4R);
- else if (rtlphy->rf_type == RF_3T3R)
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_3T3R);
- else if (rtlphy->rf_type == RF_3T4R)
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_3T4R);
- else if (rtlphy->rf_type == RF_4T4R)
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_4T4R);
- else
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_TYPE, ODM_XTXR);
-
- /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
- if (rtlhal->external_lna_2g != 0) {
- odm_board_type |= ODM_BOARD_EXT_LNA;
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, 1);
- }
- if (rtlhal->external_lna_5g != 0) {
- odm_board_type |= ODM_BOARD_EXT_LNA_5G;
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, 1);
- }
- if (rtlhal->external_pa_2g != 0) {
- odm_board_type |= ODM_BOARD_EXT_PA;
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, 1);
- }
- if (rtlhal->external_pa_5g != 0) {
- odm_board_type |= ODM_BOARD_EXT_PA_5G;
- odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, 1);
- }
- if (rtlpriv->cfg->ops->get_btc_status())
- odm_board_type |= ODM_BOARD_BT;
-
- odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
- /* 1 ============== End of BoardType ============== */
-
- odm_cmn_info_init(dm, ODM_CMNINFO_GPA, rtlhal->type_gpa);
- odm_cmn_info_init(dm, ODM_CMNINFO_APA, rtlhal->type_apa);
- odm_cmn_info_init(dm, ODM_CMNINFO_GLNA, rtlhal->type_glna);
- odm_cmn_info_init(dm, ODM_CMNINFO_ALNA, rtlhal->type_alna);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_RFE_TYPE, rtlhal->rfe_type);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_EXT_TRSW, 0);
-
- /*Add by YuChen for kfree init*/
- odm_cmn_info_init(dm, ODM_CMNINFO_REGRFKFREEENABLE, 2);
- odm_cmn_info_init(dm, ODM_CMNINFO_RFKFREEENABLE, 0);
-
- /*Antenna diversity relative parameters*/
- odm_cmn_info_hook(dm, ODM_CMNINFO_ANT_DIV,
- &rtlefuse->antenna_div_cfg);
- odm_cmn_info_init(dm, ODM_CMNINFO_RF_ANTENNA_TYPE,
- rtlefuse->antenna_div_type);
- odm_cmn_info_init(dm, ODM_CMNINFO_BE_FIX_TX_ANT, 0);
- odm_cmn_info_init(dm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 0);
-
- /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
- odm_cmn_info_init(dm, ODM_CMNINFO_EFUSE0X3D7, params->efuse0x3d7);
- odm_cmn_info_init(dm, ODM_CMNINFO_EFUSE0X3D8, params->efuse0x3d8);
-
- /*Add by YuChen for adaptivity init*/
- odm_cmn_info_hook(dm, ODM_CMNINFO_ADAPTIVITY,
- &rtlpriv->phydm.adaptivity_en);
- phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE,
- false);
- phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_DCBACKOFF, 0);
- phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
- false);
- phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_TH_L2H_INI, 0);
- phydm_adaptivity_info_init(dm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, 0);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_IQKFWOFFLOAD, 0);
-
- /* Pointer reference */
- odm_cmn_info_hook(dm, ODM_CMNINFO_TX_UNI,
- &rtlpriv->stats.txbytesunicast);
- odm_cmn_info_hook(dm, ODM_CMNINFO_RX_UNI,
- &rtlpriv->stats.rxbytesunicast);
- odm_cmn_info_hook(dm, ODM_CMNINFO_BAND, &rtlhal->current_bandtype);
- odm_cmn_info_hook(dm, ODM_CMNINFO_FORCED_RATE,
- &rtlpriv->phydm.forced_data_rate);
- odm_cmn_info_hook(dm, ODM_CMNINFO_FORCED_IGI_LB,
- &rtlpriv->phydm.forced_igi_lb);
-
- odm_cmn_info_hook(dm, ODM_CMNINFO_SEC_CHNL_OFFSET,
- &mac->cur_40_prime_sc);
- odm_cmn_info_hook(dm, ODM_CMNINFO_BW, &rtlphy->current_chan_bw);
- odm_cmn_info_hook(dm, ODM_CMNINFO_CHNL, &rtlphy->current_channel);
-
- odm_cmn_info_hook(dm, ODM_CMNINFO_SCAN, &mac->act_scanning);
- odm_cmn_info_hook(dm, ODM_CMNINFO_POWER_SAVING,
- &ppsc->dot11_psmode); /* may add new boolean flag */
- /*Add by Yuchen for phydm beamforming*/
- odm_cmn_info_hook(dm, ODM_CMNINFO_TX_TP,
- &rtlpriv->stats.txbytesunicast_inperiod_tp);
- odm_cmn_info_hook(dm, ODM_CMNINFO_RX_TP,
- &rtlpriv->stats.rxbytesunicast_inperiod_tp);
- odm_cmn_info_hook(dm, ODM_CMNINFO_ANT_TEST,
- &rtlpriv->phydm.antenna_test);
- for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
- odm_cmn_info_ptr_array_hook(dm, ODM_CMNINFO_STA_STATUS, i,
- NULL);
-
- phydm_init_debug_setting(dm);
-
- odm_cmn_info_init(dm, ODM_CMNINFO_FAB_VER, params->fab_ver);
- odm_cmn_info_init(dm, ODM_CMNINFO_CUT_VER, params->cut_ver);
-
- /* after ifup, ability is updated again */
- support_ability = ODM_RF_CALIBRATION | ODM_RF_TX_PWR_TRACK;
- odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY, support_ability);
-
- return 0;
-}
-
-static int rtl_phydm_init_priv(struct rtl_priv *rtlpriv,
- struct rtl_phydm_params *params)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum odm_ic_type ic;
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- ic = ODM_RTL8822B;
- else
- return 0;
-
- rtlpriv->phydm.internal =
- kzalloc(sizeof(struct phy_dm_struct), GFP_KERNEL);
- if (!rtlpriv->phydm.internal)
- return 0;
-
- _rtl_phydm_init_com_info(rtlpriv, ic, params);
-
- odm_init_all_timers(dm);
-
- return 1;
-}
-
-static int rtl_phydm_deinit_priv(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- odm_cancel_all_timers(dm);
-
- kfree(rtlpriv->phydm.internal);
- rtlpriv->phydm.internal = NULL;
-
- return 0;
-}
-
-static bool rtl_phydm_load_txpower_by_rate(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum hal_status status;
-
- status = odm_config_bb_with_header_file(dm, CONFIG_BB_PHY_REG_PG);
- if (status != HAL_STATUS_SUCCESS)
- return false;
-
- return true;
-}
-
-static bool rtl_phydm_load_txpower_limit(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum hal_status status;
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv)) {
- odm_read_and_config_mp_8822b_txpwr_lmt(dm);
- } else {
- status = odm_config_rf_with_header_file(dm, CONFIG_RF_TXPWR_LMT,
- 0);
- if (status != HAL_STATUS_SUCCESS)
- return false;
- }
-
- return true;
-}
-
-static int rtl_phydm_init_dm(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- u32 support_ability = 0;
-
- /* clang-format off */
- support_ability = 0
- | ODM_BB_DIG
- | ODM_BB_RA_MASK
- | ODM_BB_DYNAMIC_TXPWR
- | ODM_BB_FA_CNT
- | ODM_BB_RSSI_MONITOR
- | ODM_BB_CCK_PD
- /* | ODM_BB_PWR_SAVE*/
- | ODM_BB_CFO_TRACKING
- | ODM_MAC_EDCA_TURBO
- | ODM_RF_TX_PWR_TRACK
- | ODM_RF_CALIBRATION
- | ODM_BB_NHM_CNT
- /* | ODM_BB_PWR_TRAIN*/
- ;
- /* clang-format on */
-
- odm_cmn_info_update(dm, ODM_CMNINFO_ABILITY, support_ability);
-
- odm_dm_init(dm);
-
- return 0;
-}
-
-static int rtl_phydm_deinit_dm(struct rtl_priv *rtlpriv)
-{
- return 0;
-}
-
-static int rtl_phydm_reset_dm(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- odm_dm_reset(dm);
-
- return 0;
-}
-
-static bool rtl_phydm_parameter_init(struct rtl_priv *rtlpriv, bool post)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- return config_phydm_parameter_init(dm, post ? ODM_POST_SETTING :
- ODM_PRE_SETTING);
-
- return false;
-}
-
-static bool rtl_phydm_phy_bb_config(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum hal_status status;
-
- status = odm_config_bb_with_header_file(dm, CONFIG_BB_PHY_REG);
- if (status != HAL_STATUS_SUCCESS)
- return false;
-
- status = odm_config_bb_with_header_file(dm, CONFIG_BB_AGC_TAB);
- if (status != HAL_STATUS_SUCCESS)
- return false;
-
- return true;
-}
-
-static bool rtl_phydm_phy_rf_config(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- enum hal_status status;
- enum odm_rf_radio_path rfpath;
-
- for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
- status = odm_config_rf_with_header_file(dm, CONFIG_RF_RADIO,
- rfpath);
- if (status != HAL_STATUS_SUCCESS)
- return false;
- }
-
- status = odm_config_rf_with_tx_pwr_track_header_file(dm);
- if (status != HAL_STATUS_SUCCESS)
- return false;
-
- return true;
-}
-
-static bool rtl_phydm_phy_mac_config(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum hal_status status;
-
- status = odm_config_mac_with_header_file(dm);
- if (status != HAL_STATUS_SUCCESS)
- return false;
-
- return true;
-}
-
-static bool rtl_phydm_trx_mode(struct rtl_priv *rtlpriv,
- enum radio_mask tx_path, enum radio_mask rx_path,
- bool is_tx2_path)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- return config_phydm_trx_mode_8822b(dm,
- (enum odm_rf_path)tx_path,
- (enum odm_rf_path)rx_path,
- is_tx2_path);
-
- return false;
-}
-
-static bool rtl_phydm_watchdog(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
- bool fw_current_inpsmode = false;
- bool fw_ps_awake = true;
- u8 is_linked = false;
- u8 bsta_state = false;
- u8 is_bt_enabled = false;
-
- /* check whether do watchdog */
- rtlpriv->cfg->ops->get_hw_reg(rtlpriv->hw, HW_VAR_FW_PSMODE_STATUS,
- (u8 *)(&fw_current_inpsmode));
- rtlpriv->cfg->ops->get_hw_reg(rtlpriv->hw, HW_VAR_FWLPS_RF_ON,
- (u8 *)(&fw_ps_awake));
- if (ppsc->p2p_ps_info.p2p_ps_mode)
- fw_ps_awake = false;
-
- if ((ppsc->rfpwr_state == ERFON) &&
- ((!fw_current_inpsmode) && fw_ps_awake) &&
- (!ppsc->rfchange_inprogress))
- ;
- else
- return false;
-
- /* update common info before doing watchdog */
- if (mac->link_state >= MAC80211_LINKED) {
- is_linked = true;
- if (mac->vif && mac->vif->type == NL80211_IFTYPE_STATION)
- bsta_state = true;
- }
-
- if (rtlpriv->cfg->ops->get_btc_status())
- is_bt_enabled = !rtlpriv->btcoexist.btc_ops->btc_is_bt_disabled(
- rtlpriv);
-
- odm_cmn_info_update(dm, ODM_CMNINFO_LINK, is_linked);
- odm_cmn_info_update(dm, ODM_CMNINFO_STATION_STATE, bsta_state);
- odm_cmn_info_update(dm, ODM_CMNINFO_BT_ENABLED, is_bt_enabled);
-
- /* do watchdog */
- odm_dm_watchdog(dm);
-
- return true;
-}
-
-static bool rtl_phydm_switch_band(struct rtl_priv *rtlpriv, u8 central_ch)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- return config_phydm_switch_band_8822b(dm, central_ch);
-
- return false;
-}
-
-static bool rtl_phydm_switch_channel(struct rtl_priv *rtlpriv, u8 central_ch)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- return config_phydm_switch_channel_8822b(dm, central_ch);
-
- return false;
-}
-
-static bool rtl_phydm_switch_bandwidth(struct rtl_priv *rtlpriv,
- u8 primary_ch_idx,
- enum ht_channel_width bandwidth)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum odm_bw odm_bw = (enum odm_bw)bandwidth;
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- return config_phydm_switch_bandwidth_8822b(dm, primary_ch_idx,
- odm_bw);
-
- return false;
-}
-
-static bool rtl_phydm_iq_calibrate(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- phy_iq_calibrate_8822b(dm, false);
- else
- return false;
-
- return true;
-}
-
-static bool rtl_phydm_clear_txpowertracking_state(struct rtl_priv *rtlpriv)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- odm_clear_txpowertracking_state(dm);
-
- return true;
-}
-
-static bool rtl_phydm_pause_dig(struct rtl_priv *rtlpriv, bool pause)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- if (pause)
- odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x1e);
- else /* resume */
- odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, 0xff);
-
- return true;
-}
-
-static u32 rtl_phydm_read_rf_reg(struct rtl_priv *rtlpriv,
- enum radio_path rfpath, u32 addr, u32 mask)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum odm_rf_radio_path odm_rfpath = (enum odm_rf_radio_path)rfpath;
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- return config_phydm_read_rf_reg_8822b(dm, odm_rfpath, addr,
- mask);
-
- return -1;
-}
-
-static bool rtl_phydm_write_rf_reg(struct rtl_priv *rtlpriv,
- enum radio_path rfpath, u32 addr, u32 mask,
- u32 data)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum odm_rf_radio_path odm_rfpath = (enum odm_rf_radio_path)rfpath;
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- return config_phydm_write_rf_reg_8822b(dm, odm_rfpath, addr,
- mask, data);
-
- return false;
-}
-
-static u8 rtl_phydm_read_txagc(struct rtl_priv *rtlpriv, enum radio_path rfpath,
- u8 hw_rate)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum odm_rf_radio_path odm_rfpath = (enum odm_rf_radio_path)rfpath;
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- return config_phydm_read_txagc_8822b(dm, odm_rfpath, hw_rate);
-
- return -1;
-}
-
-static bool rtl_phydm_write_txagc(struct rtl_priv *rtlpriv, u32 power_index,
- enum radio_path rfpath, u8 hw_rate)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- enum odm_rf_radio_path odm_rfpath = (enum odm_rf_radio_path)rfpath;
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- return config_phydm_write_txagc_8822b(dm, power_index,
- odm_rfpath, hw_rate);
-
- return false;
-}
-
-static bool rtl_phydm_c2h_content_parsing(struct rtl_priv *rtlpriv, u8 cmd_id,
- u8 cmd_len, u8 *content)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- if (phydm_c2H_content_parsing(dm, cmd_id, cmd_len, content))
- return true;
-
- return false;
-}
-
-static bool rtl_phydm_query_phy_status(struct rtl_priv *rtlpriv, u8 *phystrpt,
- struct ieee80211_hdr *hdr,
- struct rtl_stats *pstatus)
-{
- /* NOTE: phystrpt may be NULL, and need to fill default value */
-
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- struct dm_per_pkt_info pktinfo; /* input of pydm */
- struct dm_phy_status_info phy_info; /* output of phydm */
- __le16 fc = hdr->frame_control;
-
- /* fill driver pstatus */
- ether_addr_copy(pstatus->psaddr, ieee80211_get_SA(hdr));
-
- /* fill pktinfo */
- memset(&pktinfo, 0, sizeof(pktinfo));
-
- pktinfo.data_rate = pstatus->rate;
-
- if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION) {
- pktinfo.station_id = 0;
- } else {
- /* TODO: use rtl_find_sta() to find ID */
- pktinfo.station_id = 0xFF;
- }
-
- pktinfo.is_packet_match_bssid =
- (!ieee80211_is_ctl(fc) &&
- (ether_addr_equal(mac->bssid,
- ieee80211_has_tods(fc) ?
- hdr->addr1 :
- ieee80211_has_fromds(fc) ?
- hdr->addr2 :
- hdr->addr3)) &&
- (!pstatus->hwerror) && (!pstatus->crc) && (!pstatus->icv));
- pktinfo.is_packet_to_self =
- pktinfo.is_packet_match_bssid &&
- (ether_addr_equal(hdr->addr1, rtlefuse->dev_addr));
- pktinfo.is_to_self = (!pstatus->icv) && (!pstatus->crc) &&
- (ether_addr_equal(hdr->addr1, rtlefuse->dev_addr));
- pktinfo.is_packet_beacon = (ieee80211_is_beacon(fc) ? true : false);
-
- /* query phy status */
- if (phystrpt)
- odm_phy_status_query(dm, &phy_info, phystrpt, &pktinfo);
- else
- memset(&phy_info, 0, sizeof(phy_info));
-
- /* copy phy_info from phydm to driver */
- pstatus->rx_pwdb_all = phy_info.rx_pwdb_all;
- pstatus->bt_rx_rssi_percentage = phy_info.bt_rx_rssi_percentage;
- pstatus->recvsignalpower = phy_info.recv_signal_power;
- pstatus->signalquality = phy_info.signal_quality;
- pstatus->rx_mimo_signalquality[0] = phy_info.rx_mimo_signal_quality[0];
- pstatus->rx_mimo_signalquality[1] = phy_info.rx_mimo_signal_quality[1];
- pstatus->rx_packet_bw =
- phy_info.band_width; /* HT_CHANNEL_WIDTH_20 <- ODM_BW20M */
-
- /* fill driver pstatus */
- pstatus->packet_matchbssid = pktinfo.is_packet_match_bssid;
- pstatus->packet_toself = pktinfo.is_packet_to_self;
- pstatus->packet_beacon = pktinfo.is_packet_beacon;
-
- return true;
-}
-
-static u8 rtl_phydm_rate_id_mapping(struct rtl_priv *rtlpriv,
- enum wireless_mode wireless_mode,
- enum rf_type rf_type,
- enum ht_channel_width bw)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- return phydm_rate_id_mapping(dm, wireless_mode, rf_type, bw);
-}
-
-static bool rtl_phydm_get_ra_bitmap(struct rtl_priv *rtlpriv,
- enum wireless_mode wireless_mode,
- enum rf_type rf_type,
- enum ht_channel_width bw,
- u8 tx_rate_level, /* 0~6 */
- u32 *tx_bitmap_msb,
- u32 *tx_bitmap_lsb)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- const u8 mimo_ps_enable = 0;
- const u8 disable_cck_rate = 0;
-
- phydm_update_hal_ra_mask(dm, wireless_mode, rf_type, bw, mimo_ps_enable,
- disable_cck_rate, tx_bitmap_msb, tx_bitmap_lsb,
- tx_rate_level);
-
- return true;
-}
-
-static u8 _rtl_phydm_get_macid(struct rtl_priv *rtlpriv,
- struct ieee80211_sta *sta)
-{
- struct rtl_mac *mac = rtl_mac(rtlpriv);
-
- if (mac->opmode == NL80211_IFTYPE_STATION ||
- mac->opmode == NL80211_IFTYPE_MESH_POINT) {
- return 0;
- } else if (mac->opmode == NL80211_IFTYPE_AP ||
- mac->opmode == NL80211_IFTYPE_ADHOC)
- return sta->aid + 1;
-
- return 0;
-}
-
-static bool rtl_phydm_add_sta(struct rtl_priv *rtlpriv,
- struct ieee80211_sta *sta)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- struct rtl_sta_info *sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- u8 mac_id = _rtl_phydm_get_macid(rtlpriv, sta);
-
- odm_cmn_info_ptr_array_hook(dm, ODM_CMNINFO_STA_STATUS, mac_id,
- sta_entry);
-
- return true;
-}
-
-static bool rtl_phydm_del_sta(struct rtl_priv *rtlpriv,
- struct ieee80211_sta *sta)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- u8 mac_id = _rtl_phydm_get_macid(rtlpriv, sta);
-
- odm_cmn_info_ptr_array_hook(dm, ODM_CMNINFO_STA_STATUS, mac_id, NULL);
-
- return true;
-}
-
-static u32 rtl_phydm_get_version(struct rtl_priv *rtlpriv)
-{
- u32 ver = 0;
-
- if (IS_HARDWARE_TYPE_8822B(rtlpriv))
- ver = RELEASE_VERSION_8822B;
-
- return ver;
-}
-
-static bool rtl_phydm_modify_ra_pcr_threshold(struct rtl_priv *rtlpriv,
- u8 ra_offset_direction,
- u8 ra_threshold_offset)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- phydm_modify_RA_PCR_threshold(dm, ra_offset_direction,
- ra_threshold_offset);
-
- return true;
-}
-
-static u32 rtl_phydm_query_counter(struct rtl_priv *rtlpriv,
- const char *info_type)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
- static const struct query_entry {
- const char *query_name;
- enum phydm_info_query query_id;
- } query_table[] = {
-#define QUERY_ENTRY(name) {#name, name}
- QUERY_ENTRY(PHYDM_INFO_FA_OFDM),
- QUERY_ENTRY(PHYDM_INFO_FA_CCK),
- QUERY_ENTRY(PHYDM_INFO_CCA_OFDM),
- QUERY_ENTRY(PHYDM_INFO_CCA_CCK),
- QUERY_ENTRY(PHYDM_INFO_CRC32_OK_CCK),
- QUERY_ENTRY(PHYDM_INFO_CRC32_OK_LEGACY),
- QUERY_ENTRY(PHYDM_INFO_CRC32_OK_HT),
- QUERY_ENTRY(PHYDM_INFO_CRC32_OK_VHT),
- QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_CCK),
- QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_LEGACY),
- QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_HT),
- QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_VHT),
- };
-#define QUERY_TABLE_SIZE ARRAY_SIZE(query_table)
-
- int i;
- const struct query_entry *entry;
-
- if (!strcmp(info_type, "IQK_TOTAL"))
- return dm->n_iqk_cnt;
-
- if (!strcmp(info_type, "IQK_OK"))
- return dm->n_iqk_ok_cnt;
-
- if (!strcmp(info_type, "IQK_FAIL"))
- return dm->n_iqk_fail_cnt;
-
- for (i = 0; i < QUERY_TABLE_SIZE; i++) {
- entry = &query_table[i];
-
- if (!strcmp(info_type, entry->query_name))
- return phydm_cmn_info_query(dm, entry->query_id);
- }
-
- pr_err("Unrecognized info_type:%s!!!!:\n", info_type);
-
- return 0xDEADDEAD;
-}
-
-static bool rtl_phydm_debug_cmd(struct rtl_priv *rtlpriv, char *in, u32 in_len,
- char *out, u32 out_len)
-{
- struct phy_dm_struct *dm = rtlpriv_to_phydm(rtlpriv);
-
- phydm_cmd(dm, in, in_len, 1, out, out_len);
-
- return true;
-}
-
-static struct rtl_phydm_ops rtl_phydm_operation = {
- /* init/deinit priv */
- .phydm_init_priv = rtl_phydm_init_priv,
- .phydm_deinit_priv = rtl_phydm_deinit_priv,
- .phydm_load_txpower_by_rate = rtl_phydm_load_txpower_by_rate,
- .phydm_load_txpower_limit = rtl_phydm_load_txpower_limit,
-
- /* init hw */
- .phydm_init_dm = rtl_phydm_init_dm,
- .phydm_deinit_dm = rtl_phydm_deinit_dm,
- .phydm_reset_dm = rtl_phydm_reset_dm,
- .phydm_parameter_init = rtl_phydm_parameter_init,
- .phydm_phy_bb_config = rtl_phydm_phy_bb_config,
- .phydm_phy_rf_config = rtl_phydm_phy_rf_config,
- .phydm_phy_mac_config = rtl_phydm_phy_mac_config,
- .phydm_trx_mode = rtl_phydm_trx_mode,
-
- /* watchdog */
- .phydm_watchdog = rtl_phydm_watchdog,
-
- /* channel */
- .phydm_switch_band = rtl_phydm_switch_band,
- .phydm_switch_channel = rtl_phydm_switch_channel,
- .phydm_switch_bandwidth = rtl_phydm_switch_bandwidth,
- .phydm_iq_calibrate = rtl_phydm_iq_calibrate,
- .phydm_clear_txpowertracking_state =
- rtl_phydm_clear_txpowertracking_state,
- .phydm_pause_dig = rtl_phydm_pause_dig,
-
- /* read/write reg */
- .phydm_read_rf_reg = rtl_phydm_read_rf_reg,
- .phydm_write_rf_reg = rtl_phydm_write_rf_reg,
- .phydm_read_txagc = rtl_phydm_read_txagc,
- .phydm_write_txagc = rtl_phydm_write_txagc,
-
- /* RX */
- .phydm_c2h_content_parsing = rtl_phydm_c2h_content_parsing,
- .phydm_query_phy_status = rtl_phydm_query_phy_status,
-
- /* TX */
- .phydm_rate_id_mapping = rtl_phydm_rate_id_mapping,
- .phydm_get_ra_bitmap = rtl_phydm_get_ra_bitmap,
-
- /* STA */
- .phydm_add_sta = rtl_phydm_add_sta,
- .phydm_del_sta = rtl_phydm_del_sta,
-
- /* BTC */
- .phydm_get_version = rtl_phydm_get_version,
- .phydm_modify_ra_pcr_threshold = rtl_phydm_modify_ra_pcr_threshold,
- .phydm_query_counter = rtl_phydm_query_counter,
-
- /* debug */
- .phydm_debug_cmd = rtl_phydm_debug_cmd,
-};
-
-struct rtl_phydm_ops *rtl_phydm_get_ops_pointer(void)
-{
- return &rtl_phydm_operation;
-}
-EXPORT_SYMBOL(rtl_phydm_get_ops_pointer);
-
-/* ********************************************************
- * Define phydm callout function in below
- * ********************************************************
- */
-
-u8 phy_get_tx_power_index(void *adapter, u8 rf_path, u8 rate,
- enum ht_channel_width bandwidth, u8 channel)
-{
- /* rate: DESC_RATE1M */
- struct rtl_priv *rtlpriv = (struct rtl_priv *)adapter;
-
- return rtlpriv->cfg->ops->get_txpower_index(rtlpriv->hw, rf_path, rate,
- bandwidth, channel);
-}
-
-void phy_set_tx_power_index_by_rs(void *adapter, u8 ch, u8 path, u8 rs)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)adapter;
-
- return rtlpriv->cfg->ops->set_tx_power_index_by_rs(rtlpriv->hw, ch,
- path, rs);
-}
-
-void phy_store_tx_power_by_rate(void *adapter, u32 band, u32 rfpath, u32 txnum,
- u32 regaddr, u32 bitmask, u32 data)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)adapter;
-
- rtlpriv->cfg->ops->store_tx_power_by_rate(
- rtlpriv->hw, band, rfpath, txnum, regaddr, bitmask, data);
-}
-
-void phy_set_tx_power_limit(void *dm, u8 *regulation, u8 *band, u8 *bandwidth,
- u8 *rate_section, u8 *rf_path, u8 *channel,
- u8 *power_limit)
-{
- struct rtl_priv *rtlpriv =
- (struct rtl_priv *)((struct phy_dm_struct *)dm)->adapter;
-
- rtlpriv->cfg->ops->phy_set_txpower_limit(rtlpriv->hw, regulation, band,
- bandwidth, rate_section,
- rf_path, channel, power_limit);
-}
-
-void rtl_hal_update_ra_mask(void *adapter, struct rtl_sta_info *psta,
- u8 rssi_level)
-{
- struct rtl_priv *rtlpriv = (struct rtl_priv *)adapter;
- struct ieee80211_sta *sta =
- container_of((void *)psta, struct ieee80211_sta, drv_priv);
-
- rtlpriv->cfg->ops->update_rate_tbl(rtlpriv->hw, sta, rssi_level, false);
-}
-
-MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
-MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __RTL_PHYDM_H__
-#define __RTL_PHYDM_H__
-
-struct rtl_phydm_ops *rtl_phydm_get_ops_pointer(void);
-
-#define rtlpriv_to_phydm(priv) \
- ((struct phy_dm_struct *)((priv)->phydm.internal))
-
-u8 phy_get_tx_power_index(void *adapter, u8 rf_path, u8 rate,
- enum ht_channel_width bandwidth, u8 channel);
-void phy_set_tx_power_index_by_rs(void *adapter, u8 ch, u8 path, u8 rs);
-void phy_store_tx_power_by_rate(void *adapter, u32 band, u32 rfpath, u32 txnum,
- u32 regaddr, u32 bitmask, u32 data);
-void phy_set_tx_power_limit(void *dm, u8 *regulation, u8 *band, u8 *bandwidth,
- u8 *rate_section, u8 *rf_path, u8 *channel,
- u8 *power_limit);
-
-void rtl_hal_update_ra_mask(void *adapter, struct rtl_sta_info *psta,
- u8 rssi_level);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __HAL_COM_TXBF_H__
-#define __HAL_COM_TXBF_H__
-
-enum txbf_set_type {
- TXBF_SET_SOUNDING_ENTER,
- TXBF_SET_SOUNDING_LEAVE,
- TXBF_SET_SOUNDING_RATE,
- TXBF_SET_SOUNDING_STATUS,
- TXBF_SET_SOUNDING_FW_NDPA,
- TXBF_SET_SOUNDING_CLK,
- TXBF_SET_TX_PATH_RESET,
- TXBF_SET_GET_TX_RATE
-};
-
-enum txbf_get_type {
- TXBF_GET_EXPLICIT_BEAMFORMEE,
- TXBF_GET_EXPLICIT_BEAMFORMER,
- TXBF_GET_MU_MIMO_STA,
- TXBF_GET_MU_MIMO_AP
-};
-
-/* 2 HAL TXBF related */
-struct _HAL_TXBF_INFO {
- u8 txbf_idx;
- u8 ndpa_idx;
- u8 BW;
- u8 rate;
-
- struct timer_list txbf_fw_ndpa_timer;
-};
-
-#define hal_com_txbf_beamform_init(dm_void) NULL
-#define hal_com_txbf_config_gtab(dm_void) NULL
-#define hal_com_txbf_enter_work_item_callback(_adapter) NULL
-#define hal_com_txbf_leave_work_item_callback(_adapter) NULL
-#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL
-#define hal_com_txbf_clk_work_item_callback(_adapter) NULL
-#define hal_com_txbf_rate_work_item_callback(_adapter) NULL
-#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL
-#define hal_com_txbf_status_work_item_callback(_adapter) NULL
-#define hal_com_txbf_get(_adapter, _get_type, _pout_buf)
-
-#endif /* #ifndef __HAL_COM_TXBF_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __HAL_TXBF_8822B_H__
-#define __HAL_TXBF_8822B_H__
-
-#define hal_txbf_8822b_enter(dm_void, idx)
-#define hal_txbf_8822b_leave(dm_void, idx)
-#define hal_txbf_8822b_status(dm_void, idx)
-#define hal_txbf_8822b_fw_txbf(dm_void, idx)
-#define hal_txbf_8822b_config_gtab(dm_void)
-
-void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
-
-void phydm_8822b_sutxbfer_workaroud(void *dm_void, bool enable_su_bfer, u8 nc,
- u8 nr, u8 ng, u8 CB, u8 BW, bool is_vht);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __HAL_TXBF_INTERFACE_H__
-#define __HAL_TXBF_INTERFACE_H__
-
-#define beamforming_get_ndpa_frame(dm, _pdu_os)
-#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE
-#define send_fw_ht_ndpa_packet(dm_void, RA, BW)
-#define send_sw_ht_ndpa_packet(dm_void, RA, BW)
-#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW)
-#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW)
-#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx)
-#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)
-#define send_sw_vht_mu_ndpa_packet(dm_void, BW)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __HAL_TXBF_JAGUAR_H__
-#define __HAL_TXBF_JAGUAR_H__
-
-#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
-#define hal_txbf_jaguar_enter(dm_void, idx)
-#define hal_txbf_jaguar_leave(dm_void, idx)
-#define hal_txbf_jaguar_status(dm_void, idx)
-#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
-#define hal_txbf_jaguar_patch(dm_void, operation)
-#define hal_txbf_jaguar_clk_8812a(dm_void)
-
-#endif /* #ifndef __HAL_TXBF_JAGUAR_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#ifndef __PHYDM_HAL_TXBF_API_H__
-#define __PHYDM_HAL_TXBF_API_H__
-
-#define tx_bf_nr(a, b) ((a > b) ? (b) : (a))
-
-u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 comp_steering_num_of_bfer);
-
-u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 comp_steering_num_of_bfer);
-
-u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *troughput,
- u8 total_bfee_num, u8 *tx_rate);
-
-u8 phydm_get_ndpa_rate(void *dm_void);
-
-u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "wifi.h"
-#include "base.h"
-#include "ps.h"
-#include <linux/export.h>
-#include "btcoexist/rtl_btc.h"
-
-bool rtl_ps_enable_nic(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
-
- /*<1> reset trx ring */
- if (rtlhal->interface == INTF_PCI)
- rtlpriv->intf_ops->reset_trx_ring(hw);
-
- if (is_hal_stop(rtlhal))
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "Driver is already down!\n");
-
- /*<2> Enable Adapter */
- if (rtlpriv->cfg->ops->hw_init(hw))
- return false;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
- &rtlmac->retry_long);
- RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
-
- /*<2.1> Switch Channel & Bandwidth to last rtl_op_config setting*/
- rtlpriv->cfg->ops->switch_channel(hw);
- rtlpriv->cfg->ops->set_channel_access(hw);
- rtlpriv->cfg->ops->set_bw_mode(hw,
- cfg80211_get_chandef_type(&hw->conf.chandef));
-
- /*<3> Enable Interrupt */
- rtlpriv->cfg->ops->enable_interrupt(hw);
-
- /*<enable timer> */
- rtl_watch_dog_timer_callback(&rtlpriv->works.watchdog_timer);
-
- return true;
-}
-
-bool rtl_ps_disable_nic(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- /*<1> Stop all timer */
- rtl_deinit_deferred_work(hw);
-
- /*<2> Disable Interrupt */
- rtlpriv->cfg->ops->disable_interrupt(hw);
- tasklet_kill(&rtlpriv->works.irq_tasklet);
-
- /*<3> Disable Adapter */
- rtlpriv->cfg->ops->hw_disable(hw);
-
- return true;
-}
-
-static bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
- enum rf_pwrstate state_toset,
- u32 changesource)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- enum rf_pwrstate rtstate;
- bool actionallowed = false;
- u16 rfwait_cnt = 0;
-
- /*Only one thread can change
- *the RF state at one time, and others
- *should wait to be executed.
- */
- while (true) {
- spin_lock(&rtlpriv->locks.rf_ps_lock);
- if (ppsc->rfchange_inprogress) {
- spin_unlock(&rtlpriv->locks.rf_ps_lock);
-
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "RF Change in progress! Wait to set..state_toset(%d).\n",
- state_toset);
-
- /* Set RF after the previous action is done. */
- while (ppsc->rfchange_inprogress) {
- rfwait_cnt++;
- mdelay(1);
- /*Wait too long, return false to avoid
- *to be stuck here.
- */
- if (rfwait_cnt > 100)
- return false;
- }
- } else {
- ppsc->rfchange_inprogress = true;
- spin_unlock(&rtlpriv->locks.rf_ps_lock);
- break;
- }
- }
-
- rtstate = ppsc->rfpwr_state;
-
- switch (state_toset) {
- case ERFON:
- ppsc->rfoff_reason &= (~changesource);
-
- if ((changesource == RF_CHANGE_BY_HW) &&
- (ppsc->hwradiooff)) {
- ppsc->hwradiooff = false;
- }
-
- if (!ppsc->rfoff_reason) {
- ppsc->rfoff_reason = 0;
- actionallowed = true;
- }
- break;
- case ERFOFF:
- if ((changesource == RF_CHANGE_BY_HW) && !ppsc->hwradiooff)
- ppsc->hwradiooff = true;
-
- ppsc->rfoff_reason |= changesource;
- actionallowed = true;
- break;
- case ERFSLEEP:
- ppsc->rfoff_reason |= changesource;
- actionallowed = true;
- break;
- default:
- pr_err("switch case %#x not processed\n", state_toset);
- break;
- }
-
- if (actionallowed)
- rtlpriv->cfg->ops->set_rf_power_state(hw, state_toset);
-
- spin_lock(&rtlpriv->locks.rf_ps_lock);
- ppsc->rfchange_inprogress = false;
- spin_unlock(&rtlpriv->locks.rf_ps_lock);
-
- return actionallowed;
-}
-
-static void _rtl_ps_inactive_ps(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
-
- ppsc->swrf_processing = true;
-
- if (ppsc->inactive_pwrstate == ERFON &&
- rtlhal->interface == INTF_PCI) {
- if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
- RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM) &&
- rtlhal->interface == INTF_PCI) {
- rtlpriv->intf_ops->disable_aspm(hw);
- RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
- }
- }
-
- rtl_ps_set_rf_state(hw, ppsc->inactive_pwrstate,
- RF_CHANGE_BY_IPS);
-
- if (ppsc->inactive_pwrstate == ERFOFF &&
- rtlhal->interface == INTF_PCI) {
- if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
- !RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
- rtlpriv->intf_ops->enable_aspm(hw);
- RT_SET_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
- }
- }
-
- ppsc->swrf_processing = false;
-}
-
-void rtl_ips_nic_off_wq_callback(void *data)
-{
- struct rtl_works *rtlworks =
- container_of_dwork_rtl(data, struct rtl_works, ips_nic_off_wq);
- struct ieee80211_hw *hw = rtlworks->hw;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- enum rf_pwrstate rtstate;
-
- if (mac->opmode != NL80211_IFTYPE_STATION) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "not station return\n");
- return;
- }
-
- if (mac->p2p_in_use)
- return;
-
- if (mac->link_state > MAC80211_NOLINK)
- return;
-
- if (is_hal_stop(rtlhal))
- return;
-
- if (rtlpriv->sec.being_setkey)
- return;
-
- if (rtlpriv->cfg->ops->bt_coex_off_before_lps)
- rtlpriv->cfg->ops->bt_coex_off_before_lps(hw);
-
- if (ppsc->inactiveps) {
- rtstate = ppsc->rfpwr_state;
-
- /*
- *Do not enter IPS in the following conditions:
- *(1) RF is already OFF or Sleep
- *(2) swrf_processing (indicates the IPS is still under going)
- *(3) Connectted (only disconnected can trigger IPS)
- *(4) IBSS (send Beacon)
- *(5) AP mode (send Beacon)
- *(6) monitor mode (rcv packet)
- */
-
- if (rtstate == ERFON &&
- !ppsc->swrf_processing &&
- (mac->link_state == MAC80211_NOLINK) &&
- !mac->act_scanning) {
- RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
- "IPSEnter(): Turn off RF\n");
-
- ppsc->inactive_pwrstate = ERFOFF;
- ppsc->in_powersavemode = true;
-
- /* call before RF off */
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_ips_notify(rtlpriv,
- ppsc->inactive_pwrstate);
-
- /*rtl_pci_reset_trx_ring(hw); */
- _rtl_ps_inactive_ps(hw);
- }
- }
-}
-
-void rtl_ips_nic_off(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- /* because when link with ap, mac80211 will ask us
- * to disable nic quickly after scan before linking,
- * this will cause link failed, so we delay 100ms here
- */
- queue_delayed_work(rtlpriv->works.rtl_wq,
- &rtlpriv->works.ips_nic_off_wq, MSECS(100));
-}
-
-/* NOTICE: any opmode should exc nic_on, or disable without
- * nic_on may something wrong, like adhoc TP
- */
-void rtl_ips_nic_on(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- enum rf_pwrstate rtstate;
-
- cancel_delayed_work(&rtlpriv->works.ips_nic_off_wq);
-
- mutex_lock(&rtlpriv->locks.ips_mutex);
- if (ppsc->inactiveps) {
- rtstate = ppsc->rfpwr_state;
-
- if (rtstate != ERFON &&
- !ppsc->swrf_processing &&
- ppsc->rfoff_reason <= RF_CHANGE_BY_IPS) {
- ppsc->inactive_pwrstate = ERFON;
- ppsc->in_powersavemode = false;
- _rtl_ps_inactive_ps(hw);
- /* call after RF on */
- if (rtlpriv->phydm.ops)
- rtlpriv->phydm.ops->phydm_reset_dm(rtlpriv);
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_ips_notify(rtlpriv,
- ppsc->inactive_pwrstate);
- }
- }
- mutex_unlock(&rtlpriv->locks.ips_mutex);
-}
-
-/*for FW LPS*/
-
-/*
- *Determine if we can set Fw into PS mode
- *in current condition.Return TRUE if it
- *can enter PS mode.
- */
-static bool rtl_get_fwlps_doze(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- u32 ps_timediff;
-
- ps_timediff = jiffies_to_msecs(jiffies -
- ppsc->last_delaylps_stamp_jiffies);
-
- if (ps_timediff < 2000) {
- RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
- "Delay enter Fw LPS for DHCP, ARP, or EAPOL exchanging state\n");
- return false;
- }
-
- if (mac->link_state != MAC80211_LINKED)
- return false;
-
- if (mac->opmode == NL80211_IFTYPE_ADHOC)
- return false;
-
- return true;
-}
-
-/* Change current and default preamble mode.*/
-void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- bool enter_fwlps;
-
- if (mac->opmode == NL80211_IFTYPE_ADHOC)
- return;
-
- if (mac->link_state != MAC80211_LINKED)
- return;
-
- if (ppsc->dot11_psmode == rt_psmode && rt_psmode == EACTIVE)
- return;
-
- /* Update power save mode configured. */
- ppsc->dot11_psmode = rt_psmode;
-
- /*
- *<FW control LPS>
- *1. Enter PS mode
- * Set RPWM to Fw to turn RF off and send H2C fw_pwrmode
- * cmd to set Fw into PS mode.
- *2. Leave PS mode
- * Send H2C fw_pwrmode cmd to Fw to set Fw into Active
- * mode and set RPWM to turn RF on.
- */
-
- if ((ppsc->fwctrl_lps) && ppsc->report_linked) {
- if (ppsc->dot11_psmode == EACTIVE) {
- RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
- "FW LPS leave ps_mode:%x\n",
- FW_PS_ACTIVE_MODE);
- enter_fwlps = false;
- ppsc->pwr_mode = FW_PS_ACTIVE_MODE;
- ppsc->smart_ps = 0;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_LPS_ACTION,
- (u8 *)(&enter_fwlps));
- if (ppsc->p2p_ps_info.opp_ps)
- rtl_p2p_ps_cmd(hw, P2P_PS_ENABLE);
-
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_lps_notify(rtlpriv, rt_psmode);
- } else {
- if (rtl_get_fwlps_doze(hw)) {
- RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
- "FW LPS enter ps_mode:%x\n",
- ppsc->fwctrl_psmode);
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_lps_notify(rtlpriv, rt_psmode);
- enter_fwlps = true;
- ppsc->pwr_mode = ppsc->fwctrl_psmode;
- ppsc->smart_ps = 2;
- rtlpriv->cfg->ops->set_hw_reg(hw,
- HW_VAR_FW_LPS_ACTION,
- (u8 *)(&enter_fwlps));
-
- } else {
- /* Reset the power save related parameters. */
- ppsc->dot11_psmode = EACTIVE;
- }
- }
- }
-}
-
-/* Interrupt safe routine to enter the leisure power save mode.*/
-static void rtl_lps_enter_core(struct ieee80211_hw *hw)
-{
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- if (!ppsc->fwctrl_lps)
- return;
-
- if (rtlpriv->sec.being_setkey)
- return;
-
- if (rtlpriv->link_info.busytraffic)
- return;
-
- /*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */
- if (mac->cnt_after_linked < 5)
- return;
-
- if (mac->opmode == NL80211_IFTYPE_ADHOC)
- return;
-
- if (mac->link_state != MAC80211_LINKED)
- return;
-
- mutex_lock(&rtlpriv->locks.lps_mutex);
-
- /* Don't need to check (ppsc->dot11_psmode == EACTIVE), because
- * bt_ccoexist may ask to enter lps.
- * In normal case, this constraint move to rtl_lps_set_psmode().
- */
- RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
- "Enter 802.11 power save mode...\n");
- rtl_lps_set_psmode(hw, EAUTOPS);
-
- mutex_unlock(&rtlpriv->locks.lps_mutex);
-}
-
-/* Interrupt safe routine to leave the leisure power save mode.*/
-static void rtl_lps_leave_core(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
-
- mutex_lock(&rtlpriv->locks.lps_mutex);
-
- if (ppsc->fwctrl_lps) {
- if (ppsc->dot11_psmode != EACTIVE) {
- /*FIX ME */
- /*rtlpriv->cfg->ops->enable_interrupt(hw); */
-
- if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM &&
- RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM) &&
- rtlhal->interface == INTF_PCI) {
- rtlpriv->intf_ops->disable_aspm(hw);
- RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
- }
-
- RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
- "Busy Traffic,Leave 802.11 power save..\n");
-
- rtl_lps_set_psmode(hw, EACTIVE);
- }
- }
- mutex_unlock(&rtlpriv->locks.lps_mutex);
-}
-
-/* For sw LPS*/
-void rtl_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct ieee80211_hdr *hdr = data;
- struct ieee80211_tim_ie *tim_ie;
- u8 *tim;
- u8 tim_len;
- bool u_buffed;
- bool m_buffed;
-
- if (mac->opmode != NL80211_IFTYPE_STATION)
- return;
-
- if (!rtlpriv->psc.swctrl_lps)
- return;
-
- if (rtlpriv->mac80211.link_state != MAC80211_LINKED)
- return;
-
- if (!rtlpriv->psc.sw_ps_enabled)
- return;
-
- if (rtlpriv->psc.fwctrl_lps)
- return;
-
- if (likely(!(hw->conf.flags & IEEE80211_CONF_PS)))
- return;
-
- /* check if this really is a beacon */
- if (!ieee80211_is_beacon(hdr->frame_control))
- return;
-
- /* min. beacon length + FCS_LEN */
- if (len <= 40 + FCS_LEN)
- return;
-
- /* and only beacons from the associated BSSID, please */
- if (!ether_addr_equal_64bits(hdr->addr3, rtlpriv->mac80211.bssid))
- return;
-
- rtlpriv->psc.last_beacon = jiffies;
-
- tim = rtl_find_ie(data, len - FCS_LEN, WLAN_EID_TIM);
- if (!tim)
- return;
-
- if (tim[1] < sizeof(*tim_ie))
- return;
-
- tim_len = tim[1];
- tim_ie = (struct ieee80211_tim_ie *)&tim[2];
-
- if (!WARN_ON_ONCE(!hw->conf.ps_dtim_period))
- rtlpriv->psc.dtim_counter = tim_ie->dtim_count;
-
- /* Check whenever the PHY can be turned off again. */
-
- /* 1. What about buffered unicast traffic for our AID? */
- u_buffed = ieee80211_check_tim(tim_ie, tim_len,
- rtlpriv->mac80211.assoc_id);
-
- /* 2. Maybe the AP wants to send multicast/broadcast data? */
- m_buffed = tim_ie->bitmap_ctrl & 0x01;
- rtlpriv->psc.multi_buffered = m_buffed;
-
- /* unicast will process by mac80211 through
- * set ~IEEE80211_CONF_PS, So we just check
- * multicast frames here
- */
- if (!m_buffed) {
- /* back to low-power land. and delay is
- * prevent null power save frame tx fail
- */
- queue_delayed_work(rtlpriv->works.rtl_wq,
- &rtlpriv->works.ps_work, MSECS(5));
- } else {
- RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
- "u_bufferd: %x, m_buffered: %x\n", u_buffed, m_buffed);
- }
-}
-
-void rtl_swlps_rf_awake(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-
- if (!rtlpriv->psc.swctrl_lps)
- return;
- if (mac->link_state != MAC80211_LINKED)
- return;
-
- if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM &&
- RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
- rtlpriv->intf_ops->disable_aspm(hw);
- RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
- }
-
- mutex_lock(&rtlpriv->locks.lps_mutex);
- rtl_ps_set_rf_state(hw, ERFON, RF_CHANGE_BY_PS);
- mutex_unlock(&rtlpriv->locks.lps_mutex);
-}
-
-void rtl_swlps_rfon_wq_callback(void *data)
-{
- struct rtl_works *rtlworks =
- container_of_dwork_rtl(data, struct rtl_works, ps_rfon_wq);
- struct ieee80211_hw *hw = rtlworks->hw;
-
- rtl_swlps_rf_awake(hw);
-}
-
-void rtl_swlps_rf_sleep(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- u8 sleep_intv;
-
- if (!rtlpriv->psc.sw_ps_enabled)
- return;
-
- if ((rtlpriv->sec.being_setkey) ||
- (mac->opmode == NL80211_IFTYPE_ADHOC))
- return;
-
- /*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */
- if ((mac->link_state != MAC80211_LINKED) || (mac->cnt_after_linked < 5))
- return;
-
- if (rtlpriv->link_info.busytraffic)
- return;
-
- spin_lock(&rtlpriv->locks.rf_ps_lock);
- if (rtlpriv->psc.rfchange_inprogress) {
- spin_unlock(&rtlpriv->locks.rf_ps_lock);
- return;
- }
- spin_unlock(&rtlpriv->locks.rf_ps_lock);
-
- mutex_lock(&rtlpriv->locks.lps_mutex);
- rtl_ps_set_rf_state(hw, ERFSLEEP, RF_CHANGE_BY_PS);
- mutex_unlock(&rtlpriv->locks.lps_mutex);
-
- if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
- !RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
- rtlpriv->intf_ops->enable_aspm(hw);
- RT_SET_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
- }
-
- /* here is power save alg, when this beacon is DTIM
- * we will set sleep time to dtim_period * n;
- * when this beacon is not DTIM, we will set sleep
- * time to sleep_intv = rtlpriv->psc.dtim_counter or
- * MAX_SW_LPS_SLEEP_INTV(default set to 5)
- */
-
- if (rtlpriv->psc.dtim_counter == 0) {
- if (hw->conf.ps_dtim_period == 1)
- sleep_intv = hw->conf.ps_dtim_period * 2;
- else
- sleep_intv = hw->conf.ps_dtim_period;
- } else {
- sleep_intv = rtlpriv->psc.dtim_counter;
- }
-
- if (sleep_intv > MAX_SW_LPS_SLEEP_INTV)
- sleep_intv = MAX_SW_LPS_SLEEP_INTV;
-
- /* this print should always be dtim_conter = 0 &
- * sleep = dtim_period, that meaons, we should
- * awake before every dtim
- */
- RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
- "dtim_counter:%x will sleep :%d beacon_intv\n",
- rtlpriv->psc.dtim_counter, sleep_intv);
-
- /* we tested that 40ms is enough for sw & hw sw delay */
- queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.ps_rfon_wq,
- MSECS(sleep_intv *
- mac->vif->bss_conf.beacon_int - 40));
-}
-
-void rtl_lps_change_work_callback(struct work_struct *work)
-{
- struct rtl_works *rtlworks =
- container_of(work, struct rtl_works, lps_change_work);
- struct ieee80211_hw *hw = rtlworks->hw;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- if (rtlpriv->enter_ps)
- rtl_lps_enter_core(hw);
- else
- rtl_lps_leave_core(hw);
-}
-
-void rtl_lps_enter(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- if (!in_interrupt())
- return rtl_lps_enter_core(hw);
- rtlpriv->enter_ps = true;
- schedule_work(&rtlpriv->works.lps_change_work);
-}
-
-void rtl_lps_leave(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- if (!in_interrupt())
- return rtl_lps_leave_core(hw);
- rtlpriv->enter_ps = false;
- schedule_work(&rtlpriv->works.lps_change_work);
-}
-
-void rtl_swlps_wq_callback(void *data)
-{
- struct rtl_works *rtlworks = container_of_dwork_rtl(data,
- struct rtl_works,
- ps_work);
- struct ieee80211_hw *hw = rtlworks->hw;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- bool ps = false;
-
- ps = (hw->conf.flags & IEEE80211_CONF_PS);
-
- /* we can sleep after ps null send ok */
- if (rtlpriv->psc.state_inap) {
- rtl_swlps_rf_sleep(hw);
-
- if (rtlpriv->psc.state && !ps) {
- rtlpriv->psc.sleep_ms = jiffies_to_msecs(jiffies -
- rtlpriv->psc.last_action);
- }
-
- if (ps)
- rtlpriv->psc.last_slept = jiffies;
-
- rtlpriv->psc.last_action = jiffies;
- rtlpriv->psc.state = ps;
- }
-}
-
-static void rtl_p2p_noa_ie(struct ieee80211_hw *hw, void *data,
- unsigned int len)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_mgmt *mgmt = data;
- struct rtl_p2p_ps_info *p2pinfo = &rtlpriv->psc.p2p_ps_info;
- u8 *pos, *end, *ie;
- u16 noa_len;
- static u8 p2p_oui_ie_type[4] = {0x50, 0x6f, 0x9a, 0x09};
- u8 noa_num, index, i, noa_index = 0;
- bool find_p2p_ie = false, find_p2p_ps_ie = false;
-
- pos = (u8 *)mgmt->u.beacon.variable;
- end = data + len;
- ie = NULL;
-
- while (pos + 1 < end) {
- if (pos + 2 + pos[1] > end)
- return;
-
- if (pos[0] == 221 && pos[1] > 4) {
- if (memcmp(&pos[2], p2p_oui_ie_type, 4) == 0) {
- ie = pos + 2 + 4;
- break;
- }
- }
- pos += 2 + pos[1];
- }
-
- if (!ie)
- return;
- find_p2p_ie = true;
- /*to find noa ie*/
- while (ie + 1 < end) {
- noa_len = READEF2BYTE((__le16 *)&ie[1]);
- if (ie + 3 + ie[1] > end)
- return;
-
- if (ie[0] == 12) {
- find_p2p_ps_ie = true;
- if ((noa_len - 2) % 13 != 0) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "P2P notice of absence: invalid length.%d\n",
- noa_len);
- return;
- }
- noa_num = (noa_len - 2) / 13;
- noa_index = ie[3];
- if (rtlpriv->psc.p2p_ps_info.p2p_ps_mode ==
- P2P_PS_NONE || noa_index != p2pinfo->noa_index) {
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
- "update NOA ie.\n");
- p2pinfo->noa_index = noa_index;
- p2pinfo->opp_ps = (ie[4] >> 7);
- p2pinfo->ctwindow = ie[4] & 0x7F;
- p2pinfo->noa_num = noa_num;
- index = 5;
- for (i = 0; i < noa_num; i++) {
- p2pinfo->noa_count_type[i] =
- READEF1BYTE(ie + index);
- index += 1;
- p2pinfo->noa_duration[i] =
- READEF4BYTE((__le32 *)ie + index);
- index += 4;
- p2pinfo->noa_interval[i] =
- READEF4BYTE((__le32 *)ie + index);
- index += 4;
- p2pinfo->noa_start_time[i] =
- READEF4BYTE((__le32 *)ie + index);
- index += 4;
- }
-
- if (p2pinfo->opp_ps == 1) {
- p2pinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
- /* Driver should wait LPS entering
- * CTWindow
- */
- if (rtlpriv->psc.fw_current_inpsmode)
- rtl_p2p_ps_cmd(hw,
- P2P_PS_ENABLE);
- } else if (p2pinfo->noa_num > 0) {
- p2pinfo->p2p_ps_mode = P2P_PS_NOA;
- rtl_p2p_ps_cmd(hw, P2P_PS_ENABLE);
- } else if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
- rtl_p2p_ps_cmd(hw, P2P_PS_DISABLE);
- }
- }
- break;
- }
- ie += 3 + noa_len;
- }
-
- if (find_p2p_ie) {
- if ((p2pinfo->p2p_ps_mode > P2P_PS_NONE) &&
- (!find_p2p_ps_ie))
- rtl_p2p_ps_cmd(hw, P2P_PS_DISABLE);
- }
-}
-
-static void rtl_p2p_action_ie(struct ieee80211_hw *hw, void *data,
- unsigned int len)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct ieee80211_mgmt *mgmt = data;
- struct rtl_p2p_ps_info *p2pinfo = &rtlpriv->psc.p2p_ps_info;
- u8 noa_num, index, i, noa_index = 0;
- u8 *pos, *end, *ie;
- u16 noa_len;
- static u8 p2p_oui_ie_type[4] = {0x50, 0x6f, 0x9a, 0x09};
-
- pos = (u8 *)&mgmt->u.action.category;
- end = data + len;
- ie = NULL;
-
- if (pos[0] == 0x7f) {
- if (memcmp(&pos[1], p2p_oui_ie_type, 4) == 0)
- ie = pos + 3 + 4;
- }
-
- if (!ie)
- return;
-
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "action frame find P2P IE.\n");
- /*to find noa ie*/
- while (ie + 1 < end) {
- noa_len = READEF2BYTE((__le16 *)&ie[1]);
- if (ie + 3 + ie[1] > end)
- return;
-
- if (ie[0] == 12) {
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "find NOA IE.\n");
- RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_LOUD, "noa ie ",
- ie, noa_len);
- if ((noa_len - 2) % 13 != 0) {
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
- "P2P notice of absence: invalid length.%d\n",
- noa_len);
- return;
- }
- noa_num = (noa_len - 2) / 13;
- noa_index = ie[3];
- if (rtlpriv->psc.p2p_ps_info.p2p_ps_mode ==
- P2P_PS_NONE || noa_index != p2pinfo->noa_index) {
- p2pinfo->noa_index = noa_index;
- p2pinfo->opp_ps = (ie[4] >> 7);
- p2pinfo->ctwindow = ie[4] & 0x7F;
- p2pinfo->noa_num = noa_num;
- index = 5;
- for (i = 0; i < noa_num; i++) {
- p2pinfo->noa_count_type[i] =
- READEF1BYTE(ie + index);
- index += 1;
- p2pinfo->noa_duration[i] =
- READEF4BYTE((__le32 *)ie + index);
- index += 4;
- p2pinfo->noa_interval[i] =
- READEF4BYTE((__le32 *)ie + index);
- index += 4;
- p2pinfo->noa_start_time[i] =
- READEF4BYTE((__le32 *)ie + index);
- index += 4;
- }
-
- if (p2pinfo->opp_ps == 1) {
- p2pinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
- /* Driver should wait LPS entering
- * CTWindow
- */
- if (rtlpriv->psc.fw_current_inpsmode)
- rtl_p2p_ps_cmd(hw,
- P2P_PS_ENABLE);
- } else if (p2pinfo->noa_num > 0) {
- p2pinfo->p2p_ps_mode = P2P_PS_NOA;
- rtl_p2p_ps_cmd(hw, P2P_PS_ENABLE);
- } else if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
- rtl_p2p_ps_cmd(hw, P2P_PS_DISABLE);
- }
- }
- break;
- }
- ie += 3 + noa_len;
- }
-}
-
-void rtl_p2p_ps_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
- struct rtl_p2p_ps_info *p2pinfo = &rtlpriv->psc.p2p_ps_info;
-
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "p2p state %x\n", p2p_ps_state);
- switch (p2p_ps_state) {
- case P2P_PS_DISABLE:
- p2pinfo->p2p_ps_state = p2p_ps_state;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
- &p2p_ps_state);
- p2pinfo->noa_index = 0;
- p2pinfo->ctwindow = 0;
- p2pinfo->opp_ps = 0;
- p2pinfo->noa_num = 0;
- p2pinfo->p2p_ps_mode = P2P_PS_NONE;
- if (rtlps->fw_current_inpsmode) {
- if (rtlps->smart_ps == 0) {
- rtlps->smart_ps = 2;
- rtlpriv->cfg->ops->set_hw_reg(hw,
- HW_VAR_H2C_FW_PWRMODE,
- &rtlps->pwr_mode);
- }
- }
- break;
- case P2P_PS_ENABLE:
- if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
- p2pinfo->p2p_ps_state = p2p_ps_state;
-
- if (p2pinfo->ctwindow > 0) {
- if (rtlps->smart_ps != 0) {
- rtlps->smart_ps = 0;
- rtlpriv->cfg->ops->set_hw_reg(hw,
- HW_VAR_H2C_FW_PWRMODE,
- &rtlps->pwr_mode);
- }
- }
- rtlpriv->cfg->ops->set_hw_reg(hw,
- HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
- &p2p_ps_state);
- }
- break;
- case P2P_PS_SCAN:
- case P2P_PS_SCAN_DONE:
- case P2P_PS_ALLSTASLEEP:
- if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
- p2pinfo->p2p_ps_state = p2p_ps_state;
- rtlpriv->cfg->ops->set_hw_reg(hw,
- HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
- &p2p_ps_state);
- }
- break;
- default:
- break;
- }
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
- "ctwindow %x oppps %x\n",
- p2pinfo->ctwindow, p2pinfo->opp_ps);
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
- "count %x duration %x index %x interval %x start time %x noa num %x\n",
- p2pinfo->noa_count_type[0],
- p2pinfo->noa_duration[0],
- p2pinfo->noa_index,
- p2pinfo->noa_interval[0],
- p2pinfo->noa_start_time[0],
- p2pinfo->noa_num);
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "end\n");
-}
-
-void rtl_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct ieee80211_hdr *hdr = data;
-
- if (!mac->p2p)
- return;
- if (mac->link_state != MAC80211_LINKED)
- return;
- /* min. beacon length + FCS_LEN */
- if (len <= 40 + FCS_LEN)
- return;
-
- /* and only beacons from the associated BSSID, please */
- if (!ether_addr_equal_64bits(hdr->addr3, rtlpriv->mac80211.bssid))
- return;
-
- /* check if this really is a beacon */
- if (!(ieee80211_is_beacon(hdr->frame_control) ||
- ieee80211_is_probe_resp(hdr->frame_control) ||
- ieee80211_is_action(hdr->frame_control)))
- return;
-
- if (ieee80211_is_action(hdr->frame_control))
- rtl_p2p_action_ie(hw, data, len - FCS_LEN);
- else
- rtl_p2p_noa_ie(hw, data, len - FCS_LEN);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __REALTEK_RTL_PCI_PS_H__
-#define __REALTEK_RTL_PCI_PS_H__
-
-#define MAX_SW_LPS_SLEEP_INTV 5
-
-bool rtl_ps_enable_nic(struct ieee80211_hw *hw);
-bool rtl_ps_disable_nic(struct ieee80211_hw *hw);
-void rtl_ips_nic_off(struct ieee80211_hw *hw);
-void rtl_ips_nic_on(struct ieee80211_hw *hw);
-void rtl_ips_nic_off_wq_callback(void *data);
-void rtl_lps_enter(struct ieee80211_hw *hw);
-void rtl_lps_leave(struct ieee80211_hw *hw);
-
-void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode);
-
-void rtl_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len);
-void rtl_swlps_wq_callback(void *data);
-void rtl_swlps_rfon_wq_callback(void *data);
-void rtl_swlps_rf_awake(struct ieee80211_hw *hw);
-void rtl_swlps_rf_sleep(struct ieee80211_hw *hw);
-void rtl_p2p_ps_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
-void rtl_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len);
-void rtl_lps_change_work_callback(struct work_struct *work);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL8723E_PWRSEQCMD_H__
-#define __RTL8723E_PWRSEQCMD_H__
-
-#include "wifi.h"
-/*---------------------------------------------
- * 3 The value of cmd: 4 bits
- *---------------------------------------------
- */
-#define PWR_CMD_READ 0x00
-#define PWR_CMD_WRITE 0x01
-#define PWR_CMD_POLLING 0x02
-#define PWR_CMD_DELAY 0x03
-#define PWR_CMD_END 0x04
-
-/* define the base address of each block */
-#define PWR_BASEADDR_MAC 0x00
-#define PWR_BASEADDR_USB 0x01
-#define PWR_BASEADDR_PCIE 0x02
-#define PWR_BASEADDR_SDIO 0x03
-
-#define PWR_INTF_SDIO_MSK BIT(0)
-#define PWR_INTF_USB_MSK BIT(1)
-#define PWR_INTF_PCI_MSK BIT(2)
-#define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-
-#define PWR_FAB_TSMC_MSK BIT(0)
-#define PWR_FAB_UMC_MSK BIT(1)
-#define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-
-#define PWR_CUT_TESTCHIP_MSK BIT(0)
-#define PWR_CUT_A_MSK BIT(1)
-#define PWR_CUT_B_MSK BIT(2)
-#define PWR_CUT_C_MSK BIT(3)
-#define PWR_CUT_D_MSK BIT(4)
-#define PWR_CUT_E_MSK BIT(5)
-#define PWR_CUT_F_MSK BIT(6)
-#define PWR_CUT_G_MSK BIT(7)
-#define PWR_CUT_ALL_MSK 0xFF
-
-enum pwrseq_delay_unit {
- PWRSEQ_DELAY_US,
- PWRSEQ_DELAY_MS,
-};
-
-struct wlan_pwr_cfg {
- u16 offset;
- u8 cut_msk;
- u8 fab_msk:4;
- u8 interface_msk:4;
- u8 base:4;
- u8 cmd:4;
- u8 msk;
- u8 value;
-};
-
-#define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset)
-#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk)
-#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk)
-#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk)
-#define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base)
-#define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd)
-#define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk)
-#define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value)
-
-bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
- u8 fab_version, u8 interface_type,
- struct wlan_pwr_cfg pwrcfgcmd[]);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "wifi.h"
-#include "base.h"
-#include "rc.h"
-
-/*
- *Finds the highest rate index we can use
- *if skb is special data like DHCP/EAPOL, we set should
- *it to lowest rate CCK_1M, otherwise we set rate to
- *highest rate based on wireless mode used for iwconfig
- *show Tx rate.
- */
-static u8 _rtl_rc_get_highest_rix(struct rtl_priv *rtlpriv,
- struct ieee80211_sta *sta,
- struct sk_buff *skb, bool not_data)
-{
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_sta_info *sta_entry = NULL;
- u16 wireless_mode = 0;
- u8 nss; /* NSS -1 */
-
- if (get_rf_type(rtlphy) >= RF_4T4R)
- nss = 3;
- else if (get_rf_type(rtlphy) >= RF_3T3R)
- nss = 2;
- else if (get_rf_type(rtlphy) >= RF_2T2R)
- nss = 1;
- else
- nss = 0;
-
- /*
- *this rate is no use for true rate, firmware
- *will control rate at all it just used for
- *1.show in iwconfig in B/G mode
- *2.in rtl_get_tcb_desc when we check rate is
- * 1M we will not use FW rate but user rate.
- */
-
- if (sta) {
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- wireless_mode = sta_entry->wireless_mode;
- }
-
- if (rtl_is_special_data(rtlpriv->mac80211.hw, skb, true, false) ||
- not_data) {
- return 0;
- }
- if (rtlhal->current_bandtype == BAND_ON_2_4G) {
- if (wireless_mode == WIRELESS_MODE_B) {
- return B_MODE_MAX_RIX;
- } else if (wireless_mode == WIRELESS_MODE_G) {
- return G_MODE_MAX_RIX;
- } else if (wireless_mode == WIRELESS_MODE_N_24G) {
- if (nss == 0)
- return N_MODE_MCS7_RIX;
- else
- return N_MODE_MCS15_RIX;
- } else if (wireless_mode == WIRELESS_MODE_AC_24G) {
- if (sta->bandwidth == IEEE80211_STA_RX_BW_20)
- return AC_MODE_MCS8_RIX | (nss << 4);
- else
- return AC_MODE_MCS9_RIX | (nss << 4);
- }
- return 0;
- }
- if (wireless_mode == WIRELESS_MODE_A) {
- return A_MODE_MAX_RIX;
- } else if (wireless_mode == WIRELESS_MODE_N_5G) {
- if (nss == 0)
- return N_MODE_MCS7_RIX;
- else
- return N_MODE_MCS15_RIX;
- } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
- if (sta->bandwidth == IEEE80211_STA_RX_BW_20)
- return AC_MODE_MCS8_RIX | (nss << 4);
- else
- return AC_MODE_MCS9_RIX | (nss << 4);
- }
- return 0;
-}
-
-static void _rtl_rc_rate_set_series(struct rtl_priv *rtlpriv,
- struct ieee80211_sta *sta,
- struct ieee80211_tx_rate *rate,
- struct ieee80211_tx_rate_control *txrc,
- u8 tries, s8 rix, int rtsctsenable,
- bool not_data)
-{
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- struct rtl_sta_info *sta_entry = NULL;
- u16 wireless_mode = 0;
- u8 sgi_20 = 0, sgi_40 = 0, sgi_80 = 0;
-
- if (sta) {
- sgi_20 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20;
- sgi_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40;
- sgi_80 = sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80;
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- wireless_mode = sta_entry->wireless_mode;
- }
- rate->count = tries;
- rate->idx = rix >= 0x00 ? rix : 0x00;
- if ((rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE ||
- rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8822BE) &&
- wireless_mode == WIRELESS_MODE_AC_5G)
- rate->idx |= 0x10;/*2NSS for 8812AE, 8822BE*/
-
- if (!not_data) {
- if (txrc->short_preamble)
- rate->flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
- if (mac->opmode == NL80211_IFTYPE_AP ||
- mac->opmode == NL80211_IFTYPE_ADHOC) {
- if (sta && (sta->ht_cap.cap &
- IEEE80211_HT_CAP_SUP_WIDTH_20_40))
- rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
- if (sta && sta->vht_cap.vht_supported)
- rate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH;
- } else {
- if (mac->bw_80)
- rate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH;
- else if (mac->bw_40)
- rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
- }
-
- if (sgi_20 || sgi_40 || sgi_80)
- rate->flags |= IEEE80211_TX_RC_SHORT_GI;
- if (sta && sta->ht_cap.ht_supported &&
- (wireless_mode == WIRELESS_MODE_N_5G ||
- wireless_mode == WIRELESS_MODE_N_24G))
- rate->flags |= IEEE80211_TX_RC_MCS;
- if (sta && sta->vht_cap.vht_supported &&
- (wireless_mode == WIRELESS_MODE_AC_5G ||
- wireless_mode == WIRELESS_MODE_AC_24G ||
- wireless_mode == WIRELESS_MODE_AC_ONLY))
- rate->flags |= IEEE80211_TX_RC_VHT_MCS;
- }
-}
-
-static void rtl_get_rate(void *ppriv, struct ieee80211_sta *sta,
- void *priv_sta,
- struct ieee80211_tx_rate_control *txrc)
-{
- struct rtl_priv *rtlpriv = ppriv;
- struct sk_buff *skb = txrc->skb;
- struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
- struct ieee80211_tx_rate *rates = tx_info->control.rates;
- __le16 fc = rtl_get_fc(skb);
- u8 try_per_rate, i, rix;
- bool not_data = !ieee80211_is_data(fc);
-
- if (rate_control_send_low(sta, priv_sta, txrc))
- return;
-
- rix = _rtl_rc_get_highest_rix(rtlpriv, sta, skb, not_data);
- try_per_rate = 1;
- _rtl_rc_rate_set_series(rtlpriv, sta, &rates[0], txrc,
- try_per_rate, rix, 1, not_data);
-
- if (!not_data) {
- for (i = 1; i < 4; i++)
- _rtl_rc_rate_set_series(rtlpriv, sta, &rates[i],
- txrc, i, (rix - i), 1,
- not_data);
- }
-}
-
-static bool _rtl_tx_aggr_check(struct rtl_priv *rtlpriv,
- struct rtl_sta_info *sta_entry, u16 tid)
-{
- struct rtl_mac *mac = rtl_mac(rtlpriv);
-
- if (mac->act_scanning)
- return false;
-
- if (mac->opmode == NL80211_IFTYPE_STATION &&
- mac->cnt_after_linked < 3)
- return false;
-
- if (sta_entry->tids[tid].agg.agg_state == RTL_AGG_STOP)
- return true;
-
- return false;
-}
-
-/*mac80211 Rate Control callbacks*/
-static void rtl_tx_status(void *ppriv,
- struct ieee80211_supported_band *sband,
- struct ieee80211_sta *sta, void *priv_sta,
- struct sk_buff *skb)
-{
- struct rtl_priv *rtlpriv = ppriv;
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
- __le16 fc = rtl_get_fc(skb);
- struct rtl_sta_info *sta_entry;
-
- if (!priv_sta || !ieee80211_is_data(fc))
- return;
-
- if (rtl_is_special_data(mac->hw, skb, true, true))
- return;
-
- if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
- is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
- return;
-
- if (sta) {
- /* Check if aggregation has to be enabled for this tid */
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- if (sta->ht_cap.ht_supported &&
- !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
- if (ieee80211_is_data_qos(fc)) {
- u8 tid = rtl_get_tid(skb);
-
- if (_rtl_tx_aggr_check(rtlpriv, sta_entry,
- tid)) {
- sta_entry->tids[tid].agg.agg_state =
- RTL_AGG_PROGRESS;
- ieee80211_start_tx_ba_session(sta, tid,
- 5000);
- }
- }
- }
- }
-}
-
-static void rtl_rate_init(void *ppriv,
- struct ieee80211_supported_band *sband,
- struct cfg80211_chan_def *chandef,
- struct ieee80211_sta *sta, void *priv_sta)
-{
-}
-
-static void rtl_rate_update(void *ppriv,
- struct ieee80211_supported_band *sband,
- struct cfg80211_chan_def *chandef,
- struct ieee80211_sta *sta, void *priv_sta,
- u32 changed)
-{
-}
-
-static void *rtl_rate_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- return rtlpriv;
-}
-
-static void rtl_rate_free(void *rtlpriv)
-{
-}
-
-static void *rtl_rate_alloc_sta(void *ppriv,
- struct ieee80211_sta *sta, gfp_t gfp)
-{
- struct rtl_priv *rtlpriv = ppriv;
- struct rtl_rate_priv *rate_priv;
-
- rate_priv = kzalloc(sizeof(*rate_priv), gfp);
- if (!rate_priv)
- return NULL;
-
- rtlpriv->rate_priv = rate_priv;
-
- return rate_priv;
-}
-
-static void rtl_rate_free_sta(void *rtlpriv,
- struct ieee80211_sta *sta, void *priv_sta)
-{
- struct rtl_rate_priv *rate_priv = priv_sta;
-
- kfree(rate_priv);
-}
-
-static const struct rate_control_ops rtl_rate_ops = {
- .name = "rtl_rc",
- .alloc = rtl_rate_alloc,
- .free = rtl_rate_free,
- .alloc_sta = rtl_rate_alloc_sta,
- .free_sta = rtl_rate_free_sta,
- .rate_init = rtl_rate_init,
- .rate_update = rtl_rate_update,
- .tx_status = rtl_tx_status,
- .get_rate = rtl_get_rate,
-};
-
-int rtl_rate_control_register(void)
-{
- return ieee80211_rate_control_register(&rtl_rate_ops);
-}
-
-void rtl_rate_control_unregister(void)
-{
- ieee80211_rate_control_unregister(&rtl_rate_ops);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_RC_H__
-#define __RTL_RC_H__
-
-#define B_MODE_MAX_RIX 3
-#define G_MODE_MAX_RIX 11
-#define A_MODE_MAX_RIX 7
-
-/* in mac80211 mcs0-mcs15 is idx0-idx15*/
-#define N_MODE_MCS7_RIX 7
-#define N_MODE_MCS15_RIX 15
-
-/* in mac80211 vht mcs0-9 is in [3:0], nss is in [:4] */
-#define AC_MODE_MCS7_RIX 7
-#define AC_MODE_MCS8_RIX 8
-#define AC_MODE_MCS9_RIX 9
-
-struct rtl_rate_priv {
- u8 ht_cap;
-};
-
-int rtl_rate_control_register(void);
-void rtl_rate_control_unregister(void);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "wifi.h"
-#include "regd.h"
-
-static struct country_code_to_enum_rd allcountries[] = {
- {COUNTRY_CODE_FCC, "US"},
- {COUNTRY_CODE_IC, "US"},
- {COUNTRY_CODE_ETSI, "EC"},
- {COUNTRY_CODE_SPAIN, "EC"},
- {COUNTRY_CODE_FRANCE, "EC"},
- {COUNTRY_CODE_MKK, "JP"},
- {COUNTRY_CODE_MKK1, "JP"},
- {COUNTRY_CODE_ISRAEL, "EC"},
- {COUNTRY_CODE_TELEC, "JP"},
- {COUNTRY_CODE_MIC, "JP"},
- {COUNTRY_CODE_GLOBAL_DOMAIN, "JP"},
- {COUNTRY_CODE_WORLD_WIDE_13, "EC"},
- {COUNTRY_CODE_TELEC_NETGEAR, "EC"},
- {COUNTRY_CODE_WORLD_WIDE_13_5G_ALL, "US"},
-};
-
-/*Only these channels all allow active
- *scan on all world regulatory domains
- */
-#define RTL819x_2GHZ_CH01_11 \
- REG_RULE(2412 - 10, 2462 + 10, 40, 0, 20, 0)
-
-/*We enable active scan on these a case
- *by case basis by regulatory domain
- */
-#define RTL819x_2GHZ_CH12_13 \
- REG_RULE(2467 - 10, 2472 + 10, 40, 0, 20,\
- NL80211_RRF_PASSIVE_SCAN)
-
-#define RTL819x_2GHZ_CH14 \
- REG_RULE(2484 - 10, 2484 + 10, 40, 0, 20, \
- NL80211_RRF_PASSIVE_SCAN | \
- NL80211_RRF_NO_OFDM)
-
-/* 5G chan 36 - chan 64*/
-#define RTL819x_5GHZ_5150_5350 \
- REG_RULE(5150 - 10, 5350 + 10, 80, 0, 30, 0)
-/* 5G chan 100 - chan 165*/
-#define RTL819x_5GHZ_5470_5850 \
- REG_RULE(5470 - 10, 5850 + 10, 80, 0, 30, 0)
-/* 5G chan 149 - chan 165*/
-#define RTL819x_5GHZ_5725_5850 \
- REG_RULE(5725 - 10, 5850 + 10, 80, 0, 30, 0)
-
-#define RTL819x_5GHZ_ALL \
- (RTL819x_5GHZ_5150_5350, RTL819x_5GHZ_5470_5850)
-
-static const struct ieee80211_regdomain rtl_regdom_11 = {
- .n_reg_rules = 1,
- .alpha2 = "99",
- .reg_rules = {
- RTL819x_2GHZ_CH01_11,
- }
-};
-
-static const struct ieee80211_regdomain rtl_regdom_12_13 = {
- .n_reg_rules = 2,
- .alpha2 = "99",
- .reg_rules = {
- RTL819x_2GHZ_CH01_11,
- RTL819x_2GHZ_CH12_13,
- }
-};
-
-static const struct ieee80211_regdomain rtl_regdom_no_midband = {
- .n_reg_rules = 3,
- .alpha2 = "99",
- .reg_rules = {
- RTL819x_2GHZ_CH01_11,
- RTL819x_5GHZ_5150_5350,
- RTL819x_5GHZ_5725_5850,
- }
-};
-
-static const struct ieee80211_regdomain rtl_regdom_60_64 = {
- .n_reg_rules = 3,
- .alpha2 = "99",
- .reg_rules = {
- RTL819x_2GHZ_CH01_11,
- RTL819x_2GHZ_CH12_13,
- RTL819x_5GHZ_5725_5850,
- }
-};
-
-static const struct ieee80211_regdomain rtl_regdom_14_60_64 = {
- .n_reg_rules = 4,
- .alpha2 = "99",
- .reg_rules = {
- RTL819x_2GHZ_CH01_11,
- RTL819x_2GHZ_CH12_13,
- RTL819x_2GHZ_CH14,
- RTL819x_5GHZ_5725_5850,
- }
-};
-
-static const struct ieee80211_regdomain rtl_regdom_12_13_5g_all = {
- .n_reg_rules = 4,
- .alpha2 = "99",
- .reg_rules = {
- RTL819x_2GHZ_CH01_11,
- RTL819x_2GHZ_CH12_13,
- RTL819x_5GHZ_5150_5350,
- RTL819x_5GHZ_5470_5850,
- }
-};
-
-static const struct ieee80211_regdomain rtl_regdom_14 = {
- .n_reg_rules = 3,
- .alpha2 = "99",
- .reg_rules = {
- RTL819x_2GHZ_CH01_11,
- RTL819x_2GHZ_CH12_13,
- RTL819x_2GHZ_CH14,
- }
-};
-
-static bool _rtl_is_radar_freq(u16 center_freq)
-{
- return center_freq >= 5260 && center_freq <= 5700;
-}
-
-static void _rtl_reg_apply_beaconing_flags(struct wiphy *wiphy,
- enum nl80211_reg_initiator initiator)
-{
- enum nl80211_band band;
- struct ieee80211_supported_band *sband;
- const struct ieee80211_reg_rule *reg_rule;
- struct ieee80211_channel *ch;
- unsigned int i;
-
- for (band = 0; band < NUM_NL80211_BANDS; band++) {
- if (!wiphy->bands[band])
- continue;
-
- sband = wiphy->bands[band];
-
- for (i = 0; i < sband->n_channels; i++) {
- ch = &sband->channels[i];
- if (_rtl_is_radar_freq(ch->center_freq) ||
- (ch->flags & IEEE80211_CHAN_RADAR))
- continue;
- if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) {
- reg_rule = freq_reg_info(wiphy,
- ch->center_freq);
- if (IS_ERR(reg_rule))
- continue;
- /*
- *If 11d had a rule for this channel ensure
- *we enable adhoc/beaconing if it allows us to
- *use it. Note that we would have disabled it
- *by applying our static world regdomain by
- *default during init, prior to calling our
- *regulatory_hint().
- */
-
- if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
- ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
- if (!(reg_rule->flags &
- NL80211_RRF_PASSIVE_SCAN))
- ch->flags &=
- ~IEEE80211_CHAN_PASSIVE_SCAN;
- } else {
- if (ch->beacon_found)
- ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN);
- }
- }
- }
-}
-
-/* Allows active scan scan on Ch 12 and 13 */
-static void _rtl_reg_apply_active_scan_flags(struct wiphy *wiphy,
- enum nl80211_reg_initiator
- initiator)
-{
- struct ieee80211_supported_band *sband;
- struct ieee80211_channel *ch;
- const struct ieee80211_reg_rule *reg_rule;
-
- if (!wiphy->bands[NL80211_BAND_2GHZ])
- return;
- sband = wiphy->bands[NL80211_BAND_2GHZ];
-
- /*
- *If no country IE has been received always enable active scan
- *on these channels. This is only done for specific regulatory SKUs
- */
- if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
- ch = &sband->channels[11]; /* CH 12 */
- if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
- ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
- ch = &sband->channels[12]; /* CH 13 */
- if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
- ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
- return;
- }
-
- /*If a country IE has been received check its rule for this
- *channel first before enabling active scan. The passive scan
- *would have been enforced by the initial processing of our
- *custom regulatory domain.
- */
-
- ch = &sband->channels[11]; /* CH 12 */
- reg_rule = freq_reg_info(wiphy, ch->center_freq);
- if (!IS_ERR(reg_rule)) {
- if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
- if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
- ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
- }
-
- ch = &sband->channels[12]; /* CH 13 */
- reg_rule = freq_reg_info(wiphy, ch->center_freq);
- if (!IS_ERR(reg_rule)) {
- if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
- if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
- ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
- }
-}
-
-/*
- *Always apply Radar/DFS rules on
- *freq range 5260 MHz - 5700 MHz
- */
-static void _rtl_reg_apply_radar_flags(struct wiphy *wiphy)
-{
- struct ieee80211_supported_band *sband;
- struct ieee80211_channel *ch;
- unsigned int i;
-
- if (!wiphy->bands[NL80211_BAND_5GHZ])
- return;
-
- sband = wiphy->bands[NL80211_BAND_5GHZ];
-
- for (i = 0; i < sband->n_channels; i++) {
- ch = &sband->channels[i];
- if (!_rtl_is_radar_freq(ch->center_freq))
- continue;
-
- /*
- *We always enable radar detection/DFS on this
- *frequency range. Additionally we also apply on
- *this frequency range:
- *- If STA mode does not yet have DFS supports disable
- * active scanning
- *- If adhoc mode does not support DFS yet then disable
- * adhoc in the frequency.
- *- If AP mode does not yet support radar detection/DFS
- *do not allow AP mode
- */
- if (!(ch->flags & IEEE80211_CHAN_DISABLED))
- ch->flags |= IEEE80211_CHAN_RADAR |
- IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN;
- }
-}
-
-static void _rtl_reg_apply_world_flags(struct wiphy *wiphy,
- enum nl80211_reg_initiator initiator,
- struct rtl_regulatory *reg)
-{
- _rtl_reg_apply_beaconing_flags(wiphy, initiator);
- _rtl_reg_apply_active_scan_flags(wiphy, initiator);
-}
-
-static void _rtl_dump_channel_map(struct wiphy *wiphy)
-{
- enum nl80211_band band;
- struct ieee80211_supported_band *sband;
- struct ieee80211_channel *ch;
- unsigned int i;
-
- for (band = 0; band < NUM_NL80211_BANDS; band++) {
- if (!wiphy->bands[band])
- continue;
- sband = wiphy->bands[band];
- for (i = 0; i < sband->n_channels; i++)
- ch = &sband->channels[i];
- }
-}
-
-static int _rtl_reg_notifier_apply(struct wiphy *wiphy,
- struct regulatory_request *request,
- struct rtl_regulatory *reg)
-{
- /* We always apply this */
- _rtl_reg_apply_radar_flags(wiphy);
-
- switch (request->initiator) {
- case NL80211_REGDOM_SET_BY_DRIVER:
- case NL80211_REGDOM_SET_BY_CORE:
- case NL80211_REGDOM_SET_BY_USER:
- break;
- case NL80211_REGDOM_SET_BY_COUNTRY_IE:
- _rtl_reg_apply_world_flags(wiphy, request->initiator, reg);
- break;
- }
-
- _rtl_dump_channel_map(wiphy);
-
- return 0;
-}
-
-static const struct ieee80211_regdomain *_rtl_regdomain_select(
- struct rtl_regulatory *reg)
-{
- switch (reg->country_code) {
- case COUNTRY_CODE_FCC:
- return &rtl_regdom_no_midband;
- case COUNTRY_CODE_IC:
- return &rtl_regdom_11;
- case COUNTRY_CODE_TELEC_NETGEAR:
- return &rtl_regdom_60_64;
- case COUNTRY_CODE_ETSI:
- case COUNTRY_CODE_SPAIN:
- case COUNTRY_CODE_FRANCE:
- case COUNTRY_CODE_ISRAEL:
- return &rtl_regdom_12_13;
- case COUNTRY_CODE_MKK:
- case COUNTRY_CODE_MKK1:
- case COUNTRY_CODE_TELEC:
- case COUNTRY_CODE_MIC:
- return &rtl_regdom_14_60_64;
- case COUNTRY_CODE_GLOBAL_DOMAIN:
- return &rtl_regdom_14;
- case COUNTRY_CODE_WORLD_WIDE_13:
- case COUNTRY_CODE_WORLD_WIDE_13_5G_ALL:
- return &rtl_regdom_12_13_5g_all;
- default:
- return &rtl_regdom_no_midband;
- }
-}
-
-static int _rtl_regd_init_wiphy(struct rtl_regulatory *reg,
- struct wiphy *wiphy,
- void (*reg_notifier)(struct wiphy *wiphy,
- struct regulatory_request *
- request))
-{
- const struct ieee80211_regdomain *regd;
-
- wiphy->reg_notifier = reg_notifier;
-
- wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;
- wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG;
- wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS;
- regd = _rtl_regdomain_select(reg);
- wiphy_apply_custom_regulatory(wiphy, regd);
- _rtl_reg_apply_radar_flags(wiphy);
- _rtl_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg);
- return 0;
-}
-
-static struct country_code_to_enum_rd *_rtl_regd_find_country(u16 countrycode)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(allcountries); i++) {
- if (allcountries[i].countrycode == countrycode)
- return &allcountries[i];
- }
- return NULL;
-}
-
-static u8 channel_plan_to_country_code(u8 channelplan)
-{
- switch (channelplan) {
- case 0x20:
- case 0x21:
- return COUNTRY_CODE_WORLD_WIDE_13;
- case 0x22:
- return COUNTRY_CODE_IC;
- case 0x25:
- return COUNTRY_CODE_ETSI;
- case 0x32:
- return COUNTRY_CODE_TELEC_NETGEAR;
- case 0x41:
- return COUNTRY_CODE_GLOBAL_DOMAIN;
- case 0x7f:
- return COUNTRY_CODE_WORLD_WIDE_13_5G_ALL;
- default:
- return COUNTRY_CODE_MAX; /*Error*/
- }
-}
-
-int rtl_regd_init(struct ieee80211_hw *hw,
- void (*reg_notifier)(struct wiphy *wiphy,
- struct regulatory_request *request))
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct wiphy *wiphy = hw->wiphy;
- struct country_code_to_enum_rd *country = NULL;
-
- if (!wiphy)
- return -EINVAL;
-
- /* init country_code from efuse channel plan */
- rtlpriv->regd.country_code =
- channel_plan_to_country_code(rtlpriv->efuse.channel_plan);
-
- RT_TRACE(rtlpriv, COMP_REGD, DBG_DMESG,
- "rtl: EEPROM regdomain: 0x%0x country code: %d\n",
- rtlpriv->efuse.channel_plan, rtlpriv->regd.country_code);
-
- if (rtlpriv->regd.country_code >= COUNTRY_CODE_MAX) {
- RT_TRACE(rtlpriv, COMP_REGD, DBG_DMESG,
- "rtl: EEPROM indicates invalid country code, world wide 13 should be used\n");
-
- rtlpriv->regd.country_code = COUNTRY_CODE_WORLD_WIDE_13;
- }
-
- country = _rtl_regd_find_country(rtlpriv->regd.country_code);
-
- if (country) {
- rtlpriv->regd.alpha2[0] = country->iso_name[0];
- rtlpriv->regd.alpha2[1] = country->iso_name[1];
- } else {
- rtlpriv->regd.alpha2[0] = '0';
- rtlpriv->regd.alpha2[1] = '0';
- }
-
- RT_TRACE(rtlpriv, COMP_REGD, DBG_TRACE,
- "rtl: Country alpha2 being used: %c%c\n",
- rtlpriv->regd.alpha2[0], rtlpriv->regd.alpha2[1]);
-
- _rtl_regd_init_wiphy(&rtlpriv->regd, wiphy, reg_notifier);
-
- return 0;
-}
-
-void rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
-{
- struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- RT_TRACE(rtlpriv, COMP_REGD, DBG_LOUD, "\n");
-
- _rtl_reg_notifier_apply(wiphy, request, &rtlpriv->regd);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_REGD_H__
-#define __RTL_REGD_H__
-
-/* for kernel 3.14 , both value are changed to IEEE80211_CHAN_NO_IR*/
-#define IEEE80211_CHAN_NO_IBSS IEEE80211_CHAN_NO_IR
-#define IEEE80211_CHAN_PASSIVE_SCAN IEEE80211_CHAN_NO_IR
-
-struct country_code_to_enum_rd {
- u16 countrycode;
- const char *iso_name;
-};
-
-enum country_code_type_t {
- COUNTRY_CODE_FCC = 0,
- COUNTRY_CODE_IC = 1,
- COUNTRY_CODE_ETSI = 2,
- COUNTRY_CODE_SPAIN = 3,
- COUNTRY_CODE_FRANCE = 4,
- COUNTRY_CODE_MKK = 5,
- COUNTRY_CODE_MKK1 = 6,
- COUNTRY_CODE_ISRAEL = 7,
- COUNTRY_CODE_TELEC = 8,
- COUNTRY_CODE_MIC = 9,
- COUNTRY_CODE_GLOBAL_DOMAIN = 10,
- COUNTRY_CODE_WORLD_WIDE_13 = 11,
- COUNTRY_CODE_TELEC_NETGEAR = 12,
- COUNTRY_CODE_WORLD_WIDE_13_5G_ALL = 13,
-
- /*add new channel plan above this line */
- COUNTRY_CODE_MAX
-};
-
-int rtl_regd_init(struct ieee80211_hw *hw,
- void (*reg_notifier)(struct wiphy *wiphy,
- struct regulatory_request *request));
-void rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
-
-#endif
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-rtl8822be-objs := \
- fw.o \
- hw.o \
- led.o \
- phy.o \
- sw.o \
- trx.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL8822B_DEF_H__
-#define __RTL8822B_DEF_H__
-
-#define RX_DESC_NUM_8822BE 512
-
-#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
-#define HAL_PRIME_CHNL_OFFSET_LOWER 1
-#define HAL_PRIME_CHNL_OFFSET_UPPER 2
-
-#define RX_MPDU_QUEUE 0
-
-#define IS_HT_RATE(_rate) (_rate >= DESC_RATEMCS0)
-#define IS_CCK_RATE(_rate) (_rate >= DESC_RATE1M && _rate <= DESC_RATE11M)
-#define IS_OFDM_RATE(_rate) (_rate >= DESC_RATE6M && _rate <= DESC_RATE54M)
-#define IS_1T_RATE(_rate) \
- ((_rate >= DESC_RATE1M && _rate <= DESC_RATEMCS7) || \
- (_rate >= DESC_RATEVHT1SS_MCS0 && _rate <= DESC_RATEVHT1SS_MCS9))
-#define IS_2T_RATE(_rate) \
- ((_rate >= DESC_RATEMCS8 && _rate <= DESC_RATEMCS15) || \
- (_rate >= DESC_RATEVHT2SS_MCS0 && _rate <= DESC_RATEVHT2SS_MCS9))
-
-#define IS_1T_RATESEC(_rs) \
- ((_rs == CCK) || (_rs == OFDM) || (_rs == HT_MCS0_MCS7) || \
- (_rs == VHT_1SSMCS0_1SSMCS9))
-#define IS_2T_RATESEC(_rs) \
- ((_rs == HT_MCS8_MCS15) || (_rs == VHT_2SSMCS0_2SSMCS9))
-
-enum rx_packet_type {
- NORMAL_RX,
- C2H_PACKET,
-};
-
-enum rtl_desc_qsel {
- QSLT_BK = 0x2,
- QSLT_BE = 0x0,
- QSLT_VI = 0x5,
- QSLT_VO = 0x7,
- QSLT_BEACON = 0x10,
- QSLT_HIGH = 0x11,
- QSLT_MGNT = 0x12,
- QSLT_CMD = 0x13,
-};
-
-enum vht_data_sc {
- VHT_DATA_SC_DONOT_CARE = 0,
- VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
- VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
- VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
- VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
- VHT_DATA_SC_20_RECV1 = 5,
- VHT_DATA_SC_20_RECV2 = 6,
- VHT_DATA_SC_20_RECV3 = 7,
- VHT_DATA_SC_20_RECV4 = 8,
- VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
- VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
-};
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../wifi.h"
-#include "../pci.h"
-#include "../base.h"
-#include "reg.h"
-#include "def.h"
-#include "fw.h"
-
-static bool _rtl8822be_check_fw_read_last_h2c(struct ieee80211_hw *hw,
- u8 boxnum)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 val_hmetfr;
- bool result = false;
-
- val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR_8822B);
- if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
- result = true;
- return result;
-}
-
-static void _rtl8822be_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
- u32 cmd_len, u8 *cmdbuffer)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- u8 boxnum;
- u16 box_reg = 0, box_extreg = 0;
- u8 u1b_tmp;
- bool isfw_read;
- u8 buf_index = 0;
- bool bwrite_success = false;
- u8 wait_h2c_limmit = 100;
- u8 boxcontent[4], boxextcontent[4];
- u32 h2c_waitcounter = 0;
- unsigned long flag;
- u8 idx;
-
- /* 1. Prevent race condition in setting H2C cmd.
- * (copy from MgntActSet_RF_State().)
- */
- while (true) {
- spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
- if (rtlhal->h2c_setinprogress) {
- RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
- "H2C set in progress! wait..H2C_ID=%d.\n",
- element_id);
-
- while (rtlhal->h2c_setinprogress) {
- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
- flag);
- h2c_waitcounter++;
- RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
- "Wait 100 us (%d times)...\n",
- h2c_waitcounter);
- udelay(100);
-
- if (h2c_waitcounter > 1000)
- return;
- spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
- flag);
- }
- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
- } else {
- rtlhal->h2c_setinprogress = true;
- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
- break;
- }
- }
-
- while (!bwrite_success) {
- /* 2. Find the last BOX number which has been written. */
- boxnum = rtlhal->last_hmeboxnum;
- switch (boxnum) {
- case 0:
- box_reg = REG_HMEBOX0_8822B;
- box_extreg = REG_HMEBOX_E0_8822B;
- break;
- case 1:
- box_reg = REG_HMEBOX1_8822B;
- box_extreg = REG_HMEBOX_E1_8822B;
- break;
- case 2:
- box_reg = REG_HMEBOX2_8822B;
- box_extreg = REG_HMEBOX_E2_8822B;
- break;
- case 3:
- box_reg = REG_HMEBOX3_8822B;
- box_extreg = REG_HMEBOX_E3_8822B;
- break;
- default:
- RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case not process\n");
- break;
- }
-
- /* 3. Check if the box content is empty. */
- u1b_tmp = rtl_read_byte(rtlpriv, REG_CR_8822B);
-
- if (u1b_tmp == 0xea) {
- if (rtl_read_byte(rtlpriv, REG_TXDMA_STATUS_8822B) ==
- 0xea ||
- rtl_read_byte(rtlpriv, REG_TXPKT_EMPTY_8822B) ==
- 0xea)
- rtl_write_byte(rtlpriv, REG_SYS_CFG1_8822B + 3,
- 0xff);
-
- RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
- "REG_CR is unavaliable\n");
- break;
- }
-
- wait_h2c_limmit = 100;
- isfw_read = _rtl8822be_check_fw_read_last_h2c(hw, boxnum);
- while (!isfw_read) {
- wait_h2c_limmit--;
- if (wait_h2c_limmit == 0) {
- RT_TRACE(rtlpriv, COMP_CMD, DBG_WARNING,
- "Wait too long for FW clear MB%d!!!\n",
- boxnum);
- break;
- }
- udelay(10);
- isfw_read =
- _rtl8822be_check_fw_read_last_h2c(hw, boxnum);
- u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
- RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
- "Waiting for FW clear MB%d!!! 0x130 = %2x\n",
- boxnum, u1b_tmp);
- }
-
- /* If Fw has not read the last H2C cmd,
- * break and give up this H2C.
- */
- if (!isfw_read) {
- RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
- "Write H2C reg BOX[%d] fail,Fw don't read.\n",
- boxnum);
- break;
- }
- /* 4. Fill the H2C cmd into box */
- memset(boxcontent, 0, sizeof(boxcontent));
- memset(boxextcontent, 0, sizeof(boxextcontent));
- boxcontent[0] = element_id;
- RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
- "Write element_id box_reg(%4x) = %2x\n", box_reg,
- element_id);
-
- switch (cmd_len) {
- case 1:
- case 2:
- case 3:
- /*boxcontent[0] &= ~(BIT(7));*/
- memcpy((u8 *)(boxcontent) + 1, cmdbuffer + buf_index,
- cmd_len);
-
- for (idx = 0; idx < 4; idx++) {
- rtl_write_byte(rtlpriv, box_reg + idx,
- boxcontent[idx]);
- }
- break;
- case 4:
- case 5:
- case 6:
- case 7:
- /*boxcontent[0] |= (BIT(7));*/
- memcpy((u8 *)(boxextcontent), cmdbuffer + buf_index + 3,
- cmd_len - 3);
- memcpy((u8 *)(boxcontent) + 1, cmdbuffer + buf_index,
- 3);
-
- for (idx = 0; idx < 4; idx++) {
- rtl_write_byte(rtlpriv, box_extreg + idx,
- boxextcontent[idx]);
- }
-
- for (idx = 0; idx < 4; idx++) {
- rtl_write_byte(rtlpriv, box_reg + idx,
- boxcontent[idx]);
- }
- break;
- default:
- RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case not process\n");
- break;
- }
-
- bwrite_success = true;
-
- rtlhal->last_hmeboxnum = boxnum + 1;
- if (rtlhal->last_hmeboxnum == 4)
- rtlhal->last_hmeboxnum = 0;
-
- RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
- "pHalData->last_hmeboxnum = %d\n",
- rtlhal->last_hmeboxnum);
- }
-
- spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
- rtlhal->h2c_setinprogress = false;
- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
-
- RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
-}
-
-void rtl8822be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, u32 cmd_len,
- u8 *cmdbuffer)
-{
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 tmp_cmdbuf[8];
-
- if (!rtlhal->fw_ready) {
- WARN_ONCE(true,
- "return H2C cmd because of Fw download fail!!!\n");
- return;
- }
-
- memset(tmp_cmdbuf, 0, 8);
- memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
-
- RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
- "h2c cmd: len=%d %02X%02X%02X%02X %02X%02X%02X%02X\n", cmd_len,
- tmp_cmdbuf[2], tmp_cmdbuf[1], tmp_cmdbuf[0], element_id,
- tmp_cmdbuf[6], tmp_cmdbuf[5], tmp_cmdbuf[4], tmp_cmdbuf[3]);
-
- _rtl8822be_fill_h2c_command(hw, element_id, cmd_len, tmp_cmdbuf);
-}
-
-void rtl8822be_set_default_port_id_cmd(struct ieee80211_hw *hw)
-{
- u8 h2c_set_default_port_id[H2C_DEFAULT_PORT_ID_LEN];
-
- SET_H2CCMD_DFTPID_PORT_ID(h2c_set_default_port_id, 0);
- SET_H2CCMD_DFTPID_MAC_ID(h2c_set_default_port_id, 0);
-
- rtl8822be_fill_h2c_cmd(hw, H2C_8822B_DEFAULT_PORT_ID,
- H2C_DEFAULT_PORT_ID_LEN,
- h2c_set_default_port_id);
-}
-
-void rtl8822be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 u1_h2c_set_pwrmode[H2C_8822B_PWEMODE_LENGTH] = {0};
- static u8 prev_h2c[H2C_8822B_PWEMODE_LENGTH] = {0};
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- u8 rlbm, power_state = 0, byte5 = 0;
- u8 awake_intvl; /* DTIM = (awake_intvl - 1) */
- u8 smart_ps = 0;
- struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
- bool bt_ctrl_lps = (rtlpriv->cfg->ops->get_btc_status() ?
- btc_ops->btc_is_bt_ctrl_lps(rtlpriv) : false);
- bool bt_lps_on = (rtlpriv->cfg->ops->get_btc_status() ?
- btc_ops->btc_is_bt_lps_on(rtlpriv) : false);
-
- memset(u1_h2c_set_pwrmode, 0, H2C_8822B_PWEMODE_LENGTH);
-
- if (bt_ctrl_lps)
- mode = (bt_lps_on ? FW_PS_MIN_MODE : FW_PS_ACTIVE_MODE);
-
- RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, "FW LPS mode = %d (coex:%d)\n",
- mode, bt_ctrl_lps);
-
- switch (mode) {
- case FW_PS_MIN_MODE:
- rlbm = 0;
- awake_intvl = 2;
- smart_ps = ppsc->smart_ps;
- break;
- case FW_PS_MAX_MODE:
- rlbm = 1;
- awake_intvl = 2;
- smart_ps = ppsc->smart_ps;
- break;
- case FW_PS_DTIM_MODE:
- rlbm = 2;
- awake_intvl = ppsc->reg_max_lps_awakeintvl;
- /*
- * hw->conf.ps_dtim_period or mac->vif->bss_conf.dtim_period
- * is only used in swlps.
- */
- smart_ps = ppsc->smart_ps;
- break;
- case FW_PS_ACTIVE_MODE:
- rlbm = 0;
- awake_intvl = 1;
- break;
- default:
- rlbm = 2;
- awake_intvl = 4;
- smart_ps = ppsc->smart_ps;
- break;
- }
-
- if (rtlpriv->mac80211.p2p) {
- awake_intvl = 2;
- rlbm = 1;
- }
-
- if (mode == FW_PS_ACTIVE_MODE) {
- byte5 = 0x40;
- power_state = FW_PWR_STATE_ACTIVE;
- } else {
- if (bt_ctrl_lps) {
- byte5 = btc_ops->btc_get_lps_val(rtlpriv);
- power_state = btc_ops->btc_get_rpwm_val(rtlpriv);
-
- if (rlbm == 2 && (byte5 & BIT(4))) {
- /* Keep awake interval to 1 to prevent from
- * decreasing coex performance
- */
- awake_intvl = 2;
- rlbm = 2;
- }
- smart_ps = 0;
- } else {
- byte5 = 0x40;
- power_state = FW_PWR_STATE_RF_OFF;
- }
- }
-
- SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
- SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
- SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, smart_ps);
- SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode, awake_intvl);
- SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
- SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
- SET_H2CCMD_PWRMODE_PARM_BYTE5(u1_h2c_set_pwrmode, byte5);
-
- RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
- "rtl8822be_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
- u1_h2c_set_pwrmode, H2C_8822B_PWEMODE_LENGTH);
- if (rtlpriv->cfg->ops->get_btc_status())
- btc_ops->btc_record_pwr_mode(rtlpriv, u1_h2c_set_pwrmode,
- H2C_8822B_PWEMODE_LENGTH);
-
- if (!memcmp(prev_h2c, u1_h2c_set_pwrmode, H2C_8822B_PWEMODE_LENGTH))
- return;
- memcpy(prev_h2c, u1_h2c_set_pwrmode, H2C_8822B_PWEMODE_LENGTH);
-
- rtl8822be_set_default_port_id_cmd(hw);
- rtl8822be_fill_h2c_cmd(hw, H2C_8822B_SETPWRMODE,
- H2C_8822B_PWEMODE_LENGTH, u1_h2c_set_pwrmode);
-}
-
-void rtl8822be_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus)
-{
- u8 parm[4] = {0, 0, 0, 0};
- /* parm[0]: bit0=0-->Disconnect, bit0=1-->Connect
- * bit1=0-->update Media Status to MACID
- * bit1=1-->update Media Status from MACID to MACID_End
- * parm[1]: MACID, if this is INFRA_STA, MacID = 0
- * parm[2]: MACID_End
- * parm[3]: bit2-0: port ID
- */
-
- SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, mstatus);
- SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
-
- rtl8822be_fill_h2c_cmd(hw, H2C_8822B_MSRRPT, 4, parm);
-}
-
-static bool _rtl8822be_send_bcn_or_cmd_packet(struct ieee80211_hw *hw,
- struct sk_buff *skb, u8 hw_queue)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl8192_tx_ring *ring;
- struct rtl_tx_desc *pdesc;
- struct rtl_tx_buffer_desc *pbd_desc;
- unsigned long flags;
- struct sk_buff *pskb = NULL;
- u8 *pdesc_or_bddesc;
- dma_addr_t dma_addr;
-
- if (hw_queue != BEACON_QUEUE && hw_queue != H2C_QUEUE)
- return false;
-
- ring = &rtlpci->tx_ring[hw_queue];
-
- spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
-
- if (hw_queue == BEACON_QUEUE) {
- pdesc = &ring->desc[0];
- pbd_desc = &ring->buffer_desc[0];
- pdesc_or_bddesc = (u8 *)pbd_desc;
-
- /* free previous beacon queue */
- pskb = __skb_dequeue(&ring->queue);
-
- if (!pskb)
- goto free_prev_skb_done;
-
- dma_addr = rtlpriv->cfg->ops->get_desc(
- hw, (u8 *)pbd_desc, true, HW_DESC_TXBUFF_ADDR);
-
- pci_unmap_single(rtlpci->pdev, dma_addr, pskb->len,
- PCI_DMA_TODEVICE);
- kfree_skb(pskb);
-
-free_prev_skb_done:
- ;
-
- } else { /* hw_queue == TXCMD_QUEUE */
- if (rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "get_available_desc fail hw_queue=%d\n",
- hw_queue);
- spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
- flags);
- return false;
- }
-
- pdesc = &ring->desc[ring->cur_tx_wp];
- pbd_desc = &ring->buffer_desc[ring->cur_tx_wp];
- pdesc_or_bddesc = (u8 *)pdesc;
- }
-
- rtlpriv->cfg->ops->fill_tx_special_desc(hw, (u8 *)pdesc, (u8 *)pbd_desc,
- skb, hw_queue);
-
- __skb_queue_tail(&ring->queue, skb);
-
- rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc_or_bddesc, true,
- HW_DESC_OWN, (u8 *)&hw_queue);
-
- spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
-
- rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
-
- return true;
-}
-
-bool rtl8822b_halmac_cb_write_data_rsvd_page(struct rtl_priv *rtlpriv, u8 *buf,
- u32 size)
-{
- struct sk_buff *skb = NULL;
- u8 u1b_tmp;
- int count;
-
- skb = dev_alloc_skb(size);
- if (!skb)
- return false;
- memcpy((u8 *)skb_put(skb, size), buf, size);
-
- if (!_rtl8822be_send_bcn_or_cmd_packet(rtlpriv->hw, skb, BEACON_QUEUE))
- return false;
-
- /* These code isn't actually need, because halmac will check
- * BCN_VALID
- */
-
- /* Polling Beacon Queue to send Beacon */
- u1b_tmp = rtl_read_byte(rtlpriv, REG_RX_RXBD_NUM_8822B + 1);
- count = 0;
- while ((count < 20) && (u1b_tmp & BIT(4))) {
- count++;
- udelay(10);
- u1b_tmp = rtl_read_byte(rtlpriv, REG_RX_RXBD_NUM_8822B + 1);
- }
-
- if (count >= 20)
- pr_err("%s polling beacon fail\n", __func__);
-
- return true;
-}
-
-bool rtl8822b_halmac_cb_write_data_h2c(struct rtl_priv *rtlpriv, u8 *buf,
- u32 size)
-{
- struct sk_buff *skb = NULL;
-
- /* without GFP_DMA, pci_map_single() may not work */
- skb = __netdev_alloc_skb(NULL, size, GFP_ATOMIC | GFP_DMA);
- if (!skb)
- return false;
- memcpy((u8 *)skb_put(skb, size), buf, size);
-
- return _rtl8822be_send_bcn_or_cmd_packet(rtlpriv->hw, skb, H2C_QUEUE);
-}
-
-/* Rsvd page HALMAC_RSVD_DRV_PGNUM_8822B occupies 16 page (2048 byte) */
-#define BEACON_PG 0 /* ->1 */
-#define PSPOLL_PG 2
-#define NULL_PG 3
-#define PROBERSP_PG 4 /* ->5 */
-#define QOS_NULL_PG 6
-#define BT_QOS_NULL_PG 7
-
-#define TOTAL_RESERVED_PKT_LEN 1024
-
-static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {/* page size = 128 */
- /* page 0 beacon */
- 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
- 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x20, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x64, 0x00, 0x10, 0x04, 0x00, 0x05, 0x54, 0x65,
- 0x73, 0x74, 0x32, 0x01, 0x08, 0x82, 0x84, 0x0B,
- 0x16, 0x24, 0x30, 0x48, 0x6C, 0x03, 0x01, 0x06,
- 0x06, 0x02, 0x00, 0x00, 0x2A, 0x01, 0x02, 0x32,
- 0x04, 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C,
- 0x09, 0x03, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x3D, 0x00, 0xDD, 0x07, 0x00, 0xE0, 0x4C,
- 0x02, 0x02, 0x00, 0x00, 0xDD, 0x18, 0x00, 0x50,
- 0xF2, 0x01, 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04,
- 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04, 0x01, 0x00,
-
- /* page 1 beacon */
- 0x00, 0x50, 0xF2, 0x02, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x10, 0x00, 0x30, 0x84, 0x00, 0x12, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* page 2 ps-poll */
- 0xA4, 0x10, 0x01, 0xC0, 0xEC, 0x1A, 0x59, 0x0B,
- 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x18, 0x00, 0x30, 0x84, 0x00, 0x12, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* page 3 null */
- 0x48, 0x01, 0x00, 0x00, 0xEC, 0x1A, 0x59, 0x0B,
- 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
- 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x72, 0x00, 0x30, 0x84, 0x00, 0x12, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* page 4 probe_resp */
- 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
- 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
- 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
- 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
- 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
- 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
- 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
- 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
- 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
- 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
- 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* page 5 probe_resp */
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x1A, 0x00, 0x30, 0x84, 0x00, 0x12, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* page 6 qos null data */
- 0xC8, 0x01, 0x00, 0x00, 0x84, 0xC9, 0xB2, 0xA7,
- 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
- 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x1A, 0x00, 0x30, 0x84, 0x00, 0x12, 0x00, 0x00,
- 0x00, 0x00, 0x80, 0x00, 0x00, 0x01, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
- /* page 7 BT-qos null data */
- 0xC8, 0x01, 0x00, 0x00, 0x84, 0xC9, 0xB2, 0xA7,
- 0xB3, 0x6E, 0x00, 0xE0, 0x4C, 0x02, 0x51, 0x02,
- 0x84, 0xC9, 0xB2, 0xA7, 0xB3, 0x6E, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
-
-void rtl8822be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct sk_buff *skb = NULL;
-
- u32 totalpacketlen;
- bool rtstatus;
- u8 u1_rsvd_page_loc[7] = {0};
- bool b_dlok = false;
-
- u8 *beacon;
- u8 *p_pspoll;
- u8 *nullfunc;
- u8 *p_probersp;
- u8 *qosnull;
- u8 *btqosnull;
-
- memset(u1_rsvd_page_loc, 0, sizeof(u1_rsvd_page_loc));
-
- /*---------------------------------------------------------
- * (1) beacon
- *---------------------------------------------------------
- */
- beacon = &reserved_page_packet[BEACON_PG * 128];
- SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
- SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
-
- /*-------------------------------------------------------
- * (2) ps-poll
- *--------------------------------------------------------
- */
- p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
- SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
- SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
- SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
-
- SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1_rsvd_page_loc, PSPOLL_PG);
-
- /*--------------------------------------------------------
- * (3) null data
- *---------------------------------------------------------
- */
- nullfunc = &reserved_page_packet[NULL_PG * 128];
- SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
- SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
- SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
-
- SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1_rsvd_page_loc, NULL_PG);
-
- /*---------------------------------------------------------
- * (4) probe response
- *----------------------------------------------------------
- */
- p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
- SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
- SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
- SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
-
- SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1_rsvd_page_loc, PROBERSP_PG);
-
- /*---------------------------------------------------------
- * (5) QoS null data
- *----------------------------------------------------------
- */
- qosnull = &reserved_page_packet[QOS_NULL_PG * 128];
- SET_80211_HDR_ADDRESS1(qosnull, mac->bssid);
- SET_80211_HDR_ADDRESS2(qosnull, mac->mac_addr);
- SET_80211_HDR_ADDRESS3(qosnull, mac->bssid);
-
- SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1_rsvd_page_loc, QOS_NULL_PG);
-
- /*---------------------------------------------------------
- * (6) BT QoS null data
- *----------------------------------------------------------
- */
- btqosnull = &reserved_page_packet[BT_QOS_NULL_PG * 128];
- SET_80211_HDR_ADDRESS1(btqosnull, mac->bssid);
- SET_80211_HDR_ADDRESS2(btqosnull, mac->mac_addr);
- SET_80211_HDR_ADDRESS3(btqosnull, mac->bssid);
-
- SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1_rsvd_page_loc,
- BT_QOS_NULL_PG);
-
- totalpacketlen = TOTAL_RESERVED_PKT_LEN;
-
- RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
- "rtl8822be_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
- &reserved_page_packet[0], totalpacketlen);
- RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
- "rtl8822be_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
- u1_rsvd_page_loc, 3);
-
- skb = dev_alloc_skb(totalpacketlen);
- if (!skb)
- return;
- memcpy((u8 *)skb_put(skb, totalpacketlen), &reserved_page_packet,
- totalpacketlen);
-
- rtstatus = _rtl8822be_send_bcn_or_cmd_packet(hw, skb, BEACON_QUEUE);
-
- if (rtstatus)
- b_dlok = true;
-
- if (b_dlok) {
- RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
- "Set RSVD page location to Fw.\n");
- RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, "H2C_RSVDPAGE:\n",
- u1_rsvd_page_loc, 3);
- rtl8822be_fill_h2c_cmd(hw, H2C_8822B_RSVDPAGE,
- sizeof(u1_rsvd_page_loc),
- u1_rsvd_page_loc);
- } else {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "Set RSVD page location to Fw FAIL!!!!!!.\n");
- }
-}
-
-/* Should check FW support p2p or not. */
-static void rtl8822be_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw,
- u8 ctwindow)
-{
- u8 u1_ctwindow_period[1] = {ctwindow};
-
- rtl8822be_fill_h2c_cmd(hw, H2C_8822B_P2P_PS_CTW_CMD, 1,
- u1_ctwindow_period);
-}
-
-void rtl8822be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_p2p_ps_info *p2pinfo = &rtlps->p2p_ps_info;
- struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
- u8 i;
- u16 ctwindow;
- u32 start_time, tsf_low;
-
- switch (p2p_ps_state) {
- case P2P_PS_DISABLE:
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
- memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
- break;
- case P2P_PS_ENABLE:
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
- /* update CTWindow value. */
- if (p2pinfo->ctwindow > 0) {
- p2p_ps_offload->ctwindow_en = 1;
- ctwindow = p2pinfo->ctwindow;
- rtl8822be_set_p2p_ctw_period_cmd(hw, ctwindow);
- }
- /* hw only support 2 set of NoA */
- for (i = 0; i < p2pinfo->noa_num; i++) {
- /* To control the register setting for which NOA*/
- rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
- if (i == 0)
- p2p_ps_offload->noa0_en = 1;
- else
- p2p_ps_offload->noa1_en = 1;
- /* config P2P NoA Descriptor Register */
- rtl_write_dword(rtlpriv, 0x5E0,
- p2pinfo->noa_duration[i]);
- rtl_write_dword(rtlpriv, 0x5E4,
- p2pinfo->noa_interval[i]);
-
- /*Get Current TSF value */
- tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR_8822B);
-
- start_time = p2pinfo->noa_start_time[i];
- if (p2pinfo->noa_count_type[i] != 1) {
- while (start_time <= (tsf_low + (50 * 1024))) {
- start_time += p2pinfo->noa_interval[i];
- if (p2pinfo->noa_count_type[i] != 255)
- p2pinfo->noa_count_type[i]--;
- }
- }
- rtl_write_dword(rtlpriv, 0x5E8, start_time);
- rtl_write_dword(rtlpriv, 0x5EC,
- p2pinfo->noa_count_type[i]);
- }
- if (p2pinfo->opp_ps == 1 || p2pinfo->noa_num > 0) {
- /* rst p2p circuit */
- rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST_8822B, BIT(4));
- p2p_ps_offload->offload_en = 1;
-
- if (rtlpriv->mac80211.p2p == P2P_ROLE_GO) {
- p2p_ps_offload->role = 1;
- p2p_ps_offload->allstasleep = 0;
- } else {
- p2p_ps_offload->role = 0;
- }
- p2p_ps_offload->discovery = 0;
- }
- break;
- case P2P_PS_SCAN:
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
- p2p_ps_offload->discovery = 1;
- break;
- case P2P_PS_SCAN_DONE:
- RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
- p2p_ps_offload->discovery = 0;
- p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
- break;
- default:
- break;
- }
-
- rtl8822be_fill_h2c_cmd(hw, H2C_8822B_P2P_PS_OFFLOAD, 1,
- (u8 *)p2p_ps_offload);
-}
-
-static
-void rtl8822be_c2h_content_parsing_ext(struct ieee80211_hw *hw,
- u8 c2h_sub_cmd_id,
- u8 c2h_cmd_len,
- u8 *c2h_content_buf)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_halmac_ops *halmac_ops;
-
- switch (c2h_sub_cmd_id) {
- case 0x0F:
- RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
- "[C2H], C2H_8822BE_TX_REPORT!\n");
- rtl_tx_report_handler(hw, c2h_content_buf, c2h_cmd_len);
- break;
- default:
- /* indicate c2h pkt + rx desc to halmac */
- halmac_ops = rtlpriv->halmac.ops;
- halmac_ops->halmac_c2h_handle(rtlpriv,
- c2h_content_buf - 24 - 2 - 2,
- c2h_cmd_len + 24 + 2 + 2);
- break;
- }
-}
-
-void rtl8822be_c2h_content_parsing(struct ieee80211_hw *hw, u8 c2h_cmd_id,
- u8 c2h_cmd_len, u8 *tmp_buf)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
-
- if (c2h_cmd_id == 0xFF) {
- rtl8822be_c2h_content_parsing_ext(hw, tmp_buf[0],
- c2h_cmd_len - 2,
- tmp_buf + 2);
- return;
- }
-
- switch (c2h_cmd_id) {
- case C2H_8822B_DBG:
- RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
- "[C2H], C2H_8822BE_DBG!!\n");
- break;
- case C2H_8822B_TXBF:
- RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
- "[C2H], C2H_8822B_TXBF!!\n");
- break;
- case C2H_8822B_BT_INFO:
- RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
- "[C2H], C2H_8822BE_BT_INFO!!\n");
- if (rtlpriv->cfg->ops->get_btc_status())
- btc_ops->btc_btinfo_notify(rtlpriv, tmp_buf,
- c2h_cmd_len);
- break;
- case C2H_8822B_BT_MP:
- RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
- "[C2H], C2H_8822BE_BT_MP!!\n");
- if (rtlpriv->cfg->ops->get_btc_status())
- btc_ops->btc_btmpinfo_notify(rtlpriv, tmp_buf,
- c2h_cmd_len);
- break;
- default:
- if (!rtlpriv->phydm.ops->phydm_c2h_content_parsing(
- rtlpriv, c2h_cmd_id, c2h_cmd_len, tmp_buf))
- break;
-
- RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
- "[C2H], Unknown packet!! CmdId(%#X)!\n", c2h_cmd_id);
- break;
- }
-}
-
-void rtl8822be_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 c2h_cmd_id = 0, c2h_cmd_seq = 0, c2h_cmd_len = 0;
- u8 *tmp_buf = NULL;
-
- c2h_cmd_id = buffer[0];
- c2h_cmd_seq = buffer[1];
- c2h_cmd_len = len - 2;
- tmp_buf = buffer + 2;
-
- RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
- "[C2H packet], c2hCmdId=0x%x, c2hCmdSeq=0x%x, c2hCmdLen=%d\n",
- c2h_cmd_id, c2h_cmd_seq, c2h_cmd_len);
-
- RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_TRACE,
- "[C2H packet], Content Hex:\n", tmp_buf, c2h_cmd_len);
-
- switch (c2h_cmd_id) {
- case C2H_8822B_BT_INFO:
- case C2H_8822B_BT_MP:
- rtl_c2hcmd_enqueue(hw, c2h_cmd_id, c2h_cmd_len, tmp_buf);
- break;
- default:
- rtl8822be_c2h_content_parsing(hw, c2h_cmd_id, c2h_cmd_len,
- tmp_buf);
- break;
- }
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL8822B__FW__H__
-#define __RTL8822B__FW__H__
-
-#define USE_OLD_WOWLAN_DEBUG_FW 0
-
-#define H2C_8822B_RSVDPAGE_LOC_LEN 5
-#define H2C_8822B_PWEMODE_LENGTH 7
-#define H2C_8822B_JOINBSSRPT_LENGTH 1
-#define H2C_8822B_AP_OFFLOAD_LENGTH 3
-#define H2C_8822B_WOWLAN_LENGTH 3
-#define H2C_8822B_KEEP_ALIVE_CTRL_LENGTH 3
-#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
-#define H2C_8822B_REMOTE_WAKE_CTRL_LEN 1
-#else
-#define H2C_8822B_REMOTE_WAKE_CTRL_LEN 3
-#endif
-#define H2C_8822B_AOAC_GLOBAL_INFO_LEN 2
-#define H2C_8822B_AOAC_RSVDPAGE_LOC_LEN 7
-#define H2C_DEFAULT_PORT_ID_LEN 2
-
-/* Fw PS state for RPWM.
- *BIT[2:0] = HW state
- *BIT[3] = Protocol PS state, 1: register active state, 0: register sleep state
- *BIT[4] = sub-state
- */
-#define FW_PS_RF_ON BIT(2)
-#define FW_PS_REGISTER_ACTIVE BIT(3)
-
-#define FW_PS_ACK BIT(6)
-#define FW_PS_TOGGLE BIT(7)
-
-/* 8822B RPWM value*/
-/* BIT[0] = 1: 32k, 0: 40M*/
-#define FW_PS_CLOCK_OFF BIT(0) /* 32k */
-#define FW_PS_CLOCK_ON 0 /* 40M */
-
-#define FW_PS_STATE_MASK (0x0F)
-#define FW_PS_STATE_HW_MASK (0x07)
-#define FW_PS_STATE_INT_MASK (0x3F)
-
-#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
-
-#define FW_PS_STATE_ALL_ON_8822B (FW_PS_CLOCK_ON)
-#define FW_PS_STATE_RF_ON_8822B (FW_PS_CLOCK_ON)
-#define FW_PS_STATE_RF_OFF_8822B (FW_PS_CLOCK_ON)
-#define FW_PS_STATE_RF_OFF_LOW_PWR (FW_PS_CLOCK_OFF)
-
-/* For 8822B H2C PwrMode Cmd ID 5.*/
-#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
-#define FW_PWR_STATE_RF_OFF 0
-
-#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK)
-
-#define IS_IN_LOW_POWER_STATE_8822B(fw_ps_state) \
- (FW_PS_STATE(fw_ps_state) == FW_PS_CLOCK_OFF)
-
-#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
-#define FW_PWR_STATE_RF_OFF 0
-
-enum rtl8822b_h2c_cmd {
- H2C_8822B_RSVDPAGE = 0,
- H2C_8822B_MSRRPT = 1,
- H2C_8822B_SCAN = 2,
- H2C_8822B_KEEP_ALIVE_CTRL = 3,
- H2C_8822B_DISCONNECT_DECISION = 4,
-#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
- H2C_8822B_WO_WLAN = 5,
-#endif
- H2C_8822B_INIT_OFFLOAD = 6,
-#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
- H2C_8822B_REMOTE_WAKE_CTRL = 7,
-#endif
- H2C_8822B_AP_OFFLOAD = 8,
- H2C_8822B_BCN_RSVDPAGE = 9,
- H2C_8822B_PROBERSP_RSVDPAGE = 10,
-
- H2C_8822B_SETPWRMODE = 0x20,
- H2C_8822B_PS_TUNING_PARA = 0x21,
- H2C_8822B_PS_TUNING_PARA2 = 0x22,
- H2C_8822B_PS_LPS_PARA = 0x23,
- H2C_8822B_P2P_PS_OFFLOAD = 024,
- H2C_8822B_DEFAULT_PORT_ID = 0x2C,
-
-#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
- H2C_8822B_WO_WLAN = 0x80,
- H2C_8822B_REMOTE_WAKE_CTRL = 0x81,
- H2C_8822B_AOAC_GLOBAL_INFO = 0x82,
- H2C_8822B_AOAC_RSVDPAGE = 0x83,
-#endif
- H2C_8822B_MACID_CFG = 0x40,
- H2C_8822B_RSSI_REPORT = 0x42,
- H2C_8822B_MACID_CFG_3SS = 0x46,
- /*Not defined CTW CMD for P2P yet*/
- H2C_8822B_P2P_PS_CTW_CMD = 0x99,
- MAX_8822B_H2CCMD
-};
-
-enum rtl8822b_c2h_evt {
- C2H_8822B_DBG = 0x00,
- C2H_8822B_LB = 0x01,
- C2H_8822B_TXBF = 0x02,
- C2H_8822B_TX_REPORT = 0x03,
- C2H_8822B_BT_INFO = 0x09,
- C2H_8822B_BT_MP = 0x0B,
- C2H_8822B_RA_RPT = 0x0C,
- MAX_8822B_C2HEVENT
-};
-
-/* H2C: 0x20 */
-#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 7, __val)
-#define SET_H2CCMD_PWRMODE_PARM_CLK_REQ(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE(__ph2ccmd, 7, 1, __val)
-#define SET_H2CCMD_PWRMODE_PARM_RLBM(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 1, 0, 4, __val)
-#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 1, 4, 4, __val)
-#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 2, 0, 8, __val)
-#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 3, 0, 1, __val)
-#define SET_H2CCMD_PWRMODE_PARM_BCN_EARLY_RPT(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 3, 2, 1, __val)
-#define SET_H2CCMD_PWRMODE_PARM_PORT_ID(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 3, 5, 3, __val)
-#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 4, 0, 8, __val)
-#define SET_H2CCMD_PWRMODE_PARM_BYTE5(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 5, 0, 8, __val)
-
-/* H2C: 0x00 */
-#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
-#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 1, 0, 8, __val)
-#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 2, 0, 8, __val)
-#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 3, 0, 8, __val)
-#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 4, 0, 8, __val)
-
-/* H2C: 0x01 */
-#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 1, __val)
-#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE(__ph2ccmd, 1, 1, __val)
-#define SET_H2CCMD_MSRRPT_PARM_MACID(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE(__ph2ccmd + 1, 0, 8, __val)
-#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE(__ph2ccmd + 2, 0, 8, __val)
-
-/* H2C: 0x2C */
-#define SET_H2CCMD_DFTPID_PORT_ID(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE(((u8 *)(__ph2ccmd)), 0, 8, (__val))
-#define SET_H2CCMD_DFTPID_MAC_ID(__ph2ccmd, __val) \
- SET_BITS_TO_LE_1BYTE(((u8 *)(__ph2ccmd)) + 1, 0, 8, (__val))
-
-void rtl8822be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, u32 cmd_len,
- u8 *cmdbuffer);
-void rtl8822be_set_default_port_id_cmd(struct ieee80211_hw *hw);
-void rtl8822be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
-void rtl8822be_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus);
-void rtl8822be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
-void rtl8822be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
-void rtl8822be_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len);
-void rtl8822be_c2h_content_parsing(struct ieee80211_hw *hw, u8 c2h_cmd_id,
- u8 c2h_cmd_len, u8 *tmp_buf);
-bool rtl8822b_halmac_cb_write_data_rsvd_page(struct rtl_priv *rtlpriv, u8 *buf,
- u32 size);
-bool rtl8822b_halmac_cb_write_data_h2c(struct rtl_priv *rtlpriv, u8 *buf,
- u32 size);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../wifi.h"
-#include "../efuse.h"
-#include "../base.h"
-#include "../regd.h"
-#include "../cam.h"
-#include "../ps.h"
-#include "../pci.h"
-#include "reg.h"
-#include "def.h"
-#include "phy.h"
-#include "fw.h"
-#include "led.h"
-#include "hw.h"
-
-#define LLT_CONFIG 5
-
-u8 rtl_channel5g[CHANNEL_MAX_NUMBER_5G] = {
- 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
- 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
- 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
- 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
- 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
- 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
- 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
-u8 rtl_channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122,
- 138, 155, 171};
-
-static void _rtl8822be_set_bcn_ctrl_reg(struct ieee80211_hw *hw, u8 set_bits,
- u8 clear_bits)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtlpci->reg_bcn_ctrl_val |= set_bits;
- rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
-
- rtl_write_byte(rtlpriv, REG_BCN_CTRL_8822B,
- (u8)rtlpci->reg_bcn_ctrl_val);
-}
-
-static void _rtl8822be_stop_tx_beacon(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 tmp;
-
- tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2);
- rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2, tmp & (~BIT(6)));
- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 1, 0x64);
- tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2);
- tmp &= ~(BIT(0));
- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2, tmp);
-}
-
-static void _rtl8822be_resume_tx_beacon(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 tmp;
-
- tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2);
- rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2, tmp | BIT(6));
- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 1, 0xff);
- tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2);
- tmp |= BIT(0);
- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2, tmp);
-}
-
-static void _rtl8822be_enable_bcn_sub_func(struct ieee80211_hw *hw)
-{
- _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(1));
-}
-
-static void _rtl8822be_disable_bcn_sub_func(struct ieee80211_hw *hw)
-{
- _rtl8822be_set_bcn_ctrl_reg(hw, BIT(1), 0);
-}
-
-static void _rtl8822be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
- bool b_need_turn_off_ckk)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- u32 count = 0, isr_regaddr, content;
- bool b_schedule_timer = b_need_turn_off_ckk;
-
- if (!rtlhal->fw_ready)
- return;
- if (!rtlpriv->psc.fw_current_inpsmode)
- return;
-
- while (1) {
- spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
- if (rtlhal->fw_clk_change_in_progress) {
- while (rtlhal->fw_clk_change_in_progress) {
- spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
- count++;
- udelay(100);
- if (count > 1000)
- return;
- spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
- }
- spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
- } else {
- rtlhal->fw_clk_change_in_progress = false;
- spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
- break;
- }
- }
-
- if (IS_IN_LOW_POWER_STATE_8822B(rtlhal->fw_ps_state)) {
- rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
- (u8 *)(&rpwm_val));
- if (FW_PS_IS_ACK(rpwm_val)) {
- isr_regaddr = REG_HISR0_8822B;
- content = rtl_read_dword(rtlpriv, isr_regaddr);
- while (!(content & IMR_CPWM) && (count < 500)) {
- udelay(50);
- count++;
- content = rtl_read_dword(rtlpriv, isr_regaddr);
- }
-
- if (content & IMR_CPWM) {
- rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
- rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8822B;
- RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
- "Receive CPWM INT!!! PSState = %X\n",
- rtlhal->fw_ps_state);
- }
- }
-
- spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
- rtlhal->fw_clk_change_in_progress = false;
- spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
- if (b_schedule_timer) {
- mod_timer(&rtlpriv->works.fw_clockoff_timer,
- jiffies + MSECS(10));
- }
-
- } else {
- spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
- rtlhal->fw_clk_change_in_progress = false;
- spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
- }
-}
-
-static void _rtl8822be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl8192_tx_ring *ring;
- enum rf_pwrstate rtstate;
- bool b_schedule_timer = false;
- u8 queue;
-
- if (!rtlhal->fw_ready)
- return;
- if (!rtlpriv->psc.fw_current_inpsmode)
- return;
- if (!rtlhal->allow_sw_to_change_hwclc)
- return;
-
- rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
- if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
- return;
-
- for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
- ring = &rtlpci->tx_ring[queue];
- if (skb_queue_len(&ring->queue)) {
- b_schedule_timer = true;
- break;
- }
- }
-
- if (b_schedule_timer) {
- mod_timer(&rtlpriv->works.fw_clockoff_timer,
- jiffies + MSECS(10));
- return;
- }
-
- if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
- spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
- if (!rtlhal->fw_clk_change_in_progress) {
- rtlhal->fw_clk_change_in_progress = true;
- spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
- rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
- rtl_write_word(rtlpriv, REG_HISR0_8822B, 0x0100);
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
- (u8 *)(&rpwm_val));
- spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
- rtlhal->fw_clk_change_in_progress = false;
- spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
- } else {
- spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
- mod_timer(&rtlpriv->works.fw_clockoff_timer,
- jiffies + MSECS(10));
- }
- }
-}
-
-static void _rtl8822be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
-{
- u8 rpwm_val = 0;
-
- rpwm_val |= (FW_PS_STATE_RF_OFF_8822B | FW_PS_ACK);
- _rtl8822be_set_fw_clock_on(hw, rpwm_val, true);
-}
-
-static void _rtl8822be_fwlps_leave(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- bool fw_current_inps = false;
- u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
-
- if (ppsc->low_power_enable) {
- rpwm_val = (FW_PS_STATE_ALL_ON_8822B | FW_PS_ACK); /* RF on */
- _rtl8822be_set_fw_clock_on(hw, rpwm_val, false);
- rtlhal->allow_sw_to_change_hwclc = false;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
- (u8 *)(&fw_pwrmode));
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
- (u8 *)(&fw_current_inps));
- } else {
- rpwm_val = FW_PS_STATE_ALL_ON_8822B; /* RF on */
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
- (u8 *)(&rpwm_val));
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
- (u8 *)(&fw_pwrmode));
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
- (u8 *)(&fw_current_inps));
- }
-}
-
-static void _rtl8822be_fwlps_enter(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- bool fw_current_inps = true;
- u8 rpwm_val;
-
- if (ppsc->low_power_enable) {
- rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
- (u8 *)(&fw_current_inps));
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
- (u8 *)(&ppsc->fwctrl_psmode));
- rtlhal->allow_sw_to_change_hwclc = true;
- _rtl8822be_set_fw_clock_off(hw, rpwm_val);
- } else {
- rpwm_val = FW_PS_STATE_RF_OFF_8822B; /* RF off */
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
- (u8 *)(&fw_current_inps));
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
- (u8 *)(&ppsc->fwctrl_psmode));
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
- (u8 *)(&rpwm_val));
- }
-}
-
-void rtl8822be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- switch (variable) {
- case HW_VAR_RCR:
- *((u32 *)(val)) = rtlpci->receive_config;
- break;
- case HW_VAR_RF_STATE:
- *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
- break;
- case HW_VAR_FWLPS_RF_ON: {
- enum rf_pwrstate rf_state;
- u32 val_rcr;
-
- rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
- (u8 *)(&rf_state));
- if (rf_state == ERFOFF) {
- *((bool *)(val)) = true;
- } else {
- val_rcr = rtl_read_dword(rtlpriv, REG_RCR_8822B);
- val_rcr &= 0x00070000;
- if (val_rcr)
- *((bool *)(val)) = false;
- else
- *((bool *)(val)) = true;
- }
- } break;
- case HW_VAR_FW_PSMODE_STATUS:
- *((bool *)(val)) = ppsc->fw_current_inpsmode;
- break;
- case HW_VAR_CORRECT_TSF: {
- u64 tsf;
- u32 *ptsf_low = (u32 *)&tsf;
- u32 *ptsf_high = ((u32 *)&tsf) + 1;
-
- *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR_8822B + 4));
- *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR_8822B);
-
- *((u64 *)(val)) = tsf;
-
- } break;
- default:
- RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
- "switch case not process %x\n", variable);
- break;
- }
-}
-
-static void _rtl8822be_download_rsvd_page(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 tmp_regcr, tmp_reg422;
- u8 bcnvalid_reg /*, txbc_reg*/;
- u8 count = 0, dlbcn_count = 0;
- bool b_recover = false;
-
- /*Set REG_CR_8822B bit 8. DMA beacon by SW.*/
- tmp_regcr = rtl_read_byte(rtlpriv, REG_CR_8822B + 1);
- rtl_write_byte(rtlpriv, REG_CR_8822B + 1, tmp_regcr | BIT(0));
-
- /* Disable Hw protection for a time which revserd for Hw sending beacon.
- * Fix download reserved page packet fail
- * that access collision with the protection time.
- * 2010.05.11. Added by tynli.
- */
- _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(3));
- _rtl8822be_set_bcn_ctrl_reg(hw, BIT(4), 0);
-
- /* Set FWHW_TXQ_CTRL 0x422[6]=0 to
- * tell Hw the packet is not a real beacon frame.
- */
- tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2);
- rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2,
- tmp_reg422 & (~BIT(6)));
-
- if (tmp_reg422 & BIT(6))
- b_recover = true;
-
- do {
- /* Clear beacon valid check bit */
- bcnvalid_reg =
- rtl_read_byte(rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1);
- bcnvalid_reg = bcnvalid_reg | BIT(7);
- rtl_write_byte(rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1,
- bcnvalid_reg);
-
- /* download rsvd page */
- rtl8822be_set_fw_rsvdpagepkt(hw, false);
-
- /* check rsvd page download OK. */
- bcnvalid_reg =
- rtl_read_byte(rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1);
-
- count = 0;
- while (!(BIT(7) & bcnvalid_reg) && count < 20) {
- count++;
- udelay(50);
- bcnvalid_reg = rtl_read_byte(
- rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1);
- }
-
- dlbcn_count++;
- } while (!(BIT(7) & bcnvalid_reg) && dlbcn_count < 5);
-
- if (!(BIT(7) & bcnvalid_reg))
- RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
- "Download RSVD page failed!\n");
-
- /* Enable Bcn */
- _rtl8822be_set_bcn_ctrl_reg(hw, BIT(3), 0);
- _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(4));
-
- if (b_recover)
- rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2,
- tmp_reg422);
-}
-
-void rtl8822be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
-
- switch (variable) {
- case HW_VAR_ETHER_ADDR:
- rtlpriv->halmac.ops->halmac_set_mac_address(rtlpriv, 0, val);
- break;
- case HW_VAR_BASIC_RATE: {
- u16 b_rate_cfg = ((u16 *)val)[0];
-
- b_rate_cfg = b_rate_cfg & 0x15f;
- b_rate_cfg |= 0x01;
- b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));
- rtl_write_byte(rtlpriv, REG_RRSR_8822B, b_rate_cfg & 0xff);
- rtl_write_byte(rtlpriv, REG_RRSR_8822B + 1,
- (b_rate_cfg >> 8) & 0xff);
- } break;
- case HW_VAR_BSSID:
- rtlpriv->halmac.ops->halmac_set_bssid(rtlpriv, 0, val);
- break;
- case HW_VAR_SIFS:
- rtl_write_byte(rtlpriv, REG_SIFS_8822B + 1, val[0]);
- rtl_write_byte(rtlpriv, REG_SIFS_TRX_8822B + 1, val[1]);
-
- rtl_write_byte(rtlpriv, REG_SPEC_SIFS_8822B + 1, val[0]);
- rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS_8822B + 1, val[0]);
-
- if (!mac->ht_enable)
- rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM_8822B,
- 0x0e0e);
- else
- rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM_8822B,
- *((u16 *)val));
- break;
- case HW_VAR_SLOT_TIME: {
- u8 e_aci;
-
- RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE, "HW_VAR_SLOT_TIME %x\n",
- val[0]);
-
- rtl_write_byte(rtlpriv, REG_SLOT_8822B, val[0]);
-
- for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
- (u8 *)(&e_aci));
- }
- } break;
- case HW_VAR_ACK_PREAMBLE: {
- u8 reg_tmp;
- u8 short_preamble = (bool)(*(u8 *)val);
-
- reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;
- if (short_preamble)
- reg_tmp |= 0x80;
- rtl_write_byte(rtlpriv, REG_RRSR_8822B + 2, reg_tmp);
- rtlpriv->mac80211.short_preamble = short_preamble;
- } break;
- case HW_VAR_WPA_CONFIG:
- rtl_write_byte(rtlpriv, REG_SECCFG_8822B, *((u8 *)val));
- break;
- case HW_VAR_AMPDU_FACTOR: {
- u32 ampdu_len = (*((u8 *)val));
-
- ampdu_len = (0x2000 << ampdu_len) - 1;
- rtl_write_dword(rtlpriv, REG_AMPDU_MAX_LENGTH_8822B, ampdu_len);
- } break;
- case HW_VAR_AC_PARAM: {
- u8 e_aci = *((u8 *)val);
-
- if (mac->vif && mac->vif->bss_conf.assoc && !mac->act_scanning)
- rtl8822be_set_qos(hw, e_aci);
-
- if (rtlpci->acm_method != EACMWAY2_SW)
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
- (u8 *)(&e_aci));
- } break;
- case HW_VAR_ACM_CTRL: {
- u8 e_aci = *((u8 *)val);
- union aci_aifsn *aifs = (union aci_aifsn *)&mac->ac[0].aifs;
-
- u8 acm = aifs->f.acm;
- u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL_8822B);
-
- acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
-
- if (acm) {
- switch (e_aci) {
- case AC0_BE:
- acm_ctrl |= ACMHW_BEQ_EN;
- break;
- case AC2_VI:
- acm_ctrl |= ACMHW_VIQ_EN;
- break;
- case AC3_VO:
- acm_ctrl |= ACMHW_VOQ_EN;
- break;
- default:
- RT_TRACE(
- rtlpriv, COMP_ERR, DBG_WARNING,
- "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
- acm);
- break;
- }
- } else {
- switch (e_aci) {
- case AC0_BE:
- acm_ctrl &= (~ACMHW_BEQ_EN);
- break;
- case AC2_VI:
- acm_ctrl &= (~ACMHW_VIQ_EN);
- break;
- case AC3_VO:
- acm_ctrl &= (~ACMHW_VOQ_EN);
- break;
- default:
- RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
- "switch case not process\n");
- break;
- }
- }
-
- RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
- "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
- acm_ctrl);
- rtl_write_byte(rtlpriv, REG_ACMHWCTRL_8822B, acm_ctrl);
- } break;
- case HW_VAR_RCR: {
- rtl_write_dword(rtlpriv, REG_RCR_8822B, ((u32 *)(val))[0]);
- rtlpci->receive_config = ((u32 *)(val))[0];
- } break;
- case HW_VAR_RETRY_LIMIT: {
- u8 retry_limit = ((u8 *)(val))[0];
-
- rtl_write_word(rtlpriv, REG_RETRY_LIMIT_8822B,
- retry_limit << RETRY_LIMIT_SHORT_SHIFT |
- retry_limit << RETRY_LIMIT_LONG_SHIFT);
- } break;
- case HW_VAR_DUAL_TSF_RST:
- rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST_8822B,
- (BIT(0) | BIT(1)));
- break;
- case HW_VAR_EFUSE_BYTES:
- efuse->efuse_usedbytes = *((u16 *)val);
- break;
- case HW_VAR_EFUSE_USAGE:
- efuse->efuse_usedpercentage = *((u8 *)val);
- break;
- case HW_VAR_IO_CMD:
- rtl8822be_phy_set_io_cmd(hw, (*(enum io_type *)val));
- break;
- case HW_VAR_SET_RPWM:
- break;
- case HW_VAR_H2C_FW_PWRMODE:
- rtl8822be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
- break;
- case HW_VAR_FW_PSMODE_STATUS:
- ppsc->fw_current_inpsmode = *((bool *)val);
- break;
- case HW_VAR_RESUME_CLK_ON:
- _rtl8822be_set_fw_ps_rf_on(hw);
- break;
- case HW_VAR_FW_LPS_ACTION: {
- bool b_enter_fwlps = *((bool *)val);
-
- if (b_enter_fwlps)
- _rtl8822be_fwlps_enter(hw);
- else
- _rtl8822be_fwlps_leave(hw);
- } break;
- case HW_VAR_H2C_FW_JOINBSSRPT: {
- u8 mstatus = (*(u8 *)val);
-
- if (mstatus == RT_MEDIA_CONNECT) {
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
- _rtl8822be_download_rsvd_page(hw);
- }
- rtl8822be_set_default_port_id_cmd(hw);
- rtl8822be_set_fw_media_status_rpt_cmd(hw, mstatus);
- } break;
- case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
- rtl8822be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
- break;
- case HW_VAR_AID: {
- u16 u2btmp;
-
- u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT_8822B);
- u2btmp &= 0xC000;
- rtl_write_word(rtlpriv, REG_BCN_PSR_RPT_8822B,
- (u2btmp | mac->assoc_id));
- } break;
- case HW_VAR_CORRECT_TSF: {
- u8 btype_ibss = ((u8 *)(val))[0];
-
- if (btype_ibss)
- _rtl8822be_stop_tx_beacon(hw);
-
- _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(3));
-
- rtl_write_dword(rtlpriv, REG_TSFTR_8822B,
- (u32)(mac->tsf & 0xffffffff));
- rtl_write_dword(rtlpriv, REG_TSFTR_8822B + 4,
- (u32)((mac->tsf >> 32) & 0xffffffff));
-
- _rtl8822be_set_bcn_ctrl_reg(hw, BIT(3), 0);
-
- if (btype_ibss)
- _rtl8822be_resume_tx_beacon(hw);
- } break;
- case HW_VAR_KEEP_ALIVE: {
- u8 array[2];
-
- array[0] = 0xff;
- array[1] = *((u8 *)val);
- rtl8822be_fill_h2c_cmd(hw, H2C_8822B_KEEP_ALIVE_CTRL, 2, array);
- } break;
- default:
- RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
- "switch case not process %x\n", variable);
- break;
- }
-}
-
-static void _rtl8822be_gen_refresh_led_state(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_led *led0 = &pcipriv->ledctl.sw_led0;
-
- if (rtlpriv->rtlhal.up_first_time)
- return;
-
- if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
- rtl8822be_sw_led_on(hw, led0);
- else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
- rtl8822be_sw_led_on(hw, led0);
- else
- rtl8822be_sw_led_off(hw, led0);
-}
-
-static bool _rtl8822be_init_trxbd(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- /*struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));*/
-
- u8 bytetmp;
- /*u16 wordtmp;*/
- u32 dwordtmp;
-
- /* Set TX/RX descriptor physical address -- HI part */
- if (!rtlpriv->cfg->mod_params->dma64)
- goto dma64_end;
-
- rtl_write_dword(rtlpriv, REG_H2CQ_TXBD_DESA_8822B + 4,
- ((u64)rtlpci->tx_ring[H2C_QUEUE].buffer_desc_dma) >>
- 32);
- rtl_write_dword(rtlpriv, REG_BCNQ_TXBD_DESA_8822B + 4,
- ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) >>
- 32);
- rtl_write_dword(rtlpriv, REG_MGQ_TXBD_DESA_8822B + 4,
- (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma >> 32);
- rtl_write_dword(rtlpriv, REG_VOQ_TXBD_DESA_8822B + 4,
- (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma >> 32);
- rtl_write_dword(rtlpriv, REG_VIQ_TXBD_DESA_8822B + 4,
- (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma >> 32);
- rtl_write_dword(rtlpriv, REG_BEQ_TXBD_DESA_8822B + 4,
- (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma >> 32);
- rtl_write_dword(rtlpriv, REG_BKQ_TXBD_DESA_8822B + 4,
- (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma >> 32);
- rtl_write_dword(rtlpriv, REG_HI0Q_TXBD_DESA_8822B + 4,
- (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma >> 32);
-
- rtl_write_dword(rtlpriv, REG_RXQ_RXBD_DESA_8822B + 4,
- (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma >> 32);
-
-dma64_end:
- /* Set TX/RX descriptor physical address(from OS API). */
- rtl_write_dword(rtlpriv, REG_H2CQ_TXBD_DESA_8822B,
- ((u64)rtlpci->tx_ring[H2C_QUEUE].buffer_desc_dma) &
- DMA_BIT_MASK(32));
- rtl_write_dword(rtlpriv, REG_BCNQ_TXBD_DESA_8822B,
- ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
- DMA_BIT_MASK(32));
- rtl_write_dword(rtlpriv, REG_MGQ_TXBD_DESA_8822B,
- (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &
- DMA_BIT_MASK(32));
- rtl_write_dword(rtlpriv, REG_VOQ_TXBD_DESA_8822B,
- (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &
- DMA_BIT_MASK(32));
- rtl_write_dword(rtlpriv, REG_VIQ_TXBD_DESA_8822B,
- (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &
- DMA_BIT_MASK(32));
- rtl_write_dword(rtlpriv, REG_BEQ_TXBD_DESA_8822B,
- (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &
- DMA_BIT_MASK(32));
- dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_TXBD_DESA_8822B); /* need? */
- rtl_write_dword(rtlpriv, REG_BKQ_TXBD_DESA_8822B,
- (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &
- DMA_BIT_MASK(32));
- rtl_write_dword(rtlpriv, REG_HI0Q_TXBD_DESA_8822B,
- (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &
- DMA_BIT_MASK(32));
-
- rtl_write_dword(rtlpriv, REG_RXQ_RXBD_DESA_8822B,
- (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
- DMA_BIT_MASK(32));
-
- /* Reset R/W point */
- rtl_write_dword(rtlpriv, REG_BD_RWPTR_CLR_8822B, 0x3fffffff);
-
- /* Reset the H2CQ R/W point index to 0 */
- dwordtmp = rtl_read_dword(rtlpriv, REG_H2CQ_CSR_8822B);
- rtl_write_dword(rtlpriv, REG_H2CQ_CSR_8822B,
- (dwordtmp | BIT(8) | BIT(16)));
-
- bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_8822B + 3);
- rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 3, bytetmp | 0xF7);
-
- rtl_write_dword(rtlpriv, REG_INT_MIG_8822B, 0);
-
- rtl_write_dword(rtlpriv, REG_MCUTST_I_8822B, 0x0);
-
- rtl_write_word(rtlpriv, REG_H2CQ_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM_8822B,
- TX_DESC_NUM_8822B |
- ((RTL8822BE_SEG_NUM << 12) & 0x3000));
- /*Rx*/
- rtl_write_word(rtlpriv, REG_RX_RXBD_NUM_8822B,
- RX_DESC_NUM_8822BE |
- ((RTL8822BE_SEG_NUM << 13) & 0x6000) | 0x8000);
-
- rtl_write_dword(rtlpriv, REG_BD_RWPTR_CLR_8822B, 0XFFFFFFFF);
-
- _rtl8822be_gen_refresh_led_state(hw);
-
- return true;
-}
-
-static void _rtl8822be_enable_aspm_back_door(struct ieee80211_hw *hw)
-{
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- u8 tmp;
-
- if (!ppsc->support_backdoor)
- return;
-
- pci_read_config_byte(rtlpci->pdev, 0x70f, &tmp);
- pci_write_config_byte(rtlpci->pdev, 0x70f, tmp | ASPM_L1_LATENCY << 3);
-
- pci_read_config_byte(rtlpci->pdev, 0x719, &tmp);
- pci_write_config_byte(rtlpci->pdev, 0x719, tmp | BIT(3) | BIT(4));
-}
-
-void rtl8822be_enable_hw_security_config(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 sec_reg_value;
- u8 tmp;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
- rtlpriv->sec.pairwise_enc_algorithm,
- rtlpriv->sec.group_enc_algorithm);
-
- if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "not open hw encryption\n");
- return;
- }
-
- sec_reg_value = SCR_TX_ENC_ENABLE | SRC_RX_DEC_ENABLE;
-
- if (rtlpriv->sec.use_defaultkey) {
- sec_reg_value |= SCR_TX_USE_DK;
- sec_reg_value |= SCR_RX_USE_DK;
- }
-
- sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
-
- tmp = rtl_read_byte(rtlpriv, REG_CR_8822B + 1);
- rtl_write_byte(rtlpriv, REG_CR_8822B + 1, tmp | BIT(1));
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "The SECR-value %x\n",
- sec_reg_value);
-
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
-}
-
-static bool _rtl8822be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
-{
- u8 tmp;
-
- /* write reg 0x350 Bit[26]=1. Enable debug port. */
- tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG_V1_8822B + 3);
- if (!(tmp & BIT(2))) {
- rtl_write_byte(rtlpriv, REG_DBI_FLAG_V1_8822B + 3,
- (tmp | BIT(2)));
- mdelay(100); /* Suggested by DD Justin_tsai. */
- }
-
- /* read reg 0x350 Bit[25] if 1 : RX hang
- * read reg 0x350 Bit[24] if 1 : TX hang
- */
- tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG_V1_8822B + 3);
- if ((tmp & BIT(0)) || (tmp & BIT(1))) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "CheckPcieDMAHang8822BE(): true!!\n");
- return true;
- } else {
- return false;
- }
-}
-
-static void _rtl8822be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
- bool mac_power_on)
-{
- u8 tmp;
- bool release_mac_rx_pause;
- u8 backup_pcie_dma_pause;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "ResetPcieInterfaceDMA8822BE()\n");
-
- /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
- * released by SD1 Alan.
- * 2013.05.07, by tynli.
- */
-
- /* 1. disable register write lock
- * write 0x1C bit[1:0] = 2'h0
- * write 0xCC bit[2] = 1'b1
- */
- tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL_8822B);
- tmp &= ~(BIT(1) | BIT(0));
- rtl_write_byte(rtlpriv, REG_RSV_CTRL_8822B, tmp);
- tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B);
- tmp |= BIT(2);
- rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B, tmp);
-
- /* 2. Check and pause TRX DMA
- * write 0x284 bit[18] = 1'b1
- * write 0x301 = 0xFF
- */
- tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL_8822B);
- if (tmp & BIT(2)) {
- /* Already pause before the function for another purpose. */
- release_mac_rx_pause = false;
- } else {
- rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL_8822B,
- (tmp | BIT(2)));
- release_mac_rx_pause = true;
- }
-
- backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_8822B + 1);
- if (backup_pcie_dma_pause != 0xFF)
- rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 1, 0xFF);
-
- if (mac_power_on) {
- /* 3. reset TRX function
- * write 0x100 = 0x00
- */
- rtl_write_byte(rtlpriv, REG_CR_8822B, 0);
- }
-
- /* 4. Reset PCIe DMA
- * write 0x003 bit[0] = 0
- */
- tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1);
- tmp &= ~(BIT(0));
- rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1, tmp);
-
- /* 5. Enable PCIe DMA
- * write 0x003 bit[0] = 1
- */
- tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1);
- tmp |= BIT(0);
- rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1, tmp);
-
- if (mac_power_on) {
- /* 6. enable TRX function
- * write 0x100 = 0xFF
- */
- rtl_write_byte(rtlpriv, REG_CR_8822B, 0xFF);
-
- /* We should init LLT & RQPN and
- * prepare Tx/Rx descrptor address later
- * because MAC function is reset.
- */
- }
-
- /* 7. Restore PCIe autoload down bit
- * write 0xF8 bit[17] = 1'b1
- */
- tmp = rtl_read_byte(rtlpriv, REG_SYS_STATUS2_8822B + 2);
- tmp |= BIT(1);
- rtl_write_byte(rtlpriv, REG_SYS_STATUS2_8822B + 2, tmp);
-
- /* In MAC power on state, BB and RF maybe in ON state,
- * if we release TRx DMA here
- * it will cause packets to be started to Tx/Rx,
- * so we release Tx/Rx DMA later.
- */
- if (!mac_power_on) {
- /* 8. release TRX DMA
- * write 0x284 bit[18] = 1'b0
- * write 0x301 = 0x00
- */
- if (release_mac_rx_pause) {
- tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL_8822B);
- rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL_8822B,
- (tmp & (~BIT(2))));
- }
- rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 1,
- backup_pcie_dma_pause);
- }
-
- /* 9. lock system register
- * write 0xCC bit[2] = 1'b0
- */
- tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B);
- tmp &= ~(BIT(2));
- rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B, tmp);
-}
-
-int rtl8822be_hw_init(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- int err = 0;
- u8 tmp_u1b;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8822BE hw init\n");
- rtlpriv->rtlhal.being_init_adapter = true;
- rtlpriv->intf_ops->disable_aspm(hw);
-
- if (_rtl8822be_check_pcie_dma_hang(rtlpriv)) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "8822be dma hang!\n");
- _rtl8822be_reset_pcie_interface_dma(rtlpriv,
- rtlhal->mac_func_enable);
- rtlhal->mac_func_enable = false;
- }
-
- /* init TRX BD */
- _rtl8822be_init_trxbd(hw);
-
- /* use halmac to init */
- err = rtlpriv->halmac.ops->halmac_init_hal(rtlpriv);
- if (err) {
- pr_err("halmac_init_hal failed\n");
- rtlhal->fw_ready = false;
- return err;
- }
-
- rtlhal->fw_ready = true;
-
- /* have to init after halmac init */
- tmp_u1b = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_8822B + 2);
- rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 2, (tmp_u1b | BIT(4)));
-
- /*rtl_write_word(rtlpriv, REG_PCIE_CTRL_8822B, 0x8000);*/
- rtlhal->rx_tag = 0;
-
- rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ_8822B, 0x4);
-
- /*fw related variable initialize */
- ppsc->fw_current_inpsmode = false;
- rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8822B;
- rtlhal->fw_clk_change_in_progress = false;
- rtlhal->allow_sw_to_change_hwclc = false;
- rtlhal->last_hmeboxnum = 0;
-
- rtlphy->rfreg_chnlval[0] =
- rtl_get_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK);
- rtlphy->rfreg_chnlval[1] =
- rtl_get_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK);
- rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
- RFREG_OFFSET_MASK);
- rtlphy->rfreg_chnlval[0] =
- (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) | BIT(10) | BIT(11);
-
- rtlhal->mac_func_enable = true;
-
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_power_on_setting(rtlpriv);
-
- /* reset cam / set security */
- rtl_cam_reset_all_entry(hw);
- rtl8822be_enable_hw_security_config(hw);
-
- /* check RCR/ICV bit */
- rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
- rtl_write_dword(rtlpriv, REG_RCR_8822B, rtlpci->receive_config);
-
- /* clear rx ctrl frame */
- rtl_write_word(rtlpriv, REG_RXFLTMAP1_8822B, 0);
-
- ppsc->rfpwr_state = ERFON;
-
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
- _rtl8822be_enable_aspm_back_door(hw);
- rtlpriv->intf_ops->enable_aspm(hw);
-
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
- else
- rtlpriv->btcoexist.btc_ops->btc_init_hw_config_wifi_only(
- rtlpriv);
-
- rtlpriv->rtlhal.being_init_adapter = false;
-
- rtlpriv->phydm.ops->phydm_init_dm(rtlpriv);
-
- /* clear ISR, and IMR will be on later */
- rtl_write_dword(rtlpriv, REG_HISR0_8822B,
- rtl_read_dword(rtlpriv, REG_HISR0_8822B));
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "end of Rtl8822BE hw init %x\n",
- err);
- return 0;
-}
-
-static u32 _rtl8822be_read_chip_version(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- /*enum version_8822b version = VERSION_UNKNOWN;*/
- u32 version;
- u32 value32;
-
- rtlphy->rf_type = RF_2T2R;
-
- value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1_8822B);
-
- version = value32;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
- (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
-
- return version;
-}
-
-static int _rtl8822be_set_media_status(struct ieee80211_hw *hw,
- enum nl80211_iftype type)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
- enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
- u8 mode = MSR_NOLINK;
-
- bt_msr &= 0xfc;
-
- switch (type) {
- case NL80211_IFTYPE_UNSPECIFIED:
- mode = MSR_NOLINK;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "Set Network type to NO LINK!\n");
- break;
- case NL80211_IFTYPE_ADHOC:
- case NL80211_IFTYPE_MESH_POINT:
- mode = MSR_ADHOC;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "Set Network type to Ad Hoc!\n");
- break;
- case NL80211_IFTYPE_STATION:
- mode = MSR_INFRA;
- ledaction = LED_CTL_LINK;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "Set Network type to STA!\n");
- break;
- case NL80211_IFTYPE_AP:
- mode = MSR_AP;
- ledaction = LED_CTL_LINK;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "Set Network type to AP!\n");
- break;
- default:
- pr_err("Network type %d not support!\n", type);
- return 1;
- }
-
- /* MSR_INFRA == Link in infrastructure network;
- * MSR_ADHOC == Link in ad hoc network;
- * Therefore, check link state is necessary.
- *
- * MSR_AP == AP mode; link state is not cared here.
- */
- if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
- mode = MSR_NOLINK;
- ledaction = LED_CTL_NO_LINK;
- }
-
- if (mode == MSR_NOLINK || mode == MSR_INFRA) {
- _rtl8822be_stop_tx_beacon(hw);
- _rtl8822be_enable_bcn_sub_func(hw);
- } else if (mode == MSR_ADHOC || mode == MSR_AP) {
- _rtl8822be_resume_tx_beacon(hw);
- _rtl8822be_disable_bcn_sub_func(hw);
- } else {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
- mode);
- }
-
- rtl_write_byte(rtlpriv, (MSR), bt_msr | mode);
- rtlpriv->cfg->ops->led_control(hw, ledaction);
- if (mode == MSR_AP)
- rtl_write_byte(rtlpriv, REG_BCNTCFG_8822B + 1, 0x00);
- else
- rtl_write_byte(rtlpriv, REG_BCNTCFG_8822B + 1, 0x66);
- return 0;
-}
-
-void rtl8822be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- u32 reg_rcr = rtlpci->receive_config;
-
- if (rtlpriv->psc.rfpwr_state != ERFON)
- return;
-
- if (check_bssid) {
- reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
- _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(4));
- } else if (!check_bssid) {
- reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
- _rtl8822be_set_bcn_ctrl_reg(hw, BIT(4), 0);
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
- }
-}
-
-int rtl8822be_set_network_type(struct ieee80211_hw *hw,
- enum nl80211_iftype type)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- if (_rtl8822be_set_media_status(hw, type))
- return -EOPNOTSUPP;
-
- if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
- if (type != NL80211_IFTYPE_AP &&
- type != NL80211_IFTYPE_MESH_POINT)
- rtl8822be_set_check_bssid(hw, true);
- } else {
- rtl8822be_set_check_bssid(hw, false);
- }
-
- return 0;
-}
-
-void rtl8822be_set_qos(struct ieee80211_hw *hw, int aci)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- u32 ac_param;
-
- ac_param = rtl_get_hal_edca_param(hw, mac->vif, mac->mode,
- &mac->edca_param[aci]);
-
- switch (aci) {
- case AC1_BK:
- rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM_8822B, ac_param);
- break;
- case AC0_BE:
- rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM_8822B, ac_param);
- break;
- case AC2_VI:
- rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM_8822B, ac_param);
- break;
- case AC3_VO:
- rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM_8822B, ac_param);
- break;
- default:
- WARN_ONCE(true, "invalid aci: %d !\n", aci);
- break;
- }
-}
-
-void rtl8822be_enable_interrupt(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- rtl_write_dword(rtlpriv, REG_HIMR0_8822B,
- rtlpci->irq_mask[0] & 0xFFFFFFFF);
- rtl_write_dword(rtlpriv, REG_HIMR1_8822B,
- rtlpci->irq_mask[1] & 0xFFFFFFFF);
- rtl_write_dword(rtlpriv, REG_HIMR3_8822B,
- rtlpci->irq_mask[3] & 0xFFFFFFFF);
- rtlpci->irq_enabled = true;
-}
-
-void rtl8822be_disable_interrupt(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- rtl_write_dword(rtlpriv, REG_HIMR0_8822B, IMR_DISABLED);
- rtl_write_dword(rtlpriv, REG_HIMR1_8822B, IMR_DISABLED);
- rtl_write_dword(rtlpriv, REG_HIMR3_8822B, IMR_DISABLED);
- rtlpci->irq_enabled = false;
- /*synchronize_irq(rtlpci->pdev->irq);*/
-}
-
-void rtl8822be_card_disable(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- enum nl80211_iftype opmode;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8822be card disable\n");
-
- RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
-
- mac->link_state = MAC80211_NOLINK;
- opmode = NL80211_IFTYPE_UNSPECIFIED;
-
- _rtl8822be_set_media_status(hw, opmode);
-
- if (rtlpriv->rtlhal.driver_is_goingto_unload ||
- ppsc->rfoff_reason > RF_CHANGE_BY_PS)
- rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
-
- rtlpriv->phydm.ops->phydm_deinit_dm(rtlpriv);
-
- rtlpriv->halmac.ops->halmac_deinit_hal(rtlpriv);
-
- /* after power off we should do iqk again */
- if (!rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->phy.iqk_initialized = false;
-}
-
-void rtl8822be_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
- u32 *p_intb, u32 *p_intc, u32 *p_intd)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- *p_inta =
- rtl_read_dword(rtlpriv, REG_HISR0_8822B) & rtlpci->irq_mask[0];
- rtl_write_dword(rtlpriv, REG_HISR0_8822B, *p_inta);
-
- *p_intb =
- rtl_read_dword(rtlpriv, REG_HISR1_8822B) & rtlpci->irq_mask[1];
- rtl_write_dword(rtlpriv, REG_HISR1_8822B, *p_intb);
-
- *p_intd =
- rtl_read_dword(rtlpriv, REG_HISR3_8822B) & rtlpci->irq_mask[3];
- rtl_write_dword(rtlpriv, REG_HISR3_8822B, *p_intd);
-}
-
-void rtl8822be_set_beacon_related_registers(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- u16 bcn_interval, atim_window;
-
- bcn_interval = mac->beacon_interval;
- atim_window = 2; /*FIX MERGE */
- rtl8822be_disable_interrupt(hw);
- rtl_write_word(rtlpriv, REG_ATIMWND_8822B, atim_window);
- rtl_write_word(rtlpriv, REG_MBSSID_BCN_SPACE_8822B, bcn_interval);
- rtl_write_word(rtlpriv, REG_BCNTCFG_8822B, 0x660f);
- rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK_8822B, 0x18);
- rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM_8822B, 0x18);
- rtl_write_byte(rtlpriv, 0x606, 0x30);
- rtlpci->reg_bcn_ctrl_val |= BIT(3);
- rtl_write_byte(rtlpriv, REG_BCN_CTRL_8822B,
- (u8)rtlpci->reg_bcn_ctrl_val);
-}
-
-void rtl8822be_set_beacon_interval(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- u16 bcn_interval = mac->beacon_interval;
-
- RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
- bcn_interval);
- rtl_write_word(rtlpriv, REG_MBSSID_BCN_SPACE_8822B, bcn_interval);
-}
-
-void rtl8822be_update_interrupt_mask(struct ieee80211_hw *hw, u32 add_msr,
- u32 rm_msr)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
- add_msr, rm_msr);
-
- if (add_msr)
- rtlpci->irq_mask[0] |= add_msr;
- if (rm_msr)
- rtlpci->irq_mask[0] &= (~rm_msr);
- rtl8822be_disable_interrupt(hw);
- rtl8822be_enable_interrupt(hw);
-}
-
-static bool _rtl8822be_get_chnl_group(u8 chnl, u8 *group)
-{
- bool in_24g;
-
- if (chnl <= 14) {
- in_24g = true;
-
- if (chnl >= 1 && chnl <= 2)
- *group = 0;
- else if (chnl >= 3 && chnl <= 5)
- *group = 1;
- else if (chnl >= 6 && chnl <= 8)
- *group = 2;
- else if (chnl >= 9 && chnl <= 11)
- *group = 3;
- else if (chnl >= 12 && chnl <= 14)
- *group = 4;
- } else {
- in_24g = false;
-
- if (chnl >= 36 && chnl <= 42)
- *group = 0;
- else if (chnl >= 44 && chnl <= 48)
- *group = 1;
- else if (chnl >= 50 && chnl <= 58)
- *group = 2;
- else if (chnl >= 60 && chnl <= 64)
- *group = 3;
- else if (chnl >= 100 && chnl <= 106)
- *group = 4;
- else if (chnl >= 108 && chnl <= 114)
- *group = 5;
- else if (chnl >= 116 && chnl <= 122)
- *group = 6;
- else if (chnl >= 124 && chnl <= 130)
- *group = 7;
- else if (chnl >= 132 && chnl <= 138)
- *group = 8;
- else if (chnl >= 140 && chnl <= 144)
- *group = 9;
- else if (chnl >= 149 && chnl <= 155)
- *group = 10;
- else if (chnl >= 157 && chnl <= 161)
- *group = 11;
- else if (chnl >= 165 && chnl <= 171)
- *group = 12;
- else if (chnl >= 173 && chnl <= 177)
- *group = 13;
- }
- return in_24g;
-}
-
-static inline bool power_valid(u8 power)
-{
- if (power <= 63)
- return true;
-
- return false;
-}
-
-static inline s8 power_diff(s8 diff)
-{
- /* bit sign number to 8 bit sign number */
- if (diff & BIT(3))
- diff |= 0xF0;
-
- return diff;
-}
-
-static void _rtl8822be_read_power_value_fromprom(struct ieee80211_hw *hw,
- struct txpower_info_2g *pwr2g,
- struct txpower_info_5g *pwr5g,
- bool autoload_fail, u8 *hwinfo)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u32 rf, addr = EEPROM_TX_PWR_INX_8822B, group, i = 0;
- u8 power;
- s8 diff;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "hal_ReadPowerValueFromPROM8822B(): PROMContent[0x%x]=0x%x\n",
- (addr + 1), hwinfo[addr + 1]);
- if (hwinfo[addr + 1] == 0xFF) /*YJ,add,120316*/
- autoload_fail = true;
-
- memset(pwr2g, 0, sizeof(struct txpower_info_2g));
- memset(pwr5g, 0, sizeof(struct txpower_info_5g));
-
- if (autoload_fail) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "auto load fail : Use Default value!\n");
- for (rf = 0; rf < MAX_RF_PATH; rf++) {
- /* 2.4G default value */
- for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
- pwr2g->index_cck_base[rf][group] = 0x2D;
- pwr2g->index_bw40_base[rf][group] = 0x2D;
- }
- for (i = 0; i < MAX_TX_COUNT; i++) {
- if (i == 0) {
- pwr2g->bw20_diff[rf][0] = 0x02;
- pwr2g->ofdm_diff[rf][0] = 0x04;
- } else {
- pwr2g->bw20_diff[rf][i] = 0xFE;
- pwr2g->bw40_diff[rf][i] = 0xFE;
- pwr2g->cck_diff[rf][i] = 0xFE;
- pwr2g->ofdm_diff[rf][i] = 0xFE;
- }
- }
-
- /*5G default value*/
- for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
- pwr5g->index_bw40_base[rf][group] = 0x2A;
-
- for (i = 0; i < MAX_TX_COUNT; i++) {
- if (i == 0) {
- pwr5g->ofdm_diff[rf][0] = 0x04;
- pwr5g->bw20_diff[rf][0] = 0x00;
- pwr5g->bw80_diff[rf][0] = 0xFE;
- pwr5g->bw160_diff[rf][0] = 0xFE;
- } else {
- pwr5g->ofdm_diff[rf][i] = 0xFE;
- pwr5g->bw20_diff[rf][i] = 0xFE;
- pwr5g->bw40_diff[rf][i] = 0xFE;
- pwr5g->bw80_diff[rf][i] = 0xFE;
- pwr5g->bw160_diff[rf][i] = 0xFE;
- }
- }
- }
- return;
- }
-
- rtl_priv(hw)->efuse.txpwr_fromeprom = true;
-
- for (rf = 0; rf < 2 /*MAX_RF_PATH*/; rf++) {
- /*2.4G default value*/
- for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
- power = hwinfo[addr++];
- if (power_valid(power))
- pwr2g->index_cck_base[rf][group] = power;
- }
- for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
- power = hwinfo[addr++];
- if (power_valid(power))
- pwr2g->index_bw40_base[rf][group] = power;
- }
- for (i = 0; i < MAX_TX_COUNT; i++) {
- if (i == 0) {
- pwr2g->bw40_diff[rf][i] = 0;
-
- diff = (hwinfo[addr] & 0xF0) >> 4;
- pwr2g->bw20_diff[rf][i] = power_diff(diff);
-
- diff = hwinfo[addr] & 0x0F;
- pwr2g->ofdm_diff[rf][i] = power_diff(diff);
-
- pwr2g->cck_diff[rf][i] = 0;
-
- addr++;
- } else {
- diff = (hwinfo[addr] & 0xF0) >> 4;
- pwr2g->bw40_diff[rf][i] = power_diff(diff);
-
- diff = hwinfo[addr] & 0x0F;
- pwr2g->bw20_diff[rf][i] = power_diff(diff);
-
- addr++;
-
- diff = (hwinfo[addr] & 0xF0) >> 4;
- pwr2g->ofdm_diff[rf][i] = power_diff(diff);
-
- diff = hwinfo[addr] & 0x0F;
- pwr2g->cck_diff[rf][i] = power_diff(diff);
-
- addr++;
- }
- }
-
- /*5G default value*/
- for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
- power = hwinfo[addr++];
- if (power_valid(power))
- pwr5g->index_bw40_base[rf][group] = power;
- }
-
- for (i = 0; i < MAX_TX_COUNT; i++) {
- if (i == 0) {
- pwr5g->bw40_diff[rf][i] = 0;
-
- diff = (hwinfo[addr] & 0xF0) >> 4;
- pwr5g->bw20_diff[rf][i] = power_diff(diff);
-
- diff = hwinfo[addr] & 0x0F;
- pwr5g->ofdm_diff[rf][i] = power_diff(diff);
-
- addr++;
- } else {
- diff = (hwinfo[addr] & 0xF0) >> 4;
- pwr5g->bw40_diff[rf][i] = power_diff(diff);
-
- diff = hwinfo[addr] & 0x0F;
- pwr5g->bw20_diff[rf][i] = power_diff(diff);
-
- addr++;
- }
- }
-
- diff = (hwinfo[addr] & 0xF0) >> 4;
- pwr5g->ofdm_diff[rf][1] = power_diff(diff);
-
- diff = hwinfo[addr] & 0x0F;
- pwr5g->ofdm_diff[rf][2] = power_diff(diff);
-
- addr++;
-
- diff = hwinfo[addr] & 0x0F;
- pwr5g->ofdm_diff[rf][3] = power_diff(diff);
-
- addr++;
-
- for (i = 0; i < MAX_TX_COUNT; i++) {
- diff = (hwinfo[addr] & 0xF0) >> 4;
- pwr5g->bw80_diff[rf][i] = power_diff(diff);
-
- diff = hwinfo[addr] & 0x0F;
- pwr5g->bw160_diff[rf][i] = power_diff(diff);
-
- addr++;
- }
- }
-}
-
-static void _rtl8822be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
- bool autoload_fail,
- u8 *hwinfo)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));
- struct txpower_info_2g pwr2g;
- struct txpower_info_5g pwr5g;
- u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
- 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
- 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
- 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
- 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
- 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
- 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
- 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
- u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122,
- 138, 155, 171};
- u8 rf, group;
- u8 i;
-
- _rtl8822be_read_power_value_fromprom(hw, &pwr2g, &pwr5g, autoload_fail,
- hwinfo);
-
- for (rf = 0; rf < MAX_RF_PATH; rf++) {
- for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
- _rtl8822be_get_chnl_group(i + 1, &group);
-
- if (i == CHANNEL_MAX_NUMBER_2G - 1) {
- efu->txpwrlevel_cck[rf][i] =
- pwr2g.index_cck_base[rf][5];
- efu->txpwrlevel_ht40_1s[rf][i] =
- pwr2g.index_bw40_base[rf][group];
- } else {
- efu->txpwrlevel_cck[rf][i] =
- pwr2g.index_cck_base[rf][group];
- efu->txpwrlevel_ht40_1s[rf][i] =
- pwr2g.index_bw40_base[rf][group];
- }
- }
- for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
- _rtl8822be_get_chnl_group(channel5g[i], &group);
- efu->txpwr_5g_bw40base[rf][i] =
- pwr5g.index_bw40_base[rf][group];
- }
- for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
- u8 upper, lower;
-
- _rtl8822be_get_chnl_group(channel5g_80m[i], &group);
- upper = pwr5g.index_bw40_base[rf][group];
- lower = pwr5g.index_bw40_base[rf][group + 1];
-
- efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
- }
- for (i = 0; i < MAX_TX_COUNT; i++) {
- efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];
- efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];
- efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];
- efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];
-
- efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];
- efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];
- efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];
- efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];
- }
- }
-
- if (!autoload_fail)
- efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_8822B];
- else
- efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
-
- if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {
- efu->apk_thermalmeterignore = true;
- efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
- }
-
- efu->thermalmeter[0] = efu->eeprom_thermalmeter;
- RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "thermalmeter = 0x%x\n",
- efu->eeprom_thermalmeter);
-
- if (!autoload_fail) {
- efu->eeprom_regulatory =
- hwinfo[EEPROM_RF_BOARD_OPTION_8822B] & 0x07;
- if (hwinfo[EEPROM_RF_BOARD_OPTION_8822B] == 0xFF)
- efu->eeprom_regulatory = 0;
- } else {
- efu->eeprom_regulatory = 0;
- }
- RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "eeprom_regulatory = 0x%x\n",
- efu->eeprom_regulatory);
-}
-
-static void _rtl8822be_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
- bool autoload_fail)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
-
- if (!autoload_fail) {
- rtlhal->pa_type_2g = hwinfo[EEPROM_2G_5G_PA_TYPE_8822B];
- rtlhal->lna_type_2g =
- hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B];
- if (rtlhal->pa_type_2g == 0xFF)
- rtlhal->pa_type_2g = 0;
- if (rtlhal->lna_type_2g == 0xFF)
- rtlhal->lna_type_2g = 0;
-
- rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(4)) ? 1 : 0;
- rtlhal->external_lna_2g =
- (rtlhal->lna_type_2g & BIT(3)) ? 1 : 0;
-
- rtlhal->pa_type_5g = hwinfo[EEPROM_2G_5G_PA_TYPE_8822B];
- rtlhal->lna_type_5g =
- hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B];
- if (rtlhal->pa_type_5g == 0xFF)
- rtlhal->pa_type_5g = 0;
- if (rtlhal->lna_type_5g == 0xFF)
- rtlhal->lna_type_5g = 0;
-
- rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(0)) ? 1 : 0;
- rtlhal->external_lna_5g =
- (rtlhal->lna_type_5g & BIT(3)) ? 1 : 0;
- } else {
- rtlhal->external_pa_2g = 0;
- rtlhal->external_lna_2g = 0;
- rtlhal->external_pa_5g = 0;
- rtlhal->external_lna_5g = 0;
- }
-}
-
-static void _rtl8822be_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo,
- bool autoload_fail)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
-
- u8 ext_type_pa_2g_a =
- (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(2)) >>
- 2; /* 0xBD[2] */
- u8 ext_type_pa_2g_b =
- (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(6)) >>
- 6; /* 0xBD[6] */
- u8 ext_type_pa_5g_a =
- (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(2)) >>
- 2; /* 0xBF[2] */
- u8 ext_type_pa_5g_b =
- (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(6)) >>
- 6; /* 0xBF[6] */
- u8 ext_type_lna_2g_a = (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] &
- (BIT(1) | BIT(0))) >>
- 0; /* 0xBD[1:0] */
- u8 ext_type_lna_2g_b = (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] &
- (BIT(5) | BIT(4))) >>
- 4; /* 0xBD[5:4] */
- u8 ext_type_lna_5g_a = (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] &
- (BIT(1) | BIT(0))) >>
- 0; /* 0xBF[1:0] */
- u8 ext_type_lna_5g_b = (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] &
- (BIT(5) | BIT(4))) >>
- 4; /* 0xBF[5:4] */
-
- _rtl8822be_read_pa_type(hw, hwinfo, autoload_fail);
-
- /* [2.4G] Path A and B are both extPA */
- if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4)))
- rtlhal->type_gpa = ext_type_pa_2g_b << 2 | ext_type_pa_2g_a;
-
- /* [5G] Path A and B are both extPA */
- if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0)))
- rtlhal->type_apa = ext_type_pa_5g_b << 2 | ext_type_pa_5g_a;
-
- /* [2.4G] Path A and B are both extLNA */
- if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
- rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a;
-
- /* [5G] Path A and B are both extLNA */
- if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
- rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a;
-}
-
-static void _rtl8822be_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
- bool autoload_fail)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
-
- if (!autoload_fail)
- rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION_8822B];
- else
- rtlhal->rfe_type = 0;
-
- if (rtlhal->rfe_type == 0xFF)
- rtlhal->rfe_type = 0;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RFE Type: 0x%2x\n",
- rtlhal->rfe_type);
-}
-
-static void _rtl8822be_read_adapter_info(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- struct rtl_halmac_ops *halmac_ops = rtlpriv->halmac.ops;
- u16 i, usvalue;
- u8 *hwinfo;
- u16 eeprom_id;
- u32 efuse_size;
- int err;
-
- if (rtlefuse->epromtype != EEPROM_BOOT_EFUSE) {
- pr_err("RTL8822B Not boot from efuse!!");
- return;
- }
-
- /* read logical efuse size (normalely, 0x0300) */
- err = halmac_ops->halmac_get_logical_efuse_size(rtlpriv, &efuse_size);
-
- if (err || !efuse_size) {
- pr_err("halmac_get_logical_efuse_size err=%d efuse_size=0x%X",
- err, efuse_size);
- efuse_size = HWSET_MAX_SIZE;
- }
-
- if (efuse_size > HWSET_MAX_SIZE) {
- pr_err("halmac_get_logical_efuse_size efuse_size=0x%X > 0x%X",
- efuse_size, HWSET_MAX_SIZE);
- efuse_size = HWSET_MAX_SIZE;
- }
-
- /* read efuse */
- hwinfo = kzalloc(efuse_size, GFP_KERNEL);
-
- err = halmac_ops->halmac_read_logical_efuse_map(rtlpriv, hwinfo,
- efuse_size);
- if (err) {
- pr_err("%s: <ERROR> fail to get efuse map!\n", __func__);
- goto label_end;
- }
-
- /* copy to efuse_map (need?) */
- memcpy(&rtlefuse->efuse_map[EFUSE_INIT_MAP][0], hwinfo,
- EFUSE_MAX_LOGICAL_SIZE);
- memcpy(&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0], hwinfo,
- EFUSE_MAX_LOGICAL_SIZE);
-
- /* parse content */
- RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n", hwinfo,
- HWSET_MAX_SIZE);
-
- eeprom_id = *((u16 *)&hwinfo[0]);
- if (eeprom_id != RTL8822B_EEPROM_ID) {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
- rtlefuse->autoload_failflag = true;
- } else {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
- rtlefuse->autoload_failflag = false;
- }
-
- if (rtlefuse->autoload_failflag)
- goto label_end;
-
- /*VID DID SVID SDID*/
- rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
- rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
- rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
- rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM VID = 0x%4x\n",
- rtlefuse->eeprom_vid);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM DID = 0x%4x\n",
- rtlefuse->eeprom_did);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM SVID = 0x%4x\n",
- rtlefuse->eeprom_svid);
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM SMID = 0x%4x\n",
- rtlefuse->eeprom_smid);
- /*customer ID*/
- rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOM_ID_8822B];
- if (rtlefuse->eeprom_oemid == 0xFF)
- rtlefuse->eeprom_oemid = 0;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
- rtlefuse->eeprom_oemid);
- /*EEPROM version*/
- rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION_8822B];
- /*mac address*/
- for (i = 0; i < 6; i += 2) {
- usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_8822BE + i];
- *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
- }
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "dev_addr: %pM\n",
- rtlefuse->dev_addr);
-
- /* channel plan */
- rtlefuse->eeprom_channelplan =
- *(u8 *)&hwinfo[EEPROM_CHANNEL_PLAN_8822B];
-
- /* set channel plan from efuse */
- rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
- if (rtlefuse->channel_plan == 0xFF)
- rtlefuse->channel_plan = 0x7f; /* use 2G + 5G as default */
-
- /*tx power*/
- _rtl8822be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
- hwinfo);
-
- rtl8822be_read_bt_coexist_info_from_hwpg(
- hw, rtlefuse->autoload_failflag, hwinfo);
-
- /*amplifier type*/
- _rtl8822be_read_amplifier_type(hw, hwinfo, rtlefuse->autoload_failflag);
-
- /*rfe type*/
- _rtl8822be_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
-
- /*board type*/
- rtlefuse->board_type =
- (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_8822B]) & 0xE0) >> 5);
- if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_8822B]) == 0xFF)
- rtlefuse->board_type = 0;
-
- if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
- rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */
-
- /* phydm maintain rtlhal->board_type and rtlhal->package_type */
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "board_type = 0x%x\n",
- rtlefuse->board_type);
- /*parse xtal*/
- rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8822B];
- if (hwinfo[EEPROM_XTAL_8822B] == 0xFF)
- rtlefuse->crystalcap = 0; /*0x20;*/
-
- /*antenna diversity*/
- rtlefuse->antenna_div_type = 0;
- rtlefuse->antenna_div_cfg = 0;
-
-label_end:
- kfree(hwinfo);
-}
-
-static void _rtl8822be_hal_customized_behavior(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
-
- pcipriv->ledctl.led_opendrain = true;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
- rtlhal->oem_id);
-}
-
-static void _rtl8822be_read_pa_bias(struct ieee80211_hw *hw,
- struct rtl_phydm_params *params)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_halmac_ops *halmac_ops = rtlpriv->halmac.ops;
- u32 size;
- u8 *map = NULL;
-
- /* fill default values */
- params->efuse0x3d7 = 0xFF;
- params->efuse0x3d8 = 0xFF;
-
- if (halmac_ops->halmac_get_physical_efuse_size(rtlpriv, &size))
- goto err;
-
- map = kmalloc(size, GFP_KERNEL);
- if (!map)
- goto err;
-
- if (halmac_ops->halmac_read_physical_efuse_map(rtlpriv, map, size))
- goto err;
-
- params->efuse0x3d7 = map[0x3d7];
- params->efuse0x3d8 = map[0x3d8];
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "efuse0x3d7 = 0x%2x, efuse0x3d8 = 0x%2x\n",
- params->efuse0x3d7, params->efuse0x3d8);
-
-err:
- kfree(map);
-}
-
-void rtl8822be_read_eeprom_info(struct ieee80211_hw *hw,
- struct rtl_phydm_params *params)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- u8 tmp_u1b;
-
- rtlhal->version = _rtl8822be_read_chip_version(hw);
-
- params->mp_chip = (rtlhal->version & BIT_RTL_ID_8822B) ? 0 : 1;
- params->fab_ver = BIT_GET_VENDOR_ID_8822B(rtlhal->version) >> 2;
- params->cut_ver = BIT_GET_CHIP_VER_8822B(rtlhal->version);
-
- /* fab_ver mapping */
- if (params->fab_ver == 2)
- params->fab_ver = 1;
- else if (params->fab_ver == 1)
- params->fab_ver = 2;
-
- /* read PA bias: params->efuse0x3d7/efuse0x3d8 */
- _rtl8822be_read_pa_bias(hw, params);
-
- if (get_rf_type(rtlphy) == RF_1T1R)
- rtlpriv->dm.rfpath_rxenable[0] = true;
- else
- rtlpriv->dm.rfpath_rxenable[0] =
- rtlpriv->dm.rfpath_rxenable[1] = true;
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
- rtlhal->version);
- tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_EEPROM_CTRL_8822B);
- if (tmp_u1b & BIT(4)) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
- rtlefuse->epromtype = EEPROM_93C46;
- } else {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
- rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
- }
- if (tmp_u1b & BIT(5)) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
- rtlefuse->autoload_failflag = false;
- _rtl8822be_read_adapter_info(hw);
- } else {
- pr_err("Autoload ERR!!\n");
- }
- _rtl8822be_hal_customized_behavior(hw);
-
- rtlphy->rfpath_rx_enable[0] = true;
- if (rtlphy->rf_type == RF_2T2R)
- rtlphy->rfpath_rx_enable[1] = true;
-}
-
-void rtl8822be_read_eeprom_info_dummy(struct ieee80211_hw *hw)
-{
- /*
- * 8822b use halmac, so
- * move rtl8822be_read_eeprom_info() to rtl8822be_init_sw_vars()
- * after halmac_init_adapter().
- */
-}
-
-static u32 _rtl8822be_rate_to_bitmap_2ssvht(__le16 vht_rate)
-{
- u8 i, j, tmp_rate;
- u32 rate_bitmap = 0;
-
- for (i = j = 0; i < 4; i += 2, j += 10) {
- tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
-
- switch (tmp_rate) {
- case 2:
- rate_bitmap = rate_bitmap | (0x03ff << j);
- break;
-
- case 1:
- rate_bitmap = rate_bitmap | (0x01ff << j);
- break;
-
- case 0:
- rate_bitmap = rate_bitmap | (0x00ff << j);
- break;
-
- default:
- break;
- }
- }
-
- return rate_bitmap;
-}
-
-static u8 _rtl8822be_get_vht_en(enum wireless_mode wirelessmode,
- u32 ratr_bitmap)
-{
- u8 ret = 0;
-
- if (wirelessmode < WIRELESS_MODE_N_24G) {
- ret = 0;
- } else if (wirelessmode == WIRELESS_MODE_AC_24G) {
- if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */
- ret = 3;
- else /* Mix, 1SS */
- ret = 2;
- } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
- ret = 1;
- } /* VHT */
-
- return ret << 4;
-}
-
-static u8 _rtl8822be_get_ra_ldpc(struct ieee80211_hw *hw, u8 mac_id,
- struct rtl_sta_info *sta_entry,
- enum wireless_mode wirelessmode)
-{
- u8 b_ldpc = 0;
- /*not support ldpc, do not open*/
- return b_ldpc << 2;
-}
-
-static u8 _rtl8822be_get_ra_rftype(struct ieee80211_hw *hw,
- enum wireless_mode wirelessmode,
- u32 ratr_bitmap)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 rf_type = RF_1T1R;
-
- if (rtlphy->rf_type == RF_1T1R) {
- rf_type = RF_1T1R;
- } else if (wirelessmode == WIRELESS_MODE_AC_5G ||
- wirelessmode == WIRELESS_MODE_AC_24G ||
- wirelessmode == WIRELESS_MODE_AC_ONLY) {
- if (ratr_bitmap & 0xffc00000)
- rf_type = RF_2T2R;
- } else if (wirelessmode == WIRELESS_MODE_N_5G ||
- wirelessmode == WIRELESS_MODE_N_24G) {
- if (ratr_bitmap & 0xfff00000)
- rf_type = RF_2T2R;
- }
-
- return rf_type;
-}
-
-static bool _rtl8822be_get_ra_shortgi(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u8 mac_id)
-{
- bool b_short_gi = false;
- u8 b_curshortgi_40mhz =
- (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1 : 0;
- u8 b_curshortgi_20mhz =
- (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1 : 0;
- u8 b_curshortgi_80mhz = 0;
-
- b_curshortgi_80mhz =
- (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
-
- if (mac_id == 99 /*MAC_ID_STATIC_FOR_BROADCAST_MULTICAST*/)
- b_short_gi = false;
-
- if (b_curshortgi_40mhz || b_curshortgi_80mhz || b_curshortgi_20mhz)
- b_short_gi = true;
-
- return b_short_gi;
-}
-
-static void rtl8822be_update_hal_rate_mask(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- u8 rssi_level, bool update_bw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_sta_info *sta_entry = NULL;
- u32 ratr_bitmap, ratr_bitmap_msb = 0;
- u8 ratr_index;
- enum wireless_mode wirelessmode = 0;
- bool b_shortgi = false;
- u8 rate_mask[7];
- u8 macid = 0;
- u8 rf_type;
-
- sta_entry = (struct rtl_sta_info *)sta->drv_priv;
- wirelessmode = sta_entry->wireless_mode;
-
- RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, "wireless mode = 0x%x\n",
- wirelessmode);
- if (mac->opmode == NL80211_IFTYPE_AP ||
- mac->opmode == NL80211_IFTYPE_ADHOC)
- macid = sta->aid + 1;
- if (wirelessmode == WIRELESS_MODE_N_5G ||
- wirelessmode == WIRELESS_MODE_AC_5G ||
- wirelessmode == WIRELESS_MODE_A)
- ratr_bitmap = (sta->supp_rates[NL80211_BAND_5GHZ]) << 4;
- else
- ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
-
- if (mac->opmode == NL80211_IFTYPE_ADHOC)
- ratr_bitmap = 0xfff;
-
- if (wirelessmode == WIRELESS_MODE_N_24G ||
- wirelessmode == WIRELESS_MODE_N_5G)
- ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
- sta->ht_cap.mcs.rx_mask[0] << 12);
- else if (wirelessmode == WIRELESS_MODE_AC_24G ||
- wirelessmode == WIRELESS_MODE_AC_5G ||
- wirelessmode == WIRELESS_MODE_AC_ONLY)
- ratr_bitmap |= _rtl8822be_rate_to_bitmap_2ssvht(
- sta->vht_cap.vht_mcs.rx_mcs_map)
- << 12;
-
- b_shortgi = _rtl8822be_get_ra_shortgi(hw, sta, macid);
- rf_type = _rtl8822be_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
-
- ratr_index = rtlpriv->phydm.ops->phydm_rate_id_mapping(
- rtlpriv, wirelessmode, rf_type, rtlphy->current_chan_bw);
- sta_entry->ratr_index = ratr_index;
-
- rtlpriv->phydm.ops->phydm_get_ra_bitmap(
- rtlpriv, wirelessmode, rf_type, rtlphy->current_chan_bw,
- rssi_level, &ratr_bitmap_msb, &ratr_bitmap);
-
- RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, "ratr_bitmap :%x\n",
- ratr_bitmap);
-
- rate_mask[0] = macid;
- rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
- rate_mask[2] =
- rtlphy->current_chan_bw | ((!update_bw) << 3) |
- _rtl8822be_get_vht_en(wirelessmode, ratr_bitmap) |
- _rtl8822be_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
-
- rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
- rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
- rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
- rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
-
- RT_TRACE(
- rtlpriv, COMP_RATR, DBG_DMESG,
- "Rate_index:%x, ratr_val:%08x, %02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
- ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
- rate_mask[2], rate_mask[3], rate_mask[4], rate_mask[5],
- rate_mask[6]);
- rtl8822be_fill_h2c_cmd(hw, H2C_8822B_MACID_CFG, 7, rate_mask);
-
- /* for h2c cmd 0x46, only modify cmd id & ra mask */
- /* Keep rate_mask0~2 of cmd 0x40, but clear byte3 and later */
- /* 8822B has no 3SS, so keep it zeros. */
- memset(rate_mask + 3, 0, 4);
-
- rtl8822be_fill_h2c_cmd(hw, H2C_8822B_MACID_CFG_3SS, 7, rate_mask);
-
- _rtl8822be_set_bcn_ctrl_reg(hw, BIT(3), 0);
-}
-
-void rtl8822be_update_hal_rate_tbl(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u8 rssi_level,
- bool update_bw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- if (rtlpriv->dm.useramask)
- rtl8822be_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
-}
-
-void rtl8822be_update_channel_access_setting(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- u16 sifs_timer;
-
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
- (u8 *)&mac->slot_time);
- if (!mac->ht_enable)
- sifs_timer = 0x0a0a;
- else
- sifs_timer = 0x0e0e;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
-}
-
-bool rtl8822be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
-{
- *valid = 1;
- return true;
-}
-
-void rtl8822be_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
- bool is_group, u8 enc_algo, bool is_wepkey,
- bool clear_all)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- u8 *macaddr = p_macaddr;
- u32 entry_id = 0;
- bool is_pairwise = false;
-
- static u8 cam_const_addr[4][6] = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x03},
- };
- static u8 cam_const_broad[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-
- if (clear_all) {
- u8 idx = 0;
- u8 cam_offset = 0;
- u8 clear_number = 5;
-
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
-
- for (idx = 0; idx < clear_number; idx++) {
- rtl_cam_mark_invalid(hw, cam_offset + idx);
- rtl_cam_empty_entry(hw, cam_offset + idx);
-
- if (idx < 5) {
- memset(rtlpriv->sec.key_buf[idx], 0,
- MAX_KEY_LEN);
- rtlpriv->sec.key_len[idx] = 0;
- }
- }
-
- return;
- }
-
- switch (enc_algo) {
- case WEP40_ENCRYPTION:
- enc_algo = CAM_WEP40;
- break;
- case WEP104_ENCRYPTION:
- enc_algo = CAM_WEP104;
- break;
- case TKIP_ENCRYPTION:
- enc_algo = CAM_TKIP;
- break;
- case AESCCMP_ENCRYPTION:
- enc_algo = CAM_AES;
- break;
- default:
- RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case %#x not processed\n", enc_algo);
- enc_algo = CAM_TKIP;
- break;
- }
-
- if (is_wepkey || rtlpriv->sec.use_defaultkey) {
- macaddr = cam_const_addr[key_index];
- entry_id = key_index;
- } else {
- if (is_group) {
- macaddr = cam_const_broad;
- entry_id = key_index;
- } else {
- if (mac->opmode == NL80211_IFTYPE_AP) {
- entry_id =
- rtl_cam_get_free_entry(hw, p_macaddr);
- if (entry_id >= TOTAL_CAM_ENTRY) {
- pr_err("Can not find free hwsecurity cam entry\n");
- return;
- }
- } else {
- entry_id = CAM_PAIRWISE_KEY_POSITION;
- }
-
- key_index = PAIRWISE_KEYIDX;
- is_pairwise = true;
- }
- }
-
- if (rtlpriv->sec.key_len[key_index] == 0) {
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "delete one entry, entry_id is %d\n", entry_id);
- if (mac->opmode == NL80211_IFTYPE_AP)
- rtl_cam_del_entry(hw, p_macaddr);
- rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
- } else {
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "add one entry\n");
- if (is_pairwise) {
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "set Pairwise key\n");
-
- rtl_cam_add_one_entry(hw, macaddr, key_index, entry_id,
- enc_algo, CAM_CONFIG_NO_USEDK,
- rtlpriv->sec.key_buf[key_index]);
- } else {
- RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
- "set group key\n");
-
- if (mac->opmode == NL80211_IFTYPE_ADHOC) {
- rtl_cam_add_one_entry(
- hw, rtlefuse->dev_addr, PAIRWISE_KEYIDX,
- CAM_PAIRWISE_KEY_POSITION, enc_algo,
- CAM_CONFIG_NO_USEDK,
- rtlpriv->sec.key_buf[entry_id]);
- }
-
- rtl_cam_add_one_entry(hw, macaddr, key_index, entry_id,
- enc_algo, CAM_CONFIG_NO_USEDK,
- rtlpriv->sec.key_buf[entry_id]);
- }
- }
-}
-
-void rtl8822be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
- bool auto_load_fail, u8 *hwinfo)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 value;
- u32 val32;
-
- val32 = rtl_read_dword(rtlpriv, REG_WL_BT_PWR_CTRL_8822B);
- if (val32 & BIT_BT_FUNC_EN_8822B)
- rtlpriv->btcoexist.btc_info.btcoexist = 1;
- else
- rtlpriv->btcoexist.btc_info.btcoexist = 0;
-
- if (!auto_load_fail) {
- value = hwinfo[EEPROM_RF_BT_SETTING_8822B];
-
- rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8822B;
- rtlpriv->btcoexist.btc_info.ant_num =
- (value & BIT(0) ? ANT_TOTAL_X1 : ANT_TOTAL_X2);
- } else {
- rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8822B;
- rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2;
- }
-}
-
-void rtl8822be_bt_reg_init(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- /* 0:Low, 1:High, 2:From Efuse. */
- rtlpriv->btcoexist.reg_bt_iso = 2;
- /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
- rtlpriv->btcoexist.reg_bt_sco = 3;
- /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
- rtlpriv->btcoexist.reg_bt_sco = 0;
-}
-
-void rtl8822be_suspend(struct ieee80211_hw *hw) {}
-
-void rtl8822be_resume(struct ieee80211_hw *hw) {}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL8822B_HW_H__
-#define __RTL8822B_HW_H__
-
-extern u8 rtl_channel5g[CHANNEL_MAX_NUMBER_5G];
-extern u8 rtl_channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
-
-void rtl8822be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
-void rtl8822be_read_eeprom_info(struct ieee80211_hw *hw,
- struct rtl_phydm_params *params);
-void rtl8822be_read_eeprom_info_dummy(struct ieee80211_hw *hw);
-void rtl8822be_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
- u32 *p_intb, u32 *p_intc, u32 *p_intd);
-int rtl8822be_hw_init(struct ieee80211_hw *hw);
-void rtl8822be_card_disable(struct ieee80211_hw *hw);
-void rtl8822be_enable_interrupt(struct ieee80211_hw *hw);
-void rtl8822be_disable_interrupt(struct ieee80211_hw *hw);
-int rtl8822be_set_network_type(struct ieee80211_hw *hw,
- enum nl80211_iftype type);
-void rtl8822be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
-void rtl8822be_set_qos(struct ieee80211_hw *hw, int aci);
-void rtl8822be_set_beacon_related_registers(struct ieee80211_hw *hw);
-void rtl8822be_set_beacon_interval(struct ieee80211_hw *hw);
-void rtl8822be_update_interrupt_mask(struct ieee80211_hw *hw, u32 add_msr,
- u32 rm_msr);
-void rtl8822be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
-void rtl8822be_update_hal_rate_tbl(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u8 rssi_level,
- bool update_bw);
-void rtl8822be_update_channel_access_setting(struct ieee80211_hw *hw);
-bool rtl8822be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
-void rtl8822be_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
- bool is_group, u8 enc_algo, bool is_wepkey,
- bool clear_all);
-void rtl8822be_enable_hw_security_config(struct ieee80211_hw *hw);
-void rtl8822be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
- bool autoload_fail, u8 *hwinfo);
-void rtl8822be_bt_reg_init(struct ieee80211_hw *hw);
-void rtl8822be_suspend(struct ieee80211_hw *hw);
-void rtl8822be_resume(struct ieee80211_hw *hw);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../wifi.h"
-#include "../pci.h"
-#include "reg.h"
-#include "led.h"
-
-static void _rtl8822be_init_led(struct ieee80211_hw *hw, struct rtl_led *pled,
- enum rtl_led_pin ledpin)
-{
- pled->hw = hw;
- pled->ledpin = ledpin;
- pled->ledon = false;
-}
-
-void rtl8822be_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- REG_LEDCFG2_8822B, pled->ledpin);
-
- switch (pled->ledpin) {
- case LED_PIN_GPIO0:
- break;
- case LED_PIN_LED0:
- break;
- case LED_PIN_LED1:
- break;
- default:
- RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case not process\n");
- break;
- }
- pled->ledon = true;
-}
-
-void rtl8822be_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, "LedAddr:%X ledpin=%d\n",
- REG_LEDCFG2_8822B, pled->ledpin);
-
- switch (pled->ledpin) {
- case LED_PIN_GPIO0:
- break;
- case LED_PIN_LED0:
- break;
- case LED_PIN_LED1:
-
- break;
- default:
- RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
- "switch case not process\n");
- break;
- }
- pled->ledon = false;
-}
-
-void rtl8822be_init_sw_leds(struct ieee80211_hw *hw)
-{
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
-
- _rtl8822be_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0);
- _rtl8822be_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1);
-}
-
-static void _rtl8822be_sw_led_control(struct ieee80211_hw *hw,
- enum led_ctl_mode ledaction)
-{
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_led *led0 = &pcipriv->ledctl.sw_led0;
-
- switch (ledaction) {
- case LED_CTL_POWER_ON:
- case LED_CTL_LINK:
- case LED_CTL_NO_LINK:
- rtl8822be_sw_led_on(hw, led0);
- break;
- case LED_CTL_POWER_OFF:
- rtl8822be_sw_led_off(hw, led0);
- break;
- default:
- break;
- }
-}
-
-void rtl8822be_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
-
- if (ppsc->rfoff_reason > RF_CHANGE_BY_PS &&
- (ledaction == LED_CTL_TX || ledaction == LED_CTL_RX ||
- ledaction == LED_CTL_SITE_SURVEY || ledaction == LED_CTL_LINK ||
- ledaction == LED_CTL_NO_LINK ||
- ledaction == LED_CTL_START_TO_LINK ||
- ledaction == LED_CTL_POWER_ON)) {
- return;
- }
- RT_TRACE(rtlpriv, COMP_LED, DBG_TRACE, "ledaction %d,\n", ledaction);
- _rtl8822be_sw_led_control(hw, ledaction);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL8822B_LED_H__
-#define __RTL8822B_LED_H__
-
-void rtl8822be_init_sw_leds(struct ieee80211_hw *hw);
-void rtl8822be_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl8822be_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
-void rtl8822be_led_control(struct ieee80211_hw *hw,
- enum led_ctl_mode ledaction);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../wifi.h"
-#include "../pci.h"
-#include "../ps.h"
-#include "../base.h"
-#include "reg.h"
-#include "def.h"
-#include "phy.h"
-#include "trx.h"
-#include "../btcoexist/halbt_precomp.h"
-#include "hw.h"
-#include "../efuse.h"
-
-static u32 _rtl8822be_phy_calculate_bit_shift(u32 bitmask);
-static void
-_rtl8822be_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
-
-static long _rtl8822be_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
- enum wireless_mode wirelessmode,
- u8 txpwridx);
-static void rtl8822be_phy_set_rf_on(struct ieee80211_hw *hw);
-static void rtl8822be_phy_set_io(struct ieee80211_hw *hw);
-
-static u8 cck_rates[] = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M};
-static u8 sizes_of_cck_retes = 4;
-static u8 ofdm_rates[] = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
- DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
- DESC_RATE48M, DESC_RATE54M};
-static u8 sizes_of_ofdm_retes = 8;
-static u8 ht_rates_1t[] = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
- DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
- DESC_RATEMCS6, DESC_RATEMCS7};
-static u8 sizes_of_ht_retes_1t = 8;
-static u8 ht_rates_2t[] = {DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10,
- DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13,
- DESC_RATEMCS14, DESC_RATEMCS15};
-static u8 sizes_of_ht_retes_2t = 8;
-static u8 vht_rates_1t[] = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
- DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
- DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
- DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
- DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9};
-static u8 vht_rates_2t[] = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
- DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
- DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
- DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
- DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9};
-static u8 sizes_of_vht_retes = 10;
-
-u32 rtl8822be_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
- u32 bitmask)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u32 returnvalue, originalvalue, bitshift;
-
- RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
- regaddr, bitmask);
- originalvalue = rtl_read_dword(rtlpriv, regaddr);
- bitshift = _rtl8822be_phy_calculate_bit_shift(bitmask);
- returnvalue = (originalvalue & bitmask) >> bitshift;
-
- RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
- bitmask, regaddr, originalvalue);
-
- return returnvalue;
-}
-
-void rtl8822be_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
- u32 data)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u32 originalvalue, bitshift;
-
- RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
- "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask,
- data);
-
- if (bitmask != MASKDWORD) {
- originalvalue = rtl_read_dword(rtlpriv, regaddr);
- bitshift = _rtl8822be_phy_calculate_bit_shift(bitmask);
- data = ((originalvalue & (~bitmask)) |
- ((data << bitshift) & bitmask));
- }
-
- rtl_write_dword(rtlpriv, regaddr, data);
-
- RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
- "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask,
- data);
-}
-
-u32 rtl8822be_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
- u32 regaddr, u32 bitmask)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u32 /*original_value,*/ readback_value /*, bitshift*/;
- unsigned long flags;
-
- RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
- "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", regaddr, rfpath,
- bitmask);
-
- spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
-
- readback_value = rtlpriv->phydm.ops->phydm_read_rf_reg(
- rtlpriv, rfpath, regaddr, bitmask);
-
- spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
-
- return readback_value;
-}
-
-void rtl8822be_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
- u32 regaddr, u32 bitmask, u32 data)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- unsigned long flags;
-
- RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
- "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
- regaddr, bitmask, data, rfpath);
-
- spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
-
- rtlpriv->phydm.ops->phydm_write_rf_reg(rtlpriv, rfpath, regaddr,
- bitmask, data);
-
- spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
-
- RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
- "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
- regaddr, bitmask, data, rfpath);
-}
-
-static u32 _rtl8822be_phy_calculate_bit_shift(u32 bitmask)
-{
- u32 i;
-
- for (i = 0; i <= 31; i++) {
- if (((bitmask >> i) & 0x1) == 1)
- break;
- }
- return i;
-}
-
-bool rtl8822be_halmac_cb_init_mac_register(struct rtl_priv *rtlpriv)
-{
- return rtlpriv->phydm.ops->phydm_phy_mac_config(rtlpriv);
-}
-
-bool rtl8822be_phy_bb_config(struct ieee80211_hw *hw)
-{
- bool rtstatus = true;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- u8 crystal_cap;
- /* u32 tmp; */
-
- rtstatus = rtlpriv->phydm.ops->phydm_phy_bb_config(rtlpriv);
-
- /* write 0x28[6:1] = 0x24[30:25] = CrystalCap */
- crystal_cap = rtlefuse->crystalcap & 0x3F;
- rtl_set_bbreg(hw, REG_AFE_XTAL_CTRL_8822B, 0x7E000000, crystal_cap);
- rtl_set_bbreg(hw, REG_AFE_PLL_CTRL_8822B, 0x7E, crystal_cap);
-
- /*rtlphy->reg_837 = rtl_read_byte(rtlpriv, 0x837);*/ /*unused*/
-
- return rtstatus;
-}
-
-bool rtl8822be_phy_rf_config(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
-
- if (rtlphy->rf_type == RF_1T1R)
- rtlphy->num_total_rfpath = 1;
- else
- rtlphy->num_total_rfpath = 2;
-
- return rtlpriv->phydm.ops->phydm_phy_rf_config(rtlpriv);
-}
-
-bool rtl8822be_halmac_cb_init_bb_rf_register(struct rtl_priv *rtlpriv)
-{
- struct ieee80211_hw *hw = rtlpriv->hw;
- enum radio_mask txpath, rxpath;
- bool tx2path;
- bool ret = false;
-
- _rtl8822be_phy_init_bb_rf_register_definition(hw);
-
- rtlpriv->halmac.ops->halmac_phy_power_switch(rtlpriv, 1);
-
- /* beofre bb/rf config */
- rtlpriv->phydm.ops->phydm_parameter_init(rtlpriv, 0);
-
- /* do bb/rf config */
- if (rtl8822be_phy_bb_config(hw) && rtl8822be_phy_rf_config(hw))
- ret = true;
-
- /* after bb/rf config */
- rtlpriv->phydm.ops->phydm_parameter_init(rtlpriv, 1);
-
- /* set trx mode (keep it to be last, r17376) */
- txpath = RF_MASK_A | RF_MASK_B;
- rxpath = RF_MASK_A | RF_MASK_B;
- tx2path = false;
- return rtlpriv->phydm.ops->phydm_trx_mode(rtlpriv, txpath, rxpath,
- tx2path);
-}
-
-static void _rtl8822be_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
-
- u8 band, rfpath, txnum, rate;
-
- for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
- for (rfpath = 0; rfpath < TX_PWR_BY_RATE_NUM_RF; ++rfpath)
- for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
- for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE;
- ++rate)
- rtlphy->tx_power_by_rate_offset
- [band][rfpath][txnum][rate] = 0;
-}
-
-static void _rtl8822be_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
- u8 band, u8 path,
- u8 rate_section, u8 txnum,
- u8 value)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
-
- if (path > RF90_PATH_D) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n",
- path);
- return;
- }
-
- if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Invalid band %d in phy_SetTxPowerByRatBase()\n",
- band);
- return;
- }
-
- if (rate_section >= MAX_RATE_SECTION ||
- (band == BAND_ON_5G && rate_section == CCK)) {
- RT_TRACE(
- rtlpriv, COMP_INIT, DBG_LOUD,
- "Invalid rate_section %d in phy_SetTxPowerByRatBase()\n",
- rate_section);
- return;
- }
-
- if (band == BAND_ON_2_4G)
- rtlphy->txpwr_by_rate_base_24g[path][txnum][rate_section] =
- value;
- else /* BAND_ON_5G */
- rtlphy->txpwr_by_rate_base_5g[path][txnum][rate_section - 1] =
- value;
-}
-
-static u8 _rtl8822be_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
- u8 band, u8 path, u8 txnum,
- u8 rate_section)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 value;
-
- if (path > RF90_PATH_D) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Invalid Rf Path %d in phy_GetTxPowerByRatBase()\n",
- path);
- return 0;
- }
-
- if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "Invalid band %d in phy_GetTxPowerByRatBase()\n",
- band);
- return 0;
- }
-
- if (rate_section >= MAX_RATE_SECTION ||
- (band == BAND_ON_5G && rate_section == CCK)) {
- RT_TRACE(
- rtlpriv, COMP_INIT, DBG_LOUD,
- "Invalid rate_section %d in phy_GetTxPowerByRatBase()\n",
- rate_section);
- return 0;
- }
-
- if (band == BAND_ON_2_4G)
- value = rtlphy->txpwr_by_rate_base_24g[path][txnum]
- [rate_section];
- else /* BAND_ON_5G */
- value = rtlphy->txpwr_by_rate_base_5g[path][txnum]
- [rate_section - 1];
-
- return value;
-}
-
-static void _rtl8822be_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
-
- struct {
- enum rtl_desc_rate rate;
- enum rate_section section;
- } rate_sec_base[] = {
- {DESC_RATE11M, CCK},
- {DESC_RATE54M, OFDM},
- {DESC_RATEMCS7, HT_MCS0_MCS7},
- {DESC_RATEMCS15, HT_MCS8_MCS15},
- {DESC_RATEVHT1SS_MCS7, VHT_1SSMCS0_1SSMCS9},
- {DESC_RATEVHT2SS_MCS7, VHT_2SSMCS0_2SSMCS9},
- };
-
- u8 band, path, rs, tx_num, base;
- u8 rate, section;
-
- for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
- for (path = RF90_PATH_A; path <= RF90_PATH_B; path++) {
- for (rs = 0; rs < MAX_RATE_SECTION; rs++) {
- rate = rate_sec_base[rs].rate;
- section = rate_sec_base[rs].section;
-
- if (IS_1T_RATE(rate))
- tx_num = RF_1TX;
- else
- tx_num = RF_2TX;
-
- if (band == BAND_ON_5G &&
- RX_HAL_IS_CCK_RATE(rate))
- continue;
-
- base = rtlphy->tx_power_by_rate_offset
- [band][path][tx_num][rate];
- _rtl8822be_phy_set_txpower_by_rate_base(
- hw, band, path, section, tx_num, base);
- }
- }
- }
-}
-
-static void __rtl8822be_phy_cross_reference_core(struct ieee80211_hw *hw,
- u8 regulation, u8 bw,
- u8 channel)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 rs, ref_rs;
- s8 pwrlmt, ref_pwrlmt;
-
- for (rs = 0; rs < MAX_RATE_SECTION_NUM; ++rs) {
- /*5G 20M 40M VHT and HT can cross reference*/
- if (bw != HT_CHANNEL_WIDTH_20 && bw != HT_CHANNEL_WIDTH_20_40)
- continue;
-
- if (rs == HT_MCS0_MCS7)
- ref_rs = VHT_1SSMCS0_1SSMCS9;
- else if (rs == HT_MCS8_MCS15)
- ref_rs = VHT_2SSMCS0_2SSMCS9;
- else if (rs == VHT_1SSMCS0_1SSMCS9)
- ref_rs = HT_MCS0_MCS7;
- else if (rs == VHT_2SSMCS0_2SSMCS9)
- ref_rs = HT_MCS8_MCS15;
- else
- continue;
-
- ref_pwrlmt = rtlphy->txpwr_limit_5g[regulation][bw][ref_rs]
- [channel][RF90_PATH_A];
- if (ref_pwrlmt == MAX_POWER_INDEX)
- continue;
-
- pwrlmt = rtlphy->txpwr_limit_5g[regulation][bw][rs][channel]
- [RF90_PATH_A];
- if (pwrlmt != MAX_POWER_INDEX)
- continue;
-
- rtlphy->txpwr_limit_5g[regulation][bw][rs][channel]
- [RF90_PATH_A] = ref_pwrlmt;
- }
-}
-
-static void
-_rtl8822be_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw *hw)
-{
- u8 regulation, bw, channel;
-
- for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
- for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
- for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G;
- ++channel) {
- __rtl8822be_phy_cross_reference_core(
- hw, regulation, bw, channel);
- }
- }
- }
-}
-
-static void __rtl8822be_txpwr_limit_to_index_2g(struct ieee80211_hw *hw,
- u8 regulation, u8 bw,
- u8 channel)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 bw40_pwr_base_dbm2_4G;
- u8 rate_section;
- s8 temp_pwrlmt;
- enum rf_tx_num txnum;
- s8 temp_value;
- u8 rf_path;
-
- for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM;
- ++rate_section) {
- /* obtain the base dBm values in 2.4G band
- * CCK => 11M, OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15
- */
-
- temp_pwrlmt =
- rtlphy->txpwr_limit_2_4g[regulation][bw][rate_section]
- [channel][RF90_PATH_A];
- txnum = IS_1T_RATESEC(rate_section) ? RF_1TX : RF_2TX;
-
- if (temp_pwrlmt == MAX_POWER_INDEX)
- continue;
-
- for (rf_path = RF90_PATH_A; rf_path < MAX_RF_PATH_NUM;
- ++rf_path) {
- bw40_pwr_base_dbm2_4G =
- _rtl8822be_phy_get_txpower_by_rate_base(
- hw, BAND_ON_2_4G, rf_path, txnum,
- rate_section);
-
- temp_value = temp_pwrlmt - bw40_pwr_base_dbm2_4G;
- rtlphy->txpwr_limit_2_4g[regulation][bw][rate_section]
- [channel][rf_path] = temp_value;
-
- RT_TRACE(
- rtlpriv, COMP_INIT, DBG_TRACE,
- "TxPwrLimit_2_4G[regulation %d][bw %d][rateSection %d][channel %d] = %d\n(TxPwrLimit in dBm %d - BW40PwrLmt2_4G[channel %d][rfPath %d] %d)\n",
- regulation, bw, rate_section, channel,
- rtlphy->txpwr_limit_2_4g[regulation][bw]
- [rate_section][channel]
- [rf_path],
- (temp_pwrlmt == 63) ? 0 : temp_pwrlmt / 2,
- channel, rf_path, bw40_pwr_base_dbm2_4G);
- }
- }
-}
-
-static void __rtl8822be_txpwr_limit_to_index_5g(struct ieee80211_hw *hw,
- u8 regulation, u8 bw,
- u8 channel)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 bw40_pwr_base_dbm5G;
- u8 rate_section;
- s8 temp_pwrlmt;
- enum rf_tx_num txnum;
- s8 temp_value;
- u8 rf_path;
-
- for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM;
- ++rate_section) {
- /* obtain the base dBm values in 5G band
- * OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15,
- * VHT => 1SSMCS7, VHT 2T => 2SSMCS7
- */
-
- temp_pwrlmt =
- rtlphy->txpwr_limit_5g[regulation][bw][rate_section]
- [channel][RF90_PATH_A];
- txnum = IS_1T_RATESEC(rate_section) ? RF_1TX : RF_2TX;
-
- if (temp_pwrlmt == MAX_POWER_INDEX)
- continue;
-
- for (rf_path = RF90_PATH_A; rf_path < MAX_RF_PATH_NUM;
- ++rf_path) {
- bw40_pwr_base_dbm5G =
- _rtl8822be_phy_get_txpower_by_rate_base(
- hw, BAND_ON_5G, rf_path, txnum,
- rate_section);
-
- temp_value = temp_pwrlmt - bw40_pwr_base_dbm5G;
- rtlphy->txpwr_limit_5g[regulation][bw][rate_section]
- [channel][rf_path] = temp_value;
-
- RT_TRACE(
- rtlpriv, COMP_INIT, DBG_TRACE,
- "TxPwrLimit_5G[regulation %d][bw %d][rateSection %d][channel %d] =%d\n(TxPwrLimit in dBm %d - BW40PwrLmt5G[chnl group %d][rfPath %d] %d)\n",
- regulation, bw, rate_section, channel,
- rtlphy->txpwr_limit_5g[regulation][bw]
- [rate_section][channel]
- [rf_path],
- temp_pwrlmt, channel, rf_path,
- bw40_pwr_base_dbm5G);
- }
- }
-}
-
-static void
-_rtl8822be_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 regulation, bw, channel;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "=====> %s()\n", __func__);
-
- _rtl8822be_phy_cross_reference_ht_and_vht_txpower_limit(hw);
-
- for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
- for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
- for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G;
- ++channel) {
- __rtl8822be_txpwr_limit_to_index_2g(
- hw, regulation, bw, channel);
- }
- }
- }
-
- for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
- for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
- for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G;
- ++channel) {
- __rtl8822be_txpwr_limit_to_index_5g(
- hw, regulation, bw, channel);
- }
- }
- }
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "<===== %s()\n", __func__);
-}
-
-static void _rtl8822be_phy_init_txpower_limit(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 i, j, k, l, m;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "=====> %s()!\n", __func__);
-
- for (i = 0; i < MAX_REGULATION_NUM; ++i) {
- for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
- for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
- for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
- for (l = 0; l < MAX_RF_PATH_NUM; ++l)
- rtlphy->txpwr_limit_2_4g[i][j]
- [k][m]
- [l] =
- MAX_POWER_INDEX;
- }
- for (i = 0; i < MAX_REGULATION_NUM; ++i) {
- for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
- for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
- for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m)
- for (l = 0; l < MAX_RF_PATH_NUM; ++l)
- rtlphy->txpwr_limit_5g[i][j][k]
- [m][l] =
- MAX_POWER_INDEX;
- }
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<===== %s()!\n", __func__);
-}
-
-static void
-_rtl8822be_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
-
- u8 base = 0, i = 0, value = 0, band = 0, path = 0, txnum = 0;
-
- for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) {
- for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
- for (txnum = RF_1TX; txnum <= RF_2TX; ++txnum) {
- /* CCK */
- base = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [DESC_RATE11M];
- for (i = 0; i < sizeof(cck_rates); ++i) {
- value = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [cck_rates[i]];
- rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [cck_rates[i]] = value - base;
- }
-
- /* OFDM */
- base = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [DESC_RATE54M];
- for (i = 0; i < sizeof(ofdm_rates); ++i) {
- value = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [ofdm_rates[i]];
- rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [ofdm_rates[i]] = value - base;
- }
-
- /* HT MCS0~7 */
- base = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [DESC_RATEMCS7];
- for (i = 0; i < sizeof(ht_rates_1t); ++i) {
- value = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [ht_rates_1t[i]];
- rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [ht_rates_1t[i]] = value - base;
- }
-
- /* HT MCS8~15 */
- base = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [DESC_RATEMCS15];
- for (i = 0; i < sizeof(ht_rates_2t); ++i) {
- value = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [ht_rates_2t[i]];
- rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [ht_rates_2t[i]] = value - base;
- }
-
- /* VHT 1SS */
- base = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [DESC_RATEVHT1SS_MCS7];
- for (i = 0; i < sizeof(vht_rates_1t); ++i) {
- value = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [vht_rates_1t[i]];
- rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [vht_rates_1t[i]] =
- value - base;
- }
-
- /* VHT 2SS */
- base = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [DESC_RATEVHT2SS_MCS7];
- for (i = 0; i < sizeof(vht_rates_2t); ++i) {
- value = rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [vht_rates_2t[i]];
- rtlphy->tx_power_by_rate_offset
- [band][path][txnum]
- [vht_rates_2t[i]] =
- value - base;
- }
- }
- }
- }
-
- RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, "<===%s()\n", __func__);
-}
-
-static void
-_rtl8822be_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
-{
- /* copy rate_section from
- * tx_power_by_rate_offset[][rate] to txpwr_by_rate_base_24g/_5g[][rs]
- */
- _rtl8822be_phy_store_txpower_by_rate_base(hw);
-
- /* convert tx_power_by_rate_offset[] to relative value */
- _rtl8822be_phy_convert_txpower_dbm_to_relative_value(hw);
-}
-
-/* string is in decimal */
-static bool _rtl8822be_get_integer_from_string(char *str, u8 *pint)
-{
- u16 i = 0;
- *pint = 0;
-
- while (str[i] != '\0') {
- if (str[i] >= '0' && str[i] <= '9') {
- *pint *= 10;
- *pint += (str[i] - '0');
- } else {
- return false;
- }
- ++i;
- }
-
- return true;
-}
-
-static bool _rtl8822be_eq_n_byte(u8 *str1, u8 *str2, u32 num)
-{
- if (num == 0)
- return false;
- while (num > 0) {
- num--;
- if (str1[num] != str2[num])
- return false;
- }
- return true;
-}
-
-static char _rtl8822be_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw,
- u8 band, u8 channel)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- char channel_index = -1;
- u8 i = 0;
-
- if (band == BAND_ON_2_4G) {
- channel_index = channel - 1;
- } else if (band == BAND_ON_5G) {
- for (i = 0; i < sizeof(rtl_channel5g) / sizeof(u8); ++i) {
- if (rtl_channel5g[i] == channel)
- channel_index = i;
- }
- } else {
- RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Band %d in %s",
- band, __func__);
- }
-
- if (channel_index == -1)
- RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
- "Invalid Channel %d of Band %d in %s", channel, band,
- __func__);
-
- return channel_index;
-}
-
-void rtl8822be_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregulation,
- u8 *pband, u8 *pbandwidth,
- u8 *prate_section, u8 *prf_path,
- u8 *pchannel, u8 *ppower_limit)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 regulation = 0, bandwidth = 0, rate_section = 0, channel;
- u8 channel_index;
- char power_limit = 0, prev_power_limit, ret;
-
- if (!_rtl8822be_get_integer_from_string((char *)pchannel, &channel) ||
- !_rtl8822be_get_integer_from_string((char *)ppower_limit,
- &power_limit)) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "Illegal index of pwr_lmt table [chnl %d][val %d]\n",
- channel, power_limit);
- }
-
- power_limit =
- power_limit > MAX_POWER_INDEX ? MAX_POWER_INDEX : power_limit;
-
- if (_rtl8822be_eq_n_byte(pregulation, (u8 *)("FCC"), 3))
- regulation = 0;
- else if (_rtl8822be_eq_n_byte(pregulation, (u8 *)("MKK"), 3))
- regulation = 1;
- else if (_rtl8822be_eq_n_byte(pregulation, (u8 *)("ETSI"), 4))
- regulation = 2;
- else if (_rtl8822be_eq_n_byte(pregulation, (u8 *)("WW13"), 4))
- regulation = 3;
-
- if (_rtl8822be_eq_n_byte(prate_section, (u8 *)("CCK"), 3))
- rate_section = CCK;
- else if (_rtl8822be_eq_n_byte(prate_section, (u8 *)("OFDM"), 4))
- rate_section = OFDM;
- else if (_rtl8822be_eq_n_byte(prate_section, (u8 *)("HT"), 2) &&
- _rtl8822be_eq_n_byte(prf_path, (u8 *)("1T"), 2))
- rate_section = HT_MCS0_MCS7;
- else if (_rtl8822be_eq_n_byte(prate_section, (u8 *)("HT"), 2) &&
- _rtl8822be_eq_n_byte(prf_path, (u8 *)("2T"), 2))
- rate_section = HT_MCS8_MCS15;
- else if (_rtl8822be_eq_n_byte(prate_section, (u8 *)("VHT"), 3) &&
- _rtl8822be_eq_n_byte(prf_path, (u8 *)("1T"), 2))
- rate_section = VHT_1SSMCS0_1SSMCS9;
- else if (_rtl8822be_eq_n_byte(prate_section, (u8 *)("VHT"), 3) &&
- _rtl8822be_eq_n_byte(prf_path, (u8 *)("2T"), 2))
- rate_section = VHT_2SSMCS0_2SSMCS9;
-
- if (_rtl8822be_eq_n_byte(pbandwidth, (u8 *)("20M"), 3))
- bandwidth = HT_CHANNEL_WIDTH_20;
- else if (_rtl8822be_eq_n_byte(pbandwidth, (u8 *)("40M"), 3))
- bandwidth = HT_CHANNEL_WIDTH_20_40;
- else if (_rtl8822be_eq_n_byte(pbandwidth, (u8 *)("80M"), 3))
- bandwidth = HT_CHANNEL_WIDTH_80;
- else if (_rtl8822be_eq_n_byte(pbandwidth, (u8 *)("160M"), 4))
- bandwidth = 3;
-
- if (_rtl8822be_eq_n_byte(pband, (u8 *)("2.4G"), 4)) {
- ret = _rtl8822be_phy_get_chnl_idx_of_txpwr_lmt(hw, BAND_ON_2_4G,
- channel);
-
- if (ret == -1)
- return;
-
- channel_index = ret;
-
- prev_power_limit =
- rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
- [rate_section][channel_index]
- [RF90_PATH_A];
-
- if (power_limit < prev_power_limit)
- rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
- [rate_section][channel_index]
- [RF90_PATH_A] = power_limit;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "2.4G [regula %d][bw %d][sec %d][chnl %d][val %d]\n",
- regulation, bandwidth, rate_section, channel_index,
- rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
- [rate_section][channel_index]
- [RF90_PATH_A]);
- } else if (_rtl8822be_eq_n_byte(pband, (u8 *)("5G"), 2)) {
- ret = _rtl8822be_phy_get_chnl_idx_of_txpwr_lmt(hw, BAND_ON_5G,
- channel);
-
- if (ret == -1)
- return;
-
- channel_index = ret;
-
- prev_power_limit =
- rtlphy->txpwr_limit_5g[regulation][bandwidth]
- [rate_section][channel_index]
- [RF90_PATH_A];
-
- if (power_limit < prev_power_limit)
- rtlphy->txpwr_limit_5g[regulation][bandwidth]
- [rate_section][channel_index]
- [RF90_PATH_A] = power_limit;
-
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "5G: [regul %d][bw %d][sec %d][chnl %d][val %d]\n",
- regulation, bandwidth, rate_section, channel,
- rtlphy->txpwr_limit_5g[regulation][bandwidth]
- [rate_section][channel_index]
- [RF90_PATH_A]);
-
- } else {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
- "Cannot recognize the band info in %s\n", pband);
- return;
- }
-}
-
-bool rtl8822be_load_txpower_by_rate(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- bool rtstatus = true;
-
- _rtl8822be_phy_init_tx_power_by_rate(hw);
-
- rtstatus = rtlpriv->phydm.ops->phydm_load_txpower_by_rate(rtlpriv);
-
- if (!rtstatus) {
- pr_err("BB_PG Reg Fail!!\n");
- return false;
- }
-
- _rtl8822be_phy_txpower_by_rate_configuration(hw);
-
- return true;
-}
-
-bool rtl8822be_load_txpower_limit(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
- bool rtstatus = true;
-
- _rtl8822be_phy_init_txpower_limit(hw);
-
- if (rtlefuse->eeprom_regulatory == 1)
- ;
- else
- return true;
-
- rtstatus = rtlpriv->phydm.ops->phydm_load_txpower_limit(rtlpriv);
-
- if (!rtstatus) {
- pr_err("RF TxPwr Limit Fail!!\n");
- return false;
- }
-
- _rtl8822be_phy_convert_txpower_limit_to_power_index(hw);
-
- return true;
-}
-
-static void _rtl8822be_get_rate_values_of_tx_power_by_rate(
- struct ieee80211_hw *hw, u32 reg_addr, u32 bit_mask, u32 value,
- u8 *rate, s8 *pwr_by_rate_val, u8 *rate_num)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 /*index = 0,*/ i = 0;
-
- switch (reg_addr) {
- case 0xE00: /*rTxAGC_A_Rate18_06:*/
- case 0x830: /*rTxAGC_B_Rate18_06:*/
- rate[0] = DESC_RATE6M;
- rate[1] = DESC_RATE9M;
- rate[2] = DESC_RATE12M;
- rate[3] = DESC_RATE18M;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xE04: /*rTxAGC_A_Rate54_24:*/
- case 0x834: /*rTxAGC_B_Rate54_24:*/
- rate[0] = DESC_RATE24M;
- rate[1] = DESC_RATE36M;
- rate[2] = DESC_RATE48M;
- rate[3] = DESC_RATE54M;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xE08: /*rTxAGC_A_CCK1_Mcs32:*/
- rate[0] = DESC_RATE1M;
- pwr_by_rate_val[0] = (s8)((((value >> (8 + 4)) & 0xF)) * 10 +
- ((value >> 8) & 0xF));
- *rate_num = 1;
- break;
-
- case 0x86C: /*rTxAGC_B_CCK11_A_CCK2_11:*/
- if (bit_mask == 0xffffff00) {
- rate[0] = DESC_RATE2M;
- rate[1] = DESC_RATE5_5M;
- rate[2] = DESC_RATE11M;
- for (i = 1; i < 4; ++i) {
- pwr_by_rate_val[i - 1] = (s8)(
- (((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 3;
- } else if (bit_mask == 0x000000ff) {
- rate[0] = DESC_RATE11M;
- pwr_by_rate_val[0] = (s8)((((value >> 4) & 0xF)) * 10 +
- (value & 0xF));
- *rate_num = 1;
- }
- break;
-
- case 0xE10: /*rTxAGC_A_Mcs03_Mcs00:*/
- case 0x83C: /*rTxAGC_B_Mcs03_Mcs00:*/
- rate[0] = DESC_RATEMCS0;
- rate[1] = DESC_RATEMCS1;
- rate[2] = DESC_RATEMCS2;
- rate[3] = DESC_RATEMCS3;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xE14: /*rTxAGC_A_Mcs07_Mcs04:*/
- case 0x848: /*rTxAGC_B_Mcs07_Mcs04:*/
- rate[0] = DESC_RATEMCS4;
- rate[1] = DESC_RATEMCS5;
- rate[2] = DESC_RATEMCS6;
- rate[3] = DESC_RATEMCS7;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xE18: /*rTxAGC_A_Mcs11_Mcs08:*/
- case 0x84C: /*rTxAGC_B_Mcs11_Mcs08:*/
- rate[0] = DESC_RATEMCS8;
- rate[1] = DESC_RATEMCS9;
- rate[2] = DESC_RATEMCS10;
- rate[3] = DESC_RATEMCS11;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xE1C: /*rTxAGC_A_Mcs15_Mcs12:*/
- case 0x868: /*rTxAGC_B_Mcs15_Mcs12:*/
- rate[0] = DESC_RATEMCS12;
- rate[1] = DESC_RATEMCS13;
- rate[2] = DESC_RATEMCS14;
- rate[3] = DESC_RATEMCS15;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
-
- break;
-
- case 0x838: /*rTxAGC_B_CCK1_55_Mcs32:*/
- rate[0] = DESC_RATE1M;
- rate[1] = DESC_RATE2M;
- rate[2] = DESC_RATE5_5M;
- for (i = 1; i < 4; ++i) {
- pwr_by_rate_val[i - 1] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 3;
- break;
-
- case 0xC20:
- case 0xE20:
- case 0x1820:
- case 0x1a20:
- rate[0] = DESC_RATE1M;
- rate[1] = DESC_RATE2M;
- rate[2] = DESC_RATE5_5M;
- rate[3] = DESC_RATE11M;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC24:
- case 0xE24:
- case 0x1824:
- case 0x1a24:
- rate[0] = DESC_RATE6M;
- rate[1] = DESC_RATE9M;
- rate[2] = DESC_RATE12M;
- rate[3] = DESC_RATE18M;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC28:
- case 0xE28:
- case 0x1828:
- case 0x1a28:
- rate[0] = DESC_RATE24M;
- rate[1] = DESC_RATE36M;
- rate[2] = DESC_RATE48M;
- rate[3] = DESC_RATE54M;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC2C:
- case 0xE2C:
- case 0x182C:
- case 0x1a2C:
- rate[0] = DESC_RATEMCS0;
- rate[1] = DESC_RATEMCS1;
- rate[2] = DESC_RATEMCS2;
- rate[3] = DESC_RATEMCS3;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC30:
- case 0xE30:
- case 0x1830:
- case 0x1a30:
- rate[0] = DESC_RATEMCS4;
- rate[1] = DESC_RATEMCS5;
- rate[2] = DESC_RATEMCS6;
- rate[3] = DESC_RATEMCS7;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC34:
- case 0xE34:
- case 0x1834:
- case 0x1a34:
- rate[0] = DESC_RATEMCS8;
- rate[1] = DESC_RATEMCS9;
- rate[2] = DESC_RATEMCS10;
- rate[3] = DESC_RATEMCS11;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC38:
- case 0xE38:
- case 0x1838:
- case 0x1a38:
- rate[0] = DESC_RATEMCS12;
- rate[1] = DESC_RATEMCS13;
- rate[2] = DESC_RATEMCS14;
- rate[3] = DESC_RATEMCS15;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC3C:
- case 0xE3C:
- case 0x183C:
- case 0x1a3C:
- rate[0] = DESC_RATEVHT1SS_MCS0;
- rate[1] = DESC_RATEVHT1SS_MCS1;
- rate[2] = DESC_RATEVHT1SS_MCS2;
- rate[3] = DESC_RATEVHT1SS_MCS3;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC40:
- case 0xE40:
- case 0x1840:
- case 0x1a40:
- rate[0] = DESC_RATEVHT1SS_MCS4;
- rate[1] = DESC_RATEVHT1SS_MCS5;
- rate[2] = DESC_RATEVHT1SS_MCS6;
- rate[3] = DESC_RATEVHT1SS_MCS7;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC44:
- case 0xE44:
- case 0x1844:
- case 0x1a44:
- rate[0] = DESC_RATEVHT1SS_MCS8;
- rate[1] = DESC_RATEVHT1SS_MCS9;
- rate[2] = DESC_RATEVHT2SS_MCS0;
- rate[3] = DESC_RATEVHT2SS_MCS1;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC48:
- case 0xE48:
- case 0x1848:
- case 0x1a48:
- rate[0] = DESC_RATEVHT2SS_MCS2;
- rate[1] = DESC_RATEVHT2SS_MCS3;
- rate[2] = DESC_RATEVHT2SS_MCS4;
- rate[3] = DESC_RATEVHT2SS_MCS5;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- case 0xC4C:
- case 0xE4C:
- case 0x184C:
- case 0x1a4C:
- rate[0] = DESC_RATEVHT2SS_MCS6;
- rate[1] = DESC_RATEVHT2SS_MCS7;
- rate[2] = DESC_RATEVHT2SS_MCS8;
- rate[3] = DESC_RATEVHT2SS_MCS9;
- for (i = 0; i < 4; ++i) {
- pwr_by_rate_val[i] =
- (s8)((((value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((value >> (i * 8)) & 0xF));
- }
- *rate_num = 4;
- break;
-
- default:
- RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
- "Invalid reg_addr 0x%x in %s()\n", reg_addr, __func__);
- break;
- }
-}
-
-void rtl8822be_store_tx_power_by_rate(struct ieee80211_hw *hw, u32 band,
- u32 rfpath, u32 txnum, u32 regaddr,
- u32 bitmask, u32 data)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 i = 0, rates[4] = {0}, rate_num = 0;
- s8 pwr_by_rate_val[4] = {0};
-
- _rtl8822be_get_rate_values_of_tx_power_by_rate(
- hw, regaddr, bitmask, data, rates, pwr_by_rate_val, &rate_num);
-
- if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid Band %d\n",
- band);
- band = BAND_ON_2_4G;
- }
- if (rfpath >= MAX_RF_PATH) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid RfPath %d\n",
- rfpath);
- rfpath = MAX_RF_PATH - 1;
- }
- if (txnum >= MAX_RF_PATH) {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid TxNum %d\n",
- txnum);
- txnum = MAX_RF_PATH - 1;
- }
-
- for (i = 0; i < rate_num; ++i) {
- u8 rate_idx = rates[i];
-
- if (IS_1T_RATE(rates[i]))
- txnum = RF_1TX;
- else if (IS_2T_RATE(rates[i]))
- txnum = RF_2TX;
- else
- WARN_ON(1);
-
- rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_idx] =
- pwr_by_rate_val[i];
-
- RT_TRACE(
- rtlpriv, COMP_INIT, DBG_LOUD,
- "TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][rate_idx %d] = 0x%x\n",
- band, rfpath, txnum, rate_idx,
- rtlphy->tx_power_by_rate_offset[band][rfpath][txnum]
- [rate_idx]);
- }
-}
-
-static void
-_rtl8822be_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
-
- rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
- rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
-
- rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
- rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
-
- rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
- rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
-
- rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8822B;
- rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8822B;
-
- rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8822BE;
- rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8822BE;
-
- rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RA_SIREAD_8822B;
- rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RB_SIREAD_8822B;
-
- rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = RA_PIREAD_8822B;
- rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = RB_PIREAD_8822B;
-}
-
-void rtl8822be_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 txpwr_level;
- long txpwr_dbm;
-
- txpwr_level = rtlphy->cur_cck_txpwridx;
- txpwr_dbm = _rtl8822be_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
- txpwr_level);
- txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
- if (_rtl8822be_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) >
- txpwr_dbm)
- txpwr_dbm = _rtl8822be_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
- txpwr_level);
- txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
- if (_rtl8822be_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
- txpwr_level) > txpwr_dbm)
- txpwr_dbm = _rtl8822be_phy_txpwr_idx_to_dbm(
- hw, WIRELESS_MODE_N_24G, txpwr_level);
- *powerlevel = txpwr_dbm;
-}
-
-static bool _rtl8822be_phy_get_chnl_index(u8 channel, u8 *chnl_index)
-{
- u8 rtl_channel5g[CHANNEL_MAX_NUMBER_5G] = {
- 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
- 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
- 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
- 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
- 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
- 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
- 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
- u8 i = 0;
- bool in_24g = true;
-
- if (channel <= 14) {
- in_24g = true;
- *chnl_index = channel - 1;
- } else {
- in_24g = false;
-
- for (i = 0; i < CHANNEL_MAX_NUMBER_5G; ++i) {
- if (rtl_channel5g[i] == channel) {
- *chnl_index = i;
- return in_24g;
- }
- }
- }
- return in_24g;
-}
-
-static char _rtl8822be_phy_get_world_wide_limit(char *limit_table)
-{
- char min = limit_table[0];
- u8 i = 0;
-
- for (i = 0; i < MAX_REGULATION_NUM; ++i) {
- if (limit_table[i] < min)
- min = limit_table[i];
- }
- return min;
-}
-
-static char _rtl8822be_phy_get_txpower_limit(struct ieee80211_hw *hw, u8 band,
- enum ht_channel_width bandwidth,
- enum radio_path rf_path, u8 rate,
- u8 channel)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- short regulation = -1, rate_section = -1, channel_index = -1;
- char power_limit = MAX_POWER_INDEX;
-
- if (rtlefuse->eeprom_regulatory == 2)
- return MAX_POWER_INDEX;
-
- regulation = TXPWR_LMT_WW;
-
- switch (rate) {
- case DESC_RATE1M:
- case DESC_RATE2M:
- case DESC_RATE5_5M:
- case DESC_RATE11M:
- rate_section = CCK;
- break;
-
- case DESC_RATE6M:
- case DESC_RATE9M:
- case DESC_RATE12M:
- case DESC_RATE18M:
- case DESC_RATE24M:
- case DESC_RATE36M:
- case DESC_RATE48M:
- case DESC_RATE54M:
- rate_section = OFDM;
- break;
-
- case DESC_RATEMCS0:
- case DESC_RATEMCS1:
- case DESC_RATEMCS2:
- case DESC_RATEMCS3:
- case DESC_RATEMCS4:
- case DESC_RATEMCS5:
- case DESC_RATEMCS6:
- case DESC_RATEMCS7:
- rate_section = HT_MCS0_MCS7;
- break;
-
- case DESC_RATEMCS8:
- case DESC_RATEMCS9:
- case DESC_RATEMCS10:
- case DESC_RATEMCS11:
- case DESC_RATEMCS12:
- case DESC_RATEMCS13:
- case DESC_RATEMCS14:
- case DESC_RATEMCS15:
- rate_section = HT_MCS8_MCS15;
- break;
-
- case DESC_RATEVHT1SS_MCS0:
- case DESC_RATEVHT1SS_MCS1:
- case DESC_RATEVHT1SS_MCS2:
- case DESC_RATEVHT1SS_MCS3:
- case DESC_RATEVHT1SS_MCS4:
- case DESC_RATEVHT1SS_MCS5:
- case DESC_RATEVHT1SS_MCS6:
- case DESC_RATEVHT1SS_MCS7:
- case DESC_RATEVHT1SS_MCS8:
- case DESC_RATEVHT1SS_MCS9:
- rate_section = VHT_1SSMCS0_1SSMCS9;
- break;
-
- case DESC_RATEVHT2SS_MCS0:
- case DESC_RATEVHT2SS_MCS1:
- case DESC_RATEVHT2SS_MCS2:
- case DESC_RATEVHT2SS_MCS3:
- case DESC_RATEVHT2SS_MCS4:
- case DESC_RATEVHT2SS_MCS5:
- case DESC_RATEVHT2SS_MCS6:
- case DESC_RATEVHT2SS_MCS7:
- case DESC_RATEVHT2SS_MCS8:
- case DESC_RATEVHT2SS_MCS9:
- rate_section = VHT_2SSMCS0_2SSMCS9;
- break;
-
- default:
- RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Wrong rate 0x%x\n",
- rate);
- break;
- }
-
- if (band == BAND_ON_5G && rate_section == 0)
- RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
- "Wrong rate 0x%x: No CCK in 5G Band\n", rate);
-
- /* workaround for wrong index combination to obtain tx power limit,
- * OFDM only exists in BW 20M
- */
- if (rate_section == 1)
- bandwidth = 0;
-
- /* workaround for wrong index combination to obtain tx power limit,
- * CCK table will only be given in BW 20M
- */
- if (rate_section == 0)
- bandwidth = 0;
-
- /* workaround for wrong indxe combination to obtain tx power limit,
- * HT on 80M will reference to HT on 40M
- */
- if ((rate_section == 2 || rate_section == 3) && band == BAND_ON_5G &&
- bandwidth == 2)
- bandwidth = 1;
-
- if (band == BAND_ON_2_4G)
- channel_index = _rtl8822be_phy_get_chnl_idx_of_txpwr_lmt(
- hw, BAND_ON_2_4G, channel);
- else if (band == BAND_ON_5G)
- channel_index = _rtl8822be_phy_get_chnl_idx_of_txpwr_lmt(
- hw, BAND_ON_5G, channel);
- else if (band == BAND_ON_BOTH)
- ; /* BAND_ON_BOTH don't care temporarily */
-
- if (band >= BANDMAX || regulation == -1 || bandwidth == -1 ||
- rate_section == -1 || channel_index == -1) {
- RT_TRACE(
- rtlpriv, COMP_POWER, DBG_LOUD,
- "Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnl %d]\n",
- band, regulation, bandwidth, rf_path, rate_section,
- channel_index);
- return MAX_POWER_INDEX;
- }
-
- if (band == BAND_ON_2_4G) {
- char limits[10] = {0};
- u8 i = 0;
-
- for (i = 0; i < 4; ++i)
- limits[i] = rtlphy->txpwr_limit_2_4g[i][bandwidth]
- [rate_section]
- [channel_index]
- [rf_path];
-
- power_limit =
- (regulation == TXPWR_LMT_WW) ?
- _rtl8822be_phy_get_world_wide_limit(limits) :
- rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
- [rate_section]
- [channel_index]
- [rf_path];
-
- } else if (band == BAND_ON_5G) {
- char limits[10] = {0};
- u8 i = 0;
-
- for (i = 0; i < MAX_REGULATION_NUM; ++i)
- limits[i] =
- rtlphy->txpwr_limit_5g[i][bandwidth]
- [rate_section]
- [channel_index][rf_path];
-
- power_limit =
- (regulation == TXPWR_LMT_WW) ?
- _rtl8822be_phy_get_world_wide_limit(limits) :
- rtlphy->txpwr_limit_5g[regulation]
- [channel_index]
- [rate_section]
- [channel_index][rf_path];
- } else {
- RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
- "No power limit table of the specified band\n");
- }
-
- return power_limit;
-}
-
-static char
-_rtl8822be_phy_get_txpower_by_rate(struct ieee80211_hw *hw, u8 band, u8 path,
- u8 rate /* enum rtl_desc8822b_rate */)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 tx_num;
- char tx_pwr_diff = 0;
-
- if (band != BAND_ON_2_4G && band != BAND_ON_5G)
- return tx_pwr_diff;
-
- if (path > RF90_PATH_B)
- return tx_pwr_diff;
-
- if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9))
- tx_num = RF_2TX;
- else
- tx_num = RF_1TX;
-
- return (char)(rtlphy->tx_power_by_rate_offset[band][path][tx_num]
- [rate] &
- 0xff);
-}
-
-u8 rtl8822be_get_txpower_index(struct ieee80211_hw *hw, u8 path, u8 rate,
- u8 bandwidth, u8 channel)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
- u8 index = (channel - 1);
- u8 txpower = 0;
- bool in_24g = false;
- char limit;
- char powerdiff_byrate = 0;
-
- if ((rtlhal->current_bandtype == BAND_ON_2_4G &&
- (channel > 14 || channel < 1)) ||
- (rtlhal->current_bandtype == BAND_ON_5G && channel <= 14)) {
- index = 0;
- RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
- "Illegal channel!!\n");
- }
-
- /* 1. base tx power */
- in_24g = _rtl8822be_phy_get_chnl_index(channel, &index);
- if (in_24g) {
- if (RX_HAL_IS_CCK_RATE(rate))
- txpower = rtlefuse->txpwrlevel_cck[path][index];
- else if (rate >= DESC_RATE6M)
- txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
- else
- RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
- "invalid rate\n");
-
- if (rate >= DESC_RATE6M && rate <= DESC_RATE54M &&
- !RX_HAL_IS_CCK_RATE(rate))
- txpower += rtlefuse->txpwr_legacyhtdiff[path][TX_1S];
-
- if (bandwidth == HT_CHANNEL_WIDTH_20) {
- if ((rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT1SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower +=
- rtlefuse->txpwr_ht20diff[path][TX_1S];
- if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT2SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower +=
- rtlefuse->txpwr_ht20diff[path][TX_2S];
- } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
- if ((rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT1SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower +=
- rtlefuse->txpwr_ht40diff[path][TX_1S];
- if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT2SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower +=
- rtlefuse->txpwr_ht40diff[path][TX_2S];
- } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
- if ((rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT1SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower +=
- rtlefuse->txpwr_ht40diff[path][TX_1S];
- if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT2SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower +=
- rtlefuse->txpwr_ht40diff[path][TX_2S];
- }
-
- } else {
- if (rate >= DESC_RATE6M)
- txpower = rtlefuse->txpwr_5g_bw40base[path][index];
- else
- RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_WARNING,
- "INVALID Rate.\n");
-
- if (rate >= DESC_RATE6M && rate <= DESC_RATE54M &&
- !RX_HAL_IS_CCK_RATE(rate))
- txpower += rtlefuse->txpwr_5g_ofdmdiff[path][TX_1S];
-
- if (bandwidth == HT_CHANNEL_WIDTH_20) {
- if ((rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT1SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower += rtlefuse->txpwr_5g_bw20diff[path]
- [TX_1S];
- if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT2SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower += rtlefuse->txpwr_5g_bw20diff[path]
- [TX_2S];
- } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
- if ((rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT1SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower += rtlefuse->txpwr_5g_bw40diff[path]
- [TX_1S];
- if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT2SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower += rtlefuse->txpwr_5g_bw40diff[path]
- [TX_2S];
- } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
- u8 i = 0;
-
- for (i = 0; i < sizeof(rtl_channel5g_80m) / sizeof(u8);
- ++i)
- if (rtl_channel5g_80m[i] == channel)
- index = i;
-
- txpower = rtlefuse->txpwr_5g_bw80base[path][index];
-
- if ((rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT1SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower += rtlefuse->txpwr_5g_bw80diff[path]
- [TX_1S];
- if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
- (rate >= DESC_RATEVHT2SS_MCS0 &&
- rate <= DESC_RATEVHT2SS_MCS9))
- txpower += rtlefuse->txpwr_5g_bw80diff[path]
- [TX_2S];
- }
- }
-
- /* 2. tx power by rate */
- if (rtlefuse->eeprom_regulatory != 2)
- powerdiff_byrate = _rtl8822be_phy_get_txpower_by_rate(
- hw, (u8)(!in_24g), path, rate);
-
- /* 3. tx power limit */
- if (rtlefuse->eeprom_regulatory == 1)
- limit = _rtl8822be_phy_get_txpower_limit(
- hw, (u8)(!in_24g), bandwidth, path, rate,
- channel);
- else
- limit = MAX_POWER_INDEX;
-
- /* ----- */
- powerdiff_byrate = powerdiff_byrate > limit ? limit : powerdiff_byrate;
-
- txpower += powerdiff_byrate;
-
- if (txpower > MAX_POWER_INDEX)
- txpower = MAX_POWER_INDEX;
-
- return txpower;
-}
-
-static void _rtl8822be_phy_set_txpower_index(struct ieee80211_hw *hw,
- u8 power_index, u8 path, u8 rate)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 shift = 0;
- static u32 index;
-
- /*
- * For 8822B, phydm api use 4 bytes txagc value driver must
- * combine every four 1 byte to one 4 byte and send to phydm
- */
- shift = rate & 0x03;
- index |= ((u32)power_index << (shift * 8));
-
- if (shift == 3) {
- rate = rate - 3;
-
- if (!rtlpriv->phydm.ops->phydm_write_txagc(rtlpriv, index, path,
- rate)) {
- RT_TRACE(rtlpriv, COMP_TXAGC, DBG_LOUD,
- "%s(index:%d, rfpath:%d, rate:0x%02x) fail\n",
- __func__, index, path, rate);
-
- WARN_ON(1);
- }
- index = 0;
- }
-}
-
-static void _rtl8822be_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
- u8 *array, u8 path,
- u8 channel, u8 size)
-{
- struct rtl_phy *rtlphy = &(rtl_priv(hw)->phy);
- u8 i;
- u8 power_index;
-
- for (i = 0; i < size; i++) {
- power_index = rtl8822be_get_txpower_index(
- hw, path, array[i], rtlphy->current_chan_bw, channel);
- _rtl8822be_phy_set_txpower_index(hw, power_index, path,
- array[i]);
- }
-}
-
-void rtl8822be_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
- u8 channel, u8 path)
-{
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
-
- /*
- * Below order is *VERY* important!
- * Because _rtl8822be_phy_set_txpower_index() do actually writing
- * every four power values.
- */
- if (rtlhal->current_bandtype == BAND_ON_2_4G)
- _rtl8822be_phy_set_txpower_level_by_path(
- hw, cck_rates, path, channel, sizes_of_cck_retes);
- _rtl8822be_phy_set_txpower_level_by_path(hw, ofdm_rates, path, channel,
- sizes_of_ofdm_retes);
- _rtl8822be_phy_set_txpower_level_by_path(hw, ht_rates_1t, path, channel,
- sizes_of_ht_retes_1t);
- _rtl8822be_phy_set_txpower_level_by_path(hw, ht_rates_2t, path, channel,
- sizes_of_ht_retes_2t);
- _rtl8822be_phy_set_txpower_level_by_path(hw, vht_rates_1t, path,
- channel, sizes_of_vht_retes);
- _rtl8822be_phy_set_txpower_level_by_path(hw, vht_rates_2t, path,
- channel, sizes_of_vht_retes);
-}
-
-void rtl8822be_phy_set_tx_power_index_by_rs(struct ieee80211_hw *hw, u8 channel,
- u8 path, enum rate_section rs)
-{
- struct {
- u8 *array;
- u8 size;
- } rs_ref[MAX_RATE_SECTION] = {
- {cck_rates, sizes_of_cck_retes},
- {ofdm_rates, sizes_of_ofdm_retes},
- {ht_rates_1t, sizes_of_ht_retes_1t},
- {ht_rates_2t, sizes_of_ht_retes_2t},
- {vht_rates_1t, sizes_of_vht_retes},
- {vht_rates_2t, sizes_of_vht_retes},
- };
-
- if (rs >= MAX_RATE_SECTION)
- return;
-
- _rtl8822be_phy_set_txpower_level_by_path(hw, rs_ref[rs].array, path,
- channel, rs_ref[rs].size);
-}
-
-void rtl8822be_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 path = 0;
-
- for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; ++path)
- rtl8822be_phy_set_txpower_level_by_path(hw, channel, path);
-}
-
-static long _rtl8822be_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
- enum wireless_mode wirelessmode,
- u8 txpwridx)
-{
- long offset;
-
- switch (wirelessmode) {
- case WIRELESS_MODE_B:
- offset = -7;
- break;
- case WIRELESS_MODE_G:
- case WIRELESS_MODE_N_24G:
- offset = -8;
- break;
- default:
- offset = -8;
- break;
- }
- return txpwridx / 2 + offset;
-}
-
-void rtl8822be_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- enum io_type iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
-
- if (!is_hal_stop(rtlhal)) {
- switch (operation) {
- case SCAN_OPT_BACKUP_BAND0:
- iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
- (u8 *)&iotype);
-
- break;
- case SCAN_OPT_BACKUP_BAND1:
- iotype = IO_CMD_PAUSE_BAND1_DM_BY_SCAN;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
- (u8 *)&iotype);
-
- break;
- case SCAN_OPT_RESTORE:
- iotype = IO_CMD_RESUME_DM_BY_SCAN;
- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
- (u8 *)&iotype);
- break;
- default:
- pr_err("Unknown Scan Backup operation.\n");
- break;
- }
- }
-}
-
-static u8 _rtl8822be_phy_get_pri_ch_id(struct rtl_priv *rtlpriv)
-{
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- u8 pri_ch_idx = 0;
-
- if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
- /* primary channel is at lower subband of 80MHz & 40MHz */
- if (mac->cur_40_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER &&
- mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER) {
- pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
- /* primary channel is at
- * lower subband of 80MHz & upper subband of 40MHz
- */
- } else if ((mac->cur_40_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER) &&
- (mac->cur_80_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_LOWER)) {
- pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
- /* primary channel is at
- * upper subband of 80MHz & lower subband of 40MHz
- */
- } else if ((mac->cur_40_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_LOWER) &&
- (mac->cur_80_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER)) {
- pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
- /* primary channel is at
- * upper subband of 80MHz & upper subband of 40MHz
- */
- } else if ((mac->cur_40_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER) &&
- (mac->cur_80_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER)) {
- pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
- } else {
- if (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER)
- pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;
- else if (mac->cur_80_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER)
- pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;
- }
- } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
- /* primary channel is at upper subband of 40MHz */
- if (mac->cur_40_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER)
- pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
- /* primary channel is at lower subband of 40MHz */
- else if (mac->cur_40_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER)
- pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
- else
- ;
- }
-
- return pri_ch_idx;
-}
-
-void rtl8822be_phy_set_bw_mode(struct ieee80211_hw *hw,
- enum nl80211_channel_type ch_type)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- u8 tmp_bw = rtlphy->current_chan_bw;
-
- if (rtlphy->set_bwmode_inprogress)
- return;
- rtlphy->set_bwmode_inprogress = true;
- if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
- /* get primary channel index */
- u8 pri_ch_idx = _rtl8822be_phy_get_pri_ch_id(rtlpriv);
-
- /* 3.1 set MAC register */
- rtlpriv->halmac.ops->halmac_set_bandwidth(
- rtlpriv, rtlphy->current_channel, pri_ch_idx,
- rtlphy->current_chan_bw);
-
- /* 3.2 set BB/RF registet */
- rtlpriv->phydm.ops->phydm_switch_bandwidth(
- rtlpriv, pri_ch_idx, rtlphy->current_chan_bw);
-
- if (!mac->act_scanning)
- rtlpriv->phydm.ops->phydm_iq_calibrate(rtlpriv);
-
- rtlphy->set_bwmode_inprogress = false;
- } else {
- RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
- "FALSE driver sleep or unload\n");
- rtlphy->set_bwmode_inprogress = false;
- rtlphy->current_chan_bw = tmp_bw;
- }
-}
-
-u8 rtl8822be_phy_sw_chnl(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- u32 timeout = 1000, timecount = 0;
- u8 channel = rtlphy->current_channel;
-
- if (rtlphy->sw_chnl_inprogress)
- return 0;
- if (rtlphy->set_bwmode_inprogress)
- return 0;
-
- if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
- RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
- "sw_chnl_inprogress false driver sleep or unload\n");
- return 0;
- }
- while (rtlphy->lck_inprogress && timecount < timeout) {
- mdelay(50);
- timecount += 50;
- }
-
- if (rtlphy->current_channel > 14)
- rtlhal->current_bandtype = BAND_ON_5G;
- else if (rtlphy->current_channel <= 14)
- rtlhal->current_bandtype = BAND_ON_2_4G;
-
- if (rtlpriv->cfg->ops->get_btc_status())
- rtlpriv->btcoexist.btc_ops->btc_switch_band_notify(
- rtlpriv, rtlhal->current_bandtype, mac->act_scanning);
- else
- rtlpriv->btcoexist.btc_ops->btc_switch_band_notify_wifi_only(
- rtlpriv, rtlhal->current_bandtype, mac->act_scanning);
-
- rtlpriv->phydm.ops->phydm_switch_band(rtlpriv, rtlphy->current_channel);
-
- rtlphy->sw_chnl_inprogress = true;
- if (channel == 0)
- channel = 1;
-
- RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
- "switch to channel%d, band type is %d\n",
- rtlphy->current_channel, rtlhal->current_bandtype);
-
- rtlpriv->phydm.ops->phydm_switch_channel(rtlpriv,
- rtlphy->current_channel);
-
- rtlpriv->phydm.ops->phydm_clear_txpowertracking_state(rtlpriv);
-
- rtl8822be_phy_set_txpower_level(hw, rtlphy->current_channel);
-
- RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
- rtlphy->sw_chnl_inprogress = false;
- return 1;
-}
-
-bool rtl8822be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- bool postprocessing = false;
-
- RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
- "-->IO Cmd(%#x), set_io_inprogress(%d)\n", iotype,
- rtlphy->set_io_inprogress);
- do {
- switch (iotype) {
- case IO_CMD_RESUME_DM_BY_SCAN:
- RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
- "[IO CMD] Resume DM after scan.\n");
- postprocessing = true;
- break;
- case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
- case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
- RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
- "[IO CMD] Pause DM before scan.\n");
- postprocessing = true;
- break;
- default:
- pr_err("switch case not process\n");
- break;
- }
- } while (false);
- if (postprocessing && !rtlphy->set_io_inprogress) {
- rtlphy->set_io_inprogress = true;
- rtlphy->current_io_type = iotype;
- } else {
- return false;
- }
- rtl8822be_phy_set_io(hw);
- RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
- return true;
-}
-
-static void rtl8822be_phy_set_io(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
-
- RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
- "--->Cmd(%#x), set_io_inprogress(%d)\n",
- rtlphy->current_io_type, rtlphy->set_io_inprogress);
- switch (rtlphy->current_io_type) {
- case IO_CMD_RESUME_DM_BY_SCAN:
- break;
- case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
- break;
- case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
- break;
- default:
- pr_err("switch case not process\n");
- break;
- }
- rtlphy->set_io_inprogress = false;
- RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "(%#x)\n",
- rtlphy->current_io_type);
-}
-
-static void rtl8822be_phy_set_rf_on(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtl_write_byte(rtlpriv, REG_SPS0_CTRL_8822B, 0x2b);
- rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN_8822B, 0xE3);
- rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN_8822B, 0xE2);
- rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN_8822B, 0xE3);
- rtl_write_byte(rtlpriv, REG_TXPAUSE_8822B, 0x00);
-}
-
-static bool _rtl8822be_phy_set_rf_power_state(struct ieee80211_hw *hw,
- enum rf_pwrstate rfpwr_state)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
- bool bresult = true;
- u8 i, queue_id;
- struct rtl8192_tx_ring *ring = NULL;
-
- switch (rfpwr_state) {
- case ERFON:
- if (ppsc->rfpwr_state == ERFOFF &&
- RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
- bool rtstatus = false;
- u32 initialize_count = 0;
-
- do {
- initialize_count++;
- RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
- "IPS Set eRf nic enable\n");
- rtstatus = rtl_ps_enable_nic(hw);
- } while ((!rtstatus) && (initialize_count < 10));
- RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
- } else {
- RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
- "Set ERFON slept:%d ms\n",
- jiffies_to_msecs(jiffies -
- ppsc->last_sleep_jiffies));
- ppsc->last_awake_jiffies = jiffies;
- rtl8822be_phy_set_rf_on(hw);
- }
- if (mac->link_state == MAC80211_LINKED)
- rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
- else
- rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
- break;
- case ERFOFF:
- for (queue_id = 0, i = 0;
- queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
- ring = &pcipriv->dev.tx_ring[queue_id];
- if (queue_id == BEACON_QUEUE ||
- skb_queue_len(&ring->queue) == 0) {
- queue_id++;
- continue;
- } else {
- RT_TRACE(
- rtlpriv, COMP_ERR, DBG_WARNING,
- "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
- (i + 1), queue_id,
- skb_queue_len(&ring->queue));
-
- udelay(10);
- i++;
- }
- if (i >= MAX_DOZE_WAITING_TIMES_9x) {
- RT_TRACE(
- rtlpriv, COMP_ERR, DBG_WARNING,
- "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
- MAX_DOZE_WAITING_TIMES_9x, queue_id,
- skb_queue_len(&ring->queue));
- break;
- }
- }
-
- if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
- RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
- "IPS Set eRf nic disable\n");
- rtl_ps_disable_nic(hw);
- RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
- } else {
- if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
- rtlpriv->cfg->ops->led_control(hw,
- LED_CTL_NO_LINK);
- } else {
- rtlpriv->cfg->ops->led_control(
- hw, LED_CTL_POWER_OFF);
- }
- }
- break;
- default:
- pr_err("switch case not process\n");
- bresult = false;
- break;
- }
- if (bresult)
- ppsc->rfpwr_state = rfpwr_state;
- return bresult;
-}
-
-bool rtl8822be_phy_set_rf_power_state(struct ieee80211_hw *hw,
- enum rf_pwrstate rfpwr_state)
-{
- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
-
- bool bresult = false;
-
- if (rfpwr_state == ppsc->rfpwr_state)
- return bresult;
- return _rtl8822be_phy_set_rf_power_state(hw, rfpwr_state);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL8822BE_PHY_H__
-#define __RTL8822BE_PHY_H__
-
-/* It must always set to 4, otherwise read
- * efuse table sequence will be wrong.
- */
-#define MAX_TX_COUNT 4
-#define TX_1S 0
-#define TX_2S 1
-#define TX_3S 2
-#define TX_4S 3
-
-#define MAX_POWER_INDEX 0x3F
-
-#define MAX_PRECMD_CNT 16
-#define MAX_RFDEPENDCMD_CNT 16
-#define MAX_POSTCMD_CNT 16
-
-#define MAX_DOZE_WAITING_TIMES_9x 64
-
-#define RT_CANNOT_IO(hw) false
-#define HIGHPOWER_RADIOA_ARRAYLEN 22
-
-#define IQK_ADDA_REG_NUM 16
-#define IQK_BB_REG_NUM 9
-#define MAX_TOLERANCE 5
-#define IQK_DELAY_TIME 10
-#define index_mapping_NUM 15
-
-#define APK_BB_REG_NUM 5
-#define APK_AFE_REG_NUM 16
-#define APK_CURVE_REG_NUM 4
-#define PATH_NUM 2
-
-#define LOOP_LIMIT 5
-#define MAX_STALL_TIME 50
-#define ANTENNA_DIVERSITY_VALUE 0x80
-#define MAX_TXPWR_IDX_NMODE_92S 63
-#define RESET_CNT_LIMIT 3
-
-#define IQK_ADDA_REG_NUM 16
-#define IQK_MAC_REG_NUM 4
-
-#define RF6052_MAX_PATH 2
-
-#define CT_OFFSET_MAC_ADDR 0X16
-
-#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
-#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
-#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
-#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
-#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
-
-#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
-#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
-
-#define CT_OFFSET_CHANNEL_PLAH 0x75
-#define CT_OFFSET_THERMAL_METER 0x78
-#define CT_OFFSET_RF_OPTION 0x79
-#define CT_OFFSET_VERSION 0x7E
-#define CT_OFFSET_CUSTOMER_ID 0x7F
-
-#define RTL8822BE_MAX_PATH_NUM 2
-
-#define TARGET_CHNL_NUM_2G_5G_8822B 59
-
-u32 rtl8822be_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
- u32 bitmask);
-void rtl8822be_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
- u32 data);
-u32 rtl8822be_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
- u32 regaddr, u32 bitmask);
-void rtl8822be_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
- u32 regaddr, u32 bitmask, u32 data);
-bool rtl8822be_phy_bb_config(struct ieee80211_hw *hw);
-bool rtl8822be_phy_rf_config(struct ieee80211_hw *hw);
-bool rtl8822be_halmac_cb_init_mac_register(struct rtl_priv *rtlpriv);
-bool rtl8822be_halmac_cb_init_bb_rf_register(struct rtl_priv *rtlpriv);
-void rtl8822be_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel);
-void rtl8822be_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
-void rtl8822be_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation);
-void rtl8822be_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
-void rtl8822be_phy_set_bw_mode(struct ieee80211_hw *hw,
- enum nl80211_channel_type ch_type);
-u8 rtl8822be_phy_sw_chnl(struct ieee80211_hw *hw);
-void rtl8822be_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
-void rtl8822be_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
-void rtl8822be_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
-void rtl8822be_phy_lc_calibrate(struct ieee80211_hw *hw);
-void rtl8822be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
-bool rtl8822be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
- enum radio_path rfpath);
-bool rtl8822be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
- enum radio_path rfpath);
-bool rtl8822be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
-bool rtl8822be_phy_set_rf_power_state(struct ieee80211_hw *hw,
- enum rf_pwrstate rfpwr_state);
-void rtl8822be_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
- u8 channel, u8 path);
-void rtl8822be_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
- u8 thermal_value, u8 threshold);
-void rtl8822be_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
- u8 thermal_value, u8 threshold);
-void rtl8822be_reset_iqk_result(struct ieee80211_hw *hw);
-
-u8 rtl8822be_get_txpower_index(struct ieee80211_hw *hw, u8 path, u8 rate,
- u8 bandwidth, u8 channel);
-void rtl8822be_phy_set_tx_power_index_by_rs(struct ieee80211_hw *hw, u8 channel,
- u8 path, enum rate_section rs);
-void rtl8822be_store_tx_power_by_rate(struct ieee80211_hw *hw, u32 band,
- u32 rfpath, u32 txnum, u32 regaddr,
- u32 bitmask, u32 data);
-void rtl8822be_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregulation,
- u8 *pband, u8 *pbandwidth,
- u8 *prate_section, u8 *prf_path,
- u8 *pchannel, u8 *ppower_limit);
-bool rtl8822be_load_txpower_by_rate(struct ieee80211_hw *hw);
-bool rtl8822be_load_txpower_limit(struct ieee80211_hw *hw);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL8822B_REG_H__
-#define __RTL8822B_REG_H__
-
-#include "../halmac/halmac_reg_8822b.h"
-#include "../halmac/halmac_bit_8822b.h"
-
-#define TXPKT_BUF_SELECT 0x69
-#define RXPKT_BUF_SELECT 0xA5
-#define DISABLE_TRXPKT_BUF_ACCESS 0x0
-
-/* Page 0 */
-#define REG_LEDCFG2_8822B 0x004E /* need review */
-#define REG_SPS0_CTRL_8822B 0x0011 /* need review: swlps */
-
-#define REG_EFUSE_ACCESS_8822B (REG_PMC_DBG_CTRL2_8822B + 3) /*0x00CF*/
-#define REG_AFE_XTAL_CTRL_8822B REG_AFE_CTRL1_8822B
-#define REG_AFE_PLL_CTRL_8822B REG_AFE_CTRL2_8822B
-
-/* Page 1 */
-
-#define MSR (REG_CR_8822B + 2)
-
-/* for MSR 0x102 */
-#define MSR_NOLINK 0x00
-#define MSR_ADHOC 0x01
-#define MSR_INFRA 0x02
-#define MSR_AP 0x03
-
-/*-----------------------------------------------------
- *
- * 0x0200h ~ 0x027Fh TXDMA Configuration
- *
- *-----------------------------------------------------
- */
-
-/*-----------------------------------------------------
- *
- * 0x0280h ~ 0x02FFh RXDMA Configuration
- *
- *-----------------------------------------------------
- */
-#define REG_RXDMA_CONTROL_8822B (REG_RXPKT_NUM_8822B + 2) /* 0x0286 */
-
-/*-----------------------------------------------------
- *
- * 0x0300h ~ 0x03FFh PCIe
- *
- *-----------------------------------------------------
- */
-
-/* REG_HIMR3_8822B */
-#define IMR_H2CDOK BIT_SETH2CDOK_MASK_8822B
-
-/* spec version 11
- *-----------------------------------------------------
- *
- * 0x0400h ~ 0x047Fh Protocol Configuration
- *
- *-----------------------------------------------------
- */
-
-#define REG_MAX_AGGR_NUM_8822B (REG_PROT_MODE_CTRL_8822B + 2) /*0x04CA*/
-
-/* for RRSR 0x440 */
-#define RRSR_RSC_OFFSET 21
-#define RRSR_SHORT_OFFSET 23
-#define RRSR_RSC_BW_40M 0x600000
-#define RRSR_RSC_UPSUBCHNL 0x400000
-#define RRSR_RSC_LOWSUBCHNL 0x200000
-#define RRSR_1M BIT(0)
-#define RRSR_2M BIT(1)
-#define RRSR_5_5M BIT(2)
-#define RRSR_11M BIT(3)
-#define RRSR_6M BIT(4)
-#define RRSR_9M BIT(5)
-#define RRSR_12M BIT(6)
-#define RRSR_18M BIT(7)
-#define RRSR_24M BIT(8)
-#define RRSR_36M BIT(9)
-#define RRSR_48M BIT(10)
-#define RRSR_54M BIT(11)
-#define RRSR_MCS0 BIT(12)
-#define RRSR_MCS1 BIT(13)
-#define RRSR_MCS2 BIT(14)
-#define RRSR_MCS3 BIT(15)
-#define RRSR_MCS4 BIT(16)
-#define RRSR_MCS5 BIT(17)
-#define RRSR_MCS6 BIT(18)
-#define RRSR_MCS7 BIT(19)
-
-#define RRSR_ALL_CCK (RRSR_1M | RRSR_2M | RRSR_5_5M | RRSR_11M)
-#define RRSR_ALL_OFDM_AG \
- (RRSR_6M | RRSR_9M | RRSR_12M | RRSR_18M | RRSR_24M | RRSR_36M | \
- RRSR_48M | RRSR_54M)
-
-/*-----------------------------------------------------
- *
- * 0x0500h ~ 0x05FFh EDCA Configuration
- *
- *-----------------------------------------------------
- */
-
-#define REG_SIFS_TRX_8822B (REG_SIFS_8822B + 2) /*0x0516*/
-
-/*-----------------------------------------------------
- *
- * 0x0600h ~ 0x07FFh WMAC Configuration
- *
- *-----------------------------------------------------
- */
-
-#define RATR_1M 0x00000001
-#define RATR_2M 0x00000002
-#define RATR_55M 0x00000004
-#define RATR_11M 0x00000008
-#define RATR_6M 0x00000010
-#define RATR_9M 0x00000020
-#define RATR_12M 0x00000040
-#define RATR_18M 0x00000080
-#define RATR_24M 0x00000100
-#define RATR_36M 0x00000200
-#define RATR_48M 0x00000400
-#define RATR_54M 0x00000800
-#define RATR_MCS0 0x00001000
-#define RATR_MCS1 0x00002000
-#define RATR_MCS2 0x00004000
-#define RATR_MCS3 0x00008000
-#define RATR_MCS4 0x00010000
-#define RATR_MCS5 0x00020000
-#define RATR_MCS6 0x00040000
-#define RATR_MCS7 0x00080000
-#define RATR_MCS8 0x00100000
-#define RATR_MCS9 0x00200000
-#define RATR_MCS10 0x00400000
-#define RATR_MCS11 0x00800000
-#define RATR_MCS12 0x01000000
-#define RATR_MCS13 0x02000000
-#define RATR_MCS14 0x04000000
-#define RATR_MCS15 0x08000000
-
-#define RATE_1M BIT(0)
-#define RATE_2M BIT(1)
-#define RATE_5_5M BIT(2)
-#define RATE_11M BIT(3)
-#define RATE_6M BIT(4)
-#define RATE_9M BIT(5)
-#define RATE_12M BIT(6)
-#define RATE_18M BIT(7)
-#define RATE_24M BIT(8)
-#define RATE_36M BIT(9)
-#define RATE_48M BIT(10)
-#define RATE_54M BIT(11)
-#define RATE_MCS0 BIT(12)
-#define RATE_MCS1 BIT(13)
-#define RATE_MCS2 BIT(14)
-#define RATE_MCS3 BIT(15)
-#define RATE_MCS4 BIT(16)
-#define RATE_MCS5 BIT(17)
-#define RATE_MCS6 BIT(18)
-#define RATE_MCS7 BIT(19)
-#define RATE_MCS8 BIT(20)
-#define RATE_MCS9 BIT(21)
-#define RATE_MCS10 BIT(22)
-#define RATE_MCS11 BIT(23)
-#define RATE_MCS12 BIT(24)
-#define RATE_MCS13 BIT(25)
-#define RATE_MCS14 BIT(26)
-#define RATE_MCS15 BIT(27)
-
-/* CAM definition */
-
-#define CAM_NONE 0x0
-#define CAM_WEP40 0x01
-#define CAM_TKIP 0x02
-#define CAM_AES 0x04
-#define CAM_WEP104 0x05
-
-/*#define TOTAL_CAM_ENTRY 64*/
-/*#define HALF_CAM_ENTRY 32*/
-
-#define CAM_WRITE BIT(16)
-#define CAM_READ 0x00000000
-#define CAM_POLLINIG BIT(31)
-
-/*********************************************
- * 8822BE IMR/ISR bits
- *********************************************
- */
-#define IMR_DISABLED 0x0
-/* IMR DW0(0x0060-0063) Bit 0-31 */
-#define IMR_TIMER2 BIT(31)
-#define IMR_TIMER1 BIT(30)
-#define IMR_PSTIMEOUT BIT(29)
-#define IMR_GTINT4 BIT(28)
-#define IMR_GTINT3 BIT(27)
-#define IMR_TBDER BIT(26)
-#define IMR_TBDOK BIT(25)
-#define IMR_TSF_BIT32_TOGGLE BIT(24)
-#define IMR_BCNDMAINT0 BIT(20)
-#define IMR_BCNDOK0 BIT(16)
-#define IMR_HSISR_IND_ON_INT BIT(15)
-#define IMR_BCNDMAINT_E BIT(14)
-#define IMR_ATIMEND BIT(12)
-#define IMR_HISR1_IND_INT BIT(11)
-#define IMR_C2HCMD BIT(10)
-#define IMR_CPWM2 BIT(9)
-#define IMR_CPWM BIT(8)
-#define IMR_HIGHDOK BIT(7)
-#define IMR_MGNTDOK BIT(6)
-#define IMR_BKDOK BIT(5)
-#define IMR_BEDOK BIT(4)
-#define IMR_VIDOK BIT(3)
-#define IMR_VODOK BIT(2)
-#define IMR_RDU BIT(1)
-#define IMR_ROK BIT(0)
-
-/* IMR DW1(0x00B4-00B7) Bit 0-31 */
-#define IMR_TXFIFO_TH_INT_8822B BIT_TXFIFO_TH_INT_8822B
-#define IMR_BTON_STS_UPDATE_MASK_8822B BIT_BTON_STS_UPDATE_MASK_8822B
-#define IMR_MCUERR BIT(28)
-#define IMR_BCNDMAINT7 BIT(27)
-#define IMR_BCNDMAINT6 BIT(26)
-#define IMR_BCNDMAINT5 BIT(25)
-#define IMR_BCNDMAINT4 BIT(24)
-#define IMR_BCNDMAINT3 BIT(23)
-#define IMR_BCNDMAINT2 BIT(22)
-#define IMR_BCNDMAINT1 BIT(21)
-#define IMR_BCNDOK7 BIT(20)
-#define IMR_BCNDOK6 BIT(19)
-#define IMR_BCNDOK5 BIT(18)
-#define IMR_BCNDOK4 BIT(17)
-#define IMR_BCNDOK3 BIT(16)
-#define IMR_BCNDOK2 BIT(15)
-#define IMR_BCNDOK1 BIT(14)
-#define IMR_ATIMEND_E BIT(13)
-#define IMR_ATIMEND BIT(12)
-#define IMR_TXERR BIT(11)
-#define IMR_RXERR BIT(10)
-#define IMR_TXFOVW BIT(9)
-#define IMR_RXFOVW BIT(8)
-#define IMR_CPU_MGQ_TXDONE_MSK_8822B BIT_CPU_MGQ_TXDONE_MSK_8822B
-#define IMR_PS_TIMER_C_MSK_8822B BIT_PS_TIMER_C_MSK_8822B
-#define IMR_PS_TIMER_B_MSK_8822B BIT_PS_TIMER_B_MSK_8822B
-#define IMR_PS_TIMER_A_MSK_8822B BIT_PS_TIMER_A_MSK_8822B
-#define IMR_CPUMGQ_TX_TIMER_MSK_8822B BIT_CPUMGQ_TX_TIMER_MSK_8822B
-
-/*********************************************
- * 8822BE EFUSE definition
- *********************************************
- */
-#define HWSET_MAX_SIZE 1024
-#define EFUSE_MAX_SECTION 64
-#define EFUSE_REAL_CONTENT_LEN 1024
-#define EFUSE_OOB_PROTECT_BYTES 18
-
-#define EEPROM_DEFAULT_THERMALMETER 0x12
-
-#define RTL8822B_EEPROM_ID 0x8129
-
-#define PPG_BB_GAIN_2G_TXA_OFFSET_8822B 0xEE
-#define PPG_THERMAL_OFFSET_8822B 0xEF
-
-#define EEPROM_TX_PWR_INX_8822B 0x10
-
-#define EEPROM_CHANNEL_PLAN_8822B 0xB8
-#define EEPROM_XTAL_8822B 0xB9
-#define EEPROM_THERMAL_METER_8822B 0xBA
-#define EEPROM_IQK_LCK_8822B 0xBB
-#define EEPROM_2G_5G_PA_TYPE_8822B 0xBC
-/* PATH A & PATH B */
-#define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBD
-/* PATH C & PATH D */
-#define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822B 0xBE
-/* PATH A & PATH B */
-#define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBF
-/* PATH C & PATH D */
-#define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822B 0xC0
-
-#define EEPROM_RF_BOARD_OPTION_8822B 0xC1
-#define EEPROM_FEATURE_OPTION_8822B 0xC2
-#define EEPROM_RF_BT_SETTING_8822B 0xC3
-#define EEPROM_VERSION_8822B 0xC4
-#define EEPROM_CUSTOM_ID_8822B 0xC5
-#define EEPROM_TX_BBSWING_2G_8822B 0xC6
-#define EEPROM_TX_PWR_CALIBRATE_RATE_8822B 0xC8
-#define EEPROM_RF_ANTENNA_OPT_8822B 0xC9
-#define EEPROM_RFE_OPTION_8822B 0xCA
-#define EEPROM_COUNTRY_CODE_8822B 0xCB
-
-#define EEPROM_VID 0xD6
-#define EEPROM_DID 0xD8
-#define EEPROM_SVID 0xDA
-#define EEPROM_SMID 0xDC
-
-/* RTL8822BU */
-#define EEPROM_MAC_ADDR_8822BU 0x107
-#define EEPROM_VID_8822BU 0x100
-#define EEPROM_PID_8822BU 0x102
-#define EEPROM_USB_OPTIONAL_FUNCTION0_8822BU 0x104
-#define EEPROM_USB_MODE_8822BU 0x06
-
-/* RTL8822BS */
-#define EEPROM_MAC_ADDR_8822BS 0x11A
-
-/* RTL8822BE */
-#define EEPROM_MAC_ADDR_8822BE 0xD0
-
-/* ------------------------- */
-
-#define STOPBECON BIT(6)
-#define STOPHIGHT BIT(5)
-#define STOPMGT BIT(4)
-#define STOPVO BIT(3)
-#define STOPVI BIT(2)
-#define STOPBE BIT(1)
-#define STOPBK BIT(0)
-
-#define RCR_APPFCS BIT(31)
-#define RCR_APP_MIC BIT(30)
-#define RCR_APP_ICV BIT(29)
-#define RCR_APP_PHYST_RXFF BIT(28)
-#define RCR_APP_BA_SSN BIT(27)
-#define RCR_VHT_DACK BIT(26)
-#define RCR_ENMBID BIT(24)
-#define RCR_LSIGEN BIT(23)
-#define RCR_MFBEN BIT(22)
-#define RCR_HTC_LOC_CTRL BIT(14)
-#define RCR_AMF BIT(13)
-#define RCR_ACF BIT(12)
-#define RCR_ADF BIT(11)
-#define RCR_AICV BIT(9)
-#define RCR_ACRC32 BIT(8)
-#define RCR_CBSSID_BCN BIT(7)
-#define RCR_CBSSID_DATA BIT(6)
-#define RCR_CBSSID RCR_CBSSID_DATA
-#define RCR_APWRMGT BIT(5)
-#define RCR_ADD3 BIT(4)
-#define RCR_AB BIT(3)
-#define RCR_AM BIT(2)
-#define RCR_APM BIT(1)
-#define RCR_AAP BIT(0)
-#define RCR_MXDMA_OFFSET 8
-#define RCR_FIFO_OFFSET 13
-
-#define RSV_CTRL 0x001C
-#define RD_CTRL 0x0524
-
-#define REG_USB_INFO_8822B 0xFE17
-#define REG_USB_SPECIAL_OPTION_8822B 0xFE55
-#define REG_USB_DMA_AGG_TO_8822B 0xFE5B
-#define REG_USB_AGG_TO_8822B 0xFE5C
-#define REG_USB_AGG_TH_8822B 0xFE5D
-
-#define REG_USB_VID_8822B 0xFE60
-#define REG_USB_PID_8822B 0xFE62
-#define REG_USB_OPTIONAL_8822B 0xFE64
-#define REG_USB_CHIRP_K_8822B 0xFE65
-#define REG_USB_PHY_8822B 0xFE66
-#define REG_USB_MAC_ADDR_8822B 0xFE70
-#define REG_USB_HRPWM_8822B 0xFE58
-#define REG_USB_HCPWM_8822B 0xFE57
-
-#define SW18_FPWM BIT(3)
-
-#define ISO_MD2PP BIT(0)
-#define ISO_UA2USB BIT(1)
-#define ISO_UD2CORE BIT(2)
-#define ISO_PA2PCIE BIT(3)
-#define ISO_PD2CORE BIT(4)
-#define ISO_IP2MAC BIT(5)
-#define ISO_DIOP BIT(6)
-#define ISO_DIOE BIT(7)
-#define ISO_EB2CORE BIT(8)
-#define ISO_DIOR BIT(9)
-
-#define PWC_EV25V BIT(14)
-#define PWC_EV12V BIT(15)
-
-#define FEN_BBRSTB BIT(0)
-#define FEN_BB_GLB_RSTN BIT(1)
-#define FEN_USBA BIT(2)
-#define FEN_UPLL BIT(3)
-#define FEN_USBD BIT(4)
-#define FEN_DIO_PCIE BIT(5)
-#define FEN_PCIEA BIT(6)
-#define FEN_PPLL BIT(7)
-#define FEN_PCIED BIT(8)
-#define FEN_DIOE BIT(9)
-#define FEN_CPUEN BIT(10)
-#define FEN_DCORE BIT(11)
-#define FEN_ELDR BIT(12)
-#define FEN_DIO_RF BIT(13)
-#define FEN_HWPDN BIT(14)
-#define FEN_MREGEN BIT(15)
-
-#define PFM_LDALL BIT(0)
-#define PFM_ALDN BIT(1)
-#define PFM_LDKP BIT(2)
-#define PFM_WOWL BIT(3)
-#define EN_PDN BIT(4)
-#define PDN_PL BIT(5)
-#define APFM_ONMAC BIT(8)
-#define APFM_OFF BIT(9)
-#define APFM_RSM BIT(10)
-#define AFSM_HSUS BIT(11)
-#define AFSM_PCIE BIT(12)
-#define APDM_MAC BIT(13)
-#define APDM_HOST BIT(14)
-#define APDM_HPDN BIT(15)
-#define RDY_MACON BIT(16)
-#define SUS_HOST BIT(17)
-#define ROP_ALD BIT(20)
-#define ROP_PWR BIT(21)
-#define ROP_SPS BIT(22)
-#define SOP_MRST BIT(25)
-#define SOP_FUSE BIT(26)
-#define SOP_ABG BIT(27)
-#define SOP_AMB BIT(28)
-#define SOP_RCK BIT(29)
-#define SOP_A8M BIT(30)
-#define XOP_BTCK BIT(31)
-
-#define ANAD16V_EN BIT(0)
-#define ANA8M BIT(1)
-#define MACSLP BIT(4)
-#define LOADER_CLK_EN BIT(5)
-#define _80M_SSC_DIS BIT(7)
-#define _80M_SSC_EN_HO BIT(8)
-#define PHY_SSC_RSTB BIT(9)
-#define SEC_CLK_EN BIT(10)
-#define MAC_CLK_EN BIT(11)
-#define SYS_CLK_EN BIT(12)
-#define RING_CLK_EN BIT(13)
-
-#define BOOT_FROM_EEPROM BIT(4)
-#define EEPROM_EN BIT(5)
-
-#define AFE_BGEN BIT(0)
-#define AFE_MBEN BIT(1)
-#define MAC_ID_EN BIT(7)
-
-#define WLOCK_ALL BIT(0)
-#define WLOCK_00 BIT(1)
-#define WLOCK_04 BIT(2)
-#define WLOCK_08 BIT(3)
-#define WLOCK_40 BIT(4)
-#define R_DIS_PRST_0 BIT(5)
-#define R_DIS_PRST_1 BIT(6)
-#define LOCK_ALL_EN BIT(7)
-
-#define RF_EN BIT(0)
-#define RF_RSTB BIT(1)
-#define RF_SDMRSTB BIT(2)
-
-#define LDA15_EN BIT(0)
-#define LDA15_STBY BIT(1)
-#define LDA15_OBUF BIT(2)
-#define LDA15_REG_VOS BIT(3)
-#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
-
-#define LDV12_EN BIT(0)
-#define LDV12_SDBY BIT(1)
-#define LPLDO_HSM BIT(2)
-#define LPLDO_LSM_DIS BIT(3)
-#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
-
-#define XTAL_EN BIT(0)
-#define XTAL_BSEL BIT(1)
-#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
-#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
-#define XTAL_GATE_USB BIT(8)
-#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
-#define XTAL_GATE_AFE BIT(11)
-#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
-#define XTAL_RF_GATE BIT(14)
-#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
-#define XTAL_GATE_DIG BIT(17)
-#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
-#define XTAL_BT_GATE BIT(20)
-#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
-#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
-
-#define CKDLY_AFE BIT(26)
-#define CKDLY_USB BIT(27)
-#define CKDLY_DIG BIT(28)
-#define CKDLY_BT BIT(29)
-
-#define APLL_EN BIT(0)
-#define APLL_320_EN BIT(1)
-#define APLL_FREF_SEL BIT(2)
-#define APLL_EDGE_SEL BIT(3)
-#define APLL_WDOGB BIT(4)
-#define APLL_LPFEN BIT(5)
-
-#define APLL_REF_CLK_13MHZ 0x1
-#define APLL_REF_CLK_19_2MHZ 0x2
-#define APLL_REF_CLK_20MHZ 0x3
-#define APLL_REF_CLK_25MHZ 0x4
-#define APLL_REF_CLK_26MHZ 0x5
-#define APLL_REF_CLK_38_4MHZ 0x6
-#define APLL_REF_CLK_40MHZ 0x7
-
-#define APLL_320EN BIT(14)
-#define APLL_80EN BIT(15)
-#define APLL_1MEN BIT(24)
-
-#define ALD_EN BIT(18)
-#define EF_PD BIT(19)
-#define EF_FLAG BIT(31)
-
-#define EF_TRPT BIT(7)
-#define LDOE25_EN BIT(31)
-
-#define RSM_EN BIT(0)
-#define TIMER_EN BIT(4)
-
-#define TRSW0EN BIT(2)
-#define TRSW1EN BIT(3)
-#define EROM_EN BIT(4)
-#define EN_BT BIT(5)
-#define EN_UART BIT(8)
-#define UART_910 BIT(9)
-#define EN_PMAC BIT(10)
-#define SIC_SWRST BIT(11)
-#define EN_SIC BIT(12)
-#define SIC_23 BIT(13)
-#define EN_HDP BIT(14)
-#define SIC_LBK BIT(15)
-
-#define LED0PL BIT(4)
-#define LED1PL BIT(12)
-#define LED0DIS BIT(7)
-
-#define MCUFWDL_EN BIT(0)
-#define MCUFWDL_RDY BIT(1)
-#define FWDL_CHKSUM_RPT BIT(2)
-#define MACINI_RDY BIT(3)
-#define BBINI_RDY BIT(4)
-#define RFINI_RDY BIT(5)
-#define WINTINI_RDY BIT(6)
-#define CPRST BIT(23)
-
-#define XCLK_VLD BIT(0)
-#define ACLK_VLD BIT(1)
-#define UCLK_VLD BIT(2)
-#define PCLK_VLD BIT(3)
-#define PCIRSTB BIT(4)
-#define V15_VLD BIT(5)
-#define TRP_B15V_EN BIT(7)
-#define SIC_IDLE BIT(8)
-#define BD_MAC2 BIT(9)
-#define BD_MAC1 BIT(10)
-#define IC_MACPHY_MODE BIT(11)
-#define VENDOR_ID BIT(19)
-#define PAD_HWPD_IDN BIT(22)
-#define TRP_VAUX_EN BIT(23)
-#define TRP_BT_EN BIT(24)
-#define BD_PKG_SEL BIT(25)
-#define BD_HCI_SEL BIT(26)
-#define TYPE_ID BIT(27)
-
-#define CHIP_VER_RTL_MASK 0xF000
-#define CHIP_VER_RTL_SHIFT 12
-
-#define REG_LBMODE_8822B (REG_CR_8822B + 3)
-
-#define HCI_TXDMA_EN BIT(0)
-#define HCI_RXDMA_EN BIT(1)
-#define TXDMA_EN BIT(2)
-#define RXDMA_EN BIT(3)
-#define PROTOCOL_EN BIT(4)
-#define SCHEDULE_EN BIT(5)
-#define MACTXEN BIT(6)
-#define MACRXEN BIT(7)
-#define ENSWBCN BIT(8)
-#define ENSEC BIT(9)
-
-#define _NETTYPE(x) (((x) & 0x3) << 16)
-#define MASK_NETTYPE 0x30000
-#define NT_NO_LINK 0x0
-#define NT_LINK_AD_HOC 0x1
-#define NT_LINK_AP 0x2
-#define NT_AS_AP 0x3
-
-#define _LBMODE(x) (((x) & 0xF) << 24)
-#define MASK_LBMODE 0xF000000
-#define LOOPBACK_NORMAL 0x0
-#define LOOPBACK_IMMEDIATELY 0xB
-#define LOOPBACK_MAC_DELAY 0x3
-#define LOOPBACK_PHY 0x1
-#define LOOPBACK_DMA 0x7
-
-#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
-#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
-#define _PSRX_MASK 0xF
-#define _PSTX_MASK 0xF0
-#define _PSRX(x) (x)
-#define _PSTX(x) ((x) << 4)
-
-#define PBP_64 0x0
-#define PBP_128 0x1
-#define PBP_256 0x2
-#define PBP_512 0x3
-#define PBP_1024 0x4
-
-#define RXDMA_ARBBW_EN BIT(0)
-#define RXSHFT_EN BIT(1)
-#define RXDMA_AGG_EN BIT(2)
-#define QS_VO_QUEUE BIT(8)
-#define QS_VI_QUEUE BIT(9)
-#define QS_BE_QUEUE BIT(10)
-#define QS_BK_QUEUE BIT(11)
-#define QS_MANAGER_QUEUE BIT(12)
-#define QS_HIGH_QUEUE BIT(13)
-
-#define HQSEL_VOQ BIT(0)
-#define HQSEL_VIQ BIT(1)
-#define HQSEL_BEQ BIT(2)
-#define HQSEL_BKQ BIT(3)
-#define HQSEL_MGTQ BIT(4)
-#define HQSEL_HIQ BIT(5)
-
-#define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14)
-#define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12)
-#define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10)
-#define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8)
-#define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6)
-#define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4)
-
-#define QUEUE_LOW 1
-#define QUEUE_NORMAL 2
-#define QUEUE_HIGH 3
-
-#define _LLT_NO_ACTIVE 0x0
-#define _LLT_WRITE_ACCESS 0x1
-#define _LLT_READ_ACCESS 0x2
-
-#define _LLT_INIT_DATA(x) ((x) & 0xFF)
-#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
-#define _LLT_OP(x) (((x) & 0x3) << 30)
-#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
-
-#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
-#define BB_WRITE_EN BIT(30)
-#define BB_READ_EN BIT(31)
-
-#define _HPQ(x) ((x) & 0xFF)
-#define _LPQ(x) (((x) & 0xFF) << 8)
-#define _PUBQ(x) (((x) & 0xFF) << 16)
-#define _NPQ(x) ((x) & 0xFF)
-
-#define HPQ_PUBLIC_DIS BIT(24)
-#define LPQ_PUBLIC_DIS BIT(25)
-#define LD_RQPN BIT(31)
-
-#define BCN_VALID BIT(16)
-#define BCN_HEAD(x) (((x) & 0xFF) << 8)
-#define BCN_HEAD_MASK 0xFF00
-
-#define BLK_DESC_NUM_SHIFT 4
-#define BLK_DESC_NUM_MASK 0xF
-
-#define DROP_DATA_EN BIT(9)
-
-#define EN_AMPDU_RTY_NEW BIT(7)
-
-#define _INIRTSMCS_SEL(x) ((x) & 0x3F)
-
-#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
-#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
-
-#define RATE_REG_BITMAP_ALL 0xFFFFF
-
-#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
-
-#define _RRSR_RSC(x) (((x) & 0x3) << 21)
-#define RRSR_RSC_RESERVED 0x0
-#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
-#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
-#define RRSR_RSC_DUPLICATE_MODE 0x3
-
-#define USE_SHORT_G1 BIT(20)
-
-#define _AGGLMT_MCS0(x) ((x) & 0xF)
-#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
-#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
-#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
-#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
-#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
-#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
-#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
-
-#define RETRY_LIMIT_SHORT_SHIFT 8
-#define RETRY_LIMIT_LONG_SHIFT 0
-
-#define _DARF_RC1(x) ((x) & 0x1F)
-#define _DARF_RC2(x) (((x) & 0x1F) << 8)
-#define _DARF_RC3(x) (((x) & 0x1F) << 16)
-#define _DARF_RC4(x) (((x) & 0x1F) << 24)
-#define _DARF_RC5(x) ((x) & 0x1F)
-#define _DARF_RC6(x) (((x) & 0x1F) << 8)
-#define _DARF_RC7(x) (((x) & 0x1F) << 16)
-#define _DARF_RC8(x) (((x) & 0x1F) << 24)
-
-#define _RARF_RC1(x) ((x) & 0x1F)
-#define _RARF_RC2(x) (((x) & 0x1F) << 8)
-#define _RARF_RC3(x) (((x) & 0x1F) << 16)
-#define _RARF_RC4(x) (((x) & 0x1F) << 24)
-#define _RARF_RC5(x) ((x) & 0x1F)
-#define _RARF_RC6(x) (((x) & 0x1F) << 8)
-#define _RARF_RC7(x) (((x) & 0x1F) << 16)
-#define _RARF_RC8(x) (((x) & 0x1F) << 24)
-
-#define AC_PARAM_TXOP_LIMIT_OFFSET 16
-#define AC_PARAM_ECW_MAX_OFFSET 12
-#define AC_PARAM_ECW_MIN_OFFSET 8
-#define AC_PARAM_AIFS_OFFSET 0
-
-#define _AIFS(x) (x)
-#define _ECW_MAX_MIN(x) ((x) << 8)
-#define _TXOP_LIMIT(x) ((x) << 16)
-
-#define _BCNIFS(x) ((x) & 0xFF)
-#define _BCNECW(x) ((((x) & 0xF)) << 8)
-
-#define _LRL(x) ((x) & 0x3F)
-#define _SRL(x) (((x) & 0x3F) << 8)
-
-#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
-#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)
-
-#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
-#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)
-
-#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
-
-#define DIS_EDCA_CNT_DWN BIT(11)
-
-#define EN_MBSSID BIT(1)
-#define EN_TXBCN_RPT BIT(2)
-#define EN_BCN_FUNCTION BIT(3)
-
-#define TSFTR_RST BIT(0)
-#define TSFTR1_RST BIT(1)
-
-#define STOP_BCNQ BIT(6)
-
-#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
-#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
-
-#define ACMHW_HW_EN BIT(0)
-#define ACMHW_BEQ_EN BIT(1)
-#define ACMHW_VIQ_EN BIT(2)
-#define ACMHW_VOQ_EN BIT(3)
-#define ACMHW_BEQ_STATUS BIT(4)
-#define ACMHW_VIQ_STATUS BIT(5)
-#define ACMHW_VOQ_STATUS BIT(6)
-
-#define APSDOFF BIT(6)
-#define APSDOFF_STATUS BIT(7)
-
-#define BW_20MHZ BIT(2)
-
-#define RATE_BITMAP_ALL 0xFFFFF
-
-#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
-
-#define TSFRST BIT(0)
-#define DIS_GCLK BIT(1)
-#define PAD_SEL BIT(2)
-#define PWR_ST BIT(6)
-#define PWRBIT_OW_EN BIT(7)
-#define ACRC BIT(8)
-#define CFENDFORM BIT(9)
-#define ICV BIT(10)
-
-#define AAP BIT(0)
-#define APM BIT(1)
-#define AM BIT(2)
-#define AB BIT(3)
-#define ADD3 BIT(4)
-#define APWRMGT BIT(5)
-#define CBSSID BIT(6)
-#define CBSSID_DATA BIT(6)
-#define CBSSID_BCN BIT(7)
-#define ACRC32 BIT(8)
-#define AICV BIT(9)
-#define ADF BIT(11)
-#define ACF BIT(12)
-#define AMF BIT(13)
-#define HTC_LOC_CTRL BIT(14)
-#define UC_DATA_EN BIT(16)
-#define BM_DATA_EN BIT(17)
-#define MFBEN BIT(22)
-#define LSIGEN BIT(23)
-#define EN_MBID BIT(24)
-#define APP_BASSN BIT(27)
-#define APP_PHYSTS BIT(28)
-#define APP_ICV BIT(29)
-#define APP_MIC BIT(30)
-#define APP_FCS BIT(31)
-
-#define _MIN_SPACE(x) ((x) & 0x7)
-#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
-
-#define RXERR_TYPE_OFDM_PPDU 0
-#define RXERR_TYPE_OFDM_FALSE_ALARM 1
-#define RXERR_TYPE_OFDM_MPDU_OK 2
-#define RXERR_TYPE_OFDM_MPDU_FAIL 3
-#define RXERR_TYPE_CCK_PPDU 4
-#define RXERR_TYPE_CCK_FALSE_ALARM 5
-#define RXERR_TYPE_CCK_MPDU_OK 6
-#define RXERR_TYPE_CCK_MPDU_FAIL 7
-#define RXERR_TYPE_HT_PPDU 8
-#define RXERR_TYPE_HT_FALSE_ALARM 9
-#define RXERR_TYPE_HT_MPDU_TOTAL 10
-#define RXERR_TYPE_HT_MPDU_OK 11
-#define RXERR_TYPE_HT_MPDU_FAIL 12
-#define RXERR_TYPE_RX_FULL_DROP 15
-
-#define RXERR_COUNTER_MASK 0xFFFFF
-#define RXERR_RPT_RST BIT(27)
-#define _RXERR_RPT_SEL(type) ((type) << 28)
-
-#define SCR_TX_USE_DK BIT(0)
-#define SCR_RX_USE_DK BIT(1)
-#define SCR_TX_ENC_ENABLE BIT(2)
-#define SRC_RX_DEC_ENABLE BIT(3)
-#define SCR_SK_BY_A2 BIT(4)
-#define SCR_NO_SKMC BIT(5)
-#define SCR_TXBCUSEDK BIT(6)
-#define SCR_RXBCUSEDK BIT(7)
-
-#define USB_IS_HIGH_SPEED 0
-#define USB_IS_FULL_SPEED 1
-#define USB_SPEED_MASK BIT(5)
-
-#define USB_NORMAL_SIE_EP_MASK 0xF
-#define USB_NORMAL_SIE_EP_SHIFT 4
-
-#define USB_TEST_EP_MASK 0x30
-#define USB_TEST_EP_SHIFT 4
-
-#define USB_AGG_EN BIT(3)
-
-#define MAC_ADDR_LEN 6
-#define LAST_ENTRY_OF_TX_PKT_BUFFER 175
-
-#define POLLING_LLT_THRESHOLD 20
-#define POLLING_READY_TIMEOUT_COUNT 3000
-
-#define MAX_MSS_DENSITY_2T 0x13
-#define MAX_MSS_DENSITY_1T 0x0A
-
-#define EPROM_CMD_OPERATING_MODE_MASK ((1 << 7) | (1 << 6))
-#define EPROM_CMD_CONFIG 0x3
-#define EPROM_CMD_LOAD 1
-
-#define HAL_8822B_HW_GPIO_WPS_BIT BIT(2)
-
-/*-----------------------------------------------------
- * BB / RF register
- *-----------------------------------------------------
- */
-
-#define RFPGA0_XA_HSSIPARAMETER1 0x820
-#define RFPGA0_XA_HSSIPARAMETER2 0x824
-#define RFPGA0_XB_HSSIPARAMETER1 0x828
-#define RFPGA0_XB_HSSIPARAMETER2 0x82c
-#define RCCAONSEC 0x838
-
-#define RFPGA0_XA_LSSIPARAMETER 0x840
-#define RFPGA0_XB_LSSIPARAMETER 0x844
-#define RL1PEAKTH 0x848
-
-#define RFPGA0_RFWAKEUPPARAMETER 0x850
-#define RFPGA0_RFSLEEPUPPARAMETER 0x854
-
-#define RFPGA0_XAB_SWITCHCONTROL 0x858
-#define RFPGA0_XCD_SWITCHCONTROL 0x85c
-
-#define RFPGA0_XA_RFINTERFACEOE 0x860
-#define RFC_AREA 0x860
-#define RFPGA0_XB_RFINTERFACEOE 0x864
-
-#define RFPGA0_XAB_RFINTERFACESW 0x870
-#define RFPGA0_XCD_RFINTERFACESW 0x874
-
-#define RFPGA0_XAB_RF_PARA_METER 0x878
-#define RFPGA0_XCD_RF_PARA_METER 0x87c
-
-#define RFPGA0_ANALOGPARAMETER1 0x880
-#define RFPGA0_ANALOGPARAMETER2 0x884
-#define RFPGA0_ANALOGPARAMETER3 0x888
-#define RFPGA0_ANALOGPARAMETER4 0x88c
-
-#define RFPGA0_XA_LSSIREADBACK 0x8a0
-#define RFPGA0_XB_LSSIREADBACK 0x8a4
-#define RFPGA0_XC_LSSIREADBACK 0x8a8
-/*#define RFPGA0_XD_LSSIREADBACK 0x8ac*/
-#define RRFMOD 0x8ac
-#define RHSSIREAD_8822BE 0x8b0
-
-#define RFPGA0_PSDREPORT 0x8b4
-#define TRANSCEIVEA_HSPI_READBACK 0x8b8
-#define TRANSCEIVEB_HSPI_READBACK 0x8bc
-/*#define REG_SC_CNT_8822B 0x8c4*/
-#define RADC_BUF_CLK 0x8c4
-#define RFPGA0_XAB_RFINTERFACERB 0x8e0
-#define RFPGA0_XCD_RFINTERFACERB 0x8e4
-
-/* PageB(0xB00) */
-
-/*Page C*/
-
-#define RA_TXPWRTRAING 0xc54
-#define RB_TXPWRTRAING 0xe54
-
-#define RA_LSSIWRITE_8822B 0xc90
-#define RB_LSSIWRITE_8822B 0xe90
-
-#define RA_PIREAD_8822B 0xd04
-#define RB_PIREAD_8822B 0xd44
-#define RA_SIREAD_8822B 0xd08
-#define RB_SIREAD_8822B 0xd48
-
-#define RZEBRA1_HSSIENABLE 0x0
-#define RZEBRA1_TRXENABLE1 0x1
-#define RZEBRA1_TRXENABLE2 0x2
-#define RZEBRA1_AGC 0x4
-#define RZEBRA1_CHARGEPUMP 0x5
-#define RZEBRA1_CHANNEL 0x7
-
-#define RZEBRA1_TXGAIN 0x8
-#define RZEBRA1_TXLPF 0x9
-#define RZEBRA1_RXLPF 0xb
-#define RZEBRA1_RXHPFCORNER 0xc
-
-#define RGLOBALCTRL 0
-#define RRTL8256_TXLPF 19
-#define RRTL8256_RXLPF 11
-#define RRTL8258_TXLPF 0x11
-#define RRTL8258_RXLPF 0x13
-#define RRTL8258_RSSILPF 0xa
-
-#define RF_AC 0x00
-
-#define RF_IQADJ_G1 0x01
-#define RF_IQADJ_G2 0x02
-#define RF_POW_TRSW 0x05
-
-#define RF_GAIN_RX 0x06
-#define RF_GAIN_TX 0x07
-
-#define RF_TXM_IDAC 0x08
-#define RF_BS_IQGEN 0x0F
-
-#define RF_MODE1 0x10
-#define RF_MODE2 0x11
-
-#define RF_RX_AGC_HP 0x12
-#define RF_TX_AGC 0x13
-#define RF_BIAS 0x14
-#define RF_IPA 0x15
-#define RF_POW_ABILITY 0x17
-#define RF_MODE_AG 0x18
-#define RRFCHANNEL 0x18
-#define RF_CHNLBW 0x18
-#define RF_TOP 0x19
-
-#define RF_RX_G1 0x1A
-#define RF_RX_G2 0x1B
-
-#define RF_RX_BB2 0x1C
-#define RF_RX_BB1 0x1D
-
-#define RF_RCK1 0x1E
-#define RF_RCK2 0x1F
-
-#define RF_TX_G1 0x20
-#define RF_TX_G2 0x21
-#define RF_TX_G3 0x22
-
-#define RF_TX_BB1 0x23
-#define RF_T_METER 0x42
-
-#define RF_SYN_G1 0x25
-#define RF_SYN_G2 0x26
-#define RF_SYN_G3 0x27
-#define RF_SYN_G4 0x28
-#define RF_SYN_G5 0x29
-#define RF_SYN_G6 0x2A
-#define RF_SYN_G7 0x2B
-#define RF_SYN_G8 0x2C
-
-#define RF_RCK_OS 0x30
-#define RF_TXPA_G1 0x31
-#define RF_TXPA_G2 0x32
-#define RF_TXPA_G3 0x33
-
-#define RF_TX_BIAS_A 0x35
-#define RF_TX_BIAS_D 0x36
-#define RF_LOBF_9 0x38
-#define RF_RXRF_A3 0x3C
-#define RF_TRSW 0x3F
-
-#define RF_TXRF_A2 0x41
-#define RF_TXPA_G4 0x46
-#define RF_TXPA_A4 0x4B
-
-#define RF_APK 0x63
-
-#define RF_WE_LUT 0xEF
-
-#define BBBRESETB 0x100
-#define BGLOBALRESETB 0x200
-#define BOFDMTXSTART 0x4
-#define BCCKTXSTART 0x8
-#define BCRC32DEBUG 0x100
-#define BPMACLOOPBACK 0x10
-#define BTXLSIG 0xffffff
-#define BOFDMTXRATE 0xf
-#define BOFDMTXRESERVED 0x10
-#define BOFDMTXLENGTH 0x1ffe0
-#define BOFDMTXPARITY 0x20000
-#define BTXHTSIG1 0xffffff
-#define BTXHTMCSRATE 0x7f
-#define BTXHTBW 0x80
-#define BTXHTLENGTH 0xffff00
-#define BTXHTSIG2 0xffffff
-#define BTXHTSMOOTHING 0x1
-#define BTXHTSOUNDING 0x2
-#define BTXHTRESERVED 0x4
-#define BTXHTAGGREATION 0x8
-#define BTXHTSTBC 0x30
-#define BTXHTADVANCECODING 0x40
-#define BTXHTSHORTGI 0x80
-#define BTXHTNUMBERHT_LTF 0x300
-#define BTXHTCRC8 0x3fc00
-#define BCOUNTERRESET 0x10000
-#define BNUMOFOFDMTX 0xffff
-#define BNUMOFCCKTX 0xffff0000
-#define BTXIDLEINTERVAL 0xffff
-#define BOFDMSERVICE 0xffff0000
-#define BTXMACHEADER 0xffffffff
-#define BTXDATAINIT 0xff
-#define BTXHTMODE 0x100
-#define BTXDATATYPE 0x30000
-#define BTXRANDOMSEED 0xffffffff
-#define BCCKTXPREAMBLE 0x1
-#define BCCKTXSFD 0xffff0000
-#define BCCKTXSIG 0xff
-#define BCCKTXSERVICE 0xff00
-#define BCCKLENGTHEXT 0x8000
-#define BCCKTXLENGHT 0xffff0000
-#define BCCKTXCRC16 0xffff
-#define BCCKTXSTATUS 0x1
-#define BOFDMTXSTATUS 0x2
-#define IS_BB_REG_OFFSET_92S(_offset) ((_offset >= 0x800) && (_offset <= 0xfff))
-
-#define BRFMOD 0x1
-#define BJAPANMODE 0x2
-#define BCCKTXSC 0x30
-/* Block & Path enable*/
-#define ROFDMCCKEN 0x808
-#define BCCKEN 0x10000000
-#define BOFDMEN 0x20000000
-/* Rx antenna*/
-#define RRXPATH 0x808
-#define BRXPATH 0xff
-/* Tx antenna*/
-#define RTXPATH 0x80c
-#define BTXPATH 0x0fffffff
-/* for cck rx path selection*/
-#define RCCK_RX 0xa04
-#define BCCK_RX 0x0c000000
-/* Use LSIG for VHT length*/
-#define RVHTLEN_USE_LSIG 0x8c3
-
-#define BOFDMRXADCPHASE 0x10000
-#define BOFDMTXDACPHASE 0x40000
-#define BXATXAGC 0x3f
-
-#define BXBTXAGC 0xf00
-#define BXCTXAGC 0xf000
-#define BXDTXAGC 0xf0000
-
-#define BPASTART 0xf0000000
-#define BTRSTART 0x00f00000
-#define BRFSTART 0x0000f000
-#define BBBSTART 0x000000f0
-#define BBBCCKSTART 0x0000000f
-#define BPAEND 0xf
-#define BTREND 0x0f000000
-#define BRFEND 0x000f0000
-#define BCCAMASK 0x000000f0
-#define BR2RCCAMASK 0x00000f00
-#define BHSSI_R2TDELAY 0xf8000000
-#define BHSSI_T2RDELAY 0xf80000
-#define BCONTXHSSI 0x400
-#define BIGFROMCCK 0x200
-#define BAGCADDRESS 0x3f
-#define BRXHPTX 0x7000
-#define BRXHP2RX 0x38000
-#define BRXHPCCKINI 0xc0000
-#define BAGCTXCODE 0xc00000
-#define BAGCRXCODE 0x300000
-
-#define B3WIREDATALENGTH 0x800
-#define B3WIREADDREAALENGTH 0x400
-
-#define B3WIRERFPOWERDOWN 0x1
-#define B5GPAPEPOLARITY 0x40000000
-#define B2GPAPEPOLARITY 0x80000000
-#define BRFSW_TXDEFAULTANT 0x3
-#define BRFSW_TXOPTIONANT 0x30
-#define BRFSW_RXDEFAULTANT 0x300
-#define BRFSW_RXOPTIONANT 0x3000
-#define BRFSI_3WIREDATA 0x1
-#define BRFSI_3WIRECLOCK 0x2
-#define BRFSI_3WIRELOAD 0x4
-#define BRFSI_3WIRERW 0x8
-#define BRFSI_3WIRE 0xf
-
-#define BRFSI_RFENV 0x10
-
-#define BRFSI_TRSW 0x20
-#define BRFSI_TRSWB 0x40
-#define BRFSI_ANTSW 0x100
-#define BRFSI_ANTSWB 0x200
-#define BRFSI_PAPE 0x400
-#define BRFSI_PAPE5G 0x800
-#define BBANDSELECT 0x1
-#define BHTSIG2_GI 0x80
-#define BHTSIG2_SMOOTHING 0x01
-#define BHTSIG2_SOUNDING 0x02
-#define BHTSIG2_AGGREATON 0x08
-#define BHTSIG2_STBC 0x30
-#define BHTSIG2_ADVCODING 0x40
-#define BHTSIG2_NUMOFHTLTF 0x300
-#define BHTSIG2_CRC8 0x3fc
-#define BHTSIG1_MCS 0x7f
-#define BHTSIG1_BANDWIDTH 0x80
-#define BHTSIG1_HTLENGTH 0xffff
-#define BLSIG_RATE 0xf
-#define BLSIG_RESERVED 0x10
-#define BLSIG_LENGTH 0x1fffe
-#define BLSIG_PARITY 0x20
-#define BCCKRXPHASE 0x4
-
-#define BLSSIREADADDRESS 0x7f800000
-#define BLSSIREADEDGE 0x80000000
-
-#define BLSSIREADBACKDATA 0xfffff
-
-#define BLSSIREADOKFLAG 0x1000
-#define BCCKSAMPLERATE 0x8
-#define BREGULATOR0STANDBY 0x1
-#define BREGULATORPLLSTANDBY 0x2
-#define BREGULATOR1STANDBY 0x4
-#define BPLLPOWERUP 0x8
-#define BDPLLPOWERUP 0x10
-#define BDA10POWERUP 0x20
-#define BAD7POWERUP 0x200
-#define BDA6POWERUP 0x2000
-#define BXTALPOWERUP 0x4000
-#define B40MDCLKPOWERUP 0x8000
-#define BDA6DEBUGMODE 0x20000
-#define BDA6SWING 0x380000
-
-#define BADCLKPHASE 0x4000000
-#define B80MCLKDELAY 0x18000000
-#define BAFEWATCHDOGENABLE 0x20000000
-
-#define BXTALCAP01 0xc0000000
-#define BXTALCAP23 0x3
-#define BXTALCAP92X 0x0f000000
-#define BXTALCAP 0x0f000000
-
-#define BINTDIFCLKENABLE 0x400
-#define BEXTSIGCLKENABLE 0x800
-#define BBANDGAP_MBIAS_POWERUP 0x10000
-#define BAD11SH_GAIN 0xc0000
-#define BAD11NPUT_RANGE 0x700000
-#define BAD110P_CURRENT 0x3800000
-#define BLPATH_LOOPBACK 0x4000000
-#define BQPATH_LOOPBACK 0x8000000
-#define BAFE_LOOPBACK 0x10000000
-#define BDA10_SWING 0x7e0
-#define BDA10_REVERSE 0x800
-#define BDA_CLK_SOURCE 0x1000
-#define BDA7INPUT_RANGE 0x6000
-#define BDA7_GAIN 0x38000
-#define BDA7OUTPUT_CM_MODE 0x40000
-#define BDA7INPUT_CM_MODE 0x380000
-#define BDA7CURRENT 0xc00000
-#define BREGULATOR_ADJUST 0x7000000
-#define BAD11POWERUP_ATTX 0x1
-#define BDA10PS_ATTX 0x10
-#define BAD11POWERUP_ATRX 0x100
-#define BDA10PS_ATRX 0x1000
-#define BCCKRX_AGC_FORMAT 0x200
-#define BPSDFFT_SAMPLE_POINT 0xc000
-#define BPSD_AVERAGE_NUM 0x3000
-#define BIQPATH_CONTROL 0xc00
-#define BPSD_FREQ 0x3ff
-#define BPSD_ANTENNA_PATH 0x30
-#define BPSD_IQ_SWITCH 0x40
-#define BPSD_RX_TRIGGER 0x400000
-#define BPSD_TX_TRIGGER 0x80000000
-#define BPSD_SINE_TONE_SCALE 0x7f000000
-#define BPSD_REPORT 0xffff
-
-#define BOFDM_TXSC 0x30000000
-#define BCCK_TXON 0x1
-#define BOFDM_TXON 0x2
-#define BDEBUG_PAGE 0xfff
-#define BDEBUG_ITEM 0xff
-#define BANTL 0x10
-#define BANT_NONHT 0x100
-#define BANT_HT1 0x1000
-#define BANT_HT2 0x10000
-#define BANT_HT1S1 0x100000
-#define BANT_NONHTS1 0x1000000
-
-#define BCCK_BBMODE 0x3
-#define BCCK_TXPOWERSAVING 0x80
-#define BCCK_RXPOWERSAVING 0x40
-
-#define BCCK_SIDEBAND 0x10
-
-#define BCCK_SCRAMBLE 0x8
-#define BCCK_ANTDIVERSITY 0x8000
-#define BCCK_CARRIER_RECOVERY 0x4000
-#define BCCK_TXRATE 0x3000
-#define BCCK_DCCANCEL 0x0800
-#define BCCK_ISICANCEL 0x0400
-#define BCCK_MATCH_FILTER 0x0200
-#define BCCK_EQUALIZER 0x0100
-#define BCCK_PREAMBLE_DETECT 0x800000
-#define BCCK_FAST_FALSECCA 0x400000
-#define BCCK_CH_ESTSTART 0x300000
-#define BCCK_CCA_COUNT 0x080000
-#define BCCK_CS_LIM 0x070000
-#define BCCK_BIST_MODE 0x80000000
-#define BCCK_CCAMASK 0x40000000
-#define BCCK_TX_DAC_PHASE 0x4
-#define BCCK_RX_ADC_PHASE 0x20000000
-#define BCCKR_CP_MODE 0x0100
-#define BCCK_TXDC_OFFSET 0xf0
-#define BCCK_RXDC_OFFSET 0xf
-#define BCCK_CCA_MODE 0xc000
-#define BCCK_FALSECS_LIM 0x3f00
-#define BCCK_CS_RATIO 0xc00000
-#define BCCK_CORGBIT_SEL 0x300000
-#define BCCK_PD_LIM 0x0f0000
-#define BCCK_NEWCCA 0x80000000
-#define BCCK_RXHP_OF_IG 0x8000
-#define BCCK_RXIG 0x7f00
-#define BCCK_LNA_POLARITY 0x800000
-#define BCCK_RX1ST_BAIN 0x7f0000
-#define BCCK_RF_EXTEND 0x20000000
-#define BCCK_RXAGC_SATLEVEL 0x1f000000
-#define BCCK_RXAGC_SATCOUNT 0xe0
-#define BCCK_RX_RF_SETTLE 0x1f
-#define BCCK_FIXED_RXAGC 0x8000
-#define BCCK_ANTENNA_POLARITY 0x2000
-#define BCCK_TXFILTER_TYPE 0x0c00
-#define BCCK_RXAGC_REPORTTYPE 0x0300
-#define BCCK_RXDAGC_EN 0x80000000
-#define BCCK_RXDAGC_PERIOD 0x20000000
-#define BCCK_RXDAGC_SATLEVEL 0x1f000000
-#define BCCK_TIMING_RECOVERY 0x800000
-#define BCCK_TXC0 0x3f0000
-#define BCCK_TXC1 0x3f000000
-#define BCCK_TXC2 0x3f
-#define BCCK_TXC3 0x3f00
-#define BCCK_TXC4 0x3f0000
-#define BCCK_TXC5 0x3f000000
-#define BCCK_TXC6 0x3f
-#define BCCK_TXC7 0x3f00
-#define BCCK_DEBUGPORT 0xff0000
-#define BCCK_DAC_DEBUG 0x0f000000
-#define BCCK_FALSEALARM_ENABLE 0x8000
-#define BCCK_FALSEALARM_READ 0x4000
-#define BCCK_TRSSI 0x7f
-#define BCCK_RXAGC_REPORT 0xfe
-#define BCCK_RXREPORT_ANTSEL 0x80000000
-#define BCCK_RXREPORT_MFOFF 0x40000000
-#define BCCK_RXREPORT_SQLOSS 0x20000000
-#define BCCK_RXREPORT_PKTLOSS 0x10000000
-#define BCCK_RXREPORT_LOCKEDBIT 0x08000000
-#define BCCK_RXREPORT_RATEERROR 0x04000000
-#define BCCK_RXREPORT_RXRATE 0x03000000
-#define BCCK_RXFA_COUNTER_LOWER 0xff
-#define BCCK_RXFA_COUNTER_UPPER 0xff000000
-#define BCCK_RXHPAGC_START 0xe000
-#define BCCK_RXHPAGC_FINAL 0x1c00
-#define BCCK_RXFALSEALARM_ENABLE 0x8000
-#define BCCK_FACOUNTER_FREEZE 0x4000
-#define BCCK_TXPATH_SEL 0x10000000
-#define BCCK_DEFAULT_RXPATH 0xc000000
-#define BCCK_OPTION_RXPATH 0x3000000
-
-#define BNUM_OFSTF 0x3
-#define BSHIFT_L 0xc0
-#define BGI_TH 0xc
-#define BRXPATH_A 0x1
-#define BRXPATH_B 0x2
-#define BRXPATH_C 0x4
-#define BRXPATH_D 0x8
-#define BTXPATH_A 0x1
-#define BTXPATH_B 0x2
-#define BTXPATH_C 0x4
-#define BTXPATH_D 0x8
-#define BTRSSI_FREQ 0x200
-#define BADC_BACKOFF 0x3000
-#define BDFIR_BACKOFF 0xc000
-#define BTRSSI_LATCH_PHASE 0x10000
-#define BRX_LDC_OFFSET 0xff
-#define BRX_QDC_OFFSET 0xff00
-#define BRX_DFIR_MODE 0x1800000
-#define BRX_DCNF_TYPE 0xe000000
-#define BRXIQIMB_A 0x3ff
-#define BRXIQIMB_B 0xfc00
-#define BRXIQIMB_C 0x3f0000
-#define BRXIQIMB_D 0xffc00000
-#define BDC_DC_NOTCH 0x60000
-#define BRXNB_NOTCH 0x1f000000
-#define BPD_TH 0xf
-#define BPD_TH_OPT2 0xc000
-#define BPWED_TH 0x700
-#define BIFMF_WIN_L 0x800
-#define BPD_OPTION 0x1000
-#define BMF_WIN_L 0xe000
-#define BBW_SEARCH_L 0x30000
-#define BWIN_ENH_L 0xc0000
-#define BBW_TH 0x700000
-#define BED_TH2 0x3800000
-#define BBW_OPTION 0x4000000
-#define BRADIO_TH 0x18000000
-#define BWINDOW_L 0xe0000000
-#define BSBD_OPTION 0x1
-#define BFRAME_TH 0x1c
-#define BFS_OPTION 0x60
-#define BDC_SLOPE_CHECK 0x80
-#define BFGUARD_COUNTER_DC_L 0xe00
-#define BFRAME_WEIGHT_SHORT 0x7000
-#define BSUB_TUNE 0xe00000
-#define BFRAME_DC_LENGTH 0xe000000
-#define BSBD_START_OFFSET 0x30000000
-#define BFRAME_TH_2 0x7
-#define BFRAME_GI2_TH 0x38
-#define BGI2_SYNC_EN 0x40
-#define BSARCH_SHORT_EARLY 0x300
-#define BSARCH_SHORT_LATE 0xc00
-#define BSARCH_GI2_LATE 0x70000
-#define BCFOANTSUM 0x1
-#define BCFOACC 0x2
-#define BCFOSTARTOFFSET 0xc
-#define BCFOLOOPBACK 0x70
-#define BCFOSUMWEIGHT 0x80
-#define BDAGCENABLE 0x10000
-#define BTXIQIMB_A 0x3ff
-#define BTXIQIMB_b 0xfc00
-#define BTXIQIMB_C 0x3f0000
-#define BTXIQIMB_D 0xffc00000
-#define BTXIDCOFFSET 0xff
-#define BTXIQDCOFFSET 0xff00
-#define BTXDFIRMODE 0x10000
-#define BTXPESUDO_NOISEON 0x4000000
-#define BTXPESUDO_NOISE_A 0xff
-#define BTXPESUDO_NOISE_B 0xff00
-#define BTXPESUDO_NOISE_C 0xff0000
-#define BTXPESUDO_NOISE_D 0xff000000
-#define BCCA_DROPOPTION 0x20000
-#define BCCA_DROPTHRES 0xfff00000
-#define BEDCCA_H 0xf
-#define BEDCCA_L 0xf0
-#define BLAMBDA_ED 0x300
-#define BRX_INITIALGAIN 0x7f
-#define BRX_ANTDIV_EN 0x80
-#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
-#define BRX_HIGHPOWER_FLOW 0x8000
-#define BRX_AGC_FREEZE_THRES 0xc0000
-#define BRX_FREEZESTEP_AGC1 0x300000
-#define BRX_FREEZESTEP_AGC2 0xc00000
-#define BRX_FREEZESTEP_AGC3 0x3000000
-#define BRX_FREEZESTEP_AGC0 0xc000000
-#define BRXRSSI_CMP_EN 0x10000000
-#define BRXQUICK_AGCEN 0x20000000
-#define BRXAGC_FREEZE_THRES_MODE 0x40000000
-#define BRX_OVERFLOW_CHECKTYPE 0x80000000
-#define BRX_AGCSHIFT 0x7f
-#define BTRSW_TRI_ONLY 0x80
-#define BPOWER_THRES 0x300
-#define BRXAGC_EN 0x1
-#define BRXAGC_TOGETHER_EN 0x2
-#define BRXAGC_MIN 0x4
-#define BRXHP_INI 0x7
-#define BRXHP_TRLNA 0x70
-#define BRXHP_RSSI 0x700
-#define BRXHP_BBP1 0x7000
-#define BRXHP_BBP2 0x70000
-#define BRXHP_BBP3 0x700000
-#define BRSSI_H 0x7f0000
-#define BRSSI_GEN 0x7f000000
-#define BRXSETTLE_TRSW 0x7
-#define BRXSETTLE_LNA 0x38
-#define BRXSETTLE_RSSI 0x1c0
-#define BRXSETTLE_BBP 0xe00
-#define BRXSETTLE_RXHP 0x7000
-#define BRXSETTLE_ANTSW_RSSI 0x38000
-#define BRXSETTLE_ANTSW 0xc0000
-#define BRXPROCESS_TIME_DAGC 0x300000
-#define BRXSETTLE_HSSI 0x400000
-#define BRXPROCESS_TIME_BBPPW 0x800000
-#define BRXANTENNA_POWER_SHIFT 0x3000000
-#define BRSSI_TABLE_SELECT 0xc000000
-#define BRXHP_FINAL 0x7000000
-#define BRXHPSETTLE_BBP 0x7
-#define BRXHTSETTLE_HSSI 0x8
-#define BRXHTSETTLE_RXHP 0x70
-#define BRXHTSETTLE_BBPPW 0x80
-#define BRXHTSETTLE_IDLE 0x300
-#define BRXHTSETTLE_RESERVED 0x1c00
-#define BRXHT_RXHP_EN 0x8000
-#define BRXAGC_FREEZE_THRES 0x30000
-#define BRXAGC_TOGETHEREN 0x40000
-#define BRXHTAGC_MIN 0x80000
-#define BRXHTAGC_EN 0x100000
-#define BRXHTDAGC_EN 0x200000
-#define BRXHT_RXHP_BBP 0x1c00000
-#define BRXHT_RXHP_FINAL 0xe0000000
-#define BRXPW_RADIO_TH 0x3
-#define BRXPW_RADIO_EN 0x4
-#define BRXMF_HOLD 0x3800
-#define BRXPD_DELAY_TH1 0x38
-#define BRXPD_DELAY_TH2 0x1c0
-#define BRXPD_DC_COUNT_MAX 0x600
-#define BRXPD_DELAY_TH 0x8000
-#define BRXPROCESS_DELAY 0xf0000
-#define BRXSEARCHRANGE_GI2_EARLY 0x700000
-#define BRXFRAME_FUARD_COUNTER_L 0x3800000
-#define BRXSGI_GUARD_L 0xc000000
-#define BRXSGI_SEARCH_L 0x30000000
-#define BRXSGI_TH 0xc0000000
-#define BDFSCNT0 0xff
-#define BDFSCNT1 0xff00
-#define BDFSFLAG 0xf0000
-#define BMF_WEIGHT_SUM 0x300000
-#define BMINIDX_TH 0x7f000000
-#define BDAFORMAT 0x40000
-#define BTXCH_EMU_ENABLE 0x01000000
-#define BTRSW_ISOLATION_A 0x7f
-#define BTRSW_ISOLATION_B 0x7f00
-#define BTRSW_ISOLATION_C 0x7f0000
-#define BTRSW_ISOLATION_D 0x7f000000
-#define BEXT_LNA_GAIN 0x7c00
-
-#define BSTBC_EN 0x4
-#define BANTENNA_MAPPING 0x10
-#define BNSS 0x20
-#define BCFO_ANTSUM_ID 0x200
-#define BPHY_COUNTER_RESET 0x8000000
-#define BCFO_REPORT_GET 0x4000000
-#define BOFDM_CONTINUE_TX 0x10000000
-#define BOFDM_SINGLE_CARRIER 0x20000000
-#define BOFDM_SINGLE_TONE 0x40000000
-#define BHT_DETECT 0x100
-#define BCFOEN 0x10000
-#define BCFOVALUE 0xfff00000
-#define BSIGTONE_RE 0x3f
-#define BSIGTONE_IM 0x7f00
-#define BCOUNTER_CCA 0xffff
-#define BCOUNTER_PARITYFAIL 0xffff0000
-#define BCOUNTER_RATEILLEGAL 0xffff
-#define BCOUNTER_CRC8FAIL 0xffff0000
-#define BCOUNTER_MCSNOSUPPORT 0xffff
-#define BCOUNTER_FASTSYNC 0xffff
-#define BSHORTCFO 0xfff
-#define BSHORTCFOT_LENGTH 12
-#define BSHORTCFOF_LENGTH 11
-#define BLONGCFO 0x7ff
-#define BLONGCFOT_LENGTH 11
-#define BLONGCFOF_LENGTH 11
-#define BTAILCFO 0x1fff
-#define BTAILCFOT_LENGTH 13
-#define BTAILCFOF_LENGTH 12
-#define BNOISE_EN_PWDB 0xffff
-#define BCC_POWER_DB 0xffff0000
-#define BMOISE_PWDB 0xffff
-#define BPOWERMEAST_LENGTH 10
-#define BPOWERMEASF_LENGTH 3
-#define BRX_HT_BW 0x1
-#define BRXSC 0x6
-#define BRX_HT 0x8
-#define BNB_INTF_DET_ON 0x1
-#define BINTF_WIN_LEN_CFG 0x30
-#define BNB_INTF_TH_CFG 0x1c0
-#define BRFGAIN 0x3f
-#define BTABLESEL 0x40
-#define BTRSW 0x80
-#define BRXSNR_A 0xff
-#define BRXSNR_B 0xff00
-#define BRXSNR_C 0xff0000
-#define BRXSNR_D 0xff000000
-#define BSNR_EVMT_LENGTH 8
-#define BSNR_EVMF_LENGTH 1
-#define BCSI1ST 0xff
-#define BCSI2ND 0xff00
-#define BRXEVM1ST 0xff0000
-#define BRXEVM2ND 0xff000000
-#define BSIGEVM 0xff
-#define BPWDB 0xff00
-#define BSGIEN 0x10000
-
-#define BSFACTOR_QMA1 0xf
-#define BSFACTOR_QMA2 0xf0
-#define BSFACTOR_QMA3 0xf00
-#define BSFACTOR_QMA4 0xf000
-#define BSFACTOR_QMA5 0xf0000
-#define BSFACTOR_QMA6 0xf0000
-#define BSFACTOR_QMA7 0xf00000
-#define BSFACTOR_QMA8 0xf000000
-#define BSFACTOR_QMA9 0xf0000000
-#define BCSI_SCHEME 0x100000
-
-#define BNOISE_LVL_TOP_SET 0x3
-#define BCHSMOOTH 0x4
-#define BCHSMOOTH_CFG1 0x38
-#define BCHSMOOTH_CFG2 0x1c0
-#define BCHSMOOTH_CFG3 0xe00
-#define BCHSMOOTH_CFG4 0x7000
-#define BMRCMODE 0x800000
-#define BTHEVMCFG 0x7000000
-
-#define BLOOP_FIT_TYPE 0x1
-#define BUPD_CFO 0x40
-#define BUPD_CFO_OFFDATA 0x80
-#define BADV_UPD_CFO 0x100
-#define BADV_TIME_CTRL 0x800
-#define BUPD_CLKO 0x1000
-#define BFC 0x6000
-#define BTRACKING_MODE 0x8000
-#define BPHCMP_ENABLE 0x10000
-#define BUPD_CLKO_LTF 0x20000
-#define BCOM_CH_CFO 0x40000
-#define BCSI_ESTI_MODE 0x80000
-#define BADV_UPD_EQZ 0x100000
-#define BUCHCFG 0x7000000
-#define BUPDEQZ 0x8000000
-
-#define BRX_PESUDO_NOISE_ON 0x20000000
-#define BRX_PESUDO_NOISE_A 0xff
-#define BRX_PESUDO_NOISE_B 0xff00
-#define BRX_PESUDO_NOISE_C 0xff0000
-#define BRX_PESUDO_NOISE_D 0xff000000
-#define BRX_PESUDO_NOISESTATE_A 0xffff
-#define BRX_PESUDO_NOISESTATE_B 0xffff0000
-#define BRX_PESUDO_NOISESTATE_C 0xffff
-#define BRX_PESUDO_NOISESTATE_D 0xffff0000
-
-#define BZEBRA1_HSSIENABLE 0x8
-#define BZEBRA1_TRXCONTROL 0xc00
-#define BZEBRA1_TRXGAINSETTING 0x07f
-#define BZEBRA1_RXCOUNTER 0xc00
-#define BZEBRA1_TXCHANGEPUMP 0x38
-#define BZEBRA1_RXCHANGEPUMP 0x7
-#define BZEBRA1_CHANNEL_NUM 0xf80
-#define BZEBRA1_TXLPFBW 0x400
-#define BZEBRA1_RXLPFBW 0x600
-
-#define BRTL8256REG_MODE_CTRL1 0x100
-#define BRTL8256REG_MODE_CTRL0 0x40
-#define BRTL8256REG_TXLPFBW 0x18
-#define BRTL8256REG_RXLPFBW 0x600
-
-#define BRTL8258_TXLPFBW 0xc
-#define BRTL8258_RXLPFBW 0xc00
-#define BRTL8258_RSSILPFBW 0xc0
-
-#define BBYTE0 0x1
-#define BBYTE1 0x2
-#define BBYTE2 0x4
-#define BBYTE3 0x8
-#define BWORD0 0x3
-#define BWORD1 0xc
-#define BWORD 0xf
-
-#define MASKBYTE0 0xff
-#define MASKBYTE1 0xff00
-#define MASKBYTE2 0xff0000
-#define MASKBYTE3 0xff000000
-#define MASKHWORD 0xffff0000
-#define MASKLWORD 0x0000ffff
-#define MASKDWORD 0xffffffff
-#define MASK12BITS 0xfff
-#define MASKH4BITS 0xf0000000
-#define MASKOFDM_D 0xffc00000
-#define MASKCCK 0x3f3f3f3f
-
-#define MASK4BITS 0x0f
-#define MASK20BITS 0xfffff
-#define RFREG_OFFSET_MASK 0xfffff
-
-#define BMASKBYTE0 0xff
-#define BMASKBYTE1 0xff00
-#define BMASKBYTE2 0xff0000
-#define BMASKBYTE3 0xff000000
-#define BMASKHWORD 0xffff0000
-#define BMASKLWORD 0x0000ffff
-#define BMASKDWORD 0xffffffff
-#define BMASK12BITS 0xfff
-#define BMASKH4BITS 0xf0000000
-#define BMASKOFDM_D 0xffc00000
-#define BMASKCCK 0x3f3f3f3f
-
-#define BRFREGOFFSETMASK 0xfffff
-
-/* WOL bit information */
-#define WOL_REASON_PTK_UPDATE BIT(0)
-#define WOL_REASON_GTK_UPDATE BIT(1)
-#define WOL_REASON_DISASSOC BIT(2)
-#define WOL_REASON_DEAUTH BIT(3)
-#define WOL_REASON_FW_DISCONNECT BIT(4)
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../wifi.h"
-#include "../core.h"
-#include "../pci.h"
-#include "../base.h"
-#include "reg.h"
-#include "def.h"
-#include "phy.h"
-#include "hw.h"
-#include "sw.h"
-#include "fw.h"
-#include "trx.h"
-#include "led.h"
-#include "../btcoexist/rtl_btc.h"
-#include "../halmac/rtl_halmac.h"
-#include "../phydm/rtl_phydm.h"
-#include <linux/vmalloc.h>
-#include <linux/module.h>
-
-static void rtl8822be_init_aspm_vars(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
-
- /*close ASPM for AMD defaultly */
- rtlpci->const_amdpci_aspm = 0;
-
- /*
- * ASPM PS mode.
- * 0 - Disable ASPM,
- * 1 - Enable ASPM without Clock Req,
- * 2 - Enable ASPM with Clock Req,
- * 3 - Always Enable ASPM with Clock Req,
- * 4 - Always Enable ASPM without Clock Req.
- * set default to RTL8822BE:3 RTL8822B:2
- *
- */
- rtlpci->const_pci_aspm = 3;
-
- /*Setting for PCI-E device */
- rtlpci->const_devicepci_aspm_setting = 0x03;
-
- /*Setting for PCI-E bridge */
- rtlpci->const_hostpci_aspm_setting = 0x02;
-
- /*
- * In Hw/Sw Radio Off situation.
- * 0 - Default,
- * 1 - From ASPM setting without low Mac Pwr,
- * 2 - From ASPM setting with low Mac Pwr,
- * 3 - Bus D3
- * set default to RTL8822BE:0 RTL8192SE:2
- */
- rtlpci->const_hwsw_rfoff_d3 = 0;
-
- /*
- * This setting works for those device with
- * backdoor ASPM setting such as EPHY setting.
- * 0 - Not support ASPM,
- * 1 - Support ASPM,
- * 2 - According to chipset.
- */
- rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
-}
-
-int rtl8822be_init_sw_vars(struct ieee80211_hw *hw)
-{
- int err = 0;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- const char *fw_name;
- struct rtl_phydm_params params;
-
- rtl8822be_bt_reg_init(hw);
- rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
- rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
- rtlpriv->halmac.ops = rtl_halmac_get_ops_pointer();
- rtlpriv->halmac.ops->halmac_init_adapter(rtlpriv);
-
- /* should after halmac_init_adapter() */
- rtl8822be_read_eeprom_info(hw, ¶ms);
-
- /* need eeprom info */
- rtlpriv->phydm.ops = rtl_phydm_get_ops_pointer();
- rtlpriv->phydm.ops->phydm_init_priv(rtlpriv, ¶ms);
-
- rtlpriv->dm.dm_initialgain_enable = 1;
- rtlpriv->dm.dm_flag = 0;
- rtlpriv->dm.disable_framebursting = 0;
- /*rtlpriv->dm.thermalvalue = 0;*/
- rtlpriv->dm.useramask = 1; /* turn on RA */
- rtlpci->transmit_config = CFENDFORM | BIT(15);
-
- rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
- /*following 2 is for register 5G band, refer to _rtl_init_mac80211()*/
- rtlpriv->rtlhal.bandset = BAND_ON_BOTH;
- rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
-
- rtlpci->receive_config = (RCR_APPFCS |
- RCR_APP_MIC |
- RCR_APP_ICV |
- RCR_APP_PHYST_RXFF |
- RCR_VHT_DACK |
- RCR_HTC_LOC_CTRL |
- /*RCR_AMF |*/
- RCR_CBSSID_BCN |
- RCR_CBSSID_DATA |
- /*RCR_ACF |*/
- /*RCR_ADF |*/
- /*RCR_AICV |*/
- /*RCR_ACRC32 |*/
- RCR_AB |
- RCR_AM |
- RCR_APM |
- 0);
-
- rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT |
- /*IMR_TBDER |*/
- /*IMR_TBDOK |*/
- /*IMR_BCNDMAINT0 |*/
- IMR_GTINT3 |
- IMR_HSISR_IND_ON_INT |
- IMR_C2HCMD |
- IMR_HIGHDOK |
- IMR_MGNTDOK |
- IMR_BKDOK |
- IMR_BEDOK |
- IMR_VIDOK |
- IMR_VODOK |
- IMR_RDU |
- IMR_ROK |
- 0);
-
- rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | IMR_TXFOVW | 0);
- rtlpci->irq_mask[3] = (u32)(BIT_SETH2CDOK_MASK | 0);
-
- /* for LPS & IPS */
- rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
- rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
- rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
- rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
- if (rtlpriv->cfg->mod_params->disable_watchdog)
- pr_info("watchdog disabled\n");
- rtlpriv->psc.reg_fwctrl_lps = 2;
- rtlpriv->psc.reg_max_lps_awakeintvl = 2;
- /* for ASPM, you can close aspm through
- * set const_support_pciaspm = 0
- */
- rtl8822be_init_aspm_vars(hw);
-
- if (rtlpriv->psc.reg_fwctrl_lps == 1)
- rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
- else if (rtlpriv->psc.reg_fwctrl_lps == 2)
- rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
- else if (rtlpriv->psc.reg_fwctrl_lps == 3)
- rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
-
- /* for early mode */
- rtlpriv->rtlhal.earlymode_enable = false;
-
- /*low power */
- rtlpriv->psc.low_power_enable = false;
-
- /* for firmware buf */
- rtlpriv->rtlhal.pfirmware = vzalloc(0x40000);
- if (!rtlpriv->rtlhal.pfirmware) {
- /*pr_err("Can't alloc buffer for fw\n");*/
- return 1;
- }
-
- /* request fw */
- fw_name = "rtlwifi/rtl8822befw.bin";
-
- rtlpriv->max_fw_size = 0x40000;
- pr_info("Using firmware %s\n", fw_name);
- err = request_firmware_nowait(THIS_MODULE, 1, fw_name, rtlpriv->io.dev,
- GFP_KERNEL, hw, rtl_fw_cb);
- if (err) {
- pr_err("Failed to request firmware!\n");
- return 1;
- }
-
- /* init table of tx power by rate & limit */
- rtl8822be_load_txpower_by_rate(hw);
- rtl8822be_load_txpower_limit(hw);
-
- return 0;
-}
-
-void rtl8822be_deinit_sw_vars(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtlpriv->halmac.ops->halmac_deinit_adapter(rtlpriv);
- rtlpriv->phydm.ops->phydm_deinit_priv(rtlpriv);
-
- if (rtlpriv->rtlhal.pfirmware) {
- vfree(rtlpriv->rtlhal.pfirmware);
- rtlpriv->rtlhal.pfirmware = NULL;
- }
-}
-
-/* get bt coexist status */
-bool rtl8822be_get_btc_status(void)
-{
- return true;
-}
-
-static void rtl8822be_phydm_watchdog(struct ieee80211_hw *hw)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u32 tmp;
-
- tmp = rtl_read_dword(rtlpriv, 0xc00);
- if (tmp & 0xFF000000) { /* Recover 0xC00: 0xF800000C --> 0x0000000C */
- RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
- "found regaddr_c00=%08X\n", tmp);
- tmp &= ~0xFF000000;
- rtl_write_dword(rtlpriv, 0xc00, tmp);
- RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
- "apply regaddr_c00=%08X\n", tmp);
- }
-
- rtlpriv->phydm.ops->phydm_watchdog(rtlpriv);
-}
-
-static struct rtl_hal_ops rtl8822be_hal_ops = {
- .init_sw_vars = rtl8822be_init_sw_vars,
- .deinit_sw_vars = rtl8822be_deinit_sw_vars,
- .read_eeprom_info = rtl8822be_read_eeprom_info_dummy,
- .interrupt_recognized = rtl8822be_interrupt_recognized,
- .hw_init = rtl8822be_hw_init,
- .hw_disable = rtl8822be_card_disable,
- .hw_suspend = rtl8822be_suspend,
- .hw_resume = rtl8822be_resume,
- .enable_interrupt = rtl8822be_enable_interrupt,
- .disable_interrupt = rtl8822be_disable_interrupt,
- .set_network_type = rtl8822be_set_network_type,
- .set_chk_bssid = rtl8822be_set_check_bssid,
- .set_qos = rtl8822be_set_qos,
- .set_bcn_reg = rtl8822be_set_beacon_related_registers,
- .set_bcn_intv = rtl8822be_set_beacon_interval,
- .update_interrupt_mask = rtl8822be_update_interrupt_mask,
- .get_hw_reg = rtl8822be_get_hw_reg,
- .set_hw_reg = rtl8822be_set_hw_reg,
- .update_rate_tbl = rtl8822be_update_hal_rate_tbl,
- .pre_fill_tx_bd_desc = rtl8822be_pre_fill_tx_bd_desc,
- .rx_desc_buff_remained_cnt = rtl8822be_rx_desc_buff_remained_cnt,
- .rx_check_dma_ok = rtl8822be_rx_check_dma_ok,
- .fill_tx_desc = rtl8822be_tx_fill_desc,
- .fill_tx_special_desc = rtl8822be_tx_fill_special_desc,
- .query_rx_desc = rtl8822be_rx_query_desc,
- .radio_onoff_checking = rtl8822be_gpio_radio_on_off_checking,
- .switch_channel = rtl8822be_phy_sw_chnl,
- .set_channel_access = rtl8822be_update_channel_access_setting,
- .set_bw_mode = rtl8822be_phy_set_bw_mode,
- .dm_watchdog = rtl8822be_phydm_watchdog,
- .scan_operation_backup = rtl8822be_phy_scan_operation_backup,
- .set_rf_power_state = rtl8822be_phy_set_rf_power_state,
- .led_control = rtl8822be_led_control,
- .set_desc = rtl8822be_set_desc,
- .get_desc = rtl8822be_get_desc,
- .is_tx_desc_closed = rtl8822be_is_tx_desc_closed,
- .get_available_desc = rtl8822be_get_available_desc,
- .tx_polling = rtl8822be_tx_polling,
- .enable_hw_sec = rtl8822be_enable_hw_security_config,
- .set_key = rtl8822be_set_key,
- .init_sw_leds = rtl8822be_init_sw_leds,
- .get_bbreg = rtl8822be_phy_query_bb_reg,
- .set_bbreg = rtl8822be_phy_set_bb_reg,
- .get_rfreg = rtl8822be_phy_query_rf_reg,
- .set_rfreg = rtl8822be_phy_set_rf_reg,
- .fill_h2c_cmd = rtl8822be_fill_h2c_cmd,
- .set_default_port_id_cmd = rtl8822be_set_default_port_id_cmd,
- .get_btc_status = rtl8822be_get_btc_status,
- .rx_command_packet = rtl8822be_rx_command_packet,
- .c2h_content_parsing = rtl8822be_c2h_content_parsing,
- /* ops for halmac cb */
- .halmac_cb_init_mac_register = rtl8822be_halmac_cb_init_mac_register,
- .halmac_cb_init_bb_rf_register =
- rtl8822be_halmac_cb_init_bb_rf_register,
- .halmac_cb_write_data_rsvd_page =
- rtl8822b_halmac_cb_write_data_rsvd_page,
- .halmac_cb_write_data_h2c = rtl8822b_halmac_cb_write_data_h2c,
- /* ops for phydm cb */
- .get_txpower_index = rtl8822be_get_txpower_index,
- .set_tx_power_index_by_rs = rtl8822be_phy_set_tx_power_index_by_rs,
- .store_tx_power_by_rate = rtl8822be_store_tx_power_by_rate,
- .phy_set_txpower_limit = rtl8822be_phy_set_txpower_limit,
-};
-
-static struct rtl_mod_params rtl8822be_mod_params = {
- .sw_crypto = false,
- .inactiveps = true,
- .swctrl_lps = false,
- .fwctrl_lps = true,
- .msi_support = true,
- .dma64 = false,
- .aspm_support = 1,
- .disable_watchdog = false,
- .debug_level = 0,
- .debug_mask = 0,
-};
-
-static struct rtl_hal_cfg rtl8822be_hal_cfg = {
- .bar_id = 2,
- .write_readback = false,
- .name = "rtl8822be_pci",
- .ops = &rtl8822be_hal_ops,
- .mod_params = &rtl8822be_mod_params,
- .spec_ver = RTL_SPEC_NEW_RATEID | RTL_SPEC_SUPPORT_VHT |
- RTL_SPEC_NEW_FW_C2H,
- .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL_8822B,
- .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN_8822B,
- .maps[SYS_CLK] = REG_SYS_CLK_CTRL_8822B,
- .maps[MAC_RCR_AM] = AM,
- .maps[MAC_RCR_AB] = AB,
- .maps[MAC_RCR_ACRC32] = ACRC32,
- .maps[MAC_RCR_ACF] = ACF,
- .maps[MAC_RCR_AAP] = AAP,
- .maps[MAC_HIMR] = REG_HIMR0_8822B,
- .maps[MAC_HIMRE] = REG_HIMR1_8822B,
-
- .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS_8822B,
-
- .maps[EFUSE_TEST] = REG_LDO_EFUSE_CTRL_8822B,
- .maps[EFUSE_CTRL] = REG_EFUSE_CTRL_8822B,
- .maps[EFUSE_CLK] = 0,
- .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL_8822B,
- .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
- .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
- .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
- .maps[EFUSE_ANA8M] = ANA8M,
- .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
- .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
- .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
- .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
-
- .maps[RWCAM] = REG_CAMCMD_8822B,
- .maps[WCAMI] = REG_CAMWRITE_8822B,
- .maps[RCAMO] = REG_CAMREAD_8822B,
- .maps[CAMDBG] = REG_CAMDBG_8822B,
- .maps[SECR] = REG_SECCFG_8822B,
- .maps[SEC_CAM_NONE] = CAM_NONE,
- .maps[SEC_CAM_WEP40] = CAM_WEP40,
- .maps[SEC_CAM_TKIP] = CAM_TKIP,
- .maps[SEC_CAM_AES] = CAM_AES,
- .maps[SEC_CAM_WEP104] = CAM_WEP104,
-
- .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
- .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
- .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
- .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
- .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
- .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
- /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
- .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
- .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
- .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
- .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
- .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
- .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
- .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
- /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
- /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
-
- .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
- .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
- .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
- .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
- .maps[RTL_IMR_RDU] = IMR_RDU,
- .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
- .maps[RTL_IMR_H2CDOK] = IMR_H2CDOK,
- .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
- .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
- .maps[RTL_IMR_TBDER] = IMR_TBDER,
- .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
- .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
- .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
- .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
- .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
- .maps[RTL_IMR_VODOK] = IMR_VODOK,
- .maps[RTL_IMR_ROK] = IMR_ROK,
- .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
-
- .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
- .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
- .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
- .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
- .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
- .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
- .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
- .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
- .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
- .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
- .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
- .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
-
- .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
- .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
-
- /*VHT hightest rate*/
- .maps[RTL_RC_VHT_RATE_1SS_MCS7] = DESC_RATEVHT1SS_MCS7,
- .maps[RTL_RC_VHT_RATE_1SS_MCS8] = DESC_RATEVHT1SS_MCS8,
- .maps[RTL_RC_VHT_RATE_1SS_MCS9] = DESC_RATEVHT1SS_MCS9,
- .maps[RTL_RC_VHT_RATE_2SS_MCS7] = DESC_RATEVHT2SS_MCS7,
- .maps[RTL_RC_VHT_RATE_2SS_MCS8] = DESC_RATEVHT2SS_MCS8,
- .maps[RTL_RC_VHT_RATE_2SS_MCS9] = DESC_RATEVHT2SS_MCS9,
-};
-
-static const struct pci_device_id rtl8822be_pci_ids[] = {
- {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xB822, rtl8822be_hal_cfg)},
- {},
-};
-
-MODULE_DEVICE_TABLE(pci, rtl8822be_pci_ids);
-
-MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
-MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Realtek 8822BE 802.11n PCI wireless");
-MODULE_FIRMWARE("rtlwifi/rtl8822befw.bin");
-
-module_param_named(swenc, rtl8822be_mod_params.sw_crypto, bool, 0444);
-module_param_named(debug_level, rtl8822be_mod_params.debug_level, int, 0644);
-module_param_named(debug_mask, rtl8822be_mod_params.debug_mask, ullong, 0644);
-module_param_named(ips, rtl8822be_mod_params.inactiveps, bool, 0444);
-module_param_named(swlps, rtl8822be_mod_params.swctrl_lps, bool, 0444);
-module_param_named(fwlps, rtl8822be_mod_params.fwctrl_lps, bool, 0444);
-module_param_named(msi, rtl8822be_mod_params.msi_support, bool, 0444);
-module_param_named(dma64, rtl8822be_mod_params.dma64, bool, 0444);
-module_param_named(aspm, rtl8822be_mod_params.aspm_support, int, 0444);
-module_param_named(disable_watchdog, rtl8822be_mod_params.disable_watchdog,
- bool, 0444);
-MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
-MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
-MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
-MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
-MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
-MODULE_PARM_DESC(dma64, "Set to 1 to use DMA 64 (default 0)\n");
-MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
-MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
-MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
-MODULE_PARM_DESC(disable_watchdog,
- "Set to 1 to disable the watchdog (default 0)\n");
-
-static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
-
-static struct pci_driver rtl8822be_driver = {
- .name = KBUILD_MODNAME,
- .id_table = rtl8822be_pci_ids,
- .probe = rtl_pci_probe,
- .remove = rtl_pci_disconnect,
- .driver.pm = &rtlwifi_pm_ops,
-};
-
-module_pci_driver(rtl8822be_driver);
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL8822B_SW_H__
-#define __RTL8822B_SW_H__
-
-int rtl8822be_init_sw_vars(struct ieee80211_hw *hw);
-void rtl8822be_deinit_sw_vars(struct ieee80211_hw *hw);
-bool rtl8822be_get_btc_status(void);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#include "../wifi.h"
-#include "../pci.h"
-#include "../base.h"
-#include "../stats.h"
-#include "reg.h"
-#include "def.h"
-#include "phy.h"
-#include "trx.h"
-#include "led.h"
-#include "fw.h"
-
-#include <linux/vermagic.h>
-
-static u8 _rtl8822be_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
-{
- switch (hw_queue) {
- case BEACON_QUEUE:
- return QSLT_BEACON;
- case H2C_QUEUE:
- return QSLT_CMD;
- case MGNT_QUEUE:
- return QSLT_MGNT;
- case HIGH_QUEUE:
- return QSLT_HIGH;
- default:
- return skb->priority;
- }
-}
-
-static void _rtl8822be_query_rxphystatus(struct ieee80211_hw *hw, u8 *phystrpt,
- struct ieee80211_hdr *hdr,
- struct rtl_stats *pstatus)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtlpriv->phydm.ops->phydm_query_phy_status(rtlpriv, phystrpt, hdr,
- pstatus);
-
- /* UI BSS List signal strength(in percentage),
- * make it good looking, from 0~100.
- */
- pstatus->signalstrength =
- (u8)(rtl_signal_scale_mapping(hw, pstatus->rx_pwdb_all));
-}
-
-static void _rtl8822be_translate_rx_signal_stuff(struct ieee80211_hw *hw,
- struct sk_buff *skb,
- struct rtl_stats *pstatus,
- u8 *p_phystrpt)
-{
- struct ieee80211_hdr *hdr;
- u8 *tmp_buf;
-
- tmp_buf = skb->data + pstatus->rx_drvinfo_size + pstatus->rx_bufshift +
- 24;
-
- hdr = (struct ieee80211_hdr *)tmp_buf;
-
- /* query phy status */
- _rtl8822be_query_rxphystatus(hw, p_phystrpt, hdr, pstatus);
-
- /* packet statistics */
- if (pstatus->packet_beacon && pstatus->packet_matchbssid)
- rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;
-
- if (pstatus->packet_matchbssid &&
- ieee80211_is_data_qos(hdr->frame_control) &&
- !is_multicast_ether_addr(ieee80211_get_DA(hdr))) {
- struct ieee80211_qos_hdr *hdr_qos =
- (struct ieee80211_qos_hdr *)tmp_buf;
- u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf;
-
- if (tid != 0 && tid != 3)
- rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++;
- }
-
- /* signal statistics */
- if (p_phystrpt)
- rtl_process_phyinfo(hw, tmp_buf, pstatus);
-}
-
-static void _rtl8822be_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
- u8 *virtualaddress)
-{
- u32 dwtmp = 0;
-
- memset(virtualaddress, 0, 8);
-
- SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
- if (ptcb_desc->empkt_num == 1) {
- dwtmp = ptcb_desc->empkt_len[0];
- } else {
- dwtmp = ptcb_desc->empkt_len[0];
- dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
- dwtmp += ptcb_desc->empkt_len[1];
- }
- SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
-
- if (ptcb_desc->empkt_num <= 3) {
- dwtmp = ptcb_desc->empkt_len[2];
- } else {
- dwtmp = ptcb_desc->empkt_len[2];
- dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
- dwtmp += ptcb_desc->empkt_len[3];
- }
- SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
- if (ptcb_desc->empkt_num <= 5) {
- dwtmp = ptcb_desc->empkt_len[4];
- } else {
- dwtmp = ptcb_desc->empkt_len[4];
- dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
- dwtmp += ptcb_desc->empkt_len[5];
- }
- SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
- SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
- if (ptcb_desc->empkt_num <= 7) {
- dwtmp = ptcb_desc->empkt_len[6];
- } else {
- dwtmp = ptcb_desc->empkt_len[6];
- dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
- dwtmp += ptcb_desc->empkt_len[7];
- }
- SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
- if (ptcb_desc->empkt_num <= 9) {
- dwtmp = ptcb_desc->empkt_len[8];
- } else {
- dwtmp = ptcb_desc->empkt_len[8];
- dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
- dwtmp += ptcb_desc->empkt_len[9];
- }
- SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
-}
-
-static bool rtl8822be_get_rxdesc_is_ht(struct ieee80211_hw *hw, u8 *pdesc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 rx_rate = 0;
-
- rx_rate = GET_RX_DESC_RX_RATE(pdesc);
-
- RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD, "rx_rate=0x%02x.\n", rx_rate);
-
- if (rx_rate >= DESC_RATEMCS0 && rx_rate <= DESC_RATEMCS15)
- return true;
- else
- return false;
-}
-
-static bool rtl8822be_get_rxdesc_is_vht(struct ieee80211_hw *hw, u8 *pdesc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 rx_rate = 0;
-
- rx_rate = GET_RX_DESC_RX_RATE(pdesc);
-
- RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD, "rx_rate=0x%02x.\n", rx_rate);
-
- if (rx_rate >= DESC_RATEVHT1SS_MCS0)
- return true;
- else
- return false;
-}
-
-static u8 rtl8822be_get_rx_vht_nss(struct ieee80211_hw *hw, u8 *pdesc)
-{
- u8 rx_rate = 0;
- u8 vht_nss = 0;
-
- rx_rate = GET_RX_DESC_RX_RATE(pdesc);
-
- if (rx_rate >= DESC_RATEVHT1SS_MCS0 &&
- rx_rate <= DESC_RATEVHT1SS_MCS9)
- vht_nss = 1;
- else if ((rx_rate >= DESC_RATEVHT2SS_MCS0) &&
- (rx_rate <= DESC_RATEVHT2SS_MCS9))
- vht_nss = 2;
-
- return vht_nss;
-}
-
-bool rtl8822be_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *status,
- struct ieee80211_rx_status *rx_status, u8 *pdesc,
- struct sk_buff *skb)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 *p_phystrpt = NULL;
- struct ieee80211_hdr *hdr;
-
- u32 phystatus = GET_RX_DESC_PHYST(pdesc);
-
- if (GET_RX_DESC_C2H(pdesc) == 0)
- status->packet_report_type = NORMAL_RX;
- else
- status->packet_report_type = C2H_PACKET;
-
- status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
- status->rx_drvinfo_size =
- (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) * RX_DRV_INFO_SIZE_UNIT;
- status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
- status->icv = (u16)GET_RX_DESC_ICV_ERR(pdesc);
- status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
- status->hwerror = (status->crc | status->icv);
- status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
- status->rate = (u8)GET_RX_DESC_RX_RATE(pdesc);
- status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
- status->isfirst_ampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
- status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
- status->is_ht = rtl8822be_get_rxdesc_is_ht(hw, pdesc);
- status->is_vht = rtl8822be_get_rxdesc_is_vht(hw, pdesc);
- status->vht_nss = rtl8822be_get_rx_vht_nss(hw, pdesc);
- status->is_cck = RX_HAL_IS_CCK_RATE(status->rate);
-
- status->macid = GET_RX_DESC_MACID(pdesc);
- if (GET_RX_DESC_PATTERN_MATCH(pdesc))
- status->wake_match = BIT(2);
- else if (GET_RX_DESC_MAGIC_WAKE(pdesc))
- status->wake_match = BIT(1);
- else if (GET_RX_DESC_UNICAST_WAKE(pdesc))
- status->wake_match = BIT(0);
- else
- status->wake_match = 0;
- if (status->wake_match)
- RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
- "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
- status->wake_match);
- rx_status->freq = hw->conf.chandef.chan->center_freq;
- rx_status->band = hw->conf.chandef.chan->band;
-
- if (phystatus)
- p_phystrpt = (skb->data + status->rx_bufshift + 24);
-
- hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size +
- status->rx_bufshift + 24);
-
- if (status->crc)
- rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
-
- if (status->is_ht)
- rx_status->encoding = RX_ENC_HT;
- if (status->is_vht)
- rx_status->encoding = RX_ENC_VHT;
-
- rx_status->nss = status->vht_nss;
-
- rx_status->flag |= RX_FLAG_MACTIME_START;
-
- /* hw will set status->decrypted true, if it finds the
- * frame is open data frame or mgmt frame.
- */
- /* So hw will not decryption robust management frame
- * for IEEE80211w but still set status->decrypted
- * true, so here we should set it back to undecrypted
- * for IEEE80211w frame, and mac80211 sw will help
- * to decrypt it
- */
- if (status->decrypted) {
- if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
- (ieee80211_has_protected(hdr->frame_control)))
- rx_status->flag |= RX_FLAG_DECRYPTED;
- else
- rx_status->flag &= ~RX_FLAG_DECRYPTED;
- }
-
- /* rate_idx: index of data rate into band's
- * supported rates or MCS index if HT rates
- * are use (RX_FLAG_HT)
- */
- /* Notice: this is diff with windows define */
- rx_status->rate_idx = rtlwifi_rate_mapping(
- hw, status->is_ht, status->is_vht, status->rate);
-
- rx_status->mactime = status->timestamp_low;
-
- _rtl8822be_translate_rx_signal_stuff(hw, skb, status, p_phystrpt);
-
- /* below info. are filled by _rtl8822be_translate_rx_signal_stuff() */
- if (!p_phystrpt)
- goto label_no_physt;
-
- rx_status->signal = status->recvsignalpower;
-
- if (status->rx_packet_bw == HT_CHANNEL_WIDTH_20_40)
- rx_status->bw = RATE_INFO_BW_40;
- else if (status->rx_packet_bw == HT_CHANNEL_WIDTH_80)
- rx_status->bw = RATE_INFO_BW_80;
-
-label_no_physt:
-
- return true;
-}
-
-void rtl8822be_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
- u8 queue_index)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 first_seg;
- u8 last_seg;
- u16 total_len;
- u16 read_cnt = 0;
-
- if (!header_desc)
- return;
-
- do {
- total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
- first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
- last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
-
- if (read_cnt++ > 20) {
- RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
- "RX chk DMA over %d times\n", read_cnt);
- break;
- }
-
- } while (total_len == 0 && first_seg == 0 && last_seg == 0);
-}
-
-u16 rtl8822be_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw, u8 queue_index)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u16 desc_idx_hw = 0, desc_idx_host = 0, remind_cnt = 0;
- u32 tmp_4byte = 0;
-
- u32 rw_mask = 0x1ff;
-
- tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_RXBD_IDX_8822B);
- desc_idx_hw = (u16)((tmp_4byte >> 16) & rw_mask);
- desc_idx_host = (u16)(tmp_4byte & rw_mask);
-
- /* may be no data, donot rx */
- if (desc_idx_hw == desc_idx_host)
- return 0;
-
- remind_cnt =
- (desc_idx_hw > desc_idx_host) ?
- (desc_idx_hw - desc_idx_host) :
- (RX_DESC_NUM_8822BE - (desc_idx_host - desc_idx_hw));
-
- rtlpci->rx_ring[queue_index].next_rx_rp = desc_idx_host;
-
- return remind_cnt;
-}
-
-static u16 get_desc_address_from_queue_index(u16 queue_index)
-{
- /*
- * Note: Access these registers will take a lot of cost.
- */
- u16 desc_address = REG_BEQ_TXBD_IDX_8822B;
-
- switch (queue_index) {
- case BK_QUEUE:
- desc_address = REG_BKQ_TXBD_IDX_8822B;
- break;
- case BE_QUEUE:
- desc_address = REG_BEQ_TXBD_IDX_8822B;
- break;
- case VI_QUEUE:
- desc_address = REG_VIQ_TXBD_IDX_8822B;
- break;
- case VO_QUEUE:
- desc_address = REG_VOQ_TXBD_IDX_8822B;
- break;
- case BEACON_QUEUE:
- desc_address = REG_BEQ_TXBD_IDX_8822B;
- break;
- case H2C_QUEUE:
- desc_address = REG_H2CQ_TXBD_IDX_8822B;
- break;
- case MGNT_QUEUE:
- desc_address = REG_MGQ_TXBD_IDX_8822B;
- break;
- case HIGH_QUEUE:
- desc_address = REG_HI0Q_TXBD_IDX_8822B;
- break;
- case HCCA_QUEUE:
- desc_address = REG_BEQ_TXBD_IDX_8822B;
- break;
- default:
- break;
- }
- return desc_address;
-}
-
-/*free desc that can be used */
-u16 rtl8822be_get_available_desc(struct ieee80211_hw *hw, u8 q_idx)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx];
-
- return calc_fifo_space(ring->cur_tx_rp, ring->cur_tx_wp,
- TX_DESC_NUM_8822B);
-}
-
-void rtl8822be_pre_fill_tx_bd_desc(struct ieee80211_hw *hw, u8 *tx_bd_desc,
- u8 *desc, u8 queue_index,
- struct sk_buff *skb, dma_addr_t data_addr)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- u32 pkt_len = skb->len;
- u16 desc_size = 48; /*tx desc size*/
- u32 psblen = 0;
- u32 total_packet_size = 0;
- u16 current_bd_desc;
- u8 i = 0;
- /*u16 real_desc_size = 0x28;*/
- u16 append_early_mode_size = 0;
- u8 segmentnum = 1 << (RTL8822BE_SEG_NUM + 1);
- dma_addr_t desc_dma_addr;
- bool dma64 = rtlpriv->cfg->mod_params->dma64;
-
- current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp;
-
- total_packet_size = desc_size + pkt_len;
-
- if (rtlpriv->rtlhal.earlymode_enable) {
- if (queue_index < BEACON_QUEUE) {
- append_early_mode_size = 8;
- total_packet_size += append_early_mode_size;
- }
- }
-
- /* page number (round up) */
- psblen = (total_packet_size - 1) / 128 + 1;
-
- /* tx desc addr */
- desc_dma_addr = rtlpci->tx_ring[queue_index].dma +
- (current_bd_desc * TX_DESC_SIZE);
-
- /* Reset */
- SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, 0);
- SET_TX_BUFF_DESC_PSB(tx_bd_desc, 0);
- SET_TX_BUFF_DESC_OWN(tx_bd_desc, 0);
-
- for (i = 1; i < segmentnum; i++) {
- SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, i, 0);
- SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, i, 0);
- SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, i, 0);
- SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(tx_bd_desc, i, 0, dma64);
- }
-
- /* Clear all status */
- CLEAR_PCI_TX_DESC_CONTENT(desc, TX_DESC_SIZE);
-
- if (rtlpriv->rtlhal.earlymode_enable) {
- if (queue_index < BEACON_QUEUE)
- SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size + 8);
- else
- SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
- } else {
- SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
- }
- SET_TX_BUFF_DESC_PSB(tx_bd_desc, psblen);
- SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc, desc_dma_addr);
- SET_TX_BUFF_DESC_ADDR_HIGH_0(tx_bd_desc, ((u64)desc_dma_addr >> 32),
- dma64);
-
- SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, 1, pkt_len);
- SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, 1, 0);
- SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, 1, data_addr);
- SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(tx_bd_desc, 1,
- ((u64)data_addr >> 32), dma64);
-
- SET_TX_DESC_TXPKTSIZE(desc, (u16)(pkt_len));
-}
-
-static u8 rtl8822be_bw_mapping(struct ieee80211_hw *hw,
- struct rtl_tcb_desc *ptcb_desc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 bw_setting_of_desc = 0;
-
- RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
- "%s, current_chan_bw %d, packet_bw %d\n", __func__,
- rtlphy->current_chan_bw, ptcb_desc->packet_bw);
-
- if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
- if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_80)
- bw_setting_of_desc = 2;
- else if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40)
- bw_setting_of_desc = 1;
- else
- bw_setting_of_desc = 0;
- } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
- if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40 ||
- ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_80)
- bw_setting_of_desc = 1;
- else
- bw_setting_of_desc = 0;
- } else {
- bw_setting_of_desc = 0;
- }
-
- return bw_setting_of_desc;
-}
-
-static u8 rtl8822be_sc_mapping(struct ieee80211_hw *hw,
- struct rtl_tcb_desc *ptcb_desc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- struct rtl_mac *mac = rtl_mac(rtlpriv);
- u8 sc_setting_of_desc = 0;
-
- if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
- if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_80) {
- sc_setting_of_desc = VHT_DATA_SC_DONOT_CARE;
- } else if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
- if (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER)
- sc_setting_of_desc =
- VHT_DATA_SC_40_LOWER_OF_80MHZ;
- else if (mac->cur_80_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER)
- sc_setting_of_desc =
- VHT_DATA_SC_40_UPPER_OF_80MHZ;
- else
- RT_TRACE(rtlpriv, COMP_SEND, DBG_LOUD,
- "%s: Not Correct Primary40MHz Setting\n",
- __func__);
- } else {
- if (mac->cur_40_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_LOWER &&
- mac->cur_80_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_LOWER)
- sc_setting_of_desc =
- VHT_DATA_SC_20_LOWEST_OF_80MHZ;
- else if ((mac->cur_40_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER) &&
- (mac->cur_80_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_LOWER))
- sc_setting_of_desc =
- VHT_DATA_SC_20_LOWER_OF_80MHZ;
- else if ((mac->cur_40_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_LOWER) &&
- (mac->cur_80_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER))
- sc_setting_of_desc =
- VHT_DATA_SC_20_UPPER_OF_80MHZ;
- else if ((mac->cur_40_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER) &&
- (mac->cur_80_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER))
- sc_setting_of_desc =
- VHT_DATA_SC_20_UPPERST_OF_80MHZ;
- else
- RT_TRACE(rtlpriv, COMP_SEND, DBG_LOUD,
- "%s: Not Correct Primary40MHz Setting\n",
- __func__);
- }
- } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
- if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
- sc_setting_of_desc = VHT_DATA_SC_DONOT_CARE;
- } else if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20) {
- if (mac->cur_40_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_UPPER) {
- sc_setting_of_desc =
- VHT_DATA_SC_20_UPPER_OF_80MHZ;
- } else if (mac->cur_40_prime_sc ==
- HAL_PRIME_CHNL_OFFSET_LOWER) {
- sc_setting_of_desc =
- VHT_DATA_SC_20_LOWER_OF_80MHZ;
- } else {
- sc_setting_of_desc = VHT_DATA_SC_DONOT_CARE;
- }
- }
- } else {
- sc_setting_of_desc = VHT_DATA_SC_DONOT_CARE;
- }
-
- return sc_setting_of_desc;
-}
-
-void rtl8822be_tx_fill_desc(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
- u8 *pdesc_tx, u8 *pbd_desc_tx,
- struct ieee80211_tx_info *info,
- struct ieee80211_sta *sta, struct sk_buff *skb,
- u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 *pdesc = (u8 *)pdesc_tx;
- u16 seq_number;
- __le16 fc = hdr->frame_control;
- u8 fw_qsel = _rtl8822be_map_hwqueue_to_fwqueue(skb, hw_queue);
- bool firstseg =
- ((hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
- bool lastseg = ((hdr->frame_control &
- cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
- dma_addr_t mapping;
- u8 short_gi = 0;
-
- seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
- rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
- /* reserve 8 byte for AMPDU early mode */
- if (rtlhal->earlymode_enable) {
- skb_push(skb, EM_HDR_LEN);
- memset(skb->data, 0, EM_HDR_LEN);
- }
- mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
- PCI_DMA_TODEVICE);
- if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
- RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "DMA mapping error");
- return;
- }
-
- if (pbd_desc_tx)
- rtl8822be_pre_fill_tx_bd_desc(hw, pbd_desc_tx, pdesc, hw_queue,
- skb, mapping);
-
- if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
- firstseg = true;
- lastseg = true;
- }
- if (firstseg) {
- if (rtlhal->earlymode_enable) {
- SET_TX_DESC_PKT_OFFSET(pdesc, 1);
- SET_TX_DESC_OFFSET(pdesc,
- USB_HWDESC_HEADER_LEN + EM_HDR_LEN);
- if (ptcb_desc->empkt_num) {
- RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
- "Insert 8 byte.pTcb->EMPktNum:%d\n",
- ptcb_desc->empkt_num);
- _rtl8822be_insert_emcontent(ptcb_desc,
- (u8 *)(skb->data));
- }
- } else {
- SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
- }
-
- /* tx report */
- rtl_get_tx_report(ptcb_desc, pdesc, hw);
-
- if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G &&
- ptcb_desc->hw_rate < DESC_RATE6M) {
- RT_TRACE(rtlpriv, COMP_SEND, DBG_WARNING,
- "hw_rate=0x%X is invalid in 5G\n",
- ptcb_desc->hw_rate);
- ptcb_desc->hw_rate = DESC_RATE6M;
- }
- SET_TX_DESC_DATARATE(pdesc, ptcb_desc->hw_rate);
-
- if (ptcb_desc->hw_rate > DESC_RATEMCS0)
- short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
- else
- short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
-
- if (info->flags & IEEE80211_TX_CTL_AMPDU) {
- SET_TX_DESC_AGG_EN(pdesc, 1);
- SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x1F);
- }
- SET_TX_DESC_SW_SEQ(pdesc, seq_number);
- SET_TX_DESC_RTSEN(pdesc, ((ptcb_desc->rts_enable &&
- !ptcb_desc->cts_enable) ?
- 1 :
- 0));
- SET_TX_DESC_HW_RTS_EN(pdesc, 0);
- SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0));
-
- SET_TX_DESC_RTSRATE(pdesc, ptcb_desc->rts_rate);
- SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
- SET_TX_DESC_RTS_SHORT(
- pdesc,
- ((ptcb_desc->rts_rate <= DESC_RATE54M) ?
- (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
- (ptcb_desc->rts_use_shortgi ? 1 : 0)));
-
- if (ptcb_desc->tx_enable_sw_calc_duration)
- SET_TX_DESC_NAVUSEHDR(pdesc, 1);
-
- SET_TX_DESC_DATA_BW(pdesc, rtl8822be_bw_mapping(hw, ptcb_desc));
- SET_TX_DESC_DATA_SC(pdesc, rtl8822be_sc_mapping(hw, ptcb_desc));
-
- if (sta) {
- u8 ampdu_density = sta->ht_cap.ampdu_density;
-
- SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
- }
- if (info->control.hw_key) {
- struct ieee80211_key_conf *key = info->control.hw_key;
-
- switch (key->cipher) {
- case WLAN_CIPHER_SUITE_WEP40:
- case WLAN_CIPHER_SUITE_WEP104:
- case WLAN_CIPHER_SUITE_TKIP:
- SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
- break;
- case WLAN_CIPHER_SUITE_CCMP:
- SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
- break;
- default:
- SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
- break;
- }
- }
-
- SET_TX_DESC_QSEL(pdesc, fw_qsel);
-
- if (rtlphy->current_channel > 14) {
- /* OFDM 6M */
- SET_TX_DESC_DATA_RTY_LOWEST_RATE(pdesc, 4);
- SET_TX_DESC_RTS_RTY_LOWEST_RATE(pdesc, 4);
- } else {
- /* CCK 1M */
- SET_TX_DESC_DATA_RTY_LOWEST_RATE(pdesc, 0);
- SET_TX_DESC_RTS_RTY_LOWEST_RATE(pdesc, 0);
- }
- SET_TX_DESC_DISDATAFB(pdesc,
- ptcb_desc->disable_ratefallback ? 1 : 0);
- SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
-
- /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
- /* Set TxRate and RTSRate in TxDesc */
- /* This prevent Tx initial rate of new-coming packets */
- /* from being overwritten by retried packet rate.*/
- if (!ptcb_desc->use_driver_rate) {
- /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
- /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
- }
- if (ieee80211_is_data_qos(fc)) {
- if (mac->rdg_en) {
- RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
- "Enable RDG function.\n");
- SET_TX_DESC_RDG_EN(pdesc, 1);
- SET_TX_DESC_HTC(pdesc, 1);
- }
- }
-
- SET_TX_DESC_PORT_ID(pdesc, 0);
- SET_TX_DESC_MULTIPLE_PORT(pdesc, 0);
- }
-
- SET_TX_DESC_LS(pdesc, (lastseg ? 1 : 0));
- if (rtlpriv->dm.useramask) {
- SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
- SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
- } else {
- SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
- SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
- }
-
- SET_TX_DESC_MOREFRAG(pdesc, (lastseg ? 0 : 1));
- if (ptcb_desc->multicast || ptcb_desc->broadcast) {
- SET_TX_DESC_BMC(pdesc, 1);
- /* BMC must be not AGG */
- SET_TX_DESC_AGG_EN(pdesc, 0);
- }
- RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
-
- /* debug purpose: used to check tx desc is correct or not */
- /*rtlpriv->halmac.ops->halmac_chk_txdesc(rtlpriv, pdesc,
- * skb->len + USB_HWDESC_HEADER_LEN);
- */
-}
-
-void rtl8822be_tx_fill_special_desc(struct ieee80211_hw *hw, u8 *pdesc,
- u8 *pbd_desc, struct sk_buff *skb,
- u8 hw_queue)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- u8 fw_queue;
- u8 txdesc_len = 48;
-
- dma_addr_t mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
- PCI_DMA_TODEVICE);
-
- if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
- RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "DMA mapping error");
- return;
- }
-
- rtl8822be_pre_fill_tx_bd_desc(hw, pbd_desc, pdesc, hw_queue, skb,
- mapping);
-
- /* it should be BEACON_QUEUE or H2C_QUEUE,
- * so skb=NULL is safe to assert
- */
- fw_queue = _rtl8822be_map_hwqueue_to_fwqueue(NULL, hw_queue);
-
- CLEAR_PCI_TX_DESC_CONTENT(pdesc, txdesc_len);
-
- /* common part for BEACON and H2C */
- SET_TX_DESC_TXPKTSIZE((u8 *)pdesc, (u16)(skb->len));
-
- SET_TX_DESC_QSEL(pdesc, fw_queue);
-
- if (hw_queue == H2C_QUEUE) {
- /* fill H2C */
- SET_TX_DESC_OFFSET(pdesc, 0);
-
- } else {
- /* fill beacon */
- SET_TX_DESC_OFFSET(pdesc, txdesc_len);
-
- SET_TX_DESC_DATARATE(pdesc, DESC_RATE1M);
-
- SET_TX_DESC_SW_SEQ(pdesc, 0);
-
- SET_TX_DESC_RATE_ID(pdesc, 7);
- SET_TX_DESC_MACID(pdesc, 0);
-
- SET_TX_DESC_LS(pdesc, 1);
-
- SET_TX_DESC_OFFSET(pdesc, 48);
-
- SET_TX_DESC_USE_RATE(pdesc, 1);
- }
-
- RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, "H2C Tx Cmd Content\n",
- pdesc, txdesc_len);
-}
-
-void rtl8822be_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
- u8 desc_name, u8 *val)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u8 q_idx = *val;
- bool dma64 = rtlpriv->cfg->mod_params->dma64;
-
- if (istx) {
- switch (desc_name) {
- case HW_DESC_OWN: {
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx];
- u16 max_tx_desc = ring->entries;
-
- if (q_idx == BEACON_QUEUE) {
- /* in case of beacon, pdesc is BD desc. */
- u8 *pbd_desc = pdesc;
-
- ring->cur_tx_wp = 0;
- ring->cur_tx_rp = 0;
- SET_TX_BUFF_DESC_OWN(pbd_desc, 1);
- return;
- }
-
- /* make sure tx desc is available by caller */
- ring->cur_tx_wp = ((ring->cur_tx_wp + 1) % max_tx_desc);
-
- rtl_write_word(
- rtlpriv,
- get_desc_address_from_queue_index(
- q_idx),
- ring->cur_tx_wp);
- } break;
- }
- } else {
- switch (desc_name) {
- case HW_DESC_RX_PREPARE:
- SET_RX_BUFFER_DESC_LS(pdesc, 0);
- SET_RX_BUFFER_DESC_FS(pdesc, 0);
- SET_RX_BUFFER_DESC_TOTAL_LENGTH(pdesc, 0);
-
- SET_RX_BUFFER_DESC_DATA_LENGTH(
- pdesc, MAX_RECEIVE_BUFFER_SIZE + RX_DESC_SIZE);
-
- SET_RX_BUFFER_PHYSICAL_LOW(
- pdesc, (*(dma_addr_t *)val) & DMA_BIT_MASK(32));
- SET_RX_BUFFER_PHYSICAL_HIGH(
- pdesc, ((u64)(*(dma_addr_t *)val) >> 32),
- dma64);
- break;
- default:
- WARN_ONCE(true, "ERR rxdesc :%d not process\n",
- desc_name);
- break;
- }
- }
-}
-
-u64 rtl8822be_get_desc(struct ieee80211_hw *hw,
- u8 *pdesc, bool istx, u8 desc_name)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u64 ret = 0;
- u8 *pbd_desc = pdesc;
- bool dma64 = rtlpriv->cfg->mod_params->dma64;
-
- if (istx) {
- switch (desc_name) {
- case HW_DESC_TXBUFF_ADDR:
- ret = GET_TXBUFFER_DESC_ADDR_LOW(pbd_desc, 1);
- ret |= (u64)GET_TXBUFFER_DESC_ADDR_HIGH(pbd_desc, 1,
- dma64) << 32;
- break;
- default:
- WARN_ONCE(true, "ERR txdesc :%d not process\n",
- desc_name);
- break;
- }
- } else {
- switch (desc_name) {
- case HW_DESC_RXPKT_LEN:
- ret = GET_RX_DESC_PKT_LEN(pdesc);
- break;
- default:
- WARN_ONCE(true, "ERR rxdesc :%d not process\n",
- desc_name);
- break;
- }
- }
- return ret;
-}
-
-bool rtl8822be_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
- u16 index)
-{
- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- bool ret = false;
- struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
- u16 cur_tx_rp, cur_tx_wp;
- u16 tmp16;
-
- /*
- * design rule:
- * idx <= cur_tx_rp <= hw_rp <= cur_tx_wp = hw_wp
- */
-
- if (index == ring->cur_tx_rp) {
- /* update only if sw_rp reach hw_rp */
- tmp16 = rtl_read_word(
- rtlpriv,
- get_desc_address_from_queue_index(hw_queue) + 2);
-
- cur_tx_rp = tmp16 & 0x01ff;
- cur_tx_wp = ring->cur_tx_wp;
-
- /* don't need to update ring->cur_tx_wp */
- ring->cur_tx_rp = cur_tx_rp;
- }
-
- if (index == ring->cur_tx_rp)
- ret = false; /* no more */
- else
- ret = true; /* more */
-
- if (hw_queue == BEACON_QUEUE)
- ret = true;
-
- if (rtlpriv->rtlhal.driver_is_goingto_unload ||
- rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS)
- ret = true;
-
- return ret;
-}
-
-void rtl8822be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- if (hw_queue == BEACON_QUEUE) {
- /* kick start */
- rtl_write_byte(
- rtlpriv, REG_RX_RXBD_NUM_8822B + 1,
- rtl_read_byte(rtlpriv, REG_RX_RXBD_NUM_8822B + 1) |
- BIT(4));
- }
-}
-
-u32 rtl8822be_rx_command_packet(struct ieee80211_hw *hw,
- const struct rtl_stats *status,
- struct sk_buff *skb)
-{
- u32 result = 0;
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- switch (status->packet_report_type) {
- case NORMAL_RX:
- result = 0;
- break;
- case C2H_PACKET:
- rtl8822be_c2h_packet_handler(hw, skb->data, (u8)skb->len);
- result = 1;
- break;
- default:
- RT_TRACE(rtlpriv, COMP_RECV, DBG_TRACE,
- "Unknown packet type %d\n",
- status->packet_report_type);
- break;
- }
-
- return result;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2016 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL8822B_TRX_H__
-#define __RTL8822B_TRX_H__
-
-#include "../halmac/halmac_tx_desc_nic.h"
-#include "../halmac/halmac_rx_desc_nic.h"
-
-#define TX_DESC_SIZE 64
-
-#define RX_DRV_INFO_SIZE_UNIT 8
-
-#define TX_DESC_NEXT_DESC_OFFSET 48
-#define USB_HWDESC_HEADER_LEN 48
-
-#define RX_DESC_SIZE 24
-#define MAX_RECEIVE_BUFFER_SIZE 8192
-
-#define SET_EARLYMODE_PKTNUM(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __val)
-#define SET_EARLYMODE_LEN0(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr, 4, 15, __val)
-#define SET_EARLYMODE_LEN1(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr, 16, 2, __val)
-#define SET_EARLYMODE_LEN1_1(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr, 19, 13, __val)
-#define SET_EARLYMODE_LEN1_2(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr + 4, 0, 2, __val)
-#define SET_EARLYMODE_LEN2(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr + 4, 2, 15, __val)
-#define SET_EARLYMODE_LEN2_1(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr, 2, 4, __val)
-#define SET_EARLYMODE_LEN2_2(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr + 4, 0, 8, __val)
-#define SET_EARLYMODE_LEN3(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr + 4, 17, 15, __val)
-#define SET_EARLYMODE_LEN4(__paddr, __val) \
- SET_BITS_TO_LE_4BYTE(__paddr + 4, 20, 12, __val)
-
-/* TX/RX buffer descriptor */
-
-/* for Txfilldescroptor8822be, fill the desc content. */
-#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
- SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16), 0, 16, __val)
-#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
- SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16), 31, 1, __val)
-#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
- SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16) + 4, 0, 32, __val)
-#define SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(pbd, off, val, dma64) \
- (dma64 ? SET_BITS_TO_LE_4BYTE((pbd) + ((off) * 16) + 8, 0, 32, val) : 0)
-#define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
- LE_BITS_TO_4BYTE((__pdesc) + ((__offset) * 16) + 4, 0, 32)
-#define GET_TXBUFFER_DESC_ADDR_HIGH(pbd, off, dma64) \
- (dma64 ? LE_BITS_TO_4BYTE((pbd) + ((off) * 16) + 8, 0, 32) : 0)
-
-/* Dword 0 */
-#define SET_TX_BUFF_DESC_LEN_0(__pdesc, __val) \
- SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
-#define SET_TX_BUFF_DESC_PSB(__pdesc, __val) \
- SET_BITS_TO_LE_4BYTE(__pdesc, 16, 15, __val)
-#define SET_TX_BUFF_DESC_OWN(__pdesc, __val) \
- SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
-
-/* Dword 1 */
-#define SET_TX_BUFF_DESC_ADDR_LOW_0(__pdesc, __val) \
- SET_BITS_TO_LE_4BYTE((__pdesc) + 4, 0, 32, __val)
-/* Dword 2 */
-#define SET_TX_BUFF_DESC_ADDR_HIGH_0(bdesc, val, dma64) \
- SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(bdesc, 0, val, dma64)
-/* Dword 3 / RESERVED 0 */
-
-/* RX buffer */
-
-/* DWORD 0 */
-#define SET_RX_BUFFER_DESC_DATA_LENGTH(__rx_status_desc, __val) \
- SET_BITS_TO_LE_4BYTE(__rx_status_desc, 0, 14, __val)
-#define SET_RX_BUFFER_DESC_LS(__rx_status_desc, __val) \
- SET_BITS_TO_LE_4BYTE(__rx_status_desc, 15, 1, __val)
-#define SET_RX_BUFFER_DESC_FS(__rx_status_desc, __val) \
- SET_BITS_TO_LE_4BYTE(__rx_status_desc, 16, 1, __val)
-#define SET_RX_BUFFER_DESC_TOTAL_LENGTH(__rx_status_desc, __val) \
- SET_BITS_TO_LE_4BYTE(__rx_status_desc, 16, 15, __val)
-
-#define GET_RX_BUFFER_DESC_OWN(__rx_status_desc) \
- LE_BITS_TO_4BYTE(__rx_status_desc, 31, 1)
-#define GET_RX_BUFFER_DESC_LS(__rx_status_desc) \
- LE_BITS_TO_4BYTE(__rx_status_desc, 15, 1)
-#define GET_RX_BUFFER_DESC_FS(__rx_status_desc) \
- LE_BITS_TO_4BYTE(__rx_status_desc, 16, 1)
-#define GET_RX_BUFFER_DESC_TOTAL_LENGTH(__rx_status_desc) \
- LE_BITS_TO_4BYTE(__rx_status_desc, 16, 15)
-
-/* DWORD 1 */
-#define SET_RX_BUFFER_PHYSICAL_LOW(__rx_status_desc, __val) \
- SET_BITS_TO_LE_4BYTE(__rx_status_desc + 4, 0, 32, __val)
-
-/* DWORD 2 */
-#define SET_RX_BUFFER_PHYSICAL_HIGH(__rx_status_desc, __val, dma64) \
- (dma64 ? SET_BITS_TO_LE_4BYTE((__rx_status_desc) + 8, 0, 32, __val) : 0)
-
-#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
- do { \
- if (_size > TX_DESC_NEXT_DESC_OFFSET) \
- memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
- else \
- memset(__pdesc, 0, _size); \
- } while (0)
-
-void rtl8822be_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
- u8 queue_index);
-u16 rtl8822be_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw,
- u8 queue_index);
-u16 rtl8822be_get_available_desc(struct ieee80211_hw *hw, u8 queue_index);
-void rtl8822be_pre_fill_tx_bd_desc(struct ieee80211_hw *hw, u8 *tx_bd_desc,
- u8 *desc, u8 queue_index,
- struct sk_buff *skb, dma_addr_t addr);
-
-void rtl8822be_tx_fill_desc(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
- u8 *pdesc_tx, u8 *pbd_desc_tx,
- struct ieee80211_tx_info *info,
- struct ieee80211_sta *sta, struct sk_buff *skb,
- u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
-void rtl8822be_tx_fill_special_desc(struct ieee80211_hw *hw, u8 *pdesc,
- u8 *pbd_desc, struct sk_buff *skb,
- u8 hw_queue);
-bool rtl8822be_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *status,
- struct ieee80211_rx_status *rx_status, u8 *pdesc,
- struct sk_buff *skb);
-void rtl8822be_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
- u8 desc_name, u8 *val);
-u64 rtl8822be_get_desc(struct ieee80211_hw *hw,
- u8 *pdesc, bool istx, u8 desc_name);
-bool rtl8822be_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
- u16 index);
-void rtl8822be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
-void rtl8822be_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
- bool firstseg, bool lastseg,
- struct sk_buff *skb);
-u32 rtl8822be_rx_command_packet(struct ieee80211_hw *hw,
- const struct rtl_stats *status,
- struct sk_buff *skb);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-#include "wifi.h"
-#include "stats.h"
-#include <linux/export.h>
-
-u8 rtl_query_rxpwrpercentage(s8 antpower)
-{
- if ((antpower <= -100) || (antpower >= 20))
- return 0;
- else if (antpower >= 0)
- return 100;
- else
- return 100 + antpower;
-}
-
-u8 rtl_evm_db_to_percentage(s8 value)
-{
- s8 ret_val = clamp(-value, 0, 33) * 3;
-
- if (ret_val == 99)
- ret_val = 100;
-
- return ret_val;
-}
-
-static long rtl_translate_todbm(struct ieee80211_hw *hw,
- u8 signal_strength_index)
-{
- long signal_power;
-
- signal_power = (long)((signal_strength_index + 1) >> 1);
- signal_power -= 95;
- return signal_power;
-}
-
-long rtl_signal_scale_mapping(struct ieee80211_hw *hw, long currsig)
-{
- long retsig;
-
- if (currsig >= 61 && currsig <= 100)
- retsig = 90 + ((currsig - 60) / 4);
- else if (currsig >= 41 && currsig <= 60)
- retsig = 78 + ((currsig - 40) / 2);
- else if (currsig >= 31 && currsig <= 40)
- retsig = 66 + (currsig - 30);
- else if (currsig >= 21 && currsig <= 30)
- retsig = 54 + (currsig - 20);
- else if (currsig >= 5 && currsig <= 20)
- retsig = 42 + (((currsig - 5) * 2) / 3);
- else if (currsig == 4)
- retsig = 36;
- else if (currsig == 3)
- retsig = 27;
- else if (currsig == 2)
- retsig = 18;
- else if (currsig == 1)
- retsig = 9;
- else
- retsig = currsig;
-
- return retsig;
-}
-
-static void rtl_process_ui_rssi(struct ieee80211_hw *hw,
- struct rtl_stats *pstatus)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_phy *rtlphy = &rtlpriv->phy;
- u8 rfpath;
- u32 last_rssi, tmpval;
-
- if (!pstatus->packet_toself && !pstatus->packet_beacon)
- return;
-
- rtlpriv->stats.pwdb_all_cnt += pstatus->rx_pwdb_all;
- rtlpriv->stats.rssi_calculate_cnt++;
-
- if (rtlpriv->stats.ui_rssi.total_num++ >= PHY_RSSI_SLID_WIN_MAX) {
- rtlpriv->stats.ui_rssi.total_num = PHY_RSSI_SLID_WIN_MAX;
- last_rssi = rtlpriv->stats.ui_rssi.elements[
- rtlpriv->stats.ui_rssi.index];
- rtlpriv->stats.ui_rssi.total_val -= last_rssi;
- }
- rtlpriv->stats.ui_rssi.total_val += pstatus->signalstrength;
- rtlpriv->stats.ui_rssi.elements[rtlpriv->stats.ui_rssi.index++] =
- pstatus->signalstrength;
- if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
- rtlpriv->stats.ui_rssi.index = 0;
- tmpval = rtlpriv->stats.ui_rssi.total_val /
- rtlpriv->stats.ui_rssi.total_num;
- rtlpriv->stats.signal_strength = rtl_translate_todbm(hw, (u8)tmpval);
- pstatus->rssi = rtlpriv->stats.signal_strength;
-
- if (pstatus->is_cck)
- return;
-
- for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
- rfpath++) {
- if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
- rtlpriv->stats.rx_rssi_percentage[rfpath] =
- pstatus->rx_mimo_signalstrength[rfpath];
- }
- if (pstatus->rx_mimo_signalstrength[rfpath] >
- rtlpriv->stats.rx_rssi_percentage[rfpath]) {
- rtlpriv->stats.rx_rssi_percentage[rfpath] =
- ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
- (RX_SMOOTH_FACTOR - 1)) +
- (pstatus->rx_mimo_signalstrength[rfpath])) /
- (RX_SMOOTH_FACTOR);
- rtlpriv->stats.rx_rssi_percentage[rfpath] =
- rtlpriv->stats.rx_rssi_percentage[rfpath] + 1;
- } else {
- rtlpriv->stats.rx_rssi_percentage[rfpath] =
- ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
- (RX_SMOOTH_FACTOR - 1)) +
- (pstatus->rx_mimo_signalstrength[rfpath])) /
- (RX_SMOOTH_FACTOR);
- }
- rtlpriv->stats.rx_snr_db[rfpath] = pstatus->rx_snr[rfpath];
- rtlpriv->stats.rx_evm_dbm[rfpath] =
- pstatus->rx_mimo_evm_dbm[rfpath];
- rtlpriv->stats.rx_cfo_short[rfpath] =
- pstatus->cfo_short[rfpath];
- rtlpriv->stats.rx_cfo_tail[rfpath] = pstatus->cfo_tail[rfpath];
- }
-}
-
-static void rtl_update_rxsignalstatistics(struct ieee80211_hw *hw,
- struct rtl_stats *pstatus)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- int weighting = 0;
-
- if (rtlpriv->stats.recv_signal_power == 0)
- rtlpriv->stats.recv_signal_power = pstatus->recvsignalpower;
- if (pstatus->recvsignalpower > rtlpriv->stats.recv_signal_power)
- weighting = 5;
- else if (pstatus->recvsignalpower < rtlpriv->stats.recv_signal_power)
- weighting = (-5);
- rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power *
- 5 + pstatus->recvsignalpower + weighting) / 6;
-}
-
-static void rtl_process_pwdb(struct ieee80211_hw *hw, struct rtl_stats *pstatus)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- struct rtl_sta_info *drv_priv = NULL;
- struct ieee80211_sta *sta = NULL;
- long undec_sm_pwdb;
-
- rcu_read_lock();
- if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
- sta = rtl_find_sta(hw, pstatus->psaddr);
-
- /* adhoc or ap mode */
- if (sta) {
- drv_priv = (struct rtl_sta_info *)sta->drv_priv;
- undec_sm_pwdb = drv_priv->rssi_stat.undec_sm_pwdb;
- } else {
- undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
- }
-
- if (undec_sm_pwdb < 0)
- undec_sm_pwdb = pstatus->rx_pwdb_all;
- if (pstatus->rx_pwdb_all > (u32)undec_sm_pwdb) {
- undec_sm_pwdb = (((undec_sm_pwdb) *
- (RX_SMOOTH_FACTOR - 1)) +
- (pstatus->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
- undec_sm_pwdb = undec_sm_pwdb + 1;
- } else {
- undec_sm_pwdb = (((undec_sm_pwdb) *
- (RX_SMOOTH_FACTOR - 1)) +
- (pstatus->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
- }
-
- if (sta)
- drv_priv->rssi_stat.undec_sm_pwdb = undec_sm_pwdb;
- else
- rtlpriv->dm.undec_sm_pwdb = undec_sm_pwdb;
- rcu_read_unlock();
-
- rtl_update_rxsignalstatistics(hw, pstatus);
-}
-
-static void rtl_process_ui_link_quality(struct ieee80211_hw *hw,
- struct rtl_stats *pstatus)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
- u32 last_evm, n_stream, tmpval;
-
- if (pstatus->signalquality == 0)
- return;
-
- if (rtlpriv->stats.ui_link_quality.total_num++ >=
- PHY_LINKQUALITY_SLID_WIN_MAX) {
- rtlpriv->stats.ui_link_quality.total_num =
- PHY_LINKQUALITY_SLID_WIN_MAX;
- last_evm = rtlpriv->stats.ui_link_quality.elements[
- rtlpriv->stats.ui_link_quality.index];
- rtlpriv->stats.ui_link_quality.total_val -= last_evm;
- }
- rtlpriv->stats.ui_link_quality.total_val += pstatus->signalquality;
- rtlpriv->stats.ui_link_quality.elements[
- rtlpriv->stats.ui_link_quality.index++] =
- pstatus->signalquality;
- if (rtlpriv->stats.ui_link_quality.index >=
- PHY_LINKQUALITY_SLID_WIN_MAX)
- rtlpriv->stats.ui_link_quality.index = 0;
- tmpval = rtlpriv->stats.ui_link_quality.total_val /
- rtlpriv->stats.ui_link_quality.total_num;
- rtlpriv->stats.signal_quality = tmpval;
- rtlpriv->stats.last_sigstrength_inpercent = tmpval;
- for (n_stream = 0; n_stream < 2; n_stream++) {
- if (pstatus->rx_mimo_sig_qual[n_stream] != -1) {
- if (rtlpriv->stats.rx_evm_percentage[n_stream] == 0) {
- rtlpriv->stats.rx_evm_percentage[n_stream] =
- pstatus->rx_mimo_sig_qual[n_stream];
- }
- rtlpriv->stats.rx_evm_percentage[n_stream] =
- ((rtlpriv->stats.rx_evm_percentage[n_stream]
- * (RX_SMOOTH_FACTOR - 1)) +
- (pstatus->rx_mimo_sig_qual[n_stream] * 1)) /
- (RX_SMOOTH_FACTOR);
- }
- }
-}
-
-void rtl_process_phyinfo(struct ieee80211_hw *hw, u8 *buffer,
- struct rtl_stats *pstatus)
-{
- if (!pstatus->packet_matchbssid)
- return;
-
- rtl_process_ui_rssi(hw, pstatus);
- rtl_process_pwdb(hw, pstatus);
- rtl_process_ui_link_quality(hw, pstatus);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_STATS_H__
-#define __RTL_STATS_H__
-
-#define PHY_RSSI_SLID_WIN_MAX 100
-#define PHY_LINKQUALITY_SLID_WIN_MAX 20
-#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
-
-/* Rx smooth factor */
-#define RX_SMOOTH_FACTOR 20
-
-u8 rtl_query_rxpwrpercentage(s8 antpower);
-u8 rtl_evm_db_to_percentage(s8 value);
-long rtl_signal_scale_mapping(struct ieee80211_hw *hw, long currsig);
-void rtl_process_phyinfo(struct ieee80211_hw *hw, u8 *buffer,
- struct rtl_stats *pstatus);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/******************************************************************************
- *
- * Copyright(c) 2009-2012 Realtek Corporation.
- *
- * Contact Information:
- * wlanfae <wlanfae@realtek.com>
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
- * Hsinchu 300, Taiwan.
- *
- * Larry Finger <Larry.Finger@lwfinger.net>
- *
- *****************************************************************************/
-
-#ifndef __RTL_WIFI_H__
-#define __RTL_WIFI_H__
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/sched.h>
-#include <linux/firmware.h>
-#include <linux/etherdevice.h>
-#include <linux/vmalloc.h>
-#include <linux/usb.h>
-#include <net/mac80211.h>
-#include <linux/completion.h>
-#include "debug.h"
-
-#define MASKBYTE0 0xff
-#define MASKBYTE1 0xff00
-#define MASKBYTE2 0xff0000
-#define MASKBYTE3 0xff000000
-#define MASKHWORD 0xffff0000
-#define MASKLWORD 0x0000ffff
-#define MASKDWORD 0xffffffff
-#define MASK12BITS 0xfff
-#define MASKH4BITS 0xf0000000
-#define MASKOFDM_D 0xffc00000
-#define MASKCCK 0x3f3f3f3f
-
-#define MASK4BITS 0x0f
-#define MASK20BITS 0xfffff
-#define RFREG_OFFSET_MASK 0xfffff
-
-#define MASKBYTE0 0xff
-#define MASKBYTE1 0xff00
-#define MASKBYTE2 0xff0000
-#define MASKBYTE3 0xff000000
-#define MASKHWORD 0xffff0000
-#define MASKLWORD 0x0000ffff
-#define MASKDWORD 0xffffffff
-#define MASK12BITS 0xfff
-#define MASKH4BITS 0xf0000000
-#define MASKOFDM_D 0xffc00000
-#define MASKCCK 0x3f3f3f3f
-
-#define MASK4BITS 0x0f
-#define MASK20BITS 0xfffff
-#define RFREG_OFFSET_MASK 0xfffff
-
-#define RF_CHANGE_BY_INIT 0
-#define RF_CHANGE_BY_IPS BIT(28)
-#define RF_CHANGE_BY_PS BIT(29)
-#define RF_CHANGE_BY_HW BIT(30)
-#define RF_CHANGE_BY_SW BIT(31)
-
-#define IQK_ADDA_REG_NUM 16
-#define IQK_MAC_REG_NUM 4
-#define IQK_THRESHOLD 8
-
-#define MAX_KEY_LEN 61
-#define KEY_BUF_SIZE 5
-
-/* QoS related. */
-/*aci: 0x00 Best Effort*/
-/*aci: 0x01 Background*/
-/*aci: 0x10 Video*/
-/*aci: 0x11 Voice*/
-/*Max: define total number.*/
-#define AC0_BE 0
-#define AC1_BK 1
-#define AC2_VI 2
-#define AC3_VO 3
-#define AC_MAX 4
-#define QOS_QUEUE_NUM 4
-#define RTL_MAC80211_NUM_QUEUE 5
-#define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
-#define RTL_USB_MAX_RX_COUNT 100
-#define QBSS_LOAD_SIZE 5
-#define MAX_WMMELE_LENGTH 64
-#define ASPM_L1_LATENCY 7
-
-#define TOTAL_CAM_ENTRY 32
-
-/*slot time for 11g. */
-#define RTL_SLOT_TIME_9 9
-#define RTL_SLOT_TIME_20 20
-
-/*related to tcp/ip. */
-#define SNAP_SIZE 6
-#define PROTOC_TYPE_SIZE 2
-
-/*related with 802.11 frame*/
-#define MAC80211_3ADDR_LEN 24
-#define MAC80211_4ADDR_LEN 30
-
-#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
-#define CHANNEL_MAX_NUMBER_2G 14
-#define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
- *"phy_GetChnlGroup8812A" and
- * "Hal_ReadTxPowerInfo8812A"
- */
-#define CHANNEL_MAX_NUMBER_5G_80M 7
-#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
-#define MAX_PG_GROUP 13
-#define CHANNEL_GROUP_MAX_2G 3
-#define CHANNEL_GROUP_IDX_5GL 3
-#define CHANNEL_GROUP_IDX_5GM 6
-#define CHANNEL_GROUP_IDX_5GH 9
-#define CHANNEL_GROUP_MAX_5G 9
-#define CHANNEL_MAX_NUMBER_2G 14
-#define AVG_THERMAL_NUM 8
-#define AVG_THERMAL_NUM_88E 4
-#define AVG_THERMAL_NUM_8723BE 4
-#define MAX_TID_COUNT 9
-
-/* for early mode */
-#define FCS_LEN 4
-#define EM_HDR_LEN 8
-
-enum rtl8192c_h2c_cmd {
- H2C_AP_OFFLOAD = 0,
- H2C_SETPWRMODE = 1,
- H2C_JOINBSSRPT = 2,
- H2C_RSVDPAGE = 3,
- H2C_RSSI_REPORT = 5,
- H2C_RA_MASK = 6,
- H2C_MACID_PS_MODE = 7,
- H2C_P2P_PS_OFFLOAD = 8,
- H2C_MAC_MODE_SEL = 9,
- H2C_PWRM = 15,
- H2C_P2P_PS_CTW_CMD = 24,
- MAX_H2CCMD
-};
-
-#define MAX_TX_COUNT 4
-#define MAX_REGULATION_NUM 4
-#define MAX_RF_PATH_NUM 4
-#define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */
-#define MAX_2_4G_BANDWIDTH_NUM 4
-#define MAX_5G_BANDWIDTH_NUM 4
-#define MAX_RF_PATH 4
-#define MAX_CHNL_GROUP_24G 6
-#define MAX_CHNL_GROUP_5G 14
-
-#define TX_PWR_BY_RATE_NUM_BAND 2
-#define TX_PWR_BY_RATE_NUM_RF 4
-#define TX_PWR_BY_RATE_NUM_SECTION 12
-/* compatible with TX_PWR_BY_RATE_NUM_SECTION */
-#define TX_PWR_BY_RATE_NUM_RATE 84
-#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */
-#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */
-
-#define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
-
-#define DEL_SW_IDX_SZ 30
-
-/* For now, it's just for 8192ee
- * but not OK yet, keep it 0
- */
-#define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
-#define RTL8822BE_SEG_NUM BUFDESC_SEG_NUM
-
-enum rf_tx_num {
- RF_1TX = 0,
- RF_2TX,
- RF_MAX_TX_NUM,
- RF_TX_NUM_NONIMPLEMENT,
-};
-
-#define PACKET_NORMAL 0
-#define PACKET_DHCP 1
-#define PACKET_ARP 2
-#define PACKET_EAPOL 3
-
-#define MAX_SUPPORT_WOL_PATTERN_NUM 16
-#define RSVD_WOL_PATTERN_NUM 1
-#define WKFMCAM_ADDR_NUM 6
-#define WKFMCAM_SIZE 24
-
-#define MAX_WOL_BIT_MASK_SIZE 16
-/* MIN LEN keeps 13 here */
-#define MIN_WOL_PATTERN_SIZE 13
-#define MAX_WOL_PATTERN_SIZE 128
-
-#define WAKE_ON_MAGIC_PACKET BIT(0)
-#define WAKE_ON_PATTERN_MATCH BIT(1)
-
-#define WOL_REASON_PTK_UPDATE BIT(0)
-#define WOL_REASON_GTK_UPDATE BIT(1)
-#define WOL_REASON_DISASSOC BIT(2)
-#define WOL_REASON_DEAUTH BIT(3)
-#define WOL_REASON_AP_LOST BIT(4)
-#define WOL_REASON_MAGIC_PKT BIT(5)
-#define WOL_REASON_UNICAST_PKT BIT(6)
-#define WOL_REASON_PATTERN_PKT BIT(7)
-#define WOL_REASON_RTD3_SSID_MATCH BIT(8)
-#define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
-#define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
-
-struct rtlwifi_firmware_header {
- __le16 signature;
- u8 category;
- u8 function;
- __le16 version;
- u8 subversion;
- u8 rsvd1;
- u8 month;
- u8 date;
- u8 hour;
- u8 minute;
- __le16 ramcodesize;
- __le16 rsvd2;
- __le32 svnindex;
- __le32 rsvd3;
- __le32 rsvd4;
- __le32 rsvd5;
-};
-
-struct txpower_info_2g {
- u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
- u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
- /*If only one tx, only BW20 and OFDM are used.*/
- u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
- u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
- u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
- u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
- u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
- u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
-};
-
-struct txpower_info_5g {
- u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
- /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
- u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
- u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
- u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
- u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
- u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
-};
-
-enum rate_section {
- CCK = 0,
- OFDM,
- HT_MCS0_MCS7,
- HT_MCS8_MCS15,
- VHT_1SSMCS0_1SSMCS9,
- VHT_2SSMCS0_2SSMCS9,
- MAX_RATE_SECTION,
-};
-
-enum intf_type {
- INTF_PCI = 0,
- INTF_USB = 1,
-};
-
-enum radio_path {
- RF90_PATH_A = 0,
- RF90_PATH_B = 1,
- RF90_PATH_C = 2,
- RF90_PATH_D = 3,
-};
-
-enum radio_mask {
- RF_MASK_A = BIT(0),
- RF_MASK_B = BIT(1),
- RF_MASK_C = BIT(2),
- RF_MASK_D = BIT(3),
-};
-
-enum regulation_txpwr_lmt {
- TXPWR_LMT_FCC = 0,
- TXPWR_LMT_MKK = 1,
- TXPWR_LMT_ETSI = 2,
- TXPWR_LMT_WW = 3,
-
- TXPWR_LMT_MAX_REGULATION_NUM = 4
-};
-
-enum rt_eeprom_type {
- EEPROM_93C46,
- EEPROM_93C56,
- EEPROM_BOOT_EFUSE,
-};
-
-enum ttl_status {
- RTL_STATUS_INTERFACE_START = 0,
-};
-
-enum hardware_type {
- HARDWARE_TYPE_RTL8192E,
- HARDWARE_TYPE_RTL8192U,
- HARDWARE_TYPE_RTL8192SE,
- HARDWARE_TYPE_RTL8192SU,
- HARDWARE_TYPE_RTL8192CE,
- HARDWARE_TYPE_RTL8192CU,
- HARDWARE_TYPE_RTL8192DE,
- HARDWARE_TYPE_RTL8192DU,
- HARDWARE_TYPE_RTL8723AE,
- HARDWARE_TYPE_RTL8723U,
- HARDWARE_TYPE_RTL8188EE,
- HARDWARE_TYPE_RTL8723BE,
- HARDWARE_TYPE_RTL8192EE,
- HARDWARE_TYPE_RTL8821AE,
- HARDWARE_TYPE_RTL8812AE,
- HARDWARE_TYPE_RTL8822BE,
-
- /* keep it last */
- HARDWARE_TYPE_NUM
-};
-
-#define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
-#define IS_NEW_GENERATION_IC(rtlpriv) \
- (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
-#define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
- (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
-#define IS_HARDWARE_TYPE_8812(rtlpriv) \
- (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
-#define IS_HARDWARE_TYPE_8821(rtlpriv) \
- (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
-#define IS_HARDWARE_TYPE_8723A(rtlpriv) \
- (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
-#define IS_HARDWARE_TYPE_8723B(rtlpriv) \
- (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
-#define IS_HARDWARE_TYPE_8192E(rtlpriv) \
- (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
-#define IS_HARDWARE_TYPE_8822B(rtlpriv) \
- (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
-
-#define RX_HAL_IS_CCK_RATE(rxmcs) \
- ((rxmcs) == DESC_RATE1M || \
- (rxmcs) == DESC_RATE2M || \
- (rxmcs) == DESC_RATE5_5M || \
- (rxmcs) == DESC_RATE11M)
-
-enum scan_operation_backup_opt {
- SCAN_OPT_BACKUP = 0,
- SCAN_OPT_BACKUP_BAND0 = 0,
- SCAN_OPT_BACKUP_BAND1,
- SCAN_OPT_RESTORE,
- SCAN_OPT_MAX
-};
-
-/*RF state.*/
-enum rf_pwrstate {
- ERFON,
- ERFSLEEP,
- ERFOFF
-};
-
-struct bb_reg_def {
- u32 rfintfs;
- u32 rfintfi;
- u32 rfintfo;
- u32 rfintfe;
- u32 rf3wire_offset;
- u32 rflssi_select;
- u32 rftxgain_stage;
- u32 rfhssi_para1;
- u32 rfhssi_para2;
- u32 rfsw_ctrl;
- u32 rfagc_control1;
- u32 rfagc_control2;
- u32 rfrxiq_imbal;
- u32 rfrx_afe;
- u32 rftxiq_imbal;
- u32 rftx_afe;
- u32 rf_rb; /* rflssi_readback */
- u32 rf_rbpi; /* rflssi_readbackpi */
-};
-
-enum io_type {
- IO_CMD_PAUSE_DM_BY_SCAN = 0,
- IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
- IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
- IO_CMD_RESUME_DM_BY_SCAN = 2,
-};
-
-enum hw_variables {
- HW_VAR_ETHER_ADDR = 0x0,
- HW_VAR_MULTICAST_REG = 0x1,
- HW_VAR_BASIC_RATE = 0x2,
- HW_VAR_BSSID = 0x3,
- HW_VAR_MEDIA_STATUS = 0x4,
- HW_VAR_SECURITY_CONF = 0x5,
- HW_VAR_BEACON_INTERVAL = 0x6,
- HW_VAR_ATIM_WINDOW = 0x7,
- HW_VAR_LISTEN_INTERVAL = 0x8,
- HW_VAR_CS_COUNTER = 0x9,
- HW_VAR_DEFAULTKEY0 = 0xa,
- HW_VAR_DEFAULTKEY1 = 0xb,
- HW_VAR_DEFAULTKEY2 = 0xc,
- HW_VAR_DEFAULTKEY3 = 0xd,
- HW_VAR_SIFS = 0xe,
- HW_VAR_R2T_SIFS = 0xf,
- HW_VAR_DIFS = 0x10,
- HW_VAR_EIFS = 0x11,
- HW_VAR_SLOT_TIME = 0x12,
- HW_VAR_ACK_PREAMBLE = 0x13,
- HW_VAR_CW_CONFIG = 0x14,
- HW_VAR_CW_VALUES = 0x15,
- HW_VAR_RATE_FALLBACK_CONTROL = 0x16,
- HW_VAR_CONTENTION_WINDOW = 0x17,
- HW_VAR_RETRY_COUNT = 0x18,
- HW_VAR_TR_SWITCH = 0x19,
- HW_VAR_COMMAND = 0x1a,
- HW_VAR_WPA_CONFIG = 0x1b,
- HW_VAR_AMPDU_MIN_SPACE = 0x1c,
- HW_VAR_SHORTGI_DENSITY = 0x1d,
- HW_VAR_AMPDU_FACTOR = 0x1e,
- HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
- HW_VAR_AC_PARAM = 0x20,
- HW_VAR_ACM_CTRL = 0x21,
- HW_VAR_DIS_REQ_QSIZE = 0x22,
- HW_VAR_CCX_CHNL_LOAD = 0x23,
- HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
- HW_VAR_CCX_CLM_NHM = 0x25,
- HW_VAR_TXOPLIMIT = 0x26,
- HW_VAR_TURBO_MODE = 0x27,
- HW_VAR_RF_STATE = 0x28,
- HW_VAR_RF_OFF_BY_HW = 0x29,
- HW_VAR_BUS_SPEED = 0x2a,
- HW_VAR_SET_DEV_POWER = 0x2b,
-
- HW_VAR_RCR = 0x2c,
- HW_VAR_RATR_0 = 0x2d,
- HW_VAR_RRSR = 0x2e,
- HW_VAR_CPU_RST = 0x2f,
- HW_VAR_CHECK_BSSID = 0x30,
- HW_VAR_LBK_MODE = 0x31,
- HW_VAR_AES_11N_FIX = 0x32,
- HW_VAR_USB_RX_AGGR = 0x33,
- HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
- HW_VAR_RETRY_LIMIT = 0x35,
- HW_VAR_INIT_TX_RATE = 0x36,
- HW_VAR_TX_RATE_REG = 0x37,
- HW_VAR_EFUSE_USAGE = 0x38,
- HW_VAR_EFUSE_BYTES = 0x39,
- HW_VAR_AUTOLOAD_STATUS = 0x3a,
- HW_VAR_RF_2R_DISABLE = 0x3b,
- HW_VAR_SET_RPWM = 0x3c,
- HW_VAR_H2C_FW_PWRMODE = 0x3d,
- HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
- HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
- HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
- HW_VAR_FW_PSMODE_STATUS = 0x41,
- HW_VAR_INIT_RTS_RATE = 0x42,
- HW_VAR_RESUME_CLK_ON = 0x43,
- HW_VAR_FW_LPS_ACTION = 0x44,
- HW_VAR_1X1_RECV_COMBINE = 0x45,
- HW_VAR_STOP_SEND_BEACON = 0x46,
- HW_VAR_TSF_TIMER = 0x47,
- HW_VAR_IO_CMD = 0x48,
-
- HW_VAR_RF_RECOVERY = 0x49,
- HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
- HW_VAR_WF_MASK = 0x4b,
- HW_VAR_WF_CRC = 0x4c,
- HW_VAR_WF_IS_MAC_ADDR = 0x4d,
- HW_VAR_H2C_FW_OFFLOAD = 0x4e,
- HW_VAR_RESET_WFCRC = 0x4f,
-
- HW_VAR_HANDLE_FW_C2H = 0x50,
- HW_VAR_DL_FW_RSVD_PAGE = 0x51,
- HW_VAR_AID = 0x52,
- HW_VAR_HW_SEQ_ENABLE = 0x53,
- HW_VAR_CORRECT_TSF = 0x54,
- HW_VAR_BCN_VALID = 0x55,
- HW_VAR_FWLPS_RF_ON = 0x56,
- HW_VAR_DUAL_TSF_RST = 0x57,
- HW_VAR_SWITCH_EPHY_WOWLAN = 0x58,
- HW_VAR_INT_MIGRATION = 0x59,
- HW_VAR_INT_AC = 0x5a,
- HW_VAR_RF_TIMING = 0x5b,
-
- HAL_DEF_WOWLAN = 0x5c,
- HW_VAR_MRC = 0x5d,
- HW_VAR_KEEP_ALIVE = 0x5e,
- HW_VAR_NAV_UPPER = 0x5f,
-
- HW_VAR_MGT_FILTER = 0x60,
- HW_VAR_CTRL_FILTER = 0x61,
- HW_VAR_DATA_FILTER = 0x62,
-};
-
-enum rt_media_status {
- RT_MEDIA_DISCONNECT = 0,
- RT_MEDIA_CONNECT = 1
-};
-
-enum rt_oem_id {
- RT_CID_DEFAULT = 0,
- RT_CID_8187_ALPHA0 = 1,
- RT_CID_8187_SERCOMM_PS = 2,
- RT_CID_8187_HW_LED = 3,
- RT_CID_8187_NETGEAR = 4,
- RT_CID_WHQL = 5,
- RT_CID_819X_CAMEO = 6,
- RT_CID_819X_RUNTOP = 7,
- RT_CID_819X_SENAO = 8,
- RT_CID_TOSHIBA = 9,
- RT_CID_819X_NETCORE = 10,
- RT_CID_NETTRONIX = 11,
- RT_CID_DLINK = 12,
- RT_CID_PRONET = 13,
- RT_CID_COREGA = 14,
- RT_CID_819X_ALPHA = 15,
- RT_CID_819X_SITECOM = 16,
- RT_CID_CCX = 17,
- RT_CID_819X_LENOVO = 18,
- RT_CID_819X_QMI = 19,
- RT_CID_819X_EDIMAX_BELKIN = 20,
- RT_CID_819X_SERCOMM_BELKIN = 21,
- RT_CID_819X_CAMEO1 = 22,
- RT_CID_819X_MSI = 23,
- RT_CID_819X_ACER = 24,
- RT_CID_819X_HP = 27,
- RT_CID_819X_CLEVO = 28,
- RT_CID_819X_ARCADYAN_BELKIN = 29,
- RT_CID_819X_SAMSUNG = 30,
- RT_CID_819X_WNC_COREGA = 31,
- RT_CID_819X_FOXCOON = 32,
- RT_CID_819X_DELL = 33,
- RT_CID_819X_PRONETS = 34,
- RT_CID_819X_EDIMAX_ASUS = 35,
- RT_CID_NETGEAR = 36,
- RT_CID_PLANEX = 37,
- RT_CID_CC_C = 38,
-};
-
-enum hw_descs {
- HW_DESC_OWN,
- HW_DESC_RXOWN,
- HW_DESC_TX_NEXTDESC_ADDR,
- HW_DESC_TXBUFF_ADDR,
- HW_DESC_RXBUFF_ADDR,
- HW_DESC_RXPKT_LEN,
- HW_DESC_RXERO,
- HW_DESC_RX_PREPARE,
-};
-
-enum prime_sc {
- PRIME_CHNL_OFFSET_DONT_CARE = 0,
- PRIME_CHNL_OFFSET_LOWER = 1,
- PRIME_CHNL_OFFSET_UPPER = 2,
-};
-
-enum rf_type {
- RF_1T1R = 0,
- RF_1T2R = 1,
- RF_2T2R = 2,
- RF_2T2R_GREEN = 3,
- RF_2T3R = 4,
- RF_2T4R = 5,
- RF_3T3R = 6,
- RF_3T4R = 7,
- RF_4T4R = 8,
-};
-
-enum ht_channel_width {
- HT_CHANNEL_WIDTH_20 = 0,
- HT_CHANNEL_WIDTH_20_40 = 1,
- HT_CHANNEL_WIDTH_80 = 2,
- HT_CHANNEL_WIDTH_MAX,
-};
-
-/* Ref: 802.11i spec D10.0 7.3.2.25.1
- * Cipher Suites Encryption Algorithms
- */
-enum rt_enc_alg {
- NO_ENCRYPTION = 0,
- WEP40_ENCRYPTION = 1,
- TKIP_ENCRYPTION = 2,
- RSERVED_ENCRYPTION = 3,
- AESCCMP_ENCRYPTION = 4,
- WEP104_ENCRYPTION = 5,
- AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
-};
-
-enum rtl_hal_state {
- _HAL_STATE_STOP = 0,
- _HAL_STATE_START = 1,
-};
-
-enum rtl_desc_rate {
- DESC_RATE1M = 0x00,
- DESC_RATE2M = 0x01,
- DESC_RATE5_5M = 0x02,
- DESC_RATE11M = 0x03,
-
- DESC_RATE6M = 0x04,
- DESC_RATE9M = 0x05,
- DESC_RATE12M = 0x06,
- DESC_RATE18M = 0x07,
- DESC_RATE24M = 0x08,
- DESC_RATE36M = 0x09,
- DESC_RATE48M = 0x0a,
- DESC_RATE54M = 0x0b,
-
- DESC_RATEMCS0 = 0x0c,
- DESC_RATEMCS1 = 0x0d,
- DESC_RATEMCS2 = 0x0e,
- DESC_RATEMCS3 = 0x0f,
- DESC_RATEMCS4 = 0x10,
- DESC_RATEMCS5 = 0x11,
- DESC_RATEMCS6 = 0x12,
- DESC_RATEMCS7 = 0x13,
- DESC_RATEMCS8 = 0x14,
- DESC_RATEMCS9 = 0x15,
- DESC_RATEMCS10 = 0x16,
- DESC_RATEMCS11 = 0x17,
- DESC_RATEMCS12 = 0x18,
- DESC_RATEMCS13 = 0x19,
- DESC_RATEMCS14 = 0x1a,
- DESC_RATEMCS15 = 0x1b,
- DESC_RATEMCS15_SG = 0x1c,
- DESC_RATEMCS32 = 0x20,
-
- DESC_RATEVHT1SS_MCS0 = 0x2c,
- DESC_RATEVHT1SS_MCS1 = 0x2d,
- DESC_RATEVHT1SS_MCS2 = 0x2e,
- DESC_RATEVHT1SS_MCS3 = 0x2f,
- DESC_RATEVHT1SS_MCS4 = 0x30,
- DESC_RATEVHT1SS_MCS5 = 0x31,
- DESC_RATEVHT1SS_MCS6 = 0x32,
- DESC_RATEVHT1SS_MCS7 = 0x33,
- DESC_RATEVHT1SS_MCS8 = 0x34,
- DESC_RATEVHT1SS_MCS9 = 0x35,
- DESC_RATEVHT2SS_MCS0 = 0x36,
- DESC_RATEVHT2SS_MCS1 = 0x37,
- DESC_RATEVHT2SS_MCS2 = 0x38,
- DESC_RATEVHT2SS_MCS3 = 0x39,
- DESC_RATEVHT2SS_MCS4 = 0x3a,
- DESC_RATEVHT2SS_MCS5 = 0x3b,
- DESC_RATEVHT2SS_MCS6 = 0x3c,
- DESC_RATEVHT2SS_MCS7 = 0x3d,
- DESC_RATEVHT2SS_MCS8 = 0x3e,
- DESC_RATEVHT2SS_MCS9 = 0x3f,
-};
-
-enum rtl_var_map {
- /*reg map */
- SYS_ISO_CTRL = 0,
- SYS_FUNC_EN,
- SYS_CLK,
- MAC_RCR_AM,
- MAC_RCR_AB,
- MAC_RCR_ACRC32,
- MAC_RCR_ACF,
- MAC_RCR_AAP,
- MAC_HIMR,
- MAC_HIMRE,
- MAC_HSISR,
-
- /*efuse map */
- EFUSE_TEST,
- EFUSE_CTRL,
- EFUSE_CLK,
- EFUSE_CLK_CTRL,
- EFUSE_PWC_EV12V,
- EFUSE_FEN_ELDR,
- EFUSE_LOADER_CLK_EN,
- EFUSE_ANA8M,
- EFUSE_HWSET_MAX_SIZE,
- EFUSE_MAX_SECTION_MAP,
- EFUSE_REAL_CONTENT_SIZE,
- EFUSE_OOB_PROTECT_BYTES_LEN,
- EFUSE_ACCESS,
-
- /*CAM map */
- RWCAM,
- WCAMI,
- RCAMO,
- CAMDBG,
- SECR,
- SEC_CAM_NONE,
- SEC_CAM_WEP40,
- SEC_CAM_TKIP,
- SEC_CAM_AES,
- SEC_CAM_WEP104,
-
- /*IMR map */
- RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
- RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
- RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
- RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
- RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
- RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
- RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrupt 8 */
- RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrupt 7 */
- RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrupt 6 */
- RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrupt 5 */
- RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrupt 4 */
- RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrupt 3 */
- RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrupt 2 */
- RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrupt 1 */
- RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
- RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
- RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
- RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
- RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
- RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
- RTL_IMR_RDU, /*Receive Descriptor Unavailable */
- RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
- RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */
- RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrupt */
- RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
- RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
- RTL_IMR_TBDOK, /*Transmit Beacon OK interrupt */
- RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
- RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
- RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
- RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
- RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
- RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
- RTL_IMR_ROK, /*Receive DMA OK Interrupt */
- RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
- RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
- * RTL_IMR_TBDER)
- */
- RTL_IMR_C2HCMD, /*fw interrupt*/
-
- /*CCK Rates, TxHT = 0 */
- RTL_RC_CCK_RATE1M,
- RTL_RC_CCK_RATE2M,
- RTL_RC_CCK_RATE5_5M,
- RTL_RC_CCK_RATE11M,
-
- /*OFDM Rates, TxHT = 0 */
- RTL_RC_OFDM_RATE6M,
- RTL_RC_OFDM_RATE9M,
- RTL_RC_OFDM_RATE12M,
- RTL_RC_OFDM_RATE18M,
- RTL_RC_OFDM_RATE24M,
- RTL_RC_OFDM_RATE36M,
- RTL_RC_OFDM_RATE48M,
- RTL_RC_OFDM_RATE54M,
-
- RTL_RC_HT_RATEMCS7,
- RTL_RC_HT_RATEMCS15,
-
- RTL_RC_VHT_RATE_1SS_MCS7,
- RTL_RC_VHT_RATE_1SS_MCS8,
- RTL_RC_VHT_RATE_1SS_MCS9,
- RTL_RC_VHT_RATE_2SS_MCS7,
- RTL_RC_VHT_RATE_2SS_MCS8,
- RTL_RC_VHT_RATE_2SS_MCS9,
-
- /*keep it last */
- RTL_VAR_MAP_MAX,
-};
-
-/*Firmware PS mode for control LPS.*/
-enum _fw_ps_mode {
- FW_PS_ACTIVE_MODE = 0,
- FW_PS_MIN_MODE = 1,
- FW_PS_MAX_MODE = 2,
- FW_PS_DTIM_MODE = 3,
- FW_PS_VOIP_MODE = 4,
- FW_PS_UAPSD_WMM_MODE = 5,
- FW_PS_UAPSD_MODE = 6,
- FW_PS_IBSS_MODE = 7,
- FW_PS_WWLAN_MODE = 8,
- FW_PS_PM_RADIO_OFF = 9,
- FW_PS_PM_CARD_DISABLE = 10,
-};
-
-enum rt_psmode {
- EACTIVE, /*Active/Continuous access. */
- EMAXPS, /*Max power save mode. */
- EFASTPS, /*Fast power save mode. */
- EAUTOPS, /*Auto power save mode. */
-};
-
-/*LED related.*/
-enum led_ctl_mode {
- LED_CTL_POWER_ON = 1,
- LED_CTL_LINK = 2,
- LED_CTL_NO_LINK = 3,
- LED_CTL_TX = 4,
- LED_CTL_RX = 5,
- LED_CTL_SITE_SURVEY = 6,
- LED_CTL_POWER_OFF = 7,
- LED_CTL_START_TO_LINK = 8,
- LED_CTL_START_WPS = 9,
- LED_CTL_STOP_WPS = 10,
-};
-
-enum rtl_led_pin {
- LED_PIN_GPIO0,
- LED_PIN_LED0,
- LED_PIN_LED1,
- LED_PIN_LED2
-};
-
-/* QoS related.*/
-/* acm implementation method.*/
-enum acm_method {
- EACMWAY0_SWANDHW = 0,
- EACMWAY1_HW = 1,
- EACMWAY2_SW = 2,
-};
-
-enum macphy_mode {
- SINGLEMAC_SINGLEPHY = 0,
- DUALMAC_DUALPHY,
- DUALMAC_SINGLEPHY,
-};
-
-enum band_type {
- BAND_ON_2_4G = 0,
- BAND_ON_5G,
- BAND_ON_BOTH,
- BANDMAX
-};
-
-/* aci/aifsn Field.
- * Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
- */
-union aci_aifsn {
- u8 char_data;
-
- struct {
- u8 aifsn:4;
- u8 acm:1;
- u8 aci:2;
- u8 reserved:1;
- } f; /* Field */
-};
-
-/*mlme related.*/
-enum wireless_mode {
- WIRELESS_MODE_UNKNOWN = 0x00,
- WIRELESS_MODE_A = 0x01,
- WIRELESS_MODE_B = 0x02,
- WIRELESS_MODE_G = 0x04,
- WIRELESS_MODE_AUTO = 0x08,
- WIRELESS_MODE_N_24G = 0x10,
- WIRELESS_MODE_N_5G = 0x20,
- WIRELESS_MODE_AC_5G = 0x40,
- WIRELESS_MODE_AC_24G = 0x80,
- WIRELESS_MODE_AC_ONLY = 0x100,
- WIRELESS_MODE_MAX = 0x800
-};
-
-#define IS_WIRELESS_MODE_A(wirelessmode) \
- (wirelessmode == WIRELESS_MODE_A)
-#define IS_WIRELESS_MODE_B(wirelessmode) \
- (wirelessmode == WIRELESS_MODE_B)
-#define IS_WIRELESS_MODE_G(wirelessmode) \
- (wirelessmode == WIRELESS_MODE_G)
-#define IS_WIRELESS_MODE_N_24G(wirelessmode) \
- (wirelessmode == WIRELESS_MODE_N_24G)
-#define IS_WIRELESS_MODE_N_5G(wirelessmode) \
- (wirelessmode == WIRELESS_MODE_N_5G)
-
-enum ratr_table_mode {
- RATR_INX_WIRELESS_NGB = 0,
- RATR_INX_WIRELESS_NG = 1,
- RATR_INX_WIRELESS_NB = 2,
- RATR_INX_WIRELESS_N = 3,
- RATR_INX_WIRELESS_GB = 4,
- RATR_INX_WIRELESS_G = 5,
- RATR_INX_WIRELESS_B = 6,
- RATR_INX_WIRELESS_MC = 7,
- RATR_INX_WIRELESS_A = 8,
- RATR_INX_WIRELESS_AC_5N = 8,
- RATR_INX_WIRELESS_AC_24N = 9,
-};
-
-enum ratr_table_mode_new {
- RATEID_IDX_BGN_40M_2SS = 0,
- RATEID_IDX_BGN_40M_1SS = 1,
- RATEID_IDX_BGN_20M_2SS_BN = 2,
- RATEID_IDX_BGN_20M_1SS_BN = 3,
- RATEID_IDX_GN_N2SS = 4,
- RATEID_IDX_GN_N1SS = 5,
- RATEID_IDX_BG = 6,
- RATEID_IDX_G = 7,
- RATEID_IDX_B = 8,
- RATEID_IDX_VHT_2SS = 9,
- RATEID_IDX_VHT_1SS = 10,
- RATEID_IDX_MIX1 = 11,
- RATEID_IDX_MIX2 = 12,
- RATEID_IDX_VHT_3SS = 13,
- RATEID_IDX_BGN_3SS = 14,
-};
-
-enum rtl_link_state {
- MAC80211_NOLINK = 0,
- MAC80211_LINKING = 1,
- MAC80211_LINKED = 2,
- MAC80211_LINKED_SCANNING = 3,
-};
-
-enum act_category {
- ACT_CAT_QOS = 1,
- ACT_CAT_DLS = 2,
- ACT_CAT_BA = 3,
- ACT_CAT_HT = 7,
- ACT_CAT_WMM = 17,
-};
-
-enum ba_action {
- ACT_ADDBAREQ = 0,
- ACT_ADDBARSP = 1,
- ACT_DELBA = 2,
-};
-
-enum rt_polarity_ctl {
- RT_POLARITY_LOW_ACT = 0,
- RT_POLARITY_HIGH_ACT = 1,
-};
-
-/* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
-enum fw_wow_reason_v2 {
- FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
- FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
- FW_WOW_V2_DISASSOC_EVENT = 0x04,
- FW_WOW_V2_DEAUTH_EVENT = 0x08,
- FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
- FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
- FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
- FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
- FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
- FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
- FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
- FW_WOW_V2_REASON_MAX = 0xff,
-};
-
-enum wolpattern_type {
- UNICAST_PATTERN = 0,
- MULTICAST_PATTERN = 1,
- BROADCAST_PATTERN = 2,
- DONT_CARE_DA = 3,
- UNKNOWN_TYPE = 4,
-};
-
-enum package_type {
- PACKAGE_DEFAULT,
- PACKAGE_QFN68,
- PACKAGE_TFBGA90,
- PACKAGE_TFBGA80,
- PACKAGE_TFBGA79
-};
-
-enum rtl_spec_ver {
- RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */
- RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */
- RTL_SPEC_NEW_FW_C2H = BIT(2), /* new FW C2H (e.g. TX REPORT) */
-};
-
-struct octet_string {
- u8 *octet;
- u16 length;
-};
-
-struct rtl_hdr_3addr {
- __le16 frame_ctl;
- __le16 duration_id;
- u8 addr1[ETH_ALEN];
- u8 addr2[ETH_ALEN];
- u8 addr3[ETH_ALEN];
- __le16 seq_ctl;
- u8 payload[0];
-} __packed;
-
-struct rtl_info_element {
- u8 id;
- u8 len;
- u8 data[0];
-} __packed;
-
-struct rtl_probe_rsp {
- struct rtl_hdr_3addr header;
- u32 time_stamp[2];
- __le16 beacon_interval;
- __le16 capability;
- /* SSID, supported rates, FH params, DS params,
- * CF params, IBSS params, TIM (if beacon), RSN
- */
- struct rtl_info_element info_element[0];
-} __packed;
-
-struct rtl_beacon_keys {
- /*u8 ssid[32];*/
- /*u32 ssid_len;*/
- u8 bcn_channel;
- __le16 ht_cap_info;
- u8 ht_info_infos_0_sco; /* bit0 & bit1 in infos[0] is 2nd ch offset */
- bool valid;
-};
-
-/*LED related.*/
-/*ledpin Identify how to implement this SW led.*/
-struct rtl_led {
- void *hw;
- enum rtl_led_pin ledpin;
- bool ledon;
-};
-
-struct rtl_led_ctl {
- bool led_opendrain;
- struct rtl_led sw_led0;
- struct rtl_led sw_led1;
-};
-
-struct rtl_qos_parameters {
- __le16 cw_min;
- __le16 cw_max;
- u8 aifs;
- u8 flag;
- __le16 tx_op;
-} __packed;
-
-struct rt_smooth_data {
- u32 elements[100]; /*array to store values */
- u32 index; /*index to current array to store */
- u32 total_num; /*num of valid elements */
- u32 total_val; /*sum of valid elements */
-};
-
-struct false_alarm_statistics {
- u32 cnt_parity_fail;
- u32 cnt_rate_illegal;
- u32 cnt_crc8_fail;
- u32 cnt_mcs_fail;
- u32 cnt_fast_fsync_fail;
- u32 cnt_sb_search_fail;
- u32 cnt_ofdm_fail;
- u32 cnt_cck_fail;
- u32 cnt_all;
- u32 cnt_ofdm_cca;
- u32 cnt_cck_cca;
- u32 cnt_cca_all;
- u32 cnt_bw_usc;
- u32 cnt_bw_lsc;
-};
-
-struct init_gain {
- u8 xaagccore1;
- u8 xbagccore1;
- u8 xcagccore1;
- u8 xdagccore1;
- u8 cca;
-
-};
-
-struct wireless_stats {
- u64 txbytesunicast;
- u64 txbytesmulticast;
- u64 txbytesbroadcast;
- u64 rxbytesunicast;
-
- u64 txbytesunicast_inperiod;
- u64 rxbytesunicast_inperiod;
- u32 txbytesunicast_inperiod_tp;
- u32 rxbytesunicast_inperiod_tp;
- u64 txbytesunicast_last;
- u64 rxbytesunicast_last;
-
- long rx_snr_db[4];
- /* Correct smoothed ss in Dbm, only used
- * in driver to report real power now.
- */
- long recv_signal_power;
- long signal_quality;
- long last_sigstrength_inpercent;
-
- u32 rssi_calculate_cnt;
- u32 pwdb_all_cnt;
-
- /* Transformed, in dbm. Beautified signal
- * strength for UI, not correct.
- */
- long signal_strength;
-
- u8 rx_rssi_percentage[4];
- u8 rx_evm_dbm[4];
- u8 rx_evm_percentage[2];
-
- u16 rx_cfo_short[4];
- u16 rx_cfo_tail[4];
-
- struct rt_smooth_data ui_rssi;
- struct rt_smooth_data ui_link_quality;
-};
-
-struct rate_adaptive {
- u8 rate_adaptive_disabled;
- u8 ratr_state;
- u16 reserve;
-
- u32 high_rssi_thresh_for_ra;
- u32 high2low_rssi_thresh_for_ra;
- u8 low2high_rssi_thresh_for_ra40m;
- u32 low_rssi_thresh_for_ra40m;
- u8 low2high_rssi_thresh_for_ra20m;
- u32 low_rssi_thresh_for_ra20m;
- u32 upper_rssi_threshold_ratr;
- u32 middleupper_rssi_threshold_ratr;
- u32 middle_rssi_threshold_ratr;
- u32 middlelow_rssi_threshold_ratr;
- u32 low_rssi_threshold_ratr;
- u32 ultralow_rssi_threshold_ratr;
- u32 low_rssi_threshold_ratr_40m;
- u32 low_rssi_threshold_ratr_20m;
- u8 ping_rssi_enable;
- u32 ping_rssi_ratr;
- u32 ping_rssi_thresh_for_ra;
- u32 last_ratr;
- u8 pre_ratr_state;
- u8 ldpc_thres;
- bool use_ldpc;
- bool lower_rts_rate;
- bool is_special_data;
-};
-
-struct regd_pair_mapping {
- u16 reg_dmnenum;
- u16 reg_5ghz_ctl;
- u16 reg_2ghz_ctl;
-};
-
-struct dynamic_primary_cca {
- u8 pricca_flag;
- u8 intf_flag;
- u8 intf_type;
- u8 dup_rts_flag;
- u8 monitor_flag;
- u8 ch_offset;
- u8 mf_state;
-};
-
-struct rtl_regulatory {
- s8 alpha2[2];
- u16 country_code;
- u16 max_power_level;
- u32 tp_scale;
- u16 current_rd;
- u16 current_rd_ext;
- s16 power_limit;
- struct regd_pair_mapping *regpair;
-};
-
-struct rtl_rfkill {
- bool rfkill_state; /*0 is off, 1 is on */
-};
-
-/*for P2P PS**/
-#define P2P_MAX_NOA_NUM 2
-
-enum p2p_role {
- P2P_ROLE_DISABLE = 0,
- P2P_ROLE_DEVICE = 1,
- P2P_ROLE_CLIENT = 2,
- P2P_ROLE_GO = 3
-};
-
-enum p2p_ps_state {
- P2P_PS_DISABLE = 0,
- P2P_PS_ENABLE = 1,
- P2P_PS_SCAN = 2,
- P2P_PS_SCAN_DONE = 3,
- P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
-};
-
-enum p2p_ps_mode {
- P2P_PS_NONE = 0,
- P2P_PS_CTWINDOW = 1,
- P2P_PS_NOA = 2,
- P2P_PS_MIX = 3, /* CTWindow and NoA */
-};
-
-struct rtl_p2p_ps_info {
- enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
- enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
- u8 noa_index; /* Identifies instance of Notice of Absence timing. */
- /* Client traffic window. A period of time in TU after TBTT. */
- u8 ctwindow;
- u8 opp_ps; /* opportunistic power save. */
- u8 noa_num; /* number of NoA descriptor in P2P IE. */
- /* Count for owner, Type of client. */
- u8 noa_count_type[P2P_MAX_NOA_NUM];
- /* Max duration for owner, preferred or min acceptable duration
- * for client.
- */
- u32 noa_duration[P2P_MAX_NOA_NUM];
- /* Length of interval for owner, preferred or max acceptable intervali
- * of client.
- */
- u32 noa_interval[P2P_MAX_NOA_NUM];
- /* schedule in terms of the lower 4 bytes of the TSF timer. */
- u32 noa_start_time[P2P_MAX_NOA_NUM];
-};
-
-struct p2p_ps_offload_t {
- u8 offload_en:1;
- u8 role:1; /* 1: Owner, 0: Client */
- u8 ctwindow_en:1;
- u8 noa0_en:1;
- u8 noa1_en:1;
- u8 allstasleep:1;
- u8 discovery:1;
- u8 reserved:1;
-};
-
-#define IQK_MATRIX_REG_NUM 8
-#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
-
-struct iqk_matrix_regs {
- bool iqk_done;
- long value[1][IQK_MATRIX_REG_NUM];
-};
-
-struct phy_parameters {
- u16 length;
- u32 *pdata;
-};
-
-enum hw_param_tab_index {
- PHY_REG_2T,
- PHY_REG_1T,
- PHY_REG_PG,
- RADIOA_2T,
- RADIOB_2T,
- RADIOA_1T,
- RADIOB_1T,
- MAC_REG,
- AGCTAB_2T,
- AGCTAB_1T,
- MAX_TAB
-};
-
-struct rtl_phy {
- struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
- struct init_gain initgain_backup;
- enum io_type current_io_type;
-
- u8 rf_mode;
- u8 rf_type;
- u8 current_chan_bw;
- u8 max_ht_chan_bw;
- u8 max_vht_chan_bw;
- u8 set_bwmode_inprogress;
- u8 sw_chnl_inprogress;
- u8 sw_chnl_stage;
- u8 sw_chnl_step;
- u8 current_channel;
- u8 h2c_box_num;
- u8 set_io_inprogress;
- u8 lck_inprogress;
-
- /* record for power tracking */
- s32 reg_e94;
- s32 reg_e9c;
- s32 reg_ea4;
- s32 reg_eac;
- s32 reg_eb4;
- s32 reg_ebc;
- s32 reg_ec4;
- s32 reg_ecc;
- u8 rfpienable;
- u8 reserve_0;
- u16 reserve_1;
- u32 reg_c04, reg_c08, reg_874;
- u32 adda_backup[16];
- u32 iqk_mac_backup[IQK_MAC_REG_NUM];
- u32 iqk_bb_backup[10];
- bool iqk_initialized;
-
- bool rfpath_rx_enable[MAX_RF_PATH];
- u8 reg_837;
- /* Dual mac */
- bool need_iqk;
- struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
-
- bool rfpi_enable;
- bool iqk_in_progress;
-
- u8 pwrgroup_cnt;
- u8 cck_high_power;
- /* this is for 88E & 8723A */
- u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
- /* MAX_PG_GROUP groups of pwr diff by rates */
- u32 mcs_offset[MAX_PG_GROUP][16];
- u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
- [TX_PWR_BY_RATE_NUM_RF]
- [TX_PWR_BY_RATE_NUM_RF]
- [TX_PWR_BY_RATE_NUM_RATE];
- /* compatible with TX_PWR_BY_RATE_NUM_SECTION*/
- u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
- [TX_PWR_BY_RATE_NUM_RF]
- [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
- u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
- [TX_PWR_BY_RATE_NUM_RF]
- [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
- u8 default_initialgain[4];
-
- /* the current Tx power level */
- u8 cur_cck_txpwridx;
- u8 cur_ofdm24g_txpwridx;
- u8 cur_bw20_txpwridx;
- u8 cur_bw40_txpwridx;
-
- s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
- [MAX_2_4G_BANDWIDTH_NUM]
- [MAX_RATE_SECTION_NUM]
- [CHANNEL_MAX_NUMBER_2G]
- [MAX_RF_PATH_NUM];
- s8 txpwr_limit_5g[MAX_REGULATION_NUM]
- [MAX_5G_BANDWIDTH_NUM]
- [MAX_RATE_SECTION_NUM]
- [CHANNEL_MAX_NUMBER_5G]
- [MAX_RF_PATH_NUM];
-
- u32 rfreg_chnlval[2];
- bool apk_done;
- u32 reg_rf3c[2]; /* pathA / pathB */
-
- u32 backup_rf_0x1a;/*92ee*/
- /* bfsync */
- u8 framesync;
- u32 framesync_c34;
-
- u8 num_total_rfpath;
- struct phy_parameters hwparam_tables[MAX_TAB];
- u16 rf_pathmap;
-
- u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
- enum rt_polarity_ctl polarity_ctl;
-};
-
-#define MAX_TID_COUNT 9
-#define RTL_AGG_STOP 0
-#define RTL_AGG_PROGRESS 1
-#define RTL_AGG_START 2
-#define RTL_AGG_OPERATIONAL 3
-#define RTL_AGG_OFF 0
-#define RTL_AGG_ON 1
-#define RTL_RX_AGG_START 1
-#define RTL_RX_AGG_STOP 0
-#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
-#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
-
-struct rtl_ht_agg {
- u16 txq_id;
- u16 wait_for_ba;
- u16 start_idx;
- u64 bitmap;
- u32 rate_n_flags;
- u8 agg_state;
- u8 rx_agg_state;
-};
-
-struct rssi_sta {
- /* for old dm */
- long undec_sm_pwdb;
- long undec_sm_cck;
-
- /* for new phydm_mod */
- s32 undecorated_smoothed_pwdb;
- s32 undecorated_smoothed_cck;
- s32 undecorated_smoothed_ofdm;
- u8 ofdm_pkt;
- u8 cck_pkt;
- u16 cck_sum_power;
- u8 is_send_rssi;
- u64 packet_map;
- u8 valid_bit;
-};
-
-struct rtl_tid_data {
- u16 seq_number;
- struct rtl_ht_agg agg;
-};
-
-struct rtl_sta_info {
- struct list_head list;
- struct rtl_tid_data tids[MAX_TID_COUNT];
- /* just used for ap adhoc or mesh*/
- struct rssi_sta rssi_stat;
- u8 rssi_level;
- u16 wireless_mode;
- u8 ratr_index;
- u8 mimo_ps;
- u8 mac_addr[ETH_ALEN];
-} __packed;
-
-struct rtl_priv;
-struct rtl_io {
- struct device *dev;
- struct mutex bb_mutex;
-
- /*PCI MEM map */
- unsigned long pci_mem_end; /*shared mem end */
- unsigned long pci_mem_start; /*shared mem start */
-
- /*PCI IO map */
- unsigned long pci_base_addr; /*device I/O address */
-
- void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
- void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
- void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
- void (*writeN_sync)(struct rtl_priv *rtlpriv, u32 addr, void *buf,
- u16 len);
-
- u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr);
- u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr);
- u32 (*read32_sync)(struct rtl_priv *rtlpriv, u32 addr);
-
-};
-
-struct rtl_mac {
- u8 mac_addr[ETH_ALEN];
- u8 mac80211_registered;
- u8 beacon_enabled;
-
- u32 tx_ss_num;
- u32 rx_ss_num;
-
- struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
- struct ieee80211_hw *hw;
- struct ieee80211_vif *vif;
- enum nl80211_iftype opmode;
-
- /*Probe Beacon management */
- struct rtl_tid_data tids[MAX_TID_COUNT];
- enum rtl_link_state link_state;
- struct rtl_beacon_keys cur_beacon_keys;
- u8 new_beacon_cnt;
-
- int n_channels;
- int n_bitrates;
-
- bool offchan_delay;
- u8 p2p; /*using p2p role*/
- bool p2p_in_use;
-
- /*filters */
- u32 rx_conf;
- u16 rx_mgt_filter;
- u16 rx_ctrl_filter;
- u16 rx_data_filter;
-
- bool act_scanning;
- u8 cnt_after_linked;
- bool skip_scan;
-
- /* early mode */
- /* skb wait queue */
- struct sk_buff_head skb_waitq[MAX_TID_COUNT];
-
- u8 ht_stbc_cap;
- u8 ht_cur_stbc;
-
- /*vht support*/
- u8 vht_enable;
- u8 bw_80;
- u8 vht_cur_ldpc;
- u8 vht_cur_stbc;
- u8 vht_stbc_cap;
- u8 vht_ldpc_cap;
-
- /*RDG*/
- bool rdg_en;
-
- /*AP*/
- u8 bssid[ETH_ALEN] __aligned(2);
- u32 vendor;
- u8 mcs[16]; /* 16 bytes mcs for HT rates. */
- u32 basic_rates; /* b/g rates */
- u8 ht_enable;
- u8 sgi_40;
- u8 sgi_20;
- u8 bw_40;
- u16 mode; /* wireless mode */
- u8 slot_time;
- u8 short_preamble;
- u8 use_cts_protect;
- u8 cur_40_prime_sc;
- u8 cur_40_prime_sc_bk;
- u8 cur_80_prime_sc;
- u64 tsf;
- u8 retry_short;
- u8 retry_long;
- u16 assoc_id;
- bool hiddenssid;
-
- /*IBSS*/
- int beacon_interval;
-
- /*AMPDU*/
- u8 min_space_cfg; /*For Min spacing configurations */
- u8 max_mss_density;
- u8 current_ampdu_factor;
- u8 current_ampdu_density;
-
- /*QOS & EDCA */
- struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
- struct rtl_qos_parameters ac[AC_MAX];
-
- /* counters */
- u64 last_txok_cnt;
- u64 last_rxok_cnt;
- u32 last_bt_edca_ul;
- u32 last_bt_edca_dl;
-};
-
-struct btdm_8723 {
- bool all_off;
- bool agc_table_en;
- bool adc_back_off_on;
- bool b2_ant_hid_en;
- bool low_penalty_rate_adaptive;
- bool rf_rx_lpf_shrink;
- bool reject_aggre_pkt;
- bool tra_tdma_on;
- u8 tra_tdma_nav;
- u8 tra_tdma_ant;
- bool tdma_on;
- u8 tdma_ant;
- u8 tdma_nav;
- u8 tdma_dac_swing;
- u8 fw_dac_swing_lvl;
- bool ps_tdma_on;
- u8 ps_tdma_byte[5];
- bool pta_on;
- u32 val_0x6c0;
- u32 val_0x6c8;
- u32 val_0x6cc;
- bool sw_dac_swing_on;
- u32 sw_dac_swing_lvl;
- u32 wlan_act_hi;
- u32 wlan_act_lo;
- u32 bt_retry_index;
- bool dec_bt_pwr;
- bool ignore_wlan_act;
-};
-
-struct bt_coexist_8723 {
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- u8 c2h_bt_info;
- bool c2h_bt_info_req_sent;
- bool c2h_bt_inquiry_page;
- u32 bt_inq_page_start_time;
- u8 bt_retry_cnt;
- u8 c2h_bt_info_original;
- u8 bt_inquiry_page_cnt;
- struct btdm_8723 btdm;
-};
-
-struct rtl_hal {
- struct ieee80211_hw *hw;
- bool driver_is_goingto_unload;
- bool up_first_time;
- bool first_init;
- bool being_init_adapter;
- bool bbrf_ready;
- bool mac_func_enable;
- bool pre_edcca_enable;
- struct bt_coexist_8723 hal_coex_8723;
-
- enum intf_type interface;
- u16 hw_type; /*92c or 92d or 92s and so on */
- u8 ic_class;
- u8 oem_id;
- u32 version; /*version of chip */
- u8 state; /*stop 0, start 1 */
- u8 board_type;
- u8 package_type;
- u8 external_pa;
-
- u8 pa_mode;
- u8 pa_type_2g;
- u8 pa_type_5g;
- u8 lna_type_2g;
- u8 lna_type_5g;
- u8 external_pa_2g;
- u8 external_lna_2g;
- u8 external_pa_5g;
- u8 external_lna_5g;
- u8 type_glna;
- u8 type_gpa;
- u8 type_alna;
- u8 type_apa;
- u8 rfe_type;
-
- /*firmware */
- u32 fwsize;
- u8 *pfirmware;
- u16 fw_version;
- u16 fw_subversion;
- bool h2c_setinprogress;
- u8 last_hmeboxnum;
- bool fw_ready;
- /*Reserve page start offset except beacon in TxQ. */
- u8 fw_rsvdpage_startoffset;
- u8 h2c_txcmd_seq;
- u8 current_ra_rate;
-
- /* FW Cmd IO related */
- u16 fwcmd_iomap;
- u32 fwcmd_ioparam;
- bool set_fwcmd_inprogress;
- u8 current_fwcmd_io;
-
- struct p2p_ps_offload_t p2p_ps_offload;
- bool fw_clk_change_in_progress;
- bool allow_sw_to_change_hwclc;
- u8 fw_ps_state;
- /**/
- bool driver_going2unload;
-
- /*AMPDU init min space*/
- u8 minspace_cfg; /*For Min spacing configurations */
-
- /* Dual mac */
- enum macphy_mode macphymode;
- enum band_type current_bandtype; /* 0:2.4G, 1:5G */
- enum band_type current_bandtypebackup;
- enum band_type bandset;
- /* dual MAC 0--Mac0 1--Mac1 */
- u32 interfaceindex;
- /* just for DualMac S3S4 */
- u8 macphyctl_reg;
- bool earlymode_enable;
- u8 max_earlymode_num;
- /* Dual mac*/
- bool during_mac0init_radiob;
- bool during_mac1init_radioa;
- bool reloadtxpowerindex;
- /* True if IMR or IQK have done
- * for 2.4G in scan progress
- */
- bool load_imrandiqk_setting_for2g;
-
- bool disable_amsdu_8k;
- bool master_of_dmsp;
- bool slave_of_dmsp;
-
- u16 rx_tag;/*for 92ee*/
- u8 rts_en;
-
- /*for wowlan*/
- bool wow_enable;
- bool enter_pnp_sleep;
- bool wake_from_pnp_sleep;
- bool wow_enabled;
- time64_t last_suspend_sec;
- u32 wowlan_fwsize;
- u8 *wowlan_firmware;
-
- u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
-
- bool real_wow_v2_enable;
- bool re_init_llt_table;
-};
-
-struct rtl_security {
- /*default 0 */
- bool use_sw_sec;
-
- bool being_setkey;
- bool use_defaultkey;
- /*Encryption Algorithm for Unicast Packet */
- enum rt_enc_alg pairwise_enc_algorithm;
- /*Encryption Algorithm for Brocast/Multicast */
- enum rt_enc_alg group_enc_algorithm;
- /*Cam Entry Bitmap */
- u32 hwsec_cam_bitmap;
- u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
- /* local Key buffer, indx 0 is for
- * pairwise key 1-4 is for agoup key.
- */
- u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
- u8 key_len[KEY_BUF_SIZE];
-
- /* The pointer of Pairwise Key,
- * it always points to KeyBuf[4]
- */
- u8 *pairwise_key;
-};
-
-#define ASSOCIATE_ENTRY_NUM 33
-
-struct fast_ant_training {
- u8 bssid[6];
- u8 antsel_rx_keep_0;
- u8 antsel_rx_keep_1;
- u8 antsel_rx_keep_2;
- u32 ant_sum[7];
- u32 ant_cnt[7];
- u32 ant_ave[7];
- u8 fat_state;
- u32 train_idx;
- u8 antsel_a[ASSOCIATE_ENTRY_NUM];
- u8 antsel_b[ASSOCIATE_ENTRY_NUM];
- u8 antsel_c[ASSOCIATE_ENTRY_NUM];
- u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
- u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
- u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
- u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
- u8 rx_idle_ant;
- bool becomelinked;
-};
-
-struct dm_phy_dbg_info {
- s8 rx_snrdb[4];
- u64 num_qry_phy_status;
- u64 num_qry_phy_status_cck;
- u64 num_qry_phy_status_ofdm;
- u16 num_qry_beacon_pkt;
- u16 num_non_be_pkt;
- s32 rx_evm[4];
-};
-
-struct rtl_dm {
- /*PHY status for Dynamic Management */
- long entry_min_undec_sm_pwdb;
- long undec_sm_cck;
- long undec_sm_pwdb; /*out dm */
- long entry_max_undec_sm_pwdb;
- s32 ofdm_pkt_cnt;
- bool dm_initialgain_enable;
- bool dynamic_txpower_enable;
- bool current_turbo_edca;
- bool is_any_nonbepkts; /*out dm */
- bool is_cur_rdlstate;
- bool txpower_trackinginit;
- bool disable_framebursting;
- bool cck_inch14;
- bool txpower_tracking;
- bool useramask;
- bool rfpath_rxenable[4];
- bool inform_fw_driverctrldm;
- bool current_mrc_switch;
- u8 txpowercount;
- u8 powerindex_backup[6];
-
- u8 thermalvalue_rxgain;
- u8 thermalvalue_iqk;
- u8 thermalvalue_lck;
- u8 thermalvalue;
- u8 last_dtp_lvl;
- u8 thermalvalue_avg[AVG_THERMAL_NUM];
- u8 thermalvalue_avg_index;
- u8 tm_trigger;
- bool done_txpower;
- u8 dynamic_txhighpower_lvl; /*Tx high power level */
- u8 dm_flag; /*Indicate each dynamic mechanism's status. */
- u8 dm_flag_tmp;
- u8 dm_type;
- u8 dm_rssi_sel;
- u8 txpower_track_control;
- bool interrupt_migration;
- bool disable_tx_int;
- s8 ofdm_index[MAX_RF_PATH];
- u8 default_ofdm_index;
- u8 default_cck_index;
- s8 cck_index;
- s8 delta_power_index[MAX_RF_PATH];
- s8 delta_power_index_last[MAX_RF_PATH];
- s8 power_index_offset[MAX_RF_PATH];
- s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
- s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
- s8 remnant_cck_idx;
- bool modify_txagc_flag_path_a;
- bool modify_txagc_flag_path_b;
-
- bool one_entry_only;
- struct dm_phy_dbg_info dbginfo;
-
- /* Dynamic ATC switch */
- bool atc_status;
- bool large_cfo_hit;
- bool is_freeze;
- int cfo_tail[2];
- int cfo_ave_pre;
- int crystal_cap;
- u8 cfo_threshold;
- u32 packet_count;
- u32 packet_count_pre;
- u8 tx_rate;
-
- /*88e tx power tracking*/
- u8 swing_idx_ofdm[MAX_RF_PATH];
- u8 swing_idx_ofdm_cur;
- u8 swing_idx_ofdm_base[MAX_RF_PATH];
- bool swing_flag_ofdm;
- u8 swing_idx_cck;
- u8 swing_idx_cck_cur;
- u8 swing_idx_cck_base;
- bool swing_flag_cck;
-
- s8 swing_diff_2g;
- s8 swing_diff_5g;
-
- /* DMSP */
- bool supp_phymode_switch;
-
- /* DulMac */
- struct fast_ant_training fat_table;
-
- u8 resp_tx_path;
- u8 path_sel;
- u32 patha_sum;
- u32 pathb_sum;
- u32 patha_cnt;
- u32 pathb_cnt;
-
- u8 pre_channel;
- u8 *p_channel;
- u8 linked_interval;
-
- u64 last_tx_ok_cnt;
- u64 last_rx_ok_cnt;
-};
-
-#define EFUSE_MAX_LOGICAL_SIZE 512
-
-struct rtl_efuse {
- bool autoload_ok;
- bool bootfromefuse;
- u16 max_physical_size;
-
- u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
- u16 efuse_usedbytes;
- u8 efuse_usedpercentage;
-
- u8 autoload_failflag;
- u8 autoload_status;
-
- short epromtype;
- u16 eeprom_vid;
- u16 eeprom_did;
- u16 eeprom_svid;
- u16 eeprom_smid;
- u8 eeprom_oemid;
- u16 eeprom_channelplan;
- u8 eeprom_version;
- u8 board_type;
- u8 external_pa;
-
- u8 dev_addr[6];
- u8 wowlan_enable;
- u8 antenna_div_cfg;
- u8 antenna_div_type;
-
- bool txpwr_fromeprom;
- u8 eeprom_crystalcap;
- u8 eeprom_tssi[2];
- u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
- u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
- u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
- u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
- u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
- u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
-
- u8 internal_pa_5g[2]; /* pathA / pathB */
- u8 eeprom_c9;
- u8 eeprom_cc;
-
- /*For power group */
- u8 eeprom_pwrgroup[2][3];
- u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
- u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
-
- u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
- /*For HT 40MHZ pwr */
- u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
- /*For HT 40MHZ pwr */
- u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
-
- /*--------------------------------------------------------*
- * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
- * other ICs (8188EE\8723BE\8192EE\8812AE...)
- * define new arrays in Windows code.
- * BUT, in linux code, we use the same array for all ICs.
- *
- * The Correspondance relation between two arrays is:
- * txpwr_cckdiff[][] == CCK_24G_Diff[][]
- * txpwr_ht20diff[][] == BW20_24G_Diff[][]
- * txpwr_ht40diff[][] == BW40_24G_Diff[][]
- * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
- *
- * Sizes of these arrays are decided by the larger ones.
- */
- s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
- s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
- s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
- s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
-
- u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
- u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
- s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
- s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
- s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
- s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
-
- u8 txpwr_safetyflag; /* Band edge enable flag */
- u16 eeprom_txpowerdiff;
- u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
- u8 antenna_txpwdiff[3];
-
- u8 eeprom_regulatory;
- u8 eeprom_thermalmeter;
- u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
- u16 tssi_13dbm;
- u8 crystalcap; /* CrystalCap. */
- u8 delta_iqk;
- u8 delta_lck;
-
- u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
- bool apk_thermalmeterignore;
-
- bool b1x1_recvcombine;
- bool b1ss_support;
-
- /*channel plan */
- u8 channel_plan;
-};
-
-struct rtl_tx_report {
- atomic_t sn;
- u16 last_sent_sn;
- unsigned long last_sent_time;
- u16 last_recv_sn;
-};
-
-struct rtl_ps_ctl {
- bool pwrdomain_protect;
- bool in_powersavemode;
- bool rfchange_inprogress;
- bool swrf_processing;
- bool hwradiooff;
- /* just for PCIE ASPM
- * If it supports ASPM, Offset[560h] = 0x40,
- * otherwise Offset[560h] = 0x00.
- */
- bool support_aspm;
- bool support_backdoor;
-
- /*for LPS */
- enum rt_psmode dot11_psmode; /*Power save mode configured. */
- bool swctrl_lps;
- bool leisure_ps;
- bool fwctrl_lps;
- u8 fwctrl_psmode;
- /*For Fw control LPS mode */
- u8 reg_fwctrl_lps;
- /*Record Fw PS mode status. */
- bool fw_current_inpsmode;
- u8 reg_max_lps_awakeintvl;
- bool report_linked;
- bool low_power_enable;/*for 32k*/
-
- /*for IPS */
- bool inactiveps;
-
- u32 rfoff_reason;
-
- /*RF OFF Level */
- u32 cur_ps_level;
- u32 reg_rfps_level;
-
- /*just for PCIE ASPM */
- u8 const_amdpci_aspm;
- bool pwrdown_mode;
-
- enum rf_pwrstate inactive_pwrstate;
- enum rf_pwrstate rfpwr_state; /*cur power state */
-
- /* for SW LPS*/
- bool sw_ps_enabled;
- bool state;
- bool state_inap;
- bool multi_buffered;
- u16 nullfunc_seq;
- unsigned int dtim_counter;
- unsigned int sleep_ms;
- unsigned long last_sleep_jiffies;
- unsigned long last_awake_jiffies;
- unsigned long last_delaylps_stamp_jiffies;
- unsigned long last_dtim;
- unsigned long last_beacon;
- unsigned long last_action;
- unsigned long last_slept;
-
- /*For P2P PS */
- struct rtl_p2p_ps_info p2p_ps_info;
- u8 pwr_mode;
- u8 smart_ps;
-
- /* wake up on line */
- u8 wo_wlan_mode;
- u8 arp_offload_enable;
- u8 gtk_offload_enable;
- /* Used for WOL, indicates the reason for waking event.*/
- u32 wakeup_reason;
- /* Record the last waking time for comparison with setting key. */
- u64 last_wakeup_time;
-};
-
-struct rtl_stats {
- u8 psaddr[ETH_ALEN];
- u32 mac_time[2];
- s8 rssi;
- u8 signal;
- u8 noise;
- u8 rate; /* hw desc rate */
- u8 received_channel;
- u8 control;
- u8 mask;
- u8 freq;
- u16 len;
- u64 tsf;
- u32 beacon_time;
- u8 nic_type;
- u16 length;
- u8 signalquality; /*in 0-100 index. */
- /*
- * Real power in dBm for this packet,
- * no beautification and aggregation.
- */
- s32 recvsignalpower;
- s8 rxpower; /*in dBm Translate from PWdB */
- u8 signalstrength; /*in 0-100 index. */
- u16 hwerror:1;
- u16 crc:1;
- u16 icv:1;
- u16 shortpreamble:1;
- u16 antenna:1;
- u16 decrypted:1;
- u16 wakeup:1;
- u32 timestamp_low;
- u32 timestamp_high;
- bool shift;
-
- u8 rx_drvinfo_size;
- u8 rx_bufshift;
- bool isampdu;
- bool isfirst_ampdu;
- bool rx_is40mhzpacket;
- u8 rx_packet_bw;
- u32 rx_pwdb_all;
- u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
- s8 rx_mimo_signalquality[4];
- u8 rx_mimo_evm_dbm[4];
- u16 cfo_short[4]; /* per-path's Cfo_short */
- u16 cfo_tail[4];
-
- s8 rx_mimo_sig_qual[4];
- u8 rx_pwr[4]; /* per-path's pwdb */
- u8 rx_snr[4]; /* per-path's SNR */
- u8 bandwidth;
- u8 bt_coex_pwr_adjust;
- bool packet_matchbssid;
- bool is_cck;
- bool is_ht;
- bool packet_toself;
- bool packet_beacon; /*for rssi */
- s8 cck_adc_pwdb[4]; /*for rx path selection */
-
- bool is_vht;
- bool is_short_gi;
- u8 vht_nss;
-
- u8 packet_report_type;
-
- u32 macid;
- u8 wake_match;
- u32 bt_rx_rssi_percentage;
- u32 macid_valid_entry[2];
-};
-
-struct rt_link_detect {
- /* count for roaming */
- u32 bcn_rx_inperiod;
- u32 roam_times;
-
- u32 num_tx_in4period[4];
- u32 num_rx_in4period[4];
-
- u32 num_tx_inperiod;
- u32 num_rx_inperiod;
-
- bool busytraffic;
- bool tx_busy_traffic;
- bool rx_busy_traffic;
- bool higher_busytraffic;
- bool higher_busyrxtraffic;
-
- u32 tidtx_in4period[MAX_TID_COUNT][4];
- u32 tidtx_inperiod[MAX_TID_COUNT];
- bool higher_busytxtraffic[MAX_TID_COUNT];
-};
-
-struct rtl_tcb_desc {
- u8 packet_bw:2;
- u8 multicast:1;
- u8 broadcast:1;
-
- u8 rts_stbc:1;
- u8 rts_enable:1;
- u8 cts_enable:1;
- u8 rts_use_shortpreamble:1;
- u8 rts_use_shortgi:1;
- u8 rts_sc:1;
- u8 rts_bw:1;
- u8 rts_rate;
-
- u8 use_shortgi:1;
- u8 use_shortpreamble:1;
- u8 use_driver_rate:1;
- u8 disable_ratefallback:1;
-
- u8 use_spe_rpt:1;
-
- u8 ratr_index;
- u8 mac_id;
- u8 hw_rate;
-
- u8 last_inipkt:1;
- u8 cmd_or_init:1;
- u8 queue_index;
-
- /* early mode */
- u8 empkt_num;
- /* The max value by HW */
- u32 empkt_len[10];
- bool tx_enable_sw_calc_duration;
-};
-
-struct rtl_wow_pattern {
- u8 type;
- u16 crc;
- u32 mask[4];
-};
-
-struct rtl_hal_ops {
- int (*init_sw_vars)(struct ieee80211_hw *hw);
- void (*deinit_sw_vars)(struct ieee80211_hw *hw);
- void (*read_chip_version)(struct ieee80211_hw *hw);
- void (*read_eeprom_info)(struct ieee80211_hw *hw);
- void (*interrupt_recognized)(struct ieee80211_hw *hw,
- u32 *p_inta, u32 *p_intb,
- u32 *p_intc, u32 *p_intd);
- int (*hw_init)(struct ieee80211_hw *hw);
- void (*hw_disable)(struct ieee80211_hw *hw);
- void (*hw_suspend)(struct ieee80211_hw *hw);
- void (*hw_resume)(struct ieee80211_hw *hw);
- void (*enable_interrupt)(struct ieee80211_hw *hw);
- void (*disable_interrupt)(struct ieee80211_hw *hw);
- int (*set_network_type)(struct ieee80211_hw *hw,
- enum nl80211_iftype type);
- void (*set_chk_bssid)(struct ieee80211_hw *hw,
- bool check_bssid);
- void (*set_bw_mode)(struct ieee80211_hw *hw,
- enum nl80211_channel_type ch_type);
- u8 (*switch_channel)(struct ieee80211_hw *hw);
- void (*set_qos)(struct ieee80211_hw *hw, int aci);
- void (*set_bcn_reg)(struct ieee80211_hw *hw);
- void (*set_bcn_intv)(struct ieee80211_hw *hw);
- void (*update_interrupt_mask)(struct ieee80211_hw *hw,
- u32 add_msr, u32 rm_msr);
- void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
- void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
- void (*update_rate_tbl)(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta, u8 rssi_leve,
- bool update_bw);
- void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
- u8 *desc, u8 queue_index,
- struct sk_buff *skb, dma_addr_t addr);
- void (*update_rate_mask)(struct ieee80211_hw *hw, u8 rssi_level);
- u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
- u8 queue_index);
- void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
- u8 queue_index);
- void (*fill_tx_desc)(struct ieee80211_hw *hw,
- struct ieee80211_hdr *hdr, u8 *pdesc_tx,
- u8 *pbd_desc_tx,
- struct ieee80211_tx_info *info,
- struct ieee80211_sta *sta,
- struct sk_buff *skb, u8 hw_queue,
- struct rtl_tcb_desc *ptcb_desc);
- void (*fill_fake_txdesc)(struct ieee80211_hw *hw, u8 *pdesc,
- u32 buffer_len, bool bispspoll);
- void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc,
- bool firstseg, bool lastseg,
- struct sk_buff *skb);
- void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
- u8 *pdesc, u8 *pbd_desc,
- struct sk_buff *skb, u8 hw_queue);
- bool (*query_rx_desc)(struct ieee80211_hw *hw,
- struct rtl_stats *stats,
- struct ieee80211_rx_status *rx_status,
- u8 *pdesc, struct sk_buff *skb);
- void (*set_channel_access)(struct ieee80211_hw *hw);
- bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid);
- void (*dm_watchdog)(struct ieee80211_hw *hw);
- void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation);
- bool (*set_rf_power_state)(struct ieee80211_hw *hw,
- enum rf_pwrstate rfpwr_state);
- void (*led_control)(struct ieee80211_hw *hw,
- enum led_ctl_mode ledaction);
- void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
- u8 desc_name, u8 *val);
- u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
- u8 desc_name);
- bool (*is_tx_desc_closed)(struct ieee80211_hw *hw,
- u8 hw_queue, u16 index);
- void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue);
- void (*enable_hw_sec)(struct ieee80211_hw *hw);
- void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
- u8 *macaddr, bool is_group, u8 enc_algo,
- bool is_wepkey, bool clear_all);
- void (*init_sw_leds)(struct ieee80211_hw *hw);
- void (*deinit_sw_leds)(struct ieee80211_hw *hw);
- u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
- void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
- u32 data);
- u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
- u32 regaddr, u32 bitmask);
- void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
- u32 regaddr, u32 bitmask, u32 data);
- void (*linked_set_reg)(struct ieee80211_hw *hw);
- void (*chk_switch_dmdp)(struct ieee80211_hw *hw);
- void (*dualmac_easy_concurrent)(struct ieee80211_hw *hw);
- void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
- bool (*phy_rf6052_config)(struct ieee80211_hw *hw);
- void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw,
- u8 *powerlevel);
- void (*phy_rf6052_set_ofdm_txpower)(struct ieee80211_hw *hw,
- u8 *ppowerlevel, u8 channel);
- bool (*config_bb_with_headerfile)(struct ieee80211_hw *hw,
- u8 configtype);
- bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw,
- u8 configtype);
- void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t);
- void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw);
- void (*dm_dynamic_txpower)(struct ieee80211_hw *hw);
- void (*c2h_command_handle)(struct ieee80211_hw *hw);
- void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw,
- bool mstate);
- void (*bt_coex_off_before_lps)(struct ieee80211_hw *hw);
- void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id,
- u32 cmd_len, u8 *p_cmdbuffer);
- void (*set_default_port_id_cmd)(struct ieee80211_hw *hw);
- bool (*get_btc_status)(void);
- bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
- u32 (*rx_command_packet)(struct ieee80211_hw *hw,
- const struct rtl_stats *status,
- struct sk_buff *skb);
- void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
- struct rtl_wow_pattern *rtl_pattern,
- u8 index);
- u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
- void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len,
- u8 *val);
- /* ops for halmac cb */
- bool (*halmac_cb_init_mac_register)(struct rtl_priv *rtlpriv);
- bool (*halmac_cb_init_bb_rf_register)(struct rtl_priv *rtlpriv);
- bool (*halmac_cb_write_data_rsvd_page)(struct rtl_priv *rtlpriv,
- u8 *buf, u32 size);
- bool (*halmac_cb_write_data_h2c)(struct rtl_priv *rtlpriv, u8 *buf,
- u32 size);
- /* ops for phydm cb */
- u8 (*get_txpower_index)(struct ieee80211_hw *hw, u8 path,
- u8 rate, u8 bandwidth, u8 channel);
- void (*set_tx_power_index_by_rs)(struct ieee80211_hw *hw,
- u8 channel, u8 path,
- enum rate_section rs);
- void (*store_tx_power_by_rate)(struct ieee80211_hw *hw,
- u32 band, u32 rfpath,
- u32 txnum, u32 regaddr,
- u32 bitmask, u32 data);
- void (*phy_set_txpower_limit)(struct ieee80211_hw *hw, u8 *pregulation,
- u8 *pband, u8 *pbandwidth,
- u8 *prate_section, u8 *prf_path,
- u8 *pchannel, u8 *ppower_limit);
-};
-
-struct rtl_intf_ops {
- /*com */
- void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
- int (*adapter_start)(struct ieee80211_hw *hw);
- void (*adapter_stop)(struct ieee80211_hw *hw);
- bool (*check_buddy_priv)(struct ieee80211_hw *hw,
- struct rtl_priv **buddy_priv);
-
- int (*adapter_tx)(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- struct sk_buff *skb,
- struct rtl_tcb_desc *ptcb_desc);
- void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
- int (*reset_trx_ring)(struct ieee80211_hw *hw);
- bool (*waitq_insert)(struct ieee80211_hw *hw,
- struct ieee80211_sta *sta,
- struct sk_buff *skb);
-
- /*pci */
- void (*disable_aspm)(struct ieee80211_hw *hw);
- void (*enable_aspm)(struct ieee80211_hw *hw);
-
- /*usb */
-};
-
-struct rtl_mod_params {
- /* default: 0,0 */
- u64 debug_mask;
- /* default: 0 = using hardware encryption */
- bool sw_crypto;
-
- /* default: 0 = DBG_EMERG (0)*/
- int debug_level;
-
- /* default: 1 = using no linked power save */
- bool inactiveps;
-
- /* default: 1 = using linked sw power save */
- bool swctrl_lps;
-
- /* default: 1 = using linked fw power save */
- bool fwctrl_lps;
-
- /* default: 0 = not using MSI interrupts mode
- * submodules should set their own default value
- */
- bool msi_support;
-
- /* default: 0 = dma 32 */
- bool dma64;
-
- /* default: 1 = enable aspm */
- int aspm_support;
-
- /* default 0: 1 means disable */
- bool disable_watchdog;
-
- /* default 0: 1 means do not disable interrupts */
- bool int_clear;
-
- /* select antenna */
- int ant_sel;
-};
-
-struct rtl_hal_usbint_cfg {
- /* data - rx */
- u32 in_ep_num;
- u32 rx_urb_num;
- u32 rx_max_size;
-
- /* op - rx */
- void (*usb_rx_hdl)(struct ieee80211_hw *hw, struct sk_buff *skb);
- void (*usb_rx_segregate_hdl)(struct ieee80211_hw *hw,
- struct sk_buff *skb,
- struct sk_buff_head *skbh);
-
- /* tx */
- void (*usb_tx_cleanup)(struct ieee80211_hw *hw, struct sk_buff *skb);
- int (*usb_tx_post_hdl)(struct ieee80211_hw *hw, struct urb *urb,
- struct sk_buff *skb);
- struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *hw,
- struct sk_buff_head *skbh);
-
- /* endpoint mapping */
- int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
- u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
-};
-
-struct rtl_hal_cfg {
- u8 bar_id;
- bool write_readback;
- char *name;
- char *alt_fw_name;
- struct rtl_hal_ops *ops;
- struct rtl_mod_params *mod_params;
- struct rtl_hal_usbint_cfg *usb_interface_cfg;
- enum rtl_spec_ver spec_ver;
-
- /* this map used for some registers or vars
- * defined int HAL but used in MAIN
- */
- u32 maps[RTL_VAR_MAP_MAX];
-
-};
-
-struct rtl_locks {
- /* mutex */
- struct mutex conf_mutex;
- struct mutex ips_mutex; /* mutex for enter/leave IPS */
- struct mutex lps_mutex; /* mutex for enter/leave LPS */
-
- /*spin lock */
- spinlock_t irq_th_lock;
- spinlock_t h2c_lock;
- spinlock_t rf_ps_lock;
- spinlock_t rf_lock;
- spinlock_t waitq_lock;
- spinlock_t entry_list_lock;
- spinlock_t usb_lock;
- spinlock_t c2hcmd_lock;
- spinlock_t scan_list_lock; /* lock for the scan list */
-
- /*FW clock change */
- spinlock_t fw_ps_lock;
-
- /*Dual mac*/
- spinlock_t cck_and_rw_pagea_lock;
-
- spinlock_t iqk_lock;
-};
-
-struct rtl_works {
- struct ieee80211_hw *hw;
-
- /*timer */
- struct timer_list watchdog_timer;
- struct timer_list dualmac_easyconcurrent_retrytimer;
- struct timer_list fw_clockoff_timer;
- struct timer_list fast_antenna_training_timer;
- /*task */
- struct tasklet_struct irq_tasklet;
- struct tasklet_struct irq_prepare_bcn_tasklet;
-
- /*work queue */
- struct workqueue_struct *rtl_wq;
- struct delayed_work watchdog_wq;
- struct delayed_work ips_nic_off_wq;
- struct delayed_work c2hcmd_wq;
-
- /* For SW LPS */
- struct delayed_work ps_work;
- struct delayed_work ps_rfon_wq;
- struct delayed_work fwevt_wq;
-
- struct work_struct lps_change_work;
- struct work_struct fill_h2c_cmd;
-};
-
-struct rtl_debug {
- /* add for debug */
- struct dentry *debugfs_dir;
- char debugfs_name[20];
-
- char *msg_buf;
-};
-
-#define MIMO_PS_STATIC 0
-#define MIMO_PS_DYNAMIC 1
-#define MIMO_PS_NOLIMIT 3
-
-struct rtl_dualmac_easy_concurrent_ctl {
- enum band_type currentbandtype_backfordmdp;
- bool close_bbandrf_for_dmsp;
- bool change_to_dmdp;
- bool change_to_dmsp;
- bool switch_in_process;
-};
-
-struct rtl_dmsp_ctl {
- bool activescan_for_slaveofdmsp;
- bool scan_for_anothermac_fordmsp;
- bool scan_for_itself_fordmsp;
- bool writedig_for_anothermacofdmsp;
- u32 curdigvalue_for_anothermacofdmsp;
- bool changecckpdstate_for_anothermacofdmsp;
- u8 curcckpdstate_for_anothermacofdmsp;
- bool changetxhighpowerlvl_for_anothermacofdmsp;
- u8 curtxhighlvl_for_anothermacofdmsp;
- long rssivalmin_for_anothermacofdmsp;
-};
-
-struct ps_t {
- u8 pre_ccastate;
- u8 cur_ccasate;
- u8 pre_rfstate;
- u8 cur_rfstate;
- u8 initialize;
- long rssi_val_min;
-};
-
-struct dig_t {
- u32 rssi_lowthresh;
- u32 rssi_highthresh;
- u32 fa_lowthresh;
- u32 fa_highthresh;
- long last_min_undec_pwdb_for_dm;
- long rssi_highpower_lowthresh;
- long rssi_highpower_highthresh;
- u32 recover_cnt;
- u32 pre_igvalue;
- u32 cur_igvalue;
- long rssi_val;
- u8 dig_enable_flag;
- u8 dig_ext_port_stage;
- u8 dig_algorithm;
- u8 dig_twoport_algorithm;
- u8 dig_dbgmode;
- u8 dig_slgorithm_switch;
- u8 cursta_cstate;
- u8 presta_cstate;
- u8 curmultista_cstate;
- u8 stop_dig;
- s8 back_val;
- s8 back_range_max;
- s8 back_range_min;
- u8 rx_gain_max;
- u8 rx_gain_min;
- u8 min_undec_pwdb_for_dm;
- u8 rssi_val_min;
- u8 pre_cck_cca_thres;
- u8 cur_cck_cca_thres;
- u8 pre_cck_pd_state;
- u8 cur_cck_pd_state;
- u8 pre_cck_fa_state;
- u8 cur_cck_fa_state;
- u8 pre_ccastate;
- u8 cur_ccasate;
- u8 large_fa_hit;
- u8 forbidden_igi;
- u8 dig_state;
- u8 dig_highpwrstate;
- u8 cur_sta_cstate;
- u8 pre_sta_cstate;
- u8 cur_ap_cstate;
- u8 pre_ap_cstate;
- u8 cur_pd_thstate;
- u8 pre_pd_thstate;
- u8 cur_cs_ratiostate;
- u8 pre_cs_ratiostate;
- u8 backoff_enable_flag;
- s8 backoffval_range_max;
- s8 backoffval_range_min;
- u8 dig_min_0;
- u8 dig_min_1;
- u8 bt30_cur_igi;
- bool media_connect_0;
- bool media_connect_1;
-
- u32 antdiv_rssi_max;
- u32 rssi_max;
-};
-
-struct rtl_global_var {
- /* from this list we can get
- * other adapter's rtl_priv
- */
- struct list_head glb_priv_list;
- spinlock_t glb_list_lock;
-};
-
-#define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
-
-struct rtl_btc_info {
- u8 bt_type;
- u8 btcoexist;
- u8 ant_num;
- u8 single_ant_path;
-
- u8 ap_num;
- bool in_4way;
- unsigned long in_4way_ts;
-};
-
-struct bt_coexist_info {
- struct rtl_btc_ops *btc_ops;
- struct rtl_btc_info btc_info;
- /* btc context */
- void *btc_context;
- void *wifi_only_context;
- /* EEPROM BT info. */
- u8 eeprom_bt_coexist;
- u8 eeprom_bt_type;
- u8 eeprom_bt_ant_num;
- u8 eeprom_bt_ant_isol;
- u8 eeprom_bt_radio_shared;
-
- u8 bt_coexistence;
- u8 bt_ant_num;
- u8 bt_coexist_type;
- u8 bt_state;
- u8 bt_cur_state; /* 0:on, 1:off */
- u8 bt_ant_isolation; /* 0:good, 1:bad */
- u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
- u8 bt_service;
- u8 bt_radio_shared_type;
- u8 bt_rfreg_origin_1e;
- u8 bt_rfreg_origin_1f;
- u8 bt_rssi_state;
- u32 ratio_tx;
- u32 ratio_pri;
- u32 bt_edca_ul;
- u32 bt_edca_dl;
-
- bool init_set;
- bool bt_busy_traffic;
- bool bt_traffic_mode_set;
- bool bt_non_traffic_mode_set;
-
- bool fw_coexist_all_off;
- bool sw_coexist_all_off;
- bool hw_coexist_all_off;
- u32 cstate;
- u32 previous_state;
- u32 cstate_h;
- u32 previous_state_h;
-
- u8 bt_pre_rssi_state;
- u8 bt_pre_rssi_state1;
-
- u8 reg_bt_iso;
- u8 reg_bt_sco;
- bool balance_on;
- u8 bt_active_zero_cnt;
- bool cur_bt_disabled;
- bool pre_bt_disabled;
-
- u8 bt_profile_case;
- u8 bt_profile_action;
- bool bt_busy;
- bool hold_for_bt_operation;
- u8 lps_counter;
-};
-
-struct rtl_btc_ops {
- void (*btc_init_variables)(struct rtl_priv *rtlpriv);
- void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
- void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
- void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv);
- void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
- void (*btc_init_hw_config)(struct rtl_priv *rtlpriv);
- void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
- void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type);
- void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
- void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype);
- void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
- u8 scantype);
- void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action);
- void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv,
- enum rt_media_status mstatus);
- void (*btc_periodical)(struct rtl_priv *rtlpriv);
- void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
- void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv,
- u8 *tmp_buf, u8 length);
- void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
- u8 *tmp_buf, u8 length);
- bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv);
- bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv);
- bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv);
- void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
- u8 pkt_type);
- void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
- bool scanning);
- void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
- u8 type, bool scanning);
- void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
- struct seq_file *m);
- void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
- u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
- u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
- bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
- void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
- u8 *ctrl_agg_size, u8 *agg_size);
- bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
-};
-
-struct rtl_halmac_ops {
- int (*halmac_init_adapter)(struct rtl_priv *rtlpriv);
- int (*halmac_deinit_adapter)(struct rtl_priv *rtlpriv);
- int (*halmac_init_hal)(struct rtl_priv *rtlpriv);
- int (*halmac_deinit_hal)(struct rtl_priv *rtlpriv);
- int (*halmac_poweron)(struct rtl_priv *rtlpriv);
- int (*halmac_poweroff)(struct rtl_priv *rtlpriv);
-
- int (*halmac_phy_power_switch)(struct rtl_priv *rtlpriv, u8 enable);
- int (*halmac_set_mac_address)(struct rtl_priv *rtlpriv, u8 hwport,
- u8 *addr);
- int (*halmac_set_bssid)(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr);
-
- int (*halmac_get_physical_efuse_size)(struct rtl_priv *rtlpriv,
- u32 *size);
- int (*halmac_read_physical_efuse_map)(struct rtl_priv *rtlpriv,
- u8 *map, u32 size);
- int (*halmac_get_logical_efuse_size)(struct rtl_priv *rtlpriv,
- u32 *size);
- int (*halmac_read_logical_efuse_map)(struct rtl_priv *rtlpriv, u8 *map,
- u32 size);
-
- int (*halmac_set_bandwidth)(struct rtl_priv *rtlpriv, u8 channel,
- u8 pri_ch_idx, u8 bw);
-
- int (*halmac_c2h_handle)(struct rtl_priv *rtlpriv, u8 *c2h, u32 size);
-
- int (*halmac_chk_txdesc)(struct rtl_priv *rtlpriv, u8 *txdesc,
- u32 size);
-};
-
-struct rtl_halmac_indicator {
- struct completion *comp;
- u32 wait_ms;
-
- u8 *buffer;
- u32 buf_size;
- u32 ret_size;
- u32 status;
-};
-
-struct rtl_halmac {
- struct rtl_halmac_ops *ops; /* halmac ops (halmac.ko own this object) */
- void *internal; /* internal context of halmac, i.e. PHALMAC_ADAPTER */
- struct rtl_halmac_indicator *indicator; /* size=10 */
-
- /* flags */
- /*
- * send_general_info
- * 0: no need to call halmac_send_general_info()
- * 1: need to call halmac_send_general_info()
- */
- u8 send_general_info;
-};
-
-struct rtl_phydm_params {
- u8 mp_chip; /* 1: MP chip, 0: test chip */
- u8 fab_ver; /* 0: TSMC, 1: UMC, ...*/
- u8 cut_ver; /* 0: A, 1: B, ..., 10: K */
- u8 efuse0x3d7; /* default: 0xff */
- u8 efuse0x3d8; /* default: 0xff */
-};
-
-struct rtl_phydm_ops {
- /* init/deinit priv */
- int (*phydm_init_priv)(struct rtl_priv *rtlpriv,
- struct rtl_phydm_params *params);
- int (*phydm_deinit_priv)(struct rtl_priv *rtlpriv);
- bool (*phydm_load_txpower_by_rate)(struct rtl_priv *rtlpriv);
- bool (*phydm_load_txpower_limit)(struct rtl_priv *rtlpriv);
-
- /* init hw */
- int (*phydm_init_dm)(struct rtl_priv *rtlpriv);
- int (*phydm_deinit_dm)(struct rtl_priv *rtlpriv);
- int (*phydm_reset_dm)(struct rtl_priv *rtlpriv);
- bool (*phydm_parameter_init)(struct rtl_priv *rtlpriv, bool post);
- bool (*phydm_phy_bb_config)(struct rtl_priv *rtlpriv);
- bool (*phydm_phy_rf_config)(struct rtl_priv *rtlpriv);
- bool (*phydm_phy_mac_config)(struct rtl_priv *rtlpriv);
- bool (*phydm_trx_mode)(struct rtl_priv *rtlpriv,
- enum radio_mask tx_path, enum radio_mask rx_path,
- bool is_tx2_path);
- /* watchdog */
- bool (*phydm_watchdog)(struct rtl_priv *rtlpriv);
-
- /* channel */
- bool (*phydm_switch_band)(struct rtl_priv *rtlpriv, u8 central_ch);
- bool (*phydm_switch_channel)(struct rtl_priv *rtlpriv, u8 central_ch);
- bool (*phydm_switch_bandwidth)(struct rtl_priv *rtlpriv,
- u8 primary_ch_idx,
- enum ht_channel_width width);
- bool (*phydm_iq_calibrate)(struct rtl_priv *rtlpriv);
- bool (*phydm_clear_txpowertracking_state)(struct rtl_priv *rtlpriv);
- bool (*phydm_pause_dig)(struct rtl_priv *rtlpriv, bool pause);
-
- /* read/write reg */
- u32 (*phydm_read_rf_reg)(struct rtl_priv *rtlpriv,
- enum radio_path rfpath,
- u32 addr, u32 mask);
- bool (*phydm_write_rf_reg)(struct rtl_priv *rtlpriv,
- enum radio_path rfpath,
- u32 addr, u32 mask, u32 data);
- u8 (*phydm_read_txagc)(struct rtl_priv *rtlpriv,
- enum radio_path rfpath, u8 hw_rate);
- bool (*phydm_write_txagc)(struct rtl_priv *rtlpriv, u32 power_index,
- enum radio_path rfpath, u8 hw_rate);
-
- /* RX */
- bool (*phydm_c2h_content_parsing)(struct rtl_priv *rtlpriv, u8 cmd_id,
- u8 cmd_len, u8 *content);
- bool (*phydm_query_phy_status)(struct rtl_priv *rtlpriv, u8 *phystrpt,
- struct ieee80211_hdr *hdr,
- struct rtl_stats *pstatus);
-
- /* TX */
- u8 (*phydm_rate_id_mapping)(struct rtl_priv *rtlpriv,
- enum wireless_mode wireless_mode,
- enum rf_type rf_type,
- enum ht_channel_width bw);
- bool (*phydm_get_ra_bitmap)(struct rtl_priv *rtlpriv,
- enum wireless_mode wireless_mode,
- enum rf_type rf_type,
- enum ht_channel_width bw,
- u8 tx_rate_level, /* 0~6 */
- u32 *tx_bitmap_msb,
- u32 *tx_bitmap_lsb);
-
- /* STA */
- bool (*phydm_add_sta)(struct rtl_priv *rtlpriv,
- struct ieee80211_sta *sta);
- bool (*phydm_del_sta)(struct rtl_priv *rtlpriv,
- struct ieee80211_sta *sta);
-
- /* BTC */
- u32 (*phydm_get_version)(struct rtl_priv *rtlpriv);
- bool (*phydm_modify_ra_pcr_threshold)(struct rtl_priv *rtlpriv,
- u8 ra_offset_direction,
- u8 ra_threshold_offset);
- u32 (*phydm_query_counter)(struct rtl_priv *rtlpriv,
- const char *info_type);
-
- /* debug */
- bool (*phydm_debug_cmd)(struct rtl_priv *rtlpriv, char *in, u32 in_len,
- char *out, u32 out_len);
-
-};
-
-struct rtl_phydm {
- struct rtl_phydm_ops *ops;/* phydm ops (phydm_mod.ko own this object) */
- void *internal; /* internal context of phydm, i.e. PHY_DM_STRUCT */
-
- u8 adaptivity_en;
- /* debug */
- u16 forced_data_rate;
- u8 forced_igi_lb;
- u8 antenna_test;
-};
-
-struct proxim {
- bool proxim_on;
-
- void *proximity_priv;
- int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
- struct sk_buff *skb);
- u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
-};
-
-struct rtl_c2hcmd {
- struct list_head list;
- u8 tag;
- u8 len;
- u8 *val;
-};
-
-struct rtl_bssid_entry {
- struct list_head list;
- u8 bssid[ETH_ALEN];
- u32 age;
-};
-
-struct rtl_scan_list {
- int num;
- struct list_head list; /* sort by age */
-};
-
-struct rtl_priv {
- struct ieee80211_hw *hw;
- struct completion firmware_loading_complete;
- struct list_head list;
- struct rtl_priv *buddy_priv;
- struct rtl_global_var *glb_var;
- struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
- struct rtl_dmsp_ctl dmsp_ctl;
- struct rtl_locks locks;
- struct rtl_works works;
- struct rtl_mac mac80211;
- struct rtl_hal rtlhal;
- struct rtl_regulatory regd;
- struct rtl_rfkill rfkill;
- struct rtl_io io;
- struct rtl_phy phy;
- struct rtl_dm dm;
- struct rtl_security sec;
- struct rtl_efuse efuse;
- struct rtl_led_ctl ledctl;
- struct rtl_tx_report tx_report;
- struct rtl_scan_list scan_list;
- struct rtl_ps_ctl psc;
- struct rate_adaptive ra;
- struct dynamic_primary_cca primarycca;
- struct wireless_stats stats;
- struct rt_link_detect link_info;
- struct false_alarm_statistics falsealm_cnt;
- struct rtl_rate_priv *rate_priv;
- /* sta entry list for ap adhoc or mesh */
- struct list_head entry_list;
- /* c2hcmd list for kthread level access */
- struct list_head c2hcmd_list;
- struct rtl_debug dbg;
- int max_fw_size;
-
- /*hal_cfg : for diff cards
- *intf_ops : for diff interface usb/pcie
- */
- struct rtl_hal_cfg *cfg;
- const struct rtl_intf_ops *intf_ops;
-
- /* this var will be set by set_bit,
- * and was used to indicate status of
- * interface or hardware
- */
- unsigned long status;
-
- /* tables for dm */
- struct dig_t dm_digtable;
- struct ps_t dm_pstable;
-
- u32 reg_874;
- u32 reg_c70;
- u32 reg_85c;
- u32 reg_a74;
- bool reg_init; /* true if regs saved */
- bool bt_operation_on;
- __le32 *usb_data;
- int usb_data_index;
- bool initialized;
- bool enter_ps; /* true when entering PS */
- u8 rate_mask[5];
-
- /* intel Proximity, should be alloc mem
- * in intel Proximity module and can only
- * be used in intel Proximity mode
- */
- struct proxim proximity;
-
- /*for bt coexist use*/
- struct bt_coexist_info btcoexist;
-
- /* halmac for newer IC. (e.g. 8822B) */
- struct rtl_halmac halmac;
-
- /* phydm for newer IC. (e.g. 8822B) */
- struct rtl_phydm phydm;
-
- /* separate 92ee from other ICs,
- * 92ee use new trx flow.
- */
- bool use_new_trx_flow;
-
-#ifdef CONFIG_PM
- struct wiphy_wowlan_support wowlan;
-#endif
- /* This must be the last item so
- * that it points to the data allocated
- * beyond this structure like:
- * rtl_pci_priv or rtl_usb_priv
- */
- u8 priv[0] __aligned(sizeof(void *));
-};
-
-#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
-#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
-#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
-#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
-#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
-
-/***************************************
- * Bluetooth Co-existence Related
- ***************************************/
-
-enum bt_ant_num {
- ANT_X2 = 0,
- ANT_X1 = 1,
-};
-
-enum bt_co_type {
- BT_2WIRE = 0,
- BT_ISSC_3WIRE = 1,
- BT_ACCEL = 2,
- BT_CSR_BC4 = 3,
- BT_CSR_BC8 = 4,
- BT_RTL8756 = 5,
- BT_RTL8723A = 6,
- BT_RTL8821A = 7,
- BT_RTL8723B = 8,
- BT_RTL8192E = 9,
- BT_RTL8812A = 11,
- BT_RTL8822B = 12,
-};
-
-enum bt_total_ant_num {
- ANT_TOTAL_X2 = 0,
- ANT_TOTAL_X1 = 1
-};
-
-enum bt_cur_state {
- BT_OFF = 0,
- BT_ON = 1,
-};
-
-enum bt_service_type {
- BT_SCO = 0,
- BT_A2DP = 1,
- BT_HID = 2,
- BT_HID_IDLE = 3,
- BT_SCAN = 4,
- BT_IDLE = 5,
- BT_OTHER_ACTION = 6,
- BT_BUSY = 7,
- BT_OTHERBUSY = 8,
- BT_PAN = 9,
-};
-
-enum bt_radio_shared {
- BT_RADIO_SHARED = 0,
- BT_RADIO_INDIVIDUAL = 1,
-};
-
-/****************************************
- * mem access macro define start
- * Call endian free function when
- * 1. Read/write packet content.
- * 2. Before write integer to IO.
- * 3. After read integer from IO.
- ***************************************/
-/* Convert little data endian to host ordering */
-#define EF1BYTE(_val) \
- ((u8)(_val))
-#define EF2BYTE(_val) \
- (le16_to_cpu(_val))
-#define EF4BYTE(_val) \
- (le32_to_cpu(_val))
-
-/* Read data from memory */
-#define READEF1BYTE(_ptr) \
- EF1BYTE(*((u8 *)(_ptr)))
-/* Read le16 data from memory and convert to host ordering */
-#define READEF2BYTE(_ptr) \
- EF2BYTE(*(_ptr))
-#define READEF4BYTE(_ptr) \
- EF4BYTE(*(_ptr))
-
-/* Create a bit mask
- * Examples:
- * BIT_LEN_MASK_32(0) => 0x00000000
- * BIT_LEN_MASK_32(1) => 0x00000001
- * BIT_LEN_MASK_32(2) => 0x00000003
- * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
- */
-#define BIT_LEN_MASK_32(__bitlen) \
- (0xFFFFFFFF >> (32 - (__bitlen)))
-#define BIT_LEN_MASK_16(__bitlen) \
- (0xFFFF >> (16 - (__bitlen)))
-#define BIT_LEN_MASK_8(__bitlen) \
- (0xFF >> (8 - (__bitlen)))
-
-/* Create an offset bit mask
- * Examples:
- * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
- * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
- */
-#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
- (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
-#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
- (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
-#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
- (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
-
-/*Description:
- * Return 4-byte value in host byte ordering from
- * 4-byte pointer in little-endian system.
- */
-#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
- (EF4BYTE(*((__le32 *)(__pstart))))
-#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
- (EF2BYTE(*((__le16 *)(__pstart))))
-#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
- (EF1BYTE(*((u8 *)(__pstart))))
-
-/* Description:
- * Translate subfield (continuous bits in little-endian) of 4-byte
- * value to host byte ordering.
- */
-#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
- ( \
- (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
- BIT_LEN_MASK_32(__bitlen) \
- )
-#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
- ( \
- (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
- BIT_LEN_MASK_16(__bitlen) \
- )
-#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
- ( \
- (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
- BIT_LEN_MASK_8(__bitlen) \
- )
-
-/* Description:
- * Mask subfield (continuous bits in little-endian) of 4-byte value
- * and return the result in 4-byte value in host byte ordering.
- */
-#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
- ( \
- LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
- (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
- )
-#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
- ( \
- LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
- (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
- )
-#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
- ( \
- LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
- (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
- )
-
-/* Description:
- * Set subfield of little-endian 4-byte value to specified value.
- */
-#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
- (*((__le32 *)(__pstart)) = \
- cpu_to_le32( \
- LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
- ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
- ))
-#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
- (*((__le16 *)(__pstart)) = \
- cpu_to_le16( \
- LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
- ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
- ))
-#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
- (*((u8 *)(__pstart)) = EF1BYTE \
- ( \
- LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
- ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
- ))
-
-#define N_BYTE_ALIGNMENT(__value, __alignment) ((__alignment == 1) ? \
- (__value) : (((__value + __alignment - 1) / \
- __alignment) * __alignment))
-
-/****************************************
- * mem access macro define end
- ****************************************/
-
-#define byte(x, n) ((x >> (8 * n)) & 0xff)
-
-#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
-#define RTL_WATCH_DOG_TIME 2000
-#define MSECS(t) msecs_to_jiffies(t)
-#define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
-#define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
-#define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
-#define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
-#define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
-
-#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
-#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
-#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
-/*NIC halt, re-initialize hw parameters*/
-#define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
-#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
-#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
-/*Always enable ASPM and Clock Req in initialization.*/
-#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
-/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
-#define RT_PS_LEVEL_ASPM BIT(7)
-/*When LPS is on, disable 2R if no packet is received or transmitted.*/
-#define RT_RF_LPS_DISALBE_2R BIT(30)
-#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
-#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
- ((ppsc->cur_ps_level & _ps_flg) ? true : false)
-#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
- (ppsc->cur_ps_level &= (~(_ps_flg)))
-#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
- (ppsc->cur_ps_level |= _ps_flg)
-
-#define container_of_dwork_rtl(x, y, z) \
- container_of(to_delayed_work(x), y, z)
-
-#define FILL_OCTET_STRING(_os, _octet, _len) \
- (_os).octet = (u8 *)(_octet); \
- (_os).length = (_len)
-
-#define CP_MACADDR(des, src) \
- ((des)[0] = (src)[0], (des)[1] = (src)[1],\
- (des)[2] = (src)[2], (des)[3] = (src)[3],\
- (des)[4] = (src)[4], (des)[5] = (src)[5])
-
-#define LDPC_HT_ENABLE_RX BIT(0)
-#define LDPC_HT_ENABLE_TX BIT(1)
-#define LDPC_HT_TEST_TX_ENABLE BIT(2)
-#define LDPC_HT_CAP_TX BIT(3)
-
-#define STBC_HT_ENABLE_RX BIT(0)
-#define STBC_HT_ENABLE_TX BIT(1)
-#define STBC_HT_TEST_TX_ENABLE BIT(2)
-#define STBC_HT_CAP_TX BIT(3)
-
-#define LDPC_VHT_ENABLE_RX BIT(0)
-#define LDPC_VHT_ENABLE_TX BIT(1)
-#define LDPC_VHT_TEST_TX_ENABLE BIT(2)
-#define LDPC_VHT_CAP_TX BIT(3)
-
-#define STBC_VHT_ENABLE_RX BIT(0)
-#define STBC_VHT_ENABLE_TX BIT(1)
-#define STBC_VHT_TEST_TX_ENABLE BIT(2)
-#define STBC_VHT_CAP_TX BIT(3)
-
-extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
-
-extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
-
-static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
-{
- return rtlpriv->io.read8_sync(rtlpriv, addr);
-}
-
-static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
-{
- return rtlpriv->io.read16_sync(rtlpriv, addr);
-}
-
-static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
-{
- return rtlpriv->io.read32_sync(rtlpriv, addr);
-}
-
-static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
-{
- rtlpriv->io.write8_async(rtlpriv, addr, val8);
-
- if (rtlpriv->cfg->write_readback)
- rtlpriv->io.read8_sync(rtlpriv, addr);
-}
-
-static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
- u32 addr, u32 val8)
-{
- struct rtl_priv *rtlpriv = rtl_priv(hw);
-
- rtl_write_byte(rtlpriv, addr, (u8)val8);
-}
-
-static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
-{
- rtlpriv->io.write16_async(rtlpriv, addr, val16);
-
- if (rtlpriv->cfg->write_readback)
- rtlpriv->io.read16_sync(rtlpriv, addr);
-}
-
-static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
- u32 addr, u32 val32)
-{
- rtlpriv->io.write32_async(rtlpriv, addr, val32);
-
- if (rtlpriv->cfg->write_readback)
- rtlpriv->io.read32_sync(rtlpriv, addr);
-}
-
-static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
- u32 regaddr, u32 bitmask)
-{
- struct rtl_priv *rtlpriv = hw->priv;
-
- return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
-}
-
-static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
- u32 bitmask, u32 data)
-{
- struct rtl_priv *rtlpriv = hw->priv;
-
- rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
-}
-
-static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
- u32 regaddr, u32 data)
-{
- rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
-}
-
-static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
- enum radio_path rfpath, u32 regaddr,
- u32 bitmask)
-{
- struct rtl_priv *rtlpriv = hw->priv;
-
- return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
-}
-
-static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
- enum radio_path rfpath, u32 regaddr,
- u32 bitmask, u32 data)
-{
- struct rtl_priv *rtlpriv = hw->priv;
-
- rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
-}
-
-static inline bool is_hal_stop(struct rtl_hal *rtlhal)
-{
- return (rtlhal->state == _HAL_STATE_STOP);
-}
-
-static inline void set_hal_start(struct rtl_hal *rtlhal)
-{
- rtlhal->state = _HAL_STATE_START;
-}
-
-static inline void set_hal_stop(struct rtl_hal *rtlhal)
-{
- rtlhal->state = _HAL_STATE_STOP;
-}
-
-static inline u8 get_rf_type(struct rtl_phy *rtlphy)
-{
- return rtlphy->rf_type;
-}
-
-static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
-{
- return (struct ieee80211_hdr *)(skb->data);
-}
-
-static inline __le16 rtl_get_fc(struct sk_buff *skb)
-{
- return rtl_get_hdr(skb)->frame_control;
-}
-
-static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
-{
- return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
-}
-
-static inline u16 rtl_get_tid(struct sk_buff *skb)
-{
- return rtl_get_tid_h(rtl_get_hdr(skb));
-}
-
-static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- const u8 *bssid)
-{
- return ieee80211_find_sta(vif, bssid);
-}
-
-static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
- u8 *mac_addr)
-{
- struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-
- return ieee80211_find_sta(mac->vif, mac_addr);
-}
-
-#endif
projects / openwrt / staging / blogic.git / commitdiff