fix clocks bits for BCM6345

SVN-Revision: 33888

diff --git a/target/linux/brcm63xx/patches-3.3/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch b/target/linux/brcm63xx/patches-3.3/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch
new file mode 100644 (file)
index 0000000..b33a845
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch
@@ -0,0 +1,34 @@
+[PATCH] MIPS: BCM63XX: fix BCM6345 clock bits shifting
+
+BCM6345 has an intermediate 16-bits wide test control register between the
+peripheral identifier function, and its clock control register is only 16-bits
+wide contrary to other platforms where it is 32-bits wide. By shifting all
+clocks bits by 16-bits to the left we ensure they get written to the proper
+clock control register, without adding specific BCM6345 handling in the clock
+code.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -53,13 +53,13 @@
+                                       CKCTL_6338_SAR_EN |             \
+                                       CKCTL_6338_SPI_EN)
+ 
+-#define CKCTL_6345_CPU_EN             (1 << 0)
+-#define CKCTL_6345_BUS_EN             (1 << 1)
+-#define CKCTL_6345_EBI_EN             (1 << 2)
+-#define CKCTL_6345_UART_EN            (1 << 3)
+-#define CKCTL_6345_ADSLPHY_EN         (1 << 4)
+-#define CKCTL_6345_ENET_EN            (1 << 7)
+-#define CKCTL_6345_USBH_EN            (1 << 8)
++#define CKCTL_6345_CPU_EN             (1 << 16)
++#define CKCTL_6345_BUS_EN             (1 << 17)
++#define CKCTL_6345_EBI_EN             (1 << 18)
++#define CKCTL_6345_UART_EN            (1 << 19)
++#define CKCTL_6345_ADSLPHY_EN         (1 << 20)
++#define CKCTL_6345_ENET_EN            (1 << 23)
++#define CKCTL_6345_USBH_EN            (1 << 24)
+ 
+ #define CKCTL_6345_ALL_SAFE_EN                (CKCTL_6345_ENET_EN |   \
+                                       CKCTL_6345_USBH_EN |    \