drm/tegra: Renaming DP training vswing pre emph defines

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 708f783ead47682f8ef76e17ebc435a1850f9eb6..d6b55e3e3716c8bcaf9e10d2f6625fbfee981797 100644 (file)
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -533,9 +533,9 @@ int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
 
        for (i = 0; i < link->num_lanes; i++)
                values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
-                           DP_TRAIN_PRE_EMPHASIS_0 |
+                           DP_TRAIN_PRE_EMPH_LEVEL_0 |
                            DP_TRAIN_MAX_SWING_REACHED |
-                           DP_TRAIN_VOLTAGE_SWING_400;
+                           DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
        err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
                                link->num_lanes);