drm/amdgpu: correct SMU11 SYSPLL0 clock id values

The SMU11 SYSPLL0 clock ids were assigned wrong values.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index c6c1666ac1201c65a5646eb66aa6a88c2a592509..092d800b703a7627a2b98fdda7be54b5b6f7ff11 100644 (file)
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -2026,17 +2026,15 @@ enum atom_smu11_syspll_id {
   SMU11_SYSPLL3_1_ID          = 6,
 };
 
-
 enum atom_smu11_syspll0_clock_id {
-  SMU11_SYSPLL0_SOCCLK_ID   = 0,       //      SOCCLK
-  SMU11_SYSPLL0_MP0CLK_ID   = 1,       //      MP0CLK
-  SMU11_SYSPLL0_DCLK_ID     = 2,       //      DCLK
-  SMU11_SYSPLL0_VCLK_ID     = 3,       //      VCLK
-  SMU11_SYSPLL0_ECLK_ID     = 4,       //      ECLK
+  SMU11_SYSPLL0_ECLK_ID     = 0,       //      ECLK
+  SMU11_SYSPLL0_SOCCLK_ID   = 1,       //      SOCCLK
+  SMU11_SYSPLL0_MP0CLK_ID   = 2,       //      MP0CLK
+  SMU11_SYSPLL0_DCLK_ID     = 3,       //      DCLK
+  SMU11_SYSPLL0_VCLK_ID     = 4,       //      VCLK
   SMU11_SYSPLL0_DCEFCLK_ID  = 5,       //      DCEFCLK
 };
 
-
 enum atom_smu11_syspll1_0_clock_id {
   SMU11_SYSPLL1_0_UCLKA_ID   = 0,       // UCLK_a
 };