core/rtw_ap.o \
core/rtw_cmd.o \
core/rtw_efuse.o \
- core/rtw_io.o \
core/rtw_ioctl_set.o \
core/rtw_ieee80211.o \
core/rtw_led.o \
u16 tmpV16;
if (PwrState == true) {
- rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
+ rtl8723au_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
/* 1.2V Power: From VDDON with Power
Cut(0x0000h[15]), defualt valid */
tmpV16 = rtl8723au_read16(padapter, REG_SYS_ISO_CTRL);
if (!(tmpV16 & PWC_EV12V)) {
tmpV16 |= PWC_EV12V;
- rtw_write16(padapter, REG_SYS_ISO_CTRL, tmpV16);
+ rtl8723au_write16(padapter, REG_SYS_ISO_CTRL, tmpV16);
}
/* Reset: 0x0000h[28], default valid */
tmpV16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
if (!(tmpV16 & FEN_ELDR)) {
tmpV16 |= FEN_ELDR;
- rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
+ rtl8723au_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
}
/* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock
tmpV16 = rtl8723au_read16(padapter, REG_SYS_CLKR);
if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
tmpV16 |= (LOADER_CLK_EN | ANA8M);
- rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
+ rtl8723au_write16(padapter, REG_SYS_CLKR, tmpV16);
}
if (bWrite == true) {
tempval = rtl8723au_read8(padapter, EFUSE_TEST + 3);
tempval &= 0x0F;
tempval |= (VOLTAGE_V25 << 4);
- rtw_write8(padapter, EFUSE_TEST + 3, (tempval | 0x80));
+ rtl8723au_write8(padapter, EFUSE_TEST + 3,
+ tempval | 0x80);
}
} else {
- rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
+ rtl8723au_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
if (bWrite == true) {
/* Disable LDO 2.5V after read/write action */
tempval = rtl8723au_read8(padapter, EFUSE_TEST + 3);
- rtw_write8(padapter, EFUSE_TEST + 3, (tempval & 0x7F));
+ rtl8723au_write8(padapter, EFUSE_TEST + 3,
+ tempval & 0x7F);
}
}
}
u16 retry;
/* Write Address */
- rtw_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff));
+ rtl8723au_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff));
readbyte = rtl8723au_read8(Adapter, EFUSE_CTRL+2);
- rtw_write8(Adapter, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
+ rtl8723au_write8(Adapter, EFUSE_CTRL+2,
+ ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
/* Write bit 32 0 */
readbyte = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
- rtw_write8(Adapter, EFUSE_CTRL+3, (readbyte & 0x7f));
+ rtl8723au_write8(Adapter, EFUSE_CTRL+3, readbyte & 0x7f);
/* Check bit 32 read-ready */
retry = 0;
{
/* Write E-fuse Register address bit0~7 */
temp = Address & 0xFF;
- rtw_write8(Adapter, EFUSE_CTRL+1, temp);
+ rtl8723au_write8(Adapter, EFUSE_CTRL+1, temp);
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+2);
/* Write E-fuse Register address bit8~9 */
temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
- rtw_write8(Adapter, EFUSE_CTRL+2, temp);
+ rtl8723au_write8(Adapter, EFUSE_CTRL+2, temp);
/* Write 0x30[31]= 0 */
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
temp = Bytetemp & 0x7F;
- rtw_write8(Adapter, EFUSE_CTRL+3, temp);
+ rtl8723au_write8(Adapter, EFUSE_CTRL+3, temp);
/* Wait Write-ready (0x30[31]= 1) */
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
if (Address < contentLen) /* E-fuse 512Byte */
{
- rtw_write8(Adapter, EFUSE_CTRL, Value);
+ rtl8723au_write8(Adapter, EFUSE_CTRL, Value);
/* Write E-fuse Register address bit0~7 */
temp = Address & 0xFF;
- rtw_write8(Adapter, EFUSE_CTRL+1, temp);
+ rtl8723au_write8(Adapter, EFUSE_CTRL+1, temp);
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+2);
/* Write E-fuse Register address bit8~9 */
temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
- rtw_write8(Adapter, EFUSE_CTRL+2, temp);
+ rtl8723au_write8(Adapter, EFUSE_CTRL+2, temp);
/* Write 0x30[31]= 1 */
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
temp = Bytetemp | 0x80;
- rtw_write8(Adapter, EFUSE_CTRL+3, temp);
+ rtl8723au_write8(Adapter, EFUSE_CTRL+3, temp);
/* Wait Write-ready (0x30[31]= 0) */
Bytetemp = rtl8723au_read8(Adapter, EFUSE_CTRL+3);
/* -----------------e-fuse reg ctrl --------------------------------- */
/* address */
- rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
- rtw_write8(pAdapter, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03)) |
+ rtl8723au_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
+ rtl8723au_write8(pAdapter, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03)) |
(rtl8723au_read8(pAdapter, EFUSE_CTRL+2)&0xFC));
- rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72);/* read cmd */
+ rtl8723au_write8(pAdapter, EFUSE_CTRL+3, 0x72);/* read cmd */
while(!(0x80 &rtl8723au_read8(pAdapter, EFUSE_CTRL+3)) && (tmpidx<100))
tmpidx++;
/* -----------------e-fuse reg ctrl --------------------------------- */
/* address */
- rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
- rtw_write8(pAdapter, EFUSE_CTRL+2,
+ rtl8723au_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff));
+ rtl8723au_write8(pAdapter, EFUSE_CTRL+2,
(rtl8723au_read8(pAdapter, EFUSE_CTRL+2)&0xFC)|(u8)((addr>>8)&0x03));
- rtw_write8(pAdapter, EFUSE_CTRL, data);/* data */
+ rtl8723au_write8(pAdapter, EFUSE_CTRL, data);/* data */
- rtw_write8(pAdapter, EFUSE_CTRL+3, 0xF2);/* write cmd */
+ rtl8723au_write8(pAdapter, EFUSE_CTRL+3, 0xF2);/* write cmd */
while((0x80 & rtl8723au_read8(pAdapter, EFUSE_CTRL+3)) &&
(tmpidx<100)) {
+++ /dev/null
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- ******************************************************************************/
-/*
-
-The purpose of rtw_io.c
-
-a. provides the API
-
-b. provides the protocol engine
-
-c. provides the software interface between caller and the hardware interface
-
-Compiler Flag Option:
-
-1. For USB:
- a. USE_ASYNC_IRP: Both sync/async operations are provided.
-
-jackson@realtek.com.tw
-
-*/
-
-#define _RTW_IO_C_
-#include <osdep_service.h>
-#include <drv_types.h>
-#include <rtw_io.h>
-#include <osdep_intf.h>
-
-#include <usb_ops.h>
-
-int _rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val)
-{
- struct _io_ops *io_ops = &adapter->io_ops;
- int ret;
-
- ret = io_ops->_write8(adapter, addr, val);
-
- if (ret < 0)
- return _FAIL;
- else
- return _SUCCESS;
-}
-
-int _rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val)
-{
- struct _io_ops *io_ops = &adapter->io_ops;
- int ret;
-
- ret = io_ops->_write16(adapter, addr, val);
-
- if (ret < 0)
- return _FAIL;
- else
- return _SUCCESS;
-}
-
-int _rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val)
-{
- struct _io_ops *io_ops = &adapter->io_ops;
- int ret;
-
- ret = io_ops->_write32(adapter, addr, val);
-
- if (ret < 0)
- return _FAIL;
- else
- return _SUCCESS;
-}
-
-int _rtw_writeN23a(struct rtw_adapter *adapter, u32 addr , u32 length , u8 *pdata)
-{
- struct _io_ops *io_ops = &adapter->io_ops;
- int ret;
-
- ret = io_ops->_writeN(adapter, addr, length, pdata);
-
- if (ret < 0)
- return _FAIL;
- else
- return _SUCCESS;
-}
mlmeext_joinbss_event_callback23a(padapter, 1);
/* restore Sequence No. */
- rtw_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn);
+ rtl8723au_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn);
sreset_restore_security_station(padapter);
}
/* Adjust CCK according to IQK result */
if (!pdmpriv->bCCKinCH14) {
- rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch1_Ch1323A[CCK_index][0]);
- rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch1_Ch1323A[CCK_index][1]);
- rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch1_Ch1323A[CCK_index][2]);
- rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch1_Ch1323A[CCK_index][3]);
- rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch1_Ch1323A[CCK_index][4]);
- rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch1_Ch1323A[CCK_index][5]);
- rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch1_Ch1323A[CCK_index][6]);
- rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch1_Ch1323A[CCK_index][7]);
+ rtl8723au_write8(Adapter, 0xa22, CCKSwingTable_Ch1_Ch1323A[CCK_index][0]);
+ rtl8723au_write8(Adapter, 0xa23, CCKSwingTable_Ch1_Ch1323A[CCK_index][1]);
+ rtl8723au_write8(Adapter, 0xa24, CCKSwingTable_Ch1_Ch1323A[CCK_index][2]);
+ rtl8723au_write8(Adapter, 0xa25, CCKSwingTable_Ch1_Ch1323A[CCK_index][3]);
+ rtl8723au_write8(Adapter, 0xa26, CCKSwingTable_Ch1_Ch1323A[CCK_index][4]);
+ rtl8723au_write8(Adapter, 0xa27, CCKSwingTable_Ch1_Ch1323A[CCK_index][5]);
+ rtl8723au_write8(Adapter, 0xa28, CCKSwingTable_Ch1_Ch1323A[CCK_index][6]);
+ rtl8723au_write8(Adapter, 0xa29, CCKSwingTable_Ch1_Ch1323A[CCK_index][7]);
} else {
- rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch1423A[CCK_index][0]);
- rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch1423A[CCK_index][1]);
- rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch1423A[CCK_index][2]);
- rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch1423A[CCK_index][3]);
- rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch1423A[CCK_index][4]);
- rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch1423A[CCK_index][5]);
- rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch1423A[CCK_index][6]);
- rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch1423A[CCK_index][7]);
+ rtl8723au_write8(Adapter, 0xa22, CCKSwingTable_Ch1423A[CCK_index][0]);
+ rtl8723au_write8(Adapter, 0xa23, CCKSwingTable_Ch1423A[CCK_index][1]);
+ rtl8723au_write8(Adapter, 0xa24, CCKSwingTable_Ch1423A[CCK_index][2]);
+ rtl8723au_write8(Adapter, 0xa25, CCKSwingTable_Ch1423A[CCK_index][3]);
+ rtl8723au_write8(Adapter, 0xa26, CCKSwingTable_Ch1423A[CCK_index][4]);
+ rtl8723au_write8(Adapter, 0xa27, CCKSwingTable_Ch1423A[CCK_index][5]);
+ rtl8723au_write8(Adapter, 0xa28, CCKSwingTable_Ch1423A[CCK_index][6]);
+ rtl8723au_write8(Adapter, 0xa29, CCKSwingTable_Ch1423A[CCK_index][7]);
}
if (is2T) {
{
u32 i;
- for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
- rtw_write8(pAdapter, MACReg[i], (u8)MACBackup[i]);
- }
- rtw_write32(pAdapter, MACReg[i], MACBackup[i]);
+ for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++)
+ rtl8723au_write8(pAdapter, MACReg[i], (u8)MACBackup[i]);
+
+ rtl8723au_write32(pAdapter, MACReg[i], MACBackup[i]);
}
static void _PHY_PathADDAOn(struct rtw_adapter *pAdapter, u32 *ADDAReg, bool isPathAOn, bool is2T)
{
u32 i = 0;
- rtw_write8(pAdapter, MACReg[i], 0x3F);
+ rtl8723au_write8(pAdapter, MACReg[i], 0x3F);
for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) {
- rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i] & ~BIT(3)));
+ rtl8723au_write8(pAdapter, MACReg[i],
+ (u8)(MACBackup[i] & ~BIT(3)));
}
- rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i] & ~BIT(5)));
+ rtl8723au_write8(pAdapter, MACReg[i], (u8)(MACBackup[i] & ~BIT(5)));
}
static void _PHY_PathAStandBy(struct rtw_adapter *pAdapter)
/* Check continuous TX and Packet TX */
tmpReg = rtl8723au_read8(pAdapter, 0xd03);
- if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
- rtw_write8(pAdapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */
- else /* Deal with Packet TX case */
- rtw_write8(pAdapter, REG_TXPAUSE, 0xFF); /* block all queues */
+ if ((tmpReg&0x70) != 0) {
+ /* Deal with contisuous TX case */
+ /* disable all continuous TX */
+ rtl8723au_write8(pAdapter, 0xd03, tmpReg&0x8F);
+ } else {
+ /* Deal with Packet TX case */
+ /* block all queues */
+ rtl8723au_write8(pAdapter, REG_TXPAUSE, 0xFF);
+ }
if ((tmpReg&0x70) != 0) {
/* 1. Read original RF mode */
/* Restore original situation */
if ((tmpReg&0x70) != 0) { /* Deal with contuous TX case */
/* Path-A */
- rtw_write8(pAdapter, 0xd03, tmpReg);
+ rtl8723au_write8(pAdapter, 0xd03, tmpReg);
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
/* Path-B */
if (is2T)
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
- } else { /* Deal with Packet TX case */
- rtw_write8(pAdapter, REG_TXPAUSE, 0x00);
- }
+ } else /* Deal with Packet TX case */
+ rtl8723au_write8(pAdapter, REG_TXPAUSE, 0x00);
}
/* Analog Pre-distortion calibration */
GET_PWR_CFG_MASK(PwrCfgCmd));
/* Write the value back to sytem register */
- rtw_write8(padapter, offset, value);
+ rtl8723au_write8(padapter, offset, value);
break;
case PWR_CMD_POLLING:
DBG_8723A("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", brate_cfg);
/* Set RRSR rate table. */
- rtw_write8(padapter, REG_RRSR, brate_cfg & 0xff);
- rtw_write8(padapter, REG_RRSR + 1, (brate_cfg >> 8) & 0xff);
- rtw_write8(padapter, REG_RRSR + 2,
- rtl8723au_read8(padapter, REG_RRSR + 2) & 0xf0);
+ rtl8723au_write8(padapter, REG_RRSR, brate_cfg & 0xff);
+ rtl8723au_write8(padapter, REG_RRSR + 1, (brate_cfg >> 8) & 0xff);
+ rtl8723au_write8(padapter, REG_RRSR + 2,
+ rtl8723au_read8(padapter, REG_RRSR + 2) & 0xf0);
rate_index = 0;
/* Set RTS initial rate */
rate_index++;
}
/* Ziv - Check */
- rtw_write8(padapter, REG_INIRTS_RATE_SEL, rate_index);
+ rtl8723au_write8(padapter, REG_INIRTS_RATE_SEL, rate_index);
return;
}
void c2h_evt_clear23a(struct rtw_adapter *adapter)
{
- rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
+ rtl8723au_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
}
int c2h_evt_read23a(struct rtw_adapter *adapter, u8 *buf)
padapter->MgntInfo.MinSpaceCfg)); */
MinSpacingToSet |=
rtl8723au_read8(padapter, REG_AMPDU_MIN_SPACE) & 0xf8;
- rtw_write8(padapter, REG_AMPDU_MIN_SPACE,
- MinSpacingToSet);
+ rtl8723au_write8(padapter, REG_AMPDU_MIN_SPACE,
+ MinSpacingToSet);
}
}
pRegToSet[index] = (pRegToSet[index] & 0xf0) |
FactorToSet;
- rtw_write8(padapter, REG_AGGLEN_LMT + index,
- pRegToSet[index]);
+ rtl8723au_write8(padapter, REG_AGGLEN_LMT + index,
+ pRegToSet[index]);
}
/* RT_TRACE(COMP_MLME, DBG_LOUD,
}
DBG_8723A("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
- rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
+ rtl8723au_write8(padapter, REG_ACMHWCTRL, hwctrl);
}
void rtl8723a_set_media_status(struct rtw_adapter *padapter, u8 status)
val8 = rtl8723au_read8(padapter, MSR) & 0x0c;
val8 |= status;
- rtw_write8(padapter, MSR, val8);
+ rtl8723au_write8(padapter, MSR, val8);
}
void rtl8723a_set_media_status1(struct rtw_adapter *padapter, u8 status)
val8 = rtl8723au_read8(padapter, MSR) & 0x03;
val8 |= status << 2;
- rtw_write8(padapter, MSR, val8);
+ rtl8723au_write8(padapter, MSR, val8);
}
void rtl8723a_set_bcn_func(struct rtw_adapter *padapter, u8 val)
val32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN;
else
val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
- rtw_write32(padapter, REG_RCR, val32);
+ rtl8723au_write32(padapter, REG_RCR, val32);
}
void rtl8723a_mlme_sitesurvey(struct rtw_adapter *padapter, u8 flag)
to receive data frame */
v32 = rtl8723au_read32(padapter, REG_RCR);
v32 &= ~(RCR_CBSSID_BCN);
- rtw_write32(padapter, REG_RCR, v32);
+ rtl8723au_write32(padapter, REG_RCR, v32);
/* reject all data frame */
- rtw_write16(padapter, REG_RXFLTMAP2, 0);
+ rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
/* disable update TSF */
SetBcnCtrlReg23a(padapter, DIS_TSF_UDT, 0);
((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) ||
((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
/* enable to rx data frame */
- rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
+ rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
/* enable update TSF */
SetBcnCtrlReg23a(padapter, 0, DIS_TSF_UDT);
v32 = rtl8723au_read32(padapter, REG_RCR);
v32 |= RCR_CBSSID_BCN;
- rtw_write32(padapter, REG_RCR, v32);
+ rtl8723au_write32(padapter, REG_RCR, v32);
}
#ifdef CONFIG_8723AU_BT_COEXIST
void rtl8723a_on_rcr_am(struct rtw_adapter *padapter)
{
- rtw_write32(padapter, REG_RCR,
+ rtl8723au_write32(padapter, REG_RCR,
rtl8723au_read32(padapter, REG_RCR) | RCR_AM);
DBG_8723A("%s, %d, RCR = %x \n", __FUNCTION__, __LINE__,
rtl8723au_read32(padapter, REG_RCR));
void rtl8723a_off_rcr_am(struct rtw_adapter *padapter)
{
- rtw_write32(padapter, REG_RCR,
+ rtl8723au_write32(padapter, REG_RCR,
rtl8723au_read32(padapter, REG_RCR) & (~RCR_AM));
DBG_8723A("%s, %d, RCR = %x \n", __FUNCTION__, __LINE__,
rtl8723au_read32(padapter, REG_RCR));
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
- rtw_write8(padapter, REG_SLOT, slottime);
+ rtl8723au_write8(padapter, REG_SLOT, slottime);
if (pmlmeinfo->WMM_enable == 0) {
if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
/* <Roger_EXP> Temporary removed, 2008.06.20. */
- rtw_write8(padapter, REG_EDCA_VO_PARAM, u1bAIFS);
- rtw_write8(padapter, REG_EDCA_VI_PARAM, u1bAIFS);
- rtw_write8(padapter, REG_EDCA_BE_PARAM, u1bAIFS);
- rtw_write8(padapter, REG_EDCA_BK_PARAM, u1bAIFS);
+ rtl8723au_write8(padapter, REG_EDCA_VO_PARAM, u1bAIFS);
+ rtl8723au_write8(padapter, REG_EDCA_VI_PARAM, u1bAIFS);
+ rtl8723au_write8(padapter, REG_EDCA_BE_PARAM, u1bAIFS);
+ rtl8723au_write8(padapter, REG_EDCA_BK_PARAM, u1bAIFS);
}
}
/* regTmp = 0; */
if (bShortPreamble)
regTmp |= 0x80;
- rtw_write8(padapter, REG_RRSR + 2, regTmp);
+ rtl8723au_write8(padapter, REG_RRSR + 2, regTmp);
}
void rtl8723a_set_sec_cfg(struct rtw_adapter *padapter, u8 sec)
{
- rtw_write8(padapter, REG_SECCFG, sec);
+ rtl8723au_write8(padapter, REG_SECCFG, sec);
}
void rtl8723a_cam_empty_entry(struct rtw_adapter *padapter, u8 ucIndex)
ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
/* write content 0 is equall to mark invalid */
/* delay_ms(40); */
- rtw_write32(padapter, WCAMI, ulContent);
+ rtl8723au_write32(padapter, WCAMI, ulContent);
/* RT_TRACE(COMP_SEC, DBG_LOUD,
("rtl8723a_cam_empty_entry(): WRITE A4: %lx \n",
ulContent));*/
/* delay_ms(40); */
- rtw_write32(padapter, RWCAM, ulCommand);
+ rtl8723au_write32(padapter, RWCAM, ulCommand);
/* RT_TRACE(COMP_SEC, DBG_LOUD,
("rtl8723a_cam_empty_entry(): WRITE A0: %lx \n",
ulCommand));*/
void rtl8723a_cam_invalid_all(struct rtw_adapter *padapter)
{
- rtw_write32(padapter, RWCAM, BIT(31) | BIT(30));
+ rtl8723au_write32(padapter, RWCAM, BIT(31) | BIT(30));
}
void rtl8723a_cam_write(struct rtw_adapter *padapter,
break;
}
- rtw_write32(padapter, WCAMI, val);
+ rtl8723au_write32(padapter, WCAMI, val);
cmd = CAM_POLLINIG | CAM_WRITE | (addr + j);
- rtw_write32(padapter, RWCAM, cmd);
+ rtl8723au_write32(padapter, RWCAM, cmd);
/* DBG_8723A("%s => cam write: %x, %x\n", __func__, cmd, val);*/
}
u8 trycnt = 100;
/* pause tx */
- rtw_write8(padapter, REG_TXPAUSE, 0xff);
+ rtl8723au_write8(padapter, REG_TXPAUSE, 0xff);
/* keep sn */
padapter->xmitpriv.nqos_ssn = rtl8723au_read16(padapter, REG_NQOS_SEQ);
/* RX DMA stop */
v32 = rtl8723au_read32(padapter, REG_RXPKT_NUM);
v32 |= RW_RELEASE_EN;
- rtw_write32(padapter, REG_RXPKT_NUM, v32);
+ rtl8723au_write32(padapter, REG_RXPKT_NUM, v32);
do {
v32 = rtl8723au_read32(padapter,
REG_RXPKT_NUM) & RXDMA_IDLE;
}
/* RQPN Load 0 */
- rtw_write16(padapter, REG_RQPN_NPQ, 0);
- rtw_write32(padapter, REG_RQPN, 0x80000000);
+ rtl8723au_write16(padapter, REG_RQPN_NPQ, 0);
+ rtl8723au_write32(padapter, REG_RQPN, 0x80000000);
mdelay(10);
}
}
{
/* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2,
write 1 to clear, Clear by sw */
- rtw_write8(padapter, REG_TDECTRL + 2,
- rtl8723au_read8(padapter, REG_TDECTRL + 2) | BIT(0));
+ rtl8723au_write8(padapter, REG_TDECTRL + 2,
+ rtl8723au_read8(padapter, REG_TDECTRL + 2) | BIT(0));
}
bool rtl8723a_get_bcn_valid(struct rtw_adapter *padapter)
void rtl8723a_set_beacon_interval(struct rtw_adapter *padapter, u16 interval)
{
- rtw_write16(padapter, REG_BCN_INTERVAL, interval);
+ rtl8723au_write16(padapter, REG_BCN_INTERVAL, interval);
}
void rtl8723a_set_resp_sifs(struct rtw_adapter *padapter,
/* SIFS_Timer = 0x0a0a0808; */
/* RESP_SIFS for CCK */
/* SIFS_T2T_CCK (0x08) */
- rtw_write8(padapter, REG_R2T_SIFS, r2t1);
+ rtl8723au_write8(padapter, REG_R2T_SIFS, r2t1);
/* SIFS_R2T_CCK(0x08) */
- rtw_write8(padapter, REG_R2T_SIFS + 1, r2t2);
+ rtl8723au_write8(padapter, REG_R2T_SIFS + 1, r2t2);
/* RESP_SIFS for OFDM */
/* SIFS_T2T_OFDM (0x0a) */
- rtw_write8(padapter, REG_T2T_SIFS, t2t1);
+ rtl8723au_write8(padapter, REG_T2T_SIFS, t2t1);
/* SIFS_R2T_OFDM(0x0a) */
- rtw_write8(padapter, REG_T2T_SIFS + 1, t2t2);
+ rtl8723au_write8(padapter, REG_T2T_SIFS + 1, t2t2);
}
void rtl8723a_set_ac_param_vo(struct rtw_adapter *padapter, u32 vo)
{
- rtw_write32(padapter, REG_EDCA_VO_PARAM, vo);
+ rtl8723au_write32(padapter, REG_EDCA_VO_PARAM, vo);
}
void rtl8723a_set_ac_param_vi(struct rtw_adapter *padapter, u32 vi)
{
- rtw_write32(padapter, REG_EDCA_VI_PARAM, vi);
+ rtl8723au_write32(padapter, REG_EDCA_VI_PARAM, vi);
}
void rtl8723a_set_ac_param_be(struct rtw_adapter *padapter, u32 be)
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
pHalData->AcParam_BE = be;
- rtw_write32(padapter, REG_EDCA_BE_PARAM, be);
+ rtl8723au_write32(padapter, REG_EDCA_BE_PARAM, be);
}
void rtl8723a_set_ac_param_bk(struct rtw_adapter *padapter, u32 bk)
{
- rtw_write32(padapter, REG_EDCA_BK_PARAM, bk);
+ rtl8723au_write32(padapter, REG_EDCA_BK_PARAM, bk);
}
void rtl8723a_set_rxdma_agg_pg_th(struct rtw_adapter *padapter, u8 val)
{
- rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, val);
+ rtl8723au_write8(padapter, REG_RXDMA_AGG_PG_TH, val);
}
void rtl8723a_set_nav_upper(struct rtw_adapter *padapter, u32 usNavUpper)
/* is getting the upper integer. */
usNavUpper = (usNavUpper + HAL_8723A_NAV_UPPER_UNIT - 1) /
HAL_8723A_NAV_UPPER_UNIT;
- rtw_write8(padapter, REG_NAV_UPPER, (u8) usNavUpper);
+ rtl8723au_write8(padapter, REG_NAV_UPPER, (u8) usNavUpper);
}
void rtl8723a_set_initial_gain(struct rtw_adapter *padapter, u32 rx_gain)
void rtl8723a_set_rpwm(struct rtw_adapter *padapter, u8 val)
{
- rtw_write8(padapter, REG_USB_HRPWM, val);
+ rtl8723au_write8(padapter, REG_USB_HRPWM, val);
}
u8 rtl8723a_get_rf_type(struct rtw_adapter *padapter)
u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
struct dm_priv *pdmpriv = &pHalData->dmpriv;
for (index = 0; index < 6; index++)
- rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
+ rtl8723au_write8(Adapter, Power_Index_REG[index],
+ pdmpriv->PowerIndex_backup[index]);
}
void odm_DynamicTxPower23aWritePowerIndex(struct dm_odm_t *pDM_Odm,
edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
else
edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
- rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
+ rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
+ edca_param);
pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
}
/* Turn Off EDCA turbo here. */
/* Restore original EDCA according to the declaration of AP. */
if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
- rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
+ rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
+ pHalData->AcParam_BE);
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
}
}
return rtl8723au_read32(Adapter, RegAddr);
}
-void ODM_Write1Byte(
- struct dm_odm_t *pDM_Odm,
- u32 RegAddr,
- u8 Data
- )
+void ODM_Write1Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u8 Data)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
- rtw_write8(Adapter, RegAddr, Data);
+ rtl8723au_write8(Adapter, RegAddr, Data);
}
-void ODM_Write2Byte(
- struct dm_odm_t *pDM_Odm,
- u32 RegAddr,
- u16 Data
- )
+void ODM_Write2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u16 Data)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
- rtw_write16(Adapter, RegAddr, Data);
+ rtl8723au_write16(Adapter, RegAddr, Data);
}
-void ODM_Write4Byte(
- struct dm_odm_t *pDM_Odm,
- u32 RegAddr,
- u32 Data
- )
+void ODM_Write4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 Data)
{
struct rtw_adapter *Adapter = pDM_Odm->Adapter;
- rtw_write32(Adapter, RegAddr, Data);
-
+ rtl8723au_write32(Adapter, RegAddr, Data);
}
void ODM_SetMACReg(
newVal = oldVal & ~EN_BCN_FUNCTION;
if (oldVal != newVal)
- rtw_write8(padapter, 0x550, newVal);
+ rtl8723au_write8(padapter, 0x550, newVal);
}
static u8 btdm_Is1AntPsTdmaStateChange(struct rtw_adapter *padapter)
case 29: /* WiFi DHCP/Site Survey & BT ACL busy */
if (btdm_Is1AntPsTdmaStateChange(padapter)) {
BTDM_SetFw3a(padapter, 0xeb, 0x1a, 0x1a, 0x01, 0x18);
- rtw_write32(padapter, 0x6c0, 0x5afa5afa);
- rtw_write32(padapter, 0x6c4, 0x5afa5afa);
+ rtl8723au_write32(padapter, 0x6c0, 0x5afa5afa);
+ rtl8723au_write32(padapter, 0x6c4, 0x5afa5afa);
}
break;
case 30: /* WiFi idle & BT Inquiry */
/* Antenna control by PTA, 0x870 = 0x310 */
BTDM_SetFw3a(padapter, 0x0, 0x0, 0x0, 0x8, 0x0);
}
- rtw_write16(padapter, 0x860, 0x210); /* Switch Antenna to BT */
+ /* Switch Antenna to BT */
+ rtl8723au_write16(padapter, 0x860, 0x210);
RTPRINT(FBT, BT_TRACE, ("[BTCoex], 0x860 = 0x210, Switch Antenna to BT\n"));
break;
case 9:
/* Antenna control by PTA, 0x870 = 0x310 */
BTDM_SetFw3a(padapter, 0x0, 0x0, 0x0, 0x8, 0x0);
}
- rtw_write16(padapter, 0x860, 0x110); /* Switch Antenna to WiFi */
+ /* Switch Antenna to WiFi */
+ rtl8723au_write16(padapter, 0x860, 0x110);
RTPRINT(FBT, BT_TRACE, ("[BTCoex], 0x860 = 0x110, Switch Antenna to WiFi\n"));
break;
}
static void btdm_1AntPtaParaReload(struct rtw_adapter *padapter)
{
/* PTA parameter */
- rtw_write8(padapter, 0x6cc, 0x0); /* 1-Ant coex */
- rtw_write32(padapter, 0x6c8, 0xffff); /* wifi break table */
- rtw_write32(padapter, 0x6c4, 0x55555555); /* coex table */
+ rtl8723au_write8(padapter, 0x6cc, 0x0); /* 1-Ant coex */
+ rtl8723au_write32(padapter, 0x6c8, 0xffff); /* wifi break table */
+ rtl8723au_write32(padapter, 0x6c4, 0x55555555); /* coex table */
/* Antenna switch control parameter */
- rtw_write32(padapter, 0x858, 0xaaaaaaaa);
+ rtl8723au_write32(padapter, 0x858, 0xaaaaaaaa);
if (IS_8723A_A_CUT(GET_HAL_DATA(padapter)->VersionID)) {
- rtw_write32(padapter, 0x870, 0x0); /* SPDT(connected with TRSW) control by hardware PTA */
- rtw_write8(padapter, 0x40, 0x24);
+ /* SPDT(connected with TRSW) control by hardware PTA */
+ rtl8723au_write32(padapter, 0x870, 0x0);
+ rtl8723au_write8(padapter, 0x40, 0x24);
} else {
- rtw_write8(padapter, 0x40, 0x20);
- rtw_write16(padapter, 0x860, 0x210); /* set antenna at bt side if ANTSW is software control */
- rtw_write32(padapter, 0x870, 0x300); /* SPDT(connected with TRSW) control by hardware PTA */
- rtw_write32(padapter, 0x874, 0x22804000); /* ANTSW keep by GNT_BT */
+ rtl8723au_write8(padapter, 0x40, 0x20);
+ /* set antenna at bt side if ANTSW is software control */
+ rtl8723au_write16(padapter, 0x860, 0x210);
+ /* SPDT(connected with TRSW) control by hardware PTA */
+ rtl8723au_write32(padapter, 0x870, 0x300);
+ /* ANTSW keep by GNT_BT */
+ rtl8723au_write32(padapter, 0x874, 0x22804000);
}
/* coexistence parameters */
- rtw_write8(padapter, 0x778, 0x1); /* enable RTK mode PTA */
+ rtl8723au_write8(padapter, 0x778, 0x1); /* enable RTK mode PTA */
/* BT don't ignore WLAN_Act */
btdm_SetFwIgnoreWlanAct(padapter, false);
case BT_INFO_STATE_CONNECT_IDLE:
/* WiFi is Busy */
btdm_1AntSetPSTDMA(padapter, false, 0, true, 5);
- rtw_write32(padapter, 0x6c0, 0x5a5a5a5a);
- rtw_write32(padapter, 0x6c4, 0x5a5a5a5a);
+ rtl8723au_write32(padapter, 0x6c0, 0x5a5a5a5a);
+ rtl8723au_write32(padapter, 0x6c4, 0x5a5a5a5a);
break;
case BT_INFO_STATE_ACL_INQ_OR_PAG:
RTPRINT(FBT, BT_TRACE,
#else /* !BTCOEX_CMCC_TEST */
btdm_1AntSetPSTDMA(padapter, false, 0,
false, 8);
- rtw_write32(padapter, 0x6c0, 0x5a5a5a5a);
- rtw_write32(padapter, 0x6c4, 0x5a5a5a5a);
+ rtl8723au_write32(padapter, 0x6c0, 0x5a5a5a5a);
+ rtl8723au_write32(padapter, 0x6c4, 0x5a5a5a5a);
#endif /* !BTCOEX_CMCC_TEST */
}
break;
if (shortGIrate)
init_rate |= BIT(6);
- rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate);
+ rtl8723au_write8(padapter, REG_INIDATA_RATE_SEL + mac_id,
+ init_rate);
}
psta->init_rate = init_rate;
pBtdm8723 = &pBtCoex->btdm1Ant;
/* Enable counter statistics */
- rtw_write8(padapter, 0x76e, 0x4);
+ rtl8723au_write8(padapter, 0x76e, 0x4);
btdm_1AntPtaParaReload(padapter);
pBtdm8723->wifiRssiThresh = 48;
BtState == BT_INFO_STATE_ACL_SCO_BUSY) {
btdm_1AntSetPSTDMA(padapter, false, 0,
false, 8);
- rtw_write32(padapter, 0x6c0, 0x5a5a5a5a);
- rtw_write32(padapter, 0x6c4, 0x5a5a5a5a);
+ rtl8723au_write32(padapter, 0x6c0, 0x5a5a5a5a);
+ rtl8723au_write32(padapter, 0x6c4, 0x5a5a5a5a);
} else if (BtState == BT_INFO_STATE_ACL_ONLY_BUSY ||
BtState == BT_INFO_STATE_ACL_INQ_OR_PAG) {
if (pBtCoex->c2hBtProfile == BT_INFO_HID)
u32 val0x6c8, u8 val0x6cc)
{
RTPRINT(FBT, BT_TRACE, ("set coex table, set 0x6c0 = 0x%x\n", val0x6c0));
- rtw_write32(padapter, 0x6c0, val0x6c0);
+ rtl8723au_write32(padapter, 0x6c0, val0x6c0);
RTPRINT(FBT, BT_TRACE, ("set coex table, set 0x6c8 = 0x%x\n", val0x6c8));
- rtw_write32(padapter, 0x6c8, val0x6c8);
+ rtl8723au_write32(padapter, 0x6c8, val0x6c8);
RTPRINT(FBT, BT_TRACE, ("set coex table, set 0x6cc = 0x%x\n", val0x6cc));
- rtw_write8(padapter, 0x6cc, val0x6cc);
+ rtl8723au_write8(padapter, 0x6cc, val0x6cc);
}
static void
RTPRINT(FBT, BT_TRACE, ("[BTCoex], 2Ant Parameter Init!!\n"));
/* Enable counter statistics */
- rtw_write8(padapter, 0x76e, 0x4);
- rtw_write8(padapter, 0x778, 0x3);
- rtw_write8(padapter, 0x40, 0x20);
+ rtl8723au_write8(padapter, 0x76e, 0x4);
+ rtl8723au_write8(padapter, 0x778, 0x3);
+ rtl8723au_write8(padapter, 0x40, 0x20);
/* force to reset coex mechanism */
pBtdm8723->preVal0x6c0 = 0x0;
RTPRINT(FBT, BT_TRACE, ("Low Priority Tx/Rx = %d / %d\n", regLPTx, regLPRx));
/* reset counter */
- rtw_write8(padapter, 0x76e, 0xc);
+ rtl8723au_write8(padapter, 0x76e, 0xc);
}
/* This function check if 8723 bt is disabled */
tmpU1 |= BIT(2);
}
- rtw_write8(padapter, 0x4fd, tmpU1);
+ rtl8723au_write8(padapter, 0x4fd, tmpU1);
}
void BTDM_SetFwDecBtPwr(struct rtw_adapter *padapter, u8 bDecBtPwr)
if (cur_EDCA_reg != EDCA_BT_BE)
bBtChangeEDCA = true;
if (bBtChangeEDCA || !pHalData->bt_coexist.bEDCAInitialized) {
- rtw_write32(padapter, REG_EDCA_BE_PARAM, EDCA_BT_BE);
+ rtl8723au_write32(padapter, REG_EDCA_BE_PARAM,
+ EDCA_BT_BE);
pHalData->bt_coexist.lastBtEdca = EDCA_BT_BE;
}
bRet = true;
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
if (type == BT_AGCTABLE_OFF) {
RTPRINT(FBT, BT_TRACE, ("[BT]AGCTable Off!\n"));
- rtw_write32(padapter, 0xc78, 0x641c0001);
- rtw_write32(padapter, 0xc78, 0x631d0001);
- rtw_write32(padapter, 0xc78, 0x621e0001);
- rtw_write32(padapter, 0xc78, 0x611f0001);
- rtw_write32(padapter, 0xc78, 0x60200001);
+ rtl8723au_write32(padapter, 0xc78, 0x641c0001);
+ rtl8723au_write32(padapter, 0xc78, 0x631d0001);
+ rtl8723au_write32(padapter, 0xc78, 0x621e0001);
+ rtl8723au_write32(padapter, 0xc78, 0x611f0001);
+ rtl8723au_write32(padapter, 0xc78, 0x60200001);
PHY_SetRFReg(padapter, PathA, RF_RX_AGC_HP, bRFRegOffsetMask, 0x32000);
PHY_SetRFReg(padapter, PathA, RF_RX_AGC_HP, bRFRegOffsetMask, 0x71000);
pHalData->bt_coexist.b8723aAgcTableOn = false;
} else if (type == BT_AGCTABLE_ON) {
RTPRINT(FBT, BT_TRACE, ("[BT]AGCTable On!\n"));
- rtw_write32(padapter, 0xc78, 0x4e1c0001);
- rtw_write32(padapter, 0xc78, 0x4d1d0001);
- rtw_write32(padapter, 0xc78, 0x4c1e0001);
- rtw_write32(padapter, 0xc78, 0x4b1f0001);
- rtw_write32(padapter, 0xc78, 0x4a200001);
+ rtl8723au_write32(padapter, 0xc78, 0x4e1c0001);
+ rtl8723au_write32(padapter, 0xc78, 0x4d1d0001);
+ rtl8723au_write32(padapter, 0xc78, 0x4c1e0001);
+ rtl8723au_write32(padapter, 0xc78, 0x4b1f0001);
+ rtl8723au_write32(padapter, 0xc78, 0x4a200001);
PHY_SetRFReg(padapter, PathA, RF_RX_AGC_HP, bRFRegOffsetMask, 0xdc000);
PHY_SetRFReg(padapter, PathA, RF_RX_AGC_HP, bRFRegOffsetMask, 0x90000);
if (type == BT_BB_BACKOFF_OFF) {
RTPRINT(FBT, BT_TRACE, ("[BT]BBBackOffLevel Off!\n"));
- rtw_write32(padapter, 0xc04, 0x3a05611);
+ rtl8723au_write32(padapter, 0xc04, 0x3a05611);
} else if (type == BT_BB_BACKOFF_ON) {
RTPRINT(FBT, BT_TRACE, ("[BT]BBBackOffLevel On!\n"));
- rtw_write32(padapter, 0xc04, 0x3a07611);
+ rtl8723au_write32(padapter, 0xc04, 0x3a07611);
pHalData->bt_coexist.bSWCoexistAllOff = false;
}
}
if (h2c_cmd & BIT(7)) {
msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
h2c_cmd_ex = le16_to_cpu(h2c_cmd_ex);
- rtw_write16(padapter, msgbox_ex_addr, h2c_cmd_ex);
+ rtl8723au_write16(padapter, msgbox_ex_addr, h2c_cmd_ex);
}
msgbox_addr = REG_HMEBOX_0 + (h2c_box_num * MESSAGE_BOX_SIZE);
h2c_cmd = le32_to_cpu(h2c_cmd);
- rtw_write32(padapter, msgbox_addr, h2c_cmd);
+ rtl8723au_write32(padapter, msgbox_addr, h2c_cmd);
bcmd_down = true;
if (shortGIrate == true)
init_rate |= BIT(6);
- rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate);
+ rtl8723au_write8(pAdapter, REG_INIDATA_RATE_SEL + macid,
+ init_rate);
}
}
/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
/* Suggested by filen. Added by tynli. */
- rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
+ rtl8723au_write16(padapter, REG_BCN_PSR_RPT,
+ 0xC000|pmlmeinfo->aid);
/* Do not set TSF again here or vWiFi beacon DMA INT will not work. */
/* correct_TSF23a(padapter, pmlmeext); */
/* Hw sequende enable by dedault. 2010.06.23. by tynli. */
- /* rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); */
- /* rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); */
+ /* rtl8723au_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); */
+ /* rtl8723au_write8(padapter, REG_HWSEQ_CTRL, 0xFF); */
/* set REG_CR bit 8 */
v8 = rtl8723au_read8(padapter, REG_CR+1);
v8 |= BIT(0); /* ENSWBCN */
- rtw_write8(padapter, REG_CR+1, v8);
+ rtl8723au_write8(padapter, REG_CR+1, v8);
/* Disable Hw protection for a time which revserd for Hw sending beacon. */
/* Fix download reserved page packet fail that access collision with the protection time. */
/* To tell Hw the packet is not a real beacon frame. */
/* U1bTmp = rtl8723au_read8(padapter, REG_FWHW_TXQ_CTRL+2); */
- rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl & ~BIT(6));
+ rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+ pHalData->RegFwHwTxQCtrl & ~BIT(6));
pHalData->RegFwHwTxQCtrl &= ~BIT(6);
SetFwRsvdPagePkt(padapter, 0);
/* the beacon cannot be sent by HW. */
/* 2010.06.23. Added by tynli. */
if (bRecover) {
- rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl | BIT(6));
+ rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+ pHalData->RegFwHwTxQCtrl | BIT(6));
pHalData->RegFwHwTxQCtrl |= BIT(6);
}
/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
v8 = rtl8723au_read8(padapter, REG_CR+1);
v8 &= ~BIT(0); /* ~ENSWBCN */
- rtw_write8(padapter, REG_CR+1, v8);
+ rtl8723au_write8(padapter, REG_CR+1, v8);
}
JoinBssRptParm.OpMode = mstatus;
/* To tell Hw the packet is not a real beacon frame. */
pHalData->RegFwHwTxQCtrl &= ~BIT(6);
- rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
+ rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+ pHalData->RegFwHwTxQCtrl);
SetFwRsvdPagePkt_BTCoex(padapter);
/* To make sure that if there exists an adapter which would like to send beacon. */
/* 2010.06.23. Added by tynli. */
if (bRecover) {
pHalData->RegFwHwTxQCtrl |= BIT(6);
- rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
+ rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+ pHalData->RegFwHwTxQCtrl);
}
}
#endif
tmp1byte = rtl8723au_read8(padapter, GPIO_IO_SEL);
tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
- rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as output mode */
+ /* enable GPIO[2] as output mode */
+ rtl8723au_write8(padapter, GPIO_IO_SEL, tmp1byte);
tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
- rtw_write8(padapter, GPIO_IN, tmp1byte); /* reset the floating voltage level */
+ /* reset the floating voltage level */
+ rtl8723au_write8(padapter, GPIO_IN, tmp1byte);
tmp1byte = rtl8723au_read8(padapter, GPIO_IO_SEL);
tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
- rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as input mode */
+ /* enable GPIO[2] as input mode */
+ rtl8723au_write8(padapter, GPIO_IO_SEL, tmp1byte);
tmp1byte = rtl8723au_read8(padapter, GPIO_IN);
if (enable) {
/* 8051 enable */
tmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
- rtw_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
+ rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
/* MCU firmware download enable. */
tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
- rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
+ rtl8723au_write8(padapter, REG_MCUFWDL, tmp | 0x01);
/* 8051 reset */
tmp = rtl8723au_read8(padapter, REG_MCUFWDL + 2);
- rtw_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
+ rtl8723au_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
} else {
/* MCU firmware download disable. */
tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
- rtw_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
+ rtl8723au_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
/* Reserved for fw extension. */
- rtw_write8(padapter, REG_MCUFWDL + 1, 0x00);
+ rtl8723au_write8(padapter, REG_MCUFWDL + 1, 0x00);
}
}
}
for (i = 0; i < blockCount_p1; i++) {
- ret = rtw_writeN(padapter,
- (FW_8723A_START_ADDRESS + i * blockSize_p1),
- blockSize_p1, (bufferPtr + i * blockSize_p1));
+ ret = rtl8723au_writeN(padapter, (FW_8723A_START_ADDRESS +
+ i * blockSize_p1),
+ blockSize_p1,
+ (bufferPtr + i * blockSize_p1));
if (ret == _FAIL)
goto exit;
}
}
for (i = 0; i < blockCount_p2; i++) {
- ret = rtw_writeN(padapter,
- (FW_8723A_START_ADDRESS + offset +
- i * blockSize_p2), blockSize_p2,
- (bufferPtr + offset +
- i * blockSize_p2));
+ ret = rtl8723au_writeN(padapter,
+ (FW_8723A_START_ADDRESS +
+ offset + i * blockSize_p2),
+ blockSize_p2,
+ (bufferPtr + offset +
+ i * blockSize_p2));
if (ret == _FAIL)
goto exit;
(buffSize - offset), blockSize_p3, blockCount_p3));
for (i = 0; i < blockCount_p3; i++) {
- ret = rtw_write8(padapter,
- (FW_8723A_START_ADDRESS + offset + i),
- *(bufferPtr + offset + i));
+ ret = rtl8723au_write8(padapter,
+ (FW_8723A_START_ADDRESS + offset + i),
+ *(bufferPtr + offset + i));
if (ret == _FAIL)
goto exit;
u8 u8Page = (u8) (page & 0x07);
value8 = (rtl8723au_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page;
- rtw_write8(padapter, REG_MCUFWDL + 2, value8);
+ rtl8723au_write8(padapter, REG_MCUFWDL + 2, value8);
return _BlockWrite(padapter, buffer, size);
}
value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
value32 |= MCUFWDL_RDY;
value32 &= ~WINTINI_RDY;
- rtw_write32(padapter, REG_MCUFWDL, value32);
+ rtl8723au_write32(padapter, REG_MCUFWDL, value32);
/* polling for FW ready */
counter = 0;
pHalData->FirmwareSubVersion < 0x01)))) {
/* after 88C Fw v33.1 */
/* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
- rtw_write8(padapter, REG_HMETFR + 3, 0x20);
+ rtl8723au_write8(padapter, REG_HMETFR + 3, 0x20);
u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
while (u1bTmp & BIT(2)) {
if ((Delay == 0)) {
/* force firmware reset */
u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
- rtw_write8(padapter, REG_SYS_FUNC_EN + 1,
- u1bTmp & ~BIT(2));
+ rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1,
+ u1bTmp & ~BIT(2));
}
}
}
if (rtl8723au_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
/* 8051 RAM code */
rtl8723a_FirmwareSelfReset(padapter);
- rtw_write8(padapter, REG_MCUFWDL, 0x00);
+ rtl8723au_write8(padapter, REG_MCUFWDL, 0x00);
}
_FWDownloadEnable(padapter, true);
fwdl_start_time = jiffies;
while (1) {
/* reset the FWDL chksum */
- rtw_write8(padapter, REG_MCUFWDL,
- rtl8723au_read8(padapter, REG_MCUFWDL) | FWDL_ChkSum_rpt);
+ rtl8723au_write8(padapter, REG_MCUFWDL,
+ rtl8723au_read8(padapter, REG_MCUFWDL) |
+ FWDL_ChkSum_rpt);
rtStatus = _WriteFW(padapter, buf, fw_size);
bRet = false;
break;
}
- rtw_write32(padapter, EFUSE_TEST, value32);
+ rtl8723au_write32(padapter, EFUSE_TEST, value32);
return bRet;
}
*pRegBcnCtrlVal |= SetBits;
*pRegBcnCtrlVal &= ~ClearBits;
- rtw_write8(padapter, addr, *pRegBcnCtrlVal);
+ rtl8723au_write8(padapter, addr, *pRegBcnCtrlVal);
}
void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
- rtw_write16(padapter, REG_BCN_CTRL, 0x1010);
+ rtl8723au_write16(padapter, REG_BCN_CTRL, 0x1010);
pHalData->RegBcnCtrlVal = 0x1010;
/* TODO: Remove these magic number */
- rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404); /* ms */
+ rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0x6404); /* ms */
/* Firmware will control REG_DRVERLYINT when power saving is enable, */
/* so don't set this register on STA mode. */
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
- rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
+ rtl8723au_write8(padapter, REG_DRVERLYINT,
+ DRIVER_EARLY_INT_TIME);
/* 2ms */
- rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
+ rtl8723au_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
/* Suggested by designer timchen. Change beacon AIFS to the
largest number beacause test chip does not contension before
sending beacon. by tynli. 2009.11.03 */
- rtw_write16(padapter, REG_BCNTCFG, 0x660F);
+ rtl8723au_write16(padapter, REG_BCNTCFG, 0x660F);
}
static void ResumeTxBeacon(struct rtw_adapter *padapter)
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n"));
pHalData->RegFwHwTxQCtrl |= BIT(6);
- rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl);
- rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff);
+ rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+ pHalData->RegFwHwTxQCtrl);
+ rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff);
pHalData->RegReg542 |= BIT(0);
- rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
+ rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
}
static void StopTxBeacon(struct rtw_adapter *padapter)
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n"));
pHalData->RegFwHwTxQCtrl &= ~BIT(6);
- rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl);
- rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64);
+ rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+ pHalData->RegFwHwTxQCtrl);
+ rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64);
pHalData->RegReg542 &= ~BIT(0);
- rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
+ rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
CheckFwRsvdPageContent23a(padapter); /* 2010.06.23. Added by tynli. */
}
{
SetBcnCtrlReg23a(padapter, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB,
0);
- rtw_write8(padapter, REG_RD_CTRL + 1, 0x6F);
+ rtl8723au_write8(padapter, REG_RD_CTRL + 1, 0x6F);
}
void rtl8723a_SetBeaconRelatedRegisters(struct rtw_adapter *padapter)
/* */
/* ATIM window */
/* */
- rtw_write16(padapter, REG_ATIMWND, 2);
+ rtl8723au_write16(padapter, REG_ATIMWND, 2);
/* */
/* Beacon interval (in unit of TU). */
/* */
- rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
+ rtl8723au_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
rtl8723a_InitBeaconParameters(padapter);
- rtw_write8(padapter, REG_SLOT, 0x09);
+ rtl8723au_write8(padapter, REG_SLOT, 0x09);
/* */
/* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
/* */
value32 = rtl8723au_read32(padapter, REG_TCR);
value32 &= ~TSFRST;
- rtw_write32(padapter, REG_TCR, value32);
+ rtl8723au_write32(padapter, REG_TCR, value32);
value32 |= TSFRST;
- rtw_write32(padapter, REG_TCR, value32);
+ rtl8723au_write32(padapter, REG_TCR, value32);
/* NOTE: Fix test chip's bug (about contention windows's randomness) */
if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE |
WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == true) {
- rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
- rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
+ rtl8723au_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
+ rtl8723au_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
}
_BeaconFunctionEnable(padapter, true, true);
{
if (enable) {
DBG_8723A("Enable notch filter\n");
- rtw_write8(adapter, rOFDM0_RxDSP + 1,
- rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) | BIT(1));
+ rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
+ rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) |
+ BIT(1));
} else {
DBG_8723A("Disable notch filter\n");
- rtw_write8(adapter, rOFDM0_RxDSP + 1,
- rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) & ~BIT(1));
+ rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
+ rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) &
+ ~BIT(1));
}
}
val = rtl8723au_read8(padapter, REG_LEDCFG2);
/* Let 8051 take control antenna settting */
val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
- rtw_write8(padapter, REG_LEDCFG2, val);
+ rtl8723au_write8(padapter, REG_LEDCFG2, val);
}
void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter)
/* Let 8051 take control antenna settting */
if (!(val & BIT(7))) {
val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
- rtw_write8(padapter, REG_LEDCFG2, val);
+ rtl8723au_write8(padapter, REG_LEDCFG2, val);
}
}
val = rtl8723au_read8(padapter, REG_LEDCFG2);
/* Let 8051 take control antenna settting */
val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */
- rtw_write8(padapter, REG_LEDCFG2, val);
+ rtl8723au_write8(padapter, REG_LEDCFG2, val);
}
void rtl8723a_init_default_value(struct rtw_adapter *padapter)
_LLT_OP(_LLT_WRITE_ACCESS);
u16 LLTReg = REG_LLT_INIT;
- rtw_write32(padapter, LLTReg, value);
+ rtl8723au_write32(padapter, LLTReg, value);
/* polling */
do {
u32 u4bTmp;
/* 1. Disable GPIO[7:0] */
- rtw_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
+ rtl8723au_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
u4bTmp = value32 & 0x000000FF;
value32 |= ((u4bTmp << 8) | 0x00FF0000);
- rtw_write32(padapter, REG_GPIO_PIN_CTRL, value32);
+ rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL, value32);
/* */
/* <Roger_Notes> For RTL8723u multi-function configuration which
/* 2. Disable GPIO[8] and GPIO[12] */
/* Configure all pins as input mode. */
- rtw_write16(padapter, REG_GPIO_IO_SEL_2, 0x0000);
+ rtl8723au_write16(padapter, REG_GPIO_IO_SEL_2, 0x0000);
value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL_2) & 0xFFFF001F;
u4bTmp = value32 & 0x0000001F;
/* Set pin 8, 10, 11 and pin 12 to output mode. */
value32 |= ((u4bTmp << 8) | 0x001D0000);
- rtw_write32(padapter, REG_GPIO_PIN_CTRL_2, value32);
+ rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL_2, value32);
/* 3. Disable LED0 & 1 */
- rtw_write16(padapter, REG_LEDCFG0, 0x8080);
+ rtl8723au_write16(padapter, REG_LEDCFG0, 0x8080);
} /* end of _DisableGPIO() */
static void _DisableRFAFEAndResetBB8192C(struct rtw_adapter *padapter)
***************************************/
u8 eRFPath = 0, value8 = 0;
- rtw_write8(padapter, REG_TXPAUSE, 0xFF);
+ rtl8723au_write8(padapter, REG_TXPAUSE, 0xFF);
PHY_SetRFReg(padapter, (enum RF_RADIO_PATH) eRFPath, 0x0, bMaskByte0, 0x0);
value8 |= APSDOFF;
- rtw_write8(padapter, REG_APSD_CTRL, value8); /* 0x40 */
+ rtl8723au_write8(padapter, REG_APSD_CTRL, value8); /* 0x40 */
/* Set BB reset at first */
value8 = 0;
value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
- rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x16 */
+ rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x16 */
/* Set global reset. */
value8 &= ~FEN_BB_GLB_RSTn;
- rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x14 */
+ rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x14 */
/* 2010/08/12 MH We need to set BB/GLBAL reset to save power
for SS mode. */
(8051 enable)
******************************/
u16 valu16 = 0;
- rtw_write8(padapter, REG_MCUFWDL, 0);
+ rtl8723au_write8(padapter, REG_MCUFWDL, 0);
valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
/* reset MCU , 8051 */
- rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));
+ rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
+ valu16 & (~FEN_CPUEN));
valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
- rtw_write16(padapter, REG_SYS_FUNC_EN,
- (valu16 | (FEN_HWPDN | FEN_ELDR))); /* reset MAC */
+ /* reset MAC */
+ rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
+ valu16 | (FEN_HWPDN | FEN_ELDR));
valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
/* enable MCU , 8051 */
- rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));
+ rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
+ valu16 | FEN_CPUEN);
} else {
u8 retry_cnts = 0;
/* 2010/08/25 MH Accordign to RD alfred's
suggestion, we need to disable other */
/* HRCV INT to influence 8051 reset. */
- rtw_write8(padapter, REG_FWIMR, 0x20);
+ rtl8723au_write8(padapter, REG_FWIMR, 0x20);
/* 2011/02/15 MH According to Alex's
suggestion, close mask to prevent
incorrect FW write operation. */
- rtw_write8(padapter, REG_FTIMR, 0x00);
- rtw_write8(padapter, REG_FSIMR, 0x00);
+ rtl8723au_write8(padapter, REG_FTIMR, 0x00);
+ rtl8723au_write8(padapter, REG_FSIMR, 0x00);
/* 8051 reset by self */
- rtw_write8(padapter, REG_HMETFR + 3, 0x20);
+ rtl8723au_write8(padapter, REG_HMETFR + 3,
+ 0x20);
while ((retry_cnts++ < 100) &&
(FEN_CPUEN &
if (retry_cnts >= 100) {
/* Reset MAC and Enable 8051 */
- rtw_write8(padapter,
- REG_SYS_FUNC_EN + 1, 0x50);
+ rtl8723au_write8(padapter,
+ REG_SYS_FUNC_EN + 1,
+ 0x50);
mdelay(10);
}
}
}
/* Reset MAC and Enable 8051 */
- rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
- rtw_write8(padapter, REG_MCUFWDL, 0);
+ rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
+ rtl8723au_write8(padapter, REG_MCUFWDL, 0);
}
if (bWithoutHWSM) {
j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
******************************/
/* modify to 0x70A3 by Scott. */
- rtw_write16(padapter, REG_SYS_CLKR, 0x70A3);
- rtw_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
- rtw_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
- rtw_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
+ rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70A3);
+ rtl8723au_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
+ rtl8723au_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
+ rtl8723au_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
} else {
/* Disable all RF/BB power */
- rtw_write8(padapter, REG_RF_CTRL, 0x00);
+ rtl8723au_write8(padapter, REG_RF_CTRL, 0x00);
}
}
m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
******************************/
/* modify to 0x70a3 by Scott. */
- rtw_write16(padapter, REG_SYS_CLKR, 0x70a3);
+ rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70a3);
/* modify to 0x82 by Scott. */
- rtw_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82);
+ rtl8723au_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82);
}
static void _DisableAnalog(struct rtw_adapter *padapter, bool bWithoutHWSM)
clock automatically
******************************/
- rtw_write8(padapter, REG_LDOA15_CTRL, 0x04);
- /* rtw_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
+ rtl8723au_write8(padapter, REG_LDOA15_CTRL, 0x04);
+ /* rtl8723au_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
value8 = rtl8723au_read8(padapter, REG_LDOV12D_CTRL);
value8 &= (~LDV12_EN);
- rtw_write8(padapter, REG_LDOV12D_CTRL, value8);
+ rtl8723au_write8(padapter, REG_LDOV12D_CTRL, value8);
/* RT_TRACE(COMP_INIT, DBG_LOUD,
(" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n", value8)); */
}
if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
value8 |= BIT(3);
- rtw_write8(padapter, REG_SPS0_CTRL, value8);
+ rtl8723au_write8(padapter, REG_SPS0_CTRL, value8);
if (bWithoutHWSM) {
/* value16 |= (APDM_HOST | FSM_HSUS |/PFM_ALDN); */
value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
}
- rtw_write16(padapter, REG_APS_FSMCO, value16); /* 0x4802 */
+ rtl8723au_write16(padapter, REG_APS_FSMCO, value16); /* 0x4802 */
- rtw_write8(padapter, REG_RSV_CTRL, 0x0e);
+ rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0e);
}
/* HW Auto state machine */
SetBcnCtrlReg23a(padapter, val8, ~val8);
/* Set RCR */
- /* rtw_write32(padapter, REG_RCR, 0x70002a8e);
+ /* rtl8723au_write32(padapter, REG_RCR, 0x70002a8e);
CBSSID_DATA must set to 0 */
/* CBSSID_DATA must set to 0 */
- rtw_write32(padapter, REG_RCR, 0x7000228e);
+ rtl8723au_write32(padapter, REG_RCR, 0x7000228e);
/* enable to rx data frame */
- rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
+ rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
/* enable to rx ps-poll */
- rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
+ rtl8723au_write16(padapter, REG_RXFLTMAP1, 0x0400);
/* Beacon Control related register for first time */
- rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */
- rtw_write8(padapter, REG_DRVERLYINT, 0x05); /* 5ms */
- rtw_write8(padapter, REG_ATIMWND, 0x0a); /* 10ms for port0 */
- rtw_write16(padapter, REG_BCNTCFG, 0x00);
- rtw_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
+ /* 2ms */
+ rtl8723au_write8(padapter, REG_BCNDMATIM, 0x02);
+ /* 5ms */
+ rtl8723au_write8(padapter, REG_DRVERLYINT, 0x05);
+ /* 10ms for port0 */
+ rtl8723au_write8(padapter, REG_ATIMWND, 0x0a);
+ rtl8723au_write16(padapter, REG_BCNTCFG, 0x00);
+ rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
/* +32767 (~32ms) */
- rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
+ rtl8723au_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
/* reset TSF */
- rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
+ rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
/* enable BCN Function */
/* don't enable update TSF (due to TSF update when
val8 = rtl8723au_read8(padapter, MSR);
val8 = (val8 & 0xC) | mode;
- rtw_write8(padapter, MSR, val8);
+ rtl8723au_write8(padapter, MSR, val8);
}
void hw_var_set_macaddr(struct rtw_adapter *padapter, u8 *val)
reg_macid = REG_MACID;
for (idx = 0; idx < 6; idx++)
- rtw_write8(padapter, (reg_macid + idx), val[idx]);
+ rtl8723au_write8(padapter, (reg_macid + idx), val[idx]);
}
void hw_var_set_bssid(struct rtw_adapter *padapter, u8 *val)
reg_bssid = REG_BSSID;
for (idx = 0; idx < 6; idx++)
- rtw_write8(padapter, (reg_bssid + idx), val[idx]);
+ rtl8723au_write8(padapter, (reg_bssid + idx), val[idx]);
}
void hw_var_set_correct_tsf(struct rtw_adapter *padapter)
if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) ||
((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
/* pHalData->RegTxPause |= STOP_BCNQ;BIT(6) */
- /* rtw_write8(padapter, REG_TXPAUSE,
+ /* rtl8723au_write8(padapter, REG_TXPAUSE,
(rtl8723au_read8(Adapter, REG_TXPAUSE)|BIT(6))); */
StopTxBeacon(padapter);
}
/* disable related TSF function */
SetBcnCtrlReg23a(padapter, 0, EN_BCN_FUNCTION);
- rtw_write32(padapter, reg_tsftr, tsf);
- rtw_write32(padapter, reg_tsftr + 4, tsf >> 32);
+ rtl8723au_write32(padapter, reg_tsftr, tsf);
+ rtl8723au_write32(padapter, reg_tsftr + 4, tsf >> 32);
/* enable related TSF function */
SetBcnCtrlReg23a(padapter, EN_BCN_FUNCTION, 0);
void hw_var_set_mlme_disconnect(struct rtw_adapter *padapter)
{
/* reject all data frames */
- rtw_write16(padapter, REG_RXFLTMAP2, 0);
+ rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
/* reset TSF */
- rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
+ rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
/* disable update TSF */
SetBcnCtrlReg23a(padapter, DIS_TSF_UDT, 0);
u32 v32;
/* enable to rx data frame.Accept all data frame */
- /* rtw_write32(padapter, REG_RCR,
+ /* rtl8723au_write32(padapter, REG_RCR,
rtl8723au_read32(padapter, REG_RCR)|RCR_ADF); */
- rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
+ rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
v32 = rtl8723au_read32(padapter, REG_RCR);
v32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN;
- rtw_write32(padapter, REG_RCR, v32);
+ rtl8723au_write32(padapter, REG_RCR, v32);
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
RetryLimit =
} else if (type == 1) { /* joinbss_event callback when join res < 0 */
/* config RCR to receive different BSSID & not to
receive data frame during linking */
- rtw_write16(padapter, REG_RXFLTMAP2, 0);
+ rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
} else if (type == 2) { /* sta add event callback */
/* enable update TSF */
SetBcnCtrlReg23a(padapter, 0, DIS_TSF_UDT);
if (check_fwstate(pmlmepriv,
WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
/* fixed beacon issue for 8191su........... */
- rtw_write8(padapter, 0x542, 0x02);
+ rtl8723au_write8(padapter, 0x542, 0x02);
RetryLimit = 0x7;
}
}
- rtw_write16(padapter, REG_RL,
- RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit <<
- RETRY_LIMIT_LONG_SHIFT);
+ rtl8723au_write16(padapter, REG_RL,
+ RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit <<
+ RETRY_LIMIT_LONG_SHIFT);
#ifdef CONFIG_8723AU_BT_COEXIST
switch (type) {
Data = ((OriginalValue & (~BitMask)) | (Data << BitShift));
}
- rtw_write32(Adapter, RegAddr, Data);
+ rtl8723au_write32(Adapter, RegAddr, Data);
/* RTPRINT(FPHY, PHY_BBW, ("BBW MASK = 0x%lx Addr[0x%lx]= 0x%lx\n", BitMask, RegAddr, Data)); */
/* RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */
/* 2010.07.13 AMPDU aggregation number 9 */
/* rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
- rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A); /* By tynli. 2010.11.18. */
+ rtl8723au_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A);
if (is92C && (BOARD_USB_DONGLE == pHalData->BoardType))
- rtw_write8(Adapter, 0x40, 0x04);
+ rtl8723au_write8(Adapter, 0x40, 0x04);
return rtStatus;
}
/* 1. 0x28[1] = 1 */
TmpU1B = rtl8723au_read8(Adapter, REG_AFE_PLL_CTRL);
udelay(2);
- rtw_write8(Adapter, REG_AFE_PLL_CTRL, TmpU1B | BIT(1));
+ rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, TmpU1B | BIT(1));
udelay(2);
/* 2. 0x29[7:0] = 0xFF */
- rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
+ rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
udelay(2);
/* 3. 0x02[1:0] = 2b'11 */
TmpU1B = rtl8723au_read8(Adapter, REG_SYS_FUNC_EN);
- rtw_write8(Adapter, REG_SYS_FUNC_EN,
- (TmpU1B | FEN_BB_GLB_RSTn | FEN_BBRSTB));
+ rtl8723au_write8(Adapter, REG_SYS_FUNC_EN,
+ (TmpU1B | FEN_BB_GLB_RSTn | FEN_BBRSTB));
/* 4. 0x25[6] = 0 */
TmpU1B = rtl8723au_read8(Adapter, REG_AFE_XTAL_CTRL + 1);
- rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, TmpU1B & ~BIT(6));
+ rtl8723au_write8(Adapter, REG_AFE_XTAL_CTRL+1, TmpU1B & ~BIT(6));
/* 5. 0x24[20] = 0 Advised by SD3 Alex Wang. 2011.02.09. */
TmpU1B = rtl8723au_read8(Adapter, REG_AFE_XTAL_CTRL+2);
- rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, TmpU1B & ~BIT(4));
+ rtl8723au_write8(Adapter, REG_AFE_XTAL_CTRL+2, TmpU1B & ~BIT(4));
/* 6. 0x1f[7:0] = 0x07 */
- rtw_write8(Adapter, REG_RF_CTRL, 0x07);
+ rtl8723au_write8(Adapter, REG_RF_CTRL, 0x07);
/* */
/* Config BB and AGC */
switch (pHalData->CurrentChannelBW) {
case HT_CHANNEL_WIDTH_20:
regBwOpMode |= BW_OPMODE_20MHZ;
- rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
+ rtl8723au_write8(Adapter, REG_BWOPMODE, regBwOpMode);
break;
case HT_CHANNEL_WIDTH_40:
regBwOpMode &= ~BW_OPMODE_20MHZ;
- rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
+ rtl8723au_write8(Adapter, REG_BWOPMODE, regBwOpMode);
regRRSR_RSC = (regRRSR_RSC & 0x90) |
(pHalData->nCur40MhzPrimeSC << 5);
- rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
+ rtl8723au_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
break;
default:
#include <drv_types.h>
#include <rtl8723a_hal.h>
+#include <usb_ops_linux.h>
/*---------------------------Define Local Constant---------------------------*/
/* Define local structure for debug!!!!! */
writeVal = (writeVal > 8) ? (writeVal-8) : 0;
else
writeVal = (writeVal > 6) ? (writeVal-6) : 0;
- rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);
+ rtl8723au_write8(Adapter, RegOffset + i,
+ (u8)writeVal);
}
}
}
break;
case LED_PIN_LED0:
/* SW control led0 on. */
- rtw_write8(padapter, REG_LEDCFG0, (LedCfg&0xf0)|BIT(5)|BIT(6));
+ rtl8723au_write8(padapter, REG_LEDCFG0,
+ (LedCfg&0xf0)|BIT(5)|BIT(6));
break;
case LED_PIN_LED1:
/* SW control led1 on. */
- rtw_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT(6));
+ rtl8723au_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT(6));
break;
case LED_PIN_LED2:
LedCfg = rtl8723au_read8(padapter, REG_LEDCFG2);
/* SW control led1 on. */
- rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT(5));
+ rtl8723au_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT(5));
break;
default:
break;
break;
case LED_PIN_LED0:
/* SW control led0 on. */
- rtw_write8(padapter, REG_LEDCFG0, (LedCfg&0xf0)|BIT(5)|BIT(6));
+ rtl8723au_write8(padapter, REG_LEDCFG0,
+ (LedCfg&0xf0)|BIT(5)|BIT(6));
break;
case LED_PIN_LED1:
/* SW control led1 on. */
- rtw_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT(5)|BIT(6));
+ rtl8723au_write8(padapter, REG_LEDCFG1,
+ (LedCfg&0x00)|BIT(5)|BIT(6));
break;
case LED_PIN_LED2:
LedCfg = rtl8723au_read8(padapter, REG_LEDCFG2);
/* SW control led1 on. */
- rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT(3)|BIT(5));
+ rtl8723au_write8(padapter, REG_LEDCFG2,
+ (LedCfg&0x80)|BIT(3)|BIT(5));
break;
default:
break;
/* RSV_CTRL 0x1C[7:0] = 0x00
unlock ISO/CLK/Power control register */
- rtw_write8(padapter, REG_RSV_CTRL, 0x0);
+ rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0);
/* HW Power on sequence */
if (!HalPwrSeqCmdParsing23a(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
/* 0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051 */
value8 = rtl8723au_read8(padapter, REG_APS_FSMCO+2);
- rtw_write8(padapter, REG_APS_FSMCO + 2, value8 | BIT(3));
+ rtl8723au_write8(padapter, REG_APS_FSMCO + 2, value8 | BIT(3));
/* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
/* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy.
value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN |
ENSEC | CALTMR_EN);
- rtw_write16(padapter, REG_CR, value16);
+ rtl8723au_write16(padapter, REG_CR, value16);
/* for Efuse PG, suggest by Jackie 2011.11.23 */
PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT(28)|BIT(29)|BIT(30), 0x06);
/* HISR - turn all on */
value32 = 0xFFFFFFFF;
- rtw_write32(Adapter, REG_HISR, value32);
+ rtl8723au_write32(Adapter, REG_HISR, value32);
/* HIMR - turn all on */
- rtw_write32(Adapter, REG_HIMR, value32);
+ rtl8723au_write32(Adapter, REG_HIMR, value32);
}
static void _InitQueueReservedPage(struct rtw_adapter *Adapter)
WMM_NORMAL_PAGE_NUM_NPQ : NORMAL_PAGE_NUM_NPQ;
}
value8 = (u8)_NPQ(numNQ);
- rtw_write8(Adapter, REG_RQPN_NPQ, value8);
+ rtl8723au_write8(Adapter, REG_RQPN_NPQ, value8);
}
/* TX DMA */
value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
- rtw_write32(Adapter, REG_RQPN, value32);
+ rtl8723au_write32(Adapter, REG_RQPN, value32);
}
static void _InitTxBufferBoundary(struct rtw_adapter *Adapter)
else /* for WMM */
txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
- rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
- rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
- rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
- rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
- rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
+ rtl8723au_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
+ rtl8723au_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
+ rtl8723au_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
+ rtl8723au_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
+ rtl8723au_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
}
static void _InitPageBoundary(struct rtw_adapter *Adapter)
/* srand(static_cast<unsigned int>(time(NULL))); */
u16 rxff_bndy = 0x27FF;/* rand() % 1) ? 0x27FF : 0x23FF; */
- rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
+ rtl8723au_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
/* TODO: ?? shall we set tx boundary? */
}
_TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
_TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
- rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
+ rtl8723au_write16(Adapter, REG_TRXDMA_CTRL, value16);
}
static void _InitNormalChipOneOutEpPriority(struct rtw_adapter *Adapter)
/* TODO: use the other function to set network type */
value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
- rtw_write32(Adapter, REG_CR, value32);
+ rtl8723au_write32(Adapter, REG_CR, value32);
}
static void _InitTransferPageSize(struct rtw_adapter *Adapter)
u8 value8;
value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
- rtw_write8(Adapter, REG_PBP, value8);
+ rtl8723au_write8(Adapter, REG_PBP, value8);
}
static void _InitDriverInfoSize(struct rtw_adapter *Adapter, u8 drvInfoSize)
{
- rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
+ rtl8723au_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
}
static void _InitWMACSetting(struct rtw_adapter *Adapter)
/* some REG_RCR will be modified later by
phy_ConfigMACWithHeaderFile() */
- rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
+ rtl8723au_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
/* Accept all multicast address */
- rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
- rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
+ rtl8723au_write32(Adapter, REG_MAR, 0xFFFFFFFF);
+ rtl8723au_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
/* Accept all data frames */
/* value16 = 0xFFFF; */
- /* rtw_write16(Adapter, REG_RXFLTMAP2, value16); */
+ /* rtl8723au_write16(Adapter, REG_RXFLTMAP2, value16); */
/* 2010.09.08 hpfan */
/* Since ADF is removed from RCR, ps-poll will not be indicate
/* RxFilterMap should mask ps-poll to gurantee AP mode can
rx ps-poll. */
/* value16 = 0x400; */
- /* rtw_write16(Adapter, REG_RXFLTMAP1, value16); */
+ /* rtl8723au_write16(Adapter, REG_RXFLTMAP1, value16); */
/* Accept all management frames */
/* value16 = 0xFFFF; */
- /* rtw_write16(Adapter, REG_RXFLTMAP0, value16); */
+ /* rtl8723au_write16(Adapter, REG_RXFLTMAP0, value16); */
/* enable RX_SHIFT bits */
- /* rtw_write8(Adapter, REG_TRXDMA_CTRL, rtl8723au_read8(Adapter,
+ /* rtl8723au_write8(Adapter, REG_TRXDMA_CTRL, rtl8723au_read8(Adapter,
REG_TRXDMA_CTRL)|BIT(1)); */
}
value32 = rtl8723au_read32(Adapter, REG_RRSR);
value32 &= ~RATE_BITMAP_ALL;
value32 |= RATE_RRSR_CCK_ONLY_1M;
- rtw_write32(Adapter, REG_RRSR, value32);
+ rtl8723au_write32(Adapter, REG_RRSR, value32);
/* CF-END Threshold */
- /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
+ /* m_spIoBase->rtl8723au_write8(REG_CFEND_TH, 0x1); */
/* SIFS (used in NAV) */
value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
- rtw_write16(Adapter, REG_SPEC_SIFS, value16);
+ rtl8723au_write16(Adapter, REG_SPEC_SIFS, value16);
/* Retry Limit */
value16 = _LRL(0x30) | _SRL(0x30);
- rtw_write16(Adapter, REG_RL, value16);
+ rtl8723au_write16(Adapter, REG_RL, value16);
}
static void _InitRateFallback(struct rtw_adapter *Adapter)
{
/* Set Data Auto Rate Fallback Retry Count register. */
- rtw_write32(Adapter, REG_DARFRC, 0x00000000);
- rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
- rtw_write32(Adapter, REG_RARFRC, 0x04030201);
- rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
+ rtl8723au_write32(Adapter, REG_DARFRC, 0x00000000);
+ rtl8723au_write32(Adapter, REG_DARFRC+4, 0x10080404);
+ rtl8723au_write32(Adapter, REG_RARFRC, 0x04030201);
+ rtl8723au_write32(Adapter, REG_RARFRC+4, 0x08070605);
}
static void _InitEDCA(struct rtw_adapter *Adapter)
{
/* Set Spec SIFS (used in NAV) */
- rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
- rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
+ rtl8723au_write16(Adapter, REG_SPEC_SIFS, 0x100a);
+ rtl8723au_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
/* Set SIFS for CCK */
- rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
+ rtl8723au_write16(Adapter, REG_SIFS_CTX, 0x100a);
/* Set SIFS for OFDM */
- rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
+ rtl8723au_write16(Adapter, REG_SIFS_TRX, 0x100a);
/* TXOP */
- rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
- rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
- rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
- rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
+ rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
+ rtl8723au_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
+ rtl8723au_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
+ rtl8723au_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
}
static void _InitHWLed(struct rtw_adapter *Adapter)
static void _InitRDGSetting(struct rtw_adapter *Adapter)
{
- rtw_write8(Adapter, REG_RD_CTRL, 0xFF);
- rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
- rtw_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
+ rtl8723au_write8(Adapter, REG_RD_CTRL, 0xFF);
+ rtl8723au_write16(Adapter, REG_RD_NAV_NXT, 0x200);
+ rtl8723au_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
}
static void _InitRetryFunction(struct rtw_adapter *Adapter)
value8 = rtl8723au_read8(Adapter, REG_FWHW_TXQ_CTRL);
value8 |= EN_AMPDU_RTY_NEW;
- rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
+ rtl8723au_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
/* Set ACK timeout */
- rtw_write8(Adapter, REG_ACKTO, 0x40);
+ rtl8723au_write8(Adapter, REG_ACKTO, 0x40);
}
/*-----------------------------------------------------------------------------
DBG_8723A("pwrdown, 0x5c(BIT7) =%02x\n", val8);
rfpowerstate = (val8 & BIT(7)) ? rf_off : rf_on;
} else { /* rf on/off */
- rtw_write8(pAdapter, REG_MAC_PINMUX_CFG,
- rtl8723au_read8(pAdapter, REG_MAC_PINMUX_CFG) &
- ~BIT(3));
+ rtl8723au_write8(pAdapter, REG_MAC_PINMUX_CFG,
+ rtl8723au_read8(pAdapter, REG_MAC_PINMUX_CFG) &
+ ~BIT(3));
val8 = rtl8723au_read8(pAdapter, REG_GPIO_IO_SEL);
DBG_8723A("GPIO_IN =%02x\n", val8);
rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off;
/* HW SEQ CTRL */
/* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
- rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
+ rtl8723au_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
/* */
/* Disable BAR, suggested by Scott */
/* 2010.04.09 add by hpfan */
/* */
- rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
+ rtl8723au_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
if (pregistrypriv->wifi_spec)
- rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
+ rtl8723au_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
/* Move by Neo for USB SS from above setp */
_RfPowerSave(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
/* fixed USB interface interference issue */
- rtw_write8(Adapter, 0xfe40, 0xe0);
- rtw_write8(Adapter, 0xfe41, 0x8d);
- rtw_write8(Adapter, 0xfe42, 0x80);
- rtw_write32(Adapter, 0x20c, 0xfd0320);
+ rtl8723au_write8(Adapter, 0xfe40, 0xe0);
+ rtl8723au_write8(Adapter, 0xfe41, 0x8d);
+ rtl8723au_write8(Adapter, 0xfe42, 0x80);
+ rtl8723au_write32(Adapter, 0x20c, 0xfd0320);
/* Solve too many protocol error on USB bus */
if (!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID)) {
/* 0xE6 = 0x94 */
- rtw_write8(Adapter, 0xFE40, 0xE6);
- rtw_write8(Adapter, 0xFE41, 0x94);
- rtw_write8(Adapter, 0xFE42, 0x80);
+ rtl8723au_write8(Adapter, 0xFE40, 0xE6);
+ rtl8723au_write8(Adapter, 0xFE41, 0x94);
+ rtl8723au_write8(Adapter, 0xFE42, 0x80);
/* 0xE0 = 0x19 */
- rtw_write8(Adapter, 0xFE40, 0xE0);
- rtw_write8(Adapter, 0xFE41, 0x19);
- rtw_write8(Adapter, 0xFE42, 0x80);
+ rtl8723au_write8(Adapter, 0xFE40, 0xE0);
+ rtl8723au_write8(Adapter, 0xFE41, 0x19);
+ rtl8723au_write8(Adapter, 0xFE42, 0x80);
/* 0xE5 = 0x91 */
- rtw_write8(Adapter, 0xFE40, 0xE5);
- rtw_write8(Adapter, 0xFE41, 0x91);
- rtw_write8(Adapter, 0xFE42, 0x80);
+ rtl8723au_write8(Adapter, 0xFE40, 0xE5);
+ rtl8723au_write8(Adapter, 0xFE41, 0x91);
+ rtl8723au_write8(Adapter, 0xFE42, 0x80);
/* 0xE2 = 0x81 */
- rtw_write8(Adapter, 0xFE40, 0xE2);
- rtw_write8(Adapter, 0xFE41, 0x81);
- rtw_write8(Adapter, 0xFE42, 0x80);
+ rtl8723au_write8(Adapter, 0xFE40, 0xE2);
+ rtl8723au_write8(Adapter, 0xFE41, 0x81);
+ rtl8723au_write8(Adapter, 0xFE42, 0x80);
}
}
/* ack for xmit mgmt frames. */
- rtw_write32(Adapter, REG_FWHW_TXQ_CTRL,
- rtl8723au_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
+ rtl8723au_write32(Adapter, REG_FWHW_TXQ_CTRL,
+ rtl8723au_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
exit:
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */
/* 2. Force PWM, Enable SPS18_LDO_Marco_Block */
- rtw_write8(Adapter, REG_SPS0_CTRL,
- rtl8723au_read8(Adapter, REG_SPS0_CTRL) |
- BIT(0) | BIT(3));
+ rtl8723au_write8(Adapter, REG_SPS0_CTRL,
+ rtl8723au_read8(Adapter, REG_SPS0_CTRL) |
+ BIT(0) | BIT(3));
/* 3. restore BB, AFE control register. */
/* RF */
} else { /* Level 2 or others. */
/* h. AFE_PLL_CTRL 0x28[7:0] = 0x80
disable AFE PLL */
- rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
+ rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
/* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F
gated AFE DIG_CLOCK */
- rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
+ rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
mdelay(1);
/* 2. Force PWM, Enable SPS18_LDO_Marco_Block */
- rtw_write8(Adapter, REG_SPS0_CTRL,
- rtl8723au_read8(Adapter, REG_SPS0_CTRL) |
- BIT(0) | BIT(3));
+ rtl8723au_write8(Adapter, REG_SPS0_CTRL,
+ rtl8723au_read8(Adapter, REG_SPS0_CTRL) |
+ BIT(0) | BIT(3));
/* 3. restore BB, AFE control register. */
/* RF */
/* 5. gated MAC Clock */
bytetmp = rtl8723au_read8(Adapter, REG_APSD_CTRL);
- rtw_write8(Adapter, REG_APSD_CTRL, bytetmp & ~BIT(6));
+ rtl8723au_write8(Adapter, REG_APSD_CTRL,
+ bytetmp & ~BIT(6));
mdelay(10);
/* Set BB reset at first */
- rtw_write8(Adapter, REG_SYS_FUNC_EN, 0x17); /* 0x16 */
+ /* 0x16 */
+ rtl8723au_write8(Adapter, REG_SYS_FUNC_EN, 0x17);
/* Enable TX */
- rtw_write8(Adapter, REG_TXPAUSE, 0x0);
+ rtl8723au_write8(Adapter, REG_TXPAUSE, 0x0);
}
break;
case rf_sleep:
bRFRegOffsetMask, 0);
/* 4. Force PFM , disable SPS18_LDO_Marco_Block */
- rtw_write8(Adapter, REG_SPS0_CTRL, value8);
+ rtl8723au_write8(Adapter, REG_SPS0_CTRL, value8);
} else { /* Level 2 or others. */
RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n"));
{
u8 eRFPath = RF_PATH_A, value8 = 0;
- rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
+ rtl8723au_write8(Adapter, REG_TXPAUSE, 0xFF);
PHY_SetRFReg(Adapter,
(enum RF_RADIO_PATH)eRFPath,
0x0, bMaskByte0, 0x0);
value8 |= APSDOFF;
/* 0x40 */
- rtw_write8(Adapter, REG_APSD_CTRL, value8);
+ rtl8723au_write8(Adapter, REG_APSD_CTRL,
+ value8);
/* After switch APSD, we need to delay
for stability */
value8 |= (FEN_USBD | FEN_USBA |
FEN_BB_GLB_RSTn);
/* 0x16 */
- rtw_write8(Adapter, REG_SYS_FUNC_EN, value8);
+ rtl8723au_write8(Adapter, REG_SYS_FUNC_EN,
+ value8);
}
/* Disable RF and BB only for SelectSuspend. */
bRFRegOffsetMask, 0);
/* 4. Force PFM , disable SPS18_LDO_Marco_Block */
- rtw_write8(Adapter, REG_SPS0_CTRL, value8);
+ rtl8723au_write8(Adapter, REG_SPS0_CTRL, value8);
/* 2010/10/13 MH/Isaachsu exchange sequence. */
/* h. AFE_PLL_CTRL 0x28[7:0] = 0x80
disable AFE PLL */
- rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
+ rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
mdelay(1);
/* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F
gated AFE DIG_CLOCK */
- rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
+ rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
}
break;
default:
PWR_INTF_USB_MSK, rtl8723AU_enter_lps_flow);
/* 2. 0x1F[7:0] = 0 turn off RF */
- rtw_write8(Adapter, REG_RF_CTRL, 0x00);
+ rtl8723au_write8(Adapter, REG_RF_CTRL, 0x00);
/* ==== Reset digital sequence ====== */
if ((rtl8723au_read8(Adapter, REG_MCUFWDL) & BIT(7)) &&
/* Reset MCU. Suggested by Filen. 2011.01.26. by tynli. */
u1bTmp = rtl8723au_read8(Adapter, REG_SYS_FUNC_EN+1);
- rtw_write8(Adapter, REG_SYS_FUNC_EN+1, u1bTmp & ~BIT(2));
+ rtl8723au_write8(Adapter, REG_SYS_FUNC_EN+1, u1bTmp & ~BIT(2));
/* g. MCUFWDL 0x80[1:0]= 0 reset MCU ready status */
- rtw_write8(Adapter, REG_MCUFWDL, 0x00);
+ rtl8723au_write8(Adapter, REG_MCUFWDL, 0x00);
/* ==== Reset digital sequence end ====== */
/* Card disable power action flow */
/* Reset MCU IO Wrapper, added by Roger, 2011.08.30. */
u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1);
- rtw_write8(Adapter, REG_RSV_CTRL+1, u1bTmp & ~BIT(0));
+ rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp & ~BIT(0));
u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1);
- rtw_write8(Adapter, REG_RSV_CTRL+1, u1bTmp | BIT(0));
+ rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp | BIT(0));
/* 7. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
- rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
+ rtl8723au_write8(Adapter, REG_RSV_CTRL, 0x0e);
}
static int rtl8723au_hal_deinit(struct rtw_adapter *padapter)
pHalData->IntrMask[0] = rtl8723au_read32(Adapter, REG_USB_HIMR);
MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
pHalData->IntrMask[0] |= UHIMR_C2HCMD|UHIMR_CPWM;
- rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
+ rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
exit:
RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
("<=== usb_inirp_init\n"));
MSG_8723A("%s pHalData->IntrMask = 0x%04x\n", __func__,
pHalData->IntrMask[0]);
pHalData->IntrMask[0] = 0x0;
- rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
+ rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
("\n <=== usb_rx_deinit\n"));
return _SUCCESS;
value32 = rtl8723au_read32(Adapter, EFUSE_TEST);
value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
- rtw_write32(Adapter, EFUSE_TEST, value32);
+ rtl8723au_write32(Adapter, EFUSE_TEST, value32);
}
void rtl8723a_read_adapter_info(struct rtw_adapter *Adapter)
if (shortGIrate == true)
init_rate |= BIT(6);
- rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate);
+ rtl8723au_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id),
+ init_rate);
}
/* set ra_id */
return le32_to_cpu(data);
}
-static int usb_write8(struct rtw_adapter *padapter, u32 addr, u8 val)
+int rtl8723au_write8(struct rtw_adapter *padapter, u32 addr, u8 val)
{
u8 request;
u8 requesttype;
return ret;
}
-static int usb_write16(struct rtw_adapter *padapter, u32 addr, u16 val)
+int rtl8723au_write16(struct rtw_adapter *padapter, u32 addr, u16 val)
{
u8 request;
u8 requesttype;
return ret;
}
-static int usb_write32(struct rtw_adapter *padapter, u32 addr, u32 val)
+int rtl8723au_write32(struct rtw_adapter *padapter, u32 addr, u32 val)
{
u8 request;
u8 requesttype;
return ret;
}
-static int usb_writeN(struct rtw_adapter *padapter,
- u32 addr, u32 length, u8 *pdata)
+int rtl8723au_writeN(struct rtw_adapter *padapter,
+ u32 addr, u32 length, u8 *pdata)
{
u8 request;
u8 requesttype;
}
}
-void rtl8723au_set_intf_ops(struct rtw_adapter *padapter)
-{
- struct _io_ops *pops = &padapter->io_ops;
-
- memset((u8 *)pops, 0, sizeof(struct _io_ops));
-
- pops->_write8 = &usb_write8;
- pops->_write16 = &usb_write16;
- pops->_write32 = &usb_write32;
- pops->_writeN = &usb_writeN;
-}
-
void rtl8723au_set_hw_type(struct rtw_adapter *padapter)
{
padapter->chip_type = RTL8723A;
struct mlme_ext_priv mlmeextpriv;
struct cmd_priv cmdpriv;
struct evt_priv evtpriv;
- struct _io_ops io_ops;
struct xmit_priv xmitpriv;
struct recv_priv recvpriv;
struct sta_priv stapriv;
struct intf_priv;
-struct _io_ops
-{
- int (*_write8)(struct rtw_adapter *adapter, u32 addr, u8 val);
- int (*_write16)(struct rtw_adapter *adapter, u32 addr, u16 val);
- int (*_write32)(struct rtw_adapter *adapter, u32 addr, u32 val);
- int (*_writeN)(struct rtw_adapter *adapter, u32 addr, u32 length,
- u8 *pdata);
-};
-
struct io_req {
struct list_head list;
u32 addr;
void _rtw_read_port23a_cancel(struct rtw_adapter *adapter);
-int _rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val);
-int _rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val);
-int _rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val);
-int _rtw_writeN23a(struct rtw_adapter *adapter, u32 addr, u32 length, u8 *pdata);
-
void _rtw_write_port23a_cancel(struct rtw_adapter *adapter);
#ifdef DBG_IO
bool match_read_sniff_ranges(u16 addr, u16 len);
bool match_write_sniff_ranges(u16 addr, u16 len);
-
-int dbg_rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
-int dbg_rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
-int dbg_rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
-int dbg_rtw_writeN23a(struct rtw_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line);
-
-#define rtw_write8(adapter, addr, val) dbg_rtw_write823a((adapter), (addr), (val), __FUNCTION__, __LINE__)
-#define rtw_write16(adapter, addr, val) dbg_rtw_write1623a((adapter), (addr), (val), __FUNCTION__, __LINE__)
-#define rtw_write32(adapter, addr, val) dbg_rtw_write3223a((adapter), (addr), (val), __FUNCTION__, __LINE__)
-#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN23a((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
-#else /* DBG_IO */
-#define rtw_write8(adapter, addr, val) _rtw_write823a((adapter), (addr), (val))
-#define rtw_write16(adapter, addr, val) _rtw_write1623a((adapter), (addr), (val))
-#define rtw_write32(adapter, addr, val) _rtw_write3223a((adapter), (addr), (val))
-#define rtw_writeN(adapter, addr, length, data) _rtw_writeN23a((adapter), (addr), (length), (data))
#endif /* DBG_IO */
#define PlatformEFIOWrite1Byte(_a,_b,_c) \
- rtw_write8(_a,_b,_c)
+ rtl8723au_write8(_a,_b,_c)
#define PlatformEFIOWrite2Byte(_a,_b,_c) \
- rtw_write16(_a,_b,_c)
+ rtl8723au_write16(_a,_b,_c)
#define PlatformEFIOWrite4Byte(_a,_b,_c) \
- rtw_write32(_a,_b,_c)
+ rtl8723au_write32(_a,_b,_c)
#define PlatformEFIORead1Byte(_a,_b) rtl8723au_read8(_a,_b)
#define PlatformEFIORead2Byte(_a,_b) rtl8723au_read16(_a,_b)
void rtl8723au_set_hw_type(struct rtw_adapter *padapter);
-void rtl8723au_set_intf_ops(struct rtw_adapter *padapter);
-
void rtl8723au_recv_tasklet(void *priv);
void rtl8723au_xmit_tasklet(void *priv);
u8 rtl8723au_read8(struct rtw_adapter *padapter, u32 addr);
u16 rtl8723au_read16(struct rtw_adapter *padapter, u32 addr);
u32 rtl8723au_read32(struct rtw_adapter *padapter, u32 addr);
+int rtl8723au_write8(struct rtw_adapter *padapter, u32 addr, u8 val);
+int rtl8723au_write16(struct rtw_adapter *padapter, u32 addr, u16 val);
+int rtl8723au_write32(struct rtw_adapter *padapter, u32 addr, u32 val);
+int rtl8723au_writeN(struct rtw_adapter *padapter,
+ u32 addr, u32 length, u8 *pdata);
#endif
if (!padapter->HalData)
goto free_wdev;
- rtl8723au_set_intf_ops(padapter);
-
/* step read_chip_version */
rtl8723a_read_chip_version(padapter);
projects / openwrt / staging / blogic.git / commitdiff