Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 1 Aug 2016 22:47:01 +0000 (18:47 -0400)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 1 Aug 2016 22:47:01 +0000 (18:47 -0400)
Pull 64-bit ARM DT updates from Olof Johansson:
 "Just as the 32-bit contents, the 64-bit device tree branch also
  contains a number of additions this release cycle.

  New platforms:
   - LG LG1313
   - Mediatek MT6755
   - Renesas r8a7796
   - Broadcom 2837

  Other platforms with larger updates are:
   - Nvidia X1 platforms (USB 3.0, regulators, display subsystem)
   - Mediatek MT8173 (display subsystem added)
   - Rockchip RK3399 (a lot of new peripherals)
   - ARM Juno reference implementation (SCPI power domains, coresight,
     thermal)"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits)
  arm64: tegra: Enable HDMI on Jetson TX1
  arm64: tegra: Add sor1_src clock
  arm64: tegra: Add XUSB powergates on Tegra210
  arm64: tegra: Add DPAUX pinctrl bindings
  arm64: tegra: Add ACONNECT bus node for Tegra210
  arm64: tegra: Add audio powergate node for Tegra210
  arm64: tegra: Add regulators for Tegra210 Smaug
  arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
  arm64: tegra: Enable XUSB controller on Jetson TX1
  arm64: tegra: Enable debug serial on Jetson TX1
  arm64: tegra: Add Tegra210 XUSB controller
  arm64: tegra: Add Tegra210 XUSB pad controller
  arm64: tegra: Add DSI panel on Jetson TX1
  arm64: tegra: p2597: Add SDMMC power supplies
  arm64: tegra: Add PMIC support on Jetson TX1
  Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock"
  arm64: dts: hi6220: Add pl031 RTC support
  arm64: dts: r8a7796/salvator-x: Enable watchdog timer
  arm64: dts: r8a7796: Add RWDT node
  arm64: dts: r8a7796: Use SYSC "always-on" PM Domain
  ...

1  2 
Documentation/devicetree/bindings/arm/shmobile.txt
arch/arm64/Kconfig.platforms
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
arch/arm64/boot/dts/apm/apm-storm.dtsi
arch/arm64/boot/dts/broadcom/ns2-svk.dts
arch/arm64/boot/dts/broadcom/ns2.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
arch/arm64/boot/dts/mediatek/mt8173.dtsi
arch/arm64/boot/dts/rockchip/rk3399.dtsi

Simple merge
index 2e1e5daa1dc7a187e3d89b6746d10bc130653c80,21028b145d91826bb53c7118f421801fab7c2b15..1425ed41620c42b024edaec35bb0ccc3588a68c2
                sgenet0: ethernet@1f610000 {
                        compatible = "apm,xgene2-sgenet";
                        status = "disabled";
 -                      reg = <0x0 0x1f610000 0x0 0x10000>,
 +                      reg = <0x0 0x1f610000 0x0 0xd100>,
-                             <0x0 0x1f600000 0x0 0Xd100>,
-                             <0x0 0x20000000 0x0 0X20000>;
+                             <0x0 0x1f600000 0x0 0xd100>,
+                             <0x0 0x20000000 0x0 0x20000>;
                        interrupts = <0 96 4>,
                                     <0 97 4>;
                        dma-coherent;
index 6bf7cbe2e72d502d3f417290245bd4c953c53511,91c73b8634750af82d12856deba02439132409d8..f1c2c713f9b0896b2dc777a960f84fe741d43ff8
                        compatible = "apm,xgene1-sgenet";
                        status = "disabled";
                        reg = <0x0 0x1f210030 0x0 0xd100>,
-                             <0x0 0x1f200000 0x0 0Xc300>,
-                             <0x0 0x1B000000 0x0 0X8000>;
+                             <0x0 0x1f200000 0x0 0xc300>,
+                             <0x0 0x1b000000 0x0 0x8000>;
                        reg-names = "enet_csr", "ring_csr", "ring_cmd";
-                       interrupts = <0x0 0xAC 0x4>,
-                                    <0x0 0xAD 0x4>;
+                       interrupts = <0x0 0xac 0x4>,
+                                    <0x0 0xad 0x4>;
                        port-id = <1>;
                        dma-coherent;
 -                      clocks = <&sge1clk 0>;
                        local-mac-address = [00 00 00 00 00 00];
                        phy-connection-type = "sgmii";
 +                      phy-handle = <&sgenet1phy>;
                };
  
                xgenet: ethernet@1f610000 {
index ea5603fd106a592fad606b2ee8f0427d54a81403,b062a44a39c7006ca138979c5657fa380e8ead76..2d7872a36b91232c1007358dfdea212052dac0b1
        };
  };
  
 +&mdio_mux_iproc {
 +      mdio@10 {
 +              gphy0: eth-phy@10 {
 +                      reg = <0x10>;
 +              };
 +      };
 +};
++
+ &pinctrl {
+       pinctrl-names = "default";
+       pinctrl-0 = <&nand_sel>;
+       nand_sel: nand_sel {
+               function = "nand";
+               groups = "nand_grp";
+       };
+ };
index 46b78fa89f4c60664de9ce2a06d6f475bb727fd1,d1dc812daaabcdddf6c8404575da21b1ccbdaf49..f53b0955bfd31c44ab05dc328bef1e4bd3dadcf4
                                      IRQ_TYPE_LEVEL_HIGH)>;
                };
  
+               cci@65590000 {
+                       compatible = "arm,cci-400";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x65590000 0x1000>;
+                       ranges = <0 0x65590000 0x10000>;
+                       pmu@9000 {
+                               compatible = "arm,cci-400-pmu,r1",
+                                            "arm,cci-400-pmu";
+                               reg = <0x9000 0x4000>;
+                               interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
 +              mdio_mux_iproc: mdio-mux@6602023c {
 +                      compatible = "brcm,mdio-mux-iproc";
 +                      reg = <0x6602023c 0x14>;
 +                      #address-cells = <1>;
 +                      #size-cells = <0>;
 +
 +                      mdio@0 {
 +                              reg = <0x0>;
 +                              #address-cells = <1>;
 +                              #size-cells = <0>;
 +
 +                              pci_phy0: pci-phy@0 {
 +                                      compatible = "brcm,ns2-pcie-phy";
 +                                      reg = <0x0>;
 +                                      #phy-cells = <0>;
 +                                      status = "disabled";
 +                              };
 +                      };
 +
 +                      mdio@7 {
 +                              reg = <0x7>;
 +                              #address-cells = <1>;
 +                              #size-cells = <0>;
 +
 +                              pci_phy1: pci-phy@0 {
 +                                      compatible = "brcm,ns2-pcie-phy";
 +                                      reg = <0x0>;
 +                                      #phy-cells = <0>;
 +                                      status = "disabled";
 +                              };
 +                      };
 +
 +                      mdio@10 {
 +                              reg = <0x10>;
 +                              #address-cells = <1>;
 +                              #size-cells = <0>;
 +                      };
 +              };
 +
                timer0: timer@66030000 {
                        compatible = "arm,sp804", "arm,primecell";
                        reg = <0x66030000 0x1000>;