/* Private functions */
+#ifdef CONFIG_COMMON_CLK
+int omap2_clk_apll96_enable(struct clk_hw *hw)
+#else
static int _apll96_enable(struct clk *clk)
+#endif
{
return omap2xxx_cm_apll96_enable();
}
+#ifdef CONFIG_COMMON_CLK
+int omap2_clk_apll54_enable(struct clk_hw *hw)
+#else
static int _apll54_enable(struct clk *clk)
+#endif
{
return omap2xxx_cm_apll54_enable();
}
+#ifdef CONFIG_COMMON_CLK
+static void _apll96_allow_idle(struct clk_hw_omap *clk)
+#else
static void _apll96_allow_idle(struct clk *clk)
+#endif
{
omap2xxx_cm_set_apll96_auto_low_power_stop();
}
+#ifdef CONFIG_COMMON_CLK
+static void _apll96_deny_idle(struct clk_hw_omap *clk)
+#else
static void _apll96_deny_idle(struct clk *clk)
+#endif
{
omap2xxx_cm_set_apll96_disable_autoidle();
}
+#ifdef CONFIG_COMMON_CLK
+static void _apll54_allow_idle(struct clk_hw_omap *clk)
+#else
static void _apll54_allow_idle(struct clk *clk)
+#endif
{
omap2xxx_cm_set_apll54_auto_low_power_stop();
}
+#ifdef CONFIG_COMMON_CLK
+static void _apll54_deny_idle(struct clk_hw_omap *clk)
+#else
static void _apll54_deny_idle(struct clk *clk)
+#endif
{
omap2xxx_cm_set_apll54_disable_autoidle();
}
+#ifdef CONFIG_COMMON_CLK
+void omap2_clk_apll96_disable(struct clk_hw *hw)
+#else
static void _apll96_disable(struct clk *clk)
+#endif
{
omap2xxx_cm_apll96_disable();
}
+#ifdef CONFIG_COMMON_CLK
+void omap2_clk_apll54_disable(struct clk_hw *hw)
+#else
static void _apll54_disable(struct clk *clk)
+#endif
{
omap2xxx_cm_apll54_disable();
}
/* Public data */
+#ifdef CONFIG_COMMON_CLK
+const struct clk_hw_omap_ops clkhwops_apll54 = {
+ .allow_idle = _apll54_allow_idle,
+ .deny_idle = _apll54_deny_idle,
+};
+const struct clk_hw_omap_ops clkhwops_apll96 = {
+ .allow_idle = _apll96_allow_idle,
+ .deny_idle = _apll96_deny_idle,
+};
+#else
const struct clkops clkops_apll96 = {
.enable = _apll96_enable,
.disable = _apll96_disable,
.allow_idle = _apll54_allow_idle,
.deny_idle = _apll54_deny_idle,
};
+#endif
/* Public functions */
* REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
* instead. Add some mechanism to optionally enter this mode.
*/
+#ifdef CONFIG_COMMON_CLK
+static void _allow_idle(struct clk_hw_omap *clk)
+#else
static void _allow_idle(struct clk *clk)
+#endif
{
if (!clk || !clk->dpll_data)
return;
*
* Disable DPLL automatic idle control. No return value.
*/
+#ifdef CONFIG_COMMON_CLK
+static void _deny_idle(struct clk_hw_omap *clk)
+#else
static void _deny_idle(struct clk *clk)
+#endif
{
if (!clk || !clk->dpll_data)
return;
/* Public data */
-
+#ifdef CONFIG_COMMON_CLK
+const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
+ .allow_idle = _allow_idle,
+ .deny_idle = _deny_idle,
+};
+#else
const struct clkops clkops_omap2xxx_dpll_ops = {
.allow_idle = _allow_idle,
.deny_idle = _deny_idle,
};
+#endif
* (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
* during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
*/
+#ifdef CONFIG_COMMON_CLK
+static struct clk_hw_omap *dpll_core_ck;
+#else
static struct clk *dpll_core_ck;
+#endif
/**
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
}
+#ifdef CONFIG_COMMON_CLK
+unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
+ unsigned long parent_rate)
+#else
unsigned long omap2_dpllcore_recalc(struct clk *clk)
+#endif
{
return omap2xxx_clk_get_core_rate();
}
+#ifdef CONFIG_COMMON_CLK
+int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+#else
int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
{
+#endif
u32 cur_rate, low, mult, div, valid_rate, done_rate;
u32 bypass = 0;
struct prcm_config tmpset;
* statically defined, this code may need to change to increment some
* kind of use count on dpll_ck.
*/
+#ifdef CONFIG_COMMON_CLK
+void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
+#else
void omap2xxx_clkt_dpllcore_init(struct clk *clk)
+#endif
{
WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
+#ifdef CONFIG_COMMON_CLK
+ dpll_core_ck = to_clk_hw_omap(hw);
+#else
dpll_core_ck = clk;
+#endif
}
* clk_enable/clk_disable()-based usecounting for osc_ck should be
* replaced with autoidle-based usecounting.
*/
+#ifdef CONFIG_COMMON_CLK
+int omap2_enable_osc_ck(struct clk_hw *clk)
+#else
static int omap2_enable_osc_ck(struct clk *clk)
+#endif
{
u32 pcc;
* clk_enable/clk_disable()-based usecounting for osc_ck should be
* replaced with autoidle-based usecounting.
*/
+#ifdef CONFIG_COMMON_CLK
+void omap2_disable_osc_ck(struct clk_hw *clk)
+#else
static void omap2_disable_osc_ck(struct clk *clk)
+#endif
{
u32 pcc;
__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
}
+#ifndef CONFIG_COMMON_CLK
const struct clkops clkops_oscck = {
.enable = omap2_enable_osc_ck,
.disable = omap2_disable_osc_ck,
};
+#endif
+#ifdef CONFIG_COMMON_CLK
+unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
+ unsigned long parent_rate)
+#else
unsigned long omap2_osc_clk_recalc(struct clk *clk)
+#endif
{
return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
}
return div;
}
+#ifdef CONFIG_COMMON_CLK
+unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
+ unsigned long parent_rate)
+{
+ return parent_rate / omap2xxx_get_sysclkdiv();
+}
+#else
unsigned long omap2xxx_sys_clk_recalc(struct clk *clk)
{
return clk->parent->rate / omap2xxx_get_sysclkdiv();
}
-
+#endif
*
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
*/
+#ifdef CONFIG_COMMON_CLK
+unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
+ unsigned long parent_rate)
+#else
unsigned long omap2_table_mpu_recalc(struct clk *clk)
+#endif
{
return curr_prcm_set->mpu_speed;
}
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
* just uses the ARM rates.
*/
+#ifdef CONFIG_COMMON_CLK
+long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+#else
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+#endif
{
const struct prcm_config *ptr;
long highest_rate;
}
/* Sets basic clocks based on the specified rate */
+#ifdef CONFIG_COMMON_CLK
+int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+#else
int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+#endif
{
u32 cur_rate, done_rate, bypass = 0, tmp;
const struct prcm_config *prcm;
* passes back the correct CM_IDLEST register address for I2CHS
* modules. No return value.
*/
+#ifdef CONFIG_COMMON_CLK
+static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk,
+#else
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+#endif
void __iomem **idlest_reg,
u8 *idlest_bit,
u8 *idlest_val)
}
/* 2430 I2CHS has non-standard IDLEST register */
+#ifdef CONFIG_COMMON_CLK
+const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = {
+ .find_idlest = omap2430_clk_i2chs_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+};
+#else
const struct clkops clkops_omap2430_i2chs_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap2430_clk_i2chs_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
+#endif
#include "cm.h"
#include "cm-regbits-24xx.h"
+struct clk_hw *dclk_hw;
/*
* Omap24xx specific clock functions
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
+#ifdef CONFIG_COMMON_CLK
+#include <linux/clk-provider.h>
+#include "clock.h"
+
+unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
+ unsigned long parent_rate);
+int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate);
+long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate);
+unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
+ unsigned long parent_rate);
+unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
+ unsigned long parent_rate);
+unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
+ unsigned long parent_rate);
+int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
+ unsigned long parent_rate);
+void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
+#else
unsigned long omap2_table_mpu_recalc(struct clk *clk);
int omap2_select_table_rate(struct clk *clk, unsigned long rate);
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
unsigned long omap2_osc_clk_recalc(struct clk *clk);
unsigned long omap2_dpllcore_recalc(struct clk *clk);
int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
+void omap2xxx_clkt_dpllcore_init(struct clk *clk);
+#endif
unsigned long omap2xxx_clk_get_core_rate(void);
u32 omap2xxx_get_apll_clkin(void);
u32 omap2xxx_get_sysclkdiv(void);
void omap2xxx_clk_prepare_for_reboot(void);
-void omap2xxx_clkt_dpllcore_init(struct clk *clk);
void omap2xxx_clkt_vps_check_bootloader_rates(void);
void omap2xxx_clkt_vps_late_init(void);
extern void __iomem *prcm_clksrc_ctrl;
+#ifdef CONFIG_COMMON_CLK
+extern struct clk_hw *dclk_hw;
+int omap2_enable_osc_ck(struct clk_hw *hw);
+void omap2_disable_osc_ck(struct clk_hw *hw);
+int omap2_clk_apll96_enable(struct clk_hw *hw);
+int omap2_clk_apll54_enable(struct clk_hw *hw);
+void omap2_clk_apll96_disable(struct clk_hw *hw);
+void omap2_clk_apll54_disable(struct clk_hw *hw);
+#else
extern const struct clkops clkops_omap2430_i2chs_wait;
extern const struct clkops clkops_oscck;
extern const struct clkops clkops_apll96;
extern const struct clkops clkops_apll54;
+#endif
#endif
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
+#ifdef CONFIG_COMMON_CLK
+#include <linux/clk-provider.h>
+#else
#include <linux/clk.h>
+#endif
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/gpio.h>
{
if (omap2_fclks_active())
return 0;
+#ifdef CONFIG_COMMON_CLK
+ if (__clk_is_enabled(osc_ck))
+#else
if (osc_ck->usecount > 1)
+#endif
return 0;
if (omap_dma_running())
return 0;
projects / openwrt / staging / blogic.git / commitdiff