Re-factor definition of some macros on ARM platforms

This patch moves the definition of some macros used only on
ARM platforms from common headers to platform specific headers.
It also forces all ARM standard platforms to have distinct
definitions (even if they are usually the same).
 1. `PLAT_ARM_TZC_BASE` and `PLAT_ARM_NSTIMER_FRAME_ID` have been
     moved from `css_def.h` to `platform_def.h`.
 2. `MHU_BASE` used in CSS platforms is moved from common css_def.h
    to platform specific header `platform_def.h` on Juno and
    renamed as `PLAT_ARM_MHU_BASE`.
 3. To cater for different sizes of BL images, new macros like
    `PLAT_ARM_MAX_BL31_SIZE` have been created for each BL image. All
    ARM platforms need to define them for each image.

Change-Id: I9255448bddfad734b387922aa9e68d2117338c3f

diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index b2db6160d319c29aa870b07447f218de3c416335..4c8435607b1a60081db94caa3394afb4772e205c 100644 (file)
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -239,44 +239,31 @@
 #define BL1_RO_LIMIT                   (PLAT_ARM_TRUSTED_ROM_BASE      \
                                         + PLAT_ARM_TRUSTED_ROM_SIZE)
 /*
- * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
- * the current BL1 RW debug size plus a little space for growth.
+ * Put BL1 RW at the top of the Trusted SRAM.
  */
-#if TRUSTED_BOARD_BOOT
 #define BL1_RW_BASE                    (ARM_BL_RAM_BASE +              \
                                                ARM_BL_RAM_SIZE -       \
-                                               0x9000)
-#else
-#define BL1_RW_BASE                    (ARM_BL_RAM_BASE +              \
-                                               ARM_BL_RAM_SIZE -       \
-                                               0x6000)
-#endif
+                                               PLAT_ARM_MAX_BL1_RW_SIZE)
 #define BL1_RW_LIMIT                   (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 
 /*******************************************************************************
  * BL2 specific defines.
  ******************************************************************************/
 /*
- * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug
- * size plus a little space for growth.
+ * Put BL2 just below BL31.
  */
-#if TRUSTED_BOARD_BOOT
-#define BL2_BASE                       (BL31_BASE - 0x1D000)
-#else
-#define BL2_BASE                       (BL31_BASE - 0xC000)
-#endif
+#define BL2_BASE                       (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
 #define BL2_LIMIT                      BL31_BASE
 
 /*******************************************************************************
  * BL31 specific defines.
  ******************************************************************************/
 /*
- * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
- * current BL31 debug size plus a little space for growth.
+ * Put BL31 at the top of the Trusted SRAM.
  */
 #define BL31_BASE                      (ARM_BL_RAM_BASE +              \
                                                ARM_BL_RAM_SIZE -       \
-                                               0x1D000)
+                                               PLAT_ARM_MAX_BL31_SIZE)
 #define BL31_PROGBITS_LIMIT            BL1_RW_BASE
 #define BL31_LIMIT                     (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 

diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index c900278b5c3fda32ff1f754608d5dd4de18c436d..43d1c54f72a1df08bf5f9b4ee27d4fd57eb4e18b 100644 (file)
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -45,7 +45,6 @@
 /* Following covers CSS Peripherals excluding NSROM and NSRAM  */
 #define CSS_DEVICE_BASE                        0x20000000
 #define CSS_DEVICE_SIZE                        0x0e000000
-#define MHU_BASE                       0x2b1f0000
 
 #define NSRAM_BASE                     0x2e000000
 #define NSRAM_SIZE                     0x00008000
@@ -125,10 +124,6 @@
 
 /* TZC related constants */
 #define PLAT_ARM_TZC_FILTERS           REG_ATTR_FILTER_BIT_ALL
-#define PLAT_ARM_TZC_BASE              0x2a4a0000
-
-/* System timer related constants */
-#define PLAT_ARM_NSTIMER_FRAME_ID      1
 
 /* Trusted mailbox base address common to all CSS */
 #define PLAT_ARM_TRUSTED_MAILBOX_BASE  ARM_TRUSTED_SRAM_BASE

diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 0d671dc03e78d93f414c5664d59d68ec599b0aef..9c82cbfa2a719fb48387557e1f9ca63e4689978d 100644 (file)
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -144,4 +144,30 @@
 
 #define PLAT_ARM_G0_IRQS               ARM_G0_IRQS
 
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL1_RW_SIZE      0x9000
+#else
+# define PLAT_ARM_MAX_BL1_RW_SIZE      0x6000
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL2_SIZE         0x1D000
+#else
+# define PLAT_ARM_MAX_BL2_SIZE         0xC000
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
+ * little space for growth.
+ */
+#define PLAT_ARM_MAX_BL31_SIZE         0x1D000
+
 #endif /* __PLATFORM_DEF_H__ */

diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 924eb0ab7c6be9e6e8d836f9d13f12f5a89a560a..99de7617b8ebc94ca0cb9200b757e1da0b4c7e18 100644 (file)
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -76,7 +76,11 @@
 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX      4
 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX      3
 
+/* System timer related constants */
+#define PLAT_ARM_NSTIMER_FRAME_ID              1
+
 /* TZC related constants */
+#define PLAT_ARM_TZC_BASE              0x2a4a0000
 #define PLAT_ARM_TZC_NS_DEV_ACCESS     (                               \
                TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400)     |       \
                TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE)       |       \
@@ -99,6 +103,9 @@
 #define PLAT_ARM_GICH_BASE             0x2c04f000
 #define PLAT_ARM_GICV_BASE             0x2c06f000
 
+/* MHU related constants */
+#define PLAT_CSS_MHU_BASE              0x2b1f0000
+
 /*
  * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
  * terminology. On a GICv2 system or mode, the lists will be merged and treated
@@ -124,5 +131,30 @@
 /* CSS SoC NIC-400 Global Programmers View (GPV) */
 #define PLAT_SOC_CSS_NIC400_BASE       0x2a000000
 
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL1_RW_SIZE      0x9000
+#else
+# define PLAT_ARM_MAX_BL1_RW_SIZE      0x6000
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL2_SIZE         0x1D000
+#else
+# define PLAT_ARM_MAX_BL2_SIZE         0xC000
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
+ * little space for growth.
+ */
+#define PLAT_ARM_MAX_BL31_SIZE         0x1D000
 
 #endif /* __PLATFORM_DEF_H__ */

diff --git a/plat/arm/css/common/css_mhu.c b/plat/arm/css/common/css_mhu.c
index b1714e222c150a01083b16ca718ea6f086dfce68..265d6c25c907d636c121a4383f37fcf83fc49dba 100644 (file)
--- a/plat/arm/css/common/css_mhu.c
+++ b/plat/arm/css/common/css_mhu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #include <bakery_lock.h>
 #include <css_def.h>
 #include <mmio.h>
+#include <platform_def.h>
 #include <plat_arm.h>
 #include "css_mhu.h"
 
@@ -66,24 +67,26 @@ void mhu_secure_message_start(unsigned int slot_id)
        arm_lock_get();
 
        /* Make sure any previous command has finished */
-       while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id))
+       while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) &
+                                                       (1 << slot_id))
                ;
 }
 
 void mhu_secure_message_send(unsigned int slot_id)
 {
        assert(slot_id <= MHU_MAX_SLOT_ID);
-       assert(!(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id)));
+       assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) &
+                                                       (1 << slot_id)));
 
        /* Send command to SCP */
-       mmio_write_32(MHU_BASE + CPU_INTR_S_SET, 1 << slot_id);
+       mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id);
 }
 
 uint32_t mhu_secure_message_wait(void)
 {
        /* Wait for response from SCP */
        uint32_t response;
-       while (!(response = mmio_read_32(MHU_BASE + SCP_INTR_S_STAT)))
+       while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT)))
                ;
 
        return response;
@@ -97,7 +100,7 @@ void mhu_secure_message_end(unsigned int slot_id)
         * Clear any response we got by writing one in the relevant slot bit to
         * the CLEAR register
         */
-       mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id);
+       mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id);
 
        arm_lock_release();
 }
@@ -111,7 +114,7 @@ void mhu_secure_init(void)
         * as a stale or garbage value would make us think it's a message we've
         * already sent.
         */
-       assert(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) == 0);
+       assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0);
 }
 
 void plat_arm_pwrc_setup(void)