Merge tag 'v3.9-rc5' into drm-intel-next-queued

Backmerge Linux 3.9-rc5 since I want to merge a few dp clock cleanups
for -next, but they will conflict all over the place with

commit 9d1a455b0ca1c2c956b4d9ab212864a8695270f1
Author: Takashi Iwai <tiwai@suse.de>
Date:   Mon Mar 18 11:25:36 2013 +0100

    drm/i915: Use the fixed pixel clock for eDP in intel_dp_set_m_n()

from -fixes.

Conflicts:
	drivers/gpu/drm/i915/intel_dp.c: Simply adjacent lines changed.
	drivers/gpu/drm/i915/intel_panel.c: A field rename in -next
	conflicts with a bugfix in -fixes. Take the version from
	-fixes and apply the rename.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --cc drivers/gpu/drm/i915/i915_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.c
index 1c53438cea47c43e27ddbe62f3c1482c3fba10bd,e9b57893db2b1ebba1348a71e37c845f98c3286b..a5b8aa9b319fef351f4ec4bea0746a3b6cb07595
--- 1/drivers/gpu/drm/i915/i915_drv.c
--- 2/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@@ -121,8 -121,15 +121,13 @@@ MODULE_PARM_DESC(i915_enable_ppgtt
  unsigned int i915_preliminary_hw_support __read_mostly = 0;
  module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
  MODULE_PARM_DESC(preliminary_hw_support,
 -              "Enable preliminary hardware support. "
 -              "Enable Haswell and ValleyView Support. "
 -              "(default: false)");
 +              "Enable preliminary hardware support. (default: false)");
  
+ int i915_disable_power_well __read_mostly = 0;
+ module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
+ MODULE_PARM_DESC(disable_power_well,
+                "Disable the power well when possible (default: false)");
+ 
  static struct drm_driver driver;
  extern int intel_agp_enabled;
  

diff --cc drivers/gpu/drm/i915/i915_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 983083976dd819038474ee643414f9c12f29a8b7,3b11ab0fbc960ab1ff58fd842a2d51ff10ca15db..a96b6a3118db6342fef2aa3abf4d1e8497ef4197
--- 1/drivers/gpu/drm/i915/i915_gem_execbuffer.c
--- 2/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@@ -730,9 -732,11 +730,11 @@@ validate_exec_list(struct drm_i915_gem_
                   int count)
  {
        int i;
+       int relocs_total = 0;
+       int relocs_max = INT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
  
        for (i = 0; i < count; i++) {
 -              char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
 +              char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
                int length; /* limited by fault_in_pages_readable() */
  
                if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)

diff --cc drivers/gpu/drm/i915/intel_display.c
index 59d52b729a6829bbbfd18d326e048489ded20ba2,b20d50192fcc8f3dda5c7efbe098d1a560e95f71..181bd0e3228c607de76266ecd42b758444b5eebb
--- 1/drivers/gpu/drm/i915/intel_display.c
--- 2/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -5810,15 -5842,10 +5815,10 @@@ static int intel_crtc_mode_set(struct d
        int pipe = intel_crtc->pipe;
        int ret;
  
-       if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
-               intel_crtc->cpu_transcoder = TRANSCODER_EDP;
-       else
-               intel_crtc->cpu_transcoder = pipe;
- 
        drm_vblank_pre_modeset(dev, pipe);
  
 -      ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
 -                                            x, y, fb);
 +      ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
 +
        drm_vblank_post_modeset(dev, pipe);
  
        if (ret != 0)

diff --cc drivers/gpu/drm/i915/intel_dp.c
index 64c8d3ed8d0f6f43614334fe776d235cc94b5a96,d7d4afe013417f489934dbab8e5bafbf48614aa9..db592e80f22cc9c5a06b380e8893267e3f2db684
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -801,10 -850,10 +811,10 @@@ intel_dp_set_m_n(struct drm_crtc *crtc
         * the number of bytes_per_pixel post-LUT, which we always
         * set up for 8-bits of R/G/B, or 3 bytes total.
         */
 -      intel_link_compute_m_n(intel_crtc->bpp, lane_count,
 +      intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane_count,
-                              mode->clock, adjusted_mode->clock, &m_n);
+                              target_clock, adjusted_mode->clock, &m_n);
  
 -      if (IS_HASWELL(dev)) {
 +      if (HAS_DDI(dev)) {
                I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
                           TU_SIZE(m_n.tu) | m_n.gmch_m);
                I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);

diff --cc drivers/gpu/drm/i915/intel_panel.c
index 0e7e873b06f5158db145f5a51c93d60e43f7f9a8,bee8cb6108a7d44883286ef4b35bb6d7f8713a0f..7874cecc286355311c55c6a2b49dad7216015cbf
--- 1/drivers/gpu/drm/i915/intel_panel.c
--- 2/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@@ -321,16 -318,9 +321,13 @@@ void intel_panel_enable_backlight(struc
  {
        struct drm_i915_private *dev_priv = dev->dev_private;
  
 -      if (dev_priv->backlight_level == 0)
 -              dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
 +      if (dev_priv->backlight.level == 0) {
 +              dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
 +              if (dev_priv->backlight.device)
 +                      dev_priv->backlight.device->props.brightness =
 +                              dev_priv->backlight.level;
 +      }
  
-       dev_priv->backlight.enabled = true;
-       intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
- 
        if (INTEL_INFO(dev)->gen >= 4) {
                uint32_t reg, tmp;
  
@@@ -366,12 -356,12 +363,12 @@@
        }
  
  set_level:
-       /* Check the current backlight level and try to set again if it's zero.
-        * On some machines, BLC_PWM_CPU_CTL is cleared to zero automatically
-        * when BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1 are written.
+       /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
+        * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
+        * registers are set.
         */
-       if (!intel_panel_get_backlight(dev))
-               intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
 -      dev_priv->backlight_enabled = true;
 -      intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
++      dev_priv->backlight.enabled = true;
++      intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
  }
  
  static void intel_panel_init_backlight(struct drm_device *dev)

diff --cc drivers/gpu/drm/i915/intel_pm.c
index 917db69276d69efd6386fe673144ef6a53659e8e,adca00783e61b304723d3d05197b53f47b6b33db..13a0666a53b42e9645179a30a3f3a2a69df09809
--- 1/drivers/gpu/drm/i915/intel_pm.c
--- 2/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@@ -4090,9 -4076,12 +4090,12 @@@ void intel_set_power_well(struct drm_de
        bool is_enabled, enable_requested;
        uint32_t tmp;
  
 -      if (!IS_HASWELL(dev))
 +      if (!HAS_POWER_WELL(dev))
                return;
  
+       if (!i915_disable_power_well && !enable)
+               return;
+ 
        tmp = I915_READ(HSW_PWR_WELL_DRIVER);
        is_enabled = tmp & HSW_PWR_WELL_STATE;
        enable_requested = tmp & HSW_PWR_WELL_ENABLE;