KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
endif
-LINUX_VERSION-5.4 = .108
+LINUX_VERSION-5.4 = .109
LINUX_VERSION-5.10 = .26
-LINUX_KERNEL_HASH-5.4.108 = f212ac07c21bd33e6898fdbb2ddba2a454f74578bbe7bef8fe4dbbbc0ec52172
+LINUX_KERNEL_HASH-5.4.109 = ac6af4562717d030266fcddb0a3c44598610ca8c9c3a654725f58b9cbd61b7ee
LINUX_KERNEL_HASH-5.10.26 = fc532833f1ac167f363f1b9de85db39d2d635ab516f66dc381bdd70804601482
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
--- a/drivers/net/dsa/b53/b53_common.c
+++ b/drivers/net/dsa/b53/b53_common.c
-@@ -2278,6 +2278,22 @@ static const struct b53_chip_data b53_sw
+@@ -2271,6 +2271,22 @@ static const struct b53_chip_data b53_sw
.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
},
offset = CORE_STS_OVERRIDE_IMP;
else
offset = CORE_STS_OVERRIDE_IMP2;
-@@ -541,7 +542,8 @@ static void bcm_sf2_sw_mac_config(struct
+@@ -543,7 +544,8 @@ static void bcm_sf2_sw_mac_config(struct
if (port == core_readl(priv, CORE_IMP0_PRT_ID))
return;
offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
else
offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
-@@ -983,6 +985,30 @@ struct bcm_sf2_of_data {
+@@ -985,6 +987,30 @@ struct bcm_sf2_of_data {
unsigned int num_cfp_rules;
};
/* Register offsets for the SWITCH_REG_* block */
static const u16 bcm_sf2_7445_reg_offsets[] = {
[REG_SWITCH_CNTRL] = 0x00,
-@@ -1031,6 +1057,9 @@ static const struct bcm_sf2_of_data bcm_
+@@ -1033,6 +1059,9 @@ static const struct bcm_sf2_of_data bcm_
};
static const struct of_device_id bcm_sf2_of_match[] = {
static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
{
intrl2_0_mask_set(priv, 0xffffffff);
-@@ -732,6 +770,8 @@ static int bcm_sf2_sw_resume(struct dsa_
+@@ -734,6 +772,8 @@ static int bcm_sf2_sw_resume(struct dsa_
return ret;
}
ret = bcm_sf2_cfp_resume(ds);
if (ret)
return ret;
-@@ -994,6 +1034,7 @@ struct bcm_sf2_of_data {
+@@ -996,6 +1036,7 @@ struct bcm_sf2_of_data {
const u16 *reg_offsets;
unsigned int core_reg_align;
unsigned int num_cfp_rules;
};
static const u16 bcm_sf2_4908_reg_offsets[] = {
-@@ -1018,6 +1059,7 @@ static const struct bcm_sf2_of_data bcm_
+@@ -1020,6 +1061,7 @@ static const struct bcm_sf2_of_data bcm_
.core_reg_align = 0,
.reg_offsets = bcm_sf2_4908_reg_offsets,
.num_cfp_rules = 0, /* FIXME */
};
/* Register offsets for the SWITCH_REG_* block */
-@@ -1128,6 +1170,7 @@ static int bcm_sf2_sw_probe(struct platf
+@@ -1130,6 +1172,7 @@ static int bcm_sf2_sw_probe(struct platf
priv->reg_offsets = data->reg_offsets;
priv->core_reg_align = data->core_reg_align;
priv->num_cfp_rules = data->num_cfp_rules;
/* Auto-detection using standard registers will not work, so
* provide an indication of what kind of device we are for
-@@ -1182,6 +1225,8 @@ static int bcm_sf2_sw_probe(struct platf
+@@ -1184,6 +1227,8 @@ static int bcm_sf2_sw_probe(struct platf
return ret;
}
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1058,7 +1058,7 @@ static const struct bcm_sf2_of_data bcm_
+@@ -1060,7 +1060,7 @@ static const struct bcm_sf2_of_data bcm_
.type = BCM4908_DEVICE_ID,
.core_reg_align = 0,
.reg_offsets = bcm_sf2_4908_reg_offsets,
static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
{
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
-@@ -586,6 +611,7 @@ static void bcm_sf2_sw_mac_config(struct
+@@ -588,6 +613,7 @@ static void bcm_sf2_sw_mac_config(struct
{
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
u32 id_mode_dis = 0, port_mode;
u32 reg, offset;
if (port == core_readl(priv, CORE_IMP0_PRT_ID))
-@@ -615,10 +641,12 @@ static void bcm_sf2_sw_mac_config(struct
+@@ -617,10 +643,12 @@ static void bcm_sf2_sw_mac_config(struct
goto force_link;
}
reg &= ~ID_MODE_DIS;
reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
-@@ -633,7 +661,7 @@ static void bcm_sf2_sw_mac_config(struct
+@@ -635,7 +663,7 @@ static void bcm_sf2_sw_mac_config(struct
reg |= RX_PAUSE_EN;
}
force_link:
/* Force link settings detected from the PHY */
-@@ -659,6 +687,7 @@ static void bcm_sf2_sw_mac_link_set(stru
+@@ -661,6 +689,7 @@ static void bcm_sf2_sw_mac_link_set(stru
phy_interface_t interface, bool link)
{
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
u32 reg;
if (!phy_interface_mode_is_rgmii(interface) &&
-@@ -666,13 +695,15 @@ static void bcm_sf2_sw_mac_link_set(stru
+@@ -668,13 +697,15 @@ static void bcm_sf2_sw_mac_link_set(stru
interface != PHY_INTERFACE_MODE_REVMII)
return;
break;
default:
switch (port) {
-@@ -1077,9 +1082,7 @@ static const u16 bcm_sf2_4908_reg_offset
+@@ -1079,9 +1084,7 @@ static const u16 bcm_sf2_4908_reg_offset
[REG_PHY_REVISION] = 0x14,
[REG_SPHY_CNTRL] = 0x24,
[REG_CROSSBAR] = 0xc8,
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1319,10 +1319,14 @@ static int bcm_sf2_sw_probe(struct platf
+@@ -1321,10 +1321,14 @@ static int bcm_sf2_sw_probe(struct platf
rev = reg_readl(priv, REG_PHY_REVISION);
priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1333,6 +1333,12 @@ static int bcm_sf2_sw_probe(struct platf
+@@ -1335,6 +1335,12 @@ static int bcm_sf2_sw_probe(struct platf
priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
priv->irq0, priv->irq1);
return -ENOMEM;
@@ -818,6 +846,7 @@ copy_entries_to_user(unsigned int total_
- const struct xt_table_info *private = xt_table_get_private_protected(table);
+ const struct xt_table_info *private = table->private;
int ret = 0;
const void *loc_cpu_entry;
+ u8 flags;
/* Initialization */
+ WARN_ON(!(table->valid_hooks & (1 << hook)));
+ local_bh_disable();
-+ private = rcu_access_pointer(table->private);
++ private = READ_ONCE(table->private); /* Address dependency. */
+ cpu = smp_processor_id();
+ table_base = private->entries;
+
- WARN_ON(!(table->valid_hooks & (1 << hook)));
- local_bh_disable();
addend = xt_write_recseq_begin();
-- private = rcu_access_pointer(table->private);
+- private = READ_ONCE(table->private); /* Address dependency. */
- cpu = smp_processor_id();
- table_base = private->entries;
jumpstack = (struct ipt_entry **)private->jumpstack[cpu];
select PM_OPP
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -138,6 +138,11 @@ static const struct of_device_id blackli
+@@ -140,6 +140,11 @@ static const struct of_device_id blackli
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -260,7 +260,7 @@
+@@ -261,7 +261,7 @@
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1012a-dcfg",
"syscon";
big-endian;
};
-@@ -317,13 +317,23 @@
+@@ -318,13 +318,23 @@
#thermal-sensor-cells = <1>;
};
status = "disabled";
};
-@@ -395,6 +405,20 @@
+@@ -396,6 +406,20 @@
big-endian;
};
sai1: sai@2b50000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
-@@ -499,6 +523,46 @@
+@@ -500,6 +524,46 @@
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
&duart0 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -277,7 +277,7 @@
+@@ -278,7 +278,7 @@
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1043a-dcfg", "syscon";
big-endian;
};
-@@ -411,7 +411,7 @@
+@@ -412,7 +412,7 @@
};
i2c0: i2c@2180000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
-@@ -421,6 +421,7 @@
+@@ -422,6 +422,7 @@
dmas = <&edma0 1 39>,
<&edma0 1 38>;
dma-names = "tx", "rx";
status = "disabled";
};
-@@ -525,6 +526,72 @@
+@@ -526,6 +527,72 @@
#interrupt-cells = <2>;
};
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
-@@ -579,6 +646,16 @@
+@@ -580,6 +647,16 @@
status = "disabled";
};
wdog0: wdog@2ad0000 {
compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -611,7 +688,10 @@
+@@ -612,7 +689,10 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
usb1: usb3@3000000 {
-@@ -621,7 +701,10 @@
+@@ -622,7 +702,10 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
usb2: usb3@3100000 {
-@@ -631,7 +714,10 @@
+@@ -632,7 +715,10 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
sata: sata@3200000 {
-@@ -670,9 +756,9 @@
+@@ -671,9 +757,9 @@
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
-@@ -696,9 +782,9 @@
+@@ -697,9 +783,9 @@
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
-@@ -722,9 +808,9 @@
+@@ -723,9 +809,9 @@
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
compatible = "spansion,m25p80";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -376,7 +376,7 @@
+@@ -377,7 +377,7 @@
};
i2c0: i2c@2180000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
-@@ -385,6 +385,7 @@
+@@ -386,6 +386,7 @@
dmas = <&edma0 1 39>,
<&edma0 1 38>;
dma-names = "tx", "rx";
status = "disabled";
};
-@@ -409,12 +410,13 @@
+@@ -410,12 +411,13 @@
};
i2c3: i2c@21b0000 {
status = "disabled";
};
-@@ -544,6 +546,15 @@
+@@ -545,6 +547,15 @@
status = "disabled";
};
wdog0: watchdog@2ad0000 {
compatible = "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -576,6 +587,8 @@
+@@ -577,6 +588,8 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb1: usb@3000000 {
-@@ -586,6 +599,8 @@
+@@ -587,6 +600,8 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb2: usb@3100000 {
-@@ -596,6 +611,8 @@
+@@ -597,6 +612,8 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
sata: sata@3200000 {
-@@ -637,6 +654,11 @@
+@@ -638,6 +655,11 @@
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -807,6 +807,7 @@
+@@ -808,6 +808,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
-@@ -833,6 +834,7 @@
+@@ -834,6 +835,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
-@@ -859,6 +861,7 @@
+@@ -860,6 +862,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -715,6 +715,7 @@
+@@ -716,6 +716,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
-@@ -751,6 +752,7 @@
+@@ -752,6 +753,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
-@@ -787,6 +789,7 @@
+@@ -788,6 +790,7 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
-@@ -771,7 +772,6 @@
+@@ -772,7 +773,6 @@
reg-names = "ahci", "sata-ecc";
interrupts = <0 69 0x4>;
clocks = <&clockgen 4 0>;
};
msi1: msi-controller1@1571000 {
-@@ -806,7 +806,6 @@
+@@ -807,7 +807,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
-@@ -833,7 +832,6 @@
+@@ -834,7 +833,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
iommu-map = <0 &smmu 0 1>; /* update by bootloader */
num-viewport = <6>;
bus-range = <0x0 0xff>;
-@@ -860,7 +858,6 @@
+@@ -861,7 +859,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -726,43 +726,51 @@
+@@ -727,43 +727,51 @@
<&clockgen 4 0>;
};
sata: sata@3200000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -624,40 +624,48 @@
+@@ -625,40 +625,48 @@
<&clockgen 4 1>;
};
soc {
compatible = "simple-bus";
-@@ -572,3 +543,9 @@
+@@ -573,3 +544,9 @@
};
};
};
timer {
compatible = "arm,armv8-timer";
-@@ -915,3 +884,29 @@
+@@ -916,3 +885,29 @@
#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"
timer {
compatible = "arm,armv8-timer";
-@@ -882,3 +851,25 @@
+@@ -883,3 +852,25 @@
#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -695,7 +695,7 @@
+@@ -696,7 +696,7 @@
<&clockgen 4 0>;
};
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
-@@ -740,15 +740,15 @@
+@@ -741,15 +741,15 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
configure-gfladj;
};
msi1: msi-controller1@1571000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -593,7 +593,7 @@
+@@ -594,7 +594,7 @@
<&clockgen 4 1>;
};
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
-@@ -635,15 +635,15 @@
+@@ -636,15 +636,15 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
};
#size-cells = <0>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -529,11 +529,6 @@
+@@ -530,11 +530,6 @@
clock-names = "pfe";
status = "okay";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -442,6 +442,7 @@
+@@ -443,6 +443,7 @@
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
sata: sata@3200000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -712,6 +712,7 @@
+@@ -713,6 +713,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
configure-gfladj;
};
-@@ -725,6 +726,7 @@
+@@ -726,6 +727,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
configure-gfladj;
};
-@@ -738,6 +740,7 @@
+@@ -739,6 +741,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -610,6 +610,7 @@
+@@ -611,6 +611,7 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
};
usb1: usb@3000000 {
-@@ -622,6 +623,7 @@
+@@ -623,6 +624,7 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
};
usb2: usb@3100000 {
-@@ -634,6 +636,7 @@
+@@ -635,6 +637,7 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
*
*/
-@@ -513,7 +514,7 @@
+@@ -514,7 +515,7 @@
};
};
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -679,11 +679,6 @@
+@@ -680,11 +680,6 @@
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
};
};
cpus {
-@@ -289,15 +290,21 @@
+@@ -290,15 +291,21 @@
#thermal-sensor-cells = <1>;
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
#address-cells = <1>;
-@@ -496,12 +503,6 @@
+@@ -497,12 +504,6 @@
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
cpus {
-@@ -660,16 +661,6 @@
+@@ -661,16 +662,6 @@
status = "disabled";
};
wdog0: wdog@2ad0000 {
compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -874,6 +865,19 @@
+@@ -875,6 +866,19 @@
big-endian;
};
};
cpus {
-@@ -560,15 +561,6 @@
+@@ -561,15 +562,6 @@
status = "disabled";
};
wdog0: watchdog@2ad0000 {
compatible = "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -810,6 +802,20 @@
+@@ -811,6 +803,20 @@
queue-sizes = <64 64>;
big-endian;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -443,7 +443,7 @@
+@@ -444,7 +444,7 @@
};
usb0: usb3@2f00000 {
dr_mode = "host";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -694,7 +694,7 @@
+@@ -695,7 +695,7 @@
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
usb0: usb3@2f00000 {
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <0 60 0x4>;
dr_mode = "host";
-@@ -708,7 +708,7 @@
+@@ -709,7 +709,7 @@
};
usb1: usb3@3000000 {
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <0 61 0x4>;
dr_mode = "host";
-@@ -722,7 +722,7 @@
+@@ -723,7 +723,7 @@
};
usb2: usb3@3100000 {
dr_mode = "host";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -593,7 +593,7 @@
+@@ -594,7 +594,7 @@
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
usb0: usb@2f00000 {
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
-@@ -606,7 +606,7 @@
+@@ -607,7 +607,7 @@
};
usb1: usb@3000000 {
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
-@@ -619,7 +619,7 @@
+@@ -620,7 +620,7 @@
};
usb2: usb@3100000 {
<&edma0 1 44>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -404,8 +404,9 @@
+@@ -405,8 +405,9 @@
reg = <0x0 0x2b50000 0x0 0x10000>;
interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>,
dma-names = "tx", "rx";
dmas = <&edma0 1 47>,
<&edma0 1 46>;
-@@ -418,8 +419,9 @@
+@@ -419,8 +420,9 @@
reg = <0x0 0x2b60000 0x0 0x10000>;
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>,
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -453,6 +453,7 @@
+@@ -454,6 +454,7 @@
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
sata: sata@3200000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -705,6 +705,7 @@
+@@ -706,6 +706,7 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
configure-gfladj;
};
usb1: usb3@3000000 {
-@@ -719,6 +720,7 @@
+@@ -720,6 +721,7 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
configure-gfladj;
};
usb2: usb3@3100000 {
-@@ -733,6 +735,7 @@
+@@ -734,6 +736,7 @@
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
configure-gfladj;
sata: sata@3200000 {
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -603,6 +603,7 @@
+@@ -604,6 +604,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,host-vbus-glitches;
};
usb1: usb@3000000 {
-@@ -616,6 +617,7 @@
+@@ -617,6 +618,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,host-vbus-glitches;
};
usb2: usb@3100000 {
-@@ -629,6 +631,7 @@
+@@ -630,6 +632,7 @@
usb3-lpm-capable;
snps,dis-u1u2-when-u3-quirk;
snps,host-vbus-glitches;
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -385,7 +385,7 @@
+@@ -386,7 +386,7 @@
};
qspi: spi@1550000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
-@@ -394,7 +394,6 @@
+@@ -395,7 +395,6 @@
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 0>, <&clockgen 4 0>;
spi-tx-bus-width = <1>;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -391,7 +391,7 @@
+@@ -392,7 +392,7 @@
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -808,7 +808,7 @@
+@@ -809,7 +809,7 @@
rcpm: rcpm@1ee208c {
compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -706,6 +706,7 @@
+@@ -707,6 +707,7 @@
snps,host-vbus-glitches;
configure-gfladj;
dma-coherent;
};
usb1: usb3@3000000 {
-@@ -721,6 +722,7 @@
+@@ -722,6 +723,7 @@
snps,host-vbus-glitches;
configure-gfladj;
dma-coherent;
};
usb2: usb3@3100000 {
-@@ -736,6 +738,7 @@
+@@ -737,6 +739,7 @@
snps,host-vbus-glitches;
configure-gfladj;
dma-coherent;
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -918,8 +918,4 @@
+@@ -919,8 +919,4 @@
thermal-zone4 {
status = "okay";
};
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -785,16 +785,23 @@ static inline struct flexcan_priv *rx_of
+@@ -791,16 +791,23 @@ static inline struct flexcan_priv *rx_of
return container_of(offload, struct flexcan_priv, offload);
}
mb = flexcan_get_mb(priv, n);
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
-@@ -808,7 +815,7 @@ static unsigned int flexcan_mailbox_read
+@@ -814,7 +821,7 @@ static unsigned int flexcan_mailbox_read
code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
(code != FLEXCAN_MB_CODE_RX_OVERRUN))
if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
/* This MB was overrun, we lost data */
-@@ -818,11 +825,17 @@ static unsigned int flexcan_mailbox_read
+@@ -824,11 +831,17 @@ static unsigned int flexcan_mailbox_read
} else {
reg_iflag1 = priv->read(®s->iflag1);
if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
/* increase timstamp to full 32 bit */
*timestamp = reg_ctrl << 16;
-@@ -841,7 +854,7 @@ static unsigned int flexcan_mailbox_read
+@@ -847,7 +860,7 @@ static unsigned int flexcan_mailbox_read
*(__be32 *)(cf->data + i) = data;
}
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
/* Clear IRQ */
if (n < 32)
-@@ -858,7 +871,7 @@ static unsigned int flexcan_mailbox_read
+@@ -864,7 +877,7 @@ static unsigned int flexcan_mailbox_read
*/
priv->read(®s->timer);
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -1579,7 +1579,6 @@ static int flexcan_probe(struct platform
+@@ -1585,7 +1585,6 @@ static int flexcan_probe(struct platform
struct net_device *dev;
struct flexcan_priv *priv;
struct regulator *reg_xceiver;
struct clk *clk_ipg = NULL, *clk_per = NULL;
struct flexcan_regs __iomem *regs;
int err, irq;
-@@ -1614,12 +1613,11 @@ static int flexcan_probe(struct platform
+@@ -1620,12 +1619,11 @@ static int flexcan_probe(struct platform
clock_freq = clk_get_rate(clk_per);
}
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -745,8 +745,6 @@ static void flexcan_irq_state(struct net
+@@ -751,8 +751,6 @@ static void flexcan_irq_state(struct net
u32 timestamp;
int err;
flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
-@@ -766,6 +764,8 @@ static void flexcan_irq_state(struct net
+@@ -772,6 +770,8 @@ static void flexcan_irq_state(struct net
if (likely(new_state == priv->can.state))
return;
#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
-@@ -881,7 +881,7 @@ static inline u64 flexcan_read_reg_iflag
+@@ -887,7 +887,7 @@ static inline u64 flexcan_read_reg_iflag
u32 iflag1, iflag2;
iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default &
iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default;
return (u64)iflag2 << 32 | iflag1;
-@@ -931,7 +931,7 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -937,7 +937,7 @@ static irqreturn_t flexcan_irq(int irq,
reg_iflag2 = priv->read(®s->iflag2);
/* transmission complete interrupt */
u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
handled = IRQ_HANDLED;
-@@ -943,7 +943,7 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -949,7 +949,7 @@ static irqreturn_t flexcan_irq(int irq,
/* after sending a RTR frame MB is in RX mode */
priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&priv->tx_mb->can_ctrl);
netif_wake_queue(dev);
}
-@@ -1323,7 +1323,7 @@ static int flexcan_open(struct net_devic
+@@ -1329,7 +1329,7 @@ static int flexcan_open(struct net_devic
priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
priv->reg_imask1_default = 0;
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -899,13 +899,13 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -905,13 +905,13 @@ static irqreturn_t flexcan_irq(int irq,
/* reception interrupt */
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
struct clk *clk_ipg;
struct clk *clk_per;
-@@ -880,9 +880,9 @@ static inline u64 flexcan_read_reg_iflag
+@@ -886,9 +886,9 @@ static inline u64 flexcan_read_reg_iflag
struct flexcan_regs __iomem *regs = priv->regs;
u32 iflag1, iflag2;
return (u64)iflag2 << 32 | iflag1;
}
-@@ -1227,8 +1227,8 @@ static int flexcan_chip_start(struct net
+@@ -1233,8 +1233,8 @@ static int flexcan_chip_start(struct net
/* enable interrupts atomically */
disable_irq(dev->irq);
priv->write(priv->reg_ctrl_default, ®s->ctrl);
enable_irq(dev->irq);
/* print chip status */
-@@ -1322,8 +1322,8 @@ static int flexcan_open(struct net_devic
+@@ -1328,8 +1328,8 @@ static int flexcan_open(struct net_devic
priv->tx_mb_idx = priv->mb_count - 1;
priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
priv->offload.mailbox_read = flexcan_mailbox_read;
-@@ -1335,12 +1335,12 @@ static int flexcan_open(struct net_devic
+@@ -1341,12 +1341,12 @@ static int flexcan_open(struct net_devic
imask = GENMASK_ULL(priv->offload.mb_last,
priv->offload.mb_first);
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -880,8 +880,7 @@ static inline u64 flexcan_read_reg_iflag
+@@ -886,8 +886,7 @@ static inline u64 flexcan_read_reg_iflag
struct flexcan_regs __iomem *regs = priv->regs;
u32 iflag1, iflag2;
iflag1 = priv->read(®s->iflag1) & priv->rx_mask1;
return (u64)iflag2 << 32 | iflag1;
-@@ -1228,7 +1227,7 @@ static int flexcan_chip_start(struct net
+@@ -1234,7 +1233,7 @@ static int flexcan_chip_start(struct net
disable_irq(dev->irq);
priv->write(priv->reg_ctrl_default, ®s->ctrl);
priv->write(priv->rx_mask1, ®s->imask1);
enable_irq(dev->irq);
/* print chip status */
-@@ -1322,9 +1321,6 @@ static int flexcan_open(struct net_devic
+@@ -1328,9 +1327,6 @@ static int flexcan_open(struct net_devic
priv->tx_mb_idx = priv->mb_count - 1;
priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
priv->offload.mailbox_read = flexcan_mailbox_read;
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
-@@ -1335,12 +1331,12 @@ static int flexcan_open(struct net_devic
+@@ -1341,12 +1337,12 @@ static int flexcan_open(struct net_devic
imask = GENMASK_ULL(priv->offload.mb_last,
priv->offload.mb_first);
struct clk *clk_ipg;
struct clk *clk_per;
-@@ -874,16 +874,15 @@ static struct sk_buff *flexcan_mailbox_r
+@@ -880,16 +880,15 @@ static struct sk_buff *flexcan_mailbox_r
return skb;
}
}
static irqreturn_t flexcan_irq(int irq, void *dev_id)
-@@ -1054,6 +1053,7 @@ static int flexcan_chip_start(struct net
+@@ -1060,6 +1059,7 @@ static int flexcan_chip_start(struct net
struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->regs;
u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
int err, i;
struct flexcan_mb __iomem *mb;
-@@ -1226,8 +1226,9 @@ static int flexcan_chip_start(struct net
+@@ -1232,8 +1232,9 @@ static int flexcan_chip_start(struct net
/* enable interrupts atomically */
disable_irq(dev->irq);
priv->write(priv->reg_ctrl_default, ®s->ctrl);
enable_irq(dev->irq);
/* print chip status */
-@@ -1324,19 +1325,14 @@ static int flexcan_open(struct net_devic
+@@ -1330,19 +1331,14 @@ static int flexcan_open(struct net_devic
priv->offload.mailbox_read = flexcan_mailbox_read;
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
u32 reg_ctrl_default;
struct clk *clk_ipg;
-@@ -892,7 +892,8 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -898,7 +898,8 @@ static irqreturn_t flexcan_irq(int irq,
struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->regs;
irqreturn_t handled = IRQ_NONE;
enum can_state last_state = priv->can.state;
/* reception interrupt */
-@@ -926,10 +927,10 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -932,10 +933,10 @@ static irqreturn_t flexcan_irq(int irq,
}
}
u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
handled = IRQ_HANDLED;
-@@ -941,7 +942,7 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -947,7 +948,7 @@ static irqreturn_t flexcan_irq(int irq,
/* after sending a RTR frame MB is in RX mode */
priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&priv->tx_mb->can_ctrl);
netif_wake_queue(dev);
}
-@@ -1226,7 +1227,7 @@ static int flexcan_chip_start(struct net
+@@ -1232,7 +1233,7 @@ static int flexcan_chip_start(struct net
/* enable interrupts atomically */
disable_irq(dev->irq);
priv->write(priv->reg_ctrl_default, ®s->ctrl);
priv->write(upper_32_bits(reg_imask), ®s->imask2);
priv->write(lower_32_bits(reg_imask), ®s->imask1);
enable_irq(dev->irq);
-@@ -1321,6 +1322,7 @@ static int flexcan_open(struct net_devic
+@@ -1327,6 +1328,7 @@ static int flexcan_open(struct net_devic
flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
priv->tx_mb_idx = priv->mb_count - 1;
priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -780,6 +780,23 @@ static void flexcan_irq_state(struct net
+@@ -786,6 +786,23 @@ static void flexcan_irq_state(struct net
dev->stats.rx_fifo_errors++;
}
static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
{
return container_of(offload, struct flexcan_priv, offload);
-@@ -874,17 +891,6 @@ static struct sk_buff *flexcan_mailbox_r
+@@ -880,17 +897,6 @@ static struct sk_buff *flexcan_mailbox_r
return skb;
}
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -792,11 +792,24 @@ static inline u64 flexcan_read64_mask(st
+@@ -798,11 +798,24 @@ static inline u64 flexcan_read64_mask(st
return reg & mask;
}
static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
{
return container_of(offload, struct flexcan_priv, offload);
-@@ -933,7 +946,7 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -939,7 +952,7 @@ static irqreturn_t flexcan_irq(int irq,
}
}
/* transmission complete interrupt */
if (reg_iflag_tx & priv->tx_mask) {
-@@ -948,7 +961,7 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -954,7 +967,7 @@ static irqreturn_t flexcan_irq(int irq,
/* after sending a RTR frame MB is in RX mode */
priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
&priv->tx_mb->can_ctrl);
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -885,15 +885,10 @@ static struct sk_buff *flexcan_mailbox_r
+@@ -891,15 +891,10 @@ static struct sk_buff *flexcan_mailbox_r
}
mark_as_read:
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -629,10 +629,10 @@ static int flexcan_get_berr_counter(cons
+@@ -635,10 +635,10 @@ static int flexcan_get_berr_counter(cons
static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
const struct flexcan_priv *priv = netdev_priv(dev);
int i;
if (can_dropped_invalid_skb(dev, skb))
-@@ -640,18 +640,18 @@ static netdev_tx_t flexcan_start_xmit(st
+@@ -646,18 +646,18 @@ static netdev_tx_t flexcan_start_xmit(st
netif_stop_queue(dev);
priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
}
-@@ -823,7 +823,7 @@ static struct sk_buff *flexcan_mailbox_r
+@@ -829,7 +829,7 @@ static struct sk_buff *flexcan_mailbox_r
struct flexcan_regs __iomem *regs = priv->regs;
struct flexcan_mb __iomem *mb;
struct sk_buff *skb;
u32 reg_ctrl, reg_id, reg_iflag1;
int i;
-@@ -860,8 +860,8 @@ static struct sk_buff *flexcan_mailbox_r
+@@ -866,8 +866,8 @@ static struct sk_buff *flexcan_mailbox_r
reg_ctrl = priv->read(&mb->can_ctrl);
}
skb = ERR_PTR(-ENOMEM);
goto mark_as_read;
}
-@@ -871,17 +871,17 @@ static struct sk_buff *flexcan_mailbox_r
+@@ -877,17 +877,17 @@ static struct sk_buff *flexcan_mailbox_r
reg_id = priv->read(&mb->can_id);
if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
/* FlexCAN module is essentially modelled as a little-endian IP in most
* SoCs, i.e the registers as well as the message buffer areas are
* implemented in a little-endian fashion.
-@@ -632,7 +686,7 @@ static netdev_tx_t flexcan_start_xmit(st
+@@ -638,7 +692,7 @@ static netdev_tx_t flexcan_start_xmit(st
struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
u32 can_id;
u32 data;
int i;
if (can_dropped_invalid_skb(dev, skb))
-@@ -650,6 +704,9 @@ static netdev_tx_t flexcan_start_xmit(st
+@@ -656,6 +710,9 @@ static netdev_tx_t flexcan_start_xmit(st
if (cfd->can_id & CAN_RTR_FLAG)
ctrl |= FLEXCAN_MB_CNT_RTR;
for (i = 0; i < cfd->len; i += sizeof(u32)) {
data = be32_to_cpup((__be32 *)&cfd->data[i]);
priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
-@@ -860,7 +917,10 @@ static struct sk_buff *flexcan_mailbox_r
+@@ -866,7 +923,10 @@ static struct sk_buff *flexcan_mailbox_r
reg_ctrl = priv->read(&mb->can_ctrl);
}
if (unlikely(!skb)) {
skb = ERR_PTR(-ENOMEM);
goto mark_as_read;
-@@ -875,9 +935,17 @@ static struct sk_buff *flexcan_mailbox_r
+@@ -881,9 +941,17 @@ static struct sk_buff *flexcan_mailbox_r
else
cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
for (i = 0; i < cfd->len; i += sizeof(u32)) {
__be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
-@@ -1022,27 +1090,14 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -1028,27 +1096,14 @@ static irqreturn_t flexcan_irq(int irq,
static void flexcan_set_bittiming(struct net_device *dev)
{
if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
reg |= FLEXCAN_CTRL_LPB;
if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
-@@ -1053,9 +1108,102 @@ static void flexcan_set_bittiming(struct
+@@ -1059,9 +1114,102 @@ static void flexcan_set_bittiming(struct
netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
priv->write(reg, ®s->ctrl);
}
/* flexcan_chip_start
-@@ -1067,7 +1215,7 @@ static int flexcan_chip_start(struct net
+@@ -1073,7 +1221,7 @@ static int flexcan_chip_start(struct net
{
struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->regs;
u64 reg_imask;
int err, i;
struct flexcan_mb __iomem *mb;
-@@ -1166,6 +1314,26 @@ static int flexcan_chip_start(struct net
+@@ -1172,6 +1320,26 @@ static int flexcan_chip_start(struct net
netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
priv->write(reg_ctrl, ®s->ctrl);
if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
reg_ctrl2 = priv->read(®s->ctrl2);
reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
-@@ -1306,6 +1474,12 @@ static int flexcan_open(struct net_devic
+@@ -1312,6 +1480,12 @@ static int flexcan_open(struct net_devic
struct flexcan_priv *priv = netdev_priv(dev);
int err;
err = pm_runtime_get_sync(priv->dev);
if (err < 0) {
pm_runtime_put_noidle(priv->dev);
-@@ -1324,7 +1498,10 @@ static int flexcan_open(struct net_devic
+@@ -1330,7 +1504,10 @@ static int flexcan_open(struct net_devic
if (err)
goto out_transceiver_disable;
priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
(sizeof(priv->regs->mb[1]) / priv->mb_size);
-@@ -1676,6 +1853,18 @@ static int flexcan_probe(struct platform
+@@ -1682,6 +1859,18 @@ static int flexcan_probe(struct platform
priv->devtype_data = devtype_data;
priv->reg_xceiver = reg_xceiver;
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
-@@ -704,9 +704,13 @@ static netdev_tx_t flexcan_start_xmit(st
+@@ -710,9 +710,13 @@ static netdev_tx_t flexcan_start_xmit(st
if (cfd->can_id & CAN_RTR_FLAG)
ctrl |= FLEXCAN_MB_CNT_RTR;
for (i = 0; i < cfd->len; i += sizeof(u32)) {
data = be32_to_cpup((__be32 *)&cfd->data[i]);
priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
-@@ -937,6 +941,9 @@ static struct sk_buff *flexcan_mailbox_r
+@@ -943,6 +947,9 @@ static struct sk_buff *flexcan_mailbox_r
if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
cfd->len = can_dlc2len(get_canfd_dlc((reg_ctrl >> 16) & 0xf));
/* FLEXCAN memory error control register (MECR) bits */
#define FLEXCAN_MECR_ECRWRDIS BIT(31)
-@@ -1326,6 +1327,7 @@ static int flexcan_chip_start(struct net
+@@ -1332,6 +1333,7 @@ static int flexcan_chip_start(struct net
reg_fdctrl = priv->read(®s->fdctrl) & ~FLEXCAN_FDCTRL_FDRATE;
reg_fdctrl &= ~(FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3));
reg_mcr = priv->read(®s->mcr) & ~FLEXCAN_MCR_FDEN;
/* support BRS when set CAN FD mode
* 64 bytes payload per MB and 7 MBs per RAM block by default
-@@ -1335,10 +1337,14 @@ static int flexcan_chip_start(struct net
+@@ -1341,10 +1343,14 @@ static int flexcan_chip_start(struct net
reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
reg_fdctrl |= FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3);
reg_mcr |= FLEXCAN_MCR_FDEN;
}
if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
-@@ -1862,7 +1868,7 @@ static int flexcan_probe(struct platform
+@@ -1868,7 +1874,7 @@ static int flexcan_probe(struct platform
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_TIMESTAMP_SUPPORT_FD) {
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
/* FLEXCAN FD Bit Timing register (FDCBT) bits */
#define FLEXCAN_FDCBT_FPRESDIV(x) (((x) & 0x3ff) << 20)
-@@ -1102,7 +1105,7 @@ static void flexcan_set_bittiming(struct
+@@ -1108,7 +1111,7 @@ static void flexcan_set_bittiming(struct
struct can_bittiming *bt = &priv->can.bittiming;
struct can_bittiming *dbt = &priv->can.data_bittiming;
struct flexcan_regs __iomem *regs = priv->regs;
reg = priv->read(®s->ctrl);
reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP | FLEXCAN_CTRL_LOM);
-@@ -1174,6 +1177,19 @@ static void flexcan_set_bittiming(struct
+@@ -1180,6 +1183,19 @@ static void flexcan_set_bittiming(struct
FLEXCAN_FDCBT_FPROPSEG(dbt->prop_seg);
priv->write(reg_fdcbt, ®s->fdcbt);
if (bt->brp != dbt->brp)
netdev_warn(dev, "Warning!! data brp = %d and brp = %d don't match.\n"
"flexcan may not work. consider using different bitrate or data bitrate\n",
-@@ -1325,6 +1341,7 @@ static int flexcan_chip_start(struct net
+@@ -1331,6 +1347,7 @@ static int flexcan_chip_start(struct net
/* FDCTRL */
if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
reg_fdctrl = priv->read(®s->fdctrl) & ~FLEXCAN_FDCTRL_FDRATE;
static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
-@@ -1769,6 +1776,7 @@ out_put_node:
+@@ -1775,6 +1782,7 @@ out_put_node:
}
static const struct of_device_id flexcan_of_match[] = {
static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
-@@ -1785,6 +1792,7 @@ static const struct of_device_id flexcan
+@@ -1791,6 +1798,7 @@ static const struct of_device_id flexcan
{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
#include <linux/regmap.h>
#define DRV_NAME "flexcan"
-@@ -1965,9 +1966,7 @@ static int __maybe_unused flexcan_suspen
+@@ -1971,9 +1972,7 @@ static int __maybe_unused flexcan_suspen
if (err)
return err;
} else {
}
netif_stop_queue(dev);
netif_device_detach(dev);
-@@ -1993,7 +1992,9 @@ static int __maybe_unused flexcan_resume
+@@ -1999,7 +1998,9 @@ static int __maybe_unused flexcan_resume
if (err)
return err;
} else {
/* FLEXCAN Bit Timing register (CBT) bits */
#define FLEXCAN_CBT_BTF BIT(31)
-@@ -1056,6 +1055,12 @@ static irqreturn_t flexcan_irq(int irq,
+@@ -1062,6 +1061,12 @@ static irqreturn_t flexcan_irq(int irq,
reg_esr = priv->read(®s->esr);
reg_mcr = priv->read(®s->mcr);
-@@ -1776,11 +1820,6 @@ static int flexcan_setup_stop_mode(struc
+@@ -1782,11 +1826,6 @@ static int flexcan_setup_stop_mode(struc
gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
priv->stm.ack_gpr, priv->stm.ack_bit);
return 0;
out_put_node:
-@@ -1788,6 +1827,30 @@ out_put_node:
+@@ -1794,6 +1833,30 @@ out_put_node:
return ret;
}
static const struct of_device_id flexcan_of_match[] = {
{ .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
-@@ -1930,9 +1993,19 @@ static int flexcan_probe(struct platform
+@@ -1936,9 +1999,19 @@ static int flexcan_probe(struct platform
devm_can_led_init(dev);
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
static const struct can_bittiming_const flexcan_bittiming_const = {
.name = DRV_NAME,
.tseg1_min = 4,
-@@ -1862,6 +1867,8 @@ static const struct of_device_id flexcan
+@@ -1868,6 +1873,8 @@ static const struct of_device_id flexcan
{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
{ .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
--- a/drivers/net/dsa/b53/b53_common.c
+++ b/drivers/net/dsa/b53/b53_common.c
-@@ -1291,7 +1291,9 @@ EXPORT_SYMBOL(b53_phylink_mac_link_down)
+@@ -1284,7 +1284,9 @@ EXPORT_SYMBOL(b53_phylink_mac_link_down)
void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface,
const struct switchdev_obj_port_vlan *vlan);
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -634,7 +634,9 @@ static void bcm_sf2_sw_mac_link_down(str
+@@ -636,7 +636,9 @@ static void bcm_sf2_sw_mac_link_down(str
static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface,
#include <linux/crc32.h>
#include <linux/if_vlan.h>
#include <linux/uaccess.h>
-@@ -4363,6 +4364,22 @@ static void rtl_tally_reset(struct r8152
+@@ -4335,6 +4336,22 @@ static void rtl_tally_reset(struct r8152
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
}
static void r8152b_init(struct r8152 *tp)
{
u32 ocp_data;
-@@ -4404,6 +4421,8 @@ static void r8152b_init(struct r8152 *tp
+@@ -4376,6 +4393,8 @@ static void r8152b_init(struct r8152 *tp
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
}
static void r8153_init(struct r8152 *tp)
-@@ -4533,6 +4552,8 @@ static void r8153_init(struct r8152 *tp)
+@@ -4510,6 +4529,8 @@ static void r8153_init(struct r8152 *tp)
tp->coalesce = COALESCE_SLOW;
break;
}
}
static void r8153b_init(struct r8152 *tp)
-@@ -4609,6 +4630,8 @@ static void r8153b_init(struct r8152 *tp
+@@ -4586,6 +4607,8 @@ static void r8153b_init(struct r8152 *tp
rtl_tally_reset(tp);
tp->coalesce = 15000; /* 15 us */
projects / openwrt / staging / dangole.git / commitdiff