net: stmmac: pci: Add HAPS support using GMAC5

Add the support for Synopsys HAPS board that uses GMAC5.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
index 20906287b6d465a921b5d2c886d6aeb4d82cdb46..292045f4581f78996036c8f243ecc90237bbf393 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
@@ -375,6 +375,75 @@ static const struct stmmac_pci_info quark_pci_info = {
        .setup = quark_default_data,
 };
 
+static int snps_gmac5_default_data(struct pci_dev *pdev,
+                                  struct plat_stmmacenet_data *plat)
+{
+       int i;
+
+       plat->clk_csr = 5;
+       plat->has_gmac4 = 1;
+       plat->force_sf_dma_mode = 1;
+       plat->tso_en = 1;
+       plat->pmt = 1;
+
+       plat->mdio_bus_data->phy_mask = 0;
+
+       /* Set default value for multicast hash bins */
+       plat->multicast_filter_bins = HASH_TABLE_SIZE;
+
+       /* Set default value for unicast filter entries */
+       plat->unicast_filter_entries = 1;
+
+       /* Set the maxmtu to a default of JUMBO_LEN */
+       plat->maxmtu = JUMBO_LEN;
+
+       /* Set default number of RX and TX queues to use */
+       plat->tx_queues_to_use = 4;
+       plat->rx_queues_to_use = 4;
+
+       plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
+       for (i = 0; i < plat->tx_queues_to_use; i++) {
+               plat->tx_queues_cfg[i].use_prio = false;
+               plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
+               plat->tx_queues_cfg[i].weight = 25;
+       }
+
+       plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
+       for (i = 0; i < plat->rx_queues_to_use; i++) {
+               plat->rx_queues_cfg[i].use_prio = false;
+               plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
+               plat->rx_queues_cfg[i].pkt_route = 0x0;
+               plat->rx_queues_cfg[i].chan = i;
+       }
+
+       plat->bus_id = 1;
+       plat->phy_addr = -1;
+       plat->interface = PHY_INTERFACE_MODE_GMII;
+
+       plat->dma_cfg->pbl = 32;
+       plat->dma_cfg->pblx8 = true;
+
+       /* Axi Configuration */
+       plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL);
+       if (!plat->axi)
+               return -ENOMEM;
+
+       plat->axi->axi_wr_osr_lmt = 31;
+       plat->axi->axi_rd_osr_lmt = 31;
+
+       plat->axi->axi_fb = false;
+       plat->axi->axi_blen[0] = 4;
+       plat->axi->axi_blen[1] = 8;
+       plat->axi->axi_blen[2] = 16;
+       plat->axi->axi_blen[3] = 32;
+
+       return 0;
+}
+
+static const struct stmmac_pci_info snps_gmac5_pci_info = {
+       .setup = snps_gmac5_default_data,
+};
+
 /**
  * stmmac_pci_probe
  *
@@ -518,6 +587,7 @@ static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume);
 #define STMMAC_EHL_RGMII1G_ID  0x4b30
 #define STMMAC_EHL_SGMII1G_ID  0x4b31
 #define STMMAC_TGL_SGMII1G_ID  0xa0ac
+#define STMMAC_GMAC5_ID                0x7102
 
 #define STMMAC_DEVICE(vendor_id, dev_id, info) {       \
        PCI_VDEVICE(vendor_id, dev_id),                 \
@@ -531,6 +601,7 @@ static const struct pci_device_id stmmac_id_table[] = {
        STMMAC_DEVICE(INTEL, STMMAC_EHL_RGMII1G_ID, ehl_rgmii1g_pci_info),
        STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info),
        STMMAC_DEVICE(INTEL, STMMAC_TGL_SGMII1G_ID, tgl_sgmii1g_pci_info),
+       STMMAC_DEVICE(SYNOPSYS, STMMAC_GMAC5_ID, snps_gmac5_pci_info),
        {}
 };