stm32mp1: fix TZC400 configuration against non-secure DDR

This change disables secure accesses to non-secure DDR which are useless.
TF-A already maps non-secure memory with non-secure permissions thanks
to the MMU.

This change also corrects some inline comments.

Change-Id: Id4c20c9ee5c95a666dae6b7446ed80baf2d53fb0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c
index 0ad43e43536bd87239c1a024c434a43639062c0a..1cd56c60f57e5fa1c93bd1e1d4e4d1843c6fdd7b 100644 (file)
--- a/plat/st/stm32mp1/stm32mp1_security.c
+++ b/plat/st/stm32mp1/stm32mp1_security.c
@@ -14,6 +14,19 @@
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <lib/mmio.h>
 
+#define TZC_REGION_NSEC_ALL_ACCESS_RDWR \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \
+       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID)
+
 /*******************************************************************************
  * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
  * and allow Non-Secure masters full access.
@@ -23,31 +36,23 @@ static void init_tzc400(void)
        unsigned long long region_base, region_top;
        unsigned long long ddr_base = STM32MP_DDR_BASE;
        unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
+       unsigned long long ddr_top = ddr_base + (ddr_size - 1U);
 
        tzc400_init(STM32MP1_TZC_BASE);
 
        tzc400_disable_filters();
 
-       /* Region 1 set to cover all DRAM at 0xC000_0000. Apply the
+       /*
+        * Region 1 set to cover all DRAM at 0xC000_0000. Apply the
         * same configuration to all filters in the TZC.
         */
        region_base = ddr_base;
-       region_top = ddr_base + (ddr_size - 1U);
+       region_top = ddr_top;
        tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
-                       region_base,
-                       region_top,
-                       TZC_REGION_S_RDWR,
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) |
-                       TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID));
+                               region_base,
+                               region_top,
+                               TZC_REGION_S_NONE,
+                               TZC_REGION_NSEC_ALL_ACCESS_RDWR);
 
        /* Raise an exception if a NS device tries to access secure memory */
        tzc400_set_action(TZC_ACTION_ERR);
@@ -69,15 +74,12 @@ static void early_init_tzc400(void)
 
        tzc400_disable_filters();
 
-       /*
-        * Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the
-        * same configuration to all filters in the TZC.
-        */
+       /* Region 1 set to cover Non-Secure DRAM at 0xC000_0000 */
        tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
                                STM32MP_DDR_BASE,
                                STM32MP_DDR_BASE +
                                (STM32MP_DDR_MAX_SIZE - 1U),
-                               TZC_REGION_S_RDWR,
+                               TZC_REGION_S_NONE,
                                TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
                                TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));