ppc4xx: Update 440EPx lwmon5 board support

- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index b6863b6a79bb7d349dc5ba9bbfae7483334a7f39..f906b859a312b51dd51b52c27d918d8daaa12cc1 100644 (file)
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -473,7 +473,7 @@ static void program_ecc(u32 start_address,
                blank_string(strlen(str));
        } else {
                /* ECC bit set method for cached memory */
-#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
                /*
                 * Some boards (like lwmon5) need to preserve the memory
                 * content upon ECC generation (for the log-buffer).
@@ -486,6 +486,11 @@ static void program_ecc(u32 start_address,
 
                current_address = start_address;
                while (current_address < end_address) {
+                       /*
+                        * TODO: Th following sequence doesn't work correctly.
+                        * Just invalidating and flushing the cache doesn't
+                        * seem to trigger the re-write of the memory.
+                        */
                        ppcDcbi(current_address);
                        ppcDcbf(current_address);
                        current_address += CFG_CACHELINE_SIZE;
@@ -514,19 +519,6 @@ static void program_ecc(u32 start_address,
 }
 #endif
 
-static __inline__ u32 get_mcsr(void)
-{
-       u32 val;
-
-       asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
-       return val;
-}
-
-static __inline__ void set_mcsr(u32 val)
-{
-       asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -534,8 +526,6 @@ static __inline__ void set_mcsr(u32 val)
  ************************************************************************/
 long int initdram (int board_type)
 {
-       u32 val;
-
 #if 0 /* test-only: will remove this define later, when ECC problems are solved! */
        /* CL=3 */
        mtsdram(DDR0_02, 0x00000000);
@@ -640,14 +630,6 @@ long int initdram (int board_type)
         * Perform data eye search if requested.
         */
        denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
-
-       /*
-        * Clear possible errors resulting from data-eye-search.
-        * If not done, then we could get an interrupt later on when
-        * exceptions are enabled.
-        */
-       val = get_mcsr();
-       set_mcsr(val);
 #endif
 
 #ifdef CONFIG_DDR_ECC
@@ -657,5 +639,12 @@ long int initdram (int board_type)
        program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 #endif
 
+       /*
+        * Clear possible errors resulting from data-eye-search.
+        * If not done, then we could get an interrupt later on when
+        * exceptions are enabled.
+        */
+       set_mcsr(get_mcsr());
+
        return (CFG_MBYTES_SDRAM << 20);
 }

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index b09b47830a457b54a7b927d8984513de647439a4..5ebe4404d92826b703583d9e2bcb651af29ceb82 100644 (file)
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -140,7 +140,6 @@
 
 /* POST support */
 #define CONFIG_POST            (CFG_POST_ECC)
-
 #endif
 
 /*-----------------------------------------------------------------------

diff --git a/include/ppc440.h b/include/ppc440.h
index 93c10f1209960809941f06a3c78478ad8abeddfc..38809f34b4b351dcaf84a9b7f4a596aaecdd349d 100644 (file)
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -3354,6 +3354,19 @@ typedef struct {
        unsigned long pciClkSync;             /* PCI clock is synchronous        */
 } PPC440_SYS_INFO;
 
+static inline u32 get_mcsr(void)
+{
+       u32 val;
+
+       asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+       return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+       asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
 #endif /* _ASMLANGUAGE */
 
 #define RESET_VECTOR           0xfffffffc

diff --git a/post/board/lwmon5/ecc.c b/post/board/lwmon5/ecc.c
index 7f04f9abed9b4d6eec9da90565253ad31b5ce082..3fa3ba62435747b338078a2bd0bce3559386fd8d 100644 (file)
--- a/post/board/lwmon5/ecc.c
+++ b/post/board/lwmon5/ecc.c
@@ -236,7 +236,6 @@ int ecc_post_test (int flags)
        mfsdram(DDR0_00, value);
        mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
 
-
        /* enable full support of ECC */
        mfsdram(DDR0_22, value);
        mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
@@ -247,6 +246,17 @@ int ecc_post_test (int flags)
                if (ret)
                        break;
        }
+
+       /* clear error status */
+       mfsdram(DDR0_00, value);
+       mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+       /*
+        * Clear possible errors resulting from ECC testing.
+        * If not done, then we could get an interrupt later on when
+        * exceptions are enabled.
+        */
+       set_mcsr(get_mcsr());
 #endif
 
        return ret;

diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c
index 27e9ed01afc86bc29efe5d7fdd25023e191a56e6..0c26fe00e4c3b90aade7978ec06e759d0d64a7a3 100644 (file)
--- a/post/cpu/ppc4xx/fpu.c
+++ b/post/cpu/ppc4xx/fpu.c
@@ -29,8 +29,8 @@
 #if defined(CONFIG_440EP) || \
     defined(CONFIG_440EPX)
 
-#include <ppc4xx.h>
 #include <asm/processor.h>
+#include <ppc4xx.h>
 
 
 int fpu_status(void)