drm/i915: wait for rings to become idle once disabled
authorNaresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Wed, 12 Mar 2014 11:09:41 +0000 (16:39 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 12 Mar 2014 15:04:19 +0000 (16:04 +0100)
make sure we wait for rings to become idle once they are
disabled. In case of timeout print an error message

Signed-off-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
[danvet: Frob patch as suggested by Chris.]
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_ringbuffer.h

index 146609ab42bb982c1510a28f7e1a432ff53474e2..6174fda4d58ea4dd8e2a4af12620516f3144c219 100644 (file)
@@ -748,6 +748,7 @@ enum punit_power_well {
 #define RING_INSTPS(base)      ((base)+0x70)
 #define RING_DMA_FADD(base)    ((base)+0x78)
 #define RING_INSTPM(base)      ((base)+0xc0)
+#define RING_MI_MODE(base)     ((base)+0x9c)
 #define INSTPS         0x02070 /* 965+ only */
 #define INSTDONE1      0x0207c /* 965+ only */
 #define ACTHD_I965     0x02074
@@ -824,6 +825,7 @@ enum punit_power_well {
 # define VS_TIMER_DISPATCH                             (1 << 6)
 # define MI_FLUSH_ENABLE                               (1 << 12)
 # define ASYNC_FLIP_PERF_DISABLE                       (1 << 14)
+# define MODE_IDLE                                     (1 << 9)
 
 #define GEN6_GT_MODE   0x20d0
 #define GEN7_GT_MODE   0x7008
index 42b4001443795f60cc55d5eb5c9fc9fe33ef854f..617634b6a6c2b3d8bd02ec4e90787f11d547aa35 100644 (file)
@@ -444,6 +444,8 @@ static int init_ring_common(struct intel_ring_buffer *ring)
        I915_WRITE_CTL(ring, 0);
        I915_WRITE_HEAD(ring, 0);
        ring->write_tail(ring, 0);
+       if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
+               DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 
        if (I915_NEED_GFX_HWS(dev))
                intel_ring_setup_status_page(ring);
index 09af92099c1bbbe30ed70e8cb0647e12e9ffa4c6..f11ceb230db48cc92db0978fc73afb5f443d6e4d 100644 (file)
@@ -33,6 +33,8 @@ struct  intel_hw_status_page {
 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
 
+#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
+
 enum intel_ring_hangcheck_action {
        HANGCHECK_IDLE = 0,
        HANGCHECK_WAIT,