--- /dev/null
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -164,6 +164,12 @@ static void __init ath79_detect_sys_type
+ rev = id & AR934X_REV_ID_REVISION_MASK;
+ break;
+
++ case REV_ID_MAJOR_QCA9556:
++ ath79_soc = ATH79_SOC_QCA9556;
++ chip = "9556";
++ rev = id & AR944X_REV_ID_REVISION_MASK;
++ break;
++
+ case REV_ID_MAJOR_QCA9558:
+ ath79_soc = ATH79_SOC_QCA9558;
+ chip = "9558";
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -460,6 +460,7 @@
+ #define REV_ID_MAJOR_AR9341 0x0120
+ #define REV_ID_MAJOR_AR9342 0x1120
+ #define REV_ID_MAJOR_AR9344 0x2120
++#define REV_ID_MAJOR_QCA9556 0x0130
+ #define REV_ID_MAJOR_QCA9558 0x1130
+
+ #define AR71XX_REV_ID_MINOR_MASK 0x3
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,6 +32,7 @@ enum ath79_soc_type {
+ ATH79_SOC_AR9341,
+ ATH79_SOC_AR9342,
+ ATH79_SOC_AR9344,
++ ATH79_SOC_QCA9556,
+ ATH79_SOC_QCA9558,
+ };
+
+@@ -99,6 +100,11 @@ static inline int soc_is_ar934x(void)
+ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
+
++static inline int soc_is_qca9556(void)
++{
++ return ath79_soc == ATH79_SOC_QCA9556;
++}
++
+ static inline int soc_is_qca9558(void)
+ {
+ return ath79_soc == ATH79_SOC_QCA9558;
+@@ -106,7 +112,7 @@ static inline int soc_is_qca9558(void)
+
+ static inline int soc_is_qca955x(void)
+ {
+- return soc_is_qca9558();
++ return soc_is_qca9556() || soc_is_qca9558();
+ }
+
+ extern void __iomem *ath79_ddr_base;
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -528,6 +625,12 @@
+@@ -529,6 +626,12 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
-@@ -559,4 +662,133 @@
+@@ -560,4 +663,133 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7