drm/i915: add S PLL control

This PLL control can drive DDI ports at desired frequencies for
DisplayPort and FDI connections.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a9a47f6ef7d16a65631f5f82e0ac79947defc523..58046ffcf031d5b0e0ab3b4847a955605b0f2a6c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4134,4 +4134,12 @@
 #define  PIXCLK_GATE_UNGATE            1<<0
 #define  PIXCLK_GATE_GATE              0<<0
 
+/* SPLL */
+#define SPLL_CTL                               0x46020
+#define  SPLL_PLL_ENABLE               (1<<31)
+#define  SPLL_PLL_SCC                  (1<<28)
+#define  SPLL_PLL_NON_SCC              (2<<28)
+#define  SPLL_PLL_FREQ_810MHz  (0<<26)
+#define  SPLL_PLL_FREQ_1350MHz (1<<26)
+
 #endif /* _I915_REG_H_ */