static bool
ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
{
+ struct bcma_device *pci = NULL;
+ struct bcma_device *pcie = NULL;
struct bcma_device *core;
- bool pci, pcie;
- uint i;
- uint pciidx, pcieidx, pcirev, pcierev;
/* no cores found, bail out */
sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
}
- /* figure out bus/orignal core idx */
- sii->pub.buscoretype = NODEV_CORE_ID;
- sii->pub.buscorerev = NOREV;
- sii->buscoreidx = BADIDX;
-
- pci = pcie = false;
- pcirev = pcierev = NOREV;
- pciidx = pcieidx = BADIDX;
-
+ /* figure out buscore */
list_for_each_entry(core, &cc->bus->cores, list) {
uint cid, crev;
crev = core->id.rev;
if (cid == PCI_CORE_ID) {
- pciidx = i;
- pcirev = crev;
- pci = true;
+ pci = core;
} else if (cid == PCIE_CORE_ID) {
- pcieidx = i;
- pcierev = crev;
- pcie = true;
+ pcie = core;
}
}
if (pci && pcie) {
if (ai_ispcie(sii))
- pci = false;
+ pci = NULL;
else
- pcie = false;
+ pcie = NULL;
}
if (pci) {
- sii->pub.buscoretype = PCI_CORE_ID;
- sii->pub.buscorerev = pcirev;
- sii->buscoreidx = pciidx;
+ sii->buscore = pci;
} else if (pcie) {
- sii->pub.buscoretype = PCIE_CORE_ID;
- sii->pub.buscorerev = pcierev;
- sii->buscoreidx = pcieidx;
+ sii->buscore = pcie;
}
/* fixup necessary chip/core configurations */
if (sii->pch == NULL)
return false;
}
- if (ai_pci_fixcfg(&sii->pub)) {
- /* si_doattach: si_pci_fixcfg failed */
+ if (ai_pci_fixcfg(&sii->pub))
return false;
- }
return true;
}
savewin = 0;
sii->icbus = pbus;
- sii->buscoreidx = BADIDX;
sii->pcibus = pbus->host_pci;
/* switch to Chipcommon core */
return false;
}
}
+
+uint ai_get_buscoretype(struct si_pub *sih)
+{
+ struct si_info *sii = (struct si_info *)sih;
+ return sii->buscore->id.id;
+}
+
+uint ai_get_buscorerev(struct si_pub *sih)
+{
+ struct si_info *sii = (struct si_info *)sih;
+ return sii->buscore->id.rev;
+}
* public (read-only) portion of aiutils handle returned by si_attach()
*/
struct si_pub {
- uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
- uint buscorerev; /* buscore rev */
int ccrev; /* chip common core rev */
u32 cccaps; /* chip common capabilities */
int pmurev; /* pmu core rev */
struct bcma_bus *icbus; /* handle to soc interconnect bus */
struct pci_dev *pcibus; /* handle to pci bus */
struct pcicore_info *pch; /* PCI/E core handle */
-
+ struct bcma_device *buscore;
struct list_head var_list; /* list of srom variables */
u32 chipst; /* chip status */
- uint buscoreidx; /* buscore index */
};
/*
/* Enable Ex-PA for 4313 */
extern void ai_epa_4313war(struct si_pub *sih);
-static inline uint ai_get_buscoretype(struct si_pub *sih)
-{
- return sih->buscoretype;
-}
+extern uint ai_get_buscoretype(struct si_pub *sih);
+extern uint ai_get_buscorerev(struct si_pub *sih);
-static inline uint ai_get_buscorerev(struct si_pub *sih)
-{
- return sih->buscorerev;
-}
static inline int ai_get_ccrev(struct si_pub *sih)
{
return sih->ccrev;
}
+
static inline u32 ai_get_cccaps(struct si_pub *sih)
{
return sih->cccaps;
}
+
static inline int ai_get_pmurev(struct si_pub *sih)
{
return sih->pmurev;
}
+
static inline u32 ai_get_pmucaps(struct si_pub *sih)
{
return sih->pmucaps;
}
+
static inline uint ai_get_boardtype(struct si_pub *sih)
{
return sih->boardtype;
}
+
static inline uint ai_get_boardvendor(struct si_pub *sih)
{
return sih->boardvendor;
}
+
static inline uint ai_get_chip_id(struct si_pub *sih)
{
return sih->chip;
}
+
static inline uint ai_get_chiprev(struct si_pub *sih)
{
return sih->chiprev;
}
+
static inline uint ai_get_chippkg(struct si_pub *sih)
{
return sih->chippkg;
bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol),
MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
- if (pi->sih->buscorerev >= 10) {
+ if (ai_get_buscorerev(pi->sih) >= 10) {
/* new serdes is slower in rw,
* using two layers of reg address mapping
*/
pcie_extendL1timer(pi, false);
}
-/* precondition: current core is sii->buscoretype */
void pcicore_fixcfg(struct pcicore_info *pi)
{
struct bcma_device *core = pi->core;