* to allow rounding later */
#define FIXED_FLL_SIZE ((1 << 22) * 10)
-static int wm8995_pll_factors(struct device *dev,
+static int wm8955_pll_factors(struct device *dev,
int Fref, int Fout, struct pll_factors *pll)
{
u64 Kpart;
/* Use the last divider configuration we saw for the
* sample rate. */
- ret = wm8995_pll_factors(component->dev, wm8955->mclk_rate,
+ ret = wm8955_pll_factors(component->dev, wm8955->mclk_rate,
clock_cfgs[sr].mclk, &pll);
if (ret != 0) {
dev_err(component->dev,