if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
resp.tunnel_offloads_caps |=
MLX5_IB_TUNNELED_OFFLOADS_GRE;
+ if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
+ MLX5_FLEX_PROTO_CW_MPLS_GRE)
+ resp.tunnel_offloads_caps |=
+ MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
+ if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
+ MLX5_FLEX_PROTO_CW_MPLS_UDP)
+ resp.tunnel_offloads_caps |=
+ MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
}
if (uhw->outlen) {
MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
};
+enum mlx5_flex_parser_protos {
+ MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
+ MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
+};
+
/* MLX5 DEV CAPs */
/* TODO: EAT.ME */
u8 reserved_at_500[0x20];
u8 num_of_uars_per_page[0x20];
- u8 reserved_at_540[0x40];
+
+ u8 flex_parser_protocols[0x20];
+ u8 reserved_at_560[0x20];
u8 reserved_at_580[0x3d];
u8 cqe_128_always[0x1];
enum mlx5_ib_tunnel_offloads {
MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
- MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
+ MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
+ MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
+ MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
};
struct mlx5_ib_query_device_resp {