clk: rockchip: use general clock flag when registering pll
authorHeiko Stübner <heiko@sntech.de>
Fri, 29 Jul 2016 07:56:55 +0000 (15:56 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 8 Aug 2016 08:57:21 +0000 (10:57 +0200)
Add the general flags the pll list already contains to the clock init,
so that needed clock flags can be used for plls.

Signed-off-by: Heiko Stübner <heiko@sntech.de>
drivers/clk/rockchip/clk-pll.c
drivers/clk/rockchip/clk.c
drivers/clk/rockchip/clk.h

index db81e454166bfba9f66f35368d6f0b58ab6fdd7f..9c1373e81683bebec4c0968b30036c5b175e8028 100644 (file)
@@ -837,7 +837,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
                u8 num_parents, int con_offset, int grf_lock_offset,
                int lock_shift, int mode_offset, int mode_shift,
                struct rockchip_pll_rate_table *rate_table,
-               u8 clk_pll_flags)
+               unsigned long flags, u8 clk_pll_flags)
 {
        const char *pll_parents[3];
        struct clk_init_data init;
@@ -892,7 +892,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
        init.name = pll_name;
 
        /* keep all plls untouched for now */
-       init.flags = CLK_IGNORE_UNUSED;
+       init.flags = flags | CLK_IGNORE_UNUSED;
 
        init.parent_names = &parent_names[0];
        init.num_parents = 1;
index 7ffd134995f222bac2a088146b4dd05d9320eca0..1f1c74f3744b7e163e5aac5ca51d7fadd34d28a5 100644 (file)
@@ -385,7 +385,7 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
                                list->con_offset, grf_lock_offset,
                                list->lock_shift, list->mode_offset,
                                list->mode_shift, list->rate_table,
-                               list->pll_flags);
+                               list->flags, list->pll_flags);
                if (IS_ERR(clk)) {
                        pr_err("%s: failed to register clock %s\n", __func__,
                                list->name);
index 2194ffa8c9fd5a778130d56c97fed31840414bfa..3747de5ce7c231875d6b2f16a98da089ed08b2da 100644 (file)
@@ -238,7 +238,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
                u8 num_parents, int con_offset, int grf_lock_offset,
                int lock_shift, int mode_offset, int mode_shift,
                struct rockchip_pll_rate_table *rate_table,
-               u8 clk_pll_flags);
+               unsigned long flags, u8 clk_pll_flags);
 
 struct rockchip_cpuclk_clksel {
        int reg;