Add workaround for errata 855423 of Cortex-A73

Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.

Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index 315457a19ff3ca8d076446d113f4b159dfc56687..d417521e41edb877fcd1d75024e199ed5a9ba420 100644 (file)
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -132,6 +132,11 @@ For Cortex-A72, the following errata build flags are defined :
 -  ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
    CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
 
+For Cortex-A73, the following errata build flags are defined :
+
+-  ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
+   CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
+
 DSU Errata Workarounds
 ----------------------
 

diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index 3b401805a8228640ef4b308064f2720b98f8c9e7..61b2b737bdc0150537940a2d51ed1f37d3d9f0ce 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -31,4 +31,6 @@
 
 #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE        (ULL(1) << 3)
 
+#define CORTEX_A73_IMP_DEF_REG2                S3_0_C15_C0_2
+
 #endif /* CORTEX_A73_H */

diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index 772b0be79d8708ebb811fac5563ac5b85e43b69c..6cfa4b5231a0f416900f6d719a5a0a08547a5e79 100644 (file)
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -35,7 +35,47 @@ func cortex_a73_disable_smp
        ret
 endfunc cortex_a73_disable_smp
 
+       /* ---------------------------------------------------
+        * Errata Workaround for Cortex A73 Errata #855423.
+        * This applies only to revision <= r0p1 of Cortex A73.
+        * Inputs:
+        * x0: variant[4:7] and revision[0:3] of current cpu.
+        * Shall clobber: x0-x17
+        * ---------------------------------------------------
+        */
+func errata_a73_855423_wa
+       /*
+        * Compare x0 against revision r0p1
+        */
+       mov     x17, x30
+       bl      check_errata_855423
+       cbz     x0, 1f
+       mrs     x1, CORTEX_A73_IMP_DEF_REG2
+       orr     x1, x1, #(1 << 7)
+       msr     CORTEX_A73_IMP_DEF_REG2, x1
+       isb
+1:
+       ret     x17
+endfunc errata_a73_855423_wa
+
+func check_errata_855423
+       mov     x1, #0x01
+       b       cpu_rev_var_ls
+endfunc check_errata_855423
+
+       /* -------------------------------------------------
+        * The CPU Ops reset function for Cortex-A73.
+        * -------------------------------------------------
+        */
+
 func cortex_a73_reset_func
+       mov     x19, x30
+       bl      cpu_get_rev_var
+
+#if ERRATA_A73_855423
+       bl      errata_a73_855423_wa
+#endif
+
 #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
        cpu_check_csv2  x0, 1f
        adr     x0, wa_cve_2017_5715_bpiall_vbar
@@ -60,7 +100,7 @@ func cortex_a73_reset_func
        orr     x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
        msr     CORTEX_A73_CPUECTLR_EL1, x0
        isb
-       ret
+       ret     x19
 endfunc cortex_a73_reset_func
 
 func cortex_a73_core_pwr_dwn
@@ -160,6 +200,7 @@ func cortex_a73_errata_report
         * Report all errata. The revision-variant information is passed to
         * checking functions of each errata.
         */
+       report_errata ERRATA_A73_855423, cortex_a73, 855423
        report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
        report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639
 

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 7824df2828d4096007bbfba806ffbb09e6a24d61..a9c6fda8d6dc4773b3d9987aa43dd6bae1596bdc 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -119,6 +119,10 @@ ERRATA_A57_859972  ?=0
 # only to revision <= r0p3 of the Cortex A72 cpu.
 ERRATA_A72_859971      ?=0
 
+# Flag to apply erratum 855423 workaround during reset. This erratum applies
+# only to revision <= r0p1 of the Cortex A73 cpu.
+ERRATA_A73_855423      ?=0
+
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202      ?=1
@@ -188,6 +192,10 @@ $(eval $(call add_define,ERRATA_A57_859972))
 $(eval $(call assert_boolean,ERRATA_A72_859971))
 $(eval $(call add_define,ERRATA_A72_859971))
 
+# Process ERRATA_A73_855423 flag
+$(eval $(call assert_boolean,ERRATA_A73_855423))
+$(eval $(call add_define,ERRATA_A73_855423))
+
 # Process ERRATA_N1_1043202 flag
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))