ti: k3: common: Enable MMU using xlat_tables_v2 library

This library will be used to properly set up mappings from different
bootloaders at different exception levels. It ensures that memory mapped
devices such as UARTs are still accessible and memory regions have the
correct access permissions.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c
index fe68d56d92622662fb32765108077f87d2e0e3dc..11289df498e9d8a33e590576d7997dc6f7bb1412 100644 (file)
--- a/plat/ti/k3/common/k3_bl31_setup.c
+++ b/plat/ti/k3/common/k3_bl31_setup.c
@@ -9,9 +9,16 @@
 #include <assert.h>
 #include <bl_common.h>
 #include <debug.h>
+#include <plat_arm.h>
 #include <platform_def.h>
 #include <string.h>
 
+/* Table of regions to map using the MMU */
+const mmap_region_t plat_arm_mmap[] = {
+       MAP_REGION_FLAT(SHARED_RAM_BASE, SHARED_RAM_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+       { /* sentinel */ }
+};
+
 /*
  * Placeholder variables for maintaining information about the next image(s)
  */
@@ -85,7 +92,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 void bl31_plat_arch_setup(void)
 {
-       /* TODO: Initialize the MMU tables */
+       arm_setup_page_tables(BL31_BASE,
+                             BL31_END - BL31_BASE,
+                             BL_CODE_BASE,
+                             BL_CODE_END,
+                             BL_RO_DATA_BASE,
+                             BL_RO_DATA_END);
+       enable_mmu_el3(0);
 }
 
 void bl31_platform_setup(void)

diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 43cdc9ac95fa2555a6ee317da10754890f82b94c..f707c63a325dfde3269aa3353d475fb79fdd09f4 100644 (file)
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -25,13 +25,18 @@ ERRATA_A53_836870   :=      1
 ERRATA_A53_843419      :=      1
 ERRATA_A53_855873      :=      1
 
+# Libraries
+include lib/xlat_tables_v2/xlat_tables.mk
+
 PLAT_INCLUDES          +=      \
                                -I${PLAT_PATH}/include                  \
                                -Iinclude/plat/arm/common/              \
                                -Iinclude/plat/arm/common/aarch64/      \
 
 PLAT_BL_COMMON_SOURCES +=      \
+                               plat/arm/common/arm_common.c            \
                                lib/cpus/aarch64/cortex_a53.S           \
+                               ${XLAT_TABLES_LIB_SRCS}                 \
 
 BL31_SOURCES           +=      \
                                ${PLAT_PATH}/common/k3_bl31_setup.c     \

diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index bac8af1958f7e11998720aee3629fbf46dcd3070..10389528caffae10dc6b4c0fac818a7e60cc8748 100644 (file)
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -87,6 +87,33 @@
 #define BL31_LIMIT                     (BL31_BASE + BL31_SIZE)
 #define BL31_PROGBITS_LIMIT            BL31_LIMIT
 
+/*
+ * Defines the maximum number of translation tables that are allocated by the
+ * translation table library code. To minimize the amount of runtime memory
+ * used, choose the smallest value needed to map the required virtual addresses
+ * for each BL stage.
+ */
+#define MAX_XLAT_TABLES                8
+
+/*
+ * Defines the maximum number of regions that are allocated by the translation
+ * table library code. A region consists of physical base address, virtual base
+ * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
+ * defined in the `mmap_region_t` structure. The platform defines the regions
+ * that should be mapped. Then, the translation table library will create the
+ * corresponding tables and descriptors at runtime. To minimize the amount of
+ * runtime memory used, choose the smallest value needed to register the
+ * required regions for each BL stage.
+ */
+#define MAX_MMAP_REGIONS       8
+
+/*
+ * Defines the total size of the address space in bytes. For example, for a 32
+ * bit address space, this value should be `(1ull << 32)`.
+ */
+#define PLAT_PHY_ADDR_SPACE_SIZE       (1ull << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE      (1ull << 32)
+
 /*
  * Some data must be aligned on the biggest cache line size in the platform.
  * This is known only to the platform as it might have a combination of