ARM plat changes to enable CryptoCell integration

This patch makes the necessary changes to enable ARM platform to
successfully integrate CryptoCell during Trusted Board Boot. The
changes are as follows:

* A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select
  the CryptoCell crypto driver for Trusted Board boot.

* The TrustZone filter settings for Non Secure DRAM is modified
  to allow CryptoCell to read this memory. This is required to
  authenticate BL33 which is loaded into the Non Secure DDR.

* The CSS platforms are modified to use coherent stacks in BL1 and BL2
  when CryptoCell crypto is selected. This is because CryptoCell makes
  use of DMA to transfer data and the CryptoCell SBROM library allocates
  buffers on the stack during signature/hash verification.

Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index c7b9e89c8859eb5776c52574ef0a7be07391a7d4..047e225008b2e8e6a43bf9c86548f45968a5ecc7 100644 (file)
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -299,6 +299,12 @@ also be defined:
     Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
     FWU content certificate.
 
+*   **#define : PLAT_CRYPTOCELL_BASE**
+
+    This defines the base address of ARM® TrustZone® CryptoCell and must be
+    defined if CryptoCell crypto driver is used for Trusted Board Boot. For
+    capable ARM platforms, this driver is used if `ARM_CRYPTOCELL_INTEG` is
+    set.
 
 If the AP Firmware Updater Configuration image, BL2U is used, the following
 must also be defined:

diff --git a/docs/user-guide.md b/docs/user-guide.md
index 29691c5be9601f9f729ae508cb22ec6c22455d0f..ea2874d8fc5e8dc6d72386b652b3d5f34b91a633 100644 (file)
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -623,6 +623,11 @@ performed.
     with version 1 of the translation tables library instead of version 2. It is
     set to 0 by default, which selects version 2.
 
+*   `ARM_CRYPTOCELL_INTEG` : bool option to enable Trusted Firmware to invoke
+    ARM® TrustZone® CryptoCell functionality for Trusted Board Boot on capable
+    ARM platforms. If this option is specified, then the path to the CryptoCell
+    SBROM library must be specified via `CCSBROM_LIB_PATH` flag.
+
 For a better understanding of these options, the ARM development platform memory
 map is explained in the [Firmware Design].
 

diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index ea309547611bfef7831ad7c7b8f5df898db44cd3..5dae30ec72f12914528e72fa900c029bca22cee2 100644 (file)
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -83,6 +83,18 @@
 #define ARM_AP_TZC_DRAM1_END           (ARM_AP_TZC_DRAM1_BASE +        \
                                         ARM_AP_TZC_DRAM1_SIZE - 1)
 
+/* Define the Access permissions for Secure peripherals to NS_DRAM */
+#if ARM_CRYPTOCELL_INTEG
+/*
+ * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
+ * This is required by CryptoCell to authenticate BL33 which is loaded
+ * into the Non Secure DDR.
+ */
+#define ARM_TZC_NS_DRAM_S_ACCESS       TZC_REGION_S_RD
+#else
+#define ARM_TZC_NS_DRAM_S_ACCESS       TZC_REGION_S_NONE
+#endif
+
 
 #define ARM_NS_DRAM1_BASE              ARM_DRAM1_BASE
 #define ARM_NS_DRAM1_SIZE              (ARM_DRAM1_SIZE -               \

diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 68c38ee1c2865dd59e9fd0b70ee83b427675d1bb..ea128b6e569592b146fa4d12ee5adf4747b54b3c 100644 (file)
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -26,6 +26,9 @@
 #define PLATFORM_CORE_COUNT            (JUNO_CLUSTER0_CORE_COUNT + \
                                        JUNO_CLUSTER1_CORE_COUNT)
 
+/* Cryptocell HW Base address */
+#define PLAT_CRYPTOCELL_BASE           0x60050000
+
 /*
  * Other platform porting definitions are provided by included headers
  */

diff --git a/plat/arm/common/aarch64/arm_helpers.S b/plat/arm/common/aarch64/arm_helpers.S
index 86565f5745fbc3d9b11c0587698c07cbaac46dc5..b53e60dba151d6c2c62ee9f9b184f50a86ad1183 100644 (file)
--- a/plat/arm/common/aarch64/arm_helpers.S
+++ b/plat/arm/common/aarch64/arm_helpers.S
@@ -115,3 +115,51 @@ func arm_disable_spe
        ret
 endfunc arm_disable_spe
 #endif
+
+/*
+ * Need to use coherent stack when ARM Cryptocell is used to autheticate images
+ * since Cryptocell uses DMA to transfer data and it is not coherent with the
+ * AP CPU.
+ */
+#if ARM_CRYPTOCELL_INTEG
+#if defined(IMAGE_BL1) || defined(IMAGE_BL2)
+       .globl  plat_get_my_stack
+       .globl  plat_set_my_stack
+       .local  platform_coherent_stacks
+
+       /* -------------------------------------------------------
+        * uintptr_t plat_get_my_stack ()
+        *
+        * For cold-boot BL images, only the primary CPU needs a
+        * stack. This function returns the stack pointer for a
+        * stack allocated in coherent memory.
+        * -------------------------------------------------------
+        */
+func plat_get_my_stack
+       get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE
+       ret
+endfunc plat_get_my_stack
+
+       /* -------------------------------------------------------
+        * void plat_set_my_stack ()
+        *
+        * For cold-boot BL images, only the primary CPU needs a
+        * stack. This function sets the stack pointer to a stack
+        * allocated in coherent memory.
+        * -------------------------------------------------------
+        */
+func plat_set_my_stack
+       get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE
+       mov sp, x0
+       ret
+endfunc plat_set_my_stack
+
+       /* ----------------------------------------------------
+        * Single cpu stack in coherent memory.
+        * ----------------------------------------------------
+        */
+declare_stack platform_coherent_stacks, tzfw_coherent_mem, \
+               PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE
+
+#endif /* defined(IMAGE_BL1) || defined(IMAGE_BL2) */
+#endif /* ARM_CRYPTOCELL_INTEG */

diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 5cc1a0ac721d3ccdc456863c87623f25dcb0a422..e0b7af409752f608d96351533f4d62ea90499fb7 100644 (file)
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -94,6 +94,11 @@ LOAD_IMAGE_V2                        :=      1
 # Use generic OID definition (tbbr_oid.h)
 USE_TBBR_DEFS                  :=      1
 
+# Disable ARM Cryptocell by default
+ARM_CRYPTOCELL_INTEG           :=      0
+$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
+$(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
+
 PLAT_INCLUDES          +=      -Iinclude/common/tbbr                           \
                                -Iinclude/plat/arm/common
 
@@ -181,7 +186,11 @@ ifneq (${TRUSTED_BOARD_BOOT},0)
     TF_MBEDTLS_KEY_ALG :=      ${KEY_ALG}
 
     # We expect to locate the *.mk files under the directories specified below
+ifeq (${ARM_CRYPTOCELL_INTEG},0)
     CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk
+else
+    CRYPTO_LIB_MK := drivers/auth/cryptocell/cryptocell_crypto.mk
+endif
     IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk
 
     $(info Including ${CRYPTO_LIB_MK})

diff --git a/plat/arm/common/arm_tzc400.c b/plat/arm/common/arm_tzc400.c
index c09814e079da121179233657324d8a9ead6b61df..1d61c576fbc24136ee2a7257f02463d1ac4a7c42 100644 (file)
--- a/plat/arm/common/arm_tzc400.c
+++ b/plat/arm/common/arm_tzc400.c
@@ -34,6 +34,7 @@ void arm_tzc400_setup(void)
        tzc400_disable_filters();
 
 #ifndef EL3_PAYLOAD_BASE
+
        /* Region 0 set to no access by default */
        tzc400_configure_region0(TZC_REGION_S_NONE, 0);
 
@@ -47,13 +48,13 @@ void arm_tzc400_setup(void)
         * Apply the same configuration to given filters in the TZC. */
        tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 2,
                        ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
-                       TZC_REGION_S_NONE,
+                       ARM_TZC_NS_DRAM_S_ACCESS,
                        PLAT_ARM_TZC_NS_DEV_ACCESS);
 
        /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
        tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 3,
                        ARM_DRAM2_BASE, ARM_DRAM2_END,
-                       TZC_REGION_S_NONE,
+                       ARM_TZC_NS_DRAM_S_ACCESS,
                        PLAT_ARM_TZC_NS_DEV_ACCESS);
 #else
        /* Allow secure access only to DRAM for EL3 payloads. */

diff --git a/plat/arm/common/arm_tzc_dmc500.c b/plat/arm/common/arm_tzc_dmc500.c
index f6dc95bb0b9017abb202ea10a88fccd678ad0998..21ca4e8d54dec103a84d7f1e5023387217aa8cd0 100644 (file)
--- a/plat/arm/common/arm_tzc_dmc500.c
+++ b/plat/arm/common/arm_tzc_dmc500.c
@@ -41,14 +41,14 @@ void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data)
        tzc_dmc500_configure_region(2,
                ARM_NS_DRAM1_BASE,
                ARM_NS_DRAM1_END,
-               TZC_REGION_S_NONE,
+               ARM_TZC_NS_DRAM_S_ACCESS,
                PLAT_ARM_TZC_NS_DEV_ACCESS);
 
        /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
        tzc_dmc500_configure_region(3,
                ARM_DRAM2_BASE,
                ARM_DRAM2_END,
-               TZC_REGION_S_NONE,
+               ARM_TZC_NS_DRAM_S_ACCESS,
                PLAT_ARM_TZC_NS_DEV_ACCESS);
 #else
        /* Allow secure access only to DRAM for EL3 payloads */