This patch adds an alterative SPL version of atmel_serial_enable_clk().
This enables the usage of this driver without full clock support (in
drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code
in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
input clock. It defaults to
132096000 for ARCH_AT91 but can be set to
a different value if needed.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
configured in the device tree, and input clock frequency can
be got from the clk node.
+config SPL_UART_CLOCK
+ int "SPL fixed UART input clock"
+ depends on ATMEL_USART && SPL && !SPL_CLK
+ default 132096000 if ARCH_AT91
+ help
+ Provide a fixed clock value as input to the UART controller. This
+ might be needed on platforms which can't enable CONFIG_SPL_CLK
+ because of SPL image size restrictions.
+
config BCM283X_MU_SERIAL
bool "Support for BCM283x Mini-UART"
depends on DM_SERIAL && ARCH_BCM283X
.setbrg = atmel_serial_setbrg,
};
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
+static int atmel_serial_enable_clk(struct udevice *dev)
+{
+ struct atmel_serial_priv *priv = dev_get_priv(dev);
+
+ /* Use fixed clock value in SPL */
+ priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
+
+ return 0;
+}
+#else
static int atmel_serial_enable_clk(struct udevice *dev)
{
struct atmel_serial_priv *priv = dev_get_priv(dev);
return 0;
}
+#endif
static int atmel_serial_probe(struct udevice *dev)
{