powerpc: Fixes for instructions not using correct register naming

These macros are using integers where they could be using logical
names since they take registers.

We are going to enforce this soon, so fix these up now.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 7215cc2495df1d95a91af88471af120e98ae2656..bc3673431fde46fd76bd0311e665e8318c08fab1 100644 (file)
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -903,7 +903,7 @@ skpinv:     addi    r6,r6,1                         /* Increment */
        bne     1b                              /* If not, repeat */
 
        /* Invalidate all TLBs */
-       PPC_TLBILX_ALL(0,0)
+       PPC_TLBILX_ALL(R0,R0)
        sync
        isync
 
@@ -961,7 +961,7 @@ skpinv:     addi    r6,r6,1                         /* Increment */
        tlbwe
 
        /* Invalidate TLB1 */
-       PPC_TLBILX_ALL(0,0)
+       PPC_TLBILX_ALL(R0,R0)
        sync
        isync
 
@@ -1020,7 +1020,7 @@ skpinv:   addi    r6,r6,1                         /* Increment */
        tlbwe
 
        /* Invalidate TLB1 */
-       PPC_TLBILX_ALL(0,0)
+       PPC_TLBILX_ALL(R0,R0)
        sync
        isync
 
@@ -1138,7 +1138,7 @@ a2_tlbinit_after_iprot_flush:
        tlbwe
 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
 
-       PPC_TLBILX(0,0,0)
+       PPC_TLBILX(0,R0,R0)
        sync
        isync
 

diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index f52f9b949fd72ba7f59a345b39d2fec2e725f58b..565b78625a32a149ce4959fb9610a46a82a5e04a 100644 (file)
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -309,7 +309,7 @@ _GLOBAL(real_205_readb)
        mtmsrd  r0
        sync
        isync
-       LBZCIX(R3,0,R3)
+       LBZCIX(R3,R0,R3)
        isync
        mtmsrd  r7
        sync
@@ -324,7 +324,7 @@ _GLOBAL(real_205_writeb)
        mtmsrd  r0
        sync
        isync
-       STBCIX(R3,0,R4)
+       STBCIX(R3,R0,R4)
        isync
        mtmsrd  r7
        sync

diff --git a/arch/powerpc/lib/ldstfp.S b/arch/powerpc/lib/ldstfp.S
index 3abae6bc7b4b27571574db0db93b3e94191749f0..85aec08ab23411a98041bfee837e82a29ff2d107 100644 (file)
--- a/arch/powerpc/lib/ldstfp.S
+++ b/arch/powerpc/lib/ldstfp.S
@@ -332,7 +332,7 @@ _GLOBAL(do_lxvd2x)
        beq     cr7,1f
        STXVD2X(0,R1,R8)
 1:     li      r9,-EFAULT
-2:     LXVD2X(0,0,R4)
+2:     LXVD2X(0,R0,R4)
        li      r9,0
 3:     beq     cr7,4f
        bl      put_vsr
@@ -361,7 +361,7 @@ _GLOBAL(do_stxvd2x)
        STXVD2X(0,R1,R8)
        bl      get_vsr
 1:     li      r9,-EFAULT
-2:     STXVD2X(0,0,R4)
+2:     STXVD2X(0,R0,R4)
        li      r9,0
 3:     beq     cr7,4f
        LXVD2X(0,R1,R8)

diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 5a1285a9109f84161f65a8d500f872768e6fc4a6..75a9d14a3deaac2101667188104ae9e5a7b41d30 100644 (file)
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -266,7 +266,7 @@ BEGIN_MMU_FTR_SECTION
        andi.   r3,r3,MMUCSR0_TLBFI@l
        bne     1b
 MMU_FTR_SECTION_ELSE
-       PPC_TLBILX_ALL(0,0)
+       PPC_TLBILX_ALL(R0,R0)
 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
        msync
        isync
@@ -279,7 +279,7 @@ BEGIN_MMU_FTR_SECTION
        wrteei  0
        mfspr   r4,SPRN_MAS6    /* save MAS6 */
        mtspr   SPRN_MAS6,r3
-       PPC_TLBILX_PID(0,0)
+       PPC_TLBILX_PID(R0,R0)
        mtspr   SPRN_MAS6,r4    /* restore MAS6 */
        wrtee   r10
 MMU_FTR_SECTION_ELSE
@@ -331,7 +331,7 @@ _GLOBAL(_tlbil_pid)
        mfmsr   r10
        wrteei  0
        mtspr   SPRN_MAS6,r4
-       PPC_TLBILX_PID(0,0)
+       PPC_TLBILX_PID(R0,R0)
        wrtee   r10
        msync
        isync
@@ -343,14 +343,14 @@ _GLOBAL(_tlbil_pid_noind)
        ori     r4,r4,MAS6_SIND
        wrteei  0
        mtspr   SPRN_MAS6,r4
-       PPC_TLBILX_PID(0,0)
+       PPC_TLBILX_PID(R0,R0)
        wrtee   r10
        msync
        isync
        blr
 
 _GLOBAL(_tlbil_all)
-       PPC_TLBILX_ALL(0,0)
+       PPC_TLBILX_ALL(R0,R0)
        msync
        isync
        blr