drm/amdgpu: Fix hard hang for S/G display BOs.
authorAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Mon, 15 Jul 2019 22:04:08 +0000 (18:04 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 31 Jul 2019 04:22:41 +0000 (23:22 -0500)
HW requires for caching to be unset for scanout BO
mappings when the BO placement is in GTT memory.
Usually the flag to unset is passed from user mode
but for FB mode this was missing.

v2:
Keep all BO placement logic in amdgpu_display_supported_domains

Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

index eb3569b46c1e112bd3b4dcf8e7e442221565ac0f..430c56f9544a1d8650c5ef7ed0565e4368d17e1c 100644 (file)
@@ -139,14 +139,14 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
        mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
                                                  fb_tiled);
        domain = amdgpu_display_supported_domains(adev);
-
        height = ALIGN(mode_cmd->height, 8);
        size = mode_cmd->pitches[0] * height;
        aligned_size = ALIGN(size, PAGE_SIZE);
        ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
                                       AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
-                                      AMDGPU_GEM_CREATE_VRAM_CLEARED,
+                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |
+                                      AMDGPU_GEM_CREATE_VRAM_CLEARED        |
+                                      AMDGPU_GEM_CREATE_CPU_GTT_USWC,
                                       ttm_bo_type_kernel, NULL, &gobj);
        if (ret) {
                pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
@@ -168,7 +168,6 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
                        dev_err(adev->dev, "FB failed to set tiling flags\n");
        }
 
-
        ret = amdgpu_bo_pin(abo, domain);
        if (ret) {
                amdgpu_bo_unreserve(abo);
index 939f8305511b89ebebc2721b7ed420992311e95d..fb291366d5ade1017c36f73b3ad9320f7dc1a9e8 100644 (file)
@@ -747,7 +747,8 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
        struct amdgpu_device *adev = dev->dev_private;
        struct drm_gem_object *gobj;
        uint32_t handle;
-       u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+       u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+                   AMDGPU_GEM_CREATE_CPU_GTT_USWC;
        u32 domain;
        int r;