perf vendor events arm64: Add some missing events for Hisi hip08 L3C PMU

Add some more missing events.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linuxarm@huawei.com
Link: http://lore.kernel.org/lkml/1567612484-195727-4-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
index ca48747642e19a640e06aede6cec7ade9f1056d7..f463d0acfaefdf2a25473d2ece218d21841a2bbb 100644 (file)
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
@@ -34,4 +34,60 @@
            "PublicDescription": "l3c precharge commands",
            "Unit": "hisi_sccl,l3c",
    },
+   {
+           "EventCode": "0x20",
+           "EventName": "uncore_hisi_l3c.rd_spipe",
+           "BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
+           "PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe",
+           "Unit": "hisi_sccl,l3c",
+   },
+   {
+           "EventCode": "0x21",
+           "EventName": "uncore_hisi_l3c.wr_spipe",
+           "BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
+           "PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe",
+           "Unit": "hisi_sccl,l3c",
+   },
+   {
+           "EventCode": "0x22",
+           "EventName": "uncore_hisi_l3c.rd_hit_spipe",
+           "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",
+           "PublicDescription": "Count of the number of read lines that hits in spipe of this L3C",
+           "Unit": "hisi_sccl,l3c",
+   },
+   {
+           "EventCode": "0x23",
+           "EventName": "uncore_hisi_l3c.wr_hit_spipe",
+           "BriefDescription": "Count of the number of write lines that hits in spipe of this L3C",
+           "PublicDescription": "Count of the number of write lines that hits in spipe of this L3C",
+           "Unit": "hisi_sccl,l3c",
+   },
+   {
+           "EventCode": "0x29",
+           "EventName": "uncore_hisi_l3c.back_invalid",
+           "BriefDescription": "Count of the number of L3C back invalid operations",
+           "PublicDescription": "Count of the number of L3C back invalid operations",
+           "Unit": "hisi_sccl,l3c",
+   },
+   {
+           "EventCode": "0x40",
+           "EventName": "uncore_hisi_l3c.retry_cpu",
+           "BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations",
+           "PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations",
+           "Unit": "hisi_sccl,l3c",
+   },
+   {
+           "EventCode": "0x41",
+           "EventName": "uncore_hisi_l3c.retry_ring",
+           "BriefDescription": "Count of the number of retry that L3C suppresses the ring operations",
+           "PublicDescription": "Count of the number of retry that L3C suppresses the ring operations",
+           "Unit": "hisi_sccl,l3c",
+   },
+   {
+           "EventCode": "0x42",
+           "EventName": "uncore_hisi_l3c.prefetch_drop",
+           "BriefDescription": "Count of the number of prefetch drops from this L3C",
+           "PublicDescription": "Count of the number of prefetch drops from this L3C",
+           "Unit": "hisi_sccl,l3c",
+   },
 ]