It compiles but *doesn't* boot so it isn't enabled yet.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_ARCH_BCM4908=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CONT_SHIFT=4
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_SSBD=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_B53=y
+# CONFIG_B53_MDIO_DRIVER is not set
+# CONFIG_B53_MMAP_DRIVER is not set
+# CONFIG_B53_SERDES is not set
+# CONFIG_B53_SPI_DRIVER is not set
+# CONFIG_B53_SRAB_DRIVER is not set
+CONFIG_BCM4908_ENET=y
+CONFIG_BCM7XXX_PHY=y
+CONFIG_BCM_NET_PHYLIB=y
+CONFIG_BCM_PMB=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_PM=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_COMMON_CLK=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_REMAP=y
+CONFIG_DRM_RCAR_WRITEBACK=y
+CONFIG_DTC=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GRO_CELLS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HOLES_IN_ZONE=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BCM_UNIMAC=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_OF_PARTS_BCM4908=y
+# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPLIT_CFE_BOOTFS=y
+# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_BCM_SF2=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_NR_CPUS=4
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_PADATA=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_BRCM_USB=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RATIONAL=y
+CONFIG_REFCOUNT_FULL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SRCU=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB_SUPPORT=y
+CONFIG_VMAP_STACK=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __UNIMAC_H
+#define __UNIMAC_H
+
+#define UMAC_HD_BKP_CTRL 0x004
+#define HD_FC_EN (1 << 0)
+#define HD_FC_BKOFF_OK (1 << 1)
+#define IPG_CONFIG_RX_SHIFT 2
+#define IPG_CONFIG_RX_MASK 0x1F
+#define UMAC_CMD 0x008
+#define CMD_TX_EN (1 << 0)
+#define CMD_RX_EN (1 << 1)
+#define CMD_SPEED_10 0
+#define CMD_SPEED_100 1
+#define CMD_SPEED_1000 2
+#define CMD_SPEED_2500 3
+#define CMD_SPEED_SHIFT 2
+#define CMD_SPEED_MASK 3
+#define CMD_PROMISC (1 << 4)
+#define CMD_PAD_EN (1 << 5)
+#define CMD_CRC_FWD (1 << 6)
+#define CMD_PAUSE_FWD (1 << 7)
+#define CMD_RX_PAUSE_IGNORE (1 << 8)
+#define CMD_TX_ADDR_INS (1 << 9)
+#define CMD_HD_EN (1 << 10)
+#define CMD_SW_RESET_OLD (1 << 11)
+#define CMD_SW_RESET (1 << 13)
+#define CMD_LCL_LOOP_EN (1 << 15)
+#define CMD_AUTO_CONFIG (1 << 22)
+#define CMD_CNTL_FRM_EN (1 << 23)
+#define CMD_NO_LEN_CHK (1 << 24)
+#define CMD_RMT_LOOP_EN (1 << 25)
+#define CMD_RX_ERR_DISC (1 << 26)
+#define CMD_PRBL_EN (1 << 27)
+#define CMD_TX_PAUSE_IGNORE (1 << 28)
+#define CMD_TX_RX_EN (1 << 29)
+#define CMD_RUNT_FILTER_DIS (1 << 30)
+#define UMAC_MAC0 0x00c
+#define UMAC_MAC1 0x010
+#define UMAC_MAX_FRAME_LEN 0x014
+#define UMAC_PAUSE_QUANTA 0x018
+#define UMAC_MODE 0x044
+#define MODE_LINK_STATUS (1 << 5)
+#define UMAC_FRM_TAG0 0x048 /* outer tag */
+#define UMAC_FRM_TAG1 0x04c /* inner tag */
+#define UMAC_TX_IPG_LEN 0x05c
+#define UMAC_EEE_CTRL 0x064
+#define EN_LPI_RX_PAUSE (1 << 0)
+#define EN_LPI_TX_PFC (1 << 1)
+#define EN_LPI_TX_PAUSE (1 << 2)
+#define EEE_EN (1 << 3)
+#define RX_FIFO_CHECK (1 << 4)
+#define EEE_TX_CLK_DIS (1 << 5)
+#define DIS_EEE_10M (1 << 6)
+#define LP_IDLE_PREDICTION_MODE (1 << 7)
+#define UMAC_EEE_LPI_TIMER 0x068
+#define UMAC_EEE_WAKE_TIMER 0x06C
+#define UMAC_EEE_REF_COUNT 0x070
+#define EEE_REFERENCE_COUNT_MASK 0xffff
+#define UMAC_RX_IPG_INV 0x078
+#define UMAC_MACSEC_PROG_TX_CRC 0x310
+#define UMAC_MACSEC_CTRL 0x314
+#define UMAC_PAUSE_CTRL 0x330
+#define UMAC_TX_FLUSH 0x334
+#define UMAC_RX_FIFO_STATUS 0x338
+#define UMAC_TX_FIFO_STATUS 0x33c
+
+#endif
--- /dev/null
+From 2f8913a7b17efd3a116825160a2d3a6610444587 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 12 Nov 2020 16:08:31 +0100
+Subject: [PATCH] dt-bindings: arm: bcm: document BCM4908 bindings
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 is a new family that includes BCM4906, BCM4908 and BCM49408.
+It's mostly used in home routers and often replaces Northstar in vendors
+portfolio.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../bindings/arm/bcm/brcm,bcm4908.yaml | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
+@@ -0,0 +1,38 @@
++# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4908.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Broadcom BCM4908 device tree bindings
++
++description:
++ Broadcom BCM4906 / BCM4908 / BCM49408 Wi-Fi/network SoCs with Brahma CPUs.
++
++maintainers:
++ - Rafał Miłecki <rafal@milecki.pl>
++
++properties:
++ $nodename:
++ const: '/'
++ compatible:
++ oneOf:
++ - description: BCM4906 based boards
++ items:
++ - const: brcm,bcm4906
++ - const: brcm,bcm4908
++
++ - description: BCM4908 based boards
++ items:
++ - enum:
++ - asus,gt-ac5300
++ - const: brcm,bcm4908
++
++ - description: BCM49408 based boards
++ items:
++ - const: brcm,bcm49408
++ - const: brcm,bcm4908
++
++additionalProperties: true
++
++...
--- /dev/null
+From 2961f69f151c0a6771f55cef46398fe49ca20902 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 12 Nov 2020 16:08:32 +0100
+Subject: [PATCH] arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early
+ DTS files
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+They don't descibe hardware fully yet but it's enough to boot a system.
+
+Some missing blocks:
+1. PMC (Power Management Controller?)
+2. Ethernet
+3. Crypto
+4. Thermal
+
+Asus DTS is missing defining full NAND partitions layout and buttons.
+
+Further changes will fill those gaps as soon as required bindings will
+be found / tested / added.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/Makefile | 1 +
+ arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 2 +
+ .../bcm4908/bcm4908-asus-gt-ac5300.dts | 66 +++++++
+ .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 187 ++++++++++++++++++
+ 4 files changed, 256 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+
+--- a/arch/arm64/boot/dts/broadcom/Makefile
++++ b/arch/arm64/boot/dts/broadcom/Makefile
+@@ -5,5 +5,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp
+ bcm2837-rpi-3-b-plus.dtb \
+ bcm2837-rpi-cm3-io3.dtb
+
++subdir-y += bcm4908
+ subdir-y += northstar2
+ subdir-y += stingray
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+@@ -0,0 +1,66 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++#include "bcm4908.dtsi"
++
++/ {
++ compatible = "asus,gt-ac5300", "brcm,bcm4908";
++ model = "Asus GT-AC5300";
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x00 0x00 0x00 0x40000000>;
++ };
++
++ gpio-keys-polled {
++ compatible = "gpio-keys-polled";
++ poll-interval = <100>;
++
++ wifi {
++ label = "WiFi";
++ linux,code = <KEY_RFKILL>;
++ gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
++ };
++
++ wps {
++ label = "WPS";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
++ };
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
++ };
++
++ brightness {
++ label = "LEDs";
++ linux,code = <KEY_BRIGHTNESS_ZERO>;
++ gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&nandcs {
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++ nand-on-flash-bbt;
++ brcm,nand-has-wp;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "cferom";
++ reg = <0x0 0x100000>;
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -0,0 +1,187 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++/dts-v1/;
++
++/ {
++ interrupt-parent = <&gic>;
++
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu0: cpu@0 {
++ device_type = "cpu";
++ compatible = "brcm,brahma-b53";
++ reg = <0x0>;
++ next-level-cache = <&l2>;
++ };
++
++ cpu1: cpu@1 {
++ device_type = "cpu";
++ compatible = "brcm,brahma-b53";
++ reg = <0x1>;
++ enable-method = "spin-table";
++ cpu-release-addr = <0x0 0xfff8>;
++ next-level-cache = <&l2>;
++ };
++
++ cpu2: cpu@2 {
++ device_type = "cpu";
++ compatible = "brcm,brahma-b53";
++ reg = <0x2>;
++ enable-method = "spin-table";
++ cpu-release-addr = <0x0 0xfff8>;
++ next-level-cache = <&l2>;
++ };
++
++ cpu3: cpu@3 {
++ device_type = "cpu";
++ compatible = "brcm,brahma-b53";
++ reg = <0x3>;
++ enable-method = "spin-table";
++ cpu-release-addr = <0x0 0xfff8>;
++ next-level-cache = <&l2>;
++ };
++
++ l2: l2-cache0 {
++ compatible = "cache";
++ };
++ };
++
++ axi@81000000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x00 0x00 0x81000000 0x4000>;
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0x1000 0x1000>,
++ <0x2000 0x2000>;
++ };
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
++ pmu {
++ compatible = "arm,cortex-a53-pmu";
++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
++ };
++
++ clocks {
++ periph_clk: periph_clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <50000000>;
++ clock-output-names = "periph";
++ };
++ };
++
++ soc {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x00 0x00 0x80000000 0x10000>;
++
++ usb@c300 {
++ compatible = "generic-ehci";
++ reg = <0xc300 0x100>;
++ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ };
++
++ usb@c400 {
++ compatible = "generic-ohci";
++ reg = <0xc400 0x100>;
++ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ };
++
++ usb@d000 {
++ compatible = "generic-xhci";
++ reg = <0xd000 0x8c8>;
++ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ };
++ };
++
++ bus@ff800000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x00 0x00 0xff800000 0x3000>;
++
++ timer: timer@400 {
++ compatible = "brcm,bcm6328-timer", "syscon";
++ reg = <0x400 0x3c>;
++ };
++
++ gpio0: gpio-controller@500 {
++ compatible = "brcm,bcm6345-gpio";
++ reg-names = "dirout", "dat";
++ reg = <0x500 0x28>, <0x528 0x28>;
++
++ #gpio-cells = <2>;
++ gpio-controller;
++ };
++
++ uart0: serial@640 {
++ compatible = "brcm,bcm6345-uart";
++ reg = <0x640 0x18>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&periph_clk>;
++ clock-names = "periph";
++ status = "okay";
++ };
++
++ nand@1800 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
++ reg = <0x1800 0x600>, <0x2000 0x10>;
++ reg-names = "nand", "nand-int-base";
++ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "nand";
++ status = "okay";
++
++ nandcs: nandcs@0 {
++ compatible = "brcm,nandcs";
++ reg = <0>;
++ };
++ };
++
++ reboot {
++ compatible = "syscon-reboot";
++ regmap = <&timer>;
++ offset = <0x34>;
++ mask = <1>;
++ };
++ };
++};
--- /dev/null
+From dccb22d078ebd098115e4f66bde1ee2249c8640b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 12 Nov 2020 16:08:30 +0100
+Subject: [PATCH] arm64: add config for Broadcom BCM4908 SoCs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add ARCH_BCM4908 config that can be used for compiling DTS files.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/Kconfig.platforms | 8 ++++++++
+ arch/arm64/configs/defconfig | 1 +
+ 2 files changed, 9 insertions(+)
+
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -43,6 +43,14 @@ config ARCH_BCM2835
+ This enables support for the Broadcom BCM2837 and BCM2711 SoC.
+ These SoCs are used in the Raspberry Pi 3 and 4 devices.
+
++config ARCH_BCM4908
++ bool "Broadcom BCM4908 family"
++ select GPIOLIB
++ help
++ This enables support for the Broadcom BCM4906, BCM4908 and
++ BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be
++ found in home routers.
++
+ config ARCH_BCM_IPROC
+ bool "Broadcom iProc SoC Family"
+ select COMMON_CLK_IPROC
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -32,6 +32,7 @@ CONFIG_ARCH_AGILEX=y
+ CONFIG_ARCH_SUNXI=y
+ CONFIG_ARCH_ALPINE=y
+ CONFIG_ARCH_BCM2835=y
++CONFIG_ARCH_BCM4908=y
+ CONFIG_ARCH_BCM_IPROC=y
+ CONFIG_ARCH_BERLIN=y
+ CONFIG_ARCH_BRCMSTB=y
--- /dev/null
+From 3a5da4f54801ac42837a0b3151fa8285e01e8b0e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 8 Dec 2020 08:03:03 +0100
+Subject: [PATCH] dt-bindings: arm: bcm: document Netgear R8000P binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's a BCM4906 based device.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
++++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
+@@ -19,6 +19,8 @@ properties:
+ oneOf:
+ - description: BCM4906 based boards
+ items:
++ - enum:
++ - netgear,r8000p
+ - const: brcm,bcm4906
+ - const: brcm,bcm4908
+
--- /dev/null
+From c8b404fb05dcfadff477e49b7ea6b500e015f101 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 8 Dec 2020 08:03:04 +0100
+Subject: [PATCH 2/4] arm64: dts: broadcom: bcm4908: add BCM4906 Netgear R8000P
+ DTS files
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Netgear R8000P is home router based on BCM4906 that is a cheaper variant
+of BCM4908 (e.g. 2 cores instead of 4).
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 1 +
+ .../bcm4908/bcm4906-netgear-r8000p.dts | 52 +++++++++++++++++++
+ .../boot/dts/broadcom/bcm4908/bcm4906.dtsi | 18 +++++++
+ 3 files changed, 71 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb
+ dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
+@@ -0,0 +1,52 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++
++#include "bcm4906.dtsi"
++
++/ {
++ compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908";
++ model = "Netgear R8000P";
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x00 0x00 0x00 0x20000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ wps {
++ function = LED_FUNCTION_WPS;
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&nandcs {
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++ nand-on-flash-bbt;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "cferom";
++ reg = <0x0 0x100000>;
++ };
++
++ partition@100000 {
++ label = "firmware";
++ reg = <0x100000 0x4400000>;
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi
+@@ -0,0 +1,18 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++#include "bcm4908.dtsi"
++
++/ {
++ cpus {
++ /delete-node/ cpu@2;
++
++ /delete-node/ cpu@3;
++ };
++
++ pmu {
++ compatible = "arm,cortex-a53-pmu";
++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&cpu0>, <&cpu1>;
++ };
++};
--- /dev/null
+From 56098be85d19cd56b59d7b3854ea035cc8cb9e95 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 8 Dec 2020 11:49:50 +0100
+Subject: [PATCH 3/4] arm64: dts: broadcom: bcm4908: use proper NAND binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 has controller that needs different IRQ handling just like the
+BCM63138. Describe it properly.
+
+On Linux this change fixes:
+brcmstb_nand ff801800.nand: timeout waiting for command 0x9
+brcmstb_nand ff801800.nand: intfc status d0000000
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -164,7 +164,7 @@
+ nand@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+- compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
++ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+ reg = <0x1800 0x600>, <0x2000 0x10>;
+ reg-names = "nand", "nand-int-base";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
--- /dev/null
+From 1b88c6ed26a1aa1d68d1661404e6e939709ff530 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 10 Dec 2020 08:21:54 +0100
+Subject: [PATCH 4/4] arm64: dts: broadcom: bcm4908: describe PCIe reset
+ controller
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reset controller is a single register in the Broadcom's MISC block.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -177,6 +177,21 @@
+ };
+ };
+
++ misc@2600 {
++ compatible = "brcm,misc", "simple-mfd";
++ reg = <0x2600 0xe4>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x00 0x2600 0xe4>;
++
++ reset-controller@2644 {
++ compatible = "brcm,bcm4908-misc-pcie-reset";
++ reg = <0x44 0x04>;
++ #reset-cells = <1>;
++ };
++ };
++
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&timer>;
--- /dev/null
+From 527a3ac9bdf81da4b7160ce3cea57f28a0e5eb64 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 13 Jan 2021 12:14:06 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe internal switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 has internal switch with 5 GPHYs. Ports 0 - 3 are always
+connected to the internal PHYs. Remaining ports depend on device setup.
+
+Asus GT-AC5300 has an extra switch with its PHYs accessible using the
+internal MDIO.
+
+CPU port and Ethernet interface remain to be documented.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../bcm4908/bcm4908-asus-gt-ac5300.dts | 51 +++++++++++
+ .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 85 ++++++++++++++++++-
+ 2 files changed, 135 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+@@ -44,6 +44,57 @@
+ };
+ };
+
++&ports {
++ port@0 {
++ label = "lan2";
++ };
++
++ port@1 {
++ label = "lan1";
++ };
++
++ port@2 {
++ label = "lan6";
++ };
++
++ port@3 {
++ label = "lan5";
++ };
++
++ /* External BCM53134S switch */
++ port@7 {
++ label = "sw";
++ reg = <7>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++};
++
++&mdio {
++ /* lan8 */
++ ethernet-phy@0 {
++ reg = <0>;
++ };
++
++ /* lan7 */
++ ethernet-phy@1 {
++ reg = <1>;
++ };
++
++ /* lan4 */
++ ethernet-phy@2 {
++ reg = <2>;
++ };
++
++ /* lan3 */
++ ethernet-phy@3 {
++ reg = <3>;
++ };
++};
++
+ &nandcs {
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -108,7 +108,7 @@
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+- ranges = <0x00 0x00 0x80000000 0x10000>;
++ ranges = <0x00 0x00 0x80000000 0xd0000>;
+
+ usb@c300 {
+ compatible = "generic-ehci";
+@@ -130,6 +130,89 @@
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
++
++ ethernet-switch@80000 {
++ compatible = "simple-bus";
++ #size-cells = <1>;
++ #address-cells = <1>;
++ ranges = <0 0x80000 0x50000>;
++
++ ethernet-switch@0 {
++ compatible = "brcm,bcm4908-switch";
++ reg = <0x0 0x40000>,
++ <0x40000 0x110>,
++ <0x40340 0x30>,
++ <0x40380 0x30>,
++ <0x40600 0x34>,
++ <0x40800 0x208>;
++ reg-names = "core", "reg", "intrl2_0",
++ "intrl2_1", "fcb", "acb";
++ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++ brcm,num-gphy = <5>;
++ brcm,num-rgmii-ports = <2>;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ports: ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ phy-mode = "internal";
++ phy-handle = <&phy8>;
++ };
++
++ port@1 {
++ reg = <1>;
++ phy-mode = "internal";
++ phy-handle = <&phy9>;
++ };
++
++ port@2 {
++ reg = <2>;
++ phy-mode = "internal";
++ phy-handle = <&phy10>;
++ };
++
++ port@3 {
++ reg = <3>;
++ phy-mode = "internal";
++ phy-handle = <&phy11>;
++ };
++ };
++ };
++
++ mdio: mdio@405c0 {
++ compatible = "brcm,unimac-mdio";
++ reg = <0x405c0 0x8>;
++ reg-names = "mdio";
++ #size-cells = <0>;
++ #address-cells = <1>;
++
++ phy8: ethernet-phy@8 {
++ reg = <8>;
++ };
++
++ phy9: ethernet-phy@9 {
++ reg = <9>;
++ };
++
++ phy10: ethernet-phy@a {
++ reg = <10>;
++ };
++
++ phy11: ethernet-phy@b {
++ reg = <11>;
++ };
++
++ phy12: ethernet-phy@c {
++ reg = <12>;
++ };
++ };
++ };
+ };
+
+ bus@ff800000 {
--- /dev/null
+From edcf90801c8e58bd6306d85a4e714a6f09f452df Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 13 Jan 2021 12:15:47 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe PMB block
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+PMB (Power Management Bus) controls powering connected devices (e.g.
+PCIe, USB, SATA). In BCM4908 it's a part of the PROCMON block.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -108,7 +108,7 @@
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+- ranges = <0x00 0x00 0x80000000 0xd0000>;
++ ranges = <0x00 0x00 0x80000000 0x281000>;
+
+ usb@c300 {
+ compatible = "generic-ehci";
+@@ -213,6 +213,21 @@
+ };
+ };
+ };
++
++ procmon: syscon@280000 {
++ compatible = "simple-bus";
++ reg = <0x280000 0x1000>;
++ ranges;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ power-controller@2800c0 {
++ compatible = "brcm,bcm4908-pmb";
++ reg = <0x2800c0 0x40>;
++ #power-domain-cells = <1>;
++ };
++ };
+ };
+
+ bus@ff800000 {
--- /dev/null
+From 3c321ba794ca6383a4aa68ea803e18cc6ad44412 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 19 Feb 2021 06:50:26 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe USB PHY
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 uses slightly modified STB family USB PHY. It handles OHCI/EHCI
+and XHCI. It requires powering up using the PMB.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../bcm4908/bcm4906-netgear-r8000p.dts | 17 +++++++++++++
+ .../bcm4908/bcm4908-asus-gt-ac5300.dts | 17 +++++++++++++
+ .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 25 ++++++++++++++++---
+ 3 files changed, 55 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
+@@ -26,6 +26,23 @@
+ };
+ };
+
++&usb_phy {
++ brcm,ioc = <1>;
++ status = "okay";
++};
++
++&ehci {
++ status = "okay";
++};
++
++&ohci {
++ status = "okay";
++};
++
++&xhci {
++ status = "okay";
++};
++
+ &nandcs {
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+@@ -44,6 +44,23 @@
+ };
+ };
+
++&usb_phy {
++ brcm,ioc = <1>;
++ status = "okay";
++};
++
++&ehci {
++ status = "okay";
++};
++
++&ohci {
++ status = "okay";
++};
++
++&xhci {
++ status = "okay";
++};
++
+ &ports {
+ port@0 {
+ label = "lan2";
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -2,6 +2,8 @@
+
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/phy/phy.h>
++#include <dt-bindings/soc/bcm-pmb.h>
+
+ /dts-v1/;
+
+@@ -110,24 +112,39 @@
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x80000000 0x281000>;
+
+- usb@c300 {
++ usb_phy: usb-phy@c200 {
++ compatible = "brcm,bcm4908-usb-phy";
++ reg = <0xc200 0x100>;
++ reg-names = "ctrl";
++ power-domains = <&pmb BCM_PMB_HOST_USB>;
++ dr_mode = "host";
++ brcm,has-xhci;
++ brcm,has-eohci;
++ #phy-cells = <1>;
++ status = "disabled";
++ };
++
++ ehci: usb@c300 {
+ compatible = "generic-ehci";
+ reg = <0xc300 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb_phy PHY_TYPE_USB2>;
+ status = "disabled";
+ };
+
+- usb@c400 {
++ ohci: usb@c400 {
+ compatible = "generic-ohci";
+ reg = <0xc400 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb_phy PHY_TYPE_USB2>;
+ status = "disabled";
+ };
+
+- usb@d000 {
++ xhci: usb@d000 {
+ compatible = "generic-xhci";
+ reg = <0xd000 0x8c8>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb_phy PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+@@ -222,7 +239,7 @@
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+- power-controller@2800c0 {
++ pmb: power-controller@2800c0 {
+ compatible = "brcm,bcm4908-pmb";
+ reg = <0x2800c0 0x40>;
+ #power-domain-cells = <1>;
--- /dev/null
+From b1bbe48eec190b6a35f400c5a3ec6b0fc8fc3fe6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 19 Feb 2021 06:50:27 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe Ethernet controller
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 SoCs have an integrated Ethernet controller.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -112,6 +112,14 @@
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x80000000 0x281000>;
+
++ enet: ethernet@2000 {
++ compatible = "brcm,bcm4908-enet";
++ reg = <0x2000 0x1000>;
++
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "rx";
++ };
++
+ usb_phy: usb-phy@c200 {
+ compatible = "brcm,bcm4908-usb-phy";
+ reg = <0xc200 0x100>;
+@@ -199,6 +207,17 @@
+ phy-mode = "internal";
+ phy-handle = <&phy11>;
+ };
++
++ port@8 {
++ reg = <8>;
++ phy-mode = "internal";
++ ethernet = <&enet>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
+ };
+ };
+
--- /dev/null
+From 406e98afffe975982f63ea5d21bf9a47a81b56ee Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 19 Feb 2021 06:50:28 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe Netgear R8000P switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+R8000P model has 4 LAN ports and 1 WAN port.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../bcm4908/bcm4906-netgear-r8000p.dts | 25 +++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
+@@ -43,6 +43,31 @@
+ status = "okay";
+ };
+
++&ports {
++ port@0 {
++ label = "lan4";
++ };
++
++ port@1 {
++ label = "lan3";
++ };
++
++ port@2 {
++ label = "lan2";
++ };
++
++ port@3 {
++ label = "lan1";
++ };
++
++ port@7 {
++ reg = <7>;
++ phy-mode = "internal";
++ phy-handle = <&phy12>;
++ label = "wan";
++ };
++};
++
+ &nandcs {
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
--- /dev/null
+From 6224415c0389ba6661825746312163a64ece8f3a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 19 Feb 2021 06:50:29 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining Netgear R8000P
+ LEDs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are a few more GPIO connected LEDs there didn't get described
+initially.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../bcm4908/bcm4906-netgear-r8000p.dts | 50 ++++++++++++++++++-
+ 1 file changed, 49 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
+@@ -18,11 +18,59 @@
+ leds {
+ compatible = "gpio-leds";
+
+- wps {
++ led-power-white {
++ function = LED_FUNCTION_POWER;
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
++ };
++
++ led-power-amber {
++ function = LED_FUNCTION_POWER;
++ color = <LED_COLOR_ID_AMBER>;
++ gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
++ };
++
++ led-wps {
+ function = LED_FUNCTION_WPS;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+ };
++
++ led-2ghz {
++ function = "2ghz";
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
++ };
++
++ led-5ghz-1 {
++ function = "5ghz-1";
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
++ };
++
++ led-5ghz-2 {
++ function = "5ghz-2";
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
++ };
++
++ led-usb2 {
++ function = "usb2";
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
++ };
++
++ led-usb3 {
++ function = "usb3";
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
++ };
++
++ led-wifi {
++ function = "wifi";
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpio0 56 GPIO_ACTIVE_LOW>;
++ };
+ };
+ };
+
--- /dev/null
+From cbaca2c467dc25a163107e14a53b7925214eab17 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 19 Feb 2021 06:50:30 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe firmware partitions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 bootloader supports multiple firmware partitions and has its own
+bindings defined for them.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts | 1 +
+ .../dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 12 +++++++++++-
+ 2 files changed, 12 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
+@@ -135,6 +135,7 @@
+ };
+
+ partition@100000 {
++ compatible = "brcm,bcm4908-firmware";
+ label = "firmware";
+ reg = <0x100000 0x4400000>;
+ };
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+@@ -122,7 +122,7 @@
+ #size-cells = <0>;
+
+ partitions {
+- compatible = "fixed-partitions";
++ compatible = "brcm,bcm4908-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+@@ -130,5 +130,15 @@
+ label = "cferom";
+ reg = <0x0 0x100000>;
+ };
++
++ partition@100000 {
++ compatible = "brcm,bcm4908-firmware";
++ reg = <0x100000 0x5700000>;
++ };
++
++ partition@5800000 {
++ compatible = "brcm,bcm4908-firmware";
++ reg = <0x5800000 0x5700000>;
++ };
+ };
+ };
--- /dev/null
+From a348ff97ffb840b9d74b0e64b3e0e6002187d224 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 9 Mar 2021 19:44:09 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: fix switch parent node name
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Ethernet switch and MDIO are grouped using "simple-bus". It's not
+allowed to use "ethernet-switch" node name as it isn't a switch. Replace
+it with "bus".
+
+Fixes: 527a3ac9bdf8 ("arm64: dts: broadcom: bcm4908: describe internal switch")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -156,7 +156,7 @@
+ status = "disabled";
+ };
+
+- ethernet-switch@80000 {
++ bus@80000 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
--- /dev/null
+From b3de2a12d1a61d90a4d86c9840acc7d05066137f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 10 Mar 2021 08:46:02 +0100
+Subject: [PATCH] dt-bindings: arm: bcm: document TP-Link Archer C2300 binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+One more BCM4906 based device.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
++++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
+@@ -21,6 +21,7 @@ properties:
+ items:
+ - enum:
+ - netgear,r8000p
++ - tplink,archer-c2300-v1
+ - const: brcm,bcm4906
+ - const: brcm,bcm4908
+
--- /dev/null
+From 6a30934a5470a0ce7ea32b0c6b600accfae94b1a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 10 Mar 2021 08:46:03 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add TP-Link Archer C2300 V1
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Archer C2300 V1 is a home router based on the BCM4906 (2 CPU cores). It
+has 512 MiB of RAM, NAND flash, USB 2.0 and USB 3.0 ports, 4 LAN ports,
+1 WAN port.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 1 +
+ .../bcm4906-tplink-archer-c2300-v1.dts | 182 ++++++++++++++++++
+ 2 files changed, 183 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
+@@ -1,3 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0
+ dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb
++dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb
+ dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
+@@ -0,0 +1,182 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++
++#include "bcm4906.dtsi"
++
++/ {
++ compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908";
++ model = "TP-Link Archer C2300 V1";
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x00 0x00 0x00 0x20000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led-power {
++ function = LED_FUNCTION_POWER;
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
++ };
++
++ led-2ghz {
++ function = "2ghz";
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
++ };
++
++ led-5ghz {
++ function = "5ghz";
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
++ };
++
++ led-wan-amber {
++ function = LED_FUNCTION_WAN;
++ color = <LED_COLOR_ID_AMBER>;
++ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
++ };
++
++ led-wan-blue {
++ function = LED_FUNCTION_WAN;
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
++ };
++
++ led-lan {
++ function = LED_FUNCTION_LAN;
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
++ };
++
++ led-wps {
++ function = LED_FUNCTION_WPS;
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
++ };
++
++ led-usb2 {
++ function = "usb2";
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
++ };
++
++ led-usb3 {
++ function = "usbd3";
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
++ };
++
++ led-brightness {
++ function = LED_FUNCTION_BACKLIGHT;
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ gpio-keys-polled {
++ compatible = "gpio-keys-polled";
++ poll-interval = <100>;
++
++ brightness {
++ label = "LEDs";
++ linux,code = <KEY_BRIGHTNESS_ZERO>;
++ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
++ };
++
++ wps {
++ label = "WPS";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
++ };
++
++ wifi {
++ label = "WiFi";
++ linux,code = <KEY_RFKILL>;
++ gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
++ };
++
++ restart {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&usb_phy {
++ brcm,ioc = <1>;
++ status = "okay";
++};
++
++&ehci {
++ status = "okay";
++};
++
++&ohci {
++ status = "okay";
++};
++
++&xhci {
++ status = "okay";
++};
++
++&ports {
++ port@0 {
++ label = "lan4";
++ };
++
++ port@1 {
++ label = "lan3";
++ };
++
++ port@2 {
++ label = "lan2";
++ };
++
++ port@3 {
++ label = "lan1";
++ };
++
++ port@7 {
++ reg = <7>;
++ phy-mode = "internal";
++ phy-handle = <&phy12>;
++ label = "wan";
++ };
++};
++
++&nandcs {
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++ nand-on-flash-bbt;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ partitions {
++ compatible = "brcm,bcm4908-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "cferom";
++ reg = <0x0 0x100000>;
++ };
++
++ partition@100000 {
++ compatible = "brcm,bcm4908-firmware";
++ reg = <0x100000 0x3900000>;
++ };
++
++ partition@5800000 {
++ compatible = "brcm,bcm4908-firmware";
++ reg = <0x3a00000 0x3900000>;
++ };
++ };
++};
--- /dev/null
+From 5ccb9f9cf05bbd729430c6d6d30d40c96a15c56a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 12 Mar 2021 12:01:20 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: set Asus GT-AC5300 port 7 PHY
+ mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Port 7 is connected to the external BCM53134S switch using RGMII.
+
+Fixes: 527a3ac9bdf8 ("arm64: dts: broadcom: bcm4908: describe internal switch")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+@@ -82,6 +82,7 @@
+ port@7 {
+ label = "sw";
+ reg = <7>;
++ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
--- /dev/null
+From 5337af7918bedde9713cd223ce5df74b3d6c7d7a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 17 Mar 2021 09:16:31 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Ethernet TX irq
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This hardware supports two interrupts, one per DMA channel (RX and TX).
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -116,8 +116,9 @@
+ compatible = "brcm,bcm4908-enet";
+ reg = <0x2000 0x1000>;
+
+- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "rx";
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "rx", "tx";
+ };
+
+ usb_phy: usb-phy@c200 {
--- /dev/null
+From 9f01f5cdb548352418b34ce77db02a560fe2913b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 29 Mar 2021 17:45:14 +0200
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Ethernet MAC addr
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On most BCM4908 devices MAC address can be read from the bootloader
+binary section containing device settings. Use NVMEM to describe that.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../broadcom/bcm4908/bcm4906-netgear-r8000p.dts | 14 ++++++++++++++
+ .../broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 14 ++++++++++++++
+ 2 files changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
+@@ -74,6 +74,11 @@
+ };
+ };
+
++&enet {
++ nvmem-cells = <&base_mac_addr>;
++ nvmem-cell-names = "mac-address";
++};
++
+ &usb_phy {
+ brcm,ioc = <1>;
+ status = "okay";
+@@ -130,8 +135,17 @@
+ #size-cells = <1>;
+
+ partition@0 {
++ compatible = "nvmem-cells";
+ label = "cferom";
+ reg = <0x0 0x100000>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x0 0x100000>;
++
++ base_mac_addr: mac@106a0 {
++ reg = <0x106a0 0x6>;
++ };
+ };
+
+ partition@100000 {
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+@@ -44,6 +44,11 @@
+ };
+ };
+
++&enet {
++ nvmem-cells = <&base_mac_addr>;
++ nvmem-cell-names = "mac-address";
++};
++
+ &usb_phy {
+ brcm,ioc = <1>;
+ status = "okay";
+@@ -128,8 +133,17 @@
+ #size-cells = <1>;
+
+ partition@0 {
++ compatible = "nvmem-cells";
+ label = "cferom";
+ reg = <0x0 0x100000>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x0 0x100000>;
++
++ base_mac_addr: mac@106a0 {
++ reg = <0x106a0 0x6>;
++ };
+ };
+
+ partition@100000 {
--- /dev/null
+From 73b7a6047971aa6ce4a70fc4901964d14f077171 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 6 Jan 2021 22:32:02 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: support BCM4908's integrated switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 family SoCs come with integrated Starfighter 2 switch. Its
+registers layout it a mix of BCM7278 and BCM7445. It has 5 integrated
+PHYs and 8 ports. It also supports RGMII and SerDes.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20210106213202.17459-3-zajec5@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/b53/b53_common.c | 14 +++++++++++++
+ drivers/net/dsa/b53/b53_priv.h | 1 +
+ drivers/net/dsa/bcm_sf2.c | 36 +++++++++++++++++++++++++++++---
+ drivers/net/dsa/bcm_sf2_regs.h | 1 +
+ 4 files changed, 49 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/dsa/b53/b53_common.c
++++ b/drivers/net/dsa/b53/b53_common.c
+@@ -2493,6 +2493,22 @@ static const struct b53_chip_data b53_sw
+ .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
+ .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
+ },
++ /* Starfighter 2 */
++ {
++ .chip_id = BCM4908_DEVICE_ID,
++ .dev_name = "BCM4908",
++ .vlans = 4096,
++ .enabled_ports = 0x1bf,
++#if 0
++ .arl_bins = 4,
++ .arl_buckets = 256,
++#endif
++ .cpu_port = 8, /* TODO: ports 4, 5, 8 */
++ .vta_regs = B53_VTA_REGS,
++ .duplex_reg = B53_DUPLEX_STAT_GE,
++ .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
++ .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
++ },
+ {
+ .chip_id = BCM7445_DEVICE_ID,
+ .dev_name = "BCM7445",
+--- a/drivers/net/dsa/b53/b53_priv.h
++++ b/drivers/net/dsa/b53/b53_priv.h
+@@ -64,6 +64,7 @@ struct b53_io_ops {
+ #define B53_INVALID_LANE 0xff
+
+ enum {
++ BCM4908_DEVICE_ID = 0x4908,
+ BCM5325_DEVICE_ID = 0x25,
+ BCM5365_DEVICE_ID = 0x65,
+ BCM5389_DEVICE_ID = 0x89,
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -105,7 +105,8 @@ static void bcm_sf2_imp_setup(struct dsa
+ b53_brcm_hdr_setup(ds, port);
+
+ if (port == 8) {
+- if (priv->type == BCM7445_DEVICE_ID)
++ if (priv->type == BCM4908_DEVICE_ID ||
++ priv->type == BCM7445_DEVICE_ID)
+ offset = CORE_STS_OVERRIDE_IMP;
+ else
+ offset = CORE_STS_OVERRIDE_IMP2;
+@@ -708,7 +709,8 @@ static void bcm_sf2_sw_mac_link_down(str
+ u32 reg, offset;
+
+ if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
+- if (priv->type == BCM7445_DEVICE_ID)
++ if (priv->type == BCM4908_DEVICE_ID ||
++ priv->type == BCM7445_DEVICE_ID)
+ offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
+ else
+ offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
+@@ -735,7 +737,8 @@ static void bcm_sf2_sw_mac_link_up(struc
+ bcm_sf2_sw_mac_link_set(ds, port, interface, true);
+
+ if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
+- if (priv->type == BCM7445_DEVICE_ID)
++ if (priv->type == BCM4908_DEVICE_ID ||
++ priv->type == BCM7445_DEVICE_ID)
+ offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
+ else
+ offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
+@@ -1128,6 +1131,30 @@ struct bcm_sf2_of_data {
+ unsigned int num_cfp_rules;
+ };
+
++static const u16 bcm_sf2_4908_reg_offsets[] = {
++ [REG_SWITCH_CNTRL] = 0x00,
++ [REG_SWITCH_STATUS] = 0x04,
++ [REG_DIR_DATA_WRITE] = 0x08,
++ [REG_DIR_DATA_READ] = 0x0c,
++ [REG_SWITCH_REVISION] = 0x10,
++ [REG_PHY_REVISION] = 0x14,
++ [REG_SPHY_CNTRL] = 0x24,
++ [REG_CROSSBAR] = 0xc8,
++ [REG_RGMII_0_CNTRL] = 0xe0,
++ [REG_RGMII_1_CNTRL] = 0xec,
++ [REG_RGMII_2_CNTRL] = 0xf8,
++ [REG_LED_0_CNTRL] = 0x40,
++ [REG_LED_1_CNTRL] = 0x4c,
++ [REG_LED_2_CNTRL] = 0x58,
++};
++
++static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
++ .type = BCM4908_DEVICE_ID,
++ .core_reg_align = 0,
++ .reg_offsets = bcm_sf2_4908_reg_offsets,
++ .num_cfp_rules = 0, /* FIXME */
++};
++
+ /* Register offsets for the SWITCH_REG_* block */
+ static const u16 bcm_sf2_7445_reg_offsets[] = {
+ [REG_SWITCH_CNTRL] = 0x00,
+@@ -1176,6 +1203,9 @@ static const struct bcm_sf2_of_data bcm_
+ };
+
+ static const struct of_device_id bcm_sf2_of_match[] = {
++ { .compatible = "brcm,bcm4908-switch",
++ .data = &bcm_sf2_4908_data
++ },
+ { .compatible = "brcm,bcm7445-switch-v4.0",
+ .data = &bcm_sf2_7445_data
+ },
+--- a/drivers/net/dsa/bcm_sf2_regs.h
++++ b/drivers/net/dsa/bcm_sf2_regs.h
+@@ -17,6 +17,7 @@ enum bcm_sf2_reg_offs {
+ REG_SWITCH_REVISION,
+ REG_PHY_REVISION,
+ REG_SPHY_CNTRL,
++ REG_CROSSBAR,
+ REG_RGMII_0_CNTRL,
+ REG_RGMII_1_CNTRL,
+ REG_RGMII_2_CNTRL,
--- /dev/null
+From 8373a0fe9c7160a55482effa8a3f725efd3f8434 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 10 Mar 2021 13:51:59 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: use 2 Gbps IMP port link on BCM4908
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 uses 2 Gbps link between switch and the Ethernet interface.
+Without this BCM4908 devices were able to achieve only 2 x ~895 Mb/s.
+This allows handling e.g. NAT traffic with 940 Mb/s.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/bcm_sf2.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -114,7 +114,10 @@ static void bcm_sf2_imp_setup(struct dsa
+ /* Force link status for IMP port */
+ reg = core_readl(priv, offset);
+ reg |= (MII_SW_OR | LINK_STS);
+- reg &= ~GMII_SPEED_UP_2G;
++ if (priv->type == BCM4908_DEVICE_ID)
++ reg |= GMII_SPEED_UP_2G;
++ else
++ reg &= ~GMII_SPEED_UP_2G;
+ core_writel(priv, reg, offset);
+
+ /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
--- /dev/null
+From 387d1c1819790aa8398c7cffab587f9a050a0d1a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sun, 7 Feb 2021 23:26:31 +0100
+Subject: [PATCH] dt-bindings: net: document BCM4908 Ethernet controller
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 is a family of SoCs with integrated Ethernet controller.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ .../bindings/net/brcm,bcm4908enet.yaml | 45 +++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml
+@@ -0,0 +1,45 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/brcm,bcm4908enet.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Broadcom BCM4908 Ethernet controller
++
++description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs
++
++maintainers:
++ - Rafał Miłecki <rafal@milecki.pl>
++
++properties:
++ compatible:
++ const: brcm,bcm4908enet
++
++ reg:
++ maxItems: 1
++
++ interrupts:
++ description: RX interrupt
++
++ interrupt-names:
++ const: rx
++
++required:
++ - reg
++ - interrupts
++ - interrupt-names
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/interrupt-controller/irq.h>
++ #include <dt-bindings/interrupt-controller/arm-gic.h>
++
++ ethernet@80002000 {
++ compatible = "brcm,bcm4908enet";
++ reg = <0x80002000 0x1000>;
++
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "rx";
++ };
--- /dev/null
+From 4feffeadbcb2e5b11cbbf191a33c245b74a5837b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sun, 7 Feb 2021 23:26:32 +0100
+Subject: [PATCH] net: broadcom: bcm4908enet: add BCM4908 controller driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 SoCs family uses Ethernel controller that includes UniMAC but
+uses different DMA engine (than other controllers) and requires
+different programming.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ MAINTAINERS | 9 +
+ drivers/net/ethernet/broadcom/Kconfig | 8 +
+ drivers/net/ethernet/broadcom/Makefile | 1 +
+ drivers/net/ethernet/broadcom/bcm4908enet.c | 676 ++++++++++++++++++++
+ drivers/net/ethernet/broadcom/bcm4908enet.h | 96 +++
+ 5 files changed, 790 insertions(+)
+ create mode 100644 drivers/net/ethernet/broadcom/bcm4908enet.c
+ create mode 100644 drivers/net/ethernet/broadcom/bcm4908enet.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -3427,6 +3427,15 @@ F: Documentation/devicetree/bindings/mip
+ F: arch/mips/bcm47xx/*
+ F: arch/mips/include/asm/mach-bcm47xx/*
+
++BROADCOM BCM4908 ETHERNET DRIVER
++M: Rafał Miłecki <rafal@milecki.pl>
++M: bcm-kernel-feedback-list@broadcom.com
++L: netdev@vger.kernel.org
++S: Maintained
++F: Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml
++F: drivers/net/ethernet/broadcom/bcm4908enet.*
++F: drivers/net/ethernet/broadcom/unimac.h
++
+ BROADCOM BCM5301X ARM ARCHITECTURE
+ M: Hauke Mehrtens <hauke@hauke-m.de>
+ M: Rafał Miłecki <zajec5@gmail.com>
+--- a/drivers/net/ethernet/broadcom/Kconfig
++++ b/drivers/net/ethernet/broadcom/Kconfig
+@@ -51,6 +51,14 @@ config B44_PCI
+ depends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT
+ default y
+
++config BCM4908ENET
++ tristate "Broadcom BCM4908 internal mac support"
++ depends on ARCH_BCM4908 || COMPILE_TEST
++ default y
++ help
++ This driver supports Ethernet controller integrated into Broadcom
++ BCM4908 family SoCs.
++
+ config BCM63XX_ENET
+ tristate "Broadcom 63xx internal mac support"
+ depends on BCM63XX
+--- a/drivers/net/ethernet/broadcom/Makefile
++++ b/drivers/net/ethernet/broadcom/Makefile
+@@ -4,6 +4,7 @@
+ #
+
+ obj-$(CONFIG_B44) += b44.o
++obj-$(CONFIG_BCM4908ENET) += bcm4908enet.o
+ obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o
+ obj-$(CONFIG_BCMGENET) += genet/
+ obj-$(CONFIG_BNX2) += bnx2.o
+--- /dev/null
++++ b/drivers/net/ethernet/broadcom/bcm4908enet.c
+@@ -0,0 +1,676 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>
++ */
++
++#include <linux/delay.h>
++#include <linux/etherdevice.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++
++#include "bcm4908enet.h"
++#include "unimac.h"
++
++#define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG
++#define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG
++#define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM
++#define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM
++
++#define ENET_TX_BDS_NUM 200
++#define ENET_RX_BDS_NUM 200
++#define ENET_RX_BDS_NUM_MAX 8192
++
++#define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \
++ ENET_DMA_CH_CFG_INT_NO_DESC | \
++ ENET_DMA_CH_CFG_INT_BUFF_DONE)
++#define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */
++
++#define ENET_MTU_MIN 60
++#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */
++#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */
++
++struct bcm4908enet_dma_ring_bd {
++ __le32 ctl;
++ __le32 addr;
++} __packed;
++
++struct bcm4908enet_dma_ring_slot {
++ struct sk_buff *skb;
++ unsigned int len;
++ dma_addr_t dma_addr;
++};
++
++struct bcm4908enet_dma_ring {
++ int is_tx;
++ int read_idx;
++ int write_idx;
++ int length;
++ u16 cfg_block;
++ u16 st_ram_block;
++
++ union {
++ void *cpu_addr;
++ struct bcm4908enet_dma_ring_bd *buf_desc;
++ };
++ dma_addr_t dma_addr;
++
++ struct bcm4908enet_dma_ring_slot *slots;
++};
++
++struct bcm4908enet {
++ struct device *dev;
++ struct net_device *netdev;
++ struct napi_struct napi;
++ void __iomem *base;
++
++ struct bcm4908enet_dma_ring tx_ring;
++ struct bcm4908enet_dma_ring rx_ring;
++};
++
++/***
++ * R/W ops
++ */
++
++static inline u32 enet_read(struct bcm4908enet *enet, u16 offset)
++{
++ return readl(enet->base + offset);
++}
++
++static inline void enet_write(struct bcm4908enet *enet, u16 offset, u32 value)
++{
++ writel(value, enet->base + offset);
++}
++
++static inline void enet_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)
++{
++ u32 val;
++
++ WARN_ON(set & ~mask);
++
++ val = enet_read(enet, offset);
++ val = (val & ~mask) | (set & mask);
++ enet_write(enet, offset, val);
++}
++
++static inline void enet_set(struct bcm4908enet *enet, u16 offset, u32 set)
++{
++ enet_maskset(enet, offset, set, set);
++}
++
++static inline u32 enet_umac_read(struct bcm4908enet *enet, u16 offset)
++{
++ return enet_read(enet, ENET_UNIMAC + offset);
++}
++
++static inline void enet_umac_write(struct bcm4908enet *enet, u16 offset, u32 value)
++{
++ enet_write(enet, ENET_UNIMAC + offset, value);
++}
++
++static inline void enet_umac_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)
++{
++ enet_maskset(enet, ENET_UNIMAC + offset, mask, set);
++}
++
++static inline void enet_umac_set(struct bcm4908enet *enet, u16 offset, u32 set)
++{
++ enet_set(enet, ENET_UNIMAC + offset, set);
++}
++
++/***
++ * Helpers
++ */
++
++static void bcm4908enet_intrs_on(struct bcm4908enet *enet)
++{
++ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
++}
++
++static void bcm4908enet_intrs_off(struct bcm4908enet *enet)
++{
++ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);
++}
++
++static void bcm4908enet_intrs_ack(struct bcm4908enet *enet)
++{
++ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
++}
++
++/***
++ * DMA
++ */
++
++static int bcm4908_dma_alloc_buf_descs(struct bcm4908enet *enet, struct bcm4908enet_dma_ring *ring)
++{
++ int size = ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
++ struct device *dev = enet->dev;
++
++ ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);
++ if (!ring->cpu_addr)
++ return -ENOMEM;
++
++ if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {
++ dev_err(dev, "Invalid DMA ring alignment\n");
++ goto err_free_buf_descs;
++ }
++
++ ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL);
++ if (!ring->slots)
++ goto err_free_buf_descs;
++
++ memset(ring->cpu_addr, 0, size);
++
++ ring->read_idx = 0;
++ ring->write_idx = 0;
++
++ return 0;
++
++err_free_buf_descs:
++ dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);
++ return -ENOMEM;
++}
++
++static void bcm4908enet_dma_free(struct bcm4908enet *enet)
++{
++ struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;
++ struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
++ struct device *dev = enet->dev;
++ int size;
++
++ size = rx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
++ if (rx_ring->cpu_addr)
++ dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);
++ kfree(rx_ring->slots);
++
++ size = tx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
++ if (tx_ring->cpu_addr)
++ dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);
++ kfree(tx_ring->slots);
++}
++
++static int bcm4908enet_dma_alloc(struct bcm4908enet *enet)
++{
++ struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;
++ struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
++ struct device *dev = enet->dev;
++ int err;
++
++ tx_ring->length = ENET_TX_BDS_NUM;
++ tx_ring->is_tx = 1;
++ tx_ring->cfg_block = ENET_DMA_CH_TX_CFG;
++ tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;
++ err = bcm4908_dma_alloc_buf_descs(enet, tx_ring);
++ if (err) {
++ dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err);
++ return err;
++ }
++
++ rx_ring->length = ENET_RX_BDS_NUM;
++ rx_ring->is_tx = 0;
++ rx_ring->cfg_block = ENET_DMA_CH_RX_CFG;
++ rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;
++ err = bcm4908_dma_alloc_buf_descs(enet, rx_ring);
++ if (err) {
++ dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err);
++ bcm4908enet_dma_free(enet);
++ return err;
++ }
++
++ return 0;
++}
++
++static void bcm4908enet_dma_reset(struct bcm4908enet *enet)
++{
++ struct bcm4908enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };
++ int i;
++
++ /* Disable the DMA controller and channel */
++ for (i = 0; i < ARRAY_SIZE(rings); i++)
++ enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);
++ enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);
++
++ /* Reset channels state */
++ for (i = 0; i < ARRAY_SIZE(rings); i++) {
++ struct bcm4908enet_dma_ring *ring = rings[i];
++
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);
++ }
++}
++
++static int bcm4908enet_dma_alloc_rx_buf(struct bcm4908enet *enet, unsigned int idx)
++{
++ struct bcm4908enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];
++ struct bcm4908enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];
++ struct device *dev = enet->dev;
++ u32 tmp;
++ int err;
++
++ slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;
++
++ slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
++ if (!slot->skb)
++ return -ENOMEM;
++
++ slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
++ err = dma_mapping_error(dev, slot->dma_addr);
++ if (err) {
++ dev_err(dev, "Failed to map DMA buffer: %d\n", err);
++ kfree_skb(slot->skb);
++ slot->skb = NULL;
++ return err;
++ }
++
++ tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
++ tmp |= DMA_CTL_STATUS_OWN;
++ if (idx == enet->rx_ring.length - 1)
++ tmp |= DMA_CTL_STATUS_WRAP;
++ buf_desc->ctl = cpu_to_le32(tmp);
++ buf_desc->addr = cpu_to_le32(slot->dma_addr);
++
++ return 0;
++}
++
++static void bcm4908enet_dma_ring_init(struct bcm4908enet *enet,
++ struct bcm4908enet_dma_ring *ring)
++{
++ int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */
++ int reset_subch = ring->is_tx ? 1 : 0;
++
++ /* Reset the DMA channel */
++ enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));
++ enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);
++
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
++
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
++ (uint32_t)ring->dma_addr);
++}
++
++static void bcm4908enet_dma_uninit(struct bcm4908enet *enet)
++{
++ struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
++ struct bcm4908enet_dma_ring_slot *slot;
++ struct device *dev = enet->dev;
++ int i;
++
++ for (i = rx_ring->length - 1; i >= 0; i--) {
++ slot = &rx_ring->slots[i];
++ if (!slot->skb)
++ continue;
++ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
++ kfree_skb(slot->skb);
++ slot->skb = NULL;
++ }
++}
++
++static int bcm4908enet_dma_init(struct bcm4908enet *enet)
++{
++ struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
++ struct device *dev = enet->dev;
++ int err;
++ int i;
++
++ for (i = 0; i < rx_ring->length; i++) {
++ err = bcm4908enet_dma_alloc_rx_buf(enet, i);
++ if (err) {
++ dev_err(dev, "Failed to alloc RX buffer: %d\n", err);
++ bcm4908enet_dma_uninit(enet);
++ return err;
++ }
++ }
++
++ bcm4908enet_dma_ring_init(enet, &enet->tx_ring);
++ bcm4908enet_dma_ring_init(enet, &enet->rx_ring);
++
++ return 0;
++}
++
++static void bcm4908enet_dma_tx_ring_ensable(struct bcm4908enet *enet,
++ struct bcm4908enet_dma_ring *ring)
++{
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
++}
++
++static void bcm4908enet_dma_tx_ring_disable(struct bcm4908enet *enet,
++ struct bcm4908enet_dma_ring *ring)
++{
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
++}
++
++static void bcm4908enet_dma_rx_ring_enable(struct bcm4908enet *enet,
++ struct bcm4908enet_dma_ring *ring)
++{
++ enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
++}
++
++static void bcm4908enet_dma_rx_ring_disable(struct bcm4908enet *enet,
++ struct bcm4908enet_dma_ring *ring)
++{
++ unsigned long deadline;
++ u32 tmp;
++
++ enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
++
++ deadline = jiffies + usecs_to_jiffies(2000);
++ do {
++ tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);
++ if (!(tmp & ENET_DMA_CH_CFG_ENABLE))
++ return;
++ enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
++ usleep_range(10, 30);
++ } while (!time_after_eq(jiffies, deadline));
++
++ dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n");
++}
++
++/***
++ * Ethernet driver
++ */
++
++static void bcm4908enet_gmac_init(struct bcm4908enet *enet)
++{
++ u32 cmd;
++
++ cmd = enet_umac_read(enet, UMAC_CMD);
++ enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);
++ enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);
++
++ enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);
++ enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);
++
++ enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);
++ enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);
++
++ cmd = enet_umac_read(enet, UMAC_CMD);
++ cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);
++ cmd &= ~CMD_TX_EN;
++ cmd &= ~CMD_RX_EN;
++ cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;
++ enet_umac_write(enet, UMAC_CMD, cmd);
++
++ enet_maskset(enet, ENET_GMAC_STATUS,
++ ENET_GMAC_STATUS_ETH_SPEED_MASK |
++ ENET_GMAC_STATUS_HD |
++ ENET_GMAC_STATUS_AUTO_CFG_EN |
++ ENET_GMAC_STATUS_LINK_UP,
++ ENET_GMAC_STATUS_ETH_SPEED_1000 |
++ ENET_GMAC_STATUS_AUTO_CFG_EN |
++ ENET_GMAC_STATUS_LINK_UP);
++}
++
++static irqreturn_t bcm4908enet_irq_handler(int irq, void *dev_id)
++{
++ struct bcm4908enet *enet = dev_id;
++
++ bcm4908enet_intrs_off(enet);
++ bcm4908enet_intrs_ack(enet);
++
++ napi_schedule(&enet->napi);
++
++ return IRQ_HANDLED;
++}
++
++static int bcm4908enet_open(struct net_device *netdev)
++{
++ struct bcm4908enet *enet = netdev_priv(netdev);
++ struct device *dev = enet->dev;
++ int err;
++
++ err = request_irq(netdev->irq, bcm4908enet_irq_handler, 0, "enet", enet);
++ if (err) {
++ dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err);
++ return err;
++ }
++
++ bcm4908enet_gmac_init(enet);
++ bcm4908enet_dma_reset(enet);
++ bcm4908enet_dma_init(enet);
++
++ enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
++
++ enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);
++ enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);
++ bcm4908enet_dma_rx_ring_enable(enet, &enet->rx_ring);
++
++ napi_enable(&enet->napi);
++ netif_carrier_on(netdev);
++ netif_start_queue(netdev);
++
++ bcm4908enet_intrs_ack(enet);
++ bcm4908enet_intrs_on(enet);
++
++ return 0;
++}
++
++static int bcm4908enet_stop(struct net_device *netdev)
++{
++ struct bcm4908enet *enet = netdev_priv(netdev);
++
++ netif_stop_queue(netdev);
++ netif_carrier_off(netdev);
++ napi_disable(&enet->napi);
++
++ bcm4908enet_dma_rx_ring_disable(enet, &enet->rx_ring);
++ bcm4908enet_dma_tx_ring_disable(enet, &enet->tx_ring);
++
++ bcm4908enet_dma_uninit(enet);
++
++ free_irq(enet->netdev->irq, enet);
++
++ return 0;
++}
++
++static int bcm4908enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++{
++ struct bcm4908enet *enet = netdev_priv(netdev);
++ struct bcm4908enet_dma_ring *ring = &enet->tx_ring;
++ struct bcm4908enet_dma_ring_slot *slot;
++ struct device *dev = enet->dev;
++ struct bcm4908enet_dma_ring_bd *buf_desc;
++ int free_buf_descs;
++ u32 tmp;
++
++ /* Free transmitted skbs */
++ while (ring->read_idx != ring->write_idx) {
++ buf_desc = &ring->buf_desc[ring->read_idx];
++ if (buf_desc->ctl & DMA_CTL_STATUS_OWN)
++ break;
++ slot = &ring->slots[ring->read_idx];
++
++ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);
++ dev_kfree_skb(slot->skb);
++ if (++ring->read_idx == ring->length)
++ ring->read_idx = 0;
++ }
++
++ /* Don't use the last empty buf descriptor */
++ if (ring->read_idx <= ring->write_idx)
++ free_buf_descs = ring->read_idx - ring->write_idx + ring->length;
++ else
++ free_buf_descs = ring->read_idx - ring->write_idx;
++ if (free_buf_descs < 2)
++ return NETDEV_TX_BUSY;
++
++ /* Hardware removes OWN bit after sending data */
++ buf_desc = &ring->buf_desc[ring->write_idx];
++ if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {
++ netif_stop_queue(netdev);
++ return NETDEV_TX_BUSY;
++ }
++
++ slot = &ring->slots[ring->write_idx];
++ slot->skb = skb;
++ slot->len = skb->len;
++ slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
++ if (unlikely(dma_mapping_error(dev, slot->dma_addr)))
++ return NETDEV_TX_BUSY;
++
++ tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
++ tmp |= DMA_CTL_STATUS_OWN;
++ tmp |= DMA_CTL_STATUS_SOP;
++ tmp |= DMA_CTL_STATUS_EOP;
++ tmp |= DMA_CTL_STATUS_APPEND_CRC;
++ if (ring->write_idx + 1 == ring->length - 1)
++ tmp |= DMA_CTL_STATUS_WRAP;
++
++ buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
++ buf_desc->ctl = cpu_to_le32(tmp);
++
++ bcm4908enet_dma_tx_ring_ensable(enet, &enet->tx_ring);
++
++ if (++ring->write_idx == ring->length - 1)
++ ring->write_idx = 0;
++ enet->netdev->stats.tx_bytes += skb->len;
++ enet->netdev->stats.tx_packets++;
++
++ return NETDEV_TX_OK;
++}
++
++static int bcm4908enet_poll(struct napi_struct *napi, int weight)
++{
++ struct bcm4908enet *enet = container_of(napi, struct bcm4908enet, napi);
++ struct device *dev = enet->dev;
++ int handled = 0;
++
++ while (handled < weight) {
++ struct bcm4908enet_dma_ring_bd *buf_desc;
++ struct bcm4908enet_dma_ring_slot slot;
++ u32 ctl;
++ int len;
++ int err;
++
++ buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];
++ ctl = le32_to_cpu(buf_desc->ctl);
++ if (ctl & DMA_CTL_STATUS_OWN)
++ break;
++
++ slot = enet->rx_ring.slots[enet->rx_ring.read_idx];
++
++ /* Provide new buffer before unpinning the old one */
++ err = bcm4908enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);
++ if (err)
++ break;
++
++ if (++enet->rx_ring.read_idx == enet->rx_ring.length)
++ enet->rx_ring.read_idx = 0;
++
++ len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
++
++ if (len < ENET_MTU_MIN ||
++ (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
++ enet->netdev->stats.rx_dropped++;
++ break;
++ }
++
++ dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
++
++ skb_put(slot.skb, len - 4 + 2);
++ slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
++ netif_receive_skb(slot.skb);
++
++ enet->netdev->stats.rx_packets++;
++ enet->netdev->stats.rx_bytes += len;
++ }
++
++ if (handled < weight) {
++ napi_complete_done(napi, handled);
++ bcm4908enet_intrs_on(enet);
++ }
++
++ return handled;
++}
++
++static const struct net_device_ops bcm96xx_netdev_ops = {
++ .ndo_open = bcm4908enet_open,
++ .ndo_stop = bcm4908enet_stop,
++ .ndo_start_xmit = bcm4908enet_start_xmit,
++ .ndo_set_mac_address = eth_mac_addr,
++};
++
++static int bcm4908enet_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct net_device *netdev;
++ struct bcm4908enet *enet;
++ int err;
++
++ netdev = devm_alloc_etherdev(dev, sizeof(*enet));
++ if (!netdev)
++ return -ENOMEM;
++
++ enet = netdev_priv(netdev);
++ enet->dev = dev;
++ enet->netdev = netdev;
++
++ enet->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(enet->base)) {
++ dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base));
++ return PTR_ERR(enet->base);
++ }
++
++ netdev->irq = platform_get_irq_byname(pdev, "rx");
++ if (netdev->irq < 0)
++ return netdev->irq;
++
++ dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
++
++ err = bcm4908enet_dma_alloc(enet);
++ if (err)
++ return err;
++
++ SET_NETDEV_DEV(netdev, &pdev->dev);
++ eth_hw_addr_random(netdev);
++ netdev->netdev_ops = &bcm96xx_netdev_ops;
++ netdev->min_mtu = ETH_ZLEN;
++ netdev->mtu = ENET_MTU_MAX;
++ netdev->max_mtu = ENET_MTU_MAX;
++ netif_napi_add(netdev, &enet->napi, bcm4908enet_poll, 64);
++
++ err = register_netdev(netdev);
++ if (err) {
++ bcm4908enet_dma_free(enet);
++ return err;
++ }
++
++ platform_set_drvdata(pdev, enet);
++
++ return 0;
++}
++
++static int bcm4908enet_remove(struct platform_device *pdev)
++{
++ struct bcm4908enet *enet = platform_get_drvdata(pdev);
++
++ unregister_netdev(enet->netdev);
++ netif_napi_del(&enet->napi);
++ bcm4908enet_dma_free(enet);
++
++ return 0;
++}
++
++static const struct of_device_id bcm4908enet_of_match[] = {
++ { .compatible = "brcm,bcm4908enet"},
++ {},
++};
++
++static struct platform_driver bcm4908enet_driver = {
++ .driver = {
++ .name = "bcm4908enet",
++ .of_match_table = bcm4908enet_of_match,
++ },
++ .probe = bcm4908enet_probe,
++ .remove = bcm4908enet_remove,
++};
++module_platform_driver(bcm4908enet_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_DEVICE_TABLE(of, bcm4908enet_of_match);
+--- /dev/null
++++ b/drivers/net/ethernet/broadcom/bcm4908enet.h
+@@ -0,0 +1,96 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++#ifndef __BCM4908ENET_H
++#define __BCM4908ENET_H
++
++#define ENET_CONTROL 0x000
++#define ENET_MIB_CTRL 0x004
++#define ENET_MIB_CTRL_CLR_MIB 0x00000001
++#define ENET_RX_ERR_MASK 0x008
++#define ENET_MIB_MAX_PKT_SIZE 0x00C
++#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
++#define ENET_DIAG_OUT 0x01c
++#define ENET_ENABLE_DROP_PKT 0x020
++#define ENET_IRQ_ENABLE 0x024
++#define ENET_IRQ_ENABLE_OVFL 0x00000001
++#define ENET_GMAC_STATUS 0x028
++#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003
++#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000
++#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001
++#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002
++#define ENET_GMAC_STATUS_HD 0x00000004
++#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008
++#define ENET_GMAC_STATUS_LINK_UP 0x00000010
++#define ENET_IRQ_STATUS 0x02c
++#define ENET_IRQ_STATUS_OVFL 0x00000001
++#define ENET_OVERFLOW_COUNTER 0x030
++#define ENET_FLUSH 0x034
++#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001
++#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002
++#define ENET_RSV_SELECT 0x038
++#define ENET_BP_FORCE 0x03c
++#define ENET_BP_FORCE_FORCE 0x00000001
++#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040
++#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f
++#define ENET_TX_CRC_CTRL 0x044
++#define ENET_MIB 0x200
++#define ENET_UNIMAC 0x400
++#define ENET_DMA 0x800
++#define ENET_DMA_CONTROLLER_CFG 0x800
++#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001
++#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002
++#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004
++#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804
++#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808
++#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c
++#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000
++#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810
++#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814
++#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818
++#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C
++#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820
++#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824
++#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828
++#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C
++#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830
++#define ENET_DMA_CTRL_CHANNEL_RESET 0x834
++#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838
++#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840
++#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844
++#define ENET_DMA_CH0_CFG 0xa00 /* RX */
++#define ENET_DMA_CH1_CFG 0xa10 /* TX */
++#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */
++#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */
++
++#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */
++#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */
++#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */
++#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */
++#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */
++#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */
++#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */
++#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */
++#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */
++#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */
++#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
++#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */
++#define ENET_DMA_CH_CFG_SIZE 0x10
++
++#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */
++#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */
++#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */
++#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */
++#define ENET_DMA_CH_STATE_RAM_SIZE 0x10
++
++#define DMA_CTL_STATUS_APPEND_CRC 0x00000100
++#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200
++#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */
++#define DMA_CTL_STATUS_WRAP 0x00001000 /* */
++#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */
++#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */
++#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */
++#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000
++#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16
++#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000
++#define DMA_CTL_LEN_DESC_USEFPM 0x80000000
++
++#endif
--- /dev/null
+From 6710c5b0674f8811f7d8fbfc526684e7ed77f765 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Feb 2021 13:12:32 +0100
+Subject: [PATCH] dt-bindings: net: rename BCM4908 Ethernet binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Rob pointed out that a normal convention is "brcm,bcm4908-enet" so
+update whole binding to match it.
+
+Suggested-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ .../net/{brcm,bcm4908enet.yaml => brcm,bcm4908-enet.yaml} | 6 +++---
+ MAINTAINERS | 2 +-
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+ rename Documentation/devicetree/bindings/net/{brcm,bcm4908enet.yaml => brcm,bcm4908-enet.yaml} (85%)
+
+--- a/Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml
++++ /dev/null
+@@ -1,45 +0,0 @@
+-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+-%YAML 1.2
+----
+-$id: http://devicetree.org/schemas/net/brcm,bcm4908enet.yaml#
+-$schema: http://devicetree.org/meta-schemas/core.yaml#
+-
+-title: Broadcom BCM4908 Ethernet controller
+-
+-description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs
+-
+-maintainers:
+- - Rafał Miłecki <rafal@milecki.pl>
+-
+-properties:
+- compatible:
+- const: brcm,bcm4908enet
+-
+- reg:
+- maxItems: 1
+-
+- interrupts:
+- description: RX interrupt
+-
+- interrupt-names:
+- const: rx
+-
+-required:
+- - reg
+- - interrupts
+- - interrupt-names
+-
+-additionalProperties: false
+-
+-examples:
+- - |
+- #include <dt-bindings/interrupt-controller/irq.h>
+- #include <dt-bindings/interrupt-controller/arm-gic.h>
+-
+- ethernet@80002000 {
+- compatible = "brcm,bcm4908enet";
+- reg = <0x80002000 0x1000>;
+-
+- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "rx";
+- };
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
+@@ -0,0 +1,45 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/brcm,bcm4908-enet.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Broadcom BCM4908 Ethernet controller
++
++description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs
++
++maintainers:
++ - Rafał Miłecki <rafal@milecki.pl>
++
++properties:
++ compatible:
++ const: brcm,bcm4908-enet
++
++ reg:
++ maxItems: 1
++
++ interrupts:
++ description: RX interrupt
++
++ interrupt-names:
++ const: rx
++
++required:
++ - reg
++ - interrupts
++ - interrupt-names
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/interrupt-controller/irq.h>
++ #include <dt-bindings/interrupt-controller/arm-gic.h>
++
++ ethernet@80002000 {
++ compatible = "brcm,bcm4908-enet";
++ reg = <0x80002000 0x1000>;
++
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "rx";
++ };
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -3432,7 +3432,7 @@ M: Rafał Miłecki <rafal@milecki.pl>
+ M: bcm-kernel-feedback-list@broadcom.com
+ L: netdev@vger.kernel.org
+ S: Maintained
+-F: Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml
++F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
+ F: drivers/net/ethernet/broadcom/bcm4908enet.*
+ F: drivers/net/ethernet/broadcom/unimac.h
+
--- /dev/null
+From f08b5cf1eb1f2aefc6fe4a89c8c757ba94721d0b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Feb 2021 13:12:33 +0100
+Subject: [PATCH] dt-bindings: net: bcm4908-enet: include
+ ethernet-controller.yaml
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It should be /included/ by every Ethernet controller binding. It adds
+support for various generic properties.
+
+Suggested-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
++++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
+@@ -11,6 +11,9 @@ description: Broadcom's Ethernet control
+ maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
++allOf:
++ - $ref: ethernet-controller.yaml#
++
+ properties:
+ compatible:
+ const: brcm,bcm4908-enet
--- /dev/null
+From 9d61d138ab30bbfe4a8609853c81e881c4054a0b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Feb 2021 13:12:34 +0100
+Subject: [PATCH] net: broadcom: rename BCM4908 driver & update DT binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+compatible string was updated to match normal naming convention so
+update driver as well
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ MAINTAINERS | 2 +-
+ drivers/net/ethernet/broadcom/Kconfig | 2 +-
+ drivers/net/ethernet/broadcom/Makefile | 2 +-
+ .../{bcm4908enet.c => bcm4908_enet.c} | 215 +++++++++---------
+ .../{bcm4908enet.h => bcm4908_enet.h} | 4 +-
+ 5 files changed, 113 insertions(+), 112 deletions(-)
+ rename drivers/net/ethernet/broadcom/{bcm4908enet.c => bcm4908_enet.c} (68%)
+ rename drivers/net/ethernet/broadcom/{bcm4908enet.h => bcm4908_enet.h} (98%)
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -3433,7 +3433,7 @@ M: bcm-kernel-feedback-list@broadcom.com
+ L: netdev@vger.kernel.org
+ S: Maintained
+ F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
+-F: drivers/net/ethernet/broadcom/bcm4908enet.*
++F: drivers/net/ethernet/broadcom/bcm4908_enet.*
+ F: drivers/net/ethernet/broadcom/unimac.h
+
+ BROADCOM BCM5301X ARM ARCHITECTURE
+--- a/drivers/net/ethernet/broadcom/Kconfig
++++ b/drivers/net/ethernet/broadcom/Kconfig
+@@ -51,7 +51,7 @@ config B44_PCI
+ depends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT
+ default y
+
+-config BCM4908ENET
++config BCM4908_ENET
+ tristate "Broadcom BCM4908 internal mac support"
+ depends on ARCH_BCM4908 || COMPILE_TEST
+ default y
+--- a/drivers/net/ethernet/broadcom/Makefile
++++ b/drivers/net/ethernet/broadcom/Makefile
+@@ -4,7 +4,7 @@
+ #
+
+ obj-$(CONFIG_B44) += b44.o
+-obj-$(CONFIG_BCM4908ENET) += bcm4908enet.o
++obj-$(CONFIG_BCM4908_ENET) += bcm4908_enet.o
+ obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o
+ obj-$(CONFIG_BCMGENET) += genet/
+ obj-$(CONFIG_BNX2) += bnx2.o
+--- a/drivers/net/ethernet/broadcom/bcm4908enet.c
++++ /dev/null
+@@ -1,676 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-only
+-/*
+- * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>
+- */
+-
+-#include <linux/delay.h>
+-#include <linux/etherdevice.h>
+-#include <linux/interrupt.h>
+-#include <linux/module.h>
+-#include <linux/of.h>
+-#include <linux/platform_device.h>
+-#include <linux/slab.h>
+-#include <linux/string.h>
+-
+-#include "bcm4908enet.h"
+-#include "unimac.h"
+-
+-#define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG
+-#define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG
+-#define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM
+-#define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM
+-
+-#define ENET_TX_BDS_NUM 200
+-#define ENET_RX_BDS_NUM 200
+-#define ENET_RX_BDS_NUM_MAX 8192
+-
+-#define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \
+- ENET_DMA_CH_CFG_INT_NO_DESC | \
+- ENET_DMA_CH_CFG_INT_BUFF_DONE)
+-#define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */
+-
+-#define ENET_MTU_MIN 60
+-#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */
+-#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */
+-
+-struct bcm4908enet_dma_ring_bd {
+- __le32 ctl;
+- __le32 addr;
+-} __packed;
+-
+-struct bcm4908enet_dma_ring_slot {
+- struct sk_buff *skb;
+- unsigned int len;
+- dma_addr_t dma_addr;
+-};
+-
+-struct bcm4908enet_dma_ring {
+- int is_tx;
+- int read_idx;
+- int write_idx;
+- int length;
+- u16 cfg_block;
+- u16 st_ram_block;
+-
+- union {
+- void *cpu_addr;
+- struct bcm4908enet_dma_ring_bd *buf_desc;
+- };
+- dma_addr_t dma_addr;
+-
+- struct bcm4908enet_dma_ring_slot *slots;
+-};
+-
+-struct bcm4908enet {
+- struct device *dev;
+- struct net_device *netdev;
+- struct napi_struct napi;
+- void __iomem *base;
+-
+- struct bcm4908enet_dma_ring tx_ring;
+- struct bcm4908enet_dma_ring rx_ring;
+-};
+-
+-/***
+- * R/W ops
+- */
+-
+-static inline u32 enet_read(struct bcm4908enet *enet, u16 offset)
+-{
+- return readl(enet->base + offset);
+-}
+-
+-static inline void enet_write(struct bcm4908enet *enet, u16 offset, u32 value)
+-{
+- writel(value, enet->base + offset);
+-}
+-
+-static inline void enet_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)
+-{
+- u32 val;
+-
+- WARN_ON(set & ~mask);
+-
+- val = enet_read(enet, offset);
+- val = (val & ~mask) | (set & mask);
+- enet_write(enet, offset, val);
+-}
+-
+-static inline void enet_set(struct bcm4908enet *enet, u16 offset, u32 set)
+-{
+- enet_maskset(enet, offset, set, set);
+-}
+-
+-static inline u32 enet_umac_read(struct bcm4908enet *enet, u16 offset)
+-{
+- return enet_read(enet, ENET_UNIMAC + offset);
+-}
+-
+-static inline void enet_umac_write(struct bcm4908enet *enet, u16 offset, u32 value)
+-{
+- enet_write(enet, ENET_UNIMAC + offset, value);
+-}
+-
+-static inline void enet_umac_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)
+-{
+- enet_maskset(enet, ENET_UNIMAC + offset, mask, set);
+-}
+-
+-static inline void enet_umac_set(struct bcm4908enet *enet, u16 offset, u32 set)
+-{
+- enet_set(enet, ENET_UNIMAC + offset, set);
+-}
+-
+-/***
+- * Helpers
+- */
+-
+-static void bcm4908enet_intrs_on(struct bcm4908enet *enet)
+-{
+- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
+-}
+-
+-static void bcm4908enet_intrs_off(struct bcm4908enet *enet)
+-{
+- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);
+-}
+-
+-static void bcm4908enet_intrs_ack(struct bcm4908enet *enet)
+-{
+- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
+-}
+-
+-/***
+- * DMA
+- */
+-
+-static int bcm4908_dma_alloc_buf_descs(struct bcm4908enet *enet, struct bcm4908enet_dma_ring *ring)
+-{
+- int size = ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
+- struct device *dev = enet->dev;
+-
+- ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);
+- if (!ring->cpu_addr)
+- return -ENOMEM;
+-
+- if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {
+- dev_err(dev, "Invalid DMA ring alignment\n");
+- goto err_free_buf_descs;
+- }
+-
+- ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL);
+- if (!ring->slots)
+- goto err_free_buf_descs;
+-
+- memset(ring->cpu_addr, 0, size);
+-
+- ring->read_idx = 0;
+- ring->write_idx = 0;
+-
+- return 0;
+-
+-err_free_buf_descs:
+- dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);
+- return -ENOMEM;
+-}
+-
+-static void bcm4908enet_dma_free(struct bcm4908enet *enet)
+-{
+- struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;
+- struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
+- struct device *dev = enet->dev;
+- int size;
+-
+- size = rx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
+- if (rx_ring->cpu_addr)
+- dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);
+- kfree(rx_ring->slots);
+-
+- size = tx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
+- if (tx_ring->cpu_addr)
+- dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);
+- kfree(tx_ring->slots);
+-}
+-
+-static int bcm4908enet_dma_alloc(struct bcm4908enet *enet)
+-{
+- struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;
+- struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
+- struct device *dev = enet->dev;
+- int err;
+-
+- tx_ring->length = ENET_TX_BDS_NUM;
+- tx_ring->is_tx = 1;
+- tx_ring->cfg_block = ENET_DMA_CH_TX_CFG;
+- tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;
+- err = bcm4908_dma_alloc_buf_descs(enet, tx_ring);
+- if (err) {
+- dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err);
+- return err;
+- }
+-
+- rx_ring->length = ENET_RX_BDS_NUM;
+- rx_ring->is_tx = 0;
+- rx_ring->cfg_block = ENET_DMA_CH_RX_CFG;
+- rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;
+- err = bcm4908_dma_alloc_buf_descs(enet, rx_ring);
+- if (err) {
+- dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err);
+- bcm4908enet_dma_free(enet);
+- return err;
+- }
+-
+- return 0;
+-}
+-
+-static void bcm4908enet_dma_reset(struct bcm4908enet *enet)
+-{
+- struct bcm4908enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };
+- int i;
+-
+- /* Disable the DMA controller and channel */
+- for (i = 0; i < ARRAY_SIZE(rings); i++)
+- enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);
+- enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);
+-
+- /* Reset channels state */
+- for (i = 0; i < ARRAY_SIZE(rings); i++) {
+- struct bcm4908enet_dma_ring *ring = rings[i];
+-
+- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);
+- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);
+- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);
+- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);
+- }
+-}
+-
+-static int bcm4908enet_dma_alloc_rx_buf(struct bcm4908enet *enet, unsigned int idx)
+-{
+- struct bcm4908enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];
+- struct bcm4908enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];
+- struct device *dev = enet->dev;
+- u32 tmp;
+- int err;
+-
+- slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;
+-
+- slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
+- if (!slot->skb)
+- return -ENOMEM;
+-
+- slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
+- err = dma_mapping_error(dev, slot->dma_addr);
+- if (err) {
+- dev_err(dev, "Failed to map DMA buffer: %d\n", err);
+- kfree_skb(slot->skb);
+- slot->skb = NULL;
+- return err;
+- }
+-
+- tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
+- tmp |= DMA_CTL_STATUS_OWN;
+- if (idx == enet->rx_ring.length - 1)
+- tmp |= DMA_CTL_STATUS_WRAP;
+- buf_desc->ctl = cpu_to_le32(tmp);
+- buf_desc->addr = cpu_to_le32(slot->dma_addr);
+-
+- return 0;
+-}
+-
+-static void bcm4908enet_dma_ring_init(struct bcm4908enet *enet,
+- struct bcm4908enet_dma_ring *ring)
+-{
+- int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */
+- int reset_subch = ring->is_tx ? 1 : 0;
+-
+- /* Reset the DMA channel */
+- enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));
+- enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);
+-
+- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
+- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);
+- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
+-
+- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
+- (uint32_t)ring->dma_addr);
+-}
+-
+-static void bcm4908enet_dma_uninit(struct bcm4908enet *enet)
+-{
+- struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
+- struct bcm4908enet_dma_ring_slot *slot;
+- struct device *dev = enet->dev;
+- int i;
+-
+- for (i = rx_ring->length - 1; i >= 0; i--) {
+- slot = &rx_ring->slots[i];
+- if (!slot->skb)
+- continue;
+- dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
+- kfree_skb(slot->skb);
+- slot->skb = NULL;
+- }
+-}
+-
+-static int bcm4908enet_dma_init(struct bcm4908enet *enet)
+-{
+- struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
+- struct device *dev = enet->dev;
+- int err;
+- int i;
+-
+- for (i = 0; i < rx_ring->length; i++) {
+- err = bcm4908enet_dma_alloc_rx_buf(enet, i);
+- if (err) {
+- dev_err(dev, "Failed to alloc RX buffer: %d\n", err);
+- bcm4908enet_dma_uninit(enet);
+- return err;
+- }
+- }
+-
+- bcm4908enet_dma_ring_init(enet, &enet->tx_ring);
+- bcm4908enet_dma_ring_init(enet, &enet->rx_ring);
+-
+- return 0;
+-}
+-
+-static void bcm4908enet_dma_tx_ring_ensable(struct bcm4908enet *enet,
+- struct bcm4908enet_dma_ring *ring)
+-{
+- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
+-}
+-
+-static void bcm4908enet_dma_tx_ring_disable(struct bcm4908enet *enet,
+- struct bcm4908enet_dma_ring *ring)
+-{
+- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
+-}
+-
+-static void bcm4908enet_dma_rx_ring_enable(struct bcm4908enet *enet,
+- struct bcm4908enet_dma_ring *ring)
+-{
+- enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
+-}
+-
+-static void bcm4908enet_dma_rx_ring_disable(struct bcm4908enet *enet,
+- struct bcm4908enet_dma_ring *ring)
+-{
+- unsigned long deadline;
+- u32 tmp;
+-
+- enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
+-
+- deadline = jiffies + usecs_to_jiffies(2000);
+- do {
+- tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);
+- if (!(tmp & ENET_DMA_CH_CFG_ENABLE))
+- return;
+- enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
+- usleep_range(10, 30);
+- } while (!time_after_eq(jiffies, deadline));
+-
+- dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n");
+-}
+-
+-/***
+- * Ethernet driver
+- */
+-
+-static void bcm4908enet_gmac_init(struct bcm4908enet *enet)
+-{
+- u32 cmd;
+-
+- cmd = enet_umac_read(enet, UMAC_CMD);
+- enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);
+- enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);
+-
+- enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);
+- enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);
+-
+- enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);
+- enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);
+-
+- cmd = enet_umac_read(enet, UMAC_CMD);
+- cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);
+- cmd &= ~CMD_TX_EN;
+- cmd &= ~CMD_RX_EN;
+- cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;
+- enet_umac_write(enet, UMAC_CMD, cmd);
+-
+- enet_maskset(enet, ENET_GMAC_STATUS,
+- ENET_GMAC_STATUS_ETH_SPEED_MASK |
+- ENET_GMAC_STATUS_HD |
+- ENET_GMAC_STATUS_AUTO_CFG_EN |
+- ENET_GMAC_STATUS_LINK_UP,
+- ENET_GMAC_STATUS_ETH_SPEED_1000 |
+- ENET_GMAC_STATUS_AUTO_CFG_EN |
+- ENET_GMAC_STATUS_LINK_UP);
+-}
+-
+-static irqreturn_t bcm4908enet_irq_handler(int irq, void *dev_id)
+-{
+- struct bcm4908enet *enet = dev_id;
+-
+- bcm4908enet_intrs_off(enet);
+- bcm4908enet_intrs_ack(enet);
+-
+- napi_schedule(&enet->napi);
+-
+- return IRQ_HANDLED;
+-}
+-
+-static int bcm4908enet_open(struct net_device *netdev)
+-{
+- struct bcm4908enet *enet = netdev_priv(netdev);
+- struct device *dev = enet->dev;
+- int err;
+-
+- err = request_irq(netdev->irq, bcm4908enet_irq_handler, 0, "enet", enet);
+- if (err) {
+- dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err);
+- return err;
+- }
+-
+- bcm4908enet_gmac_init(enet);
+- bcm4908enet_dma_reset(enet);
+- bcm4908enet_dma_init(enet);
+-
+- enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
+-
+- enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);
+- enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);
+- bcm4908enet_dma_rx_ring_enable(enet, &enet->rx_ring);
+-
+- napi_enable(&enet->napi);
+- netif_carrier_on(netdev);
+- netif_start_queue(netdev);
+-
+- bcm4908enet_intrs_ack(enet);
+- bcm4908enet_intrs_on(enet);
+-
+- return 0;
+-}
+-
+-static int bcm4908enet_stop(struct net_device *netdev)
+-{
+- struct bcm4908enet *enet = netdev_priv(netdev);
+-
+- netif_stop_queue(netdev);
+- netif_carrier_off(netdev);
+- napi_disable(&enet->napi);
+-
+- bcm4908enet_dma_rx_ring_disable(enet, &enet->rx_ring);
+- bcm4908enet_dma_tx_ring_disable(enet, &enet->tx_ring);
+-
+- bcm4908enet_dma_uninit(enet);
+-
+- free_irq(enet->netdev->irq, enet);
+-
+- return 0;
+-}
+-
+-static int bcm4908enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+-{
+- struct bcm4908enet *enet = netdev_priv(netdev);
+- struct bcm4908enet_dma_ring *ring = &enet->tx_ring;
+- struct bcm4908enet_dma_ring_slot *slot;
+- struct device *dev = enet->dev;
+- struct bcm4908enet_dma_ring_bd *buf_desc;
+- int free_buf_descs;
+- u32 tmp;
+-
+- /* Free transmitted skbs */
+- while (ring->read_idx != ring->write_idx) {
+- buf_desc = &ring->buf_desc[ring->read_idx];
+- if (buf_desc->ctl & DMA_CTL_STATUS_OWN)
+- break;
+- slot = &ring->slots[ring->read_idx];
+-
+- dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);
+- dev_kfree_skb(slot->skb);
+- if (++ring->read_idx == ring->length)
+- ring->read_idx = 0;
+- }
+-
+- /* Don't use the last empty buf descriptor */
+- if (ring->read_idx <= ring->write_idx)
+- free_buf_descs = ring->read_idx - ring->write_idx + ring->length;
+- else
+- free_buf_descs = ring->read_idx - ring->write_idx;
+- if (free_buf_descs < 2)
+- return NETDEV_TX_BUSY;
+-
+- /* Hardware removes OWN bit after sending data */
+- buf_desc = &ring->buf_desc[ring->write_idx];
+- if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {
+- netif_stop_queue(netdev);
+- return NETDEV_TX_BUSY;
+- }
+-
+- slot = &ring->slots[ring->write_idx];
+- slot->skb = skb;
+- slot->len = skb->len;
+- slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
+- if (unlikely(dma_mapping_error(dev, slot->dma_addr)))
+- return NETDEV_TX_BUSY;
+-
+- tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
+- tmp |= DMA_CTL_STATUS_OWN;
+- tmp |= DMA_CTL_STATUS_SOP;
+- tmp |= DMA_CTL_STATUS_EOP;
+- tmp |= DMA_CTL_STATUS_APPEND_CRC;
+- if (ring->write_idx + 1 == ring->length - 1)
+- tmp |= DMA_CTL_STATUS_WRAP;
+-
+- buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
+- buf_desc->ctl = cpu_to_le32(tmp);
+-
+- bcm4908enet_dma_tx_ring_ensable(enet, &enet->tx_ring);
+-
+- if (++ring->write_idx == ring->length - 1)
+- ring->write_idx = 0;
+- enet->netdev->stats.tx_bytes += skb->len;
+- enet->netdev->stats.tx_packets++;
+-
+- return NETDEV_TX_OK;
+-}
+-
+-static int bcm4908enet_poll(struct napi_struct *napi, int weight)
+-{
+- struct bcm4908enet *enet = container_of(napi, struct bcm4908enet, napi);
+- struct device *dev = enet->dev;
+- int handled = 0;
+-
+- while (handled < weight) {
+- struct bcm4908enet_dma_ring_bd *buf_desc;
+- struct bcm4908enet_dma_ring_slot slot;
+- u32 ctl;
+- int len;
+- int err;
+-
+- buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];
+- ctl = le32_to_cpu(buf_desc->ctl);
+- if (ctl & DMA_CTL_STATUS_OWN)
+- break;
+-
+- slot = enet->rx_ring.slots[enet->rx_ring.read_idx];
+-
+- /* Provide new buffer before unpinning the old one */
+- err = bcm4908enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);
+- if (err)
+- break;
+-
+- if (++enet->rx_ring.read_idx == enet->rx_ring.length)
+- enet->rx_ring.read_idx = 0;
+-
+- len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
+-
+- if (len < ENET_MTU_MIN ||
+- (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
+- enet->netdev->stats.rx_dropped++;
+- break;
+- }
+-
+- dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
+-
+- skb_put(slot.skb, len - 4 + 2);
+- slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
+- netif_receive_skb(slot.skb);
+-
+- enet->netdev->stats.rx_packets++;
+- enet->netdev->stats.rx_bytes += len;
+- }
+-
+- if (handled < weight) {
+- napi_complete_done(napi, handled);
+- bcm4908enet_intrs_on(enet);
+- }
+-
+- return handled;
+-}
+-
+-static const struct net_device_ops bcm96xx_netdev_ops = {
+- .ndo_open = bcm4908enet_open,
+- .ndo_stop = bcm4908enet_stop,
+- .ndo_start_xmit = bcm4908enet_start_xmit,
+- .ndo_set_mac_address = eth_mac_addr,
+-};
+-
+-static int bcm4908enet_probe(struct platform_device *pdev)
+-{
+- struct device *dev = &pdev->dev;
+- struct net_device *netdev;
+- struct bcm4908enet *enet;
+- int err;
+-
+- netdev = devm_alloc_etherdev(dev, sizeof(*enet));
+- if (!netdev)
+- return -ENOMEM;
+-
+- enet = netdev_priv(netdev);
+- enet->dev = dev;
+- enet->netdev = netdev;
+-
+- enet->base = devm_platform_ioremap_resource(pdev, 0);
+- if (IS_ERR(enet->base)) {
+- dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base));
+- return PTR_ERR(enet->base);
+- }
+-
+- netdev->irq = platform_get_irq_byname(pdev, "rx");
+- if (netdev->irq < 0)
+- return netdev->irq;
+-
+- dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+-
+- err = bcm4908enet_dma_alloc(enet);
+- if (err)
+- return err;
+-
+- SET_NETDEV_DEV(netdev, &pdev->dev);
+- eth_hw_addr_random(netdev);
+- netdev->netdev_ops = &bcm96xx_netdev_ops;
+- netdev->min_mtu = ETH_ZLEN;
+- netdev->mtu = ENET_MTU_MAX;
+- netdev->max_mtu = ENET_MTU_MAX;
+- netif_napi_add(netdev, &enet->napi, bcm4908enet_poll, 64);
+-
+- err = register_netdev(netdev);
+- if (err) {
+- bcm4908enet_dma_free(enet);
+- return err;
+- }
+-
+- platform_set_drvdata(pdev, enet);
+-
+- return 0;
+-}
+-
+-static int bcm4908enet_remove(struct platform_device *pdev)
+-{
+- struct bcm4908enet *enet = platform_get_drvdata(pdev);
+-
+- unregister_netdev(enet->netdev);
+- netif_napi_del(&enet->napi);
+- bcm4908enet_dma_free(enet);
+-
+- return 0;
+-}
+-
+-static const struct of_device_id bcm4908enet_of_match[] = {
+- { .compatible = "brcm,bcm4908enet"},
+- {},
+-};
+-
+-static struct platform_driver bcm4908enet_driver = {
+- .driver = {
+- .name = "bcm4908enet",
+- .of_match_table = bcm4908enet_of_match,
+- },
+- .probe = bcm4908enet_probe,
+- .remove = bcm4908enet_remove,
+-};
+-module_platform_driver(bcm4908enet_driver);
+-
+-MODULE_LICENSE("GPL v2");
+-MODULE_DEVICE_TABLE(of, bcm4908enet_of_match);
+--- /dev/null
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -0,0 +1,677 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>
++ */
++
++#include <linux/delay.h>
++#include <linux/etherdevice.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++
++#include "bcm4908_enet.h"
++#include "unimac.h"
++
++#define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG
++#define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG
++#define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM
++#define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM
++
++#define ENET_TX_BDS_NUM 200
++#define ENET_RX_BDS_NUM 200
++#define ENET_RX_BDS_NUM_MAX 8192
++
++#define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \
++ ENET_DMA_CH_CFG_INT_NO_DESC | \
++ ENET_DMA_CH_CFG_INT_BUFF_DONE)
++#define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */
++
++#define ENET_MTU_MIN 60
++#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */
++#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */
++
++struct bcm4908_enet_dma_ring_bd {
++ __le32 ctl;
++ __le32 addr;
++} __packed;
++
++struct bcm4908_enet_dma_ring_slot {
++ struct sk_buff *skb;
++ unsigned int len;
++ dma_addr_t dma_addr;
++};
++
++struct bcm4908_enet_dma_ring {
++ int is_tx;
++ int read_idx;
++ int write_idx;
++ int length;
++ u16 cfg_block;
++ u16 st_ram_block;
++
++ union {
++ void *cpu_addr;
++ struct bcm4908_enet_dma_ring_bd *buf_desc;
++ };
++ dma_addr_t dma_addr;
++
++ struct bcm4908_enet_dma_ring_slot *slots;
++};
++
++struct bcm4908_enet {
++ struct device *dev;
++ struct net_device *netdev;
++ struct napi_struct napi;
++ void __iomem *base;
++
++ struct bcm4908_enet_dma_ring tx_ring;
++ struct bcm4908_enet_dma_ring rx_ring;
++};
++
++/***
++ * R/W ops
++ */
++
++static inline u32 enet_read(struct bcm4908_enet *enet, u16 offset)
++{
++ return readl(enet->base + offset);
++}
++
++static inline void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value)
++{
++ writel(value, enet->base + offset);
++}
++
++static inline void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)
++{
++ u32 val;
++
++ WARN_ON(set & ~mask);
++
++ val = enet_read(enet, offset);
++ val = (val & ~mask) | (set & mask);
++ enet_write(enet, offset, val);
++}
++
++static inline void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set)
++{
++ enet_maskset(enet, offset, set, set);
++}
++
++static inline u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset)
++{
++ return enet_read(enet, ENET_UNIMAC + offset);
++}
++
++static inline void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value)
++{
++ enet_write(enet, ENET_UNIMAC + offset, value);
++}
++
++static inline void enet_umac_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)
++{
++ enet_maskset(enet, ENET_UNIMAC + offset, mask, set);
++}
++
++static inline void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set)
++{
++ enet_set(enet, ENET_UNIMAC + offset, set);
++}
++
++/***
++ * Helpers
++ */
++
++static void bcm4908_enet_intrs_on(struct bcm4908_enet *enet)
++{
++ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
++}
++
++static void bcm4908_enet_intrs_off(struct bcm4908_enet *enet)
++{
++ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);
++}
++
++static void bcm4908_enet_intrs_ack(struct bcm4908_enet *enet)
++{
++ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
++}
++
++/***
++ * DMA
++ */
++
++static int bcm4908_dma_alloc_buf_descs(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
++{
++ int size = ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
++ struct device *dev = enet->dev;
++
++ ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);
++ if (!ring->cpu_addr)
++ return -ENOMEM;
++
++ if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {
++ dev_err(dev, "Invalid DMA ring alignment\n");
++ goto err_free_buf_descs;
++ }
++
++ ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL);
++ if (!ring->slots)
++ goto err_free_buf_descs;
++
++ memset(ring->cpu_addr, 0, size);
++
++ ring->read_idx = 0;
++ ring->write_idx = 0;
++
++ return 0;
++
++err_free_buf_descs:
++ dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);
++ return -ENOMEM;
++}
++
++static void bcm4908_enet_dma_free(struct bcm4908_enet *enet)
++{
++ struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
++ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
++ struct device *dev = enet->dev;
++ int size;
++
++ size = rx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
++ if (rx_ring->cpu_addr)
++ dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);
++ kfree(rx_ring->slots);
++
++ size = tx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
++ if (tx_ring->cpu_addr)
++ dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);
++ kfree(tx_ring->slots);
++}
++
++static int bcm4908_enet_dma_alloc(struct bcm4908_enet *enet)
++{
++ struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
++ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
++ struct device *dev = enet->dev;
++ int err;
++
++ tx_ring->length = ENET_TX_BDS_NUM;
++ tx_ring->is_tx = 1;
++ tx_ring->cfg_block = ENET_DMA_CH_TX_CFG;
++ tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;
++ err = bcm4908_dma_alloc_buf_descs(enet, tx_ring);
++ if (err) {
++ dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err);
++ return err;
++ }
++
++ rx_ring->length = ENET_RX_BDS_NUM;
++ rx_ring->is_tx = 0;
++ rx_ring->cfg_block = ENET_DMA_CH_RX_CFG;
++ rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;
++ err = bcm4908_dma_alloc_buf_descs(enet, rx_ring);
++ if (err) {
++ dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err);
++ bcm4908_enet_dma_free(enet);
++ return err;
++ }
++
++ return 0;
++}
++
++static void bcm4908_enet_dma_reset(struct bcm4908_enet *enet)
++{
++ struct bcm4908_enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };
++ int i;
++
++ /* Disable the DMA controller and channel */
++ for (i = 0; i < ARRAY_SIZE(rings); i++)
++ enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);
++ enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);
++
++ /* Reset channels state */
++ for (i = 0; i < ARRAY_SIZE(rings); i++) {
++ struct bcm4908_enet_dma_ring *ring = rings[i];
++
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);
++ }
++}
++
++static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx)
++{
++ struct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];
++ struct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];
++ struct device *dev = enet->dev;
++ u32 tmp;
++ int err;
++
++ slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;
++
++ slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
++ if (!slot->skb)
++ return -ENOMEM;
++
++ slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
++ err = dma_mapping_error(dev, slot->dma_addr);
++ if (err) {
++ dev_err(dev, "Failed to map DMA buffer: %d\n", err);
++ kfree_skb(slot->skb);
++ slot->skb = NULL;
++ return err;
++ }
++
++ tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
++ tmp |= DMA_CTL_STATUS_OWN;
++ if (idx == enet->rx_ring.length - 1)
++ tmp |= DMA_CTL_STATUS_WRAP;
++ buf_desc->ctl = cpu_to_le32(tmp);
++ buf_desc->addr = cpu_to_le32(slot->dma_addr);
++
++ return 0;
++}
++
++static void bcm4908_enet_dma_ring_init(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
++{
++ int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */
++ int reset_subch = ring->is_tx ? 1 : 0;
++
++ /* Reset the DMA channel */
++ enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));
++ enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);
++
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
++
++ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
++ (uint32_t)ring->dma_addr);
++}
++
++static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet)
++{
++ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
++ struct bcm4908_enet_dma_ring_slot *slot;
++ struct device *dev = enet->dev;
++ int i;
++
++ for (i = rx_ring->length - 1; i >= 0; i--) {
++ slot = &rx_ring->slots[i];
++ if (!slot->skb)
++ continue;
++ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
++ kfree_skb(slot->skb);
++ slot->skb = NULL;
++ }
++}
++
++static int bcm4908_enet_dma_init(struct bcm4908_enet *enet)
++{
++ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
++ struct device *dev = enet->dev;
++ int err;
++ int i;
++
++ for (i = 0; i < rx_ring->length; i++) {
++ err = bcm4908_enet_dma_alloc_rx_buf(enet, i);
++ if (err) {
++ dev_err(dev, "Failed to alloc RX buffer: %d\n", err);
++ bcm4908_enet_dma_uninit(enet);
++ return err;
++ }
++ }
++
++ bcm4908_enet_dma_ring_init(enet, &enet->tx_ring);
++ bcm4908_enet_dma_ring_init(enet, &enet->rx_ring);
++
++ return 0;
++}
++
++static void bcm4908_enet_dma_tx_ring_ensable(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
++{
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
++}
++
++static void bcm4908_enet_dma_tx_ring_disable(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
++{
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
++}
++
++static void bcm4908_enet_dma_rx_ring_enable(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
++{
++ enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
++}
++
++static void bcm4908_enet_dma_rx_ring_disable(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
++{
++ unsigned long deadline;
++ u32 tmp;
++
++ enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
++
++ deadline = jiffies + usecs_to_jiffies(2000);
++ do {
++ tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);
++ if (!(tmp & ENET_DMA_CH_CFG_ENABLE))
++ return;
++ enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
++ usleep_range(10, 30);
++ } while (!time_after_eq(jiffies, deadline));
++
++ dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n");
++}
++
++/***
++ * Ethernet driver
++ */
++
++static void bcm4908_enet_gmac_init(struct bcm4908_enet *enet)
++{
++ u32 cmd;
++
++ cmd = enet_umac_read(enet, UMAC_CMD);
++ enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);
++ enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);
++
++ enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);
++ enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);
++
++ enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);
++ enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);
++
++ cmd = enet_umac_read(enet, UMAC_CMD);
++ cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);
++ cmd &= ~CMD_TX_EN;
++ cmd &= ~CMD_RX_EN;
++ cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;
++ enet_umac_write(enet, UMAC_CMD, cmd);
++
++ enet_maskset(enet, ENET_GMAC_STATUS,
++ ENET_GMAC_STATUS_ETH_SPEED_MASK |
++ ENET_GMAC_STATUS_HD |
++ ENET_GMAC_STATUS_AUTO_CFG_EN |
++ ENET_GMAC_STATUS_LINK_UP,
++ ENET_GMAC_STATUS_ETH_SPEED_1000 |
++ ENET_GMAC_STATUS_AUTO_CFG_EN |
++ ENET_GMAC_STATUS_LINK_UP);
++}
++
++static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id)
++{
++ struct bcm4908_enet *enet = dev_id;
++
++ bcm4908_enet_intrs_off(enet);
++ bcm4908_enet_intrs_ack(enet);
++
++ napi_schedule(&enet->napi);
++
++ return IRQ_HANDLED;
++}
++
++static int bcm4908_enet_open(struct net_device *netdev)
++{
++ struct bcm4908_enet *enet = netdev_priv(netdev);
++ struct device *dev = enet->dev;
++ int err;
++
++ err = request_irq(netdev->irq, bcm4908_enet_irq_handler, 0, "enet", enet);
++ if (err) {
++ dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err);
++ return err;
++ }
++
++ bcm4908_enet_gmac_init(enet);
++ bcm4908_enet_dma_reset(enet);
++ bcm4908_enet_dma_init(enet);
++
++ enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
++
++ enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);
++ enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);
++ bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring);
++
++ napi_enable(&enet->napi);
++ netif_carrier_on(netdev);
++ netif_start_queue(netdev);
++
++ bcm4908_enet_intrs_ack(enet);
++ bcm4908_enet_intrs_on(enet);
++
++ return 0;
++}
++
++static int bcm4908_enet_stop(struct net_device *netdev)
++{
++ struct bcm4908_enet *enet = netdev_priv(netdev);
++
++ netif_stop_queue(netdev);
++ netif_carrier_off(netdev);
++ napi_disable(&enet->napi);
++
++ bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);
++ bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);
++
++ bcm4908_enet_dma_uninit(enet);
++
++ free_irq(enet->netdev->irq, enet);
++
++ return 0;
++}
++
++static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++{
++ struct bcm4908_enet *enet = netdev_priv(netdev);
++ struct bcm4908_enet_dma_ring *ring = &enet->tx_ring;
++ struct bcm4908_enet_dma_ring_slot *slot;
++ struct device *dev = enet->dev;
++ struct bcm4908_enet_dma_ring_bd *buf_desc;
++ int free_buf_descs;
++ u32 tmp;
++
++ /* Free transmitted skbs */
++ while (ring->read_idx != ring->write_idx) {
++ buf_desc = &ring->buf_desc[ring->read_idx];
++ if (buf_desc->ctl & DMA_CTL_STATUS_OWN)
++ break;
++ slot = &ring->slots[ring->read_idx];
++
++ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);
++ dev_kfree_skb(slot->skb);
++ if (++ring->read_idx == ring->length)
++ ring->read_idx = 0;
++ }
++
++ /* Don't use the last empty buf descriptor */
++ if (ring->read_idx <= ring->write_idx)
++ free_buf_descs = ring->read_idx - ring->write_idx + ring->length;
++ else
++ free_buf_descs = ring->read_idx - ring->write_idx;
++ if (free_buf_descs < 2)
++ return NETDEV_TX_BUSY;
++
++ /* Hardware removes OWN bit after sending data */
++ buf_desc = &ring->buf_desc[ring->write_idx];
++ if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {
++ netif_stop_queue(netdev);
++ return NETDEV_TX_BUSY;
++ }
++
++ slot = &ring->slots[ring->write_idx];
++ slot->skb = skb;
++ slot->len = skb->len;
++ slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
++ if (unlikely(dma_mapping_error(dev, slot->dma_addr)))
++ return NETDEV_TX_BUSY;
++
++ tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
++ tmp |= DMA_CTL_STATUS_OWN;
++ tmp |= DMA_CTL_STATUS_SOP;
++ tmp |= DMA_CTL_STATUS_EOP;
++ tmp |= DMA_CTL_STATUS_APPEND_CRC;
++ if (ring->write_idx + 1 == ring->length - 1)
++ tmp |= DMA_CTL_STATUS_WRAP;
++
++ buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
++ buf_desc->ctl = cpu_to_le32(tmp);
++
++ bcm4908_enet_dma_tx_ring_ensable(enet, &enet->tx_ring);
++
++ if (++ring->write_idx == ring->length - 1)
++ ring->write_idx = 0;
++ enet->netdev->stats.tx_bytes += skb->len;
++ enet->netdev->stats.tx_packets++;
++
++ return NETDEV_TX_OK;
++}
++
++static int bcm4908_enet_poll(struct napi_struct *napi, int weight)
++{
++ struct bcm4908_enet *enet = container_of(napi, struct bcm4908_enet, napi);
++ struct device *dev = enet->dev;
++ int handled = 0;
++
++ while (handled < weight) {
++ struct bcm4908_enet_dma_ring_bd *buf_desc;
++ struct bcm4908_enet_dma_ring_slot slot;
++ u32 ctl;
++ int len;
++ int err;
++
++ buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];
++ ctl = le32_to_cpu(buf_desc->ctl);
++ if (ctl & DMA_CTL_STATUS_OWN)
++ break;
++
++ slot = enet->rx_ring.slots[enet->rx_ring.read_idx];
++
++ /* Provide new buffer before unpinning the old one */
++ err = bcm4908_enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);
++ if (err)
++ break;
++
++ if (++enet->rx_ring.read_idx == enet->rx_ring.length)
++ enet->rx_ring.read_idx = 0;
++
++ len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
++
++ if (len < ENET_MTU_MIN ||
++ (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
++ enet->netdev->stats.rx_dropped++;
++ break;
++ }
++
++ dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
++
++ skb_put(slot.skb, len - 4 + 2);
++ slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
++ netif_receive_skb(slot.skb);
++
++ enet->netdev->stats.rx_packets++;
++ enet->netdev->stats.rx_bytes += len;
++ }
++
++ if (handled < weight) {
++ napi_complete_done(napi, handled);
++ bcm4908_enet_intrs_on(enet);
++ }
++
++ return handled;
++}
++
++static const struct net_device_ops bcm96xx_netdev_ops = {
++ .ndo_open = bcm4908_enet_open,
++ .ndo_stop = bcm4908_enet_stop,
++ .ndo_start_xmit = bcm4908_enet_start_xmit,
++ .ndo_set_mac_address = eth_mac_addr,
++};
++
++static int bcm4908_enet_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct net_device *netdev;
++ struct bcm4908_enet *enet;
++ int err;
++
++ netdev = devm_alloc_etherdev(dev, sizeof(*enet));
++ if (!netdev)
++ return -ENOMEM;
++
++ enet = netdev_priv(netdev);
++ enet->dev = dev;
++ enet->netdev = netdev;
++
++ enet->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(enet->base)) {
++ dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base));
++ return PTR_ERR(enet->base);
++ }
++
++ netdev->irq = platform_get_irq_byname(pdev, "rx");
++ if (netdev->irq < 0)
++ return netdev->irq;
++
++ dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
++
++ err = bcm4908_enet_dma_alloc(enet);
++ if (err)
++ return err;
++
++ SET_NETDEV_DEV(netdev, &pdev->dev);
++ eth_hw_addr_random(netdev);
++ netdev->netdev_ops = &bcm96xx_netdev_ops;
++ netdev->min_mtu = ETH_ZLEN;
++ netdev->mtu = ENET_MTU_MAX;
++ netdev->max_mtu = ENET_MTU_MAX;
++ netif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64);
++
++ err = register_netdev(netdev);
++ if (err) {
++ bcm4908_enet_dma_free(enet);
++ return err;
++ }
++
++ platform_set_drvdata(pdev, enet);
++
++ return 0;
++}
++
++static int bcm4908_enet_remove(struct platform_device *pdev)
++{
++ struct bcm4908_enet *enet = platform_get_drvdata(pdev);
++
++ unregister_netdev(enet->netdev);
++ netif_napi_del(&enet->napi);
++ bcm4908_enet_dma_free(enet);
++
++ return 0;
++}
++
++static const struct of_device_id bcm4908_enet_of_match[] = {
++ { .compatible = "brcm,bcm4908-enet"},
++ {},
++};
++
++static struct platform_driver bcm4908_enet_driver = {
++ .driver = {
++ .name = "bcm4908_enet",
++ .of_match_table = bcm4908_enet_of_match,
++ },
++ .probe = bcm4908_enet_probe,
++ .remove = bcm4908_enet_remove,
++};
++module_platform_driver(bcm4908_enet_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_DEVICE_TABLE(of, bcm4908_enet_of_match);
+--- a/drivers/net/ethernet/broadcom/bcm4908enet.h
++++ /dev/null
+@@ -1,96 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-#ifndef __BCM4908ENET_H
+-#define __BCM4908ENET_H
+-
+-#define ENET_CONTROL 0x000
+-#define ENET_MIB_CTRL 0x004
+-#define ENET_MIB_CTRL_CLR_MIB 0x00000001
+-#define ENET_RX_ERR_MASK 0x008
+-#define ENET_MIB_MAX_PKT_SIZE 0x00C
+-#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
+-#define ENET_DIAG_OUT 0x01c
+-#define ENET_ENABLE_DROP_PKT 0x020
+-#define ENET_IRQ_ENABLE 0x024
+-#define ENET_IRQ_ENABLE_OVFL 0x00000001
+-#define ENET_GMAC_STATUS 0x028
+-#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003
+-#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000
+-#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001
+-#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002
+-#define ENET_GMAC_STATUS_HD 0x00000004
+-#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008
+-#define ENET_GMAC_STATUS_LINK_UP 0x00000010
+-#define ENET_IRQ_STATUS 0x02c
+-#define ENET_IRQ_STATUS_OVFL 0x00000001
+-#define ENET_OVERFLOW_COUNTER 0x030
+-#define ENET_FLUSH 0x034
+-#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001
+-#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002
+-#define ENET_RSV_SELECT 0x038
+-#define ENET_BP_FORCE 0x03c
+-#define ENET_BP_FORCE_FORCE 0x00000001
+-#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040
+-#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f
+-#define ENET_TX_CRC_CTRL 0x044
+-#define ENET_MIB 0x200
+-#define ENET_UNIMAC 0x400
+-#define ENET_DMA 0x800
+-#define ENET_DMA_CONTROLLER_CFG 0x800
+-#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001
+-#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002
+-#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004
+-#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804
+-#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808
+-#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c
+-#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000
+-#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810
+-#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814
+-#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818
+-#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C
+-#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820
+-#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824
+-#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828
+-#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C
+-#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830
+-#define ENET_DMA_CTRL_CHANNEL_RESET 0x834
+-#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838
+-#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840
+-#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844
+-#define ENET_DMA_CH0_CFG 0xa00 /* RX */
+-#define ENET_DMA_CH1_CFG 0xa10 /* TX */
+-#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */
+-#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */
+-
+-#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */
+-#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */
+-#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */
+-#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */
+-#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */
+-#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */
+-#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */
+-#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */
+-#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */
+-#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */
+-#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
+-#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */
+-#define ENET_DMA_CH_CFG_SIZE 0x10
+-
+-#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */
+-#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */
+-#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */
+-#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */
+-#define ENET_DMA_CH_STATE_RAM_SIZE 0x10
+-
+-#define DMA_CTL_STATUS_APPEND_CRC 0x00000100
+-#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200
+-#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */
+-#define DMA_CTL_STATUS_WRAP 0x00001000 /* */
+-#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */
+-#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */
+-#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */
+-#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000
+-#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16
+-#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000
+-#define DMA_CTL_LEN_DESC_USEFPM 0x80000000
+-
+-#endif
+--- /dev/null
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.h
+@@ -0,0 +1,96 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++#ifndef __BCM4908_ENET_H
++#define __BCM4908_ENET_H
++
++#define ENET_CONTROL 0x000
++#define ENET_MIB_CTRL 0x004
++#define ENET_MIB_CTRL_CLR_MIB 0x00000001
++#define ENET_RX_ERR_MASK 0x008
++#define ENET_MIB_MAX_PKT_SIZE 0x00C
++#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
++#define ENET_DIAG_OUT 0x01c
++#define ENET_ENABLE_DROP_PKT 0x020
++#define ENET_IRQ_ENABLE 0x024
++#define ENET_IRQ_ENABLE_OVFL 0x00000001
++#define ENET_GMAC_STATUS 0x028
++#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003
++#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000
++#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001
++#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002
++#define ENET_GMAC_STATUS_HD 0x00000004
++#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008
++#define ENET_GMAC_STATUS_LINK_UP 0x00000010
++#define ENET_IRQ_STATUS 0x02c
++#define ENET_IRQ_STATUS_OVFL 0x00000001
++#define ENET_OVERFLOW_COUNTER 0x030
++#define ENET_FLUSH 0x034
++#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001
++#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002
++#define ENET_RSV_SELECT 0x038
++#define ENET_BP_FORCE 0x03c
++#define ENET_BP_FORCE_FORCE 0x00000001
++#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040
++#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f
++#define ENET_TX_CRC_CTRL 0x044
++#define ENET_MIB 0x200
++#define ENET_UNIMAC 0x400
++#define ENET_DMA 0x800
++#define ENET_DMA_CONTROLLER_CFG 0x800
++#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001
++#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002
++#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004
++#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804
++#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808
++#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c
++#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000
++#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810
++#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814
++#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818
++#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C
++#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820
++#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824
++#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828
++#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C
++#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830
++#define ENET_DMA_CTRL_CHANNEL_RESET 0x834
++#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838
++#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840
++#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844
++#define ENET_DMA_CH0_CFG 0xa00 /* RX */
++#define ENET_DMA_CH1_CFG 0xa10 /* TX */
++#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */
++#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */
++
++#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */
++#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */
++#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */
++#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */
++#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */
++#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */
++#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */
++#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */
++#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */
++#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */
++#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
++#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */
++#define ENET_DMA_CH_CFG_SIZE 0x10
++
++#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */
++#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */
++#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */
++#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */
++#define ENET_DMA_CH_STATE_RAM_SIZE 0x10
++
++#define DMA_CTL_STATUS_APPEND_CRC 0x00000100
++#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200
++#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */
++#define DMA_CTL_STATUS_WRAP 0x00001000 /* */
++#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */
++#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */
++#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */
++#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000
++#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16
++#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000
++#define DMA_CTL_LEN_DESC_USEFPM 0x80000000
++
++#endif
--- /dev/null
+From af263af64683f018be9ce3c309edfa9903f5109a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Feb 2021 13:12:35 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: drop unneeded memset()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+dma_alloc_coherent takes care of zeroing allocated memory
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -163,8 +163,6 @@ static int bcm4908_dma_alloc_buf_descs(s
+ if (!ring->slots)
+ goto err_free_buf_descs;
+
+- memset(ring->cpu_addr, 0, size);
+-
+ ring->read_idx = 0;
+ ring->write_idx = 0;
+
--- /dev/null
+From 7b778ae4eb9cd6e1518e4e47902a104b13ae8929 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Feb 2021 13:12:36 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: drop "inline" from C functions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It seems preferred to let compiler optimize code if applicable.
+While at it drop unused enet_umac_maskset().
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 19 +++++++------------
+ 1 file changed, 7 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -75,17 +75,17 @@ struct bcm4908_enet {
+ * R/W ops
+ */
+
+-static inline u32 enet_read(struct bcm4908_enet *enet, u16 offset)
++static u32 enet_read(struct bcm4908_enet *enet, u16 offset)
+ {
+ return readl(enet->base + offset);
+ }
+
+-static inline void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value)
++static void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value)
+ {
+ writel(value, enet->base + offset);
+ }
+
+-static inline void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)
++static void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)
+ {
+ u32 val;
+
+@@ -96,27 +96,22 @@ static inline void enet_maskset(struct b
+ enet_write(enet, offset, val);
+ }
+
+-static inline void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set)
++static void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set)
+ {
+ enet_maskset(enet, offset, set, set);
+ }
+
+-static inline u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset)
++static u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset)
+ {
+ return enet_read(enet, ENET_UNIMAC + offset);
+ }
+
+-static inline void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value)
++static void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value)
+ {
+ enet_write(enet, ENET_UNIMAC + offset, value);
+ }
+
+-static inline void enet_umac_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)
+-{
+- enet_maskset(enet, ENET_UNIMAC + offset, mask, set);
+-}
+-
+-static inline void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set)
++static void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set)
+ {
+ enet_set(enet, ENET_UNIMAC + offset, set);
+ }
--- /dev/null
+From e3948811720341f99cd5cb4a8a650473400ec4f8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Feb 2021 13:12:37 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: fix minor typos
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+1. Fix "ensable" typo noticed by Andrew
+2. Fix chipset name in the struct net_device_ops variable
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -328,8 +328,8 @@ static int bcm4908_enet_dma_init(struct
+ return 0;
+ }
+
+-static void bcm4908_enet_dma_tx_ring_ensable(struct bcm4908_enet *enet,
+- struct bcm4908_enet_dma_ring *ring)
++static void bcm4908_enet_dma_tx_ring_enable(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
+ {
+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
+ }
+@@ -519,7 +519,7 @@ static int bcm4908_enet_start_xmit(struc
+ buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
+ buf_desc->ctl = cpu_to_le32(tmp);
+
+- bcm4908_enet_dma_tx_ring_ensable(enet, &enet->tx_ring);
++ bcm4908_enet_dma_tx_ring_enable(enet, &enet->tx_ring);
+
+ if (++ring->write_idx == ring->length - 1)
+ ring->write_idx = 0;
+@@ -583,7 +583,7 @@ static int bcm4908_enet_poll(struct napi
+ return handled;
+ }
+
+-static const struct net_device_ops bcm96xx_netdev_ops = {
++static const struct net_device_ops bcm4908_enet_netdev_ops = {
+ .ndo_open = bcm4908_enet_open,
+ .ndo_stop = bcm4908_enet_stop,
+ .ndo_start_xmit = bcm4908_enet_start_xmit,
+@@ -623,7 +623,7 @@ static int bcm4908_enet_probe(struct pla
+
+ SET_NETDEV_DEV(netdev, &pdev->dev);
+ eth_hw_addr_random(netdev);
+- netdev->netdev_ops = &bcm96xx_netdev_ops;
++ netdev->netdev_ops = &bcm4908_enet_netdev_ops;
+ netdev->min_mtu = ETH_ZLEN;
+ netdev->mtu = ENET_MTU_MAX;
+ netdev->max_mtu = ENET_MTU_MAX;
--- /dev/null
+From 195e2d9febfbeef1d09701c387925e5c2f5cb038 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Feb 2021 13:12:38 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: fix received skb length
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use ETH_FCS_LEN instead of magic value and drop incorrect + 2
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -567,7 +567,7 @@ static int bcm4908_enet_poll(struct napi
+
+ dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
+
+- skb_put(slot.skb, len - 4 + 2);
++ skb_put(slot.skb, len - ETH_FCS_LEN);
+ slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
+ netif_receive_skb(slot.skb);
+
--- /dev/null
+From bdd70b997799099597fc0952fb0ec1bd80505bc4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Feb 2021 13:12:39 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: fix endianness in xmit code
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use le32_to_cpu() for reading __le32 struct field filled by hw.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -476,7 +476,7 @@ static int bcm4908_enet_start_xmit(struc
+ /* Free transmitted skbs */
+ while (ring->read_idx != ring->write_idx) {
+ buf_desc = &ring->buf_desc[ring->read_idx];
+- if (buf_desc->ctl & DMA_CTL_STATUS_OWN)
++ if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)
+ break;
+ slot = &ring->slots[ring->read_idx];
+
--- /dev/null
+From 14b3b46a67f78ade99eafcbf320105615e948569 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 12 Feb 2021 16:21:35 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: set MTU on open & on request
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Hardware comes up with default max frame size set to 1518. When using it
+with switch it results in actual Ethernet MTU 1492:
+1518 - 14 (Ethernet header) - 4 (Broadcom's tag) - 4 (802.1q) - 4 (FCS)
+
+Above means hardware in its default state can't handle standard Ethernet
+traffic (MTU 1500).
+
+Define maximum possible Ethernet overhead and always set MAC max frame
+length accordingly. This change fixes handling Ethernet frames of length
+1506 - 1514.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 31 ++++++++++++++++----
+ 1 file changed, 25 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -5,6 +5,7 @@
+
+ #include <linux/delay.h>
+ #include <linux/etherdevice.h>
++#include <linux/if_vlan.h>
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+@@ -29,9 +30,10 @@
+ ENET_DMA_CH_CFG_INT_BUFF_DONE)
+ #define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */
+
+-#define ENET_MTU_MIN 60
+-#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */
+-#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */
++#define ENET_MTU_MAX ETH_DATA_LEN /* Is it possible to support 2044? */
++#define BRCM_MAX_TAG_LEN 6
++#define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
++ ETH_FCS_LEN + 4) /* 32 */
+
+ struct bcm4908_enet_dma_ring_bd {
+ __le32 ctl;
+@@ -135,6 +137,11 @@ static void bcm4908_enet_intrs_ack(struc
+ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
+ }
+
++static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu)
++{
++ enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD);
++}
++
+ /***
+ * DMA
+ */
+@@ -246,7 +253,7 @@ static int bcm4908_enet_dma_alloc_rx_buf
+ u32 tmp;
+ int err;
+
+- slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;
++ slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD;
+
+ slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
+ if (!slot->skb)
+@@ -374,6 +381,8 @@ static void bcm4908_enet_gmac_init(struc
+ {
+ u32 cmd;
+
++ bcm4908_enet_set_mtu(enet, enet->netdev->mtu);
++
+ cmd = enet_umac_read(enet, UMAC_CMD);
+ enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);
+ enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);
+@@ -559,7 +568,7 @@ static int bcm4908_enet_poll(struct napi
+
+ len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
+
+- if (len < ENET_MTU_MIN ||
++ if (len < ETH_ZLEN ||
+ (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
+ enet->netdev->stats.rx_dropped++;
+ break;
+@@ -583,11 +592,21 @@ static int bcm4908_enet_poll(struct napi
+ return handled;
+ }
+
++static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu)
++{
++ struct bcm4908_enet *enet = netdev_priv(netdev);
++
++ bcm4908_enet_set_mtu(enet, new_mtu);
++
++ return 0;
++}
++
+ static const struct net_device_ops bcm4908_enet_netdev_ops = {
+ .ndo_open = bcm4908_enet_open,
+ .ndo_stop = bcm4908_enet_stop,
+ .ndo_start_xmit = bcm4908_enet_start_xmit,
+ .ndo_set_mac_address = eth_mac_addr,
++ .ndo_change_mtu = bcm4908_enet_change_mtu,
+ };
+
+ static int bcm4908_enet_probe(struct platform_device *pdev)
+@@ -625,7 +644,7 @@ static int bcm4908_enet_probe(struct pla
+ eth_hw_addr_random(netdev);
+ netdev->netdev_ops = &bcm4908_enet_netdev_ops;
+ netdev->min_mtu = ETH_ZLEN;
+- netdev->mtu = ENET_MTU_MAX;
++ netdev->mtu = ETH_DATA_LEN;
+ netdev->max_mtu = ENET_MTU_MAX;
+ netif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64);
+
--- /dev/null
+From 4dc7f09b8becfa35a55430a49d95acf19f996e6b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 24 Feb 2021 16:18:41 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: fix RX path possible mem leak
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+After filling RX ring slot with new skb it's required to free old skb.
+Immediately on error or later in the net subsystem.
+
+Fixes: 4feffeadbcb2 ("net: broadcom: bcm4908enet: add BCM4908 controller driver")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20210224151842.2419-1-zajec5@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -570,6 +570,7 @@ static int bcm4908_enet_poll(struct napi
+
+ if (len < ETH_ZLEN ||
+ (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
++ kfree_skb(slot.skb);
+ enet->netdev->stats.rx_dropped++;
+ break;
+ }
--- /dev/null
+From 4d9274cee40b6a20dd6148c6c81c6733c2678cbc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 24 Feb 2021 16:18:42 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: fix NAPI poll returned value
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Missing increment was resulting in poll function always returning 0
+instead of amount of processed packets.
+
+Fixes: 4feffeadbcb2 ("net: broadcom: bcm4908enet: add BCM4908 controller driver")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20210224151842.2419-2-zajec5@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -583,6 +583,8 @@ static int bcm4908_enet_poll(struct napi
+
+ enet->netdev->stats.rx_packets++;
+ enet->netdev->stats.rx_bytes += len;
++
++ handled++;
+ }
+
+ if (handled < weight) {
--- /dev/null
+From d313d16bbaea0f11a2e98f04a6c678b43c208915 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 26 Feb 2021 14:20:38 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: enable RX after processing
+ packets
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When receiving a lot of packets hardware may run out of free
+descriptiors and stop RX ring. Enable it every time after handling
+received packets.
+
+Fixes: 4feffeadbcb2 ("net: broadcom: bcm4908enet: add BCM4908 controller driver")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20210226132038.29849-1-zajec5@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -592,6 +592,9 @@ static int bcm4908_enet_poll(struct napi
+ bcm4908_enet_intrs_on(enet);
+ }
+
++ /* Hardware could disable ring if it run out of descriptors */
++ bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring);
++
+ return handled;
+ }
+
--- /dev/null
+From a3bc483216650a7232559bf0a1debfbabff3e12c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 16 Mar 2021 15:03:41 +0100
+Subject: [PATCH] net: broadcom: BCM4908_ENET should not default to y,
+ unconditionally
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Merely enabling compile-testing should not enable additional code.
+To fix this, restrict the automatic enabling of BCM4908_ENET to
+ARCH_BCM4908.
+
+Fixes: 4feffeadbcb2e5b1 ("net: broadcom: bcm4908enet: add BCM4908 controller driver")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Acked-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/broadcom/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/broadcom/Kconfig
++++ b/drivers/net/ethernet/broadcom/Kconfig
+@@ -54,7 +54,7 @@ config B44_PCI
+ config BCM4908_ENET
+ tristate "Broadcom BCM4908 internal mac support"
+ depends on ARCH_BCM4908 || COMPILE_TEST
+- default y
++ default y if ARCH_BCM4908
+ help
+ This driver supports Ethernet controller integrated into Broadcom
+ BCM4908 family SoCs.
--- /dev/null
+From 3559c1ea4336636c886002996d50805365d3055c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 10 Mar 2021 09:48:13 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: read MAC from OF
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 devices have MAC address accessible using NVMEM so it's needed
+to use OF helper for reading it.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -9,6 +9,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_net.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
+ #include <linux/string.h>
+@@ -647,7 +648,9 @@ static int bcm4908_enet_probe(struct pla
+ return err;
+
+ SET_NETDEV_DEV(netdev, &pdev->dev);
+- eth_hw_addr_random(netdev);
++ of_get_mac_address(dev->of_node, netdev->dev_addr);
++ if (!is_valid_ether_addr(netdev->dev_addr))
++ eth_hw_addr_random(netdev);
+ netdev->netdev_ops = &bcm4908_enet_netdev_ops;
+ netdev->min_mtu = ETH_ZLEN;
+ netdev->mtu = ETH_DATA_LEN;
--- /dev/null
+From ab4dda7a8cb7e55ea3d92fd5e249cf6f5396028c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Mar 2021 13:35:20 +0100
+Subject: [PATCH] dt-bindings: net: bcm4908-enet: add optional TX interrupt
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+I discovered that hardware actually supports two interrupts, one per DMA
+channel (RX and TX).
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ .../bindings/net/brcm,bcm4908-enet.yaml | 17 +++++++++++++----
+ 1 file changed, 13 insertions(+), 4 deletions(-)
+
+--- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
++++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
+@@ -22,10 +22,18 @@ properties:
+ maxItems: 1
+
+ interrupts:
+- description: RX interrupt
++ minItems: 1
++ maxItems: 2
++ items:
++ - description: RX interrupt
++ - description: TX interrupt
+
+ interrupt-names:
+- const: rx
++ minItems: 1
++ maxItems: 2
++ items:
++ - const: rx
++ - const: tx
+
+ required:
+ - reg
+@@ -43,6 +51,7 @@ examples:
+ compatible = "brcm,bcm4908-enet";
+ reg = <0x80002000 0x1000>;
+
+- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "rx";
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "rx", "tx";
+ };
--- /dev/null
+From 12bb508bfe5a564c36864b12253db23cac83bfa1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Mar 2021 13:35:21 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: support TX interrupt
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It appears that each DMA channel has its own interrupt and both rings
+can be configured (the same way) to handle interrupts.
+
+1. Make ring interrupts code generic (make it operate on given ring)
+2. Move napi to ring (so each has its own)
+3. Make IRQ handler generic (match ring against received IRQ number)
+4. Add (optional) support for TX interrupt
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 138 ++++++++++++++-----
+ 1 file changed, 103 insertions(+), 35 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -54,6 +54,7 @@ struct bcm4908_enet_dma_ring {
+ int length;
+ u16 cfg_block;
+ u16 st_ram_block;
++ struct napi_struct napi;
+
+ union {
+ void *cpu_addr;
+@@ -67,8 +68,8 @@ struct bcm4908_enet_dma_ring {
+ struct bcm4908_enet {
+ struct device *dev;
+ struct net_device *netdev;
+- struct napi_struct napi;
+ void __iomem *base;
++ int irq_tx;
+
+ struct bcm4908_enet_dma_ring tx_ring;
+ struct bcm4908_enet_dma_ring rx_ring;
+@@ -123,24 +124,31 @@ static void enet_umac_set(struct bcm4908
+ * Helpers
+ */
+
+-static void bcm4908_enet_intrs_on(struct bcm4908_enet *enet)
++static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu)
+ {
+- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
++ enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD);
+ }
+
+-static void bcm4908_enet_intrs_off(struct bcm4908_enet *enet)
++/***
++ * DMA ring ops
++ */
++
++static void bcm4908_enet_dma_ring_intrs_on(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
+ {
+- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
+ }
+
+-static void bcm4908_enet_intrs_ack(struct bcm4908_enet *enet)
++static void bcm4908_enet_dma_ring_intrs_off(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
+ {
+- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
+ }
+
+-static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu)
++static void bcm4908_enet_dma_ring_intrs_ack(struct bcm4908_enet *enet,
++ struct bcm4908_enet_dma_ring *ring)
+ {
+- enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD);
++ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
+ }
+
+ /***
+@@ -414,11 +422,14 @@ static void bcm4908_enet_gmac_init(struc
+ static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id)
+ {
+ struct bcm4908_enet *enet = dev_id;
++ struct bcm4908_enet_dma_ring *ring;
+
+- bcm4908_enet_intrs_off(enet);
+- bcm4908_enet_intrs_ack(enet);
++ ring = (irq == enet->irq_tx) ? &enet->tx_ring : &enet->rx_ring;
+
+- napi_schedule(&enet->napi);
++ bcm4908_enet_dma_ring_intrs_off(enet, ring);
++ bcm4908_enet_dma_ring_intrs_ack(enet, ring);
++
++ napi_schedule(&ring->napi);
+
+ return IRQ_HANDLED;
+ }
+@@ -426,6 +437,8 @@ static irqreturn_t bcm4908_enet_irq_hand
+ static int bcm4908_enet_open(struct net_device *netdev)
+ {
+ struct bcm4908_enet *enet = netdev_priv(netdev);
++ struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
++ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
+ struct device *dev = enet->dev;
+ int err;
+
+@@ -435,6 +448,17 @@ static int bcm4908_enet_open(struct net_
+ return err;
+ }
+
++ if (enet->irq_tx > 0) {
++ err = request_irq(enet->irq_tx, bcm4908_enet_irq_handler, 0,
++ "tx", enet);
++ if (err) {
++ dev_err(dev, "Failed to request IRQ %d: %d\n",
++ enet->irq_tx, err);
++ free_irq(netdev->irq, enet);
++ return err;
++ }
++ }
++
+ bcm4908_enet_gmac_init(enet);
+ bcm4908_enet_dma_reset(enet);
+ bcm4908_enet_dma_init(enet);
+@@ -443,14 +467,19 @@ static int bcm4908_enet_open(struct net_
+
+ enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);
+ enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);
+- bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring);
+
+- napi_enable(&enet->napi);
++ if (enet->irq_tx > 0) {
++ napi_enable(&tx_ring->napi);
++ bcm4908_enet_dma_ring_intrs_ack(enet, tx_ring);
++ bcm4908_enet_dma_ring_intrs_on(enet, tx_ring);
++ }
++
++ bcm4908_enet_dma_rx_ring_enable(enet, rx_ring);
++ napi_enable(&rx_ring->napi);
+ netif_carrier_on(netdev);
+ netif_start_queue(netdev);
+-
+- bcm4908_enet_intrs_ack(enet);
+- bcm4908_enet_intrs_on(enet);
++ bcm4908_enet_dma_ring_intrs_ack(enet, rx_ring);
++ bcm4908_enet_dma_ring_intrs_on(enet, rx_ring);
+
+ return 0;
+ }
+@@ -458,16 +487,20 @@ static int bcm4908_enet_open(struct net_
+ static int bcm4908_enet_stop(struct net_device *netdev)
+ {
+ struct bcm4908_enet *enet = netdev_priv(netdev);
++ struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
++ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
+
+ netif_stop_queue(netdev);
+ netif_carrier_off(netdev);
+- napi_disable(&enet->napi);
++ napi_disable(&rx_ring->napi);
++ napi_disable(&tx_ring->napi);
+
+ bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);
+ bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);
+
+ bcm4908_enet_dma_uninit(enet);
+
++ free_irq(enet->irq_tx, enet);
+ free_irq(enet->netdev->irq, enet);
+
+ return 0;
+@@ -484,25 +517,19 @@ static int bcm4908_enet_start_xmit(struc
+ u32 tmp;
+
+ /* Free transmitted skbs */
+- while (ring->read_idx != ring->write_idx) {
+- buf_desc = &ring->buf_desc[ring->read_idx];
+- if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)
+- break;
+- slot = &ring->slots[ring->read_idx];
+-
+- dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);
+- dev_kfree_skb(slot->skb);
+- if (++ring->read_idx == ring->length)
+- ring->read_idx = 0;
+- }
++ if (enet->irq_tx < 0 &&
++ !(le32_to_cpu(ring->buf_desc[ring->read_idx].ctl) & DMA_CTL_STATUS_OWN))
++ napi_schedule(&enet->tx_ring.napi);
+
+ /* Don't use the last empty buf descriptor */
+ if (ring->read_idx <= ring->write_idx)
+ free_buf_descs = ring->read_idx - ring->write_idx + ring->length;
+ else
+ free_buf_descs = ring->read_idx - ring->write_idx;
+- if (free_buf_descs < 2)
++ if (free_buf_descs < 2) {
++ netif_stop_queue(netdev);
+ return NETDEV_TX_BUSY;
++ }
+
+ /* Hardware removes OWN bit after sending data */
+ buf_desc = &ring->buf_desc[ring->write_idx];
+@@ -539,9 +566,10 @@ static int bcm4908_enet_start_xmit(struc
+ return NETDEV_TX_OK;
+ }
+
+-static int bcm4908_enet_poll(struct napi_struct *napi, int weight)
++static int bcm4908_enet_poll_rx(struct napi_struct *napi, int weight)
+ {
+- struct bcm4908_enet *enet = container_of(napi, struct bcm4908_enet, napi);
++ struct bcm4908_enet_dma_ring *rx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi);
++ struct bcm4908_enet *enet = container_of(rx_ring, struct bcm4908_enet, rx_ring);
+ struct device *dev = enet->dev;
+ int handled = 0;
+
+@@ -590,7 +618,7 @@ static int bcm4908_enet_poll(struct napi
+
+ if (handled < weight) {
+ napi_complete_done(napi, handled);
+- bcm4908_enet_intrs_on(enet);
++ bcm4908_enet_dma_ring_intrs_on(enet, rx_ring);
+ }
+
+ /* Hardware could disable ring if it run out of descriptors */
+@@ -599,6 +627,42 @@ static int bcm4908_enet_poll(struct napi
+ return handled;
+ }
+
++static int bcm4908_enet_poll_tx(struct napi_struct *napi, int weight)
++{
++ struct bcm4908_enet_dma_ring *tx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi);
++ struct bcm4908_enet *enet = container_of(tx_ring, struct bcm4908_enet, tx_ring);
++ struct bcm4908_enet_dma_ring_bd *buf_desc;
++ struct bcm4908_enet_dma_ring_slot *slot;
++ struct device *dev = enet->dev;
++ unsigned int bytes = 0;
++ int handled = 0;
++
++ while (handled < weight && tx_ring->read_idx != tx_ring->write_idx) {
++ buf_desc = &tx_ring->buf_desc[tx_ring->read_idx];
++ if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)
++ break;
++ slot = &tx_ring->slots[tx_ring->read_idx];
++
++ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);
++ dev_kfree_skb(slot->skb);
++ bytes += slot->len;
++ if (++tx_ring->read_idx == tx_ring->length)
++ tx_ring->read_idx = 0;
++
++ handled++;
++ }
++
++ if (handled < weight) {
++ napi_complete_done(napi, handled);
++ bcm4908_enet_dma_ring_intrs_on(enet, tx_ring);
++ }
++
++ if (netif_queue_stopped(enet->netdev))
++ netif_wake_queue(enet->netdev);
++
++ return handled;
++}
++
+ static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu)
+ {
+ struct bcm4908_enet *enet = netdev_priv(netdev);
+@@ -641,6 +705,8 @@ static int bcm4908_enet_probe(struct pla
+ if (netdev->irq < 0)
+ return netdev->irq;
+
++ enet->irq_tx = platform_get_irq_byname(pdev, "tx");
++
+ dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+
+ err = bcm4908_enet_dma_alloc(enet);
+@@ -655,7 +721,8 @@ static int bcm4908_enet_probe(struct pla
+ netdev->min_mtu = ETH_ZLEN;
+ netdev->mtu = ETH_DATA_LEN;
+ netdev->max_mtu = ENET_MTU_MAX;
+- netif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64);
++ netif_tx_napi_add(netdev, &enet->tx_ring.napi, bcm4908_enet_poll_tx, NAPI_POLL_WEIGHT);
++ netif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT);
+
+ err = register_netdev(netdev);
+ if (err) {
+@@ -673,7 +740,8 @@ static int bcm4908_enet_remove(struct pl
+ struct bcm4908_enet *enet = platform_get_drvdata(pdev);
+
+ unregister_netdev(enet->netdev);
+- netif_napi_del(&enet->napi);
++ netif_napi_del(&enet->rx_ring.napi);
++ netif_napi_del(&enet->tx_ring.napi);
+ bcm4908_enet_dma_free(enet);
+
+ return 0;
--- /dev/null
+From 01488a0ccd9abe15565bed50a45afcddbb0fe199 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 12 Mar 2021 11:41:07 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: store PHY interface/mode in port structure
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's needed later for proper switch / crossbar setup.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/bcm_sf2.c | 16 ++++++++++++----
+ drivers/net/dsa/bcm_sf2.h | 1 +
+ 2 files changed, 13 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -446,10 +446,11 @@ static void bcm_sf2_intr_disable(struct
+ static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
+ struct device_node *dn)
+ {
++ struct device *dev = priv->dev->ds->dev;
++ struct bcm_sf2_port_status *port_st;
+ struct device_node *port;
+ unsigned int port_num;
+ struct property *prop;
+- phy_interface_t mode;
+ int err;
+
+ priv->moca_port = -1;
+@@ -458,19 +459,26 @@ static void bcm_sf2_identify_ports(struc
+ if (of_property_read_u32(port, "reg", &port_num))
+ continue;
+
++ if (port_num >= DSA_MAX_PORTS) {
++ dev_err(dev, "Invalid port number %d\n", port_num);
++ continue;
++ }
++
++ port_st = &priv->port_sts[port_num];
++
+ /* Internal PHYs get assigned a specific 'phy-mode' property
+ * value: "internal" to help flag them before MDIO probing
+ * has completed, since they might be turned off at that
+ * time
+ */
+- err = of_get_phy_mode(port, &mode);
++ err = of_get_phy_mode(port, &port_st->mode);
+ if (err)
+ continue;
+
+- if (mode == PHY_INTERFACE_MODE_INTERNAL)
++ if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)
+ priv->int_phy_mask |= 1 << port_num;
+
+- if (mode == PHY_INTERFACE_MODE_MOCA)
++ if (port_st->mode == PHY_INTERFACE_MODE_MOCA)
+ priv->moca_port = port_num;
+
+ if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
+--- a/drivers/net/dsa/bcm_sf2.h
++++ b/drivers/net/dsa/bcm_sf2.h
+@@ -44,6 +44,7 @@ struct bcm_sf2_hw_params {
+ #define BCM_SF2_REGS_NUM 6
+
+ struct bcm_sf2_port_status {
++ phy_interface_t mode;
+ unsigned int link;
+ bool enabled;
+ };
--- /dev/null
+From a9349f08ec6c1251d41ef167d27a15cc39bc5b97 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 12 Mar 2021 11:41:08 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: setup BCM4908 internal crossbar
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On some SoCs (e.g. BCM4908, BCM631[345]8) SF2 has an integrated
+crossbar. It allows connecting its selected external ports to internal
+ports. It's used by vendors to handle custom Ethernet setups.
+
+BCM4908 has following 3x2 crossbar. On Asus GT-AC5300 rgmii is used for
+connecting external BCM53134S switch. GPHY4 is usually used for WAN
+port. More fancy devices use SerDes for 2.5 Gbps Ethernet.
+
+ ┌──────────┐
+SerDes ─── 0 ─┤ │
+ │ 3x2 ├─ 0 ─── switch port 7
+ GPHY4 ─── 1 ─┤ │
+ │ crossbar ├─ 1 ─── runner (accelerator)
+ rgmii ─── 2 ─┤ │
+ └──────────┘
+
+Use setup data based on DT info to configure BCM4908's switch port 7.
+Right now only GPHY and rgmii variants are supported. Handling SerDes
+can be implemented later.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/bcm_sf2.c | 45 ++++++++++++++++++++++++++++++++++
+ drivers/net/dsa/bcm_sf2.h | 1 +
+ drivers/net/dsa/bcm_sf2_regs.h | 7 ++++++
+ 3 files changed, 53 insertions(+)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -435,6 +435,44 @@ static int bcm_sf2_sw_rst(struct bcm_sf2
+ return 0;
+ }
+
++static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
++{
++ struct device *dev = priv->dev->ds->dev;
++ int shift;
++ u32 mask;
++ u32 reg;
++ int i;
++
++ mask = BIT(priv->num_crossbar_int_ports) - 1;
++
++ reg = reg_readl(priv, REG_CROSSBAR);
++ switch (priv->type) {
++ case BCM4908_DEVICE_ID:
++ shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
++ reg &= ~(mask << shift);
++ if (0) /* FIXME */
++ reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
++ else if (priv->int_phy_mask & BIT(7))
++ reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
++ else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))
++ reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
++ else if (WARN(1, "Invalid port mode\n"))
++ return;
++ break;
++ default:
++ return;
++ }
++ reg_writel(priv, reg, REG_CROSSBAR);
++
++ reg = reg_readl(priv, REG_CROSSBAR);
++ for (i = 0; i < priv->num_crossbar_int_ports; i++) {
++ shift = i * priv->num_crossbar_int_ports;
++
++ dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
++ (reg >> shift) & mask);
++ }
++}
++
+ static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
+ {
+ intrl2_0_mask_set(priv, 0xffffffff);
+@@ -869,6 +907,8 @@ static int bcm_sf2_sw_resume(struct dsa_
+ return ret;
+ }
+
++ bcm_sf2_crossbar_setup(priv);
++
+ ret = bcm_sf2_cfp_resume(ds);
+ if (ret)
+ return ret;
+@@ -1140,6 +1180,7 @@ struct bcm_sf2_of_data {
+ const u16 *reg_offsets;
+ unsigned int core_reg_align;
+ unsigned int num_cfp_rules;
++ unsigned int num_crossbar_int_ports;
+ };
+
+ static const u16 bcm_sf2_4908_reg_offsets[] = {
+@@ -1164,6 +1205,7 @@ static const struct bcm_sf2_of_data bcm_
+ .core_reg_align = 0,
+ .reg_offsets = bcm_sf2_4908_reg_offsets,
+ .num_cfp_rules = 0, /* FIXME */
++ .num_crossbar_int_ports = 2,
+ };
+
+ /* Register offsets for the SWITCH_REG_* block */
+@@ -1274,6 +1316,7 @@ static int bcm_sf2_sw_probe(struct platf
+ priv->reg_offsets = data->reg_offsets;
+ priv->core_reg_align = data->core_reg_align;
+ priv->num_cfp_rules = data->num_cfp_rules;
++ priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
+
+ priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
+ "switch");
+@@ -1347,6 +1390,8 @@ static int bcm_sf2_sw_probe(struct platf
+ goto out_clk_mdiv;
+ }
+
++ bcm_sf2_crossbar_setup(priv);
++
+ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
+
+ ret = bcm_sf2_mdio_register(ds);
+--- a/drivers/net/dsa/bcm_sf2.h
++++ b/drivers/net/dsa/bcm_sf2.h
+@@ -74,6 +74,7 @@ struct bcm_sf2_priv {
+ const u16 *reg_offsets;
+ unsigned int core_reg_align;
+ unsigned int num_cfp_rules;
++ unsigned int num_crossbar_int_ports;
+
+ /* spinlock protecting access to the indirect registers */
+ spinlock_t indir_lock;
+--- a/drivers/net/dsa/bcm_sf2_regs.h
++++ b/drivers/net/dsa/bcm_sf2_regs.h
+@@ -48,6 +48,13 @@ enum bcm_sf2_reg_offs {
+ #define PHY_PHYAD_SHIFT 8
+ #define PHY_PHYAD_MASK 0x1F
+
++/* Relative to REG_CROSSBAR */
++#define CROSSBAR_BCM4908_INT_P7 0
++#define CROSSBAR_BCM4908_INT_RUNNER 1
++#define CROSSBAR_BCM4908_EXT_SERDES 0
++#define CROSSBAR_BCM4908_EXT_GPHY4 1
++#define CROSSBAR_BCM4908_EXT_RGMII 2
++
+ #define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x))
+
+ /* Relative to REG_RGMII_CNTRL */
--- /dev/null
+From f4e6d7cdbfae502788bc468295b232dec76ee57e Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Fri, 12 Mar 2021 13:11:01 -0800
+Subject: [PATCH] net: dsa: bcm_sf2: Fill in BCM4908 CFP entries
+
+The BCM4908 switch has 256 CFP entrie, update that setting so CFP can be
+used.
+
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/bcm_sf2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -1204,7 +1204,7 @@ static const struct bcm_sf2_of_data bcm_
+ .type = BCM4908_DEVICE_ID,
+ .core_reg_align = 0,
+ .reg_offsets = bcm_sf2_4908_reg_offsets,
+- .num_cfp_rules = 0, /* FIXME */
++ .num_cfp_rules = 256,
+ .num_crossbar_int_ports = 2,
+ };
+
--- /dev/null
+From 55cfeb396965c3906a84d09a9c487d065e37773b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 18 Mar 2021 09:01:42 +0100
+Subject: [PATCH 1/2] net: dsa: bcm_sf2: add function finding RGMII register
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Simple macro like REG_RGMII_CNTRL_P() is insufficient as:
+1. It doesn't validate port argument
+2. It doesn't support chipsets with non-lineral RGMII regs layout
+
+Missing port validation could result in getting register offset from out
+of array. Random memory -> random offset -> random reads/writes. It
+affected e.g. BCM4908 for REG_RGMII_CNTRL_P(7).
+
+Fixes: a78e86ed586d ("net: dsa: bcm_sf2: Prepare for different register layouts")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/bcm_sf2.c | 49 +++++++++++++++++++++++++++++-----
+ drivers/net/dsa/bcm_sf2_regs.h | 2 --
+ 2 files changed, 42 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -75,6 +75,31 @@ static void bcm_sf2_recalc_clock(struct
+ clk_set_rate(priv->clk_mdiv, new_rate);
+ }
+
++static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
++{
++ switch (priv->type) {
++ case BCM4908_DEVICE_ID:
++ /* TODO */
++ break;
++ default:
++ switch (port) {
++ case 0:
++ return REG_RGMII_0_CNTRL;
++ case 1:
++ return REG_RGMII_1_CNTRL;
++ case 2:
++ return REG_RGMII_2_CNTRL;
++ default:
++ break;
++ }
++ }
++
++ WARN_ONCE(1, "Unsupported port %d\n", port);
++
++ /* RO fallback reg */
++ return REG_SWITCH_STATUS;
++}
++
+ static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
+ {
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
+@@ -693,6 +718,7 @@ static void bcm_sf2_sw_mac_config(struct
+ {
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
+ u32 id_mode_dis = 0, port_mode;
++ u32 reg_rgmii_ctrl;
+ u32 reg;
+
+ if (port == core_readl(priv, CORE_IMP0_PRT_ID))
+@@ -716,10 +742,12 @@ static void bcm_sf2_sw_mac_config(struct
+ return;
+ }
+
++ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
++
+ /* Clear id_mode_dis bit, and the existing port mode, let
+ * RGMII_MODE_EN bet set by mac_link_{up,down}
+ */
+- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
++ reg = reg_readl(priv, reg_rgmii_ctrl);
+ reg &= ~ID_MODE_DIS;
+ reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
+
+@@ -727,13 +755,14 @@ static void bcm_sf2_sw_mac_config(struct
+ if (id_mode_dis)
+ reg |= ID_MODE_DIS;
+
+- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
++ reg_writel(priv, reg, reg_rgmii_ctrl);
+ }
+
+ static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
+ phy_interface_t interface, bool link)
+ {
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
++ u32 reg_rgmii_ctrl;
+ u32 reg;
+
+ if (!phy_interface_mode_is_rgmii(interface) &&
+@@ -741,13 +770,15 @@ static void bcm_sf2_sw_mac_link_set(stru
+ interface != PHY_INTERFACE_MODE_REVMII)
+ return;
+
++ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
++
+ /* If the link is down, just disable the interface to conserve power */
+- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
++ reg = reg_readl(priv, reg_rgmii_ctrl);
+ if (link)
+ reg |= RGMII_MODE_EN;
+ else
+ reg &= ~RGMII_MODE_EN;
+- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
++ reg_writel(priv, reg, reg_rgmii_ctrl);
+ }
+
+ static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
+@@ -781,11 +812,15 @@ static void bcm_sf2_sw_mac_link_up(struc
+ {
+ struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
+ struct ethtool_eee *p = &priv->dev->ports[port].eee;
+- u32 reg, offset;
+
+ bcm_sf2_sw_mac_link_set(ds, port, interface, true);
+
+ if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
++ u32 reg_rgmii_ctrl;
++ u32 reg, offset;
++
++ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
++
+ if (priv->type == BCM4908_DEVICE_ID ||
+ priv->type == BCM7445_DEVICE_ID)
+ offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
+@@ -796,7 +831,7 @@ static void bcm_sf2_sw_mac_link_up(struc
+ interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+ interface == PHY_INTERFACE_MODE_MII ||
+ interface == PHY_INTERFACE_MODE_REVMII) {
+- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
++ reg = reg_readl(priv, reg_rgmii_ctrl);
+ reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
+
+ if (tx_pause)
+@@ -804,7 +839,7 @@ static void bcm_sf2_sw_mac_link_up(struc
+ if (rx_pause)
+ reg |= RX_PAUSE_EN;
+
+- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
++ reg_writel(priv, reg, reg_rgmii_ctrl);
+ }
+
+ reg = SW_OVERRIDE | LINK_STS;
+--- a/drivers/net/dsa/bcm_sf2_regs.h
++++ b/drivers/net/dsa/bcm_sf2_regs.h
+@@ -55,8 +55,6 @@ enum bcm_sf2_reg_offs {
+ #define CROSSBAR_BCM4908_EXT_GPHY4 1
+ #define CROSSBAR_BCM4908_EXT_RGMII 2
+
+-#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x))
+-
+ /* Relative to REG_RGMII_CNTRL */
+ #define RGMII_MODE_EN (1 << 0)
+ #define ID_MODE_DIS (1 << 1)
--- /dev/null
+From 6859d91549341c2ad769d482de58129f080c0f04 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 18 Mar 2021 09:01:43 +0100
+Subject: [PATCH 2/2] net: dsa: bcm_sf2: fix BCM4908 RGMII reg(s)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 has only 1 RGMII reg for controlling port 7.
+
+Fixes: 73b7a6047971 ("net: dsa: bcm_sf2: support BCM4908's integrated switch")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/bcm_sf2.c | 11 +++++++----
+ drivers/net/dsa/bcm_sf2_regs.h | 1 +
+ 2 files changed, 8 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -79,7 +79,12 @@ static u16 bcm_sf2_reg_rgmii_cntrl(struc
+ {
+ switch (priv->type) {
+ case BCM4908_DEVICE_ID:
+- /* TODO */
++ switch (port) {
++ case 7:
++ return REG_RGMII_11_CNTRL;
++ default:
++ break;
++ }
+ break;
+ default:
+ switch (port) {
+@@ -1223,9 +1228,7 @@ static const u16 bcm_sf2_4908_reg_offset
+ [REG_PHY_REVISION] = 0x14,
+ [REG_SPHY_CNTRL] = 0x24,
+ [REG_CROSSBAR] = 0xc8,
+- [REG_RGMII_0_CNTRL] = 0xe0,
+- [REG_RGMII_1_CNTRL] = 0xec,
+- [REG_RGMII_2_CNTRL] = 0xf8,
++ [REG_RGMII_11_CNTRL] = 0x014c,
+ [REG_LED_0_CNTRL] = 0x40,
+ [REG_LED_1_CNTRL] = 0x4c,
+ [REG_LED_2_CNTRL] = 0x58,
+--- a/drivers/net/dsa/bcm_sf2_regs.h
++++ b/drivers/net/dsa/bcm_sf2_regs.h
+@@ -21,6 +21,7 @@ enum bcm_sf2_reg_offs {
+ REG_RGMII_0_CNTRL,
+ REG_RGMII_1_CNTRL,
+ REG_RGMII_2_CNTRL,
++ REG_RGMII_11_CNTRL,
+ REG_LED_0_CNTRL,
+ REG_LED_1_CNTRL,
+ REG_LED_2_CNTRL,
--- /dev/null
+From f35a07f92616700733636c06dd6e5b6cdc807fe4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 25 Nov 2020 10:06:08 +0100
+Subject: [PATCH] tty: serial: bcm63xx: lower driver dependencies
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Hardware supported by bcm63xx is also used by BCM4908 SoCs family that
+is ARM64. In future more architectures may need it as well. There is
+nothing arch specific breaking compilation so just stick to requiring
+COMMON_CLK.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20201125090608.28442-1-zajec5@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/serial/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -1133,7 +1133,7 @@ config SERIAL_TIMBERDALE
+ config SERIAL_BCM63XX
+ tristate "Broadcom BCM63xx/BCM33xx UART support"
+ select SERIAL_CORE
+- depends on MIPS || ARM || COMPILE_TEST
++ depends on COMMON_CLK
+ help
+ This enables the driver for the onchip UART core found on
+ the following chipsets:
--- /dev/null
+From def26913b66fd94e431afecf28e09c08e8c02a35 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 27 Nov 2020 12:14:42 +0100
+Subject: [PATCH] reset: simple: add BCM4908 MISC PCIe reset controller support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's a trivial reset controller. One register with bit per PCIe core.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
+---
+ drivers/reset/Kconfig | 2 +-
+ drivers/reset/reset-simple.c | 2 ++
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/reset/Kconfig
++++ b/drivers/reset/Kconfig
+@@ -167,7 +167,7 @@ config RESET_SCMI
+
+ config RESET_SIMPLE
+ bool "Simple Reset Controller Driver" if COMPILE_TEST
+- default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
++ default ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
+ help
+ This enables a simple reset controller driver for reset lines that
+ that can be asserted and deasserted by toggling bits in a contiguous,
+--- a/drivers/reset/reset-simple.c
++++ b/drivers/reset/reset-simple.c
+@@ -146,6 +146,8 @@ static const struct of_device_id reset_s
+ { .compatible = "aspeed,ast2500-lpc-reset" },
+ { .compatible = "bitmain,bm1880-reset",
+ .data = &reset_simple_active_low },
++ { .compatible = "brcm,bcm4908-misc-pcie-reset",
++ .data = &reset_simple_active_low },
+ { .compatible = "snps,dw-high-reset" },
+ { .compatible = "snps,dw-low-reset",
+ .data = &reset_simple_active_low },
--- /dev/null
+From 82853543057f78d8a331272b70bc3f1e8cb0cbf4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 14 Dec 2020 19:07:42 +0100
+Subject: [PATCH] dt-bindings: power: document Broadcom's PMB binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Broadcom's PMB is power controller used for disabling and enabling SoC
+devices.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../bindings/power/brcm,bcm-pmb.yaml | 50 +++++++++++++++++++
+ include/dt-bindings/soc/bcm-pmb.h | 11 ++++
+ 2 files changed, 61 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml
+ create mode 100644 include/dt-bindings/soc/bcm-pmb.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml
+@@ -0,0 +1,50 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/power/brcm,bcm-pmb.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Broadcom PMB (Power Management Bus) controller
++
++description: This document describes Broadcom's PMB controller. It supports
++ powering various types of connected devices (e.g. PCIe, USB, SATA).
++
++maintainers:
++ - Rafał Miłecki <rafal@milecki.pl>
++
++properties:
++ compatible:
++ enum:
++ - brcm,bcm4908-pmb
++
++ reg:
++ description: register space of one or more buses
++ maxItems: 1
++
++ big-endian:
++ $ref: /schemas/types.yaml#/definitions/flag
++ description: Flag to use for block working in big endian mode.
++
++ "#power-domain-cells":
++ description: cell specifies device ID (see bcm-pmb.h)
++ const: 1
++
++required:
++ - reg
++ - "#power-domain-cells"
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/soc/bcm-pmb.h>
++
++ pmb: power-controller@802800e0 {
++ compatible = "brcm,bcm4908-pmb";
++ reg = <0x802800e0 0x40>;
++ #power-domain-cells = <1>;
++ };
++
++ foo {
++ power-domains = <&pmb BCM_PMB_PCIE0>;
++ };
+--- /dev/null
++++ b/include/dt-bindings/soc/bcm-pmb.h
+@@ -0,0 +1,11 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
++
++#ifndef __DT_BINDINGS_SOC_BCM_PMB_H
++#define __DT_BINDINGS_SOC_BCM_PMB_H
++
++#define BCM_PMB_PCIE0 0x01
++#define BCM_PMB_PCIE1 0x02
++#define BCM_PMB_PCIE2 0x03
++#define BCM_PMB_HOST_USB 0x04
++
++#endif
--- /dev/null
+From 8bcac4011ebe0dbdd46fd55b036ee855c95702d3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 14 Dec 2020 19:07:43 +0100
+Subject: [PATCH] soc: bcm: add PM driver for Broadcom's PMB
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+PMB originally comes from BCM63138 but can be also found on many other
+chipsets (e.g. BCM4908). It's needed to power on and off SoC blocks like
+PCIe, SATA, USB.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ MAINTAINERS | 10 +
+ drivers/soc/bcm/Makefile | 2 +-
+ drivers/soc/bcm/bcm63xx/Kconfig | 9 +
+ drivers/soc/bcm/bcm63xx/Makefile | 1 +
+ drivers/soc/bcm/bcm63xx/bcm-pmb.c | 333 ++++++++++++++++++++++++++++++
+ 5 files changed, 354 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/soc/bcm/bcm63xx/bcm-pmb.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -3674,6 +3674,16 @@ L: linux-mips@vger.kernel.org
+ S: Maintained
+ F: drivers/firmware/broadcom/*
+
++BROADCOM PMB (POWER MANAGEMENT BUS) DRIVER
++M: Rafał Miłecki <rafal@milecki.pl>
++M: Florian Fainelli <f.fainelli@gmail.com>
++M: bcm-kernel-feedback-list@broadcom.com
++L: linux-pm@vger.kernel.org
++S: Maintained
++T: git git://github.com/broadcom/stblinux.git
++F: drivers/soc/bcm/bcm-pmb.c
++F: include/dt-bindings/soc/bcm-pmb.h
++
+ BROADCOM SPECIFIC AMBA DRIVER (BCMA)
+ M: Rafał Miłecki <zajec5@gmail.com>
+ L: linux-wireless@vger.kernel.org
+--- a/drivers/soc/bcm/Makefile
++++ b/drivers/soc/bcm/Makefile
+@@ -1,5 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ obj-$(CONFIG_BCM2835_POWER) += bcm2835-power.o
+ obj-$(CONFIG_RASPBERRYPI_POWER) += raspberrypi-power.o
+-obj-$(CONFIG_SOC_BCM63XX) += bcm63xx/
++obj-y += bcm63xx/
+ obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/
+--- a/drivers/soc/bcm/bcm63xx/Kconfig
++++ b/drivers/soc/bcm/bcm63xx/Kconfig
+@@ -10,3 +10,12 @@ config BCM63XX_POWER
+ BCM6318, BCM6328, BCM6362 and BCM63268 SoCs.
+
+ endif # SOC_BCM63XX
++
++config BCM_PMB
++ bool "Broadcom PMB (Power Management Bus) driver"
++ depends on ARCH_BCM4908 || (COMPILE_TEST && OF)
++ default ARCH_BCM4908
++ select PM_GENERIC_DOMAINS if PM
++ help
++ This enables support for the Broadcom's PMB (Power Management Bus) that
++ is used for disabling and enabling SoC devices.
+--- a/drivers/soc/bcm/bcm63xx/Makefile
++++ b/drivers/soc/bcm/bcm63xx/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ obj-$(CONFIG_BCM63XX_POWER) += bcm63xx-power.o
++obj-$(CONFIG_BCM_PMB) += bcm-pmb.o
+--- /dev/null
++++ b/drivers/soc/bcm/bcm63xx/bcm-pmb.c
+@@ -0,0 +1,333 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2013 Broadcom
++ * Copyright (C) 2020 Rafał Miłecki <rafal@milecki.pl>
++ */
++
++#include <dt-bindings/soc/bcm-pmb.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/pm_domain.h>
++#include <linux/reset/bcm63xx_pmb.h>
++
++#define BPCM_ID_REG 0x00
++#define BPCM_CAPABILITIES 0x04
++#define BPCM_CAP_NUM_ZONES 0x000000ff
++#define BPCM_CAP_SR_REG_BITS 0x0000ff00
++#define BPCM_CAP_PLLTYPE 0x00030000
++#define BPCM_CAP_UBUS 0x00080000
++#define BPCM_CONTROL 0x08
++#define BPCM_STATUS 0x0c
++#define BPCM_ROSC_CONTROL 0x10
++#define BPCM_ROSC_THRESH_H 0x14
++#define BPCM_ROSC_THRESHOLD_BCM6838 0x14
++#define BPCM_ROSC_THRESH_S 0x18
++#define BPCM_ROSC_COUNT_BCM6838 0x18
++#define BPCM_ROSC_COUNT 0x1c
++#define BPCM_PWD_CONTROL_BCM6838 0x1c
++#define BPCM_PWD_CONTROL 0x20
++#define BPCM_SR_CONTROL_BCM6838 0x20
++#define BPCM_PWD_ACCUM_CONTROL 0x24
++#define BPCM_SR_CONTROL 0x28
++#define BPCM_GLOBAL_CONTROL 0x2c
++#define BPCM_MISC_CONTROL 0x30
++#define BPCM_MISC_CONTROL2 0x34
++#define BPCM_SGPHY_CNTL 0x38
++#define BPCM_SGPHY_STATUS 0x3c
++#define BPCM_ZONE0 0x40
++#define BPCM_ZONE_CONTROL 0x00
++#define BPCM_ZONE_CONTROL_MANUAL_CLK_EN 0x00000001
++#define BPCM_ZONE_CONTROL_MANUAL_RESET_CTL 0x00000002
++#define BPCM_ZONE_CONTROL_FREQ_SCALE_USED 0x00000004 /* R/O */
++#define BPCM_ZONE_CONTROL_DPG_CAPABLE 0x00000008 /* R/O */
++#define BPCM_ZONE_CONTROL_MANUAL_MEM_PWR 0x00000030
++#define BPCM_ZONE_CONTROL_MANUAL_ISO_CTL 0x00000040
++#define BPCM_ZONE_CONTROL_MANUAL_CTL 0x00000080
++#define BPCM_ZONE_CONTROL_DPG_CTL_EN 0x00000100
++#define BPCM_ZONE_CONTROL_PWR_DN_REQ 0x00000200
++#define BPCM_ZONE_CONTROL_PWR_UP_REQ 0x00000400
++#define BPCM_ZONE_CONTROL_MEM_PWR_CTL_EN 0x00000800
++#define BPCM_ZONE_CONTROL_BLK_RESET_ASSERT 0x00001000
++#define BPCM_ZONE_CONTROL_MEM_STBY 0x00002000
++#define BPCM_ZONE_CONTROL_RESERVED 0x0007c000
++#define BPCM_ZONE_CONTROL_PWR_CNTL_STATE 0x00f80000
++#define BPCM_ZONE_CONTROL_FREQ_SCALAR_DYN_SEL 0x01000000 /* R/O */
++#define BPCM_ZONE_CONTROL_PWR_OFF_STATE 0x02000000 /* R/O */
++#define BPCM_ZONE_CONTROL_PWR_ON_STATE 0x04000000 /* R/O */
++#define BPCM_ZONE_CONTROL_PWR_GOOD 0x08000000 /* R/O */
++#define BPCM_ZONE_CONTROL_DPG_PWR_STATE 0x10000000 /* R/O */
++#define BPCM_ZONE_CONTROL_MEM_PWR_STATE 0x20000000 /* R/O */
++#define BPCM_ZONE_CONTROL_ISO_STATE 0x40000000 /* R/O */
++#define BPCM_ZONE_CONTROL_RESET_STATE 0x80000000 /* R/O */
++#define BPCM_ZONE_CONFIG1 0x04
++#define BPCM_ZONE_CONFIG2 0x08
++#define BPCM_ZONE_FREQ_SCALAR_CONTROL 0x0c
++#define BPCM_ZONE_SIZE 0x10
++
++struct bcm_pmb {
++ struct device *dev;
++ void __iomem *base;
++ spinlock_t lock;
++ bool little_endian;
++ struct genpd_onecell_data genpd_onecell_data;
++};
++
++struct bcm_pmb_pd_data {
++ const char * const name;
++ int id;
++ u8 bus;
++ u8 device;
++};
++
++struct bcm_pmb_pm_domain {
++ struct bcm_pmb *pmb;
++ const struct bcm_pmb_pd_data *data;
++ struct generic_pm_domain genpd;
++};
++
++static int bcm_pmb_bpcm_read(struct bcm_pmb *pmb, int bus, u8 device,
++ int offset, u32 *val)
++{
++ void __iomem *base = pmb->base + bus * 0x20;
++ unsigned long flags;
++ int err;
++
++ spin_lock_irqsave(&pmb->lock, flags);
++ err = bpcm_rd(base, device, offset, val);
++ spin_unlock_irqrestore(&pmb->lock, flags);
++
++ if (!err)
++ *val = pmb->little_endian ? le32_to_cpu(*val) : be32_to_cpu(*val);
++
++ return err;
++}
++
++static int bcm_pmb_bpcm_write(struct bcm_pmb *pmb, int bus, u8 device,
++ int offset, u32 val)
++{
++ void __iomem *base = pmb->base + bus * 0x20;
++ unsigned long flags;
++ int err;
++
++ val = pmb->little_endian ? cpu_to_le32(val) : cpu_to_be32(val);
++
++ spin_lock_irqsave(&pmb->lock, flags);
++ err = bpcm_wr(base, device, offset, val);
++ spin_unlock_irqrestore(&pmb->lock, flags);
++
++ return err;
++}
++
++static int bcm_pmb_power_off_zone(struct bcm_pmb *pmb, int bus, u8 device,
++ int zone)
++{
++ int offset;
++ u32 val;
++ int err;
++
++ offset = BPCM_ZONE0 + zone * BPCM_ZONE_SIZE + BPCM_ZONE_CONTROL;
++
++ err = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val);
++ if (err)
++ return err;
++
++ val |= BPCM_ZONE_CONTROL_PWR_DN_REQ;
++ val &= ~BPCM_ZONE_CONTROL_PWR_UP_REQ;
++
++ err = bcm_pmb_bpcm_write(pmb, bus, device, offset, val);
++
++ return err;
++}
++
++static int bcm_pmb_power_on_zone(struct bcm_pmb *pmb, int bus, u8 device,
++ int zone)
++{
++ int offset;
++ u32 val;
++ int err;
++
++ offset = BPCM_ZONE0 + zone * BPCM_ZONE_SIZE + BPCM_ZONE_CONTROL;
++
++ err = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val);
++ if (err)
++ return err;
++
++ if (!(val & BPCM_ZONE_CONTROL_PWR_ON_STATE)) {
++ val &= ~BPCM_ZONE_CONTROL_PWR_DN_REQ;
++ val |= BPCM_ZONE_CONTROL_DPG_CTL_EN;
++ val |= BPCM_ZONE_CONTROL_PWR_UP_REQ;
++ val |= BPCM_ZONE_CONTROL_MEM_PWR_CTL_EN;
++ val |= BPCM_ZONE_CONTROL_BLK_RESET_ASSERT;
++
++ err = bcm_pmb_bpcm_write(pmb, bus, device, offset, val);
++ }
++
++ return err;
++}
++
++static int bcm_pmb_power_off_device(struct bcm_pmb *pmb, int bus, u8 device)
++{
++ int offset;
++ u32 val;
++ int err;
++
++ /* Entire device can be powered off by powering off the 0th zone */
++ offset = BPCM_ZONE0 + BPCM_ZONE_CONTROL;
++
++ err = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val);
++ if (err)
++ return err;
++
++ if (!(val & BPCM_ZONE_CONTROL_PWR_OFF_STATE)) {
++ val = BPCM_ZONE_CONTROL_PWR_DN_REQ;
++
++ err = bcm_pmb_bpcm_write(pmb, bus, device, offset, val);
++ }
++
++ return err;
++}
++
++static int bcm_pmb_power_on_device(struct bcm_pmb *pmb, int bus, u8 device)
++{
++ u32 val;
++ int err;
++ int i;
++
++ err = bcm_pmb_bpcm_read(pmb, bus, device, BPCM_CAPABILITIES, &val);
++ if (err)
++ return err;
++
++ for (i = 0; i < (val & BPCM_CAP_NUM_ZONES); i++) {
++ err = bcm_pmb_power_on_zone(pmb, bus, device, i);
++ if (err)
++ return err;
++ }
++
++ return err;
++}
++
++static int bcm_pmb_power_on(struct generic_pm_domain *genpd)
++{
++ struct bcm_pmb_pm_domain *pd = container_of(genpd, struct bcm_pmb_pm_domain, genpd);
++ const struct bcm_pmb_pd_data *data = pd->data;
++ struct bcm_pmb *pmb = pd->pmb;
++
++ switch (data->id) {
++ case BCM_PMB_PCIE0:
++ case BCM_PMB_PCIE1:
++ case BCM_PMB_PCIE2:
++ return bcm_pmb_power_on_zone(pmb, data->bus, data->device, 0);
++ case BCM_PMB_HOST_USB:
++ return bcm_pmb_power_on_device(pmb, data->bus, data->device);
++ default:
++ dev_err(pmb->dev, "unsupported device id: %d\n", data->id);
++ return -EINVAL;
++ }
++}
++
++static int bcm_pmb_power_off(struct generic_pm_domain *genpd)
++{
++ struct bcm_pmb_pm_domain *pd = container_of(genpd, struct bcm_pmb_pm_domain, genpd);
++ const struct bcm_pmb_pd_data *data = pd->data;
++ struct bcm_pmb *pmb = pd->pmb;
++
++ switch (data->id) {
++ case BCM_PMB_PCIE0:
++ case BCM_PMB_PCIE1:
++ case BCM_PMB_PCIE2:
++ return bcm_pmb_power_off_zone(pmb, data->bus, data->device, 0);
++ case BCM_PMB_HOST_USB:
++ return bcm_pmb_power_off_device(pmb, data->bus, data->device);
++ default:
++ dev_err(pmb->dev, "unsupported device id: %d\n", data->id);
++ return -EINVAL;
++ }
++}
++
++static int bcm_pmb_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ const struct bcm_pmb_pd_data *table;
++ const struct bcm_pmb_pd_data *e;
++ struct resource *res;
++ struct bcm_pmb *pmb;
++ int max_id;
++ int err;
++
++ pmb = devm_kzalloc(dev, sizeof(*pmb), GFP_KERNEL);
++ if (!pmb)
++ return -ENOMEM;
++
++ pmb->dev = dev;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ pmb->base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(pmb->base))
++ return PTR_ERR(pmb->base);
++
++ spin_lock_init(&pmb->lock);
++
++ pmb->little_endian = !of_device_is_big_endian(dev->of_node);
++
++ table = of_device_get_match_data(dev);
++ if (!table)
++ return -EINVAL;
++
++ max_id = 0;
++ for (e = table; e->name; e++)
++ max_id = max(max_id, e->id);
++
++ pmb->genpd_onecell_data.num_domains = max_id + 1;
++ pmb->genpd_onecell_data.domains =
++ devm_kcalloc(dev, pmb->genpd_onecell_data.num_domains,
++ sizeof(struct generic_pm_domain *), GFP_KERNEL);
++ if (!pmb->genpd_onecell_data.domains)
++ return -ENOMEM;
++
++ for (e = table; e->name; e++) {
++ struct bcm_pmb_pm_domain *pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
++
++ pd->pmb = pmb;
++ pd->data = e;
++ pd->genpd.name = e->name;
++ pd->genpd.power_on = bcm_pmb_power_on;
++ pd->genpd.power_off = bcm_pmb_power_off;
++
++ pm_genpd_init(&pd->genpd, NULL, true);
++ pmb->genpd_onecell_data.domains[e->id] = &pd->genpd;
++ }
++
++ err = of_genpd_add_provider_onecell(dev->of_node, &pmb->genpd_onecell_data);
++ if (err) {
++ dev_err(dev, "failed to add genpd provider: %d\n", err);
++ return err;
++ }
++
++ return 0;
++}
++
++static const struct bcm_pmb_pd_data bcm_pmb_bcm4908_data[] = {
++ { .name = "pcie2", .id = BCM_PMB_PCIE2, .bus = 0, .device = 2, },
++ { .name = "pcie0", .id = BCM_PMB_PCIE0, .bus = 1, .device = 14, },
++ { .name = "pcie1", .id = BCM_PMB_PCIE1, .bus = 1, .device = 15, },
++ { .name = "usb", .id = BCM_PMB_HOST_USB, .bus = 1, .device = 17, },
++ { },
++};
++
++static const struct of_device_id bcm_pmb_of_match[] = {
++ { .compatible = "brcm,bcm4908-pmb", .data = &bcm_pmb_bcm4908_data, },
++ { },
++};
++
++static struct platform_driver bcm_pmb_driver = {
++ .driver = {
++ .name = "bcm-pmb",
++ .of_match_table = bcm_pmb_of_match,
++ },
++ .probe = bcm_pmb_probe,
++};
++
++builtin_platform_driver(bcm_pmb_driver);
--- /dev/null
+From 149ae80b1d50e7db5ac7df1cdf0820017b70e716 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 14 Jan 2021 11:53:18 +0100
+Subject: [PATCH] soc: bcm: brcmstb: add stubs for getting platform IDs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Some brcmstb drivers may be shared with other SoC families. E.g. the
+same USB PHY block is shared by brcmstb and BCM4908.
+
+To avoid building brcmstb common code on non-brcmstb platforms we need
+stubs for:
+1. brcmstb_get_family_id()
+2. brcmstb_get_product_id()
+(to avoid "undefined reference to" errors).
+
+With this change PHY_BRCM_USB will not have to unconditionally select
+SOC_BRCMSTB anymore.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ include/linux/soc/brcmstb/brcmstb.h | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/include/linux/soc/brcmstb/brcmstb.h
++++ b/include/linux/soc/brcmstb/brcmstb.h
+@@ -2,6 +2,8 @@
+ #ifndef __BRCMSTB_SOC_H
+ #define __BRCMSTB_SOC_H
+
++#include <linux/kconfig.h>
++
+ static inline u32 BRCM_ID(u32 reg)
+ {
+ return reg >> 28 ? reg >> 16 : reg >> 8;
+@@ -12,6 +14,8 @@ static inline u32 BRCM_REV(u32 reg)
+ return reg & 0xff;
+ }
+
++#if IS_ENABLED(CONFIG_SOC_BRCMSTB)
++
+ /*
+ * Helper functions for getting family or product id from the
+ * SoC driver.
+@@ -19,4 +23,16 @@ static inline u32 BRCM_REV(u32 reg)
+ u32 brcmstb_get_family_id(void);
+ u32 brcmstb_get_product_id(void);
+
++#else
++static inline u32 brcmstb_get_family_id(void)
++{
++ return 0;
++}
++
++static inline u32 brcmstb_get_product_id(void)
++{
++ return 0;
++}
++#endif
++
+ #endif /* __BRCMSTB_SOC_H */
--- /dev/null
+From d14f4cce9340a6586512a0eb6bc680dedeaaef14 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 16 Dec 2020 15:33:04 +0100
+Subject: [PATCH] phy: phy-brcm-usb: improve getting OF matching data
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+1. Use of_device_get_match_data() helper to simplify the code
+2. Check for NULL as a good practice
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20201216143305.12179-1-zajec5@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/broadcom/phy-brcm-usb.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/phy/broadcom/phy-brcm-usb.c
++++ b/drivers/phy/broadcom/phy-brcm-usb.c
+@@ -11,6 +11,7 @@
+ #include <linux/io.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+ #include <linux/interrupt.h>
+@@ -427,7 +428,6 @@ static int brcm_usb_phy_probe(struct pla
+ struct device_node *dn = pdev->dev.of_node;
+ int err;
+ const char *mode;
+- const struct of_device_id *match;
+ void (*dvr_init)(struct brcm_usb_init_params *params);
+ const struct match_chip_info *info;
+ struct regmap *rmap;
+@@ -441,8 +441,9 @@ static int brcm_usb_phy_probe(struct pla
+ priv->ini.family_id = brcmstb_get_family_id();
+ priv->ini.product_id = brcmstb_get_product_id();
+
+- match = of_match_node(brcm_usb_dt_ids, dev->of_node);
+- info = match->data;
++ info = of_device_get_match_data(&pdev->dev);
++ if (!info)
++ return -ENOENT;
+ dvr_init = info->init_func;
+ (*dvr_init)(&priv->ini);
+
--- /dev/null
+From 915f1d230e5292bc2156a9997bcb19d9e632f10b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 16 Dec 2020 15:33:05 +0100
+Subject: [PATCH] phy: phy-brcm-usb: specify init function format at struct
+ level
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is slightly cleaner solution that assures noone assings a wrong
+function to the pointer.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20201216143305.12179-2-zajec5@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/broadcom/phy-brcm-usb.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+--- a/drivers/phy/broadcom/phy-brcm-usb.c
++++ b/drivers/phy/broadcom/phy-brcm-usb.c
+@@ -35,7 +35,7 @@ struct value_to_name_map {
+ };
+
+ struct match_chip_info {
+- void *init_func;
++ void (*init_func)(struct brcm_usb_init_params *params);
+ u8 required_regs[BRCM_REGS_MAX + 1];
+ u8 optional_reg;
+ };
+@@ -428,7 +428,6 @@ static int brcm_usb_phy_probe(struct pla
+ struct device_node *dn = pdev->dev.of_node;
+ int err;
+ const char *mode;
+- void (*dvr_init)(struct brcm_usb_init_params *params);
+ const struct match_chip_info *info;
+ struct regmap *rmap;
+ int x;
+@@ -444,8 +443,8 @@ static int brcm_usb_phy_probe(struct pla
+ info = of_device_get_match_data(&pdev->dev);
+ if (!info)
+ return -ENOENT;
+- dvr_init = info->init_func;
+- (*dvr_init)(&priv->ini);
++
++ info->init_func(&priv->ini);
+
+ dev_dbg(dev, "Best mapping table is for %s\n",
+ priv->ini.family_name);
--- /dev/null
+From b39069a482ade0c5e18c407c3218ba1aeed371b6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 6 Jan 2021 21:58:36 +0100
+Subject: [PATCH] dt-bindings: phy: brcm, brcmstb-usb-phy: convert to the
+ json-schema
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Changes that require mentioning:
+1. interrupt-names
+ Name "wakeup" was changed to the "wake". It matches example and what
+ Linux driver looks for in the first place
+2. brcm,ipp and brcm,ioc
+ Both were described as booleans with 0 / 1 values. In examples they
+ were integers and Linux checks for int as well. Both got uint32.
+3. Added minimal description
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20210106205838.10964-1-zajec5@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ .../bindings/phy/brcm,brcmstb-usb-phy.txt | 86 --------
+ .../bindings/phy/brcm,brcmstb-usb-phy.yaml | 193 ++++++++++++++++++
+ 2 files changed, 193 insertions(+), 86 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt
+ create mode 100644 Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
+
+--- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt
++++ /dev/null
+@@ -1,86 +0,0 @@
+-Broadcom STB USB PHY
+-
+-Required properties:
+-- compatible: should be one of
+- "brcm,brcmstb-usb-phy"
+- "brcm,bcm7216-usb-phy"
+- "brcm,bcm7211-usb-phy"
+-
+-- reg and reg-names properties requirements are specific to the
+- compatible string.
+- "brcm,brcmstb-usb-phy":
+- - reg: 1 or 2 offset and length pairs. One for the base CTRL registers
+- and an optional pair for systems with USB 3.x support
+- - reg-names: not specified
+- "brcm,bcm7216-usb-phy":
+- - reg: 3 offset and length pairs for CTRL, XHCI_EC and XHCI_GBL
+- registers
+- - reg-names: "ctrl", "xhci_ec", "xhci_gbl"
+- "brcm,bcm7211-usb-phy":
+- - reg: 5 offset and length pairs for CTRL, XHCI_EC, XHCI_GBL,
+- USB_PHY and USB_MDIO registers and an optional pair
+- for the BDC registers
+- - reg-names: "ctrl", "xhci_ec", "xhci_gbl", "usb_phy", "usb_mdio", "bdc_ec"
+-
+-- #phy-cells: Shall be 1 as it expects one argument for setting
+- the type of the PHY. Possible values are:
+- - PHY_TYPE_USB2 for USB1.1/2.0 PHY
+- - PHY_TYPE_USB3 for USB3.x PHY
+-
+-Optional Properties:
+-- clocks : clock phandles.
+-- clock-names: String, clock name.
+-- interrupts: wakeup interrupt
+-- interrupt-names: "wakeup"
+-- brcm,ipp: Boolean, Invert Port Power.
+- Possible values are: 0 (Don't invert), 1 (Invert)
+-- brcm,ioc: Boolean, Invert Over Current detection.
+- Possible values are: 0 (Don't invert), 1 (Invert)
+-- dr_mode: String, PHY Device mode.
+- Possible values are: "host", "peripheral ", "drd" or "typec-pd"
+- If this property is not defined, the phy will default to "host" mode.
+-- brcm,syscon-piarbctl: phandle to syscon for handling config registers
+-NOTE: one or both of the following two properties must be set
+-- brcm,has-xhci: Boolean indicating the phy has an XHCI phy.
+-- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy.
+-
+-
+-Example:
+-
+-usbphy_0: usb-phy@f0470200 {
+- reg = <0xf0470200 0xb8>,
+- <0xf0471940 0x6c0>;
+- compatible = "brcm,brcmstb-usb-phy";
+- #phy-cells = <1>;
+- dr_mode = "host"
+- brcm,ioc = <1>;
+- brcm,ipp = <1>;
+- brcm,has-xhci;
+- brcm,has-eohci;
+- clocks = <&usb20>, <&usb30>;
+- clock-names = "sw_usb", "sw_usb3";
+-};
+-
+-usb-phy@29f0200 {
+- reg = <0x29f0200 0x200>,
+- <0x29c0880 0x30>,
+- <0x29cc100 0x534>,
+- <0x2808000 0x24>,
+- <0x2980080 0x8>;
+- reg-names = "ctrl",
+- "xhci_ec",
+- "xhci_gbl",
+- "usb_phy",
+- "usb_mdio";
+- brcm,ioc = <0x0>;
+- brcm,ipp = <0x0>;
+- compatible = "brcm,bcm7211-usb-phy";
+- interrupts = <0x30>;
+- interrupt-parent = <&vpu_intr1_nosec_intc>;
+- interrupt-names = "wake";
+- #phy-cells = <0x1>;
+- brcm,has-xhci;
+- syscon-piarbctl = <&syscon_piarbctl>;
+- clocks = <&scmi_clk 256>;
+- clock-names = "sw_usb";
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
+@@ -0,0 +1,193 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/brcm,brcmstb-usb-phy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Broadcom STB USB PHY
++
++description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI
++
++maintainers:
++ - Al Cooper <alcooperx@gmail.com>
++ - Rafał Miłecki <rafal@milecki.pl>
++
++properties:
++ compatible:
++ enum:
++ - brcm,bcm7211-usb-phy
++ - brcm,bcm7216-usb-phy
++ - brcm,brcmstb-usb-phy
++
++ reg:
++ minItems: 1
++ maxItems: 6
++ items:
++ - description: the base CTRL register
++ - description: XHCI EC register
++ - description: XHCI GBL register
++ - description: USB PHY register
++ - description: USB MDIO register
++ - description: BDC register
++
++ reg-names:
++ minItems: 1
++ maxItems: 6
++ items:
++ - const: ctrl
++ - const: xhci_ec
++ - const: xhci_gbl
++ - const: usb_phy
++ - const: usb_mdio
++ - const: bdc_ec
++
++ clocks:
++ minItems: 1
++ maxItems: 2
++
++ clock-names:
++ minItems: 1
++ maxItems: 2
++ items:
++ - const: sw_usb
++ - const: sw_usb3
++
++ interrupts:
++ description: wakeup interrupt
++
++ interrupt-names:
++ const: wake
++
++ brcm,ipp:
++ $ref: /schemas/types.yaml#/definitions/uint32
++ description: Invert Port Power
++ minimum: 0
++ maximum: 1
++
++ brcm,ioc:
++ $ref: /schemas/types.yaml#/definitions/uint32
++ description: Invert Over Current detection
++ minimum: 0
++ maximum: 1
++
++ dr_mode:
++ description: PHY Device mode. If this property is not defined, the PHY will
++ default to "host" mode.
++ enum:
++ - host
++ - peripheral
++ - drd
++ - typec-pd
++
++ brcm,syscon-piarbctl:
++ description: phandle to syscon for handling config registers
++ $ref: /schemas/types.yaml#/definitions/phandle
++
++ brcm,has-xhci:
++ description: Indicates the PHY has an XHCI PHY.
++ type: boolean
++
++ brcm,has-eohci:
++ description: Indicates the PHY has an EHCI/OHCI PHY.
++ type: boolean
++
++ "#phy-cells":
++ description: |
++ Cell allows setting the type of the PHY. Possible values are:
++ - PHY_TYPE_USB2 for USB1.1/2.0 PHY
++ - PHY_TYPE_USB3 for USB3.x PHY
++ const: 1
++
++required:
++ - reg
++ - "#phy-cells"
++
++anyOf:
++ - required:
++ - brcm,has-xhci
++ - required:
++ - brcm,has-eohci
++
++allOf:
++ - if:
++ properties:
++ compatible:
++ contains:
++ const: brcm,brcmstb-usb-phy
++ then:
++ properties:
++ reg:
++ minItems: 1
++ maxItems: 2
++ - if:
++ properties:
++ compatible:
++ contains:
++ const: brcm,bcm7211-usb-phy
++ then:
++ properties:
++ reg:
++ minItems: 5
++ maxItems: 6
++ reg-names:
++ minItems: 5
++ maxItems: 6
++ - if:
++ properties:
++ compatible:
++ contains:
++ const: brcm,bcm7216-usb-phy
++ then:
++ properties:
++ reg:
++ minItems: 3
++ maxItems: 3
++ reg-names:
++ minItems: 3
++ maxItems: 3
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/phy/phy.h>
++
++ usb-phy@f0470200 {
++ compatible = "brcm,brcmstb-usb-phy";
++ reg = <0xf0470200 0xb8>,
++ <0xf0471940 0x6c0>;
++ #phy-cells = <1>;
++ dr_mode = "host";
++ brcm,ioc = <1>;
++ brcm,ipp = <1>;
++ brcm,has-xhci;
++ brcm,has-eohci;
++ clocks = <&usb20>, <&usb30>;
++ clock-names = "sw_usb", "sw_usb3";
++ };
++ - |
++ #include <dt-bindings/phy/phy.h>
++
++ usb-phy@29f0200 {
++ compatible = "brcm,bcm7211-usb-phy";
++ reg = <0x29f0200 0x200>,
++ <0x29c0880 0x30>,
++ <0x29cc100 0x534>,
++ <0x2808000 0x24>,
++ <0x2980080 0x8>;
++ reg-names = "ctrl",
++ "xhci_ec",
++ "xhci_gbl",
++ "usb_phy",
++ "usb_mdio";
++ brcm,ioc = <0x0>;
++ brcm,ipp = <0x0>;
++ interrupts = <0x30>;
++ interrupt-parent = <&vpu_intr1_nosec_intc>;
++ interrupt-names = "wake";
++ #phy-cells = <0x1>;
++ brcm,has-xhci;
++ brcm,syscon-piarbctl = <&syscon_piarbctl>;
++ clocks = <&scmi_clk 256>;
++ clock-names = "sw_usb";
++ };
--- /dev/null
+From 46b616c1574def7a1629bdeded3d44e76382f950 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 6 Jan 2021 21:58:37 +0100
+Subject: [PATCH] dt-bindings: phy: brcm, brcmstb-usb-phy: add BCM4908 binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 uses the same PHY and may require just a slightly different
+programming.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20210106205838.10964-2-zajec5@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ .../devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
++++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
+@@ -15,6 +15,7 @@ maintainers:
+ properties:
+ compatible:
+ enum:
++ - brcm,bcm4908-usb-phy
+ - brcm,bcm7211-usb-phy
+ - brcm,bcm7216-usb-phy
+ - brcm,brcmstb-usb-phy
+@@ -113,7 +114,9 @@ allOf:
+ properties:
+ compatible:
+ contains:
+- const: brcm,brcmstb-usb-phy
++ enum:
++ - const: brcm,bcm4908-usb-phy
++ - const: brcm,brcmstb-usb-phy
+ then:
+ properties:
+ reg:
--- /dev/null
+From 4b402fa8e0b7817f3e3738d7828038f114e6899e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 6 Jan 2021 21:58:38 +0100
+Subject: [PATCH] phy: phy-brcm-usb: support PHY on the BCM4908
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 seems to have slightly different registers but works when
+programmed just like the STB one.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20210106205838.10964-3-zajec5@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/broadcom/Kconfig | 3 ++-
+ drivers/phy/broadcom/phy-brcm-usb.c | 4 ++++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/broadcom/Kconfig
++++ b/drivers/phy/broadcom/Kconfig
+@@ -91,10 +91,11 @@ config PHY_BRCM_SATA
+
+ config PHY_BRCM_USB
+ tristate "Broadcom STB USB PHY driver"
+- depends on ARCH_BRCMSTB || COMPILE_TEST
++ depends on ARCH_BCM4908 || ARCH_BRCMSTB || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ select SOC_BRCMSTB
++ default ARCH_BCM4908
+ default ARCH_BRCMSTB
+ help
+ Enable this to support the Broadcom STB USB PHY.
+--- a/drivers/phy/broadcom/phy-brcm-usb.c
++++ b/drivers/phy/broadcom/phy-brcm-usb.c
+@@ -287,6 +287,10 @@ static const struct match_chip_info chip
+
+ static const struct of_device_id brcm_usb_dt_ids[] = {
+ {
++ .compatible = "brcm,bcm4908-usb-phy",
++ .data = &chip_info_7445,
++ },
++ {
+ .compatible = "brcm,bcm7216-usb-phy",
+ .data = &chip_info_7216,
+ },
--- /dev/null
+From 261ab1fd5c5d2d7ff7d5bab3f5db3c69c4bcea58 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 5 Mar 2021 16:24:06 +0100
+Subject: [PATCH] phy: phy-brcm-usb: select SOC_BRCMSTB on brcmstb only
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+phy-brcm-usb has some conditional init code required on selected brcmstb
+devices. Execution of that code depends on family / product detected by
+brcmstb soc code.
+
+For ARCH_BCM4908 brcmstb soc code always return 0 values as ids. Don't
+bother selecting & compiling that redundant driver.
+
+Depends-on: 149ae80b1d50 ("soc: bcm: brcmstb: add stubs for getting platform IDs")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20210305152406.2588-1-zajec5@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/broadcom/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/phy/broadcom/Kconfig
++++ b/drivers/phy/broadcom/Kconfig
+@@ -94,7 +94,7 @@ config PHY_BRCM_USB
+ depends on ARCH_BCM4908 || ARCH_BRCMSTB || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+- select SOC_BRCMSTB
++ select SOC_BRCMSTB if ARCH_BRCMSTB
+ default ARCH_BCM4908
+ default ARCH_BRCMSTB
+ help
--- /dev/null
+From d9de0cbd5b1f6b51c92a40937945f26a35d848ff Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 9 Mar 2021 19:26:16 +0100
+Subject: [PATCH] dt-bindings: phy: brcm,brcmstb-usb-phy: add power-domains
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On BCM4908 USB PHY is managed using power controller so it needs
+describing properly using the power-domains.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20210309182616.25783-1-zajec5@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ .../devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
++++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
+@@ -42,6 +42,9 @@ properties:
+ - const: usb_mdio
+ - const: bdc_ec
+
++ power-domains:
++ maxItems: 1
++
+ clocks:
+ minItems: 1
+ maxItems: 2
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 22 Jun 2021 07:05:04 +0200
+Subject: [PATCH] net: broadcom: bcm4908_enet: reset DMA rings sw indexes
+ properly
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Resetting software indexes in bcm4908_dma_alloc_buf_descs() is not
+enough as it's called during device probe only. Driver resets DMA on
+every .ndo_open callback and it's required to reset indexes then.
+
+This fixes inconsistent rings state and stalled traffic after interface
+down & up sequence.
+
+Fixes: 4feffeadbcb2 ("net: broadcom: bcm4908enet: add BCM4908 controller driver")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -174,9 +174,6 @@ static int bcm4908_dma_alloc_buf_descs(s
+ if (!ring->slots)
+ goto err_free_buf_descs;
+
+- ring->read_idx = 0;
+- ring->write_idx = 0;
+-
+ return 0;
+
+ err_free_buf_descs:
+@@ -303,6 +300,9 @@ static void bcm4908_enet_dma_ring_init(s
+
+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
+ (uint32_t)ring->dma_addr);
++
++ ring->read_idx = 0;
++ ring->write_idx = 0;
+ }
+
+ static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet)
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 15 Feb 2021 22:01:03 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: limit amount of GPIOs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Linux driver can't handle more than 64 GPIOs
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -281,7 +281,7 @@
+ gpio0: gpio-controller@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg-names = "dirout", "dat";
+- reg = <0x500 0x28>, <0x528 0x28>;
++ reg = <0x500 0x8>, <0x528 0x8>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 21 Jan 2021 10:44:53 +0100
+Subject: [PATCH] mtd: rawnand: brcmnand: disable WP on BCM4908
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 contains NAND controller version 0x0701 (v7.1). It means that
+NAND_WP should be available.
+
+For some reason setting #WP on doesn't result in clearing NAND_STATUS_WP
+status bit:
+[ 1.077857] bcm63138_nand ff801800.nand: timeout on status poll (expected c0000040 got c00000c0)
+[ 1.086832] bcm63138_nand ff801800.nand: nand #WP expected on
+
+For now try working without touching #WP.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -37,7 +37,11 @@
+ * 1: NAND_WP is set by default, cleared for erase/write operations
+ * 2: NAND_WP is always cleared
+ */
++#if IS_ENABLED(CONFIG_ARCH_BCM4908)
++static int wp_on = 0;
++#else
+ static int wp_on = 1;
++#endif
+ module_param(wp_on, int, 0444);
+
+ /***********************************************************************
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 15 Feb 2021 23:59:26 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+GPHY needs to be enabled to succesfully probe & setup switch port
+connected to it. Otherwise hardcoding PHY OUI would be required.
+
+Before:
+brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7
+
+After:
+brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL)
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/net/dsa/bcm_sf2.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -1484,10 +1484,14 @@ static int bcm_sf2_sw_probe(struct platf
+ rev = reg_readl(priv, REG_PHY_REVISION);
+ priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
+
++ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
++
+ ret = b53_switch_register(dev);
+ if (ret)
+ goto out_mdio;
+
++ bcm_sf2_gphy_enable_set(priv->dev->ds, false);
++
+ dev_info(&pdev->dev,
+ "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
+ priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 16 Feb 2021 00:06:35 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: keep GPHY enabled on the BCM4908
+
+Trying to access disabled PHY results in MDIO_READ_FAIL and:
+[ 11.962886] brcm-sf2 80080000.switch wan: configuring for phy/internal link mode
+[ 11.972500] 8021q: adding VLAN 0 to HW filter on device wan
+[ 11.980205] ------------[ cut here ]------------
+[ 11.984885] WARNING: CPU: 0 PID: 7 at phy_error+0x10/0x58
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/net/dsa/bcm_sf2.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -1498,6 +1498,12 @@ static int bcm_sf2_sw_probe(struct platf
+ priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
+ priv->irq0, priv->irq1);
+
++ /* BCM4908 has 5 GPHYs which means bcm_sf2_port_setup() will not enable
++ * GPHY when needed. Leave it enabled here.
++ */
++ if (priv->type == BCM4908_DEVICE_ID)
++ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
++
+ return 0;
+
+ out_mdio:
projects / openwrt / staging / lynxis.git / commitdiff