drm/exynos: fix incorrect interrupt induced by m2m operation.

This patch fixes incorrect interrupt induced by m2m operation.
the m2m operation calls s/w reset every frame but there is the case that
the interrupt to m2m operation occures after s/w reset sometimes.
So this patch makes dma and capture operations stop at s/w reset
to avoid incorrect interrupt.

Signed-off-by: Jinyoung Jeon <jy0.jeon@samsung.com>
Signed-off-by: Eunchul Kim <chulspro.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index a99ceefcc2865433581d46d841054a6477aa1dec..9f52b7faa4b37df20abebe305ee32840da421813 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -169,10 +169,23 @@ static void fimc_sw_reset(struct fimc_context *ctx)
 
        DRM_DEBUG_KMS("%s\n", __func__);
 
+       /* stop dma operation */
+       cfg = fimc_read(EXYNOS_CISTATUS);
+       if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) {
+               cfg = fimc_read(EXYNOS_MSCTRL);
+               cfg &= ~EXYNOS_MSCTRL_ENVID;
+               fimc_write(cfg, EXYNOS_MSCTRL);
+       }
+
        cfg = fimc_read(EXYNOS_CISRCFMT);
        cfg |= EXYNOS_CISRCFMT_ITU601_8BIT;
        fimc_write(cfg, EXYNOS_CISRCFMT);
 
+       /* disable image capture */
+       cfg = fimc_read(EXYNOS_CIIMGCPT);
+       cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
+       fimc_write(cfg, EXYNOS_CIIMGCPT);
+
        /* s/w reset */
        cfg = fimc_read(EXYNOS_CIGCTRL);
        cfg |= (EXYNOS_CIGCTRL_SWRST);