MIPS: idle: Workaround wait + FDC problems

On certain cores (namely proAptiv and P5600) incoming data via a Fast
Debug Channel (FDC) while the core is blocked on a wait instruction will
cause the wait not to wake up even when another interrupt is received.
This makes an idle target stop as soon as you send FDC data to it, until
the debug probe interrupts it and restarts the wait instruction.

This is worked around by avoiding using r4k_wait on these cores if
CONFIG_MIPS_EJTAG_FDC_TTY is enabled (which would imply the user intends
to use the FDC).

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9144/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 368c88b7eb6c985a848601415c9e8baf7aa2a5bb..e4f62b7875d24b068ee44000b1ad7f8b7b5a38d4 100644 (file)
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -176,6 +176,17 @@ void __init check_wait(void)
                cpu_wait = rm7k_wait_irqoff;
                break;
 
+       case CPU_PROAPTIV:
+       case CPU_P5600:
+               /*
+                * Incoming Fast Debug Channel (FDC) data during a wait
+                * instruction causes the wait never to resume, even if an
+                * interrupt is received. Avoid using wait at all if FDC data is
+                * likely to be received.
+                */
+               if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
+                       break;
+               /* fall through */
        case CPU_M14KC:
        case CPU_M14KEC:
        case CPU_24K:
@@ -183,8 +194,6 @@ void __init check_wait(void)
        case CPU_1004K:
        case CPU_1074K:
        case CPU_INTERAPTIV:
-       case CPU_PROAPTIV:
-       case CPU_P5600:
        case CPU_M5150:
        case CPU_QEMU_GENERIC:
                cpu_wait = r4k_wait;