.rate = ADM8668_UARTCLK_FREQ,
};
+static struct clk sys_clk;
+
struct clk *clk_get(struct device *dev, const char *id)
{
- const char *name = dev_name(dev);
+ const char *lookup = id;
+
+ if (dev)
+ lookup = dev_name(dev);
- if (!strcmp(name, "apb:uart0"))
+ if (!strcmp(lookup, "apb:uart0"))
return &uart_clk;
+ if (!strcmp(lookup, "sys"))
+ return &sys_clk;
return ERR_PTR(-ENOENT);
}
{
}
EXPORT_SYMBOL(clk_put);
+
+void __init adm8668_init_clocks(void)
+{
+ u32 adj;
+
+ /* adjustable clock selection
+ * CR3 bit 14~11, 0000 -> 175MHz, 0001 -> 180MHz, etc...
+ */
+ adj = (ADM8668_CONFIG_REG(ADM8668_CR3) >> 11) & 0xf;
+ sys_clk.rate = SYS_CLOCK + adj * 5000000;
+
+ pr_info("ADM8668 CPU clock: %lu MHz\n", sys_clk.rate / 1000000);
+}
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/clk.h>
#include <asm/time.h>
#include <adm8668.h>
void __init plat_time_init(void)
{
- int adj = (ADM8668_CONFIG_REG(ADM8668_CR3) >> 11) & 0xf;
+ struct clk *sys_clk;
- /* adjustable clock selection
- CR3 bit 14~11, 0000 -> 175MHz, 0001 -> 180MHz, etc... */
+ adm8668_init_clocks();
- mips_hpt_frequency = (SYS_CLOCK + adj * 5000000) / 2;
- printk("ADM8668 CPU clock: %d MHz\n", 2*mips_hpt_frequency / 1000000);
+ sys_clk = clk_get(NULL, "sys");
+ if (IS_ERR(sys_clk))
+ panic("unable to get system clock\n");
+
+ mips_hpt_frequency = clk_get_rate(sys_clk) / 2;
}