drm/msm: Add MSM_PARAM_GMEM_BASE
authorJordan Crouse <jcrouse@codeaurora.org>
Tue, 7 Mar 2017 17:02:53 +0000 (10:02 -0700)
committerRob Clark <robdclark@gmail.com>
Sat, 8 Apr 2017 10:59:36 +0000 (06:59 -0400)
User space needs to know where the GMEM whole starts so that they
can set up the addressing correctly.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/adreno/adreno_gpu.c
include/uapi/drm/msm_drm.h

index 9a92bcf982b85e6c81b51e5a1c4988ab7ce4e396..4cac22633ce4eff45be478581b7598b2c64c0a73 100644 (file)
@@ -35,6 +35,9 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
        case MSM_PARAM_GMEM_SIZE:
                *value = adreno_gpu->gmem;
                return 0;
+       case MSM_PARAM_GMEM_BASE:
+               *value = 0x100000;
+               return 0;
        case MSM_PARAM_CHIP_ID:
                *value = adreno_gpu->rev.patchid |
                                (adreno_gpu->rev.minor << 8) |
index 4d5d6a2bc59e8553fc5e1d6c7a56fb5f494d3830..a4a189a240d71885093fd39cf43dccc2676ac9ff 100644 (file)
@@ -72,6 +72,7 @@ struct drm_msm_timespec {
 #define MSM_PARAM_CHIP_ID    0x03
 #define MSM_PARAM_MAX_FREQ   0x04
 #define MSM_PARAM_TIMESTAMP  0x05
+#define MSM_PARAM_GMEM_BASE  0x06
 
 struct drm_msm_param {
        __u32 pipe;           /* in, MSM_PIPE_x */