drm/amdgpu: add a generic fb accessing helper function(v3)
authorTianci.Yin <tianci.yin@amd.com>
Mon, 30 Sep 2019 05:33:50 +0000 (13:33 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 17 Oct 2019 20:31:13 +0000 (16:31 -0400)
add a generic helper function for accessing framebuffer via MMIO

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

index b42fa21de80626779d6a2199869fa029523274d9..ef195f2930003e6b04bc6f0e669c1fdd0b41ebd1 100644 (file)
@@ -981,6 +981,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 void amdgpu_device_fini(struct amdgpu_device *adev);
 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
 
+void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
+                              uint32_t *buf, size_t size, bool write);
 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
                        uint32_t acc_flags);
 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
index b29bdf22c8bf177b766754daa005656b0466d3b7..46218b36dc9ed0023f8154121f21d0cf803e8cef 100644 (file)
@@ -153,6 +153,36 @@ bool amdgpu_device_is_px(struct drm_device *dev)
        return false;
 }
 
+/**
+ * VRAM access helper functions.
+ *
+ * amdgpu_device_vram_access - read/write a buffer in vram
+ *
+ * @adev: amdgpu_device pointer
+ * @pos: offset of the buffer in vram
+ * @buf: virtual address of the buffer in system memory
+ * @size: read/write size, sizeof(@buf) must > @size
+ * @write: true - write to vram, otherwise - read from vram
+ */
+void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
+                              uint32_t *buf, size_t size, bool write)
+{
+       uint64_t last;
+       unsigned long flags;
+
+       last = size - 4;
+       for (last += pos; pos <= last; pos += 4) {
+               spin_lock_irqsave(&adev->mmio_idx_lock, flags);
+               WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
+               WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
+               if (write)
+                       WREG32_NO_KIQ(mmMM_DATA, *buf++);
+               else
+                       *buf++ = RREG32_NO_KIQ(mmMM_DATA);
+               spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
+       }
+}
+
 /*
  * MMIO register access helper functions.
  */
index ddd8364102a2985d43581786498ef3bf4fe255e6..f95092741c38af4dc776054fc7c542b0d5f7f987 100644 (file)
@@ -134,20 +134,10 @@ static int hw_id_map[MAX_HWIP] = {
 
 static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
 {
-       uint32_t *p = (uint32_t *)binary;
        uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
        uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
-       unsigned long flags;
-
-       while (pos < vram_size) {
-               spin_lock_irqsave(&adev->mmio_idx_lock, flags);
-               WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
-               WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
-               *p++ = RREG32_NO_KIQ(mmMM_DATA);
-               spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
-               pos += 4;
-       }
 
+       amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, DISCOVERY_TMR_SIZE, false);
        return 0;
 }