mpc83xx: Migrate SPCR to Kconfig
authorMario Six <mario.six@gdsys.cc>
Mon, 21 Jan 2019 08:18:13 +0000 (09:18 +0100)
committerMario Six <mario.six@gdsys.cc>
Tue, 21 May 2019 05:52:33 +0000 (07:52 +0200)
Migrate the SPCR setting to Kconfig.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
37 files changed:
arch/powerpc/cpu/mpc83xx/Kconfig
arch/powerpc/cpu/mpc83xx/cpu_init.c
arch/powerpc/cpu/mpc83xx/initreg/Kconfig [new file with mode: 0644]
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr [new file with mode: 0644]
arch/powerpc/cpu/mpc83xx/initreg/initreg.h [new file with mode: 0644]
configs/MPC8308RDB_defconfig
configs/MPC8315ERDB_defconfig
configs/MPC8323ERDB_defconfig
configs/MPC8349EMDS_PCI64_defconfig
configs/MPC8349EMDS_SLAVE_defconfig
configs/MPC8349EMDS_defconfig
configs/MPC8349ITXGP_defconfig
configs/MPC8349ITX_LOWBOOT_defconfig
configs/MPC8349ITX_defconfig
configs/MPC837XEMDS_HOST_defconfig
configs/MPC837XEMDS_SLAVE_defconfig
configs/MPC837XEMDS_defconfig
configs/MPC837XERDB_SLAVE_defconfig
configs/MPC837XERDB_defconfig
configs/hrcon_defconfig
configs/hrcon_dh_defconfig
configs/mpc8308_p1m_defconfig
configs/strider_con_defconfig
configs/strider_con_dp_defconfig
configs/strider_cpu_defconfig
configs/strider_cpu_dp_defconfig
include/configs/MPC8308RDB.h
include/configs/MPC8315ERDB.h
include/configs/MPC8323ERDB.h
include/configs/MPC8349EMDS.h
include/configs/MPC8349ITX.h
include/configs/MPC837XEMDS.h
include/configs/MPC837XERDB.h
include/configs/hrcon.h
include/configs/mpc8308_p1m.h
include/configs/strider.h
scripts/config_whitelist.txt

index 8a3bb10466c64c4f562f51ff254799c7f6826181..fe20e85086ba53228ea13d5f2a63840c2bf3bb8b 100644 (file)
@@ -296,6 +296,7 @@ source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig"
 source "arch/powerpc/cpu/mpc83xx/hid/Kconfig"
 source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
 source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
 
 menu "Legacy options"
 
index 77502567a70630d600b4ef8a39afd7f790dea0f6..59faa78d24cb1fec878dcd19328afa810626deef 100644 (file)
@@ -16,6 +16,7 @@
 #include "elbc/elbc.h"
 #include "sysio/sysio.h"
 #include "arbiter/arbiter.h"
+#include "initreg/initreg.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,34 +53,6 @@ static void config_qe_ioports(void)
  */
 void cpu_init_f (volatile immap_t * im)
 {
-       __be32 spcr_mask =
-#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
-               SPCR_OPT |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
-               SPCR_TSECEP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
-               SPCR_TSEC1EP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
-               SPCR_TSEC2EP |
-#endif
-               0;
-       __be32 spcr_val =
-#ifdef CONFIG_SYS_SPCR_OPT
-               (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
-               (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
-               (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
-               (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
-#endif
-               0;
        __be32 sccr_mask =
 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
                SCCR_ENCCM |
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
new file mode 100644 (file)
index 0000000..82c2489
--- /dev/null
@@ -0,0 +1,5 @@
+menu "Initial register configuration"
+
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
new file mode 100644 (file)
index 0000000..f32309e
--- /dev/null
@@ -0,0 +1,115 @@
+menu "SPCR - System priority and configuration register"
+
+choice
+       prompt "Optimize"
+
+config SPCR_OPT_UNSET
+       bool "Don't set value"
+
+config SPCR_OPT_NONE
+       bool "No performance enhancement"
+
+config SPCR_OPT_SPEC_READ
+       bool "Performance enhancement by speculative read"
+
+endchoice
+
+if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X
+
+choice
+       prompt "TSEC emergency priority"
+
+config SPCR_TSECEP_UNSET
+       bool "Don't set value"
+
+config SPCR_TSECEP_0
+       bool "Level 0 (lowest priority)"
+
+config SPCR_TSECEP_1
+       bool "Level 1"
+
+config SPCR_TSECEP_2
+       bool "Level 2"
+
+config SPCR_TSECEP_3
+       bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+if ARCH_MPC8349
+
+choice
+       prompt "TSEC1 emergency priority"
+
+config SPCR_TSEC1EP_UNSET
+       bool "Don't set value"
+
+config SPCR_TSEC1EP_0
+       bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC1EP_1
+       bool "Level 1"
+
+config SPCR_TSEC1EP_2
+       bool "Level 2"
+
+config SPCR_TSEC1EP_3
+       bool "Level 3 (highest priority)"
+
+endchoice
+
+choice
+       prompt "TSEC2 emergency priority"
+
+config SPCR_TSEC2EP_UNSET
+       bool "Don't set value"
+
+config SPCR_TSEC2EP_0
+       bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC2EP_1
+       bool "Level 1"
+
+config SPCR_TSEC2EP_2
+       bool "Level 2"
+
+config SPCR_TSEC2EP_3
+       bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+config SPCR_OPT
+       hex
+       default 0x0 if SPCR_OPT_UNSET
+       default 0x0 if SPCR_OPT_NONE
+       default 0x800000 if SPCR_OPT_SPEC_READ
+
+config SPCR_TSECEP
+       hex
+       default 0x0 if SPCR_TSECEP_UNSET
+       default 0x0 if SPCR_TSECEP_0
+       default 0x100 if SPCR_TSECEP_1
+       default 0x200 if SPCR_TSECEP_2
+       default 0x300 if SPCR_TSECEP_3
+
+config SPCR_TSEC1EP
+       hex
+       default 0x0 if SPCR_TSEC1EP_UNSET
+       default 0x0 if SPCR_TSEC1EP_0
+       default 0x100 if SPCR_TSEC1EP_1
+       default 0x200 if SPCR_TSEC1EP_2
+       default 0x300 if SPCR_TSEC1EP_3
+
+config SPCR_TSEC2EP
+       hex
+       default 0x0 if SPCR_TSEC2EP_UNSET
+       default 0x0 if SPCR_TSEC2EP_0
+       default 0x1 if SPCR_TSEC2EP_1
+       default 0x2 if SPCR_TSEC2EP_2
+       default 0x3 if SPCR_TSEC2EP_3
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
new file mode 100644 (file)
index 0000000..d61c70f
--- /dev/null
@@ -0,0 +1,43 @@
+#define SPCR_PCIHPE_MASK       0x10000000
+#define SPCR_PCIPR_MASK                0x03000000
+#define SPCR_OPT_MASK          0x00800000
+#define SPCR_TBEN_MASK         0x00400000
+#define SPCR_COREPR_MASK       0x00300000
+#define SPCR_TSEC1DP_MASK      0x00003000
+#define SPCR_TSEC1BDP_MASK     0x00000C00
+#define SPCR_TSEC1EP_MASK      0x00000300
+#define SPCR_TSEC2DP_MASK      0x00000030
+#define SPCR_TSEC2BDP_MASK     0x0000000C
+#define SPCR_TSEC2EP_MASK      0x00000003
+#define SPCR_TSECDP_MASK       0x00003000
+#define SPCR_TSECBDP_MASK      0x00000C00
+#define SPCR_TSECEP_MASK       0x00000300
+
+       const __be32 spcr_mask =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+               SPCR_OPT_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+               SPCR_TSECEP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+               SPCR_TSEC1EP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+               SPCR_TSEC2EP_MASK |
+#endif
+               0;
+       const __be32 spcr_val =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+               CONFIG_SPCR_OPT |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+               CONFIG_SPCR_TSECEP |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+               CONFIG_SPCR_TSEC1EP |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+               CONFIG_SPCR_TSEC2EP |
+#endif
+               0;
index 00feaccc3058a2b4530a36720e11736bd95f9a78..a01ff8920b3683c67892eedde2c375083b58b116 100644 (file)
@@ -72,6 +72,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
index 2263b9cb51b98be8abc2e9f68280106a8e681054..e5e1b7a29d793a09ce3d6fd3e455db5e3b19234e 100644 (file)
@@ -82,6 +82,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
index b52d1fd62a54d800da06c0faa323d2c417269cc5..08486f81a74806873e82028da895312c44cff5b3 100644 (file)
@@ -75,6 +75,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_OPT_SPEC_READ=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
index 9108275f3c22771f78c9f33c4dcc6833c3a10eb3..fa646f543fb68aa93c129181d84af19a712216c3 100644 (file)
@@ -58,6 +58,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
index 7454dd64f1a7c80baf0efd318a75a9e89696e829..8af1a3d3b26e0ccfe9a7e1c3eea4755edafdef23 100644 (file)
@@ -56,6 +56,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
index 328c3aa567eaf974690c562e610228c08160ef7a..b2b944a30dad7ecde08d25e686ce6ea750d8e3df 100644 (file)
@@ -58,6 +58,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
index fa121d721ae5ddcdac6dc881722d18007625d1dd..fcd78338c9077bfa71387bf398a7cd5f8d551709 100644 (file)
@@ -101,6 +101,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
index 0a79d1e625481a6ab2ebab7fa5646e72e95492e8..319b8d8c40cb83894ed6d6590e8289bd19e7e523 100644 (file)
@@ -101,6 +101,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
index e7461072edfa56fdd7cc47bd325e2b45c1bdf929..f60527b361a135af032170c85c5721974bd5da62 100644 (file)
@@ -100,6 +100,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
index 0df5bdb2c5a4114365eeb7926a4a14d1b6085cb6..33e536ce182f50276d79facab5da3c04cf074bbd 100644 (file)
@@ -106,6 +106,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
index 99f206e719fd371d8ad52ccc1e18ae7aa2970044..7d1f40517114c50cb092ead176edd3986bc0a909 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
index 98dc6ca7848b42b725c67e21a673b849f78f8d3a..d4515cbb8c33a442798616689551fde90d820e1d 100644 (file)
@@ -86,6 +86,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6
index 11a33d982f0384eaed321c0cac765c825d334270..9730aefd54836af2df503dc2e6ac72b475ee106f 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
index d43b364910a3d82f675ebd603cb7a1491f35900d..7bf081a20bf187a065538b0c84ccbdc9f6160846 100644 (file)
@@ -106,6 +106,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCIE"
index 3dad033be02be78ecd01231aced9970123ab4123..9c1ab75e0095c2013da697d1c127d23b19f816d7 100644 (file)
@@ -69,6 +69,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index 4fb7cb5ffdb5b28db3f681f3edc643c9ee53fbc8..0f1cc637cfcfadad1f12d2907df6a8171d141882 100644 (file)
@@ -69,6 +69,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index f73084c0e1f59962c9c3f1095b141c8cb00a056a..f1559bef548b8dc376eadd556efeb8b1ae34158f 100644 (file)
@@ -70,6 +70,7 @@ CONFIG_SICR_GTM_GPIO=y
 CONFIG_SICR_GPIOSEL_IEEE1588=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=5
index 722f25d63e95de751529eadd6b5c0f6203ede3d3..b11a26c2fc135502fd29683287e90afa3907aa1c 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index dd3c83d4fcd805cf40604f882081a082065fb484..72cb274348ebcaa88e5f2d972c28e150056f5d97 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index 1a35132987294f45af6963f0247644663af2105a..f36404deb4d1e79206a355ec735d90acbc707056 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index 79fdc140e5a4b2435f56a9c3e243285801ad0338..0ade98545a3d9fe5014b1aee39ce64afe1173aca 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index 60c6b920f92ecb0d0e6fdea8d306a246b0f6d1c7..c4b604cc0d02fdb3edcb32738b96b6f356cec1d2 100644 (file)
@@ -33,8 +33,6 @@
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1     0xe3000
 
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */
index 9531be30721ac8bdae4ae861541f85d70d189d3d..10742ae312a8895dc474b459291caad1515ded77 100644 (file)
@@ -31,8 +31,6 @@
 
 #define CONFIG_HWCONFIG
 
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */
index 23496518b311833eff75f0dfa518876f74ab3708..2ef16e543d815cf68cff92631764f4310ea28457 100644 (file)
@@ -20,9 +20,6 @@
  */
 #define CONFIG_SYS_SICRL               0x00000000
 
-/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
-#define CONFIG_SYS_SPCR_OPT    1
-
 /*
  * DDR Setup
  */
index 51c47a8221b9cb5d1eb48aec372679ac477fedbe..b64a91183849a69487d0b23dc0b7373685b6469e 100644 (file)
 /*
  * System performance
  */
-#define CONFIG_SYS_SPCR_TSEC1EP        3       /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP        3       /* TSEC2 emergency priority (0-3) */
 #define CONFIG_SYS_SCCR_TSEC1CM        1       /* TSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM        1       /* TSEC2 & I2C0 clock mode (0-3) */
 
index 1c8574a40f374c5a275db23ddcef4fc44a6aa675..d8e86f21ea14e00c99e8f4f86863e598fd2ef04a 100644 (file)
@@ -403,8 +403,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 /*
  * System performance
  */
-#define CONFIG_SYS_SPCR_TSEC1EP        3       /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP        3       /* TSEC2 emergency priority (0-3) */
 #define CONFIG_SYS_SCCR_TSEC1CM        1       /* TSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM        1       /* TSEC2 & I2C0 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_USBMPHCM 3     /* USB MPH controller's clock */
index d8a02b8e06212ad47c68dd3712d2ee55ede6b813..5d469073312e255b3d81bd2efb0c1b436d620fd6 100644 (file)
@@ -12,9 +12,6 @@
  */
 #define CONFIG_E300            1 /* E300 family */
 
-/* System Priority Control Register */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
-
 /*
  * IP blocks clock configuration
  */
index 6fa57ebee45c9fce66fd5cf3353e2bea16951b41..b6756c3794c3d5e3302fa594e9b848c2dc28e993 100644 (file)
@@ -23,9 +23,6 @@
 /* System performance - define the value i.e. CONFIG_SYS_XXX
 */
 
-/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP 3       /* eTSEC1&2 emergency priority (0-3) */
-
 /* System Clock Configuration Register */
 #define CONFIG_SYS_SCCR_TSEC1CM        1               /* eTSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM        1               /* eTSEC2 clock mode (0-3) */
index 76b28e07f4ec5eb9efa1231d9a22845eec62ca37..9cb5df4a72e3a81b0cd6b30b49106f560804a0a0 100644 (file)
@@ -21,8 +21,6 @@
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1     0xe3000
 
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */
index 60871b757d54dcbbb467e39aad4ca121511d0449..ce3a899480064c7e4919bec1bc831c0f0b389eb9 100644 (file)
@@ -36,8 +36,6 @@
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1     0xe3000
 
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */
index 95bc20203f52f52a4e7c39effabe3181323c0c41..e4584db7d5d792c088ef4632445a66c2d0afac08 100644 (file)
@@ -21,8 +21,6 @@
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1     0xe3000
 
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */
index ae07c8da24bb8476ff6bbf7330e381279fee52de..30b8b55132575c23b7cc316444df7af236ee6c33 100644 (file)
@@ -4085,7 +4085,6 @@ CONFIG_SYS_SPANSION_BOOT
 CONFIG_SYS_SPCR_OPT
 CONFIG_SYS_SPCR_TSEC1EP
 CONFIG_SYS_SPCR_TSEC2EP
-CONFIG_SYS_SPCR_TSECEP
 CONFIG_SYS_SPD_BUS_NUM
 CONFIG_SYS_SPI0
 CONFIG_SYS_SPI0_NUM_CS