--- /dev/null
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -35,44 +35,17 @@ static void ath79_misc_irq_handler(unsig
+ pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
+ __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+
+- if (pending & MISC_INT_UART)
+- generic_handle_irq(ATH79_MISC_IRQ_UART);
+-
+- else if (pending & MISC_INT_DMA)
+- generic_handle_irq(ATH79_MISC_IRQ_DMA);
+-
+- else if (pending & MISC_INT_PERFC)
+- generic_handle_irq(ATH79_MISC_IRQ_PERFC);
+-
+- else if (pending & MISC_INT_TIMER)
+- generic_handle_irq(ATH79_MISC_IRQ_TIMER);
+-
+- else if (pending & MISC_INT_TIMER2)
+- generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
+-
+- else if (pending & MISC_INT_TIMER3)
+- generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
+-
+- else if (pending & MISC_INT_TIMER4)
+- generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
+-
+- else if (pending & MISC_INT_OHCI)
+- generic_handle_irq(ATH79_MISC_IRQ_OHCI);
+-
+- else if (pending & MISC_INT_ERROR)
+- generic_handle_irq(ATH79_MISC_IRQ_ERROR);
+-
+- else if (pending & MISC_INT_GPIO)
+- generic_handle_irq(ATH79_MISC_IRQ_GPIO);
+-
+- else if (pending & MISC_INT_WDOG)
+- generic_handle_irq(ATH79_MISC_IRQ_WDOG);
++ if (!pending) {
++ spurious_interrupt();
++ return;
++ }
+
+- else if (pending & MISC_INT_ETHSW)
+- generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
++ while (pending) {
++ int bit = __ffs(pending);
+
+- else
+- spurious_interrupt();
++ generic_handle_irq(ATH79_MISC_IRQ(bit));
++ pending &= ~BIT(bit);
++ }
+ }
+
+ static void ar71xx_misc_irq_unmask(struct irq_data *d)
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -14,6 +14,7 @@
+
+ #define ATH79_MISC_IRQ_BASE 8
+ #define ATH79_MISC_IRQ_COUNT 32
++#define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x))
+
+ #define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
+ #define ATH79_PCI_IRQ_COUNT 6