ARM: dts: imx6q-bx50v3: Add internal switch

B850v3, B650v3 and B450v3 all have a GPIO bit banged MDIO bus to
communicate with a Marvell switch. On all devices the switch is
connected to a PCI based network card, which needs to be referenced
by DT, so this also adds the common PCI root node.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index b915837bbb5f7f867aad5fc27d39898a034ce4fb..916ea94d75cacb4f03fc5f8429a17b33b0dc474e 100644 (file)
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -92,6 +92,56 @@
                mux-int-port = <1>;
                mux-ext-port = <4>;
        };
+
+       aliases {
+               mdio-gpio0 = &mdio0;
+       };
+
+       mdio0: mdio-gpio {
+               compatible = "virtual,mdio-gpio";
+               gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
+                       <&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               switch@0 {
+                       compatible = "marvell,mv88e6085"; /* 88e6240*/
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0>;
+
+                       switch_ports: ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               switchphy0: switchphy@0 {
+                                       reg = <0>;
+                               };
+
+                               switchphy1: switchphy@1 {
+                                       reg = <1>;
+                               };
+
+                               switchphy2: switchphy@2 {
+                                       reg = <2>;
+                               };
+
+                               switchphy3: switchphy@3 {
+                                       reg = <3>;
+                               };
+
+                               switchphy4: switchphy@4 {
+                                       reg = <4>;
+                               };
+                       };
+               };
+       };
 };
 
 &ecspi5 {
@@ -326,3 +376,15 @@
                tcxo-clock-frequency = <26000000>;
        };
 };
+
+&pcie {
+       /* Synopsys, Inc. Device */
+       pci_root: root@0,0 {
+               compatible = "pci16c3,abcd";
+               reg = <0x00000000 0 0 0 0>;
+
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+       };
+};