hisi_ipc_cluster_on(cpu, cluster);
hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint);
+ hisi_pwrc_enable_debug(cpu, cluster);
hisi_ipc_cpu_on(cpu, cluster);
+
return 0;
}
}
}
+void hisi_pwrc_enable_debug(unsigned int core, unsigned int cluster)
+{
+ unsigned int val, enable;
+
+ enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster);
+
+ /* Enable debug module */
+ val = mmio_read_32(ACPU_SC_PDBGUP_MBIST);
+ mmio_write_32(ACPU_SC_PDBGUP_MBIST, val | enable);
+ do {
+ /* RAW barrier */
+ val = mmio_read_32(ACPU_SC_PDBGUP_MBIST);
+ } while (!(val & enable));
+}
+
int hisi_pwrc_setup(void)
{
unsigned int reg, sec_entrypoint;
void hisi_pwrc_set_core_bx_addr(unsigned int core,
unsigned int cluster,
uintptr_t entry_point);
+void hisi_pwrc_enable_debug(unsigned int core,
+ unsigned int cluster);
int hisi_pwrc_setup(void);
#endif /*__ASSEMBLY__*/