usb: phy: mxs: add delay before set phyctrl.clkgate

There is a request from IC engineer that if we doesn't
set phypwd as 0xffffffff, we need to delay about five
32Khz cycles before set phy's pwd register, otherwise,
the wakeup signal may can't wake up controller.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
index c3177a1757ee296aee5e9650b0df299dc8c83a25..8f7cb068d29bab1eb1f9641e41cbe4da30e22489 100644 (file)
--- a/drivers/usb/phy/phy-mxs-usb.c
+++ b/drivers/usb/phy/phy-mxs-usb.c
@@ -371,10 +371,16 @@ static int mxs_phy_suspend(struct usb_phy *x, int suspend)
                 * connect. The low speed connection will have problem at
                 * very rare cases during usb suspend and resume process.
                 */
-               if (low_speed_connection & vbus_is_on)
-                       writel(0xfffbffff, x->io_priv + HW_USBPHY_PWD);
-               else
+               if (low_speed_connection & vbus_is_on) {
+                       /*
+                        * If value to be set as pwd value is not 0xffffffff,
+                        * several 32Khz cycles are needed.
+                        */
+                       mxs_phy_clock_switch_delay();
+                       writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
+               } else {
                        writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
+               }
                writel(BM_USBPHY_CTRL_CLKGATE,
                       x->io_priv + HW_USBPHY_CTRL_SET);
                clk_disable_unprepare(mxs_phy->clk);