powerpc/mpc85xx: Use GOT when loading IVORs post-relocation

Commit 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors")
simplified IVOR initialization a bit too much, failing to use the
post-relocation offset.  This doesn't cause a problem with normal NOR
boot, in which both the pre-relocation and post-relocation addresses
are 64 KiB aligned.  However, if TEXT_BASE is only 4 KiB aligned, such
as for NAND/SD/etc. boot on some targets, as well as the QEMU target,
the post-relocation address will not be the same in the lower 16 bits,
as reserve_uboot() ensures that the relocation address is always 64
KiB aligned even if the pre-relocation address was not.

Use the GOT to get the proper post-relocation offsets.

Fixes: 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors")
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Tested-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 28f04eefabb86e959e7ec113d9f10587446ab2e8..e61d8e0fc2b3e3da10cfec92275ea4fb0da4907f 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1664,41 +1664,46 @@ clear_bss:
         */
        .globl  trap_init
 trap_init:
+       mflr    r11
+       bl      _GLOBAL_OFFSET_TABLE_-4
+       mflr    r12
+
        /* Update IVORs as per relocation */
        mtspr   IVPR,r3
 
-       li      r4,CriticalInput@l
+       lwz     r4,CriticalInput@got(r12)
        mtspr   IVOR0,r4        /* 0: Critical input */
-       li      r4,MachineCheck@l
+       lwz     r4,MachineCheck@got(r12)
        mtspr   IVOR1,r4        /* 1: Machine check */
-       li      r4,DataStorage@l
+       lwz     r4,DataStorage@got(r12)
        mtspr   IVOR2,r4        /* 2: Data storage */
-       li      r4,InstStorage@l
+       lwz     r4,InstStorage@got(r12)
        mtspr   IVOR3,r4        /* 3: Instruction storage */
-       li      r4,ExtInterrupt@l
+       lwz     r4,ExtInterrupt@got(r12)
        mtspr   IVOR4,r4        /* 4: External interrupt */
-       li      r4,Alignment@l
+       lwz     r4,Alignment@got(r12)
        mtspr   IVOR5,r4        /* 5: Alignment */
-       li      r4,ProgramCheck@l
+       lwz     r4,ProgramCheck@got(r12)
        mtspr   IVOR6,r4        /* 6: Program check */
-       li      r4,FPUnavailable@l
+       lwz     r4,FPUnavailable@got(r12)
        mtspr   IVOR7,r4        /* 7: floating point unavailable */
-       li      r4,SystemCall@l
+       lwz     r4,SystemCall@got(r12)
        mtspr   IVOR8,r4        /* 8: System call */
        /* 9: Auxiliary processor unavailable(unsupported) */
-       li      r4,Decrementer@l
+       lwz     r4,Decrementer@got(r12)
        mtspr   IVOR10,r4       /* 10: Decrementer */
-       li      r4,IntervalTimer@l
+       lwz     r4,IntervalTimer@got(r12)
        mtspr   IVOR11,r4       /* 11: Interval timer */
-       li      r4,WatchdogTimer@l
+       lwz     r4,WatchdogTimer@got(r12)
        mtspr   IVOR12,r4       /* 12: Watchdog timer */
-       li      r4,DataTLBError@l
+       lwz     r4,DataTLBError@got(r12)
        mtspr   IVOR13,r4       /* 13: Data TLB error */
-       li      r4,InstructionTLBError@l
+       lwz     r4,InstructionTLBError@got(r12)
        mtspr   IVOR14,r4       /* 14: Instruction TLB error */
-       li      r4,DebugBreakpoint@l
+       lwz     r4,DebugBreakpoint@got(r12)
        mtspr   IVOR15,r4       /* 15: Debug */
 
+       mtlr    r11
        blr
 
 .globl unlock_ram_in_cache