drm/amdgpu: RLC must be disabled after SMU when S3 on navi

SMU requires to interact with RLC when disable all features,
so RLC shouldn't be disabled ahead of SMU.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f9ad98889c7d07e1f09c7b4f925b0cc8949d16f6..80b100caf628d3e7c9e3d7dc4169441c56e67648 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1573,8 +1573,6 @@ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
 
        tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
        WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
-
-       gfx_v10_0_enable_gui_idle_interrupt(adev, false);
 }
 
 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
@@ -3607,7 +3605,7 @@ static int gfx_v10_0_hw_fini(void *handle)
                return 0;
        }
        gfx_v10_0_cp_enable(adev, false);
-       gfx_v10_0_rlc_stop(adev);
+       gfx_v10_0_enable_gui_idle_interrupt(adev, false);
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 9e0b439b41ca3d5ceb16d5985f6701e6e4b6a0dd..30dae7ca19c4a2ca801c734c631c552286d0ab64 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -943,6 +943,10 @@ static int smu_suspend(void *handle)
 
        smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
 
+       if (adev->asic_type >= CHIP_NAVI10 &&
+           adev->gfx.rlc.funcs->stop)
+               adev->gfx.rlc.funcs->stop(adev);
+
        return 0;
 }